STM32L4xx_HAL_Driver - Hal Drivers for L4

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Hal Drivers for L4

Dependents: BSP OneHopeOnePrayer FINAL_AUDIO_RECORD AudioDemo

Fork of STM32L4xx_HAL_Driver by Senior Design: Sound Monitor

Inc/stm32l4xx_ll_adc.h@2:7aef7655b0a8, 2015-11-25 (annotated)

Committer:: EricLew
Date:: Wed Nov 25 17:30:43 2015 +0000
Revision:: 2:7aef7655b0a8
Parent:: 0:80ee8f3b695e

commit;

Who changed what in which revision?

User	Revision	Line number	New contents of line
EricLew	0:80ee8f3b695e	1	/**
EricLew	0:80ee8f3b695e	2	******************************************************************************
EricLew	0:80ee8f3b695e	3	* @file stm32l4xx_ll_adc.h
EricLew	0:80ee8f3b695e	4	* @author MCD Application Team
EricLew	0:80ee8f3b695e	5	* @version V1.1.0
EricLew	0:80ee8f3b695e	6	* @date 16-September-2015
EricLew	0:80ee8f3b695e	7	* @brief Header file of ADC LL module.
EricLew	0:80ee8f3b695e	8	******************************************************************************
EricLew	0:80ee8f3b695e	9	* @attention
EricLew	0:80ee8f3b695e	10	*
EricLew	0:80ee8f3b695e	11	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
EricLew	0:80ee8f3b695e	12	*
EricLew	0:80ee8f3b695e	13	* Redistribution and use in source and binary forms, with or without modification,
EricLew	0:80ee8f3b695e	14	* are permitted provided that the following conditions are met:
EricLew	0:80ee8f3b695e	15	* 1. Redistributions of source code must retain the above copyright notice,
EricLew	0:80ee8f3b695e	16	* this list of conditions and the following disclaimer.
EricLew	0:80ee8f3b695e	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
EricLew	0:80ee8f3b695e	18	* this list of conditions and the following disclaimer in the documentation
EricLew	0:80ee8f3b695e	19	* and/or other materials provided with the distribution.
EricLew	0:80ee8f3b695e	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
EricLew	0:80ee8f3b695e	21	* may be used to endorse or promote products derived from this software
EricLew	0:80ee8f3b695e	22	* without specific prior written permission.
EricLew	0:80ee8f3b695e	23	*
EricLew	0:80ee8f3b695e	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
EricLew	0:80ee8f3b695e	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
EricLew	0:80ee8f3b695e	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
EricLew	0:80ee8f3b695e	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
EricLew	0:80ee8f3b695e	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
EricLew	0:80ee8f3b695e	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
EricLew	0:80ee8f3b695e	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
EricLew	0:80ee8f3b695e	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
EricLew	0:80ee8f3b695e	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
EricLew	0:80ee8f3b695e	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
EricLew	0:80ee8f3b695e	34	*
EricLew	0:80ee8f3b695e	35	******************************************************************************
EricLew	0:80ee8f3b695e	36	*/
EricLew	0:80ee8f3b695e	37
EricLew	0:80ee8f3b695e	38	/* Define to prevent recursive inclusion -------------------------------------*/
EricLew	0:80ee8f3b695e	39	#ifndef __STM32L4xx_LL_ADC_H
EricLew	0:80ee8f3b695e	40	#define __STM32L4xx_LL_ADC_H
EricLew	0:80ee8f3b695e	41
EricLew	0:80ee8f3b695e	42	#ifdef __cplusplus
EricLew	0:80ee8f3b695e	43	extern "C" {
EricLew	0:80ee8f3b695e	44	#endif
EricLew	0:80ee8f3b695e	45
EricLew	0:80ee8f3b695e	46	/* Includes ------------------------------------------------------------------*/
EricLew	0:80ee8f3b695e	47	#include "stm32l4xx.h"
EricLew	0:80ee8f3b695e	48
EricLew	0:80ee8f3b695e	49	/** @addtogroup STM32L4xx_LL_Driver
EricLew	0:80ee8f3b695e	50	* @{
EricLew	0:80ee8f3b695e	51	*/
EricLew	0:80ee8f3b695e	52
EricLew	0:80ee8f3b695e	53	#if defined (ADC1) \|\| defined (ADC2) \|\| defined (ADC3)
EricLew	0:80ee8f3b695e	54
EricLew	0:80ee8f3b695e	55	/** @defgroup ADC_LL ADC
EricLew	0:80ee8f3b695e	56	* @{
EricLew	0:80ee8f3b695e	57	*/
EricLew	0:80ee8f3b695e	58
EricLew	0:80ee8f3b695e	59	/* Private types -------------------------------------------------------------*/
EricLew	0:80ee8f3b695e	60	/* Private variables ---------------------------------------------------------*/
EricLew	0:80ee8f3b695e	61
EricLew	0:80ee8f3b695e	62	/* Private constants ---------------------------------------------------------*/
EricLew	0:80ee8f3b695e	63	/** @defgroup ADC_LL_Private_Constants ADC Private Constants
EricLew	0:80ee8f3b695e	64	* @{
EricLew	0:80ee8f3b695e	65	*/
EricLew	0:80ee8f3b695e	66
EricLew	0:80ee8f3b695e	67	/* Internal mask for ADC group regular sequencer: */
EricLew	0:80ee8f3b695e	68	/* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */
EricLew	0:80ee8f3b695e	69	/* - sequencer register offset */
EricLew	0:80ee8f3b695e	70	/* - sequencer rank bits position into the selected register */
EricLew	0:80ee8f3b695e	71
EricLew	0:80ee8f3b695e	72	/* Internal register offset for ADC group regular sequencer configuration */
EricLew	0:80ee8f3b695e	73	/* (offset placed into a spare area of literal definition) */
EricLew	0:80ee8f3b695e	74	#define ADC_SQR1_REGOFFSET ((uint32_t)0x00000000)
EricLew	0:80ee8f3b695e	75	#define ADC_SQR2_REGOFFSET ((uint32_t)0x00000100)
EricLew	0:80ee8f3b695e	76	#define ADC_SQR3_REGOFFSET ((uint32_t)0x00000200)
EricLew	0:80ee8f3b695e	77	#define ADC_SQR4_REGOFFSET ((uint32_t)0x00000300)
EricLew	0:80ee8f3b695e	78
EricLew	0:80ee8f3b695e	79	#define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET \| ADC_SQR2_REGOFFSET \| ADC_SQR3_REGOFFSET \| ADC_SQR4_REGOFFSET)
EricLew	0:80ee8f3b695e	80	#define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
EricLew	0:80ee8f3b695e	81
EricLew	0:80ee8f3b695e	82	/* Definition of ADC group regular sequencer bits information to be inserted */
EricLew	0:80ee8f3b695e	83	/* into ADC group regular sequencer ranks literals definition. */
EricLew	0:80ee8f3b695e	84	#define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ((uint32_t) 6) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ1) */
EricLew	0:80ee8f3b695e	85	#define ADC_REG_RANK_2_SQRX_BITOFFSET_POS ((uint32_t)12) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ2) */
EricLew	0:80ee8f3b695e	86	#define ADC_REG_RANK_3_SQRX_BITOFFSET_POS ((uint32_t)18) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ3) */
EricLew	0:80ee8f3b695e	87	#define ADC_REG_RANK_4_SQRX_BITOFFSET_POS ((uint32_t)24) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ4) */
EricLew	0:80ee8f3b695e	88	#define ADC_REG_RANK_5_SQRX_BITOFFSET_POS ((uint32_t) 0) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ5) */
EricLew	0:80ee8f3b695e	89	#define ADC_REG_RANK_6_SQRX_BITOFFSET_POS ((uint32_t) 6) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ6) */
EricLew	0:80ee8f3b695e	90	#define ADC_REG_RANK_7_SQRX_BITOFFSET_POS ((uint32_t)12) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ7) */
EricLew	0:80ee8f3b695e	91	#define ADC_REG_RANK_8_SQRX_BITOFFSET_POS ((uint32_t)18) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ8) */
EricLew	0:80ee8f3b695e	92	#define ADC_REG_RANK_9_SQRX_BITOFFSET_POS ((uint32_t)24) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ9) */
EricLew	0:80ee8f3b695e	93	#define ADC_REG_RANK_10_SQRX_BITOFFSET_POS ((uint32_t) 0) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ10) */
EricLew	0:80ee8f3b695e	94	#define ADC_REG_RANK_11_SQRX_BITOFFSET_POS ((uint32_t) 6) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ11) */
EricLew	0:80ee8f3b695e	95	#define ADC_REG_RANK_12_SQRX_BITOFFSET_POS ((uint32_t)12) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ12) */
EricLew	0:80ee8f3b695e	96	#define ADC_REG_RANK_13_SQRX_BITOFFSET_POS ((uint32_t)18) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ13) */
EricLew	0:80ee8f3b695e	97	#define ADC_REG_RANK_14_SQRX_BITOFFSET_POS ((uint32_t)24) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ14) */
EricLew	0:80ee8f3b695e	98	#define ADC_REG_RANK_15_SQRX_BITOFFSET_POS ((uint32_t) 0) /* Value equivalent to POSITION_VAL(ADC_SQR4_SQ15) */
EricLew	0:80ee8f3b695e	99	#define ADC_REG_RANK_16_SQRX_BITOFFSET_POS ((uint32_t) 6) /* Value equivalent to POSITION_VAL(ADC_SQR4_SQ16) */
EricLew	0:80ee8f3b695e	100
EricLew	0:80ee8f3b695e	101
EricLew	0:80ee8f3b695e	102
EricLew	0:80ee8f3b695e	103	/* Internal mask for ADC group injected sequencer: */
EricLew	0:80ee8f3b695e	104	/* To select into literal LL_ADC_INJ_RANK_x the relevant bits for: */
EricLew	0:80ee8f3b695e	105	/* - data register offset */
EricLew	0:80ee8f3b695e	106	/* - sequencer rank bits position into the selected register */
EricLew	0:80ee8f3b695e	107
EricLew	0:80ee8f3b695e	108	/* Internal register offset for ADC group injected data register */
EricLew	0:80ee8f3b695e	109	/* (offset placed into a spare area of literal definition) */
EricLew	0:80ee8f3b695e	110	#define ADC_JDR1_REGOFFSET ((uint32_t)0x00000000)
EricLew	0:80ee8f3b695e	111	#define ADC_JDR2_REGOFFSET ((uint32_t)0x00000100)
EricLew	0:80ee8f3b695e	112	#define ADC_JDR3_REGOFFSET ((uint32_t)0x00000200)
EricLew	0:80ee8f3b695e	113	#define ADC_JDR4_REGOFFSET ((uint32_t)0x00000300)
EricLew	0:80ee8f3b695e	114
EricLew	0:80ee8f3b695e	115	#define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET \| ADC_JDR2_REGOFFSET \| ADC_JDR3_REGOFFSET \| ADC_JDR4_REGOFFSET)
EricLew	0:80ee8f3b695e	116	#define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
EricLew	0:80ee8f3b695e	117
EricLew	0:80ee8f3b695e	118	/* Definition of ADC group injected sequencer bits information to be inserted */
EricLew	0:80ee8f3b695e	119	/* into ADC group injected sequencer ranks literals definition. */
EricLew	0:80ee8f3b695e	120	#define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS ((uint32_t) 8) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ1) */
EricLew	0:80ee8f3b695e	121	#define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS ((uint32_t)14) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ2) */
EricLew	0:80ee8f3b695e	122	#define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS ((uint32_t)20) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ3) */
EricLew	0:80ee8f3b695e	123	#define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS ((uint32_t)26) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ4) */
EricLew	0:80ee8f3b695e	124
EricLew	0:80ee8f3b695e	125
EricLew	0:80ee8f3b695e	126
EricLew	0:80ee8f3b695e	127	/* Internal mask for ADC group regular trigger: */
EricLew	0:80ee8f3b695e	128	/* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */
EricLew	0:80ee8f3b695e	129	/* - regular trigger source */
EricLew	0:80ee8f3b695e	130	/* - regular trigger edge */
EricLew	0:80ee8f3b695e	131	#define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
EricLew	0:80ee8f3b695e	132
EricLew	0:80ee8f3b695e	133	/* Mask containing trigger source masks for each of possible */
EricLew	0:80ee8f3b695e	134	/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
EricLew	0:80ee8f3b695e	135	/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
EricLew	0:80ee8f3b695e	136	#define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SW_START & ADC_CFGR_EXTSEL) << (4 * 0)) \| \
EricLew	0:80ee8f3b695e	137	((ADC_CFGR_EXTSEL) << (4 * 1)) \| \
EricLew	0:80ee8f3b695e	138	((ADC_CFGR_EXTSEL) << (4 * 2)) \| \
EricLew	0:80ee8f3b695e	139	((ADC_CFGR_EXTSEL) << (4 * 3)) )
EricLew	0:80ee8f3b695e	140
EricLew	0:80ee8f3b695e	141	/* Mask containing trigger edge masks for each of possible */
EricLew	0:80ee8f3b695e	142	/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
EricLew	0:80ee8f3b695e	143	/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
EricLew	0:80ee8f3b695e	144	#define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SW_START & ADC_CFGR_EXTEN) << (4 * 0)) \| \
EricLew	0:80ee8f3b695e	145	((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4 * 1)) \| \
EricLew	0:80ee8f3b695e	146	((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4 * 2)) \| \
EricLew	0:80ee8f3b695e	147	((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4 * 3)) )
EricLew	0:80ee8f3b695e	148
EricLew	0:80ee8f3b695e	149	/* Definition of ADC group regular trigger bits information. */
EricLew	0:80ee8f3b695e	150	#define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS ((uint32_t) 6) /* Value equivalent to POSITION_VAL(ADC_CFGR_EXTSEL) */
EricLew	0:80ee8f3b695e	151	#define ADC_REG_TRIG_EXTEN_BITOFFSET_POS ((uint32_t)10) /* Value equivalent to POSITION_VAL(ADC_CFGR_EXTEN) */
EricLew	0:80ee8f3b695e	152
EricLew	0:80ee8f3b695e	153
EricLew	0:80ee8f3b695e	154
EricLew	0:80ee8f3b695e	155	/* Internal mask for ADC group injected trigger: */
EricLew	0:80ee8f3b695e	156	/* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for: */
EricLew	0:80ee8f3b695e	157	/* - injected trigger source */
EricLew	0:80ee8f3b695e	158	/* - injected trigger edge */
EricLew	0:80ee8f3b695e	159	#define ADC_INJ_TRIG_EXT_EDGE_DEFAULT (ADC_JSQR_JEXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
EricLew	0:80ee8f3b695e	160
EricLew	0:80ee8f3b695e	161	/* Mask containing trigger source masks for each of possible */
EricLew	0:80ee8f3b695e	162	/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
EricLew	0:80ee8f3b695e	163	/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
EricLew	0:80ee8f3b695e	164	#define ADC_INJ_TRIG_SOURCE_MASK (((LL_ADC_INJ_TRIG_SW_START & ADC_JSQR_JEXTSEL) << (4 * 0)) \| \
EricLew	0:80ee8f3b695e	165	((ADC_JSQR_JEXTSEL) << (4 * 1)) \| \
EricLew	0:80ee8f3b695e	166	((ADC_JSQR_JEXTSEL) << (4 * 2)) \| \
EricLew	0:80ee8f3b695e	167	((ADC_JSQR_JEXTSEL) << (4 * 3)) )
EricLew	0:80ee8f3b695e	168
EricLew	0:80ee8f3b695e	169	/* Mask containing trigger edge masks for each of possible */
EricLew	0:80ee8f3b695e	170	/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
EricLew	0:80ee8f3b695e	171	/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
EricLew	0:80ee8f3b695e	172	#define ADC_INJ_TRIG_EDGE_MASK (((LL_ADC_INJ_TRIG_SW_START & ADC_JSQR_JEXTEN) << (4 * 0)) \| \
EricLew	0:80ee8f3b695e	173	((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4 * 1)) \| \
EricLew	0:80ee8f3b695e	174	((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4 * 2)) \| \
EricLew	0:80ee8f3b695e	175	((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4 * 3)) )
EricLew	0:80ee8f3b695e	176
EricLew	0:80ee8f3b695e	177	/* Definition of ADC group injected trigger bits information. */
EricLew	0:80ee8f3b695e	178	#define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS ((uint32_t) 2) /* Value equivalent to POSITION_VAL(ADC_JSQR_JEXTSEL) */
EricLew	0:80ee8f3b695e	179	#define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS ((uint32_t) 6) /* Value equivalent to POSITION_VAL(ADC_JSQR_JEXTEN) */
EricLew	0:80ee8f3b695e	180
EricLew	0:80ee8f3b695e	181
EricLew	0:80ee8f3b695e	182
EricLew	0:80ee8f3b695e	183	/* Internal register offset for ADC group regular sequencer configuration */
EricLew	0:80ee8f3b695e	184	/* (offset placed into a spare area of literal definition) */
EricLew	0:80ee8f3b695e	185	#define ADC_SQR1_REGOFFSET ((uint32_t)0x00000000)
EricLew	0:80ee8f3b695e	186	#define ADC_SQR2_REGOFFSET ((uint32_t)0x00000100)
EricLew	0:80ee8f3b695e	187	#define ADC_SQR3_REGOFFSET ((uint32_t)0x00000200)
EricLew	0:80ee8f3b695e	188	#define ADC_SQR4_REGOFFSET ((uint32_t)0x00000300)
EricLew	0:80ee8f3b695e	189
EricLew	0:80ee8f3b695e	190	#define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET \| ADC_SQR2_REGOFFSET \| ADC_SQR3_REGOFFSET \| ADC_SQR4_REGOFFSET)
EricLew	0:80ee8f3b695e	191	#define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
EricLew	0:80ee8f3b695e	192
EricLew	0:80ee8f3b695e	193
EricLew	0:80ee8f3b695e	194
EricLew	0:80ee8f3b695e	195	/* Internal mask for ADC channel: */
EricLew	0:80ee8f3b695e	196	/* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */
EricLew	0:80ee8f3b695e	197	/* - channel identifier defined by number */
EricLew	0:80ee8f3b695e	198	/* - channel identifier defined by bitfield */
EricLew	0:80ee8f3b695e	199	/* - channel differentiation between external channels (connected to */
EricLew	0:80ee8f3b695e	200	/* GPIO pins) and internal channels (connected to internal paths) */
EricLew	0:80ee8f3b695e	201	/* - channel sampling time defined by SMPRx register offset */
EricLew	0:80ee8f3b695e	202	/* and SMPx bits positions into SMPRx register */
EricLew	0:80ee8f3b695e	203	#define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR_AWD1CH)
EricLew	0:80ee8f3b695e	204	#define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_AWD2CR_AWD2CH)
EricLew	0:80ee8f3b695e	205	#define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK \| ADC_CHANNEL_ID_BITFIELD_MASK \| ADC_CHANNEL_ID_INTERNAL_CH_MASK)
EricLew	0:80ee8f3b695e	206	/* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
EricLew	0:80ee8f3b695e	207	#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (ADC_SQR2_SQ5) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */
EricLew	0:80ee8f3b695e	208
EricLew	0:80ee8f3b695e	209	/* Channel differentiation between external and internal channels */
EricLew	0:80ee8f3b695e	210	#define ADC_CHANNEL_ID_INTERNAL_CH ((uint32_t)0x80000000) /* Marker of internal channel */
EricLew	0:80ee8f3b695e	211	#define ADC_CHANNEL_ID_INTERNAL_CH_2 ((uint32_t)0x02000000) /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */
EricLew	0:80ee8f3b695e	212	#define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH \| ADC_CHANNEL_ID_INTERNAL_CH_2)
EricLew	0:80ee8f3b695e	213
EricLew	0:80ee8f3b695e	214	/* Internal register offset for ADC channel sampling time configuration */
EricLew	0:80ee8f3b695e	215	/* (offset placed into a spare area of literal definition) */
EricLew	0:80ee8f3b695e	216	#define ADC_SMPR1_REGOFFSET ((uint32_t)0x00000000)
EricLew	0:80ee8f3b695e	217	#define ADC_SMPR2_REGOFFSET ((uint32_t)0x01000000)
EricLew	0:80ee8f3b695e	218	#define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET \| ADC_SMPR2_REGOFFSET)
EricLew	0:80ee8f3b695e	219
EricLew	0:80ee8f3b695e	220	#define ADC_CHANNEL_SMPx_BITOFFSET_MASK ((uint32_t)0x00F80000)
EricLew	0:80ee8f3b695e	221	#define ADC_CHANNEL_SMPx_BITOFFSET_POS ((uint32_t)19) /* Value equivalent to POSITION_VAL(ADC_CHANNEL_SMPx_BITOFFSET_MASK) */
EricLew	0:80ee8f3b695e	222
EricLew	0:80ee8f3b695e	223	/* Definition of channels ID number information to be inserted into */
EricLew	0:80ee8f3b695e	224	/* channels literals definition. */
EricLew	0:80ee8f3b695e	225	#define ADC_CHANNEL_0_NUMBER ((uint32_t)0x00000000)
EricLew	0:80ee8f3b695e	226	#define ADC_CHANNEL_1_NUMBER ( ADC_CFGR_AWD1CH_0)
EricLew	0:80ee8f3b695e	227	#define ADC_CHANNEL_2_NUMBER ( ADC_CFGR_AWD1CH_1 )
EricLew	0:80ee8f3b695e	228	#define ADC_CHANNEL_3_NUMBER ( ADC_CFGR_AWD1CH_1 \| ADC_CFGR_AWD1CH_0)
EricLew	0:80ee8f3b695e	229	#define ADC_CHANNEL_4_NUMBER ( ADC_CFGR_AWD1CH_2 )
EricLew	0:80ee8f3b695e	230	#define ADC_CHANNEL_5_NUMBER ( ADC_CFGR_AWD1CH_2 \| ADC_CFGR_AWD1CH_0)
EricLew	0:80ee8f3b695e	231	#define ADC_CHANNEL_6_NUMBER ( ADC_CFGR_AWD1CH_2 \| ADC_CFGR_AWD1CH_1 )
EricLew	0:80ee8f3b695e	232	#define ADC_CHANNEL_7_NUMBER ( ADC_CFGR_AWD1CH_2 \| ADC_CFGR_AWD1CH_1 \| ADC_CFGR_AWD1CH_0)
EricLew	0:80ee8f3b695e	233	#define ADC_CHANNEL_8_NUMBER ( ADC_CFGR_AWD1CH_3 )
EricLew	0:80ee8f3b695e	234	#define ADC_CHANNEL_9_NUMBER ( ADC_CFGR_AWD1CH_3 \| ADC_CFGR_AWD1CH_0)
EricLew	0:80ee8f3b695e	235	#define ADC_CHANNEL_10_NUMBER ( ADC_CFGR_AWD1CH_3 \| ADC_CFGR_AWD1CH_1 )
EricLew	0:80ee8f3b695e	236	#define ADC_CHANNEL_11_NUMBER ( ADC_CFGR_AWD1CH_3 \| ADC_CFGR_AWD1CH_1 \| ADC_CFGR_AWD1CH_0)
EricLew	0:80ee8f3b695e	237	#define ADC_CHANNEL_12_NUMBER ( ADC_CFGR_AWD1CH_3 \| ADC_CFGR_AWD1CH_2 )
EricLew	0:80ee8f3b695e	238	#define ADC_CHANNEL_13_NUMBER ( ADC_CFGR_AWD1CH_3 \| ADC_CFGR_AWD1CH_2 \| ADC_CFGR_AWD1CH_0)
EricLew	0:80ee8f3b695e	239	#define ADC_CHANNEL_14_NUMBER ( ADC_CFGR_AWD1CH_3 \| ADC_CFGR_AWD1CH_2 \| ADC_CFGR_AWD1CH_1 )
EricLew	0:80ee8f3b695e	240	#define ADC_CHANNEL_15_NUMBER ( ADC_CFGR_AWD1CH_3 \| ADC_CFGR_AWD1CH_2 \| ADC_CFGR_AWD1CH_1 \| ADC_CFGR_AWD1CH_0)
EricLew	0:80ee8f3b695e	241	#define ADC_CHANNEL_16_NUMBER (ADC_CFGR_AWD1CH_4 )
EricLew	0:80ee8f3b695e	242	#define ADC_CHANNEL_17_NUMBER (ADC_CFGR_AWD1CH_4 \| ADC_CFGR_AWD1CH_0)
EricLew	0:80ee8f3b695e	243	#define ADC_CHANNEL_18_NUMBER (ADC_CFGR_AWD1CH_4 \| ADC_CFGR_AWD1CH_1 )
EricLew	0:80ee8f3b695e	244
EricLew	0:80ee8f3b695e	245	/* Definition of channels ID bitfield information to be inserted into */
EricLew	0:80ee8f3b695e	246	/* channels literals definition. */
EricLew	0:80ee8f3b695e	247	#define ADC_CHANNEL_0_BITFIELD (ADC_AWD2CR_AWD2CH_0)
EricLew	0:80ee8f3b695e	248	#define ADC_CHANNEL_1_BITFIELD (ADC_AWD2CR_AWD2CH_1)
EricLew	0:80ee8f3b695e	249	#define ADC_CHANNEL_2_BITFIELD (ADC_AWD2CR_AWD2CH_2)
EricLew	0:80ee8f3b695e	250	#define ADC_CHANNEL_3_BITFIELD (ADC_AWD2CR_AWD2CH_3)
EricLew	0:80ee8f3b695e	251	#define ADC_CHANNEL_4_BITFIELD (ADC_AWD2CR_AWD2CH_4)
EricLew	0:80ee8f3b695e	252	#define ADC_CHANNEL_5_BITFIELD (ADC_AWD2CR_AWD2CH_5)
EricLew	0:80ee8f3b695e	253	#define ADC_CHANNEL_6_BITFIELD (ADC_AWD2CR_AWD2CH_6)
EricLew	0:80ee8f3b695e	254	#define ADC_CHANNEL_7_BITFIELD (ADC_AWD2CR_AWD2CH_7)
EricLew	0:80ee8f3b695e	255	#define ADC_CHANNEL_8_BITFIELD (ADC_AWD2CR_AWD2CH_8)
EricLew	0:80ee8f3b695e	256	#define ADC_CHANNEL_9_BITFIELD (ADC_AWD2CR_AWD2CH_9)
EricLew	0:80ee8f3b695e	257	#define ADC_CHANNEL_10_BITFIELD (ADC_AWD2CR_AWD2CH_10)
EricLew	0:80ee8f3b695e	258	#define ADC_CHANNEL_11_BITFIELD (ADC_AWD2CR_AWD2CH_11)
EricLew	0:80ee8f3b695e	259	#define ADC_CHANNEL_12_BITFIELD (ADC_AWD2CR_AWD2CH_12)
EricLew	0:80ee8f3b695e	260	#define ADC_CHANNEL_13_BITFIELD (ADC_AWD2CR_AWD2CH_13)
EricLew	0:80ee8f3b695e	261	#define ADC_CHANNEL_14_BITFIELD (ADC_AWD2CR_AWD2CH_14)
EricLew	0:80ee8f3b695e	262	#define ADC_CHANNEL_15_BITFIELD (ADC_AWD2CR_AWD2CH_15)
EricLew	0:80ee8f3b695e	263	#define ADC_CHANNEL_16_BITFIELD (ADC_AWD2CR_AWD2CH_16)
EricLew	0:80ee8f3b695e	264	#define ADC_CHANNEL_17_BITFIELD (ADC_AWD2CR_AWD2CH_17)
EricLew	0:80ee8f3b695e	265	#define ADC_CHANNEL_18_BITFIELD (ADC_AWD2CR_AWD2CH_18)
EricLew	0:80ee8f3b695e	266
EricLew	0:80ee8f3b695e	267	/* Definition of channels sampling time information to be inserted into */
EricLew	0:80ee8f3b695e	268	/* channels literals definition. */
EricLew	0:80ee8f3b695e	269	#define ADC_CHANNEL_0_SMP (ADC_SMPR1_REGOFFSET \| (((uint32_t) 0) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP0) */
EricLew	0:80ee8f3b695e	270	#define ADC_CHANNEL_1_SMP (ADC_SMPR1_REGOFFSET \| (((uint32_t) 3) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP1) */
EricLew	0:80ee8f3b695e	271	#define ADC_CHANNEL_2_SMP (ADC_SMPR1_REGOFFSET \| (((uint32_t) 6) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP2) */
EricLew	0:80ee8f3b695e	272	#define ADC_CHANNEL_3_SMP (ADC_SMPR1_REGOFFSET \| (((uint32_t) 9) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP3) */
EricLew	0:80ee8f3b695e	273	#define ADC_CHANNEL_4_SMP (ADC_SMPR1_REGOFFSET \| (((uint32_t)12) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP4) */
EricLew	0:80ee8f3b695e	274	#define ADC_CHANNEL_5_SMP (ADC_SMPR1_REGOFFSET \| (((uint32_t)15) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP5) */
EricLew	0:80ee8f3b695e	275	#define ADC_CHANNEL_6_SMP (ADC_SMPR1_REGOFFSET \| (((uint32_t)18) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP6) */
EricLew	0:80ee8f3b695e	276	#define ADC_CHANNEL_7_SMP (ADC_SMPR1_REGOFFSET \| (((uint32_t)21) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP7) */
EricLew	0:80ee8f3b695e	277	#define ADC_CHANNEL_8_SMP (ADC_SMPR1_REGOFFSET \| (((uint32_t)24) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP8) */
EricLew	0:80ee8f3b695e	278	#define ADC_CHANNEL_9_SMP (ADC_SMPR1_REGOFFSET \| (((uint32_t)27) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP9) */
EricLew	0:80ee8f3b695e	279	#define ADC_CHANNEL_10_SMP (ADC_SMPR2_REGOFFSET \| (((uint32_t) 0) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP10) */
EricLew	0:80ee8f3b695e	280	#define ADC_CHANNEL_11_SMP (ADC_SMPR2_REGOFFSET \| (((uint32_t) 3) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP11) */
EricLew	0:80ee8f3b695e	281	#define ADC_CHANNEL_12_SMP (ADC_SMPR2_REGOFFSET \| (((uint32_t) 6) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP12) */
EricLew	0:80ee8f3b695e	282	#define ADC_CHANNEL_13_SMP (ADC_SMPR2_REGOFFSET \| (((uint32_t) 9) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP13) */
EricLew	0:80ee8f3b695e	283	#define ADC_CHANNEL_14_SMP (ADC_SMPR2_REGOFFSET \| (((uint32_t)12) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP14) */
EricLew	0:80ee8f3b695e	284	#define ADC_CHANNEL_15_SMP (ADC_SMPR2_REGOFFSET \| (((uint32_t)15) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP15) */
EricLew	0:80ee8f3b695e	285	#define ADC_CHANNEL_16_SMP (ADC_SMPR2_REGOFFSET \| (((uint32_t)18) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP16) */
EricLew	0:80ee8f3b695e	286	#define ADC_CHANNEL_17_SMP (ADC_SMPR2_REGOFFSET \| (((uint32_t)21) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP17) */
EricLew	0:80ee8f3b695e	287	#define ADC_CHANNEL_18_SMP (ADC_SMPR2_REGOFFSET \| (((uint32_t)24) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP18) */
EricLew	0:80ee8f3b695e	288
EricLew	0:80ee8f3b695e	289
EricLew	0:80ee8f3b695e	290	/* Internal mask for ADC mode single or differential ended: */
EricLew	0:80ee8f3b695e	291	/* To select into literals LL_ADC_SINGLE_ENDED or LL_ADC_SINGLE_DIFFERENTIAL */
EricLew	0:80ee8f3b695e	292	/* the relevant bits for: */
EricLew	0:80ee8f3b695e	293	/* (concatenation of multiple bits used in different registers) */
EricLew	0:80ee8f3b695e	294	/* - ADC calibration: calibration start, calibration factor get or set */
EricLew	0:80ee8f3b695e	295	/* - ADC channels: set each ADC channel ending mode */
EricLew	0:80ee8f3b695e	296	#define ADC_SINGLEDIFF_CALIB_START_MASK (ADC_CR_ADCALDIF)
EricLew	0:80ee8f3b695e	297	#define ADC_SINGLEDIFF_CALIB_FACTOR_MASK (ADC_CALFACT_CALFACT_D \| ADC_CALFACT_CALFACT_S)
EricLew	0:80ee8f3b695e	298	#define ADC_SINGLEDIFF_CHANNEL_MASK (ADC_CHANNEL_ID_BITFIELD_MASK) /* Equivalent to ADC_DIFSEL_DIFSEL */
EricLew	0:80ee8f3b695e	299	#define ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK (ADC_CALFACT_CALFACT_S_5) /* Bit chosen to perform of shift when single mode is selected, shift value out of channels bits range. */
EricLew	0:80ee8f3b695e	300
EricLew	0:80ee8f3b695e	301
EricLew	0:80ee8f3b695e	302	/* Internal mask for ADC analog watchdog: */
EricLew	0:80ee8f3b695e	303	/* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */
EricLew	0:80ee8f3b695e	304	/* (concatenation of multiple bits used in different analog watchdogs, */
EricLew	0:80ee8f3b695e	305	/* (feature of several watchdogs not available on all STM32 families)). */
EricLew	0:80ee8f3b695e	306	/* - analog watchdog 1: monitored channel defined by number, */
EricLew	0:80ee8f3b695e	307	/* selection of ADC group (ADC groups regular and-or injected). */
EricLew	0:80ee8f3b695e	308	/* - analog watchdog 2 and 3: monitored channel defined by bitfield, no */
EricLew	0:80ee8f3b695e	309	/* selection on groups. */
EricLew	0:80ee8f3b695e	310
EricLew	0:80ee8f3b695e	311	/* Internal register offset for ADC analog watchdog channel configuration */
EricLew	0:80ee8f3b695e	312	#define ADC_AWD_CR1_REGOFFSET ((uint32_t)0x00000000)
EricLew	0:80ee8f3b695e	313	#define ADC_AWD_CR2_REGOFFSET ((uint32_t)0x00080000)
EricLew	0:80ee8f3b695e	314	#define ADC_AWD_CR3_REGOFFSET ((uint32_t)0x00100000)
EricLew	0:80ee8f3b695e	315
EricLew	0:80ee8f3b695e	316	/* Register offset gap between AWD1 and AWD2-AWD3 configuration registers */
EricLew	0:80ee8f3b695e	317	/* (Set separately as ADC_AWD_CRX_REGOFFSET to spare 32 bits space */
EricLew	0:80ee8f3b695e	318	#define ADC_AWD_CR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0)
EricLew	0:80ee8f3b695e	319	#define ADC_AWD_CR12_REGOFFSETGAP_VAL ((uint32_t)0x00000024)
EricLew	0:80ee8f3b695e	320
EricLew	0:80ee8f3b695e	321	#define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET \| ADC_AWD_CR2_REGOFFSET \| ADC_AWD_CR3_REGOFFSET)
EricLew	0:80ee8f3b695e	322
EricLew	0:80ee8f3b695e	323	#define ADC_AWD_CR1_CHANNEL_MASK (ADC_CFGR_AWD1CH \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL)
EricLew	0:80ee8f3b695e	324	#define ADC_AWD_CR23_CHANNEL_MASK (ADC_AWD2CR_AWD2CH)
EricLew	0:80ee8f3b695e	325	#define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK \| ADC_AWD_CR23_CHANNEL_MASK)
EricLew	0:80ee8f3b695e	326
EricLew	0:80ee8f3b695e	327	/* Internal register offset for ADC analog watchdog threshold configuration */
EricLew	0:80ee8f3b695e	328	#define ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET)
EricLew	0:80ee8f3b695e	329	#define ADC_AWD_TR2_REGOFFSET (ADC_AWD_CR2_REGOFFSET)
EricLew	0:80ee8f3b695e	330	#define ADC_AWD_TR3_REGOFFSET (ADC_AWD_CR3_REGOFFSET)
EricLew	0:80ee8f3b695e	331	#define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET \| ADC_AWD_TR2_REGOFFSET \| ADC_AWD_TR3_REGOFFSET)
EricLew	0:80ee8f3b695e	332
EricLew	0:80ee8f3b695e	333
EricLew	0:80ee8f3b695e	334	/* Internal mask for ADC offset: */
EricLew	0:80ee8f3b695e	335	/* Internal register offset for ADC offset number configuration */
EricLew	0:80ee8f3b695e	336	#define ADC_OFR1_REGOFFSET ((uint32_t)0x00000000)
EricLew	0:80ee8f3b695e	337	#define ADC_OFR2_REGOFFSET ((uint32_t)0x00000001)
EricLew	0:80ee8f3b695e	338	#define ADC_OFR3_REGOFFSET ((uint32_t)0x00000002)
EricLew	0:80ee8f3b695e	339	#define ADC_OFR4_REGOFFSET ((uint32_t)0x00000003)
EricLew	0:80ee8f3b695e	340	#define ADC_OFRx_REGOFFSET_MASK (ADC_OFR1_REGOFFSET \| ADC_OFR2_REGOFFSET \| ADC_OFR3_REGOFFSET \| ADC_OFR4_REGOFFSET)
EricLew	0:80ee8f3b695e	341
EricLew	0:80ee8f3b695e	342
EricLew	0:80ee8f3b695e	343	/* ADC registers bits positions */
EricLew	0:80ee8f3b695e	344	#define ADC_CFGR_RES_BITOFFSET_POS ((uint32_t) 3) /* Value equivalent to POSITION_VAL(ADC_CFGR_RES) */
EricLew	0:80ee8f3b695e	345	#define ADC_TR1_HT1_BITOFFSET_POS ((uint32_t)16) /* Value equivalent to POSITION_VAL(ADC_TR1_HT1) */
EricLew	0:80ee8f3b695e	346
EricLew	0:80ee8f3b695e	347
EricLew	0:80ee8f3b695e	348	/* ADC registers bits groups */
EricLew	0:80ee8f3b695e	349	#define ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL \| ADC_CR_JADSTP \| ADC_CR_ADSTP \| ADC_CR_JADSTART \| ADC_CR_ADSTART \| ADC_CR_ADDIS \| ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */
EricLew	0:80ee8f3b695e	350
EricLew	0:80ee8f3b695e	351
EricLew	0:80ee8f3b695e	352	/* ADC internal channels related definitions */
EricLew	0:80ee8f3b695e	353	/* Internal voltage reference VrefInt */
EricLew	0:80ee8f3b695e	354	#define VREFINT_CAL_ADDR ((uint16_t) ((uint32_t)0x1FFF75AA)) / Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
EricLew	0:80ee8f3b695e	355	#define VREFINT_CAL_VREF ((uint32_t) 3000) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
EricLew	0:80ee8f3b695e	356	/* Temperature sensor */
EricLew	0:80ee8f3b695e	357	#define TEMPSENSOR_CAL1_ADDR ((uint16_t) ((uint32_t)0x1FFF75A8)) / Internal temperature sensor, address of parameter TS_CAL1: On STM32L4, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
EricLew	0:80ee8f3b695e	358	#define TEMPSENSOR_CAL2_ADDR ((uint16_t) ((uint32_t)0x1FFF75CA)) / Internal temperature sensor, address of parameter TS_CAL2: On STM32L4, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
EricLew	0:80ee8f3b695e	359	#define TEMPSENSOR_CAL1_TEMP (( int32_t) 30) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
EricLew	0:80ee8f3b695e	360	#define TEMPSENSOR_CAL2_TEMP (( int32_t) 110) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
EricLew	0:80ee8f3b695e	361	#define TEMPSENSOR_CAL_VREFANALOG ((uint32_t) 3000) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */
EricLew	0:80ee8f3b695e	362
EricLew	0:80ee8f3b695e	363
EricLew	0:80ee8f3b695e	364	/**
EricLew	0:80ee8f3b695e	365	* @}
EricLew	0:80ee8f3b695e	366	*/
EricLew	0:80ee8f3b695e	367
EricLew	0:80ee8f3b695e	368
EricLew	0:80ee8f3b695e	369	/* Private macros ------------------------------------------------------------*/
EricLew	0:80ee8f3b695e	370	/** @defgroup ADC_LL_Private_Macros ADC Private Macros
EricLew	0:80ee8f3b695e	371	* @{
EricLew	0:80ee8f3b695e	372	*/
EricLew	0:80ee8f3b695e	373
EricLew	0:80ee8f3b695e	374	/**
EricLew	0:80ee8f3b695e	375	* @brief Driver macro reserved for internal use: isolate bits with the
EricLew	0:80ee8f3b695e	376	* selected mask and shift them to the register LSB
EricLew	0:80ee8f3b695e	377	* (shift mask on register position bit 0).
EricLew	0:80ee8f3b695e	378	* @param __BITS__ Bits in register 32 bits
EricLew	0:80ee8f3b695e	379	* @param __MASK__ Mask in register 32 bits
EricLew	0:80ee8f3b695e	380	* @retval Bits in register 32 bits
EricLew	0:80ee8f3b695e	381	*/
EricLew	0:80ee8f3b695e	382	#define __ADC_MASK_SHIFT(__BITS__, __MASK__) \
EricLew	0:80ee8f3b695e	383	(((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
EricLew	0:80ee8f3b695e	384
EricLew	0:80ee8f3b695e	385	/**
EricLew	0:80ee8f3b695e	386	* @brief Driver macro reserved for internal use: set a pointer to
EricLew	0:80ee8f3b695e	387	* a register from a register basis from which an offset
EricLew	0:80ee8f3b695e	388	* is applied.
EricLew	0:80ee8f3b695e	389	* @param __REG__ Register basis from which the offset is applied.
EricLew	0:80ee8f3b695e	390	* @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
EricLew	0:80ee8f3b695e	391	* @retval Pointer to register address
EricLew	0:80ee8f3b695e	392	*/
EricLew	0:80ee8f3b695e	393	#define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
EricLew	0:80ee8f3b695e	394	((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2))))
EricLew	0:80ee8f3b695e	395
EricLew	0:80ee8f3b695e	396	/**
EricLew	0:80ee8f3b695e	397	* @}
EricLew	0:80ee8f3b695e	398	*/
EricLew	0:80ee8f3b695e	399
EricLew	0:80ee8f3b695e	400
EricLew	0:80ee8f3b695e	401	/* Exported types ------------------------------------------------------------*/
EricLew	0:80ee8f3b695e	402	/* Exported constants --------------------------------------------------------*/
EricLew	0:80ee8f3b695e	403	/** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
EricLew	0:80ee8f3b695e	404	* @{
EricLew	0:80ee8f3b695e	405	*/
EricLew	0:80ee8f3b695e	406
EricLew	0:80ee8f3b695e	407	/** @defgroup ADC_LL_EC_GET_FLAG ADC flags
EricLew	0:80ee8f3b695e	408	* @brief Flags defines which can be used with LL_ADC_ReadReg function
EricLew	0:80ee8f3b695e	409	* @{
EricLew	0:80ee8f3b695e	410	*/
EricLew	0:80ee8f3b695e	411	#define LL_ADC_ISR_ADRDY ADC_ISR_ADRDY /!< ADC flag ADC instance ready /
EricLew	0:80ee8f3b695e	412	#define LL_ADC_ISR_EOC ADC_ISR_EOC /!< ADC flag ADC group regular end of unitary conversion /
EricLew	0:80ee8f3b695e	413	#define LL_ADC_ISR_EOS ADC_ISR_EOS /!< ADC flag ADC group regular end of sequence conversions /
EricLew	0:80ee8f3b695e	414	#define LL_ADC_ISR_OVR ADC_ISR_OVR /!< ADC flag ADC group regular overrun /
EricLew	0:80ee8f3b695e	415	#define LL_ADC_ISR_EOSMP ADC_ISR_EOSMP /!< ADC flag ADC group regular end of sampling phase /
EricLew	0:80ee8f3b695e	416	#define LL_ADC_ISR_JEOC ADC_ISR_JEOC /!< ADC flag ADC group injected end of unitary conversion /
EricLew	0:80ee8f3b695e	417	#define LL_ADC_ISR_JEOS ADC_ISR_JEOS /!< ADC flag ADC group injected end of sequence conversions /
EricLew	0:80ee8f3b695e	418	#define LL_ADC_ISR_JQOVF ADC_ISR_JQOVF /!< ADC flag ADC group injected contexts queue overflow /
EricLew	0:80ee8f3b695e	419	#define LL_ADC_ISR_AWD1 ADC_ISR_AWD1 /!< ADC flag ADC analog watchdog 1 /
EricLew	0:80ee8f3b695e	420	#define LL_ADC_ISR_AWD2 ADC_ISR_AWD2 /!< ADC flag ADC analog watchdog 2 /
EricLew	0:80ee8f3b695e	421	#define LL_ADC_ISR_AWD3 ADC_ISR_AWD3 /!< ADC flag ADC analog watchdog 3 /
EricLew	0:80ee8f3b695e	422	#define LL_ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST /!< ADC flag ADC instance ready of the ADC master /
EricLew	0:80ee8f3b695e	423	#define LL_ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV /!< ADC flag ADC instance ready of the ADC slave /
EricLew	0:80ee8f3b695e	424	#if defined(ADC2)
EricLew	0:80ee8f3b695e	425	#define LL_ADC_CSR_EOC_MST ADC_CSR_EOC_MST /!< ADC flag multimode ADC group regular end of unitary conversion of the ADC master /
EricLew	0:80ee8f3b695e	426	#define LL_ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV /!< ADC flag multimode ADC group regular end of unitary conversion of the ADC slave /
EricLew	0:80ee8f3b695e	427	#define LL_ADC_CSR_EOS_MST ADC_CSR_EOS_MST /!< ADC flag multimode ADC group regular end of sequence conversions of the ADC master /
EricLew	0:80ee8f3b695e	428	#define LL_ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV /!< ADC flag multimode ADC group regular end of sequence conversions of the ADC slave /
EricLew	0:80ee8f3b695e	429	#define LL_ADC_CSR_OVR_MST ADC_CSR_OVR_MST /!< ADC flag multimode ADC group regular overrun of the ADC master /
EricLew	0:80ee8f3b695e	430	#define LL_ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV /!< ADC flag multimode ADC group regular overrun of the ADC slave /
EricLew	0:80ee8f3b695e	431	#define LL_ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST /!< ADC flag multimode ADC group regular end of sampling phase of the ADC master /
EricLew	0:80ee8f3b695e	432	#define LL_ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV /!< ADC flag multimode ADC group regular end of sampling phase of the ADC slave /
EricLew	0:80ee8f3b695e	433	#define LL_ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST /!< ADC flag multimode ADC group injected end of unitary conversion of the ADC master /
EricLew	0:80ee8f3b695e	434	#define LL_ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV /!< ADC flag multimode ADC group injected end of unitary conversion of the ADC slave /
EricLew	0:80ee8f3b695e	435	#define LL_ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST /!< ADC flag multimode ADC group injected end of sequence conversions of the ADC master /
EricLew	0:80ee8f3b695e	436	#define LL_ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV /!< ADC flag multimode ADC group injected end of sequence conversions of the ADC slave /
EricLew	0:80ee8f3b695e	437	#define LL_ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST /!< ADC flag multimode ADC group injected contexts queue overflow of the ADC master /
EricLew	0:80ee8f3b695e	438	#define LL_ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV /!< ADC flag multimode ADC group injected contexts queue overflow of the ADC slave /
EricLew	0:80ee8f3b695e	439	#define LL_ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST /!< ADC flag multimode ADC analog watchdog 1 of the ADC master /
EricLew	0:80ee8f3b695e	440	#define LL_ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV /!< ADC flag multimode ADC analog watchdog 1 of the ADC slave /
EricLew	0:80ee8f3b695e	441	#define LL_ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST /!< ADC flag multimode ADC analog watchdog 2 of the ADC master /
EricLew	0:80ee8f3b695e	442	#define LL_ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV /!< ADC flag multimode ADC analog watchdog 2 of the ADC slave /
EricLew	0:80ee8f3b695e	443	#define LL_ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST /!< ADC flag multimode ADC analog watchdog 3 of the ADC master /
EricLew	0:80ee8f3b695e	444	#define LL_ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV /!< ADC flag multimode ADC analog watchdog 3 of the ADC slave /
EricLew	0:80ee8f3b695e	445	#endif
EricLew	0:80ee8f3b695e	446	/**
EricLew	0:80ee8f3b695e	447	* @}
EricLew	0:80ee8f3b695e	448	*/
EricLew	0:80ee8f3b695e	449
EricLew	0:80ee8f3b695e	450	/** @defgroup ADC_LL_EC_IT ADC interruptions
EricLew	0:80ee8f3b695e	451	* @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions
EricLew	0:80ee8f3b695e	452	* @{
EricLew	0:80ee8f3b695e	453	*/
EricLew	0:80ee8f3b695e	454	#define LL_ADC_IER_ADRDY ADC_IER_ADRDY /!< ADC interruption ADC instance ready /
EricLew	0:80ee8f3b695e	455	#define LL_ADC_IER_EOC ADC_IER_EOC /!< ADC interruption ADC group regular end of unitary conversion /
EricLew	0:80ee8f3b695e	456	#define LL_ADC_IER_EOS ADC_IER_EOS /!< ADC interruption ADC group regular end of sequence conversions /
EricLew	0:80ee8f3b695e	457	#define LL_ADC_IER_OVR ADC_IER_OVR /!< ADC interruption ADC group regular overrun /
EricLew	0:80ee8f3b695e	458	#define LL_ADC_IER_EOSMP ADC_IER_EOSMP /!< ADC interruption ADC group regular end of sampling phase /
EricLew	0:80ee8f3b695e	459	#define LL_ADC_IER_JEOC ADC_IER_JEOC /!< ADC interruption ADC group injected end of unitary conversion /
EricLew	0:80ee8f3b695e	460	#define LL_ADC_IER_JEOS ADC_IER_JEOS /!< ADC interruption ADC group injected end of sequence conversions /
EricLew	0:80ee8f3b695e	461	#define LL_ADC_IER_JQOVF ADC_IER_JQOVF /!< ADC interruption ADC group injected contexts queue overflow /
EricLew	0:80ee8f3b695e	462	#define LL_ADC_IER_AWD1 ADC_IER_AWD1 /!< ADC interruption ADC analog watchdog 1 /
EricLew	0:80ee8f3b695e	463	#define LL_ADC_IER_AWD2 ADC_IER_AWD2 /!< ADC interruption ADC analog watchdog 2 /
EricLew	0:80ee8f3b695e	464	#define LL_ADC_IER_AWD3 ADC_IER_AWD3 /!< ADC interruption ADC analog watchdog 3 /
EricLew	0:80ee8f3b695e	465	/**
EricLew	0:80ee8f3b695e	466	* @}
EricLew	0:80ee8f3b695e	467	*/
EricLew	0:80ee8f3b695e	468
EricLew	0:80ee8f3b695e	469	/** @defgroup ADC_LL_EC_REGISTERS ADC instance - Registers compliant with specific purpose
EricLew	0:80ee8f3b695e	470	* @{
EricLew	0:80ee8f3b695e	471	*/
EricLew	0:80ee8f3b695e	472	/* List of ADC registers intended to be used (most commonly) with */
EricLew	0:80ee8f3b695e	473	/* DMA transfer. */
EricLew	0:80ee8f3b695e	474	/* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */
EricLew	0:80ee8f3b695e	475	#define LL_ADC_DMA_REG_REGULAR_DATA ((uint32_t)0x00000000) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
EricLew	0:80ee8f3b695e	476	#if defined(ADC2)
EricLew	0:80ee8f3b695e	477	#define LL_ADC_DMA_REG_REGULAR_DATA_MULTI ((uint32_t)0x00000001) /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */
EricLew	0:80ee8f3b695e	478	#endif
EricLew	0:80ee8f3b695e	479	/**
EricLew	0:80ee8f3b695e	480	* @}
EricLew	0:80ee8f3b695e	481	*/
EricLew	0:80ee8f3b695e	482
EricLew	0:80ee8f3b695e	483	/** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source
EricLew	0:80ee8f3b695e	484	* @{
EricLew	0:80ee8f3b695e	485	*/
EricLew	0:80ee8f3b695e	486	#define LL_ADC_CLOCK_SYNC_PCLK_DIV1 (ADC_CCR_CKMODE_0) /!< ADC synchronous clock derived from AHB clock not divided /
EricLew	0:80ee8f3b695e	487	#define LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CCR_CKMODE_1 ) /!< ADC synchronous clock derived from AHB clock divided by 2 /
EricLew	0:80ee8f3b695e	488	#define LL_ADC_CLOCK_SYNC_PCLK_DIV4 (ADC_CCR_CKMODE_1 \| ADC_CCR_CKMODE_0) /!< ADC synchronous clock derived from AHB clock divided by 4 /
EricLew	0:80ee8f3b695e	489	#define LL_ADC_CLOCK_ASYNC_DIV1 ((uint32_t)0x00000000) /!< ADC asynchronous clock not divided /
EricLew	0:80ee8f3b695e	490	#define LL_ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0) /!< ADC asynchronous clock divided by 2 /
EricLew	0:80ee8f3b695e	491	#define LL_ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1 ) /!< ADC asynchronous clock divided by 4 /
EricLew	0:80ee8f3b695e	492	#define LL_ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 \| ADC_CCR_PRESC_0) /!< ADC asynchronous clock divided by 6 /
EricLew	0:80ee8f3b695e	493	#define LL_ADC_CLOCK_ASYNC_DIV8 (ADC_CCR_PRESC_2 ) /!< ADC asynchronous clock divided by 8 /
EricLew	0:80ee8f3b695e	494	#define LL_ADC_CLOCK_ASYNC_DIV10 (ADC_CCR_PRESC_2 \| ADC_CCR_PRESC_0) /!< ADC asynchronous clock divided by 10 /
EricLew	0:80ee8f3b695e	495	#define LL_ADC_CLOCK_ASYNC_DIV12 (ADC_CCR_PRESC_2 \| ADC_CCR_PRESC_1 ) /!< ADC asynchronous clock divided by 12 /
EricLew	0:80ee8f3b695e	496	#define LL_ADC_CLOCK_ASYNC_DIV16 (ADC_CCR_PRESC_2 \| ADC_CCR_PRESC_1 \| ADC_CCR_PRESC_0) /!< ADC asynchronous clock divided by 16 /
EricLew	0:80ee8f3b695e	497	#define LL_ADC_CLOCK_ASYNC_DIV32 (ADC_CCR_PRESC_3) /!< ADC asynchronous clock divided by 32 /
EricLew	0:80ee8f3b695e	498	#define LL_ADC_CLOCK_ASYNC_DIV64 (ADC_CCR_PRESC_3 \| ADC_CCR_PRESC_0) /!< ADC asynchronous clock divided by 64 /
EricLew	0:80ee8f3b695e	499	#define LL_ADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 \| ADC_CCR_PRESC_1) /!< ADC asynchronous clock divided by 128 /
EricLew	0:80ee8f3b695e	500	#define LL_ADC_CLOCK_ASYNC_DIV256 (ADC_CCR_PRESC_3 \| ADC_CCR_PRESC_1 \| ADC_CCR_PRESC_0) /!< ADC asynchronous clock divided by 256 /
EricLew	0:80ee8f3b695e	501	/**
EricLew	0:80ee8f3b695e	502	* @}
EricLew	0:80ee8f3b695e	503	*/
EricLew	0:80ee8f3b695e	504
EricLew	0:80ee8f3b695e	505	/** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels
EricLew	0:80ee8f3b695e	506	* @{
EricLew	0:80ee8f3b695e	507	*/
EricLew	0:80ee8f3b695e	508	/* Note: Other measurement paths to internal channels may be available */
EricLew	0:80ee8f3b695e	509	/* (connections to other peripherals). */
EricLew	0:80ee8f3b695e	510	/* If they are not listed below, they do not require any specific */
EricLew	0:80ee8f3b695e	511	/* path enable. In this case, Access to measurement path is done */
EricLew	0:80ee8f3b695e	512	/* only by selecting the corresponding ADC internal channel. */
EricLew	0:80ee8f3b695e	513	#define LL_ADC_PATH_INTERNAL_NONE ((uint32_t)0x00000000) /!< ADC measurement pathes all disabled /
EricLew	0:80ee8f3b695e	514	#define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN) /!< ADC measurement path to internal channel VrefInt /
EricLew	0:80ee8f3b695e	515	#define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSEN) /!< ADC measurement path to internal channel temperature sensor /
EricLew	0:80ee8f3b695e	516	#define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATEN) /!< ADC measurement path to internal channel Vbat /
EricLew	0:80ee8f3b695e	517	/**
EricLew	0:80ee8f3b695e	518	* @}
EricLew	0:80ee8f3b695e	519	*/
EricLew	0:80ee8f3b695e	520
EricLew	0:80ee8f3b695e	521	/** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution
EricLew	0:80ee8f3b695e	522	* @{
EricLew	0:80ee8f3b695e	523	*/
EricLew	0:80ee8f3b695e	524	#define LL_ADC_RESOLUTION_12B ((uint32_t)0x00000000) /!< ADC resolution 12 bits /
EricLew	0:80ee8f3b695e	525	#define LL_ADC_RESOLUTION_10B ( ADC_CFGR_RES_0) /!< ADC resolution 10 bits /
EricLew	0:80ee8f3b695e	526	#define LL_ADC_RESOLUTION_8B (ADC_CFGR_RES_1 ) /!< ADC resolution 8 bits /
EricLew	0:80ee8f3b695e	527	#define LL_ADC_RESOLUTION_6B (ADC_CFGR_RES_1 \| ADC_CFGR_RES_0) /!< ADC resolution 6 bits /
EricLew	0:80ee8f3b695e	528	/**
EricLew	0:80ee8f3b695e	529	* @}
EricLew	0:80ee8f3b695e	530	*/
EricLew	0:80ee8f3b695e	531
EricLew	0:80ee8f3b695e	532	/** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment
EricLew	0:80ee8f3b695e	533	* @{
EricLew	0:80ee8f3b695e	534	*/
EricLew	0:80ee8f3b695e	535	#define LL_ADC_DATA_ALIGN_RIGHT ((uint32_t)0x00000000) /!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)/
EricLew	0:80ee8f3b695e	536	#define LL_ADC_DATA_ALIGN_LEFT (ADC_CFGR_ALIGN) /!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)/
EricLew	0:80ee8f3b695e	537	/**
EricLew	0:80ee8f3b695e	538	* @}
EricLew	0:80ee8f3b695e	539	*/
EricLew	0:80ee8f3b695e	540
EricLew	0:80ee8f3b695e	541	/** @defgroup ADC_LL_EC_LP_MODE ADC instance - Low power mode
EricLew	0:80ee8f3b695e	542	* @{
EricLew	0:80ee8f3b695e	543	*/
EricLew	0:80ee8f3b695e	544	#define LL_ADC_LP_MODE_NONE ((uint32_t)0x00000000) /!< No ADC low power mode activated /
EricLew	0:80ee8f3b695e	545	#define LL_ADC_LP_AUTOWAIT (ADC_CFGR_AUTDLY) /!< ADC low power mode auto delay: Dynamic low power mode, ADC conversions are performed only when necessary. See description with function @ref LL_ADC_SetLowPowerMode(). /
EricLew	0:80ee8f3b695e	546	/**
EricLew	0:80ee8f3b695e	547	* @}
EricLew	0:80ee8f3b695e	548	*/
EricLew	0:80ee8f3b695e	549
EricLew	0:80ee8f3b695e	550	/** @defgroup ADC_LL_EC_OFFSET_NB ADC instance - Offset number
EricLew	0:80ee8f3b695e	551	* @{
EricLew	0:80ee8f3b695e	552	*/
EricLew	0:80ee8f3b695e	553	#define LL_ADC_OFFSET_1 ADC_OFR1_REGOFFSET /!< ADC offset number 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) /
EricLew	0:80ee8f3b695e	554	#define LL_ADC_OFFSET_2 ADC_OFR2_REGOFFSET /!< ADC offset number 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) /
EricLew	0:80ee8f3b695e	555	#define LL_ADC_OFFSET_3 ADC_OFR3_REGOFFSET /!< ADC offset number 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) /
EricLew	0:80ee8f3b695e	556	#define LL_ADC_OFFSET_4 ADC_OFR4_REGOFFSET /!< ADC offset number 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) /
EricLew	0:80ee8f3b695e	557	/**
EricLew	0:80ee8f3b695e	558	* @}
EricLew	0:80ee8f3b695e	559	*/
EricLew	0:80ee8f3b695e	560
EricLew	0:80ee8f3b695e	561	/** @defgroup ADC_LL_EC_OFFSET_STATE ADC instance - Offset state
EricLew	0:80ee8f3b695e	562	* @{
EricLew	0:80ee8f3b695e	563	*/
EricLew	0:80ee8f3b695e	564	#define LL_ADC_OFFSET_DISABLE ((uint32_t)0x00000000) /!< ADC offset disabled (among ADC selected offset number 1, 2, 3 or 4) /
EricLew	0:80ee8f3b695e	565	#define LL_ADC_OFFSET_ENABLE (ADC_OFR1_OFFSET1_EN) /!< ADC offset enabled (among ADC selected offset number 1, 2, 3 or 4) /
EricLew	0:80ee8f3b695e	566	/**
EricLew	0:80ee8f3b695e	567	* @}
EricLew	0:80ee8f3b695e	568	*/
EricLew	0:80ee8f3b695e	569
EricLew	0:80ee8f3b695e	570	/** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups
EricLew	0:80ee8f3b695e	571	* @{
EricLew	0:80ee8f3b695e	572	*/
EricLew	0:80ee8f3b695e	573	#define LL_ADC_GROUP_REGULAR ((uint32_t)0x00000001) /!< ADC group regular (available on all STM32 devices) /
EricLew	0:80ee8f3b695e	574	#define LL_ADC_GROUP_INJECTED ((uint32_t)0x00000002) /!< ADC group injected (not available on all STM32 devices)/
EricLew	0:80ee8f3b695e	575	#define LL_ADC_GROUP_REGULAR_INJECTED ((uint32_t)0x00000003) /!< ADC both groups regular and injected /
EricLew	0:80ee8f3b695e	576	/**
EricLew	0:80ee8f3b695e	577	* @}
EricLew	0:80ee8f3b695e	578	*/
EricLew	0:80ee8f3b695e	579
EricLew	0:80ee8f3b695e	580	/** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number
EricLew	0:80ee8f3b695e	581	* @{
EricLew	0:80ee8f3b695e	582	*/
EricLew	0:80ee8f3b695e	583	#define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER \| ADC_CHANNEL_0_SMP \| ADC_CHANNEL_0_BITFIELD ) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 /
EricLew	0:80ee8f3b695e	584	#define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER \| ADC_CHANNEL_1_SMP \| ADC_CHANNEL_1_BITFIELD ) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 /
EricLew	0:80ee8f3b695e	585	#define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER \| ADC_CHANNEL_2_SMP \| ADC_CHANNEL_2_BITFIELD ) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 /
EricLew	0:80ee8f3b695e	586	#define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER \| ADC_CHANNEL_3_SMP \| ADC_CHANNEL_3_BITFIELD ) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 /
EricLew	0:80ee8f3b695e	587	#define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER \| ADC_CHANNEL_4_SMP \| ADC_CHANNEL_4_BITFIELD ) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 /
EricLew	0:80ee8f3b695e	588	#define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER \| ADC_CHANNEL_5_SMP \| ADC_CHANNEL_5_BITFIELD ) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 /
EricLew	0:80ee8f3b695e	589	#define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER \| ADC_CHANNEL_6_SMP \| ADC_CHANNEL_6_BITFIELD ) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 /
EricLew	0:80ee8f3b695e	590	#define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER \| ADC_CHANNEL_7_SMP \| ADC_CHANNEL_7_BITFIELD ) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 /
EricLew	0:80ee8f3b695e	591	#define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER \| ADC_CHANNEL_8_SMP \| ADC_CHANNEL_8_BITFIELD ) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 /
EricLew	0:80ee8f3b695e	592	#define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER \| ADC_CHANNEL_9_SMP \| ADC_CHANNEL_9_BITFIELD ) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 /
EricLew	0:80ee8f3b695e	593	#define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER \| ADC_CHANNEL_10_SMP \| ADC_CHANNEL_10_BITFIELD) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 /
EricLew	0:80ee8f3b695e	594	#define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER \| ADC_CHANNEL_11_SMP \| ADC_CHANNEL_11_BITFIELD) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 /
EricLew	0:80ee8f3b695e	595	#define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER \| ADC_CHANNEL_12_SMP \| ADC_CHANNEL_12_BITFIELD) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 /
EricLew	0:80ee8f3b695e	596	#define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER \| ADC_CHANNEL_13_SMP \| ADC_CHANNEL_13_BITFIELD) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 /
EricLew	0:80ee8f3b695e	597	#define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER \| ADC_CHANNEL_14_SMP \| ADC_CHANNEL_14_BITFIELD) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 /
EricLew	0:80ee8f3b695e	598	#define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER \| ADC_CHANNEL_15_SMP \| ADC_CHANNEL_15_BITFIELD) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 /
EricLew	0:80ee8f3b695e	599	#define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER \| ADC_CHANNEL_16_SMP \| ADC_CHANNEL_16_BITFIELD) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 /
EricLew	0:80ee8f3b695e	600	#define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER \| ADC_CHANNEL_17_SMP \| ADC_CHANNEL_17_BITFIELD) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 /
EricLew	0:80ee8f3b695e	601	#define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER \| ADC_CHANNEL_18_SMP \| ADC_CHANNEL_18_BITFIELD) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 /
EricLew	0:80ee8f3b695e	602	#define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_0 \| ADC_CHANNEL_ID_INTERNAL_CH) /!< ADC internal channel connected to VrefInt: Internal voltage reference. On STM32L4, ADC channel available only on ADC instance: ADC1. /
EricLew	0:80ee8f3b695e	603	#define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_17 \| ADC_CHANNEL_ID_INTERNAL_CH) /!< ADC internal channel connected to Temperature sensor. On STM32L4, ADC channel available only on ADC instances: ADC1, ADC3. /
EricLew	0:80ee8f3b695e	604	#define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_18 \| ADC_CHANNEL_ID_INTERNAL_CH) /!< ADC internal channel connected to Vbat/3: Vbat voltage through an dividor ladder of factor 1/3 to have Vbat always below Vdda. On STM32L4, ADC channel available only on ADC instances: ADC1, ADC3. /
EricLew	0:80ee8f3b695e	605	#define LL_ADC_CHANNEL_DAC1CH1_ADC2 (LL_ADC_CHANNEL_17 \| ADC_CHANNEL_ID_INTERNAL_CH \| ADC_CHANNEL_ID_INTERNAL_CH_2) /!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC2 /
EricLew	0:80ee8f3b695e	606	#define LL_ADC_CHANNEL_DAC1CH2_ADC2 (LL_ADC_CHANNEL_18 \| ADC_CHANNEL_ID_INTERNAL_CH \| ADC_CHANNEL_ID_INTERNAL_CH_2) /!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC2 /
EricLew	0:80ee8f3b695e	607	#define LL_ADC_CHANNEL_DAC1CH1_ADC3 (LL_ADC_CHANNEL_14 \| ADC_CHANNEL_ID_INTERNAL_CH) /!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC3 /
EricLew	0:80ee8f3b695e	608	#define LL_ADC_CHANNEL_DAC1CH2_ADC3 (LL_ADC_CHANNEL_15 \| ADC_CHANNEL_ID_INTERNAL_CH) /!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC3 /
EricLew	0:80ee8f3b695e	609	/**
EricLew	0:80ee8f3b695e	610	* @}
EricLew	0:80ee8f3b695e	611	*/
EricLew	0:80ee8f3b695e	612
EricLew	0:80ee8f3b695e	613	/** @defgroup ADC_LL_EC_REG_TRIG_SOURCE ADC group regular - Trigger source
EricLew	0:80ee8f3b695e	614	* @{
EricLew	0:80ee8f3b695e	615	*/
EricLew	0:80ee8f3b695e	616	#define LL_ADC_REG_TRIG_SW_START ((uint32_t)0x00000000) /!< ADC group regular conversion trigger internal (SW start) /
EricLew	0:80ee8f3b695e	617	#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CFGR_EXTSEL_3 \| ADC_CFGR_EXTSEL_0 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger external from TIM1 TRGO. Trigger edge set to rising edge (default setting). /
EricLew	0:80ee8f3b695e	618	#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CFGR_EXTSEL_3 \| ADC_CFGR_EXTSEL_1 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger external from TIM1 TRGO2. Trigger edge set to rising edge (default setting). /
EricLew	0:80ee8f3b695e	619	#define LL_ADC_REG_TRIG_EXT_TIM1_CC1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger external from TIM1 CC1. Trigger edge set to rising edge (default setting). /
EricLew	0:80ee8f3b695e	620	#define LL_ADC_REG_TRIG_EXT_TIM1_CC2 (ADC_CFGR_EXTSEL_0 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger external from TIM1 CC2. Trigger edge set to rising edge (default setting). /
EricLew	0:80ee8f3b695e	621	#define LL_ADC_REG_TRIG_EXT_TIM1_CC3 (ADC_CFGR_EXTSEL_1 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger external from TIM1 CC3. Trigger edge set to rising edge (default setting). /
EricLew	0:80ee8f3b695e	622	#define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR_EXTSEL_3 \| ADC_CFGR_EXTSEL_1 \| ADC_CFGR_EXTSEL_0 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger external from TIM2 TRGO. Trigger edge set to rising edge (default setting). /
EricLew	0:80ee8f3b695e	623	#define LL_ADC_REG_TRIG_EXT_TIM2_CC2 (ADC_CFGR_EXTSEL_1 \| ADC_CFGR_EXTSEL_0 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger external from TIM2 CC2. Trigger edge set to rising edge (default setting). /
EricLew	0:80ee8f3b695e	624	#define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CFGR_EXTSEL_2 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger external from TIM3 TRGO. Trigger edge set to rising edge (default setting). /
EricLew	0:80ee8f3b695e	625	#define LL_ADC_REG_TRIG_EXT_TIM3_CC4 (ADC_CFGR_EXTSEL_3 \| ADC_CFGR_EXTSEL_2 \| ADC_CFGR_EXTSEL_1 \| ADC_CFGR_EXTSEL_0 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger external from TIM3 CC4. Trigger edge set to rising edge (default setting). /
EricLew	0:80ee8f3b695e	626	#define LL_ADC_REG_TRIG_EXT_TIM4_TRGO (ADC_CFGR_EXTSEL_3 \| ADC_CFGR_EXTSEL_2 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger external from TIM4 TRGO. Trigger edge set to rising edge (default setting). /
EricLew	0:80ee8f3b695e	627	#define LL_ADC_REG_TRIG_EXT_TIM4_CC4 (ADC_CFGR_EXTSEL_2 \| ADC_CFGR_EXTSEL_0 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger external from TIM4 CC4. Trigger edge set to rising edge (default setting). /
EricLew	0:80ee8f3b695e	628	#define LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CFGR_EXTSEL_3 \| ADC_CFGR_EXTSEL_2 \| ADC_CFGR_EXTSEL_0 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger external from TIM6 TRGO. Trigger edge set to rising edge (default setting). /
EricLew	0:80ee8f3b695e	629	#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO (ADC_CFGR_EXTSEL_2 \| ADC_CFGR_EXTSEL_1 \| ADC_CFGR_EXTSEL_0 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger external from TIM8 TRGO. Trigger edge set to rising edge (default setting). /
EricLew	0:80ee8f3b695e	630	#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 (ADC_CFGR_EXTSEL_3 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger external from TIM8 TRGO2. Trigger edge set to rising edge (default setting). /
EricLew	0:80ee8f3b695e	631	#define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR_EXTSEL_3 \| ADC_CFGR_EXTSEL_2 \| ADC_CFGR_EXTSEL_1 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger external from TIM15 TRGO. Trigger edge set to rising edge (default setting). /
EricLew	0:80ee8f3b695e	632	#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR_EXTSEL_2 \| ADC_CFGR_EXTSEL_1 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger external from external interrupt line 11. Trigger edge set to rising edge (default setting). /
EricLew	0:80ee8f3b695e	633	/**
EricLew	0:80ee8f3b695e	634	* @}
EricLew	0:80ee8f3b695e	635	*/
EricLew	0:80ee8f3b695e	636
EricLew	0:80ee8f3b695e	637	/** @defgroup ADC_LL_EC_REG_TRIG_EDGE ADC group regular - Trigger edge
EricLew	0:80ee8f3b695e	638	* @{
EricLew	0:80ee8f3b695e	639	*/
EricLew	0:80ee8f3b695e	640	#define LL_ADC_REG_TRIG_EXT_RISING ( ADC_CFGR_EXTEN_0) /!< ADC group regular conversion trigger polarity set to rising edge /
EricLew	0:80ee8f3b695e	641	#define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CFGR_EXTEN_1 ) /!< ADC group regular conversion trigger polarity set to falling edge /
EricLew	0:80ee8f3b695e	642	#define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CFGR_EXTEN_1 \| ADC_CFGR_EXTEN_0) /!< ADC group regular conversion trigger polarity set to both rising and falling edges /
EricLew	0:80ee8f3b695e	643	/**
EricLew	0:80ee8f3b695e	644	* @}
EricLew	0:80ee8f3b695e	645	*/
EricLew	0:80ee8f3b695e	646
EricLew	0:80ee8f3b695e	647	/** @defgroup ADC_LL_EC_REG_CONV ADC group regular - Continuous mode
EricLew	0:80ee8f3b695e	648	* @{
EricLew	0:80ee8f3b695e	649	*/
EricLew	0:80ee8f3b695e	650	#define LL_ADC_REG_CONV_SINGLE ((uint32_t)0x00000000) /!< ADC conversions are performed in single mode: one conversion per trigger /
EricLew	0:80ee8f3b695e	651	#define LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR_CONT) /!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically /
EricLew	0:80ee8f3b695e	652	/**
EricLew	0:80ee8f3b695e	653	* @}
EricLew	0:80ee8f3b695e	654	*/
EricLew	0:80ee8f3b695e	655
EricLew	0:80ee8f3b695e	656	/** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer
EricLew	0:80ee8f3b695e	657	* @{
EricLew	0:80ee8f3b695e	658	*/
EricLew	0:80ee8f3b695e	659	#define LL_ADC_REG_DMA_TRANSFER_NONE ((uint32_t)0x00000000) /!< ADC conversions are not transferred by DMA /
EricLew	0:80ee8f3b695e	660	#define LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CFGR_DMAEN) /!< ADC conversions are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. /
EricLew	0:80ee8f3b695e	661	#define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR_DMACFG \| ADC_CFGR_DMAEN) /!< ADC conversions are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. /
EricLew	0:80ee8f3b695e	662	/**
EricLew	0:80ee8f3b695e	663	* @}
EricLew	0:80ee8f3b695e	664	*/
EricLew	0:80ee8f3b695e	665
EricLew	0:80ee8f3b695e	666	/** @defgroup ADC_LL_EC_REG_OVR ADC group regular - Overrun
EricLew	0:80ee8f3b695e	667	* @{
EricLew	0:80ee8f3b695e	668	*/
EricLew	0:80ee8f3b695e	669	#define LL_ADC_REG_OVR_DATA_PRESERVED ((uint32_t)0x00000000) /!< ADC group regular behaviour in case of overrun: data preserved /
EricLew	0:80ee8f3b695e	670	#define LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR_OVRMOD) /!< ADC group regular behaviour in case of overrun: data overwritten /
EricLew	0:80ee8f3b695e	671	/**
EricLew	0:80ee8f3b695e	672	* @}
EricLew	0:80ee8f3b695e	673	*/
EricLew	0:80ee8f3b695e	674
EricLew	0:80ee8f3b695e	675	/** @defgroup ADC_LL_EC_REG_SEQ_LENGTH ADC group regular - Sequencer length
EricLew	0:80ee8f3b695e	676	* @{
EricLew	0:80ee8f3b695e	677	*/
EricLew	0:80ee8f3b695e	678	#define LL_ADC_REG_SEQ_SCAN_DISABLE ((uint32_t)0x00000000) /!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) /
EricLew	0:80ee8f3b695e	679	#define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0) /!< ADC group regular sequencer enable with 2 ranks in the sequence /
EricLew	0:80ee8f3b695e	680	#define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 ) /!< ADC group regular sequencer enable with 3 ranks in the sequence /
EricLew	0:80ee8f3b695e	681	#define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 \| ADC_SQR1_L_0) /!< ADC group regular sequencer enable with 4 ranks in the sequence /
EricLew	0:80ee8f3b695e	682	#define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_L_2 ) /!< ADC group regular sequencer enable with 5 ranks in the sequence /
EricLew	0:80ee8f3b695e	683	#define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_L_2 \| ADC_SQR1_L_0) /!< ADC group regular sequencer enable with 6 ranks in the sequence /
EricLew	0:80ee8f3b695e	684	#define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_L_2 \| ADC_SQR1_L_1 ) /!< ADC group regular sequencer enable with 7 ranks in the sequence /
EricLew	0:80ee8f3b695e	685	#define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_L_2 \| ADC_SQR1_L_1 \| ADC_SQR1_L_0) /!< ADC group regular sequencer enable with 8 ranks in the sequence /
EricLew	0:80ee8f3b695e	686	#define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3 ) /!< ADC group regular sequencer enable with 9 ranks in the sequence /
EricLew	0:80ee8f3b695e	687	#define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 \| ADC_SQR1_L_0) /!< ADC group regular sequencer enable with 10 ranks in the sequence /
EricLew	0:80ee8f3b695e	688	#define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 \| ADC_SQR1_L_1 ) /!< ADC group regular sequencer enable with 11 ranks in the sequence /
EricLew	0:80ee8f3b695e	689	#define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 \| ADC_SQR1_L_1 \| ADC_SQR1_L_0) /!< ADC group regular sequencer enable with 12 ranks in the sequence /
EricLew	0:80ee8f3b695e	690	#define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 \| ADC_SQR1_L_2 ) /!< ADC group regular sequencer enable with 13 ranks in the sequence /
EricLew	0:80ee8f3b695e	691	#define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 \| ADC_SQR1_L_2 \| ADC_SQR1_L_0) /!< ADC group regular sequencer enable with 14 ranks in the sequence /
EricLew	0:80ee8f3b695e	692	#define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 \| ADC_SQR1_L_2 \| ADC_SQR1_L_1 ) /!< ADC group regular sequencer enable with 15 ranks in the sequence /
EricLew	0:80ee8f3b695e	693	#define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 \| ADC_SQR1_L_2 \| ADC_SQR1_L_1 \| ADC_SQR1_L_0) /!< ADC group regular sequencer enable with 16 ranks in the sequence /
EricLew	0:80ee8f3b695e	694	/**
EricLew	0:80ee8f3b695e	695	* @}
EricLew	0:80ee8f3b695e	696	*/
EricLew	0:80ee8f3b695e	697
EricLew	0:80ee8f3b695e	698	/** @defgroup ADC_LL_EC_REG_SEQ_DISCONT ADC group regular - Sequencer discontinuous mode
EricLew	0:80ee8f3b695e	699	* @{
EricLew	0:80ee8f3b695e	700	*/
EricLew	0:80ee8f3b695e	701	#define LL_ADC_REG_SEQ_DISCONT_DISABLE ((uint32_t)0x00000000) /!< ADC group regular sequencer discontinuous mode disable /
EricLew	0:80ee8f3b695e	702	#define LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CFGR_DISCEN) /!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank /
EricLew	0:80ee8f3b695e	703	#define LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CFGR_DISCNUM_0 \| ADC_CFGR_DISCEN) /!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks /
EricLew	0:80ee8f3b695e	704	#define LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CFGR_DISCNUM_1 \| ADC_CFGR_DISCEN) /!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks /
EricLew	0:80ee8f3b695e	705	#define LL_ADC_REG_SEQ_DISCONT_4RANKS ( ADC_CFGR_DISCNUM_1 \| ADC_CFGR_DISCNUM_0 \| ADC_CFGR_DISCEN) /!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks /
EricLew	0:80ee8f3b695e	706	#define LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CFGR_DISCNUM_2 \| ADC_CFGR_DISCEN) /!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks /
EricLew	0:80ee8f3b695e	707	#define LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CFGR_DISCNUM_2 \| ADC_CFGR_DISCNUM_0 \| ADC_CFGR_DISCEN) /!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks /
EricLew	0:80ee8f3b695e	708	#define LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CFGR_DISCNUM_2 \| ADC_CFGR_DISCNUM_1 \| ADC_CFGR_DISCEN) /!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks /
EricLew	0:80ee8f3b695e	709	#define LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CFGR_DISCNUM_2 \| ADC_CFGR_DISCNUM_1 \| ADC_CFGR_DISCNUM_0 \| ADC_CFGR_DISCEN) /!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks /
EricLew	0:80ee8f3b695e	710	/**
EricLew	0:80ee8f3b695e	711	* @}
EricLew	0:80ee8f3b695e	712	*/
EricLew	0:80ee8f3b695e	713
EricLew	0:80ee8f3b695e	714	/** @defgroup ADC_LL_EC_REG_RANKS ADC group regular - Sequencer ranks
EricLew	0:80ee8f3b695e	715	* @{
EricLew	0:80ee8f3b695e	716	*/
EricLew	0:80ee8f3b695e	717	#define LL_ADC_REG_RANK_1 (ADC_SQR1_REGOFFSET \| ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 1 /
EricLew	0:80ee8f3b695e	718	#define LL_ADC_REG_RANK_2 (ADC_SQR1_REGOFFSET \| ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 2 /
EricLew	0:80ee8f3b695e	719	#define LL_ADC_REG_RANK_3 (ADC_SQR1_REGOFFSET \| ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 3 /
EricLew	0:80ee8f3b695e	720	#define LL_ADC_REG_RANK_4 (ADC_SQR1_REGOFFSET \| ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 4 /
EricLew	0:80ee8f3b695e	721	#define LL_ADC_REG_RANK_5 (ADC_SQR2_REGOFFSET \| ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 5 /
EricLew	0:80ee8f3b695e	722	#define LL_ADC_REG_RANK_6 (ADC_SQR2_REGOFFSET \| ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 6 /
EricLew	0:80ee8f3b695e	723	#define LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET \| ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 7 /
EricLew	0:80ee8f3b695e	724	#define LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET \| ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 8 /
EricLew	0:80ee8f3b695e	725	#define LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET \| ADC_REG_RANK_9_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 9 /
EricLew	0:80ee8f3b695e	726	#define LL_ADC_REG_RANK_10 (ADC_SQR3_REGOFFSET \| ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 10 /
EricLew	0:80ee8f3b695e	727	#define LL_ADC_REG_RANK_11 (ADC_SQR3_REGOFFSET \| ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 11 /
EricLew	0:80ee8f3b695e	728	#define LL_ADC_REG_RANK_12 (ADC_SQR3_REGOFFSET \| ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 12 /
EricLew	0:80ee8f3b695e	729	#define LL_ADC_REG_RANK_13 (ADC_SQR3_REGOFFSET \| ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 13 /
EricLew	0:80ee8f3b695e	730	#define LL_ADC_REG_RANK_14 (ADC_SQR3_REGOFFSET \| ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 14 /
EricLew	0:80ee8f3b695e	731	#define LL_ADC_REG_RANK_15 (ADC_SQR4_REGOFFSET \| ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 15 /
EricLew	0:80ee8f3b695e	732	#define LL_ADC_REG_RANK_16 (ADC_SQR4_REGOFFSET \| ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 16 /
EricLew	0:80ee8f3b695e	733	/**
EricLew	0:80ee8f3b695e	734	* @}
EricLew	0:80ee8f3b695e	735	*/
EricLew	0:80ee8f3b695e	736
EricLew	0:80ee8f3b695e	737	/** @defgroup ADC_LL_EC_INJ_TRIG_SOURCE ADC group injected - Trigger source
EricLew	0:80ee8f3b695e	738	* @{
EricLew	0:80ee8f3b695e	739	*/
EricLew	0:80ee8f3b695e	740	#define LL_ADC_INJ_TRIG_SW_START ((uint32_t)0x00000000) /!< ADC group injected conversion trigger internal (SW start). Trigger edge set to rising edge (default setting). /
EricLew	0:80ee8f3b695e	741	#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /!< ADC group injected conversion trigger external from TIM1 TRGO. Trigger edge set to rising edge (default setting). /
EricLew	0:80ee8f3b695e	742	#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_JSQR_JEXTSEL_3 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /!< ADC group injected conversion trigger external from TIM1 TRGO2. Trigger edge set to rising edge (default setting). /
EricLew	0:80ee8f3b695e	743	#define LL_ADC_INJ_TRIG_EXT_TIM1_CC4 (ADC_JSQR_JEXTSEL_0 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /!< ADC group injected conversion trigger external from TIM1 CC4. Trigger edge set to rising edge (default setting). /
EricLew	0:80ee8f3b695e	744	#define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_JSQR_JEXTSEL_1 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /!< ADC group injected conversion trigger external from TIM2 TRGO. Trigger edge set to rising edge (default setting). /
EricLew	0:80ee8f3b695e	745	#define LL_ADC_INJ_TRIG_EXT_TIM2_CC1 (ADC_JSQR_JEXTSEL_1 \| ADC_JSQR_JEXTSEL_0 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /!< ADC group injected conversion trigger external from TIM2 CC1. Trigger edge set to rising edge (default setting). /
EricLew	0:80ee8f3b695e	746	#define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO (ADC_JSQR_JEXTSEL_3 \| ADC_JSQR_JEXTSEL_2 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /!< ADC group injected conversion trigger external from TIM3 TRGO. Trigger edge set to rising edge (default setting). /
EricLew	0:80ee8f3b695e	747	#define LL_ADC_INJ_TRIG_EXT_TIM3_CC1 (ADC_JSQR_JEXTSEL_3 \| ADC_JSQR_JEXTSEL_2 \| ADC_JSQR_JEXTSEL_0 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /!< ADC group injected conversion trigger external from TIM3 CC1. Trigger edge set to rising edge (default setting). /
EricLew	0:80ee8f3b695e	748	#define LL_ADC_INJ_TRIG_EXT_TIM3_CC3 (ADC_JSQR_JEXTSEL_3 \| ADC_JSQR_JEXTSEL_1 \| ADC_JSQR_JEXTSEL_0 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /!< ADC group injected conversion trigger external from TIM3 CC3. Trigger edge set to rising edge (default setting). /
EricLew	0:80ee8f3b695e	749	#define LL_ADC_INJ_TRIG_EXT_TIM3_CC4 (ADC_JSQR_JEXTSEL_2 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /!< ADC group injected conversion trigger external from TIM3 CC4. Trigger edge set to rising edge (default setting). /
EricLew	0:80ee8f3b695e	750	#define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_JSQR_JEXTSEL_2 \| ADC_JSQR_JEXTSEL_0 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /!< ADC group injected conversion trigger external from TIM4 TRGO. Trigger edge set to rising edge (default setting). /
EricLew	0:80ee8f3b695e	751	#define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (ADC_JSQR_JEXTSEL_3 \| ADC_JSQR_JEXTSEL_2 \| ADC_JSQR_JEXTSEL_1 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /!< ADC group injected conversion trigger external from TIM6 TRGO. Trigger edge set to rising edge (default setting). /
EricLew	0:80ee8f3b695e	752	#define LL_ADC_INJ_TRIG_EXT_TIM8_CC4 (ADC_JSQR_JEXTSEL_2 \| ADC_JSQR_JEXTSEL_1 \| ADC_JSQR_JEXTSEL_0 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /!< ADC group injected conversion trigger external from TIM8 CC4. Trigger edge set to rising edge (default setting). /
EricLew	0:80ee8f3b695e	753	#define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO (ADC_JSQR_JEXTSEL_3 \| ADC_JSQR_JEXTSEL_0 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /!< ADC group injected conversion trigger external from TIM8 TRGO. Trigger edge set to rising edge (default setting). /
EricLew	0:80ee8f3b695e	754	#define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 (ADC_JSQR_JEXTSEL_3 \| ADC_JSQR_JEXTSEL_1 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /!< ADC group injected conversion trigger external from TIM8 TRGO2. Trigger edge set to rising edge (default setting). /
EricLew	0:80ee8f3b695e	755	#define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO (ADC_JSQR_JEXTSEL_3 \| ADC_JSQR_JEXTSEL_2 \| ADC_JSQR_JEXTSEL_1 \| ADC_JSQR_JEXTSEL_0 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /!< ADC group injected conversion trigger external from TIM15 TRGO. Trigger edge set to rising edge (default setting). /
EricLew	0:80ee8f3b695e	756	#define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_JSQR_JEXTSEL_2 \| ADC_JSQR_JEXTSEL_1 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /!< ADC group injected conversion trigger external from external interrupt line 15. Trigger edge set to rising edge (default setting). /
EricLew	0:80ee8f3b695e	757	/**
EricLew	0:80ee8f3b695e	758	* @}
EricLew	0:80ee8f3b695e	759	*/
EricLew	0:80ee8f3b695e	760
EricLew	0:80ee8f3b695e	761	/** @defgroup ADC_LL_EC_INJ_TRIG_EDGE ADC group injected - Trigger edge
EricLew	0:80ee8f3b695e	762	* @{
EricLew	0:80ee8f3b695e	763	*/
EricLew	0:80ee8f3b695e	764	#define LL_ADC_INJ_TRIG_EXT_RISING ( ADC_JSQR_JEXTEN_0) /!< ADC group injected conversion trigger polarity set to rising edge /
EricLew	0:80ee8f3b695e	765	#define LL_ADC_INJ_TRIG_EXT_FALLING (ADC_JSQR_JEXTEN_1 ) /!< ADC group injected conversion trigger polarity set to falling edge /
EricLew	0:80ee8f3b695e	766	#define LL_ADC_INJ_TRIG_EXT_RISINGFALLING (ADC_JSQR_JEXTEN_1 \| ADC_JSQR_JEXTEN_0) /!< ADC group injected conversion trigger polarity set to both rising and falling edges /
EricLew	0:80ee8f3b695e	767	/**
EricLew	0:80ee8f3b695e	768	* @}
EricLew	0:80ee8f3b695e	769	*/
EricLew	0:80ee8f3b695e	770
EricLew	0:80ee8f3b695e	771	/** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Trigger automatic mode
EricLew	0:80ee8f3b695e	772	* @{
EricLew	0:80ee8f3b695e	773	*/
EricLew	0:80ee8f3b695e	774	#define LL_ADC_INJ_TRIG_INDEPENDENT ((uint32_t)0x00000000) /!< ADC group injected conversion trigger independent /
EricLew	0:80ee8f3b695e	775	#define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CFGR_JAUTO) /!< ADC group injected conversion trigger from ADC group regular /
EricLew	0:80ee8f3b695e	776	/**
EricLew	0:80ee8f3b695e	777	* @}
EricLew	0:80ee8f3b695e	778	*/
EricLew	0:80ee8f3b695e	779
EricLew	0:80ee8f3b695e	780	/** @defgroup ADC_LL_EC_INJ_CONTEXT_QUEUE ADC group injected - Context queue mode
EricLew	0:80ee8f3b695e	781	* @{
EricLew	0:80ee8f3b695e	782	*/
EricLew	0:80ee8f3b695e	783	#define LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE ((uint32_t)0x00000000) /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue maintains the last context active perpetually. */
EricLew	0:80ee8f3b695e	784	#define LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY (ADC_CFGR_JQM) /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue is empty and injected group triggers are disabled. */
EricLew	0:80ee8f3b695e	785	#define LL_ADC_INJ_QUEUE_DISABLE (ADC_CFGR_JQDIS) /* Group injected sequence context queue is disabled: only 1 sequence can be configured and is active perpetually. */
EricLew	0:80ee8f3b695e	786	/**
EricLew	0:80ee8f3b695e	787	* @}
EricLew	0:80ee8f3b695e	788	*/
EricLew	0:80ee8f3b695e	789
EricLew	0:80ee8f3b695e	790	/** @defgroup ADC_LL_EC_INJ_SEQ_LENGTH ADC group injected - Sequencer length
EricLew	0:80ee8f3b695e	791	* @{
EricLew	0:80ee8f3b695e	792	*/
EricLew	0:80ee8f3b695e	793	#define LL_ADC_INJ_SEQ_SCAN_DISABLE ((uint32_t)0x00000000) /!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) /
EricLew	0:80ee8f3b695e	794	#define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0) /!< ADC group injected sequencer enable with 2 ranks in the sequence /
EricLew	0:80ee8f3b695e	795	#define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 ) /!< ADC group injected sequencer enable with 3 ranks in the sequence /
EricLew	0:80ee8f3b695e	796	#define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 \| ADC_JSQR_JL_0) /!< ADC group injected sequencer enable with 4 ranks in the sequence /
EricLew	0:80ee8f3b695e	797	/**
EricLew	0:80ee8f3b695e	798	* @}
EricLew	0:80ee8f3b695e	799	*/
EricLew	0:80ee8f3b695e	800
EricLew	0:80ee8f3b695e	801	/** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT ADC group injected - Sequencer discontinuous mode
EricLew	0:80ee8f3b695e	802	* @{
EricLew	0:80ee8f3b695e	803	*/
EricLew	0:80ee8f3b695e	804	#define LL_ADC_INJ_SEQ_DISCONT_DISABLE ((uint32_t)0x00000000) /!< ADC group injected sequencer discontinuous mode disable /
EricLew	0:80ee8f3b695e	805	#define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CFGR_JDISCEN) /!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank /
EricLew	0:80ee8f3b695e	806	/**
EricLew	0:80ee8f3b695e	807	* @}
EricLew	0:80ee8f3b695e	808	*/
EricLew	0:80ee8f3b695e	809
EricLew	0:80ee8f3b695e	810	/** @defgroup ADC_LL_EC_INJ_RANKS ADC group injected - Sequencer ranks
EricLew	0:80ee8f3b695e	811	* @{
EricLew	0:80ee8f3b695e	812	*/
EricLew	0:80ee8f3b695e	813	#define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET \| ADC_INJ_RANK_1_JSQR_BITOFFSET_POS) /!< ADC group injected sequencer rank 1 /
EricLew	0:80ee8f3b695e	814	#define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET \| ADC_INJ_RANK_2_JSQR_BITOFFSET_POS) /!< ADC group injected sequencer rank 2 /
EricLew	0:80ee8f3b695e	815	#define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET \| ADC_INJ_RANK_3_JSQR_BITOFFSET_POS) /!< ADC group injected sequencer rank 3 /
EricLew	0:80ee8f3b695e	816	#define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET \| ADC_INJ_RANK_4_JSQR_BITOFFSET_POS) /!< ADC group injected sequencer rank 4 /
EricLew	0:80ee8f3b695e	817	/**
EricLew	0:80ee8f3b695e	818	* @}
EricLew	0:80ee8f3b695e	819	*/
EricLew	0:80ee8f3b695e	820
EricLew	0:80ee8f3b695e	821	/** @defgroup ADC_LL_EC_SAMPLINGTIME Channel - Sampling time
EricLew	0:80ee8f3b695e	822	* @{
EricLew	0:80ee8f3b695e	823	*/
EricLew	0:80ee8f3b695e	824	#define LL_ADC_SAMPLINGTIME_2CYCLES_5 (0x00000000) /!< Sampling time 2.5 ADC clock cycle /
EricLew	0:80ee8f3b695e	825	#define LL_ADC_SAMPLINGTIME_6CYCLES_5 ( ADC_SMPR2_SMP10_0) /!< Sampling time 6.5 ADC clock cycles /
EricLew	0:80ee8f3b695e	826	#define LL_ADC_SAMPLINGTIME_12CYCLES_5 ( ADC_SMPR2_SMP10_1 ) /!< Sampling time 12.5 ADC clock cycles /
EricLew	0:80ee8f3b695e	827	#define LL_ADC_SAMPLINGTIME_24CYCLES_5 ( ADC_SMPR2_SMP10_1 \| ADC_SMPR2_SMP10_0) /!< Sampling time 24.5 ADC clock cycles /
EricLew	0:80ee8f3b695e	828	#define LL_ADC_SAMPLINGTIME_47CYCLES_5 (ADC_SMPR2_SMP10_2 ) /!< Sampling time 47.5 ADC clock cycles /
EricLew	0:80ee8f3b695e	829	#define LL_ADC_SAMPLINGTIME_92CYCLES_5 (ADC_SMPR2_SMP10_2 \| ADC_SMPR2_SMP10_0) /!< Sampling time 92.5 ADC clock cycles /
EricLew	0:80ee8f3b695e	830	#define LL_ADC_SAMPLINGTIME_247CYCLES_5 (ADC_SMPR2_SMP10_2 \| ADC_SMPR2_SMP10_1 ) /!< Sampling time 247.5 ADC clock cycles /
EricLew	0:80ee8f3b695e	831	#define LL_ADC_SAMPLINGTIME_640CYCLES_5 (ADC_SMPR2_SMP10_2 \| ADC_SMPR2_SMP10_1 \| ADC_SMPR2_SMP10_0) /!< Sampling time 640.5 ADC clock cycles /
EricLew	0:80ee8f3b695e	832	/**
EricLew	0:80ee8f3b695e	833	* @}
EricLew	0:80ee8f3b695e	834	*/
EricLew	0:80ee8f3b695e	835
EricLew	0:80ee8f3b695e	836	/** @defgroup ADC_LL_EC_SINGLE_DIFF_ENDING Channel - Single or differential ending
EricLew	0:80ee8f3b695e	837	* @{
EricLew	0:80ee8f3b695e	838	*/
EricLew	0:80ee8f3b695e	839	#define LL_ADC_SINGLE_ENDED ( ADC_CALFACT_CALFACT_S) /!< ADC channel ending set to single ended (literal also used to set calibration mode) /
EricLew	0:80ee8f3b695e	840	#define LL_ADC_DIFFERENTIAL_ENDED (ADC_CR_ADCALDIF \| ADC_CALFACT_CALFACT_D) /!< ADC channel ending set to differential (literal also used to set calibration mode) /
EricLew	0:80ee8f3b695e	841	#define LL_ADC_BOTH_SINGLE_DIFF_ENDED (LL_ADC_SINGLE_ENDED \| LL_ADC_DIFFERENTIAL_ENDED) /!< ADC channel ending set to both single ended and differential (literal used only to set calibration factors) /
EricLew	0:80ee8f3b695e	842	/**
EricLew	0:80ee8f3b695e	843	* @}
EricLew	0:80ee8f3b695e	844	*/
EricLew	0:80ee8f3b695e	845
EricLew	0:80ee8f3b695e	846	/** @defgroup ADC_LL_EC_AWD Analog watchdog - Analog watchdog number
EricLew	0:80ee8f3b695e	847	* @{
EricLew	0:80ee8f3b695e	848	*/
EricLew	0:80ee8f3b695e	849	#define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK \| ADC_AWD_CR1_REGOFFSET) /!< ADC analog watchdog number 1 /
EricLew	0:80ee8f3b695e	850	#define LL_ADC_AWD2 (ADC_AWD_CR23_CHANNEL_MASK \| ADC_AWD_CR2_REGOFFSET) /!< ADC analog watchdog number 2 /
EricLew	0:80ee8f3b695e	851	#define LL_ADC_AWD3 (ADC_AWD_CR23_CHANNEL_MASK \| ADC_AWD_CR3_REGOFFSET) /!< ADC analog watchdog number 3 /
EricLew	0:80ee8f3b695e	852	/**
EricLew	0:80ee8f3b695e	853	* @}
EricLew	0:80ee8f3b695e	854	*/
EricLew	0:80ee8f3b695e	855
EricLew	0:80ee8f3b695e	856	/** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels
EricLew	0:80ee8f3b695e	857	* @{
EricLew	0:80ee8f3b695e	858	*/
EricLew	0:80ee8f3b695e	859	#define LL_ADC_AWD_DISABLE ((uint32_t)0x00000000)
EricLew	0:80ee8f3b695e	860	#define LL_ADC_AWD_ALL_CHANNELS_REG (ADC_AWD_CR23_CHANNEL_MASK \| ADC_CFGR_AWD1EN ) /!< ADC analog watchdog monitoring of all channels, converted by group regular only /
EricLew	0:80ee8f3b695e	861	#define LL_ADC_AWD_ALL_CHANNELS_INJ (ADC_AWD_CR23_CHANNEL_MASK \| ADC_CFGR_JAWD1EN ) /!< ADC analog watchdog monitoring of all channels, converted by group injected only /
EricLew	0:80ee8f3b695e	862	#define LL_ADC_AWD_ALL_CHANNELS_REG_INJ (ADC_AWD_CR23_CHANNEL_MASK \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN ) /!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected /
EricLew	0:80ee8f3b695e	863	#define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only /
EricLew	0:80ee8f3b695e	864	#define LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only /
EricLew	0:80ee8f3b695e	865	#define LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected /
EricLew	0:80ee8f3b695e	866	#define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only /
EricLew	0:80ee8f3b695e	867	#define LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only /
EricLew	0:80ee8f3b695e	868	#define LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected /
EricLew	0:80ee8f3b695e	869	#define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only /
EricLew	0:80ee8f3b695e	870	#define LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only /
EricLew	0:80ee8f3b695e	871	#define LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected /
EricLew	0:80ee8f3b695e	872	#define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only /
EricLew	0:80ee8f3b695e	873	#define LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only /
EricLew	0:80ee8f3b695e	874	#define LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected /
EricLew	0:80ee8f3b695e	875	#define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only /
EricLew	0:80ee8f3b695e	876	#define LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only /
EricLew	0:80ee8f3b695e	877	#define LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected /
EricLew	0:80ee8f3b695e	878	#define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only /
EricLew	0:80ee8f3b695e	879	#define LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only /
EricLew	0:80ee8f3b695e	880	#define LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected /
EricLew	0:80ee8f3b695e	881	#define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only /
EricLew	0:80ee8f3b695e	882	#define LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only /
EricLew	0:80ee8f3b695e	883	#define LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected /
EricLew	0:80ee8f3b695e	884	#define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only /
EricLew	0:80ee8f3b695e	885	#define LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only /
EricLew	0:80ee8f3b695e	886	#define LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected /
EricLew	0:80ee8f3b695e	887	#define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only /
EricLew	0:80ee8f3b695e	888	#define LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only /
EricLew	0:80ee8f3b695e	889	#define LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected /
EricLew	0:80ee8f3b695e	890	#define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only /
EricLew	0:80ee8f3b695e	891	#define LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only /
EricLew	0:80ee8f3b695e	892	#define LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected /
EricLew	0:80ee8f3b695e	893	#define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only /
EricLew	0:80ee8f3b695e	894	#define LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only /
EricLew	0:80ee8f3b695e	895	#define LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected /
EricLew	0:80ee8f3b695e	896	#define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only /
EricLew	0:80ee8f3b695e	897	#define LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only /
EricLew	0:80ee8f3b695e	898	#define LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected /
EricLew	0:80ee8f3b695e	899	#define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only /
EricLew	0:80ee8f3b695e	900	#define LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only /
EricLew	0:80ee8f3b695e	901	#define LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected /
EricLew	0:80ee8f3b695e	902	#define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only /
EricLew	0:80ee8f3b695e	903	#define LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only /
EricLew	0:80ee8f3b695e	904	#define LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected /
EricLew	0:80ee8f3b695e	905	#define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only /
EricLew	0:80ee8f3b695e	906	#define LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only /
EricLew	0:80ee8f3b695e	907	#define LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected /
EricLew	0:80ee8f3b695e	908	#define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only /
EricLew	0:80ee8f3b695e	909	#define LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only /
EricLew	0:80ee8f3b695e	910	#define LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected /
EricLew	0:80ee8f3b695e	911	#define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only /
EricLew	0:80ee8f3b695e	912	#define LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only /
EricLew	0:80ee8f3b695e	913	#define LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected /
EricLew	0:80ee8f3b695e	914	#define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only /
EricLew	0:80ee8f3b695e	915	#define LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only /
EricLew	0:80ee8f3b695e	916	#define LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected /
EricLew	0:80ee8f3b695e	917	#define LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only /
EricLew	0:80ee8f3b695e	918	#define LL_ADC_AWD_CHANNEL_18_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group injected only /
EricLew	0:80ee8f3b695e	919	#define LL_ADC_AWD_CHANNEL_18_REG_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by either group regular or injected /
EricLew	0:80ee8f3b695e	920	#define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only /
EricLew	0:80ee8f3b695e	921	#define LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only /
EricLew	0:80ee8f3b695e	922	#define LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected /
EricLew	0:80ee8f3b695e	923	#define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only /
EricLew	0:80ee8f3b695e	924	#define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only /
EricLew	0:80ee8f3b695e	925	#define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected /
EricLew	0:80ee8f3b695e	926	#define LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through an dividor ladder of factor 1/3 to have Vbat always below Vdda, converted by group regular only /
EricLew	0:80ee8f3b695e	927	#define LL_ADC_AWD_CH_VBAT_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through an dividor ladder of factor 1/3 to have Vbat always below Vdda, converted by group injected only /
EricLew	0:80ee8f3b695e	928	#define LL_ADC_AWD_CH_VBAT_REG_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through an dividor ladder of factor 1/3 to have Vbat always below Vdda /
EricLew	0:80ee8f3b695e	929	#define LL_ADC_AWD_CH_DAC1CH1_ADC2_REG ((LL_ADC_CHANNEL_DAC1CH1_ADC2 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group regular only /
EricLew	0:80ee8f3b695e	930	#define LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC2 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group injected only /
EricLew	0:80ee8f3b695e	931	#define LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC2 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by either group regular or injected /
EricLew	0:80ee8f3b695e	932	#define LL_ADC_AWD_CH_DAC1CH2_ADC2_REG ((LL_ADC_CHANNEL_DAC1CH2_ADC2 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group regular only /
EricLew	0:80ee8f3b695e	933	#define LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC2 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group injected only /
EricLew	0:80ee8f3b695e	934	#define LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC2 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by either group regular or injected /
EricLew	0:80ee8f3b695e	935	#define LL_ADC_AWD_CH_DAC1CH1_ADC3_REG ((LL_ADC_CHANNEL_DAC1CH1_ADC3 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by group regular only /
EricLew	0:80ee8f3b695e	936	#define LL_ADC_AWD_CH_DAC1CH1_ADC3_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC3 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by group injected only /
EricLew	0:80ee8f3b695e	937	#define LL_ADC_AWD_CH_DAC1CH1_ADC3_REG_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC3 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by either group regular or injected /
EricLew	0:80ee8f3b695e	938	#define LL_ADC_AWD_CH_DAC1CH2_ADC3_REG ((LL_ADC_CHANNEL_DAC1CH2_ADC3 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by group regular only /
EricLew	0:80ee8f3b695e	939	#define LL_ADC_AWD_CH_DAC1CH2_ADC3_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC3 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by group injected only /
EricLew	0:80ee8f3b695e	940	#define LL_ADC_AWD_CH_DAC1CH2_ADC3_REG_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC3 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by either group regular or injected /
EricLew	0:80ee8f3b695e	941	/**
EricLew	0:80ee8f3b695e	942	* @}
EricLew	0:80ee8f3b695e	943	*/
EricLew	0:80ee8f3b695e	944
EricLew	0:80ee8f3b695e	945	/** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds
EricLew	0:80ee8f3b695e	946	* @{
EricLew	0:80ee8f3b695e	947	*/
EricLew	0:80ee8f3b695e	948	#define LL_ADC_AWD_THRESHOLD_HIGH (ADC_TR1_HT1 ) /!< ADC analog watchdog threshold high /
EricLew	0:80ee8f3b695e	949	#define LL_ADC_AWD_THRESHOLD_LOW ( ADC_TR1_LT1) /!< ADC analog watchdog threshold low /
EricLew	0:80ee8f3b695e	950	#define LL_ADC_AWD_THRESHOLDS_HIGH_LOW (ADC_TR1_HT1 \| ADC_TR1_LT1) /!< ADC analog watchdog both thresholds high and low concatenated into the same data /
EricLew	0:80ee8f3b695e	951	/**
EricLew	0:80ee8f3b695e	952	* @}
EricLew	0:80ee8f3b695e	953	*/
EricLew	0:80ee8f3b695e	954
EricLew	0:80ee8f3b695e	955	/** @defgroup ADC_LL_EC_OVS Oversampling - Oversampling scope
EricLew	0:80ee8f3b695e	956	* @{
EricLew	0:80ee8f3b695e	957	*/
EricLew	0:80ee8f3b695e	958	#define LL_ADC_OVS_DISABLE ((uint32_t)0x00000000)
EricLew	0:80ee8f3b695e	959	#define LL_ADC_OVS_GRP_REGULAR_CONTINUED ( ADC_CFGR2_ROVSE) /!< ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is temporary stopped and continued. /
EricLew	0:80ee8f3b695e	960	#define LL_ADC_OVS_GRP_REGULAR_RESUMED (ADC_CFGR2_ROVSM \| ADC_CFGR2_ROVSE) /!< ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset). /
EricLew	0:80ee8f3b695e	961	#define LL_ADC_OVS_GRP_INJECTED ( ADC_CFGR2_JOVSE ) /!< ADC oversampling on conversions of ADC group injected /
EricLew	0:80ee8f3b695e	962	#define LL_ADC_OVS_GRP_INJ_REG_RESUMED ( ADC_CFGR2_JOVSE \| ADC_CFGR2_ROVSE) /!< ADC oversampling on conversions of both ADC groups regular and injected. If group injected interrupting group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset). /
EricLew	0:80ee8f3b695e	963	/**
EricLew	0:80ee8f3b695e	964	* @}
EricLew	0:80ee8f3b695e	965	*/
EricLew	0:80ee8f3b695e	966
EricLew	0:80ee8f3b695e	967	/** @defgroup ADC_LL_EC_OVS_DISCONT Oversampling - Discontinuous mode
EricLew	0:80ee8f3b695e	968	* @{
EricLew	0:80ee8f3b695e	969	*/
EricLew	0:80ee8f3b695e	970	#define LL_ADC_OVS_REG_CONT ((uint32_t)0x00000000) /!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) /
EricLew	0:80ee8f3b695e	971	#define LL_ADC_OVS_REG_DISCONT (ADC_CFGR2_TROVS) /!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) /
EricLew	0:80ee8f3b695e	972	/**
EricLew	0:80ee8f3b695e	973	* @}
EricLew	0:80ee8f3b695e	974	*/
EricLew	0:80ee8f3b695e	975
EricLew	0:80ee8f3b695e	976	/** @defgroup ADC_LL_EC_OVS_RATIO Oversampling - Ratio
EricLew	0:80ee8f3b695e	977	* @{
EricLew	0:80ee8f3b695e	978	*/
EricLew	0:80ee8f3b695e	979	#define LL_ADC_OVS_RATIO_2 ((uint32_t)0x00000000) /!< ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) /
EricLew	0:80ee8f3b695e	980	#define LL_ADC_OVS_RATIO_4 ( ADC_CFGR2_OVSR_0) /!< ADC oversampling ratio of 4 (4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) /
EricLew	0:80ee8f3b695e	981	#define LL_ADC_OVS_RATIO_8 ( ADC_CFGR2_OVSR_1 ) /!< ADC oversampling ratio of 8 (8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) /
EricLew	0:80ee8f3b695e	982	#define LL_ADC_OVS_RATIO_16 ( ADC_CFGR2_OVSR_1 \| ADC_CFGR2_OVSR_0) /!< ADC oversampling ratio of 16 (16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) /
EricLew	0:80ee8f3b695e	983	#define LL_ADC_OVS_RATIO_32 (ADC_CFGR2_OVSR_2 ) /!< ADC oversampling ratio of 32 (32 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) /
EricLew	0:80ee8f3b695e	984	#define LL_ADC_OVS_RATIO_64 (ADC_CFGR2_OVSR_2 \| ADC_CFGR2_OVSR_0) /!< ADC oversampling ratio of 64 (64 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) /
EricLew	0:80ee8f3b695e	985	#define LL_ADC_OVS_RATIO_128 (ADC_CFGR2_OVSR_2 \| ADC_CFGR2_OVSR_1 ) /!< ADC oversampling ratio of 128 (128 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) /
EricLew	0:80ee8f3b695e	986	#define LL_ADC_OVS_RATIO_256 (ADC_CFGR2_OVSR_2 \| ADC_CFGR2_OVSR_1 \| ADC_CFGR2_OVSR_0) /!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) /
EricLew	0:80ee8f3b695e	987	/**
EricLew	0:80ee8f3b695e	988	* @}
EricLew	0:80ee8f3b695e	989	*/
EricLew	0:80ee8f3b695e	990
EricLew	0:80ee8f3b695e	991	/** @defgroup ADC_LL_EC_OVS_RIGHTBITSHIFT Oversampling - Data right shift
EricLew	0:80ee8f3b695e	992	* @{
EricLew	0:80ee8f3b695e	993	*/
EricLew	0:80ee8f3b695e	994	#define LL_ADC_OVS_DATA_SHIFT_NONE ((uint32_t)0x00000000) /!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) /
EricLew	0:80ee8f3b695e	995	#define LL_ADC_OVS_DATA_SHIFT_1 ( ADC_CFGR2_OVSS_0) /!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data) /
EricLew	0:80ee8f3b695e	996	#define LL_ADC_OVS_DATA_SHIFT_2 ( ADC_CFGR2_OVSS_1 ) /!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data) /
EricLew	0:80ee8f3b695e	997	#define LL_ADC_OVS_DATA_SHIFT_3 ( ADC_CFGR2_OVSS_1 \| ADC_CFGR2_OVSS_0) /!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data) /
EricLew	0:80ee8f3b695e	998	#define LL_ADC_OVS_DATA_SHIFT_4 ( ADC_CFGR2_OVSS_2 ) /!< ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data) /
EricLew	0:80ee8f3b695e	999	#define LL_ADC_OVS_DATA_SHIFT_5 ( ADC_CFGR2_OVSS_2 \| ADC_CFGR2_OVSS_0) /!< ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data) /
EricLew	0:80ee8f3b695e	1000	#define LL_ADC_OVS_DATA_SHIFT_6 ( ADC_CFGR2_OVSS_2 \| ADC_CFGR2_OVSS_1 ) /!< ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data) /
EricLew	0:80ee8f3b695e	1001	#define LL_ADC_OVS_DATA_SHIFT_7 ( ADC_CFGR2_OVSS_2 \| ADC_CFGR2_OVSS_1 \| ADC_CFGR2_OVSS_0) /!< ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data) /
EricLew	0:80ee8f3b695e	1002	#define LL_ADC_OVS_DATA_SHIFT_8 (ADC_CFGR2_OVSS_3 ) /!< ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data) /
EricLew	0:80ee8f3b695e	1003	/**
EricLew	0:80ee8f3b695e	1004	* @}
EricLew	0:80ee8f3b695e	1005	*/
EricLew	0:80ee8f3b695e	1006
EricLew	0:80ee8f3b695e	1007	#if defined(ADC2)
EricLew	0:80ee8f3b695e	1008	/** @defgroup ADC_LL_EC_MULTI Multimode - Mode
EricLew	0:80ee8f3b695e	1009	* @{
EricLew	0:80ee8f3b695e	1010	*/
EricLew	0:80ee8f3b695e	1011	#define LL_ADC_MULTI_INDEPENDENT ((uint32_t)0x00000000) /!< ADC dual mode disabled (ADC independent mode) /
EricLew	0:80ee8f3b695e	1012	#define LL_ADC_MULTI_DUAL_REG_SIMULT ( ADC_CCR_DUAL_2 \| ADC_CCR_DUAL_1 ) /!< ADC dual mode enabled: group regular simultaneous /
EricLew	0:80ee8f3b695e	1013	#define LL_ADC_MULTI_DUAL_REG_INTERL ( ADC_CCR_DUAL_2 \| ADC_CCR_DUAL_1 \| ADC_CCR_DUAL_0) /!< ADC dual mode enabled: Combined group regular interleaved /
EricLew	0:80ee8f3b695e	1014	#define LL_ADC_MULTI_DUAL_INJ_SIMULT ( ADC_CCR_DUAL_2 \| ADC_CCR_DUAL_0) /!< ADC dual mode enabled: group injected simultaneous /
EricLew	0:80ee8f3b695e	1015	#define LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CCR_DUAL_3 \| ADC_CCR_DUAL_0) /!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) /
EricLew	0:80ee8f3b695e	1016	#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM ( ADC_CCR_DUAL_0) /!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous /
EricLew	0:80ee8f3b695e	1017	#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT ( ADC_CCR_DUAL_1 ) /!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger /
EricLew	0:80ee8f3b695e	1018	#define LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM ( ADC_CCR_DUAL_1 \| ADC_CCR_DUAL_0) /!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous /
EricLew	0:80ee8f3b695e	1019	/**
EricLew	0:80ee8f3b695e	1020	* @}
EricLew	0:80ee8f3b695e	1021	*/
EricLew	0:80ee8f3b695e	1022
EricLew	0:80ee8f3b695e	1023	/** @defgroup ADC_LL_EC_MULTI_DMA_TRANSFER Multimode - DMA transfer
EricLew	0:80ee8f3b695e	1024	* @{
EricLew	0:80ee8f3b695e	1025	*/
EricLew	0:80ee8f3b695e	1026	#define LL_ADC_MULTI_REG_DMA_EACH_ADC ((uint32_t)0x00000000) /!< ADC multimode group regular conversions are transferred by DMA: each ADC uses its own DMA channel, with its individual DMA transfer settings /
EricLew	0:80ee8f3b695e	1027	#define LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B ( ADC_CCR_MDMA_1 ) /!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting for ADC resolution of 12 and 10 bits /
EricLew	0:80ee8f3b695e	1028	#define LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B ( ADC_CCR_MDMA_1 \| ADC_CCR_MDMA_0) /!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting for ADC resolution of 8 and 6 bits /
EricLew	0:80ee8f3b695e	1029	#define LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B (ADC_CCR_DMACFG \| ADC_CCR_MDMA_1 ) /!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. Setting for ADC resolution of 12 and 10 bits /
EricLew	0:80ee8f3b695e	1030	#define LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B (ADC_CCR_DMACFG \| ADC_CCR_MDMA_1 \| ADC_CCR_MDMA_0) /!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. Setting for ADC resolution of 8 and 6 bits /
EricLew	0:80ee8f3b695e	1031	/**
EricLew	0:80ee8f3b695e	1032	* @}
EricLew	0:80ee8f3b695e	1033	*/
EricLew	0:80ee8f3b695e	1034
EricLew	0:80ee8f3b695e	1035	/** @defgroup ADC_LL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases
EricLew	0:80ee8f3b695e	1036	* @{
EricLew	0:80ee8f3b695e	1037	*/
EricLew	0:80ee8f3b695e	1038	#define LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE ((uint32_t)0x00000000) /!< ADC multimode delay between two sampling phases: 1 ADC clock cycle /
EricLew	0:80ee8f3b695e	1039	#define LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES ( ADC_CCR_DELAY_0) /!< ADC multimode delay between two sampling phases: 2 ADC clock cycles /
EricLew	0:80ee8f3b695e	1040	#define LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES ( ADC_CCR_DELAY_1 ) /!< ADC multimode delay between two sampling phases: 3 ADC clock cycles /
EricLew	0:80ee8f3b695e	1041	#define LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES ( ADC_CCR_DELAY_1 \| ADC_CCR_DELAY_0) /!< ADC multimode delay between two sampling phases: 4 ADC clock cycles /
EricLew	0:80ee8f3b695e	1042	#define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES ( ADC_CCR_DELAY_2 ) /!< ADC multimode delay between two sampling phases: 5 ADC clock cycles /
EricLew	0:80ee8f3b695e	1043	#define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES ( ADC_CCR_DELAY_2 \| ADC_CCR_DELAY_0) /!< ADC multimode delay between two sampling phases: 6 ADC clock cycles /
EricLew	0:80ee8f3b695e	1044	#define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES ( ADC_CCR_DELAY_2 \| ADC_CCR_DELAY_1 ) /!< ADC multimode delay between two sampling phases: 7 ADC clock cycles /
EricLew	0:80ee8f3b695e	1045	#define LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES ( ADC_CCR_DELAY_2 \| ADC_CCR_DELAY_1 \| ADC_CCR_DELAY_0) /!< ADC multimode delay between two sampling phases: 8 ADC clock cycles /
EricLew	0:80ee8f3b695e	1046	#define LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (ADC_CCR_DELAY_3 ) /!< ADC multimode delay between two sampling phases: 9 ADC clock cycles /
EricLew	0:80ee8f3b695e	1047	#define LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (ADC_CCR_DELAY_3 \| ADC_CCR_DELAY_0) /!< ADC multimode delay between two sampling phases: 10 ADC clock cycles /
EricLew	0:80ee8f3b695e	1048	#define LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (ADC_CCR_DELAY_3 \| ADC_CCR_DELAY_1 ) /!< ADC multimode delay between two sampling phases: 11 ADC clock cycles /
EricLew	0:80ee8f3b695e	1049	#define LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (ADC_CCR_DELAY_3 \| ADC_CCR_DELAY_1 \| ADC_CCR_DELAY_0) /!< ADC multimode delay between two sampling phases: 12 ADC clock cycles /
EricLew	0:80ee8f3b695e	1050	/**
EricLew	0:80ee8f3b695e	1051	* @}
EricLew	0:80ee8f3b695e	1052	*/
EricLew	0:80ee8f3b695e	1053
EricLew	0:80ee8f3b695e	1054	/** @defgroup ADC_LL_EC_MULTI_CONV_DATA Multimode - ADC master or slave
EricLew	0:80ee8f3b695e	1055	* @{
EricLew	0:80ee8f3b695e	1056	*/
EricLew	0:80ee8f3b695e	1057	#define LL_ADC_MULTI_MASTER ( ADC_CDR_RDATA_MST) /!< In multimode, selection among several ADC instances: ADC master /
EricLew	0:80ee8f3b695e	1058	#define LL_ADC_MULTI_SLAVE (ADC_CDR_RDATA_SLV ) /!< In multimode, selection among several ADC instances: ADC slave /
EricLew	0:80ee8f3b695e	1059	#define LL_ADC_MULTI_MASTER_SLAVE (ADC_CDR_RDATA_SLV \| ADC_CDR_RDATA_MST) /!< In multimode, selection among several ADC instances: both ADC master and ADC slave /
EricLew	0:80ee8f3b695e	1060	/**
EricLew	0:80ee8f3b695e	1061	* @}
EricLew	0:80ee8f3b695e	1062	*/
EricLew	0:80ee8f3b695e	1063
EricLew	0:80ee8f3b695e	1064	#endif /* ADC2 */
EricLew	0:80ee8f3b695e	1065
EricLew	0:80ee8f3b695e	1066	/**
EricLew	0:80ee8f3b695e	1067	* @}
EricLew	0:80ee8f3b695e	1068	*/
EricLew	0:80ee8f3b695e	1069
EricLew	0:80ee8f3b695e	1070
EricLew	0:80ee8f3b695e	1071	/* Exported macro ------------------------------------------------------------*/
EricLew	0:80ee8f3b695e	1072	/** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
EricLew	0:80ee8f3b695e	1073	* @{
EricLew	0:80ee8f3b695e	1074	*/
EricLew	0:80ee8f3b695e	1075
EricLew	0:80ee8f3b695e	1076	/** @defgroup ADC_LL_EM_WRITE_READ Common Write and read registers Macros
EricLew	0:80ee8f3b695e	1077	* @{
EricLew	0:80ee8f3b695e	1078	*/
EricLew	0:80ee8f3b695e	1079
EricLew	0:80ee8f3b695e	1080	/**
EricLew	0:80ee8f3b695e	1081	* @brief Write a value in ADC register
EricLew	0:80ee8f3b695e	1082	* @param __INSTANCE__ ADC Instance
EricLew	0:80ee8f3b695e	1083	* @param __REG__ Register to be written
EricLew	0:80ee8f3b695e	1084	* @param __VALUE__ Value to be written in the register
EricLew	0:80ee8f3b695e	1085	* @retval None
EricLew	0:80ee8f3b695e	1086	*/
EricLew	0:80ee8f3b695e	1087	#define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
EricLew	0:80ee8f3b695e	1088
EricLew	0:80ee8f3b695e	1089	/**
EricLew	0:80ee8f3b695e	1090	* @brief Read a value in ADC register
EricLew	0:80ee8f3b695e	1091	* @param __INSTANCE__ ADC Instance
EricLew	0:80ee8f3b695e	1092	* @param __REG__ Register to be read
EricLew	0:80ee8f3b695e	1093	* @retval Register value
EricLew	0:80ee8f3b695e	1094	*/
EricLew	0:80ee8f3b695e	1095	#define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
EricLew	0:80ee8f3b695e	1096	/**
EricLew	0:80ee8f3b695e	1097	* @}
EricLew	0:80ee8f3b695e	1098	*/
EricLew	0:80ee8f3b695e	1099
EricLew	0:80ee8f3b695e	1100	/** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
EricLew	0:80ee8f3b695e	1101	* @{
EricLew	0:80ee8f3b695e	1102	*/
EricLew	0:80ee8f3b695e	1103
EricLew	0:80ee8f3b695e	1104	/**
EricLew	0:80ee8f3b695e	1105	* @brief Helper macro to get ADC channel number in decimal format
EricLew	0:80ee8f3b695e	1106	* from literals LL_ADC_CHANNEL_x.
EricLew	0:80ee8f3b695e	1107	* @note Example:
EricLew	0:80ee8f3b695e	1108	* __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
EricLew	0:80ee8f3b695e	1109	* will return decimal number "4".
EricLew	0:80ee8f3b695e	1110	* @note The input can be a value from functions where a channel
EricLew	0:80ee8f3b695e	1111	* number is returned, either defined with number
EricLew	0:80ee8f3b695e	1112	* or with bitfield (only one bit must be set).
EricLew	0:80ee8f3b695e	1113	* @param __CHANNEL__ This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1114	* @arg @ref LL_ADC_CHANNEL_0
EricLew	0:80ee8f3b695e	1115	* @arg @ref LL_ADC_CHANNEL_1 (5)
EricLew	0:80ee8f3b695e	1116	* @arg @ref LL_ADC_CHANNEL_2 (5)
EricLew	0:80ee8f3b695e	1117	* @arg @ref LL_ADC_CHANNEL_3 (5)
EricLew	0:80ee8f3b695e	1118	* @arg @ref LL_ADC_CHANNEL_4 (5)
EricLew	0:80ee8f3b695e	1119	* @arg @ref LL_ADC_CHANNEL_5 (5)
EricLew	0:80ee8f3b695e	1120	* @arg @ref LL_ADC_CHANNEL_6
EricLew	0:80ee8f3b695e	1121	* @arg @ref LL_ADC_CHANNEL_7
EricLew	0:80ee8f3b695e	1122	* @arg @ref LL_ADC_CHANNEL_8
EricLew	0:80ee8f3b695e	1123	* @arg @ref LL_ADC_CHANNEL_9
EricLew	0:80ee8f3b695e	1124	* @arg @ref LL_ADC_CHANNEL_10
EricLew	0:80ee8f3b695e	1125	* @arg @ref LL_ADC_CHANNEL_11
EricLew	0:80ee8f3b695e	1126	* @arg @ref LL_ADC_CHANNEL_12
EricLew	0:80ee8f3b695e	1127	* @arg @ref LL_ADC_CHANNEL_13
EricLew	0:80ee8f3b695e	1128	* @arg @ref LL_ADC_CHANNEL_14
EricLew	0:80ee8f3b695e	1129	* @arg @ref LL_ADC_CHANNEL_15
EricLew	0:80ee8f3b695e	1130	* @arg @ref LL_ADC_CHANNEL_16
EricLew	0:80ee8f3b695e	1131	* @arg @ref LL_ADC_CHANNEL_17
EricLew	0:80ee8f3b695e	1132	* @arg @ref LL_ADC_CHANNEL_18
EricLew	0:80ee8f3b695e	1133	* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
EricLew	0:80ee8f3b695e	1134	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
EricLew	0:80ee8f3b695e	1135	* @arg @ref LL_ADC_CHANNEL_VBAT (4)
EricLew	0:80ee8f3b695e	1136	* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
EricLew	0:80ee8f3b695e	1137	* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
EricLew	0:80ee8f3b695e	1138	* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)
EricLew	0:80ee8f3b695e	1139	* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)
EricLew	0:80ee8f3b695e	1140	* (1) On STM32L4, parameter available only on ADC instance: ADC1.
EricLew	0:80ee8f3b695e	1141	* (2) On STM32L4, parameter available only on ADC instance: ADC2.
EricLew	0:80ee8f3b695e	1142	* (3) On STM32L4, parameter available only on ADC instance: ADC3.
EricLew	0:80ee8f3b695e	1143	* (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.
EricLew	0:80ee8f3b695e	1144	* (5) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
EricLew	0:80ee8f3b695e	1145	* Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
EricLew	0:80ee8f3b695e	1146	* @retval 0...18
EricLew	0:80ee8f3b695e	1147	*/
EricLew	0:80ee8f3b695e	1148	#define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
EricLew	0:80ee8f3b695e	1149	((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) != 0) \
EricLew	0:80ee8f3b695e	1150	? ( \
EricLew	0:80ee8f3b695e	1151	POSITION_VAL((__CHANNEL__)) \
EricLew	0:80ee8f3b695e	1152	) \
EricLew	0:80ee8f3b695e	1153	: \
EricLew	0:80ee8f3b695e	1154	( \
EricLew	0:80ee8f3b695e	1155	((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) \
EricLew	0:80ee8f3b695e	1156	) \
EricLew	0:80ee8f3b695e	1157	)
EricLew	0:80ee8f3b695e	1158
EricLew	0:80ee8f3b695e	1159	/**
EricLew	0:80ee8f3b695e	1160	* @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
EricLew	0:80ee8f3b695e	1161	* from number in decimal format.
EricLew	0:80ee8f3b695e	1162	* @note Example:
EricLew	0:80ee8f3b695e	1163	* __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
EricLew	0:80ee8f3b695e	1164	* will return a data equivalent to "LL_ADC_CHANNEL_4".
EricLew	0:80ee8f3b695e	1165	* @param __DECIMAL_NB__: 0...18
EricLew	0:80ee8f3b695e	1166	* @retval Returned value can be one of the following values:
EricLew	0:80ee8f3b695e	1167	* @arg @ref LL_ADC_CHANNEL_0
EricLew	0:80ee8f3b695e	1168	* @arg @ref LL_ADC_CHANNEL_1 (5)
EricLew	0:80ee8f3b695e	1169	* @arg @ref LL_ADC_CHANNEL_2 (5)
EricLew	0:80ee8f3b695e	1170	* @arg @ref LL_ADC_CHANNEL_3 (5)
EricLew	0:80ee8f3b695e	1171	* @arg @ref LL_ADC_CHANNEL_4 (5)
EricLew	0:80ee8f3b695e	1172	* @arg @ref LL_ADC_CHANNEL_5 (5)
EricLew	0:80ee8f3b695e	1173	* @arg @ref LL_ADC_CHANNEL_6
EricLew	0:80ee8f3b695e	1174	* @arg @ref LL_ADC_CHANNEL_7
EricLew	0:80ee8f3b695e	1175	* @arg @ref LL_ADC_CHANNEL_8
EricLew	0:80ee8f3b695e	1176	* @arg @ref LL_ADC_CHANNEL_9
EricLew	0:80ee8f3b695e	1177	* @arg @ref LL_ADC_CHANNEL_10
EricLew	0:80ee8f3b695e	1178	* @arg @ref LL_ADC_CHANNEL_11
EricLew	0:80ee8f3b695e	1179	* @arg @ref LL_ADC_CHANNEL_12
EricLew	0:80ee8f3b695e	1180	* @arg @ref LL_ADC_CHANNEL_13
EricLew	0:80ee8f3b695e	1181	* @arg @ref LL_ADC_CHANNEL_14
EricLew	0:80ee8f3b695e	1182	* @arg @ref LL_ADC_CHANNEL_15
EricLew	0:80ee8f3b695e	1183	* @arg @ref LL_ADC_CHANNEL_16
EricLew	0:80ee8f3b695e	1184	* @arg @ref LL_ADC_CHANNEL_17
EricLew	0:80ee8f3b695e	1185	* @arg @ref LL_ADC_CHANNEL_18
EricLew	0:80ee8f3b695e	1186	* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
EricLew	0:80ee8f3b695e	1187	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
EricLew	0:80ee8f3b695e	1188	* @arg @ref LL_ADC_CHANNEL_VBAT (4)
EricLew	0:80ee8f3b695e	1189	* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
EricLew	0:80ee8f3b695e	1190	* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
EricLew	0:80ee8f3b695e	1191	* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)
EricLew	0:80ee8f3b695e	1192	* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)
EricLew	0:80ee8f3b695e	1193	* (1) On STM32L4, parameter available only on ADC instance: ADC1.
EricLew	0:80ee8f3b695e	1194	* (2) On STM32L4, parameter available only on ADC instance: ADC2.
EricLew	0:80ee8f3b695e	1195	* (3) On STM32L4, parameter available only on ADC instance: ADC3.
EricLew	0:80ee8f3b695e	1196	* (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.
EricLew	0:80ee8f3b695e	1197	* (5) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
EricLew	0:80ee8f3b695e	1198	* Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
EricLew	0:80ee8f3b695e	1199	* (1, 2, 3, 4) For ADC channel read back from ADC register,
EricLew	0:80ee8f3b695e	1200	* comparison with internal channel parameter to be done
EricLew	0:80ee8f3b695e	1201	* using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
EricLew	0:80ee8f3b695e	1202	*/
EricLew	0:80ee8f3b695e	1203	#define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
EricLew	0:80ee8f3b695e	1204	(((__DECIMAL_NB__) <= 9) \
EricLew	0:80ee8f3b695e	1205	? ( \
EricLew	0:80ee8f3b695e	1206	((__DECIMAL_NB__) << POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK)) \| \
EricLew	0:80ee8f3b695e	1207	(ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) \| \
EricLew	0:80ee8f3b695e	1208	(ADC_SMPR1_REGOFFSET \| (((uint32_t) (3 * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
EricLew	0:80ee8f3b695e	1209	) \
EricLew	0:80ee8f3b695e	1210	: \
EricLew	0:80ee8f3b695e	1211	( \
EricLew	0:80ee8f3b695e	1212	((__DECIMAL_NB__) << POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK)) \| \
EricLew	0:80ee8f3b695e	1213	(ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) \| \
EricLew	0:80ee8f3b695e	1214	(ADC_SMPR2_REGOFFSET \| (((uint32_t) (3 * ((__DECIMAL_NB__) - 10))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
EricLew	0:80ee8f3b695e	1215	) \
EricLew	0:80ee8f3b695e	1216	)
EricLew	0:80ee8f3b695e	1217
EricLew	0:80ee8f3b695e	1218	/**
EricLew	0:80ee8f3b695e	1219	* @brief Helper macro to determine whether the channel corresponds to
EricLew	0:80ee8f3b695e	1220	* parameters definitions of driver:
EricLew	0:80ee8f3b695e	1221	* * Parameter definition of a ADC internal channel
EricLew	0:80ee8f3b695e	1222	* (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...)
EricLew	0:80ee8f3b695e	1223	* * Parameter definition of a ADC external channel (channel connected
EricLew	0:80ee8f3b695e	1224	* to a GPIO pin) (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
EricLew	0:80ee8f3b695e	1225	* @note The channel parameter must be a value defined from parameter
EricLew	0:80ee8f3b695e	1226	* definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
EricLew	0:80ee8f3b695e	1227	* LL_ADC_CHANNEL_TEMPSENSOR, ...),
EricLew	0:80ee8f3b695e	1228	* ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
EricLew	0:80ee8f3b695e	1229	* must not be a value from functions where a channel number is
EricLew	0:80ee8f3b695e	1230	* returned from ADC registers,
EricLew	0:80ee8f3b695e	1231	* because internal and external channels share the same channel
EricLew	0:80ee8f3b695e	1232	* number in ADC registers. The differentiation is made only with
EricLew	0:80ee8f3b695e	1233	* parameters definitions of driver.
EricLew	0:80ee8f3b695e	1234	* @param __CHANNEL__ This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1235	* @arg @ref LL_ADC_CHANNEL_0
EricLew	0:80ee8f3b695e	1236	* @arg @ref LL_ADC_CHANNEL_1 (5)
EricLew	0:80ee8f3b695e	1237	* @arg @ref LL_ADC_CHANNEL_2 (5)
EricLew	0:80ee8f3b695e	1238	* @arg @ref LL_ADC_CHANNEL_3 (5)
EricLew	0:80ee8f3b695e	1239	* @arg @ref LL_ADC_CHANNEL_4 (5)
EricLew	0:80ee8f3b695e	1240	* @arg @ref LL_ADC_CHANNEL_5 (5)
EricLew	0:80ee8f3b695e	1241	* @arg @ref LL_ADC_CHANNEL_6
EricLew	0:80ee8f3b695e	1242	* @arg @ref LL_ADC_CHANNEL_7
EricLew	0:80ee8f3b695e	1243	* @arg @ref LL_ADC_CHANNEL_8
EricLew	0:80ee8f3b695e	1244	* @arg @ref LL_ADC_CHANNEL_9
EricLew	0:80ee8f3b695e	1245	* @arg @ref LL_ADC_CHANNEL_10
EricLew	0:80ee8f3b695e	1246	* @arg @ref LL_ADC_CHANNEL_11
EricLew	0:80ee8f3b695e	1247	* @arg @ref LL_ADC_CHANNEL_12
EricLew	0:80ee8f3b695e	1248	* @arg @ref LL_ADC_CHANNEL_13
EricLew	0:80ee8f3b695e	1249	* @arg @ref LL_ADC_CHANNEL_14
EricLew	0:80ee8f3b695e	1250	* @arg @ref LL_ADC_CHANNEL_15
EricLew	0:80ee8f3b695e	1251	* @arg @ref LL_ADC_CHANNEL_16
EricLew	0:80ee8f3b695e	1252	* @arg @ref LL_ADC_CHANNEL_17
EricLew	0:80ee8f3b695e	1253	* @arg @ref LL_ADC_CHANNEL_18
EricLew	0:80ee8f3b695e	1254	* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
EricLew	0:80ee8f3b695e	1255	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
EricLew	0:80ee8f3b695e	1256	* @arg @ref LL_ADC_CHANNEL_VBAT (4)
EricLew	0:80ee8f3b695e	1257	* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
EricLew	0:80ee8f3b695e	1258	* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
EricLew	0:80ee8f3b695e	1259	* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)
EricLew	0:80ee8f3b695e	1260	* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)
EricLew	0:80ee8f3b695e	1261	* (1) On STM32L4, parameter available only on ADC instance: ADC1.
EricLew	0:80ee8f3b695e	1262	* (2) On STM32L4, parameter available only on ADC instance: ADC2.
EricLew	0:80ee8f3b695e	1263	* (3) On STM32L4, parameter available only on ADC instance: ADC3.
EricLew	0:80ee8f3b695e	1264	* (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.
EricLew	0:80ee8f3b695e	1265	* (5) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
EricLew	0:80ee8f3b695e	1266	* Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
EricLew	0:80ee8f3b695e	1267	* @retval 0 if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin)
EricLew	0:80ee8f3b695e	1268	* 1 if the channel corresponds to a parameter definition of a ADC internal channel
EricLew	0:80ee8f3b695e	1269	*/
EricLew	0:80ee8f3b695e	1270	#define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
EricLew	0:80ee8f3b695e	1271	(((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0)
EricLew	0:80ee8f3b695e	1272
EricLew	0:80ee8f3b695e	1273	/**
EricLew	0:80ee8f3b695e	1274	* @brief Helper macro to convert a channel defined from parameter
EricLew	0:80ee8f3b695e	1275	* definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
EricLew	0:80ee8f3b695e	1276	* LL_ADC_CHANNEL_TEMPSENSOR, ...),
EricLew	0:80ee8f3b695e	1277	* to its equivalent parameter definition of a ADC external channel
EricLew	0:80ee8f3b695e	1278	* (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
EricLew	0:80ee8f3b695e	1279	* @note The channel parameter can be, additionally to a value
EricLew	0:80ee8f3b695e	1280	* defined from parameter definition of a ADC internal channel
EricLew	0:80ee8f3b695e	1281	* (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),
EricLew	0:80ee8f3b695e	1282	* a value defined from parameter definition of
EricLew	0:80ee8f3b695e	1283	* ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
EricLew	0:80ee8f3b695e	1284	* or a value from functions where a channel number is returned
EricLew	0:80ee8f3b695e	1285	* from ADC registers.
EricLew	0:80ee8f3b695e	1286	* @param __CHANNEL__ This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1287	* @arg @ref LL_ADC_CHANNEL_0
EricLew	0:80ee8f3b695e	1288	* @arg @ref LL_ADC_CHANNEL_1 (5)
EricLew	0:80ee8f3b695e	1289	* @arg @ref LL_ADC_CHANNEL_2 (5)
EricLew	0:80ee8f3b695e	1290	* @arg @ref LL_ADC_CHANNEL_3 (5)
EricLew	0:80ee8f3b695e	1291	* @arg @ref LL_ADC_CHANNEL_4 (5)
EricLew	0:80ee8f3b695e	1292	* @arg @ref LL_ADC_CHANNEL_5 (5)
EricLew	0:80ee8f3b695e	1293	* @arg @ref LL_ADC_CHANNEL_6
EricLew	0:80ee8f3b695e	1294	* @arg @ref LL_ADC_CHANNEL_7
EricLew	0:80ee8f3b695e	1295	* @arg @ref LL_ADC_CHANNEL_8
EricLew	0:80ee8f3b695e	1296	* @arg @ref LL_ADC_CHANNEL_9
EricLew	0:80ee8f3b695e	1297	* @arg @ref LL_ADC_CHANNEL_10
EricLew	0:80ee8f3b695e	1298	* @arg @ref LL_ADC_CHANNEL_11
EricLew	0:80ee8f3b695e	1299	* @arg @ref LL_ADC_CHANNEL_12
EricLew	0:80ee8f3b695e	1300	* @arg @ref LL_ADC_CHANNEL_13
EricLew	0:80ee8f3b695e	1301	* @arg @ref LL_ADC_CHANNEL_14
EricLew	0:80ee8f3b695e	1302	* @arg @ref LL_ADC_CHANNEL_15
EricLew	0:80ee8f3b695e	1303	* @arg @ref LL_ADC_CHANNEL_16
EricLew	0:80ee8f3b695e	1304	* @arg @ref LL_ADC_CHANNEL_17
EricLew	0:80ee8f3b695e	1305	* @arg @ref LL_ADC_CHANNEL_18
EricLew	0:80ee8f3b695e	1306	* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
EricLew	0:80ee8f3b695e	1307	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
EricLew	0:80ee8f3b695e	1308	* @arg @ref LL_ADC_CHANNEL_VBAT (4)
EricLew	0:80ee8f3b695e	1309	* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
EricLew	0:80ee8f3b695e	1310	* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
EricLew	0:80ee8f3b695e	1311	* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)
EricLew	0:80ee8f3b695e	1312	* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)
EricLew	0:80ee8f3b695e	1313	* (1) On STM32L4, parameter available only on ADC instance: ADC1.
EricLew	0:80ee8f3b695e	1314	* (2) On STM32L4, parameter available only on ADC instance: ADC2.
EricLew	0:80ee8f3b695e	1315	* (3) On STM32L4, parameter available only on ADC instance: ADC3.
EricLew	0:80ee8f3b695e	1316	* (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.
EricLew	0:80ee8f3b695e	1317	* (5) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
EricLew	0:80ee8f3b695e	1318	* Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
EricLew	0:80ee8f3b695e	1319	* @retval Returned value can be one of the following values:
EricLew	0:80ee8f3b695e	1320	* @arg @ref LL_ADC_CHANNEL_0
EricLew	0:80ee8f3b695e	1321	* @arg @ref LL_ADC_CHANNEL_1
EricLew	0:80ee8f3b695e	1322	* @arg @ref LL_ADC_CHANNEL_2
EricLew	0:80ee8f3b695e	1323	* @arg @ref LL_ADC_CHANNEL_3
EricLew	0:80ee8f3b695e	1324	* @arg @ref LL_ADC_CHANNEL_4
EricLew	0:80ee8f3b695e	1325	* @arg @ref LL_ADC_CHANNEL_5
EricLew	0:80ee8f3b695e	1326	* @arg @ref LL_ADC_CHANNEL_6
EricLew	0:80ee8f3b695e	1327	* @arg @ref LL_ADC_CHANNEL_7
EricLew	0:80ee8f3b695e	1328	* @arg @ref LL_ADC_CHANNEL_8
EricLew	0:80ee8f3b695e	1329	* @arg @ref LL_ADC_CHANNEL_9
EricLew	0:80ee8f3b695e	1330	* @arg @ref LL_ADC_CHANNEL_10
EricLew	0:80ee8f3b695e	1331	* @arg @ref LL_ADC_CHANNEL_11
EricLew	0:80ee8f3b695e	1332	* @arg @ref LL_ADC_CHANNEL_12
EricLew	0:80ee8f3b695e	1333	* @arg @ref LL_ADC_CHANNEL_13
EricLew	0:80ee8f3b695e	1334	* @arg @ref LL_ADC_CHANNEL_14
EricLew	0:80ee8f3b695e	1335	* @arg @ref LL_ADC_CHANNEL_15
EricLew	0:80ee8f3b695e	1336	* @arg @ref LL_ADC_CHANNEL_16
EricLew	0:80ee8f3b695e	1337	* @arg @ref LL_ADC_CHANNEL_17
EricLew	0:80ee8f3b695e	1338	* @arg @ref LL_ADC_CHANNEL_18
EricLew	0:80ee8f3b695e	1339	*/
EricLew	0:80ee8f3b695e	1340	#define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \
EricLew	0:80ee8f3b695e	1341	((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
EricLew	0:80ee8f3b695e	1342
EricLew	0:80ee8f3b695e	1343	/**
EricLew	0:80ee8f3b695e	1344	* @brief Helper macro to determine whether the internal channel
EricLew	0:80ee8f3b695e	1345	* selected is available on the ADC instance selected.
EricLew	0:80ee8f3b695e	1346	* @note The channel parameter must be a value defined from parameter
EricLew	0:80ee8f3b695e	1347	* definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
EricLew	0:80ee8f3b695e	1348	* LL_ADC_CHANNEL_TEMPSENSOR, ...),
EricLew	0:80ee8f3b695e	1349	* must not be a value defined from parameter definition of
EricLew	0:80ee8f3b695e	1350	* ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
EricLew	0:80ee8f3b695e	1351	* or a value from functions where a channel number is
EricLew	0:80ee8f3b695e	1352	* returned from ADC registers,
EricLew	0:80ee8f3b695e	1353	* because internal and external channels share the same channel
EricLew	0:80ee8f3b695e	1354	* number in ADC registers. The differentiation is made only with
EricLew	0:80ee8f3b695e	1355	* parameters definitions of driver.
EricLew	0:80ee8f3b695e	1356	* @param __ADC_INSTANCE__ ADC instance
EricLew	0:80ee8f3b695e	1357	* @param __CHANNEL__ This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1358	* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
EricLew	0:80ee8f3b695e	1359	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
EricLew	0:80ee8f3b695e	1360	* @arg @ref LL_ADC_CHANNEL_VBAT (4)
EricLew	0:80ee8f3b695e	1361	* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
EricLew	0:80ee8f3b695e	1362	* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
EricLew	0:80ee8f3b695e	1363	* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)
EricLew	0:80ee8f3b695e	1364	* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)
EricLew	0:80ee8f3b695e	1365	* (1) On STM32L4, parameter available only on ADC instance: ADC1.
EricLew	0:80ee8f3b695e	1366	* (2) On STM32L4, parameter available only on ADC instance: ADC2.
EricLew	0:80ee8f3b695e	1367	* (3) On STM32L4, parameter available only on ADC instance: ADC3.
EricLew	0:80ee8f3b695e	1368	* (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.
EricLew	0:80ee8f3b695e	1369	* @retval 0 if the internal channel selected is not available on the ADC instance selected.
EricLew	0:80ee8f3b695e	1370	* 1 if the internal channel selected is available on the ADC instance selected.
EricLew	0:80ee8f3b695e	1371	*/
EricLew	0:80ee8f3b695e	1372	#if defined (ADC1) && defined (ADC2) && defined (ADC3)
EricLew	0:80ee8f3b695e	1373	#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
EricLew	0:80ee8f3b695e	1374	(((__ADC_INSTANCE__) == ADC1) \
EricLew	0:80ee8f3b695e	1375	? ( \
EricLew	0:80ee8f3b695e	1376	((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \|\| \
EricLew	0:80ee8f3b695e	1377	((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) \|\| \
EricLew	0:80ee8f3b695e	1378	((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) \
EricLew	0:80ee8f3b695e	1379	) \
EricLew	0:80ee8f3b695e	1380	: \
EricLew	0:80ee8f3b695e	1381	((__ADC_INSTANCE__) == ADC2) \
EricLew	0:80ee8f3b695e	1382	? ( \
EricLew	0:80ee8f3b695e	1383	((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \|\| \
EricLew	0:80ee8f3b695e	1384	((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH1_ADC2) \|\| \
EricLew	0:80ee8f3b695e	1385	((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2_ADC2) \
EricLew	0:80ee8f3b695e	1386	) \
EricLew	0:80ee8f3b695e	1387	: \
EricLew	0:80ee8f3b695e	1388	((__ADC_INSTANCE__) == ADC3) \
EricLew	0:80ee8f3b695e	1389	? ( \
EricLew	0:80ee8f3b695e	1390	((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \|\| \
EricLew	0:80ee8f3b695e	1391	((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) \|\| \
EricLew	0:80ee8f3b695e	1392	((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) \|\| \
EricLew	0:80ee8f3b695e	1393	((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH1_ADC3) \|\| \
EricLew	0:80ee8f3b695e	1394	((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2_ADC3) \
EricLew	0:80ee8f3b695e	1395	) \
EricLew	0:80ee8f3b695e	1396	: \
EricLew	0:80ee8f3b695e	1397	(0) \
EricLew	0:80ee8f3b695e	1398	)
EricLew	0:80ee8f3b695e	1399	#elif defined (ADC1) && defined (ADC2)
EricLew	0:80ee8f3b695e	1400	#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
EricLew	0:80ee8f3b695e	1401	(((__ADC_INSTANCE__) == ADC1) \
EricLew	0:80ee8f3b695e	1402	? ( \
EricLew	0:80ee8f3b695e	1403	((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \|\| \
EricLew	0:80ee8f3b695e	1404	((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) \|\| \
EricLew	0:80ee8f3b695e	1405	((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) \
EricLew	0:80ee8f3b695e	1406	) \
EricLew	0:80ee8f3b695e	1407	: \
EricLew	0:80ee8f3b695e	1408	((__ADC_INSTANCE__) == ADC2) \
EricLew	0:80ee8f3b695e	1409	? ( \
EricLew	0:80ee8f3b695e	1410	((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \|\| \
EricLew	0:80ee8f3b695e	1411	((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH1_ADC2) \|\| \
EricLew	0:80ee8f3b695e	1412	((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2_ADC2) \
EricLew	0:80ee8f3b695e	1413	) \
EricLew	0:80ee8f3b695e	1414	: \
EricLew	0:80ee8f3b695e	1415	(0) \
EricLew	0:80ee8f3b695e	1416	)
EricLew	0:80ee8f3b695e	1417	#elif defined (ADC1)
EricLew	0:80ee8f3b695e	1418	#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
EricLew	0:80ee8f3b695e	1419	( \
EricLew	0:80ee8f3b695e	1420	((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \|\| \
EricLew	0:80ee8f3b695e	1421	((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) \|\| \
EricLew	0:80ee8f3b695e	1422	((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) \
EricLew	0:80ee8f3b695e	1423	)
EricLew	0:80ee8f3b695e	1424	#endif
EricLew	0:80ee8f3b695e	1425
EricLew	0:80ee8f3b695e	1426	/**
EricLew	0:80ee8f3b695e	1427	* @brief Helper macro to define ADC analog watchdog parameter:
EricLew	0:80ee8f3b695e	1428	* define a single channel to monitor with analog watchdog
EricLew	0:80ee8f3b695e	1429	* from sequencer channel and groups definition.
EricLew	0:80ee8f3b695e	1430	* @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
EricLew	0:80ee8f3b695e	1431	* Example:
EricLew	0:80ee8f3b695e	1432	* LL_ADC_SetAnalogWDMonitChannels(
EricLew	0:80ee8f3b695e	1433	* ADC1, LL_ADC_AWD1,
EricLew	0:80ee8f3b695e	1434	* __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_REGULAR_GROUP))
EricLew	0:80ee8f3b695e	1435	* @param __CHANNEL__ This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1436	* @arg @ref LL_ADC_CHANNEL_0
EricLew	0:80ee8f3b695e	1437	* @arg @ref LL_ADC_CHANNEL_1 (5)
EricLew	0:80ee8f3b695e	1438	* @arg @ref LL_ADC_CHANNEL_2 (5)
EricLew	0:80ee8f3b695e	1439	* @arg @ref LL_ADC_CHANNEL_3 (5)
EricLew	0:80ee8f3b695e	1440	* @arg @ref LL_ADC_CHANNEL_4 (5)
EricLew	0:80ee8f3b695e	1441	* @arg @ref LL_ADC_CHANNEL_5 (5)
EricLew	0:80ee8f3b695e	1442	* @arg @ref LL_ADC_CHANNEL_6
EricLew	0:80ee8f3b695e	1443	* @arg @ref LL_ADC_CHANNEL_7
EricLew	0:80ee8f3b695e	1444	* @arg @ref LL_ADC_CHANNEL_8
EricLew	0:80ee8f3b695e	1445	* @arg @ref LL_ADC_CHANNEL_9
EricLew	0:80ee8f3b695e	1446	* @arg @ref LL_ADC_CHANNEL_10
EricLew	0:80ee8f3b695e	1447	* @arg @ref LL_ADC_CHANNEL_11
EricLew	0:80ee8f3b695e	1448	* @arg @ref LL_ADC_CHANNEL_12
EricLew	0:80ee8f3b695e	1449	* @arg @ref LL_ADC_CHANNEL_13
EricLew	0:80ee8f3b695e	1450	* @arg @ref LL_ADC_CHANNEL_14
EricLew	0:80ee8f3b695e	1451	* @arg @ref LL_ADC_CHANNEL_15
EricLew	0:80ee8f3b695e	1452	* @arg @ref LL_ADC_CHANNEL_16
EricLew	0:80ee8f3b695e	1453	* @arg @ref LL_ADC_CHANNEL_17
EricLew	0:80ee8f3b695e	1454	* @arg @ref LL_ADC_CHANNEL_18
EricLew	0:80ee8f3b695e	1455	* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
EricLew	0:80ee8f3b695e	1456	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
EricLew	0:80ee8f3b695e	1457	* @arg @ref LL_ADC_CHANNEL_VBAT (4)
EricLew	0:80ee8f3b695e	1458	* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
EricLew	0:80ee8f3b695e	1459	* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
EricLew	0:80ee8f3b695e	1460	* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)
EricLew	0:80ee8f3b695e	1461	* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)
EricLew	0:80ee8f3b695e	1462	* (1) On STM32L4, parameter available only on ADC instance: ADC1.
EricLew	0:80ee8f3b695e	1463	* (2) On STM32L4, parameter available only on ADC instance: ADC2.
EricLew	0:80ee8f3b695e	1464	* (3) On STM32L4, parameter available only on ADC instance: ADC3.
EricLew	0:80ee8f3b695e	1465	* (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.
EricLew	0:80ee8f3b695e	1466	* (5) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
EricLew	0:80ee8f3b695e	1467	* Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
EricLew	0:80ee8f3b695e	1468	* (1, 2, 3, 4) For ADC channel read back from ADC register,
EricLew	0:80ee8f3b695e	1469	* comparison with internal channel parameter to be done
EricLew	0:80ee8f3b695e	1470	* using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
EricLew	0:80ee8f3b695e	1471	* @param __GROUP__ This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1472	* @arg @ref LL_ADC_GROUP_REGULAR
EricLew	0:80ee8f3b695e	1473	* @arg @ref LL_ADC_GROUP_INJECTED
EricLew	0:80ee8f3b695e	1474	* @arg @ref LL_ADC_GROUP_REGULAR_INJECTED
EricLew	0:80ee8f3b695e	1475	* @retval Returned value can be one of the following values:
EricLew	0:80ee8f3b695e	1476	* @arg @ref LL_ADC_AWD_DISABLE
EricLew	0:80ee8f3b695e	1477	* @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
EricLew	0:80ee8f3b695e	1478	* @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
EricLew	0:80ee8f3b695e	1479	* @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
EricLew	0:80ee8f3b695e	1480	* @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
EricLew	0:80ee8f3b695e	1481	* @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
EricLew	0:80ee8f3b695e	1482	* @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
EricLew	0:80ee8f3b695e	1483	* @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
EricLew	0:80ee8f3b695e	1484	* @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
EricLew	0:80ee8f3b695e	1485	* @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
EricLew	0:80ee8f3b695e	1486	* @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
EricLew	0:80ee8f3b695e	1487	* @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
EricLew	0:80ee8f3b695e	1488	* @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
EricLew	0:80ee8f3b695e	1489	* @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
EricLew	0:80ee8f3b695e	1490	* @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
EricLew	0:80ee8f3b695e	1491	* @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
EricLew	0:80ee8f3b695e	1492	* @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
EricLew	0:80ee8f3b695e	1493	* @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
EricLew	0:80ee8f3b695e	1494	* @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
EricLew	0:80ee8f3b695e	1495	* @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
EricLew	0:80ee8f3b695e	1496	* @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
EricLew	0:80ee8f3b695e	1497	* @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
EricLew	0:80ee8f3b695e	1498	* @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
EricLew	0:80ee8f3b695e	1499	* @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
EricLew	0:80ee8f3b695e	1500	* @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
EricLew	0:80ee8f3b695e	1501	* @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
EricLew	0:80ee8f3b695e	1502	* @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
EricLew	0:80ee8f3b695e	1503	* @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
EricLew	0:80ee8f3b695e	1504	* @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
EricLew	0:80ee8f3b695e	1505	* @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
EricLew	0:80ee8f3b695e	1506	* @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
EricLew	0:80ee8f3b695e	1507	* @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
EricLew	0:80ee8f3b695e	1508	* @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
EricLew	0:80ee8f3b695e	1509	* @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
EricLew	0:80ee8f3b695e	1510	* @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
EricLew	0:80ee8f3b695e	1511	* @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
EricLew	0:80ee8f3b695e	1512	* @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
EricLew	0:80ee8f3b695e	1513	* @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
EricLew	0:80ee8f3b695e	1514	* @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
EricLew	0:80ee8f3b695e	1515	* @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
EricLew	0:80ee8f3b695e	1516	* @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
EricLew	0:80ee8f3b695e	1517	* @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
EricLew	0:80ee8f3b695e	1518	* @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
EricLew	0:80ee8f3b695e	1519	* @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
EricLew	0:80ee8f3b695e	1520	* @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
EricLew	0:80ee8f3b695e	1521	* @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
EricLew	0:80ee8f3b695e	1522	* @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
EricLew	0:80ee8f3b695e	1523	* @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
EricLew	0:80ee8f3b695e	1524	* @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
EricLew	0:80ee8f3b695e	1525	* @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
EricLew	0:80ee8f3b695e	1526	* @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
EricLew	0:80ee8f3b695e	1527	* @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
EricLew	0:80ee8f3b695e	1528	* @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
EricLew	0:80ee8f3b695e	1529	* @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
EricLew	0:80ee8f3b695e	1530	* @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
EricLew	0:80ee8f3b695e	1531	* @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
EricLew	0:80ee8f3b695e	1532	* @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
EricLew	0:80ee8f3b695e	1533	* @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
EricLew	0:80ee8f3b695e	1534	* @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
EricLew	0:80ee8f3b695e	1535	* @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
EricLew	0:80ee8f3b695e	1536	* @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
EricLew	0:80ee8f3b695e	1537	* @arg @ref LL_ADC_AWD_CH_VREFINT_REG (0)(1)
EricLew	0:80ee8f3b695e	1538	* @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (0)(1)
EricLew	0:80ee8f3b695e	1539	* @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
EricLew	0:80ee8f3b695e	1540	* @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (0)(4)
EricLew	0:80ee8f3b695e	1541	* @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (4)(4)
EricLew	0:80ee8f3b695e	1542	* @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (4)
EricLew	0:80ee8f3b695e	1543	* @arg @ref LL_ADC_AWD_CH_VBAT_REG (0)(4)
EricLew	0:80ee8f3b695e	1544	* @arg @ref LL_ADC_AWD_CH_VBAT_INJ (0)(4)
EricLew	0:80ee8f3b695e	1545	* @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (4)
EricLew	0:80ee8f3b695e	1546	* @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG (0)(2)
EricLew	0:80ee8f3b695e	1547	* @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ (0)(2)
EricLew	0:80ee8f3b695e	1548	* @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ (2)
EricLew	0:80ee8f3b695e	1549	* @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG (0)(2)
EricLew	0:80ee8f3b695e	1550	* @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ (0)(2)
EricLew	0:80ee8f3b695e	1551	* @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ (2)
EricLew	0:80ee8f3b695e	1552	* @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC3_REG (0)(3)
EricLew	0:80ee8f3b695e	1553	* @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC3_INJ (0)(3)
EricLew	0:80ee8f3b695e	1554	* @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC3_REG_INJ (3)
EricLew	0:80ee8f3b695e	1555	* @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC3_REG (0)(3)
EricLew	0:80ee8f3b695e	1556	* @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC3_INJ (0)(3)
EricLew	0:80ee8f3b695e	1557	* @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC3_REG_INJ (3)
EricLew	0:80ee8f3b695e	1558	* (0) On STM32L4, parameter available only on analog watchdog number: AWD1.
EricLew	0:80ee8f3b695e	1559	* (1) On STM32L4, parameter available only on ADC instance: ADC1.
EricLew	0:80ee8f3b695e	1560	* (2) On STM32L4, parameter available only on ADC instance: ADC2.
EricLew	0:80ee8f3b695e	1561	* (3) On STM32L4, parameter available only on ADC instance: ADC3.
EricLew	0:80ee8f3b695e	1562	* (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.
EricLew	0:80ee8f3b695e	1563	*/
EricLew	0:80ee8f3b695e	1564	#define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \
EricLew	0:80ee8f3b695e	1565	(((__GROUP__) == LL_ADC_GROUP_REGULAR) \
EricLew	0:80ee8f3b695e	1566	? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) \
EricLew	0:80ee8f3b695e	1567	: \
EricLew	0:80ee8f3b695e	1568	((__GROUP__) == LL_ADC_GROUP_INJECTED) \
EricLew	0:80ee8f3b695e	1569	? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1SGL) \
EricLew	0:80ee8f3b695e	1570	: \
EricLew	0:80ee8f3b695e	1571	(((__CHANNEL__) & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) \
EricLew	0:80ee8f3b695e	1572	)
EricLew	0:80ee8f3b695e	1573
EricLew	0:80ee8f3b695e	1574	/**
EricLew	0:80ee8f3b695e	1575	* @brief Helper macro to get the ADC analog watchdog threshold high
EricLew	0:80ee8f3b695e	1576	* or low from raw value with both thresholds concatenated.
EricLew	0:80ee8f3b695e	1577	* @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
EricLew	0:80ee8f3b695e	1578	* Example, to get analog watchdog threshold high from the register raw value:
EricLew	0:80ee8f3b695e	1579	* __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(LL_ADC_AWD_THRESHOLD_HIGH, <raw_value_with_both_thresholds>);
EricLew	0:80ee8f3b695e	1580	* @param __AWD_THRESHOLD_TYPE__ This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1581	* @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
EricLew	0:80ee8f3b695e	1582	* @arg @ref LL_ADC_AWD_THRESHOLD_LOW
EricLew	0:80ee8f3b695e	1583	* @param __AWD_THRESHOLDS__ For AWD1: 0x000...0xFFF, for AWD2, AWD3: 0x00...0xFF
EricLew	0:80ee8f3b695e	1584	* @retval 0x00000000...0xFFFFFFFF
EricLew	0:80ee8f3b695e	1585	*/
EricLew	0:80ee8f3b695e	1586	#define __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__) \
EricLew	0:80ee8f3b695e	1587	(((__AWD_THRESHOLDS__) >> POSITION_VAL((__AWD_THRESHOLD_TYPE__))) & LL_ADC_AWD_THRESHOLD_LOW)
EricLew	0:80ee8f3b695e	1588
EricLew	0:80ee8f3b695e	1589	/**
EricLew	0:80ee8f3b695e	1590	* @brief Helper macro to set the ADC calibration value with both single ended
EricLew	0:80ee8f3b695e	1591	* and differential modes calibration factors concatenated.
EricLew	0:80ee8f3b695e	1592	* @note To be used with function @ref LL_ADC_SetCalibrationFactor().
EricLew	0:80ee8f3b695e	1593	* Example, to set calibration factors single ended to 0x55
EricLew	0:80ee8f3b695e	1594	* and differential ended to 0x2A:
EricLew	0:80ee8f3b695e	1595	* LL_ADC_SetCalibrationFactor(
EricLew	0:80ee8f3b695e	1596	* ADC1,
EricLew	0:80ee8f3b695e	1597	* __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(0x55, 0x2A))
EricLew	0:80ee8f3b695e	1598	* @param __CALIB_FACTOR_SINGLE_ENDED__ 0x00...0x7F
EricLew	0:80ee8f3b695e	1599	* @param __CALIB_FACTOR_DIFFERENTIAL__ 0x00...0x7F
EricLew	0:80ee8f3b695e	1600	* @retval 0x00000000...0xFFFFFFFF
EricLew	0:80ee8f3b695e	1601	*/
EricLew	0:80ee8f3b695e	1602	#define __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(__CALIB_FACTOR_SINGLE_ENDED__, __CALIB_FACTOR_DIFFERENTIAL__) \
EricLew	0:80ee8f3b695e	1603	(((__CALIB_FACTOR_DIFFERENTIAL__) << POSITION_VAL(ADC_CALFACT_CALFACT_D)) \| (__CALIB_FACTOR_SINGLE_ENDED__))
EricLew	0:80ee8f3b695e	1604
EricLew	0:80ee8f3b695e	1605	#if defined(ADC2)
EricLew	0:80ee8f3b695e	1606	/**
EricLew	0:80ee8f3b695e	1607	* @brief Helper macro to get the ADC multimode conversion data of ADC master
EricLew	0:80ee8f3b695e	1608	* or ADC slave from raw value with both ADC conversion data concatenated.
EricLew	0:80ee8f3b695e	1609	* @note This macro is intended to be used when multimode transfer by DMA
EricLew	0:80ee8f3b695e	1610	* is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer().
EricLew	0:80ee8f3b695e	1611	* In this case the transferred data need to processed with this macro
EricLew	0:80ee8f3b695e	1612	* to separate the conversion data of ADC master and ADC slave.
EricLew	0:80ee8f3b695e	1613	* @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1614	* @arg @ref LL_ADC_MULTI_MASTER
EricLew	0:80ee8f3b695e	1615	* @arg @ref LL_ADC_MULTI_SLAVE
EricLew	0:80ee8f3b695e	1616	* @param __ADC_MULTI_CONV_DATA__ 0x000...0xFFF
EricLew	0:80ee8f3b695e	1617	* @retval 0x000...0xFFF
EricLew	0:80ee8f3b695e	1618	*/
EricLew	0:80ee8f3b695e	1619	#define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \
EricLew	0:80ee8f3b695e	1620	(((__ADC_MULTI_CONV_DATA__) >> POSITION_VAL((__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST)
EricLew	0:80ee8f3b695e	1621	#endif
EricLew	0:80ee8f3b695e	1622
EricLew	0:80ee8f3b695e	1623	/**
EricLew	0:80ee8f3b695e	1624	* @brief Helper macro to select the ADC common instance
EricLew	0:80ee8f3b695e	1625	* to which is belonging the selected ADC instance.
EricLew	0:80ee8f3b695e	1626	* @note ADC common register instance can be used for:
EricLew	0:80ee8f3b695e	1627	* * Set parameters common to several ADC instances
EricLew	0:80ee8f3b695e	1628	* * Multimode (for devices with several ADC instances)
EricLew	0:80ee8f3b695e	1629	* Refer to functions having argument "ADCxy_COMMON" as parameter.
EricLew	0:80ee8f3b695e	1630	* @param __ADCx__ ADC instance
EricLew	0:80ee8f3b695e	1631	* @retval ADC common register instance
EricLew	0:80ee8f3b695e	1632	*/
EricLew	0:80ee8f3b695e	1633	#if defined(ADC1) && defined(ADC2) && defined(ADC3)
EricLew	0:80ee8f3b695e	1634	#define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
EricLew	0:80ee8f3b695e	1635	(ADC123_COMMON)
EricLew	0:80ee8f3b695e	1636	#elif defined(ADC1) && defined(ADC2)
EricLew	0:80ee8f3b695e	1637	#define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
EricLew	0:80ee8f3b695e	1638	(ADC12_COMMON)
EricLew	0:80ee8f3b695e	1639	#else
EricLew	0:80ee8f3b695e	1640	#define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
EricLew	0:80ee8f3b695e	1641	(ADC1_COMMON)
EricLew	0:80ee8f3b695e	1642	#endif
EricLew	0:80ee8f3b695e	1643
EricLew	0:80ee8f3b695e	1644	/**
EricLew	0:80ee8f3b695e	1645	* @brief Helper macro to check if all ADC instances sharing the same
EricLew	0:80ee8f3b695e	1646	* ADC common instance are disabled.
EricLew	0:80ee8f3b695e	1647	* @note This check is required by functions with setting conditioned to
EricLew	0:80ee8f3b695e	1648	* ADC state:
EricLew	0:80ee8f3b695e	1649	* All ADC instances of the ADC common group must be disabled.
EricLew	0:80ee8f3b695e	1650	* Refer to functions having argument "ADCxy_COMMON" as parameter.
EricLew	0:80ee8f3b695e	1651	* @retval 0: All ADC instances sharing the same ADC common instance
EricLew	0:80ee8f3b695e	1652	* are disabled.
EricLew	0:80ee8f3b695e	1653	* 1: At least one ADC instance sharing the same ADC common instance
EricLew	0:80ee8f3b695e	1654	* is enabled
EricLew	0:80ee8f3b695e	1655	*/
EricLew	0:80ee8f3b695e	1656	#if defined(ADC1) && defined(ADC2) && defined(ADC3)
EricLew	0:80ee8f3b695e	1657	#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE() \
EricLew	0:80ee8f3b695e	1658	(LL_ADC_IsEnabled(ADC1) \| \
EricLew	0:80ee8f3b695e	1659	LL_ADC_IsEnabled(ADC2) \| \
EricLew	0:80ee8f3b695e	1660	LL_ADC_IsEnabled(ADC3) )
EricLew	0:80ee8f3b695e	1661	#elif defined(ADC1) && defined(ADC2)
EricLew	0:80ee8f3b695e	1662	#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE() \
EricLew	0:80ee8f3b695e	1663	(LL_ADC_IsEnabled(ADC1) \| \
EricLew	0:80ee8f3b695e	1664	LL_ADC_IsEnabled(ADC2) )
EricLew	0:80ee8f3b695e	1665	#else
EricLew	0:80ee8f3b695e	1666	#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE() \
EricLew	0:80ee8f3b695e	1667	LL_ADC_IsEnabled(ADC1)
EricLew	0:80ee8f3b695e	1668	#endif
EricLew	0:80ee8f3b695e	1669
EricLew	0:80ee8f3b695e	1670	/**
EricLew	0:80ee8f3b695e	1671	* @brief Helper macro to define the ADC conversion data full-scale digital
EricLew	0:80ee8f3b695e	1672	* value corresponding to the selected ADC resolution.
EricLew	0:80ee8f3b695e	1673	* @note ADC conversion data full-scale corresponds to voltage range
EricLew	0:80ee8f3b695e	1674	* determined by analog voltage references Vref+ and Vref-,
EricLew	0:80ee8f3b695e	1675	* refer to reference manual)
EricLew	0:80ee8f3b695e	1676	* @param __RESOLUTION__ This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1677	* @arg @ref LL_ADC_RESOLUTION_12B
EricLew	0:80ee8f3b695e	1678	* @arg @ref LL_ADC_RESOLUTION_10B
EricLew	0:80ee8f3b695e	1679	* @arg @ref LL_ADC_RESOLUTION_8B
EricLew	0:80ee8f3b695e	1680	* @arg @ref LL_ADC_RESOLUTION_6B
EricLew	0:80ee8f3b695e	1681	* @retval ADC conversion data equivalent voltage value (unit: mVolt)
EricLew	0:80ee8f3b695e	1682	*/
EricLew	0:80ee8f3b695e	1683	#define __LL_ADC_DIGITAL_SCALE(__RESOLUTION__) \
EricLew	0:80ee8f3b695e	1684	(((uint32_t)0xFFF) >> ((__RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1 )))
EricLew	0:80ee8f3b695e	1685
EricLew	0:80ee8f3b695e	1686	/**
EricLew	0:80ee8f3b695e	1687	* @brief Helper macro to calculate the voltage (unit: mVolt)
EricLew	0:80ee8f3b695e	1688	* corresponding to a ADC conversion data (unit: digital value).
EricLew	0:80ee8f3b695e	1689	* @note ADC measurement data must correspond to a resolution of 12bits
EricLew	0:80ee8f3b695e	1690	* (full scale digital value 4095). If not the case, the data must be
EricLew	0:80ee8f3b695e	1691	* preliminarily rescaled to an equivalent resolution of 12 bits.
EricLew	0:80ee8f3b695e	1692	* @note Analog reference voltage (Vref+) must be either known from
EricLew	0:80ee8f3b695e	1693	* user board environment or can be calculated using ADC measurement
EricLew	0:80ee8f3b695e	1694	* and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
EricLew	0:80ee8f3b695e	1695	* @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
EricLew	0:80ee8f3b695e	1696	* @param __ADC_DATA__ ADC conversion data (resolution 12 bits)
EricLew	0:80ee8f3b695e	1697	* (unit: digital value).
EricLew	0:80ee8f3b695e	1698	* @retval ADC conversion data equivalent voltage value (unit: mVolt)
EricLew	0:80ee8f3b695e	1699	*/
EricLew	0:80ee8f3b695e	1700	#define __LL_ADC_CALC_DATA_VOLTAGE(__VREFANALOG_VOLTAGE__, __ADC_DATA__) \
EricLew	0:80ee8f3b695e	1701	((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) / __LL_ADC_DIGITAL_SCALE(LL_ADC_RESOLUTION_12B))
EricLew	0:80ee8f3b695e	1702
EricLew	0:80ee8f3b695e	1703	/**
EricLew	0:80ee8f3b695e	1704	* @brief Helper macro to calculate analog reference voltage (Vref+)
EricLew	0:80ee8f3b695e	1705	* (unit: mVolt) from ADC conversion data of internal voltage
EricLew	0:80ee8f3b695e	1706	* reference VrefInt.
EricLew	0:80ee8f3b695e	1707	* Computation is using VrefInt calibration value
EricLew	0:80ee8f3b695e	1708	* stored in system memory for each device during production.
EricLew	0:80ee8f3b695e	1709	* @note This voltage depends on user board environment: voltage level
EricLew	0:80ee8f3b695e	1710	* connected to pin Vref+.
EricLew	0:80ee8f3b695e	1711	* On devices with small package, the pin Vref+ is not present
EricLew	0:80ee8f3b695e	1712	* and internally bonded to pin Vdda.
EricLew	0:80ee8f3b695e	1713	* @note ADC measurement data must correspond to a resolution of 12bits
EricLew	0:80ee8f3b695e	1714	* (full scale digital value 4095). If not the case, the data must be
EricLew	0:80ee8f3b695e	1715	* preliminarily rescaled to an equivalent resolution of 12 bits.
EricLew	0:80ee8f3b695e	1716	* @param __VREFINT_ADC_DATA__: ADC conversion data (resolution 12 bits)
EricLew	0:80ee8f3b695e	1717	* of internal voltage reference VrefInt (unit: digital value).
EricLew	0:80ee8f3b695e	1718	* @retval Analog reference voltage (unit: mV)
EricLew	0:80ee8f3b695e	1719	*/
EricLew	0:80ee8f3b695e	1720	#define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__) \
EricLew	0:80ee8f3b695e	1721	(((uint32_t)(VREFINT_CAL_ADDR) VREFINT_CAL_VREF) / (__VREFINT_ADC_DATA__))
EricLew	0:80ee8f3b695e	1722
EricLew	0:80ee8f3b695e	1723	/**
EricLew	0:80ee8f3b695e	1724	* @brief Helper macro to calculate the temperature (unit: degree Celsius)
EricLew	0:80ee8f3b695e	1725	* from ADC conversion data of internal temperature sensor.
EricLew	0:80ee8f3b695e	1726	* Computation is using temperature sensor calibration values
EricLew	0:80ee8f3b695e	1727	* stored in system memory for each device during production.
EricLew	0:80ee8f3b695e	1728	* @note Calculation formula:
EricLew	0:80ee8f3b695e	1729	* Temperature = ((TS_ADC_DATA - TS_CAL1)
EricLew	0:80ee8f3b695e	1730	* * (TS_CAL2_TEMP - TS_CAL1_TEMP))
EricLew	0:80ee8f3b695e	1731	* / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
EricLew	0:80ee8f3b695e	1732	* with TS_ADC_DATA = temperature sensor raw data measured by ADC
EricLew	0:80ee8f3b695e	1733	* Avg_Slope = (TS_CAL2 - TS_CAL1)
EricLew	0:80ee8f3b695e	1734	* / (TS_CAL2_TEMP - TS_CAL1_TEMP)
EricLew	0:80ee8f3b695e	1735	* TS_CAL1 = equivalent TS_ADC_DATA at temperature
EricLew	0:80ee8f3b695e	1736	* TEMP_DEGC_CAL1 (calibrated in factory)
EricLew	0:80ee8f3b695e	1737	* TS_CAL2 = equivalent TS_ADC_DATA at temperature
EricLew	0:80ee8f3b695e	1738	* TEMP_DEGC_CAL2 (calibrated in factory)
EricLew	0:80ee8f3b695e	1739	* Caution: Calculation relevancy under reserve that calibration
EricLew	0:80ee8f3b695e	1740	* parameters are correct (address and data).
EricLew	0:80ee8f3b695e	1741	* To calculate temperature using temperature sensor
EricLew	0:80ee8f3b695e	1742	* datasheet typical values (generic values less, therefore
EricLew	0:80ee8f3b695e	1743	* less accurate than calibrated values),
EricLew	0:80ee8f3b695e	1744	* use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
EricLew	0:80ee8f3b695e	1745	* @note As calculation input, the analog reference voltage (Vref+) must be
EricLew	0:80ee8f3b695e	1746	* defined as it impacts the ADC LSB equivalent voltage.
EricLew	0:80ee8f3b695e	1747	* @note Analog reference voltage (Vref+) must be either known from
EricLew	0:80ee8f3b695e	1748	* user board environment or can be calculated using ADC measurement
EricLew	0:80ee8f3b695e	1749	* and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
EricLew	0:80ee8f3b695e	1750	* @note ADC measurement data must correspond to a resolution of 12bits
EricLew	0:80ee8f3b695e	1751	* (full scale digital value 4095). If not the case, the data must be
EricLew	0:80ee8f3b695e	1752	* preliminarily rescaled to an equivalent resolution of 12 bits.
EricLew	0:80ee8f3b695e	1753	* @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
EricLew	0:80ee8f3b695e	1754	* @param __TEMPSENSOR_ADC_DATA__ ADC conversion data (resolution 12 bits)
EricLew	0:80ee8f3b695e	1755	* of internal temperature sensor (unit: digital value).
EricLew	0:80ee8f3b695e	1756	* @retval Temperature (unit: degree Celsius)
EricLew	0:80ee8f3b695e	1757	*/
EricLew	0:80ee8f3b695e	1758	#define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__, __TEMPSENSOR_ADC_DATA__) \
EricLew	0:80ee8f3b695e	1759	(((( ((int32_t)(((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \
EricLew	0:80ee8f3b695e	1760	/ TEMPSENSOR_CAL_VREFANALOG) \
EricLew	0:80ee8f3b695e	1761	- (int32_t) *TEMPSENSOR_CAL1_ADDR) \
EricLew	0:80ee8f3b695e	1762	) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \
EricLew	0:80ee8f3b695e	1763	) / (int32_t)((int32_t)TEMPSENSOR_CAL2_ADDR - (int32_t)TEMPSENSOR_CAL1_ADDR) \
EricLew	0:80ee8f3b695e	1764	) + TEMPSENSOR_CAL1_TEMP \
EricLew	0:80ee8f3b695e	1765	)
EricLew	0:80ee8f3b695e	1766
EricLew	0:80ee8f3b695e	1767	/**
EricLew	0:80ee8f3b695e	1768	* @brief Helper macro to calculate the temperature (unit: degree Celsius)
EricLew	0:80ee8f3b695e	1769	* from ADC conversion data of internal temperature sensor.
EricLew	0:80ee8f3b695e	1770	* Computation is using temperature sensor typical values
EricLew	0:80ee8f3b695e	1771	* (refer to device datasheet).
EricLew	0:80ee8f3b695e	1772	* @note Calculation formula:
EricLew	0:80ee8f3b695e	1773	* Temperature = (TS_ADC_DATA * conv_uV - TS_TYP_CAL1_VOLT)
EricLew	0:80ee8f3b695e	1774	* / Avg_Slope + CAL1_TEMP
EricLew	0:80ee8f3b695e	1775	* with TS_ADC_DATA = temperature sensor raw data measured by ADC
EricLew	0:80ee8f3b695e	1776	* (unit: digital value)
EricLew	0:80ee8f3b695e	1777	* Avg_Slope = temperature sensor slope
EricLew	0:80ee8f3b695e	1778	* (unit: uV/Degree Celsius)
EricLew	0:80ee8f3b695e	1779	* TS_TYP_CAL1_VOLT = temperature sensor digital value at
EricLew	0:80ee8f3b695e	1780	* temperature CAL1_TEMP (unit: mV)
EricLew	0:80ee8f3b695e	1781	* Caution: Calculation relevancy under reserve the temperature sensor
EricLew	0:80ee8f3b695e	1782	* of the current device has characteristics in line with
EricLew	0:80ee8f3b695e	1783	* datasheet typical values.
EricLew	0:80ee8f3b695e	1784	* If temperature sensor calibration values are available on
EricLew	0:80ee8f3b695e	1785	* on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
EricLew	0:80ee8f3b695e	1786	* temperature calculation will be more accurate using
EricLew	0:80ee8f3b695e	1787	* helper macro @ref __LL_ADC_CALC_TEMPERATURE().
EricLew	0:80ee8f3b695e	1788	* @note As calculation input, the analog reference voltage (Vref+) must be
EricLew	0:80ee8f3b695e	1789	* defined as it impacts the ADC LSB equivalent voltage.
EricLew	0:80ee8f3b695e	1790	* @note Analog reference voltage (Vref+) must be either known from
EricLew	0:80ee8f3b695e	1791	* user board environment or can be calculated using ADC measurement
EricLew	0:80ee8f3b695e	1792	* and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
EricLew	0:80ee8f3b695e	1793	* @note ADC measurement data must correspond to a resolution of 12bits
EricLew	0:80ee8f3b695e	1794	* (full scale digital value 4095). If not the case, the data must be
EricLew	0:80ee8f3b695e	1795	* preliminarily rescaled to an equivalent resolution of 12 bits.
EricLew	0:80ee8f3b695e	1796	* @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius).
EricLew	0:80ee8f3b695e	1797	* On STM32L4, refer to device datasheet parameter "Avg_Slope".
EricLew	0:80ee8f3b695e	1798	* @param __TEMPSENSOR_TYP_CAL1_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV).
EricLew	0:80ee8f3b695e	1799	* On STM32L4, refer to device datasheet parameter "V30".
EricLew	0:80ee8f3b695e	1800	* @param __TEMPSENSOR_CAL1_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding(unit: mV)
EricLew	0:80ee8f3b695e	1801	* @param __TEMPSENSOR_CAL_VREFANALOG__ Analog voltage reference (Vref+) voltage (unit: mV)
EricLew	0:80ee8f3b695e	1802	* @param __VREFANALOG_VOLTAGE__ Analog reference voltage at which temperature sensor voltage (see parameter above) is corresponding(unit: mV)
EricLew	0:80ee8f3b695e	1803	* @param __TEMPSENSOR_ADC_DATA__ ADC conversion data (resolution 12 bits) of internal
EricLew	0:80ee8f3b695e	1804	* temperature sensor (unit: digital value).
EricLew	0:80ee8f3b695e	1805	* @retval Temperature (unit: degree Celsius)
EricLew	0:80ee8f3b695e	1806	*/
EricLew	0:80ee8f3b695e	1807	#define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
EricLew	0:80ee8f3b695e	1808	__TEMPSENSOR_TYP_CAL1_V__,\
EricLew	0:80ee8f3b695e	1809	__TEMPSENSOR_CAL1_TEMP__,\
EricLew	0:80ee8f3b695e	1810	__TEMPSENSOR_CAL_VREFANALOG__,\
EricLew	0:80ee8f3b695e	1811	__VREFANALOG_VOLTAGE__,\
EricLew	0:80ee8f3b695e	1812	__TEMPSENSOR_ADC_DATA__) \
EricLew	0:80ee8f3b695e	1813	((( ((int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \
EricLew	0:80ee8f3b695e	1814	/ __LL_ADC_DIGITAL_SCALE(LL_ADC_RESOLUTION_12B)) \
EricLew	0:80ee8f3b695e	1815	* 1000) \
EricLew	0:80ee8f3b695e	1816	- \
EricLew	0:80ee8f3b695e	1817	(int32_t)(((__TEMPSENSOR_TYP_CAL1_V__)) \
EricLew	0:80ee8f3b695e	1818	* 1000) \
EricLew	0:80ee8f3b695e	1819	) \
EricLew	0:80ee8f3b695e	1820	) / (__TEMPSENSOR_TYP_AVGSLOPE__) \
EricLew	0:80ee8f3b695e	1821	) + (__TEMPSENSOR_CAL1_TEMP__) \
EricLew	0:80ee8f3b695e	1822	)
EricLew	0:80ee8f3b695e	1823
EricLew	0:80ee8f3b695e	1824	/**
EricLew	0:80ee8f3b695e	1825	* @}
EricLew	0:80ee8f3b695e	1826	*/
EricLew	0:80ee8f3b695e	1827
EricLew	0:80ee8f3b695e	1828	/**
EricLew	0:80ee8f3b695e	1829	* @}
EricLew	0:80ee8f3b695e	1830	*/
EricLew	0:80ee8f3b695e	1831
EricLew	0:80ee8f3b695e	1832
EricLew	0:80ee8f3b695e	1833	/* Exported functions --------------------------------------------------------*/
EricLew	0:80ee8f3b695e	1834	/** @defgroup ADC_LL_Exported_Functions ADC Exported Functions
EricLew	0:80ee8f3b695e	1835	* @{
EricLew	0:80ee8f3b695e	1836	*/
EricLew	0:80ee8f3b695e	1837
EricLew	0:80ee8f3b695e	1838	/** @defgroup ADC_LL_EF_DMA_Management ADC DMA management
EricLew	0:80ee8f3b695e	1839	* @{
EricLew	0:80ee8f3b695e	1840	*/
EricLew	0:80ee8f3b695e	1841	/* Note: LL ADC functions to set DMA transfer are located into sections of */
EricLew	0:80ee8f3b695e	1842	/* configuration of ADC instance, groups and multimode (if available): */
EricLew	0:80ee8f3b695e	1843	/* @ref LL_ADC_REG_SetDMATransfer(), ... */
EricLew	0:80ee8f3b695e	1844
EricLew	0:80ee8f3b695e	1845	/**
EricLew	0:80ee8f3b695e	1846	* @brief Function to help to configure DMA transfer from ADC: retrieve the
EricLew	0:80ee8f3b695e	1847	* ADC register address from ADC instance and a list of ADC registers
EricLew	0:80ee8f3b695e	1848	* intended to be used (most commonly) with DMA transfer.
EricLew	0:80ee8f3b695e	1849	* These ADC registers are data registers:
EricLew	0:80ee8f3b695e	1850	* when ADC conversion data is available in ADC data registers,
EricLew	0:80ee8f3b695e	1851	* ADC generates a DMA transfer request.
EricLew	0:80ee8f3b695e	1852	* @note This macro is intended to be used with LL DMA driver, refer to
EricLew	0:80ee8f3b695e	1853	* function "LL_DMA_ConfigAddresses()".
EricLew	0:80ee8f3b695e	1854	* Example:
EricLew	0:80ee8f3b695e	1855	* LL_DMA_ConfigAddresses(DMA1,
EricLew	0:80ee8f3b695e	1856	* LL_DMA_CHANNEL_1,
EricLew	0:80ee8f3b695e	1857	* LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
EricLew	0:80ee8f3b695e	1858	* (uint32_t)&< array or variable >,
EricLew	0:80ee8f3b695e	1859	* LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
EricLew	0:80ee8f3b695e	1860	* @note For devices with several ADC: in multimode, some devices
EricLew	0:80ee8f3b695e	1861	* use a different data register outside of ADC instance scope
EricLew	0:80ee8f3b695e	1862	* (common data register). This macro manages this register difference,
EricLew	0:80ee8f3b695e	1863	* only ADC instance has to be set as parameter.
EricLew	0:80ee8f3b695e	1864	* @rmtoll DR RDATA LL_ADC_DMA_GetRegAddr\n
EricLew	0:80ee8f3b695e	1865	* CDR RDATA_MST LL_ADC_DMA_GetRegAddr\n
EricLew	0:80ee8f3b695e	1866	* CDR RDATA_SLV LL_ADC_DMA_GetRegAddr
EricLew	0:80ee8f3b695e	1867	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	1868	* @param Register This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1869	* @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
EricLew	0:80ee8f3b695e	1870	* @arg @ref LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1)
EricLew	0:80ee8f3b695e	1871	* (1) Available on devices with several ADC instances.
EricLew	0:80ee8f3b695e	1872	* @retval ADC register address
EricLew	0:80ee8f3b695e	1873	*/
EricLew	0:80ee8f3b695e	1874	#if defined(ADC2)
EricLew	0:80ee8f3b695e	1875	__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
EricLew	0:80ee8f3b695e	1876	{
EricLew	0:80ee8f3b695e	1877	register uint32_t data_reg_addr = 0;
EricLew	0:80ee8f3b695e	1878
EricLew	0:80ee8f3b695e	1879	if (Register == LL_ADC_DMA_REG_REGULAR_DATA)
EricLew	0:80ee8f3b695e	1880	{
EricLew	0:80ee8f3b695e	1881	/* Retrieve address of register DR */
EricLew	0:80ee8f3b695e	1882	data_reg_addr = (uint32_t)&(ADCx->DR);
EricLew	0:80ee8f3b695e	1883	}
EricLew	0:80ee8f3b695e	1884	else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */
EricLew	0:80ee8f3b695e	1885	{
EricLew	0:80ee8f3b695e	1886	/* Retrieve address of register CDR */
EricLew	0:80ee8f3b695e	1887	data_reg_addr = (uint32_t)&((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR);
EricLew	0:80ee8f3b695e	1888	}
EricLew	0:80ee8f3b695e	1889
EricLew	0:80ee8f3b695e	1890	return data_reg_addr;
EricLew	0:80ee8f3b695e	1891	}
EricLew	0:80ee8f3b695e	1892	#else
EricLew	0:80ee8f3b695e	1893	__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
EricLew	0:80ee8f3b695e	1894	{
EricLew	0:80ee8f3b695e	1895	/* Retrieve address of register DR */
EricLew	0:80ee8f3b695e	1896	return (uint32_t)&(ADCx->DR);
EricLew	0:80ee8f3b695e	1897	}
EricLew	0:80ee8f3b695e	1898	#endif
EricLew	0:80ee8f3b695e	1899
EricLew	0:80ee8f3b695e	1900	/**
EricLew	0:80ee8f3b695e	1901	* @}
EricLew	0:80ee8f3b695e	1902	*/
EricLew	0:80ee8f3b695e	1903
EricLew	0:80ee8f3b695e	1904	/** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC
EricLew	0:80ee8f3b695e	1905	* @{
EricLew	0:80ee8f3b695e	1906	*/
EricLew	0:80ee8f3b695e	1907
EricLew	0:80ee8f3b695e	1908	/**
EricLew	0:80ee8f3b695e	1909	* @brief Set parameter common to several ADC: Clock source and prescaler.
EricLew	0:80ee8f3b695e	1910	* @note On this STM32 family, if ADC group injected is used, some
EricLew	0:80ee8f3b695e	1911	* clock ratio constraints between ADC clock and AHB clock
EricLew	0:80ee8f3b695e	1912	* must be respected.
EricLew	0:80ee8f3b695e	1913	* Refer to reference manual.
EricLew	0:80ee8f3b695e	1914	* @note On this STM32 family, setting of this feature is conditioned to
EricLew	0:80ee8f3b695e	1915	* ADC state:
EricLew	0:80ee8f3b695e	1916	* All ADC instances of the ADC common group must be disabled.
EricLew	0:80ee8f3b695e	1917	* This check can be done with function @ref LL_ADC_IsEnabled() for each
EricLew	0:80ee8f3b695e	1918	* ADC instance or by using helper macro helper macro
EricLew	0:80ee8f3b695e	1919	* @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
EricLew	0:80ee8f3b695e	1920	* @rmtoll CCR CKMODE LL_ADC_SetCommonClock\n
EricLew	0:80ee8f3b695e	1921	* CCR PRESC LL_ADC_SetCommonClock
EricLew	0:80ee8f3b695e	1922	* @param ADCxy_COMMON ADC common instance
EricLew	0:80ee8f3b695e	1923	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
EricLew	0:80ee8f3b695e	1924	* @param ClockSource This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1925	* @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1
EricLew	0:80ee8f3b695e	1926	* @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
EricLew	0:80ee8f3b695e	1927	* @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
EricLew	0:80ee8f3b695e	1928	* @arg @ref LL_ADC_CLOCK_ASYNC_DIV1
EricLew	0:80ee8f3b695e	1929	* @arg @ref LL_ADC_CLOCK_ASYNC_DIV2
EricLew	0:80ee8f3b695e	1930	* @arg @ref LL_ADC_CLOCK_ASYNC_DIV4
EricLew	0:80ee8f3b695e	1931	* @arg @ref LL_ADC_CLOCK_ASYNC_DIV6
EricLew	0:80ee8f3b695e	1932	* @arg @ref LL_ADC_CLOCK_ASYNC_DIV8
EricLew	0:80ee8f3b695e	1933	* @arg @ref LL_ADC_CLOCK_ASYNC_DIV10
EricLew	0:80ee8f3b695e	1934	* @arg @ref LL_ADC_CLOCK_ASYNC_DIV12
EricLew	0:80ee8f3b695e	1935	* @arg @ref LL_ADC_CLOCK_ASYNC_DIV16
EricLew	0:80ee8f3b695e	1936	* @arg @ref LL_ADC_CLOCK_ASYNC_DIV32
EricLew	0:80ee8f3b695e	1937	* @arg @ref LL_ADC_CLOCK_ASYNC_DIV64
EricLew	0:80ee8f3b695e	1938	* @arg @ref LL_ADC_CLOCK_ASYNC_DIV128
EricLew	0:80ee8f3b695e	1939	* @arg @ref LL_ADC_CLOCK_ASYNC_DIV256
EricLew	0:80ee8f3b695e	1940	* @retval None
EricLew	0:80ee8f3b695e	1941	*/
EricLew	0:80ee8f3b695e	1942	__STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t ClockSource)
EricLew	0:80ee8f3b695e	1943	{
EricLew	0:80ee8f3b695e	1944	MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE \| ADC_CCR_PRESC, ClockSource);
EricLew	0:80ee8f3b695e	1945	}
EricLew	0:80ee8f3b695e	1946
EricLew	0:80ee8f3b695e	1947	/**
EricLew	0:80ee8f3b695e	1948	* @brief Get parameter common to several ADC: Clock source and prescaler.
EricLew	0:80ee8f3b695e	1949	* @rmtoll CCR CKMODE LL_ADC_GetCommonClock\n
EricLew	0:80ee8f3b695e	1950	* CCR PRESC LL_ADC_GetCommonClock
EricLew	0:80ee8f3b695e	1951	* @param ADCxy_COMMON ADC common instance
EricLew	0:80ee8f3b695e	1952	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
EricLew	0:80ee8f3b695e	1953	* @retval Returned value can be one of the following values:
EricLew	0:80ee8f3b695e	1954	* @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1
EricLew	0:80ee8f3b695e	1955	* @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
EricLew	0:80ee8f3b695e	1956	* @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
EricLew	0:80ee8f3b695e	1957	* @arg @ref LL_ADC_CLOCK_ASYNC_DIV1
EricLew	0:80ee8f3b695e	1958	* @arg @ref LL_ADC_CLOCK_ASYNC_DIV2
EricLew	0:80ee8f3b695e	1959	* @arg @ref LL_ADC_CLOCK_ASYNC_DIV4
EricLew	0:80ee8f3b695e	1960	* @arg @ref LL_ADC_CLOCK_ASYNC_DIV6
EricLew	0:80ee8f3b695e	1961	* @arg @ref LL_ADC_CLOCK_ASYNC_DIV8
EricLew	0:80ee8f3b695e	1962	* @arg @ref LL_ADC_CLOCK_ASYNC_DIV10
EricLew	0:80ee8f3b695e	1963	* @arg @ref LL_ADC_CLOCK_ASYNC_DIV12
EricLew	0:80ee8f3b695e	1964	* @arg @ref LL_ADC_CLOCK_ASYNC_DIV16
EricLew	0:80ee8f3b695e	1965	* @arg @ref LL_ADC_CLOCK_ASYNC_DIV32
EricLew	0:80ee8f3b695e	1966	* @arg @ref LL_ADC_CLOCK_ASYNC_DIV64
EricLew	0:80ee8f3b695e	1967	* @arg @ref LL_ADC_CLOCK_ASYNC_DIV128
EricLew	0:80ee8f3b695e	1968	* @arg @ref LL_ADC_CLOCK_ASYNC_DIV256
EricLew	0:80ee8f3b695e	1969	*/
EricLew	0:80ee8f3b695e	1970	__STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON)
EricLew	0:80ee8f3b695e	1971	{
EricLew	0:80ee8f3b695e	1972	return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_CKMODE \| ADC_CCR_PRESC));
EricLew	0:80ee8f3b695e	1973	}
EricLew	0:80ee8f3b695e	1974
EricLew	0:80ee8f3b695e	1975	/**
EricLew	0:80ee8f3b695e	1976	* @brief Set parameter common to several ADC: measurement path to internal
EricLew	0:80ee8f3b695e	1977	* channels (VrefInt, temperature sensor, ...).
EricLew	0:80ee8f3b695e	1978	* One or several values can be selected.
EricLew	0:80ee8f3b695e	1979	* Example: (LL_ADC_PATH_INTERNAL_VREFINT \|
EricLew	0:80ee8f3b695e	1980	* LL_ADC_PATH_INTERNAL_TEMPSENSOR)
EricLew	0:80ee8f3b695e	1981	* @note On this STM32 family, setting of this feature is conditioned to
EricLew	0:80ee8f3b695e	1982	* ADC state:
EricLew	0:80ee8f3b695e	1983	* All ADC instances of the ADC common group must be disabled.
EricLew	0:80ee8f3b695e	1984	* This check can be done with function @ref LL_ADC_IsEnabled() for each
EricLew	0:80ee8f3b695e	1985	* ADC instance or by using helper macro helper macro
EricLew	0:80ee8f3b695e	1986	* @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
EricLew	0:80ee8f3b695e	1987	* @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalCh\n
EricLew	0:80ee8f3b695e	1988	* CCR TSEN LL_ADC_SetCommonPathInternalCh\n
EricLew	0:80ee8f3b695e	1989	* CCR VBATEN LL_ADC_SetCommonPathInternalCh
EricLew	0:80ee8f3b695e	1990	* @param ADCxy_COMMON ADC common instance
EricLew	0:80ee8f3b695e	1991	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
EricLew	0:80ee8f3b695e	1992	* @param PathInternal This parameter can be a combination of the following values:
EricLew	0:80ee8f3b695e	1993	* @arg @ref LL_ADC_PATH_INTERNAL_NONE
EricLew	0:80ee8f3b695e	1994	* @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
EricLew	0:80ee8f3b695e	1995	* @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
EricLew	0:80ee8f3b695e	1996	* @arg @ref LL_ADC_PATH_INTERNAL_VBAT
EricLew	0:80ee8f3b695e	1997	* @retval None
EricLew	0:80ee8f3b695e	1998	*/
EricLew	0:80ee8f3b695e	1999	__STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
EricLew	0:80ee8f3b695e	2000	{
EricLew	0:80ee8f3b695e	2001	MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN \| ADC_CCR_TSEN \| ADC_CCR_VBATEN, PathInternal);
EricLew	0:80ee8f3b695e	2002	}
EricLew	0:80ee8f3b695e	2003
EricLew	0:80ee8f3b695e	2004	/**
EricLew	0:80ee8f3b695e	2005	* @brief Get parameter common to several ADC: measurement path to internal
EricLew	0:80ee8f3b695e	2006	* channels (VrefInt, temperature sensor, ...).
EricLew	0:80ee8f3b695e	2007	* One or several values can be selected.
EricLew	0:80ee8f3b695e	2008	* Example: (LL_ADC_PATH_INTERNAL_VREFINT \|
EricLew	0:80ee8f3b695e	2009	* LL_ADC_PATH_INTERNAL_TEMPSENSOR)
EricLew	0:80ee8f3b695e	2010	* @rmtoll CCR VREFEN LL_ADC_GetCommonPathInternalCh\n
EricLew	0:80ee8f3b695e	2011	* CCR TSEN LL_ADC_GetCommonPathInternalCh\n
EricLew	0:80ee8f3b695e	2012	* CCR VBATEN LL_ADC_GetCommonPathInternalCh
EricLew	0:80ee8f3b695e	2013	* @param ADCxy_COMMON ADC common instance
EricLew	0:80ee8f3b695e	2014	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
EricLew	0:80ee8f3b695e	2015	* @retval Returned value can be a combination of the following values:
EricLew	0:80ee8f3b695e	2016	* @arg @ref LL_ADC_PATH_INTERNAL_NONE
EricLew	0:80ee8f3b695e	2017	* @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
EricLew	0:80ee8f3b695e	2018	* @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
EricLew	0:80ee8f3b695e	2019	* @arg @ref LL_ADC_PATH_INTERNAL_VBAT
EricLew	0:80ee8f3b695e	2020	*/
EricLew	0:80ee8f3b695e	2021	__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON)
EricLew	0:80ee8f3b695e	2022	{
EricLew	0:80ee8f3b695e	2023	return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN \| ADC_CCR_TSEN \| ADC_CCR_VBATEN));
EricLew	0:80ee8f3b695e	2024	}
EricLew	0:80ee8f3b695e	2025
EricLew	0:80ee8f3b695e	2026	/**
EricLew	0:80ee8f3b695e	2027	* @}
EricLew	0:80ee8f3b695e	2028	*/
EricLew	0:80ee8f3b695e	2029
EricLew	0:80ee8f3b695e	2030	/** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance
EricLew	0:80ee8f3b695e	2031	* @{
EricLew	0:80ee8f3b695e	2032	*/
EricLew	0:80ee8f3b695e	2033
EricLew	0:80ee8f3b695e	2034	/**
EricLew	0:80ee8f3b695e	2035	* @brief Set ADC calibration factor in the mode single-ended
EricLew	0:80ee8f3b695e	2036	* or differential (for devices with differential mode available).
EricLew	0:80ee8f3b695e	2037	* This function is intended to set calibration parameters
EricLew	0:80ee8f3b695e	2038	* without performing a new calibration using
EricLew	0:80ee8f3b695e	2039	* @ref LL_ADC_StartCalibration().
EricLew	0:80ee8f3b695e	2040	* @note In case of setting calibration factors of both modes single ended
EricLew	0:80ee8f3b695e	2041	* and differential (parameter LL_ADC_BOTH_SINGLE_DIFF_ENDED):
EricLew	0:80ee8f3b695e	2042	* both calibration factors must be concatenated.
EricLew	0:80ee8f3b695e	2043	* To perform this processing, use helper macro
EricLew	0:80ee8f3b695e	2044	* @ref __LL_ADC_CALIB_FACTOR_SINGLE_DIFF().
EricLew	0:80ee8f3b695e	2045	* @note On this STM32 family, setting of this feature is conditioned to
EricLew	0:80ee8f3b695e	2046	* ADC state:
EricLew	0:80ee8f3b695e	2047	* ADC must be enabled, without calibration on going, without conversion
EricLew	0:80ee8f3b695e	2048	* on going on group regular.
EricLew	0:80ee8f3b695e	2049	* @rmtoll CALFACT CALFACT_S LL_ADC_SetCalibrationFactor\n
EricLew	0:80ee8f3b695e	2050	* CALFACT CALFACT_D LL_ADC_SetCalibrationFactor
EricLew	0:80ee8f3b695e	2051	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	2052	* @param SingleDiff This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2053	* @arg @ref LL_ADC_SINGLE_ENDED
EricLew	0:80ee8f3b695e	2054	* @arg @ref LL_ADC_DIFFERENTIAL_ENDED
EricLew	0:80ee8f3b695e	2055	* @arg @ref LL_ADC_BOTH_SINGLE_DIFF_ENDED
EricLew	0:80ee8f3b695e	2056	* @param CalibrationFactor 0x00...0x7F
EricLew	0:80ee8f3b695e	2057	* @retval None
EricLew	0:80ee8f3b695e	2058	*/
EricLew	0:80ee8f3b695e	2059	__STATIC_INLINE void LL_ADC_SetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff, uint32_t CalibrationFactor)
EricLew	0:80ee8f3b695e	2060	{
EricLew	0:80ee8f3b695e	2061	MODIFY_REG(ADCx->CALFACT,
EricLew	0:80ee8f3b695e	2062	SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK,
EricLew	0:80ee8f3b695e	2063	CalibrationFactor << POSITION_VAL(SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK));
EricLew	0:80ee8f3b695e	2064	}
EricLew	0:80ee8f3b695e	2065
EricLew	0:80ee8f3b695e	2066	/**
EricLew	0:80ee8f3b695e	2067	* @brief Get ADC calibration factor in the mode single-ended
EricLew	0:80ee8f3b695e	2068	* or differential (for devices with differential mode available).
EricLew	0:80ee8f3b695e	2069	* Calibration factors are set by hardware after performing a
EricLew	0:80ee8f3b695e	2070	* calibration using function @ref LL_ADC_StartCalibration().
EricLew	0:80ee8f3b695e	2071	* @rmtoll CALFACT CALFACT_S LL_ADC_GetCalibrationFactor\n
EricLew	0:80ee8f3b695e	2072	* CALFACT CALFACT_D LL_ADC_GetCalibrationFactor
EricLew	0:80ee8f3b695e	2073	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	2074	* @param SingleDiff This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2075	* @arg @ref LL_ADC_SINGLE_ENDED
EricLew	0:80ee8f3b695e	2076	* @arg @ref LL_ADC_DIFFERENTIAL_ENDED
EricLew	0:80ee8f3b695e	2077	* @retval 0x00...0x7F
EricLew	0:80ee8f3b695e	2078	*/
EricLew	0:80ee8f3b695e	2079	__STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff)
EricLew	0:80ee8f3b695e	2080	{
EricLew	0:80ee8f3b695e	2081	/* Retrieve bits with position in register depending on parameter */
EricLew	0:80ee8f3b695e	2082	/* "SingleDiff". */
EricLew	0:80ee8f3b695e	2083	/* Parameter used with mask "ADC_SINGLEDIFF_CALIB_FACTOR_MASK" because */
EricLew	0:80ee8f3b695e	2084	/* containing other bits reserved for other purpose. */
EricLew	0:80ee8f3b695e	2085	return (uint32_t)(READ_BIT(ADCx->CALFACT, (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) >> POSITION_VAL(SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK));
EricLew	0:80ee8f3b695e	2086	}
EricLew	0:80ee8f3b695e	2087
EricLew	0:80ee8f3b695e	2088	/**
EricLew	0:80ee8f3b695e	2089	* @brief Set ADC data resolution.
EricLew	0:80ee8f3b695e	2090	* Refer to reference manual for alignments formats versus ADC resolutions.
EricLew	0:80ee8f3b695e	2091	* @note On this STM32 family, setting of this feature is conditioned to
EricLew	0:80ee8f3b695e	2092	* ADC state:
EricLew	0:80ee8f3b695e	2093	* ADC must be disabled or enabled without conversion on going
EricLew	0:80ee8f3b695e	2094	* on either groups regular or injected.
EricLew	0:80ee8f3b695e	2095	* @rmtoll CFGR RES LL_ADC_SetResolution
EricLew	0:80ee8f3b695e	2096	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	2097	* @param Resolution This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2098	* @arg @ref LL_ADC_RESOLUTION_12B
EricLew	0:80ee8f3b695e	2099	* @arg @ref LL_ADC_RESOLUTION_10B
EricLew	0:80ee8f3b695e	2100	* @arg @ref LL_ADC_RESOLUTION_8B
EricLew	0:80ee8f3b695e	2101	* @arg @ref LL_ADC_RESOLUTION_6B
EricLew	0:80ee8f3b695e	2102	* @retval None
EricLew	0:80ee8f3b695e	2103	*/
EricLew	0:80ee8f3b695e	2104	__STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)
EricLew	0:80ee8f3b695e	2105	{
EricLew	0:80ee8f3b695e	2106	MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution);
EricLew	0:80ee8f3b695e	2107	}
EricLew	0:80ee8f3b695e	2108
EricLew	0:80ee8f3b695e	2109	/**
EricLew	0:80ee8f3b695e	2110	* @brief Get ADC data resolution.
EricLew	0:80ee8f3b695e	2111	* Refer to reference manual for alignments formats versus ADC resolutions.
EricLew	0:80ee8f3b695e	2112	* @rmtoll CFGR RES LL_ADC_GetResolution
EricLew	0:80ee8f3b695e	2113	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	2114	* @retval Returned value can be one of the following values:
EricLew	0:80ee8f3b695e	2115	* @arg @ref LL_ADC_RESOLUTION_12B
EricLew	0:80ee8f3b695e	2116	* @arg @ref LL_ADC_RESOLUTION_10B
EricLew	0:80ee8f3b695e	2117	* @arg @ref LL_ADC_RESOLUTION_8B
EricLew	0:80ee8f3b695e	2118	* @arg @ref LL_ADC_RESOLUTION_6B
EricLew	0:80ee8f3b695e	2119	*/
EricLew	0:80ee8f3b695e	2120	__STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	2121	{
EricLew	0:80ee8f3b695e	2122	return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES));
EricLew	0:80ee8f3b695e	2123	}
EricLew	0:80ee8f3b695e	2124
EricLew	0:80ee8f3b695e	2125	/**
EricLew	0:80ee8f3b695e	2126	* @brief Set ADC conversion data alignment.
EricLew	0:80ee8f3b695e	2127	* Refer to reference manual for alignments formats
EricLew	0:80ee8f3b695e	2128	* dependencies to ADC resolutions.
EricLew	0:80ee8f3b695e	2129	* @note On this STM32 family, setting of this feature is conditioned to
EricLew	0:80ee8f3b695e	2130	* ADC state:
EricLew	0:80ee8f3b695e	2131	* ADC must be disabled or enabled without conversion on going
EricLew	0:80ee8f3b695e	2132	* on either groups regular or injected.
EricLew	0:80ee8f3b695e	2133	* @rmtoll CFGR ALIGN LL_ADC_SetDataAlignment
EricLew	0:80ee8f3b695e	2134	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	2135	* @param DataAlignment This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2136	* @arg @ref LL_ADC_DATA_ALIGN_RIGHT
EricLew	0:80ee8f3b695e	2137	* @arg @ref LL_ADC_DATA_ALIGN_LEFT
EricLew	0:80ee8f3b695e	2138	* @retval None
EricLew	0:80ee8f3b695e	2139	*/
EricLew	0:80ee8f3b695e	2140	__STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment)
EricLew	0:80ee8f3b695e	2141	{
EricLew	0:80ee8f3b695e	2142	MODIFY_REG(ADCx->CFGR, ADC_CFGR_ALIGN, DataAlignment);
EricLew	0:80ee8f3b695e	2143	}
EricLew	0:80ee8f3b695e	2144
EricLew	0:80ee8f3b695e	2145	/**
EricLew	0:80ee8f3b695e	2146	* @brief Get ADC conversion data alignment.
EricLew	0:80ee8f3b695e	2147	* Refer to reference manual for alignments formats
EricLew	0:80ee8f3b695e	2148	* dependencies to ADC resolutions.
EricLew	0:80ee8f3b695e	2149	* @rmtoll CFGR ALIGN LL_ADC_GetDataAlignment
EricLew	0:80ee8f3b695e	2150	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	2151	* @retval Returned value can be one of the following values:
EricLew	0:80ee8f3b695e	2152	* @arg @ref LL_ADC_DATA_ALIGN_RIGHT
EricLew	0:80ee8f3b695e	2153	* @arg @ref LL_ADC_DATA_ALIGN_LEFT
EricLew	0:80ee8f3b695e	2154	*/
EricLew	0:80ee8f3b695e	2155	__STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	2156	{
EricLew	0:80ee8f3b695e	2157	return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_ALIGN));
EricLew	0:80ee8f3b695e	2158	}
EricLew	0:80ee8f3b695e	2159
EricLew	0:80ee8f3b695e	2160	/**
EricLew	0:80ee8f3b695e	2161	* @brief Set ADC low power mode:
EricLew	0:80ee8f3b695e	2162	* * ADC low power mode "auto wait": Dynamic low power mode,
EricLew	0:80ee8f3b695e	2163	* ADC conversions occurrences are limited to the minimum necessary
EricLew	0:80ee8f3b695e	2164	* in order to reduce power consumption.
EricLew	0:80ee8f3b695e	2165	* New ADC conversion starts only when the previous
EricLew	0:80ee8f3b695e	2166	* unitary conversion data (for ADC group regular)
EricLew	0:80ee8f3b695e	2167	* or previous sequence conversions data (for ADC group injected)
EricLew	0:80ee8f3b695e	2168	* has been retrieved by user software.
EricLew	0:80ee8f3b695e	2169	* In the meantime, ADC remains idle: does not performs any
EricLew	0:80ee8f3b695e	2170	* other conversion.
EricLew	0:80ee8f3b695e	2171	* This mode allows to automatically adapt the ADC conversions
EricLew	0:80ee8f3b695e	2172	* trigs to the speed of the software that reads the data.
EricLew	0:80ee8f3b695e	2173	* Moreover, this avoids risk of overrun for low frequency
EricLew	0:80ee8f3b695e	2174	* applications.
EricLew	0:80ee8f3b695e	2175	* How to use this low power mode:
EricLew	0:80ee8f3b695e	2176	* * Do not use with interruption or DMA since these modes
EricLew	0:80ee8f3b695e	2177	* have to clear immediately the EOC flag to free the
EricLew	0:80ee8f3b695e	2178	* IRQ vector sequencer.
EricLew	0:80ee8f3b695e	2179	* * Do use with polling: 1. Start conversion,
EricLew	0:80ee8f3b695e	2180	* 2. Later on, when conversion data is needed: poll for end of
EricLew	0:80ee8f3b695e	2181	* conversion to ensure that conversion is completed and
EricLew	0:80ee8f3b695e	2182	* retrieve ADC conversion data. This will trig another
EricLew	0:80ee8f3b695e	2183	* ADC conversion start.
EricLew	0:80ee8f3b695e	2184	* * ADC low power mode "auto power-off" (feature available on
EricLew	0:80ee8f3b695e	2185	* this device if parameter LL_ADC_LP_MODE_AUTOOFF is available):
EricLew	0:80ee8f3b695e	2186	* the ADC automatically powers-off after a conversion and
EricLew	0:80ee8f3b695e	2187	* automatically wakes-up when a new conversion is triggered
EricLew	0:80ee8f3b695e	2188	* (with startup time between trigger and start of sampling).
EricLew	0:80ee8f3b695e	2189	* This feature can be combined with low power mode "auto wait".
EricLew	0:80ee8f3b695e	2190	* @note With ADC low power mode "auto wait", the ADC conversion data read
EricLew	0:80ee8f3b695e	2191	* is corresponding to previous ADC conversion start, independently
EricLew	0:80ee8f3b695e	2192	* of delay during which ADC was idle.
EricLew	0:80ee8f3b695e	2193	* Therefore, the ADC conversion data may be outdated: does not
EricLew	0:80ee8f3b695e	2194	* correspond to the current voltage level on the selected
EricLew	0:80ee8f3b695e	2195	* ADC channel.
EricLew	0:80ee8f3b695e	2196	* @note On this STM32 family, setting of this feature is conditioned to
EricLew	0:80ee8f3b695e	2197	* ADC state:
EricLew	0:80ee8f3b695e	2198	* ADC must be disabled or enabled without conversion on going
EricLew	0:80ee8f3b695e	2199	* on either groups regular or injected.
EricLew	0:80ee8f3b695e	2200	* @rmtoll CFGR AUTDLY LL_ADC_SetLowPowerMode
EricLew	0:80ee8f3b695e	2201	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	2202	* @param LowPowerMode This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2203	* @arg @ref LL_ADC_LP_MODE_NONE
EricLew	0:80ee8f3b695e	2204	* @arg @ref LL_ADC_LP_AUTOWAIT
EricLew	0:80ee8f3b695e	2205	* @retval None
EricLew	0:80ee8f3b695e	2206	*/
EricLew	0:80ee8f3b695e	2207	__STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPowerMode)
EricLew	0:80ee8f3b695e	2208	{
EricLew	0:80ee8f3b695e	2209	MODIFY_REG(ADCx->CFGR, ADC_CFGR_AUTDLY, LowPowerMode);
EricLew	0:80ee8f3b695e	2210	}
EricLew	0:80ee8f3b695e	2211
EricLew	0:80ee8f3b695e	2212	/**
EricLew	0:80ee8f3b695e	2213	* @brief Get ADC low power mode:
EricLew	0:80ee8f3b695e	2214	* * ADC low power mode "auto wait": Dynamic low power mode,
EricLew	0:80ee8f3b695e	2215	* ADC conversions occurrences are limited to the minimum necessary
EricLew	0:80ee8f3b695e	2216	* in order to reduce power consumption.
EricLew	0:80ee8f3b695e	2217	* New ADC conversion starts only when the previous
EricLew	0:80ee8f3b695e	2218	* unitary conversion data (for ADC group regular)
EricLew	0:80ee8f3b695e	2219	* or previous sequence conversions data (for ADC group injected)
EricLew	0:80ee8f3b695e	2220	* has been retrieved by user software.
EricLew	0:80ee8f3b695e	2221	* In the meantime, ADC remains idle: does not performs any
EricLew	0:80ee8f3b695e	2222	* other conversion.
EricLew	0:80ee8f3b695e	2223	* This mode allows to automatically adapt the ADC conversions
EricLew	0:80ee8f3b695e	2224	* trigs to the speed of the software that reads the data.
EricLew	0:80ee8f3b695e	2225	* Moreover, this avoids risk of overrun for low frequency
EricLew	0:80ee8f3b695e	2226	* applications.
EricLew	0:80ee8f3b695e	2227	* How to use this low power mode:
EricLew	0:80ee8f3b695e	2228	* * Do not use with interruption or DMA since these modes
EricLew	0:80ee8f3b695e	2229	* have to clear immediately the EOC flag to free the
EricLew	0:80ee8f3b695e	2230	* IRQ vector sequencer.
EricLew	0:80ee8f3b695e	2231	* * Do use with polling: 1. Start conversion,
EricLew	0:80ee8f3b695e	2232	* 2. Later on, when conversion data is needed: poll for end of
EricLew	0:80ee8f3b695e	2233	* conversion to ensure that conversion is completed and
EricLew	0:80ee8f3b695e	2234	* retrieve ADC conversion data. This will trig another
EricLew	0:80ee8f3b695e	2235	* ADC conversion start.
EricLew	0:80ee8f3b695e	2236	* * ADC low power mode "auto power-off" (feature available on
EricLew	0:80ee8f3b695e	2237	* this device if parameter LL_ADC_LP_MODE_AUTOOFF is available):
EricLew	0:80ee8f3b695e	2238	* the ADC automatically powers-off after a conversion and
EricLew	0:80ee8f3b695e	2239	* automatically wakes-up when a new conversion is triggered
EricLew	0:80ee8f3b695e	2240	* (with startup time between trigger and start of sampling).
EricLew	0:80ee8f3b695e	2241	* This feature can be combined with low power mode "auto wait".
EricLew	0:80ee8f3b695e	2242	* @note With ADC low power mode "auto wait", the ADC conversion data read
EricLew	0:80ee8f3b695e	2243	* is corresponding to previous ADC conversion start, independently
EricLew	0:80ee8f3b695e	2244	* of delay during which ADC was idle.
EricLew	0:80ee8f3b695e	2245	* Therefore, the ADC conversion data may be outdated: does not
EricLew	0:80ee8f3b695e	2246	* correspond to the current voltage level on the selected
EricLew	0:80ee8f3b695e	2247	* ADC channel.
EricLew	0:80ee8f3b695e	2248	* @rmtoll CFGR AUTDLY LL_ADC_GetLowPowerMode
EricLew	0:80ee8f3b695e	2249	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	2250	* @retval Returned value can be one of the following values:
EricLew	0:80ee8f3b695e	2251	* @arg @ref LL_ADC_LP_MODE_NONE
EricLew	0:80ee8f3b695e	2252	* @arg @ref LL_ADC_LP_AUTOWAIT
EricLew	0:80ee8f3b695e	2253	*/
EricLew	0:80ee8f3b695e	2254	__STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	2255	{
EricLew	0:80ee8f3b695e	2256	return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_AUTDLY));
EricLew	0:80ee8f3b695e	2257	}
EricLew	0:80ee8f3b695e	2258
EricLew	0:80ee8f3b695e	2259	/**
EricLew	0:80ee8f3b695e	2260	* @brief Set ADC selected offset number 1, 2, 3 or 4:
EricLew	0:80ee8f3b695e	2261	* * ADC channel to which the offset programmed will be applied
EricLew	0:80ee8f3b695e	2262	* (independently of channel mapped on ADC group regular
EricLew	0:80ee8f3b695e	2263	* or group injected)
EricLew	0:80ee8f3b695e	2264	* * Offset level (offset to be subtracted from the raw
EricLew	0:80ee8f3b695e	2265	* converted data).
EricLew	0:80ee8f3b695e	2266	* Caution: Offset format is dependent to ADC resolution:
EricLew	0:80ee8f3b695e	2267	* offset has to be left-aligned on bit 11, the LSB (right bits)
EricLew	0:80ee8f3b695e	2268	* are set to 0.
EricLew	0:80ee8f3b695e	2269	* @note This function enables the offset, by default. It can be forced
EricLew	0:80ee8f3b695e	2270	* to disable state using function LL_ADC_SetOffsetState().
EricLew	0:80ee8f3b695e	2271	* @note If a channel is mapped on several offsets numbers, only the offset
EricLew	0:80ee8f3b695e	2272	* with the lowest value is considered for the subtraction.
EricLew	0:80ee8f3b695e	2273	* @note On this STM32 family, setting of this feature is conditioned to
EricLew	0:80ee8f3b695e	2274	* ADC state:
EricLew	0:80ee8f3b695e	2275	* ADC must be disabled or enabled without conversion on going
EricLew	0:80ee8f3b695e	2276	* on either groups regular or injected.
EricLew	0:80ee8f3b695e	2277	* @note On STM32L4, some fast channels are available: fast analog inputs
EricLew	0:80ee8f3b695e	2278	* coming from GPIO pads (ADC_IN1..5).
EricLew	0:80ee8f3b695e	2279	* @rmtoll OFR1 OFFSET1_CH LL_ADC_SetOffset\n
EricLew	0:80ee8f3b695e	2280	* OFR1 OFFSET1 LL_ADC_SetOffset\n
EricLew	0:80ee8f3b695e	2281	* OFR1 OFFSET1_EN LL_ADC_SetOffset\n
EricLew	0:80ee8f3b695e	2282	* OFR2 OFFSET2_CH LL_ADC_SetOffset\n
EricLew	0:80ee8f3b695e	2283	* OFR2 OFFSET2 LL_ADC_SetOffset\n
EricLew	0:80ee8f3b695e	2284	* OFR2 OFFSET2_EN LL_ADC_SetOffset\n
EricLew	0:80ee8f3b695e	2285	* OFR3 OFFSET3_CH LL_ADC_SetOffset\n
EricLew	0:80ee8f3b695e	2286	* OFR3 OFFSET3 LL_ADC_SetOffset\n
EricLew	0:80ee8f3b695e	2287	* OFR3 OFFSET3_EN LL_ADC_SetOffset\n
EricLew	0:80ee8f3b695e	2288	* OFR4 OFFSET4_CH LL_ADC_SetOffset\n
EricLew	0:80ee8f3b695e	2289	* OFR4 OFFSET4 LL_ADC_SetOffset\n
EricLew	0:80ee8f3b695e	2290	* OFR4 OFFSET4_EN LL_ADC_SetOffset
EricLew	0:80ee8f3b695e	2291	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	2292	* @param Offsety This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2293	* @arg @ref LL_ADC_OFFSET_1
EricLew	0:80ee8f3b695e	2294	* @arg @ref LL_ADC_OFFSET_2
EricLew	0:80ee8f3b695e	2295	* @arg @ref LL_ADC_OFFSET_3
EricLew	0:80ee8f3b695e	2296	* @arg @ref LL_ADC_OFFSET_4
EricLew	0:80ee8f3b695e	2297	* @param Channel This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2298	* @arg @ref LL_ADC_CHANNEL_0
EricLew	0:80ee8f3b695e	2299	* @arg @ref LL_ADC_CHANNEL_1 (5)
EricLew	0:80ee8f3b695e	2300	* @arg @ref LL_ADC_CHANNEL_2 (5)
EricLew	0:80ee8f3b695e	2301	* @arg @ref LL_ADC_CHANNEL_3 (5)
EricLew	0:80ee8f3b695e	2302	* @arg @ref LL_ADC_CHANNEL_4 (5)
EricLew	0:80ee8f3b695e	2303	* @arg @ref LL_ADC_CHANNEL_5 (5)
EricLew	0:80ee8f3b695e	2304	* @arg @ref LL_ADC_CHANNEL_6
EricLew	0:80ee8f3b695e	2305	* @arg @ref LL_ADC_CHANNEL_7
EricLew	0:80ee8f3b695e	2306	* @arg @ref LL_ADC_CHANNEL_8
EricLew	0:80ee8f3b695e	2307	* @arg @ref LL_ADC_CHANNEL_9
EricLew	0:80ee8f3b695e	2308	* @arg @ref LL_ADC_CHANNEL_10
EricLew	0:80ee8f3b695e	2309	* @arg @ref LL_ADC_CHANNEL_11
EricLew	0:80ee8f3b695e	2310	* @arg @ref LL_ADC_CHANNEL_12
EricLew	0:80ee8f3b695e	2311	* @arg @ref LL_ADC_CHANNEL_13
EricLew	0:80ee8f3b695e	2312	* @arg @ref LL_ADC_CHANNEL_14
EricLew	0:80ee8f3b695e	2313	* @arg @ref LL_ADC_CHANNEL_15
EricLew	0:80ee8f3b695e	2314	* @arg @ref LL_ADC_CHANNEL_16
EricLew	0:80ee8f3b695e	2315	* @arg @ref LL_ADC_CHANNEL_17
EricLew	0:80ee8f3b695e	2316	* @arg @ref LL_ADC_CHANNEL_18
EricLew	0:80ee8f3b695e	2317	* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
EricLew	0:80ee8f3b695e	2318	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
EricLew	0:80ee8f3b695e	2319	* @arg @ref LL_ADC_CHANNEL_VBAT (4)
EricLew	0:80ee8f3b695e	2320	* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
EricLew	0:80ee8f3b695e	2321	* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
EricLew	0:80ee8f3b695e	2322	* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)
EricLew	0:80ee8f3b695e	2323	* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)
EricLew	0:80ee8f3b695e	2324	* (1) On STM32L4, parameter available only on ADC instance: ADC1.
EricLew	0:80ee8f3b695e	2325	* (2) On STM32L4, parameter available only on ADC instance: ADC2.
EricLew	0:80ee8f3b695e	2326	* (3) On STM32L4, parameter available only on ADC instance: ADC3.
EricLew	0:80ee8f3b695e	2327	* (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.
EricLew	0:80ee8f3b695e	2328	* (5) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
EricLew	0:80ee8f3b695e	2329	* Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
EricLew	0:80ee8f3b695e	2330	* @param OffsetLevel 0x000...0xFFF
EricLew	0:80ee8f3b695e	2331	* @retval None
EricLew	0:80ee8f3b695e	2332	*/
EricLew	0:80ee8f3b695e	2333	__STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef* ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel)
EricLew	0:80ee8f3b695e	2334	{
EricLew	0:80ee8f3b695e	2335	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
EricLew	0:80ee8f3b695e	2336
EricLew	0:80ee8f3b695e	2337	MODIFY_REG(*preg,
EricLew	0:80ee8f3b695e	2338	ADC_OFR1_OFFSET1_EN \| ADC_OFR1_OFFSET1_CH \| ADC_OFR1_OFFSET1,
EricLew	0:80ee8f3b695e	2339	ADC_OFR1_OFFSET1_EN \| (Channel & ADC_CHANNEL_ID_NUMBER_MASK) \| OffsetLevel);
EricLew	0:80ee8f3b695e	2340	}
EricLew	0:80ee8f3b695e	2341
EricLew	0:80ee8f3b695e	2342	/**
EricLew	0:80ee8f3b695e	2343	* @brief Get ADC selected offset number 1, 2, 3 or 4:
EricLew	0:80ee8f3b695e	2344	* * Channel to which the offset programmed will be applied
EricLew	0:80ee8f3b695e	2345	* (independently of channel mapped on ADC group regular
EricLew	0:80ee8f3b695e	2346	* or group injected)
EricLew	0:80ee8f3b695e	2347	* @note Usage of the returned channel number:
EricLew	0:80ee8f3b695e	2348	* - To reinject this channel into another function LL_ADC_xxx:
EricLew	0:80ee8f3b695e	2349	* the returned channel number is only partly formatted on definition
EricLew	0:80ee8f3b695e	2350	* of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
EricLew	0:80ee8f3b695e	2351	* with literals LL_ADC_CHANNEL_x, then the selected
EricLew	0:80ee8f3b695e	2352	* literal LL_ADC_CHANNEL_x can be used as parameter for another
EricLew	0:80ee8f3b695e	2353	* function.
EricLew	0:80ee8f3b695e	2354	* - To get the channel number in decimal format:
EricLew	0:80ee8f3b695e	2355	* process the returned value with the helper macro
EricLew	0:80ee8f3b695e	2356	* @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
EricLew	0:80ee8f3b695e	2357	* @note On STM32L4, some fast channels are available: fast analog inputs
EricLew	0:80ee8f3b695e	2358	* coming from GPIO pads (ADC_IN1..5).
EricLew	0:80ee8f3b695e	2359	* @rmtoll OFR1 OFFSET1_CH LL_ADC_GetOffsetChannel\n
EricLew	0:80ee8f3b695e	2360	* OFR2 OFFSET2_CH LL_ADC_GetOffsetChannel\n
EricLew	0:80ee8f3b695e	2361	* OFR3 OFFSET3_CH LL_ADC_GetOffsetChannel\n
EricLew	0:80ee8f3b695e	2362	* OFR4 OFFSET4_CH LL_ADC_GetOffsetChannel
EricLew	0:80ee8f3b695e	2363	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	2364	* @param Offsety This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2365	* @arg @ref LL_ADC_OFFSET_1
EricLew	0:80ee8f3b695e	2366	* @arg @ref LL_ADC_OFFSET_2
EricLew	0:80ee8f3b695e	2367	* @arg @ref LL_ADC_OFFSET_3
EricLew	0:80ee8f3b695e	2368	* @arg @ref LL_ADC_OFFSET_4
EricLew	0:80ee8f3b695e	2369	* @retval Returned value can be one of the following values:
EricLew	0:80ee8f3b695e	2370	* @arg @ref LL_ADC_CHANNEL_0
EricLew	0:80ee8f3b695e	2371	* @arg @ref LL_ADC_CHANNEL_1 (5)
EricLew	0:80ee8f3b695e	2372	* @arg @ref LL_ADC_CHANNEL_2 (5)
EricLew	0:80ee8f3b695e	2373	* @arg @ref LL_ADC_CHANNEL_3 (5)
EricLew	0:80ee8f3b695e	2374	* @arg @ref LL_ADC_CHANNEL_4 (5)
EricLew	0:80ee8f3b695e	2375	* @arg @ref LL_ADC_CHANNEL_5 (5)
EricLew	0:80ee8f3b695e	2376	* @arg @ref LL_ADC_CHANNEL_6
EricLew	0:80ee8f3b695e	2377	* @arg @ref LL_ADC_CHANNEL_7
EricLew	0:80ee8f3b695e	2378	* @arg @ref LL_ADC_CHANNEL_8
EricLew	0:80ee8f3b695e	2379	* @arg @ref LL_ADC_CHANNEL_9
EricLew	0:80ee8f3b695e	2380	* @arg @ref LL_ADC_CHANNEL_10
EricLew	0:80ee8f3b695e	2381	* @arg @ref LL_ADC_CHANNEL_11
EricLew	0:80ee8f3b695e	2382	* @arg @ref LL_ADC_CHANNEL_12
EricLew	0:80ee8f3b695e	2383	* @arg @ref LL_ADC_CHANNEL_13
EricLew	0:80ee8f3b695e	2384	* @arg @ref LL_ADC_CHANNEL_14
EricLew	0:80ee8f3b695e	2385	* @arg @ref LL_ADC_CHANNEL_15
EricLew	0:80ee8f3b695e	2386	* @arg @ref LL_ADC_CHANNEL_16
EricLew	0:80ee8f3b695e	2387	* @arg @ref LL_ADC_CHANNEL_17
EricLew	0:80ee8f3b695e	2388	* @arg @ref LL_ADC_CHANNEL_18
EricLew	0:80ee8f3b695e	2389	* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
EricLew	0:80ee8f3b695e	2390	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
EricLew	0:80ee8f3b695e	2391	* @arg @ref LL_ADC_CHANNEL_VBAT (4)
EricLew	0:80ee8f3b695e	2392	* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
EricLew	0:80ee8f3b695e	2393	* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
EricLew	0:80ee8f3b695e	2394	* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)
EricLew	0:80ee8f3b695e	2395	* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)
EricLew	0:80ee8f3b695e	2396	* (1) On STM32L4, parameter available only on ADC instance: ADC1.
EricLew	0:80ee8f3b695e	2397	* (2) On STM32L4, parameter available only on ADC instance: ADC2.
EricLew	0:80ee8f3b695e	2398	* (3) On STM32L4, parameter available only on ADC instance: ADC3.
EricLew	0:80ee8f3b695e	2399	* (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.
EricLew	0:80ee8f3b695e	2400	* (5) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
EricLew	0:80ee8f3b695e	2401	* Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
EricLew	0:80ee8f3b695e	2402	* (1, 2, 3, 4) For ADC channel read back from ADC register,
EricLew	0:80ee8f3b695e	2403	* comparison with internal channel parameter to be done
EricLew	0:80ee8f3b695e	2404	* using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
EricLew	0:80ee8f3b695e	2405	*/
EricLew	0:80ee8f3b695e	2406	__STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(ADC_TypeDef *ADCx, uint32_t Offsety)
EricLew	0:80ee8f3b695e	2407	{
EricLew	0:80ee8f3b695e	2408	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
EricLew	0:80ee8f3b695e	2409
EricLew	0:80ee8f3b695e	2410	return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH);
EricLew	0:80ee8f3b695e	2411	}
EricLew	0:80ee8f3b695e	2412
EricLew	0:80ee8f3b695e	2413	/**
EricLew	0:80ee8f3b695e	2414	* @brief Get ADC instance selected offset number 1, 2, 3 or 4:
EricLew	0:80ee8f3b695e	2415	* * Offset level (offset to be subtracted from the raw
EricLew	0:80ee8f3b695e	2416	* converted data).
EricLew	0:80ee8f3b695e	2417	* Caution: Offset format is dependent to ADC resolution:
EricLew	0:80ee8f3b695e	2418	* offset has to be left-aligned on bit 11, the LSB (right bits)
EricLew	0:80ee8f3b695e	2419	* are set to 0.
EricLew	0:80ee8f3b695e	2420	* @rmtoll OFR1 OFFSET1 LL_ADC_GetOffsetLevel\n
EricLew	0:80ee8f3b695e	2421	* OFR2 OFFSET2 LL_ADC_GetOffsetLevel\n
EricLew	0:80ee8f3b695e	2422	* OFR3 OFFSET3 LL_ADC_GetOffsetLevel\n
EricLew	0:80ee8f3b695e	2423	* OFR4 OFFSET4 LL_ADC_GetOffsetLevel
EricLew	0:80ee8f3b695e	2424	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	2425	* @param Offsety This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2426	* @arg @ref LL_ADC_OFFSET_1
EricLew	0:80ee8f3b695e	2427	* @arg @ref LL_ADC_OFFSET_2
EricLew	0:80ee8f3b695e	2428	* @arg @ref LL_ADC_OFFSET_3
EricLew	0:80ee8f3b695e	2429	* @arg @ref LL_ADC_OFFSET_4
EricLew	0:80ee8f3b695e	2430	* @retval 0x000...0xFFF
EricLew	0:80ee8f3b695e	2431	*/
EricLew	0:80ee8f3b695e	2432	__STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(ADC_TypeDef *ADCx, uint32_t Offsety)
EricLew	0:80ee8f3b695e	2433	{
EricLew	0:80ee8f3b695e	2434	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
EricLew	0:80ee8f3b695e	2435
EricLew	0:80ee8f3b695e	2436	return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1);
EricLew	0:80ee8f3b695e	2437	}
EricLew	0:80ee8f3b695e	2438
EricLew	0:80ee8f3b695e	2439	/**
EricLew	0:80ee8f3b695e	2440	* @brief Set ADC instance selected offset number 1, 2, 3 or 4:
EricLew	0:80ee8f3b695e	2441	* * Force offset disable (or enable) without modifying offset channel
EricLew	0:80ee8f3b695e	2442	* or value.
EricLew	0:80ee8f3b695e	2443	* @note This function should be needed only in case of offset to be
EricLew	0:80ee8f3b695e	2444	* enabled-disabled dynamically, and should not be needed in other cases:
EricLew	0:80ee8f3b695e	2445	* function LL_ADC_SetOffset() automatically enables the offset.
EricLew	0:80ee8f3b695e	2446	* @note On this STM32 family, setting of this feature is conditioned to
EricLew	0:80ee8f3b695e	2447	* ADC state:
EricLew	0:80ee8f3b695e	2448	* ADC must be disabled or enabled without conversion on going
EricLew	0:80ee8f3b695e	2449	* on either groups regular or injected.
EricLew	0:80ee8f3b695e	2450	* @rmtoll OFR1 OFFSET1_EN LL_ADC_SetOffsetState\n
EricLew	0:80ee8f3b695e	2451	* OFR2 OFFSET2_EN LL_ADC_SetOffsetState\n
EricLew	0:80ee8f3b695e	2452	* OFR3 OFFSET3_EN LL_ADC_SetOffsetState\n
EricLew	0:80ee8f3b695e	2453	* OFR4 OFFSET4_EN LL_ADC_SetOffsetState
EricLew	0:80ee8f3b695e	2454	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	2455	* @param Offsety This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2456	* @arg @ref LL_ADC_OFFSET_1
EricLew	0:80ee8f3b695e	2457	* @arg @ref LL_ADC_OFFSET_2
EricLew	0:80ee8f3b695e	2458	* @arg @ref LL_ADC_OFFSET_3
EricLew	0:80ee8f3b695e	2459	* @arg @ref LL_ADC_OFFSET_4
EricLew	0:80ee8f3b695e	2460	* @param OffsetState This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2461	* @arg @ref LL_ADC_OFFSET_DISABLE
EricLew	0:80ee8f3b695e	2462	* @arg @ref LL_ADC_OFFSET_ENABLE
EricLew	0:80ee8f3b695e	2463	* @retval None
EricLew	0:80ee8f3b695e	2464	*/
EricLew	0:80ee8f3b695e	2465	__STATIC_INLINE void LL_ADC_SetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetState)
EricLew	0:80ee8f3b695e	2466	{
EricLew	0:80ee8f3b695e	2467	register uint32_t preg = (uint32_t )((uint32_t)
EricLew	0:80ee8f3b695e	2468	((uint32_t)(&ADCx->OFR1) + (Offsety*4)));
EricLew	0:80ee8f3b695e	2469
EricLew	0:80ee8f3b695e	2470	MODIFY_REG(*preg,
EricLew	0:80ee8f3b695e	2471	ADC_OFR1_OFFSET1_EN,
EricLew	0:80ee8f3b695e	2472	OffsetState);
EricLew	0:80ee8f3b695e	2473	}
EricLew	0:80ee8f3b695e	2474
EricLew	0:80ee8f3b695e	2475	/**
EricLew	0:80ee8f3b695e	2476	* @brief Get ADC instance selected offset number 1, 2, 3 or 4:
EricLew	0:80ee8f3b695e	2477	* * Get offset state disabled or enabled.
EricLew	0:80ee8f3b695e	2478	* @rmtoll OFR1 OFFSET1_EN LL_ADC_GetOffsetState\n
EricLew	0:80ee8f3b695e	2479	* OFR2 OFFSET2_EN LL_ADC_GetOffsetState\n
EricLew	0:80ee8f3b695e	2480	* OFR3 OFFSET3_EN LL_ADC_GetOffsetState\n
EricLew	0:80ee8f3b695e	2481	* OFR4 OFFSET4_EN LL_ADC_GetOffsetState
EricLew	0:80ee8f3b695e	2482	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	2483	* @param Offsety This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2484	* @arg @ref LL_ADC_OFFSET_1
EricLew	0:80ee8f3b695e	2485	* @arg @ref LL_ADC_OFFSET_2
EricLew	0:80ee8f3b695e	2486	* @arg @ref LL_ADC_OFFSET_3
EricLew	0:80ee8f3b695e	2487	* @arg @ref LL_ADC_OFFSET_4
EricLew	0:80ee8f3b695e	2488	* @retval Returned value can be one of the following values:
EricLew	0:80ee8f3b695e	2489	* @arg @ref LL_ADC_OFFSET_DISABLE
EricLew	0:80ee8f3b695e	2490	* @arg @ref LL_ADC_OFFSET_ENABLE
EricLew	0:80ee8f3b695e	2491	*/
EricLew	0:80ee8f3b695e	2492	__STATIC_INLINE uint32_t LL_ADC_GetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety)
EricLew	0:80ee8f3b695e	2493	{
EricLew	0:80ee8f3b695e	2494	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
EricLew	0:80ee8f3b695e	2495
EricLew	0:80ee8f3b695e	2496	return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_EN);
EricLew	0:80ee8f3b695e	2497	}
EricLew	0:80ee8f3b695e	2498
EricLew	0:80ee8f3b695e	2499	/**
EricLew	0:80ee8f3b695e	2500	* @}
EricLew	0:80ee8f3b695e	2501	*/
EricLew	0:80ee8f3b695e	2502
EricLew	0:80ee8f3b695e	2503	/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular
EricLew	0:80ee8f3b695e	2504	* @{
EricLew	0:80ee8f3b695e	2505	*/
EricLew	0:80ee8f3b695e	2506
EricLew	0:80ee8f3b695e	2507	/**
EricLew	0:80ee8f3b695e	2508	* @brief Set ADC group regular conversion trigger source:
EricLew	0:80ee8f3b695e	2509	* internal (SW start) or external from timer or external interrupt.
EricLew	0:80ee8f3b695e	2510	* @note Setting trigger source to external trigger also set trigger polarity
EricLew	0:80ee8f3b695e	2511	* to rising edge
EricLew	0:80ee8f3b695e	2512	* (default setting for compatibility with some ADC on other
EricLew	0:80ee8f3b695e	2513	* STM32 families having this setting set by HW default value).
EricLew	0:80ee8f3b695e	2514	* In case of need to modify trigger edge, use
EricLew	0:80ee8f3b695e	2515	* function @ref LL_ADC_REG_SetTrigEdge().
EricLew	0:80ee8f3b695e	2516	* @note On this STM32 family, setting of this feature is conditioned to
EricLew	0:80ee8f3b695e	2517	* ADC state:
EricLew	0:80ee8f3b695e	2518	* ADC must be disabled or enabled without conversion on going
EricLew	0:80ee8f3b695e	2519	* on group regular.
EricLew	0:80ee8f3b695e	2520	* @rmtoll CFGR EXTSEL LL_ADC_REG_SetTrigSource\n
EricLew	0:80ee8f3b695e	2521	* CFGR EXTEN LL_ADC_REG_SetTrigSource
EricLew	0:80ee8f3b695e	2522	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	2523	* @param TriggerSource This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2524	* @arg @ref LL_ADC_REG_TRIG_SW_START
EricLew	0:80ee8f3b695e	2525	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
EricLew	0:80ee8f3b695e	2526	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
EricLew	0:80ee8f3b695e	2527	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CC1
EricLew	0:80ee8f3b695e	2528	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CC2
EricLew	0:80ee8f3b695e	2529	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CC3
EricLew	0:80ee8f3b695e	2530	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
EricLew	0:80ee8f3b695e	2531	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CC2
EricLew	0:80ee8f3b695e	2532	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
EricLew	0:80ee8f3b695e	2533	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CC4
EricLew	0:80ee8f3b695e	2534	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO
EricLew	0:80ee8f3b695e	2535	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CC4
EricLew	0:80ee8f3b695e	2536	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
EricLew	0:80ee8f3b695e	2537	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
EricLew	0:80ee8f3b695e	2538	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2
EricLew	0:80ee8f3b695e	2539	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO
EricLew	0:80ee8f3b695e	2540	* @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
EricLew	0:80ee8f3b695e	2541	* @retval None
EricLew	0:80ee8f3b695e	2542	*/
EricLew	0:80ee8f3b695e	2543	__STATIC_INLINE void LL_ADC_REG_SetTrigSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
EricLew	0:80ee8f3b695e	2544	{
EricLew	0:80ee8f3b695e	2545	MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN \| ADC_CFGR_EXTSEL, TriggerSource);
EricLew	0:80ee8f3b695e	2546	}
EricLew	0:80ee8f3b695e	2547
EricLew	0:80ee8f3b695e	2548	/**
EricLew	0:80ee8f3b695e	2549	* @brief Get ADC group regular conversion trigger source:
EricLew	0:80ee8f3b695e	2550	* internal (SW start) or external from timer or external interrupt.
EricLew	0:80ee8f3b695e	2551	* @note To determine whether group regular trigger source is
EricLew	0:80ee8f3b695e	2552	* internal (SW start) or external, without detail
EricLew	0:80ee8f3b695e	2553	* of which peripheral is selected as external trigger,
EricLew	0:80ee8f3b695e	2554	* (equivalent to
EricLew	0:80ee8f3b695e	2555	* " if(LL_ADC_REG_GetTrigSource(ADC1) == LL_ADC_REG_TRIG_SW_START) ")
EricLew	0:80ee8f3b695e	2556	* use function @ref LL_ADC_REG_IsTrigSourceSWStart.
EricLew	0:80ee8f3b695e	2557	* @rmtoll CFGR EXTSEL LL_ADC_REG_GetTrigSource\n
EricLew	0:80ee8f3b695e	2558	* CFGR EXTEN LL_ADC_REG_GetTrigSource
EricLew	0:80ee8f3b695e	2559	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	2560	* @retval Returned value can be one of the following values:
EricLew	0:80ee8f3b695e	2561	* @arg @ref LL_ADC_REG_TRIG_SW_START
EricLew	0:80ee8f3b695e	2562	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
EricLew	0:80ee8f3b695e	2563	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
EricLew	0:80ee8f3b695e	2564	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CC1
EricLew	0:80ee8f3b695e	2565	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CC2
EricLew	0:80ee8f3b695e	2566	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CC3
EricLew	0:80ee8f3b695e	2567	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
EricLew	0:80ee8f3b695e	2568	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CC2
EricLew	0:80ee8f3b695e	2569	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
EricLew	0:80ee8f3b695e	2570	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CC4
EricLew	0:80ee8f3b695e	2571	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO
EricLew	0:80ee8f3b695e	2572	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CC4
EricLew	0:80ee8f3b695e	2573	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
EricLew	0:80ee8f3b695e	2574	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
EricLew	0:80ee8f3b695e	2575	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2
EricLew	0:80ee8f3b695e	2576	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO
EricLew	0:80ee8f3b695e	2577	* @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
EricLew	0:80ee8f3b695e	2578	*/
EricLew	0:80ee8f3b695e	2579	__STATIC_INLINE uint32_t LL_ADC_REG_GetTrigSource(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	2580	{
EricLew	0:80ee8f3b695e	2581	register uint32_t TriggerSource = READ_BIT(ADCx->CFGR, ADC_CFGR_EXTSEL \| ADC_CFGR_EXTEN);
EricLew	0:80ee8f3b695e	2582
EricLew	0:80ee8f3b695e	2583	/* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
EricLew	0:80ee8f3b695e	2584	/* corresponding to ADC_CFGR_EXTEN {0; 1; 2; 3}. */
EricLew	0:80ee8f3b695e	2585	register uint32_t ShiftExten = ((TriggerSource & ADC_CFGR_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2));
EricLew	0:80ee8f3b695e	2586
EricLew	0:80ee8f3b695e	2587	/* Set bitfield corresponding to ADC_CFGR_EXTEN and ADC_CFGR_EXTSEL */
EricLew	0:80ee8f3b695e	2588	/* to match with triggers literals definition. */
EricLew	0:80ee8f3b695e	2589	return ((TriggerSource
EricLew	0:80ee8f3b695e	2590	& (ADC_REG_TRIG_SOURCE_MASK >> ShiftExten) & ADC_CFGR_EXTSEL)
EricLew	0:80ee8f3b695e	2591	\| ((ADC_REG_TRIG_EDGE_MASK >> ShiftExten) & ADC_CFGR_EXTEN)
EricLew	0:80ee8f3b695e	2592	);
EricLew	0:80ee8f3b695e	2593	}
EricLew	0:80ee8f3b695e	2594
EricLew	0:80ee8f3b695e	2595	/**
EricLew	0:80ee8f3b695e	2596	* @brief Get ADC group regular conversion trigger source:
EricLew	0:80ee8f3b695e	2597	* (0: trigger source external trigger, 1: trigger source SW start).
EricLew	0:80ee8f3b695e	2598	* @note In case of group regular trigger source set to external trigger,
EricLew	0:80ee8f3b695e	2599	* to determine which peripheral is selected as external trigger,
EricLew	0:80ee8f3b695e	2600	* use function @ref LL_ADC_REG_GetTrigSource().
EricLew	0:80ee8f3b695e	2601	* @rmtoll CFGR EXTEN LL_ADC_REG_IsTrigSourceSWStart
EricLew	0:80ee8f3b695e	2602	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	2603	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	2604	*/
EricLew	0:80ee8f3b695e	2605	__STATIC_INLINE uint32_t LL_ADC_REG_IsTrigSourceSWStart(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	2606	{
EricLew	0:80ee8f3b695e	2607	return (READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SW_START & ADC_CFGR_EXTEN));
EricLew	0:80ee8f3b695e	2608	}
EricLew	0:80ee8f3b695e	2609
EricLew	0:80ee8f3b695e	2610	/**
EricLew	0:80ee8f3b695e	2611	* @brief Set ADC group regular conversion trigger polarity.
EricLew	0:80ee8f3b695e	2612	* Applicable only for trigger source set to external trigger.
EricLew	0:80ee8f3b695e	2613	* @note On this STM32 family, setting of this feature is conditioned to
EricLew	0:80ee8f3b695e	2614	* ADC state:
EricLew	0:80ee8f3b695e	2615	* ADC must be disabled or enabled without conversion on going
EricLew	0:80ee8f3b695e	2616	* on group regular.
EricLew	0:80ee8f3b695e	2617	* @rmtoll CFGR EXTEN LL_ADC_REG_SetTrigEdge
EricLew	0:80ee8f3b695e	2618	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	2619	* @param ExternalTriggerEdge This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2620	* @arg @ref LL_ADC_REG_TRIG_EXT_RISING
EricLew	0:80ee8f3b695e	2621	* @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
EricLew	0:80ee8f3b695e	2622	* @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
EricLew	0:80ee8f3b695e	2623	* @retval None
EricLew	0:80ee8f3b695e	2624	*/
EricLew	0:80ee8f3b695e	2625	__STATIC_INLINE void LL_ADC_REG_SetTrigEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
EricLew	0:80ee8f3b695e	2626	{
EricLew	0:80ee8f3b695e	2627	MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN, ExternalTriggerEdge);
EricLew	0:80ee8f3b695e	2628	}
EricLew	0:80ee8f3b695e	2629
EricLew	0:80ee8f3b695e	2630	/**
EricLew	0:80ee8f3b695e	2631	* @brief Get ADC group regular conversion trigger polarity.
EricLew	0:80ee8f3b695e	2632	* Applicable only for trigger source set to external trigger.
EricLew	0:80ee8f3b695e	2633	* @rmtoll CFGR EXTEN LL_ADC_REG_GetTrigEdge
EricLew	0:80ee8f3b695e	2634	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	2635	* @retval Returned value can be one of the following values:
EricLew	0:80ee8f3b695e	2636	* @arg @ref LL_ADC_REG_TRIG_EXT_RISING
EricLew	0:80ee8f3b695e	2637	* @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
EricLew	0:80ee8f3b695e	2638	* @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
EricLew	0:80ee8f3b695e	2639	*/
EricLew	0:80ee8f3b695e	2640	__STATIC_INLINE uint32_t LL_ADC_REG_GetTrigEdge(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	2641	{
EricLew	0:80ee8f3b695e	2642	return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN));
EricLew	0:80ee8f3b695e	2643	}
EricLew	0:80ee8f3b695e	2644
EricLew	0:80ee8f3b695e	2645	/**
EricLew	0:80ee8f3b695e	2646	* @brief Set ADC continuous conversion mode on ADC group regular:
EricLew	0:80ee8f3b695e	2647	* whether ADC conversions are performed:
EricLew	0:80ee8f3b695e	2648	* * single mode: one conversion per trigger
EricLew	0:80ee8f3b695e	2649	* * continuous mode: after the first trigger, following
EricLew	0:80ee8f3b695e	2650	* conversions launched successively automatically.
EricLew	0:80ee8f3b695e	2651	* @note It is not possible to enable both ADC continuous mode
EricLew	0:80ee8f3b695e	2652	* and ADC group regular discontinuous mode.
EricLew	0:80ee8f3b695e	2653	* @note On this STM32 family, setting of this feature is conditioned to
EricLew	0:80ee8f3b695e	2654	* ADC state:
EricLew	0:80ee8f3b695e	2655	* ADC must be disabled or enabled without conversion on going
EricLew	0:80ee8f3b695e	2656	* on group regular.
EricLew	0:80ee8f3b695e	2657	* @rmtoll CFGR CONT LL_ADC_REG_SetContinuousMode
EricLew	0:80ee8f3b695e	2658	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	2659	* @param Continuous This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2660	* @arg @ref LL_ADC_REG_CONV_SINGLE
EricLew	0:80ee8f3b695e	2661	* @arg @ref LL_ADC_REG_CONV_CONTINUOUS
EricLew	0:80ee8f3b695e	2662	* @retval None
EricLew	0:80ee8f3b695e	2663	*/
EricLew	0:80ee8f3b695e	2664	__STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
EricLew	0:80ee8f3b695e	2665	{
EricLew	0:80ee8f3b695e	2666	MODIFY_REG(ADCx->CFGR, ADC_CFGR_CONT, Continuous);
EricLew	0:80ee8f3b695e	2667	}
EricLew	0:80ee8f3b695e	2668
EricLew	0:80ee8f3b695e	2669	/**
EricLew	0:80ee8f3b695e	2670	* @brief Get ADC continuous conversion mode on ADC group regular:
EricLew	0:80ee8f3b695e	2671	* whether ADC conversions are performed:
EricLew	0:80ee8f3b695e	2672	* * single mode: one conversion per trigger
EricLew	0:80ee8f3b695e	2673	* * continuous mode: after the first trigger, following
EricLew	0:80ee8f3b695e	2674	* conversions launched successively automatically.
EricLew	0:80ee8f3b695e	2675	* @rmtoll CFGR CONT LL_ADC_REG_GetContinuousMode
EricLew	0:80ee8f3b695e	2676	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	2677	* @retval Returned value can be one of the following values:
EricLew	0:80ee8f3b695e	2678	* @arg @ref LL_ADC_REG_CONV_SINGLE
EricLew	0:80ee8f3b695e	2679	* @arg @ref LL_ADC_REG_CONV_CONTINUOUS
EricLew	0:80ee8f3b695e	2680	*/
EricLew	0:80ee8f3b695e	2681	__STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	2682	{
EricLew	0:80ee8f3b695e	2683	return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_CONT));
EricLew	0:80ee8f3b695e	2684	}
EricLew	0:80ee8f3b695e	2685
EricLew	0:80ee8f3b695e	2686	/**
EricLew	0:80ee8f3b695e	2687	* @brief Set ADC group regular conversion data transfer: no transfer or transfer by DMA.
EricLew	0:80ee8f3b695e	2688	* If transfer by DMA selected, specifies the DMA requests
EricLew	0:80ee8f3b695e	2689	* mode:
EricLew	0:80ee8f3b695e	2690	* * Limited mode (One shot mode): DMA transfer requests are stopped
EricLew	0:80ee8f3b695e	2691	* when number of DMA data transfers (number of
EricLew	0:80ee8f3b695e	2692	* ADC conversions) is reached.
EricLew	0:80ee8f3b695e	2693	* This ADC mode is intended to be used with DMA mode non-circular.
EricLew	0:80ee8f3b695e	2694	* * Unlimited mode: DMA transfer requests are unlimited,
EricLew	0:80ee8f3b695e	2695	* whatever number of DMA data transfers (number of
EricLew	0:80ee8f3b695e	2696	* ADC conversions).
EricLew	0:80ee8f3b695e	2697	* This ADC mode is intended to be used with DMA mode circular.
EricLew	0:80ee8f3b695e	2698	* @note If ADC DMA requests mode is set to unlimited and DMA is set to
EricLew	0:80ee8f3b695e	2699	* mode non-circular:
EricLew	0:80ee8f3b695e	2700	* when DMA transfers size will be reached, DMA will stop transfers of
EricLew	0:80ee8f3b695e	2701	* ADC conversions data ADC will raise an overrun error
EricLew	0:80ee8f3b695e	2702	* (overrun flag and interruption if enabled).
EricLew	0:80ee8f3b695e	2703	* @note For devices with several ADC instances: ADC multimode DMA
EricLew	0:80ee8f3b695e	2704	* settings are available using function @ref LL_ADC_SetMultiDMATransfer().
EricLew	0:80ee8f3b695e	2705	* @note To configure DMA source address (peripheral address),
EricLew	0:80ee8f3b695e	2706	* use function @ref LL_ADC_DMA_GetRegAddr().
EricLew	0:80ee8f3b695e	2707	* @note On this STM32 family, setting of this feature is conditioned to
EricLew	0:80ee8f3b695e	2708	* ADC state:
EricLew	0:80ee8f3b695e	2709	* ADC must be disabled or enabled without conversion on going
EricLew	0:80ee8f3b695e	2710	* on either groups regular or injected.
EricLew	0:80ee8f3b695e	2711	* @rmtoll CFGR DMAEN LL_ADC_REG_SetDMATransfer\n
EricLew	0:80ee8f3b695e	2712	* CFGR DMACFG LL_ADC_REG_SetDMATransfer
EricLew	0:80ee8f3b695e	2713	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	2714	* @param DMATransfer This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2715	* @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
EricLew	0:80ee8f3b695e	2716	* @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
EricLew	0:80ee8f3b695e	2717	* @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
EricLew	0:80ee8f3b695e	2718	* @retval None
EricLew	0:80ee8f3b695e	2719	*/
EricLew	0:80ee8f3b695e	2720	__STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer)
EricLew	0:80ee8f3b695e	2721	{
EricLew	0:80ee8f3b695e	2722	MODIFY_REG(ADCx->CFGR, ADC_CFGR_DMAEN \| ADC_CFGR_DMACFG, DMATransfer);
EricLew	0:80ee8f3b695e	2723	}
EricLew	0:80ee8f3b695e	2724
EricLew	0:80ee8f3b695e	2725	/**
EricLew	0:80ee8f3b695e	2726	* @brief Get ADC group regular conversion data transfer: no transfer or transfer by DMA.
EricLew	0:80ee8f3b695e	2727	* If transfer by DMA selected, specifies the DMA requests
EricLew	0:80ee8f3b695e	2728	* mode:
EricLew	0:80ee8f3b695e	2729	* * Limited mode (One shot mode): DMA transfer requests are stopped
EricLew	0:80ee8f3b695e	2730	* when number of DMA data transfers (number of
EricLew	0:80ee8f3b695e	2731	* ADC conversions) is reached.
EricLew	0:80ee8f3b695e	2732	* This ADC mode is intended to be used with DMA mode non-circular.
EricLew	0:80ee8f3b695e	2733	* * Unlimited mode: DMA transfer requests are unlimited,
EricLew	0:80ee8f3b695e	2734	* whatever number of DMA data transfers (number of
EricLew	0:80ee8f3b695e	2735	* ADC conversions).
EricLew	0:80ee8f3b695e	2736	* This ADC mode is intended to be used with DMA mode circular.
EricLew	0:80ee8f3b695e	2737	* @note If ADC DMA requests mode is set to unlimited and DMA is set to
EricLew	0:80ee8f3b695e	2738	* mode non-circular:
EricLew	0:80ee8f3b695e	2739	* when DMA transfers size will be reached, DMA will stop transfers of
EricLew	0:80ee8f3b695e	2740	* ADC conversions data ADC will raise an overrun error
EricLew	0:80ee8f3b695e	2741	* (overrun flag and interruption if enabled).
EricLew	0:80ee8f3b695e	2742	* @note For devices with several ADC instances: ADC multimode DMA
EricLew	0:80ee8f3b695e	2743	* settings are available using function @ref LL_ADC_GetMultiDMATransfer().
EricLew	0:80ee8f3b695e	2744	* @note To configure DMA source address (peripheral address),
EricLew	0:80ee8f3b695e	2745	* use function @ref LL_ADC_DMA_GetRegAddr().
EricLew	0:80ee8f3b695e	2746	* @rmtoll CFGR DMAEN LL_ADC_REG_GetDMATransfer\n
EricLew	0:80ee8f3b695e	2747	* CFGR DMACFG LL_ADC_REG_GetDMATransfer
EricLew	0:80ee8f3b695e	2748	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	2749	* @retval Returned value can be one of the following values:
EricLew	0:80ee8f3b695e	2750	* @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
EricLew	0:80ee8f3b695e	2751	* @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
EricLew	0:80ee8f3b695e	2752	* @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
EricLew	0:80ee8f3b695e	2753	*/
EricLew	0:80ee8f3b695e	2754	__STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	2755	{
EricLew	0:80ee8f3b695e	2756	return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DMAEN \| ADC_CFGR_DMACFG));
EricLew	0:80ee8f3b695e	2757	}
EricLew	0:80ee8f3b695e	2758
EricLew	0:80ee8f3b695e	2759	/**
EricLew	0:80ee8f3b695e	2760	* @brief Set ADC group regular behaviour in case of overrun:
EricLew	0:80ee8f3b695e	2761	* data preserved or overwritten.
EricLew	0:80ee8f3b695e	2762	* @note Compatibility with devices without feature overrun:
EricLew	0:80ee8f3b695e	2763	* other devices without this feature have a behaviour
EricLew	0:80ee8f3b695e	2764	* equivalent to data overwritten.
EricLew	0:80ee8f3b695e	2765	* The default setting of overrun is data preserved.
EricLew	0:80ee8f3b695e	2766	* Therefore, for compatibility with all devices, parameter
EricLew	0:80ee8f3b695e	2767	* overrun should be set to data overwritten.
EricLew	0:80ee8f3b695e	2768	* @note On this STM32 family, setting of this feature is conditioned to
EricLew	0:80ee8f3b695e	2769	* ADC state:
EricLew	0:80ee8f3b695e	2770	* ADC must be disabled or enabled without conversion on going
EricLew	0:80ee8f3b695e	2771	* on group regular.
EricLew	0:80ee8f3b695e	2772	* @rmtoll CFGR OVRMOD LL_ADC_REG_SetOverrun
EricLew	0:80ee8f3b695e	2773	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	2774	* @param Overrun This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2775	* @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
EricLew	0:80ee8f3b695e	2776	* @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
EricLew	0:80ee8f3b695e	2777	* @retval None
EricLew	0:80ee8f3b695e	2778	*/
EricLew	0:80ee8f3b695e	2779	__STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun)
EricLew	0:80ee8f3b695e	2780	{
EricLew	0:80ee8f3b695e	2781	MODIFY_REG(ADCx->CFGR, ADC_CFGR_OVRMOD, Overrun);
EricLew	0:80ee8f3b695e	2782	}
EricLew	0:80ee8f3b695e	2783
EricLew	0:80ee8f3b695e	2784	/**
EricLew	0:80ee8f3b695e	2785	* @brief Get ADC group regular behaviour in case of overrun:
EricLew	0:80ee8f3b695e	2786	* data preserved or overwritten.
EricLew	0:80ee8f3b695e	2787	* @rmtoll CFGR OVRMOD LL_ADC_REG_GetOverrun
EricLew	0:80ee8f3b695e	2788	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	2789	* @retval Returned value can be one of the following values:
EricLew	0:80ee8f3b695e	2790	* @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
EricLew	0:80ee8f3b695e	2791	* @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
EricLew	0:80ee8f3b695e	2792	*/
EricLew	0:80ee8f3b695e	2793	__STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	2794	{
EricLew	0:80ee8f3b695e	2795	return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_OVRMOD));
EricLew	0:80ee8f3b695e	2796	}
EricLew	0:80ee8f3b695e	2797
EricLew	0:80ee8f3b695e	2798	/**
EricLew	0:80ee8f3b695e	2799	* @brief Set ADC group regular sequencer length and scan direction.
EricLew	0:80ee8f3b695e	2800	* * For devices with sequencer fully configurable
EricLew	0:80ee8f3b695e	2801	* (function "LL_ADC_REG_SetSequencerRanks()" available):
EricLew	0:80ee8f3b695e	2802	* sequencer length and each rank affectation to a channel
EricLew	0:80ee8f3b695e	2803	* are configurable.
EricLew	0:80ee8f3b695e	2804	* This function performs:
EricLew	0:80ee8f3b695e	2805	* - Sequence length: Set number of ranks in the scan sequence.
EricLew	0:80ee8f3b695e	2806	* - Sequence direction: Unless specified in parameters, sequencer
EricLew	0:80ee8f3b695e	2807	* scan direction is forward (from rank 1 to rank n).
EricLew	0:80ee8f3b695e	2808	* Sequencer ranks are selected using
EricLew	0:80ee8f3b695e	2809	* function "LL_ADC_REG_SetSequencerRanks()".
EricLew	0:80ee8f3b695e	2810	* * For devices with sequencer not fully configurable
EricLew	0:80ee8f3b695e	2811	* (function "LL_ADC_REG_SetSequencerChannels()" available):
EricLew	0:80ee8f3b695e	2812	* sequencer length and each rank affectation to a channel
EricLew	0:80ee8f3b695e	2813	* are defined by channel number.
EricLew	0:80ee8f3b695e	2814	* This function performs:
EricLew	0:80ee8f3b695e	2815	* - Sequence length: Number of ranks in the scan sequence is
EricLew	0:80ee8f3b695e	2816	* defined by number of channels set in the sequence,
EricLew	0:80ee8f3b695e	2817	* rank of each channel is fixed by channel HW number.
EricLew	0:80ee8f3b695e	2818	* (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
EricLew	0:80ee8f3b695e	2819	* - Sequence direction: Unless specified in parameters, sequencer
EricLew	0:80ee8f3b695e	2820	* scan direction is forward (from lowest channel number to
EricLew	0:80ee8f3b695e	2821	* highest channel number).
EricLew	0:80ee8f3b695e	2822	* Sequencer ranks are selected using
EricLew	0:80ee8f3b695e	2823	* function "LL_ADC_REG_SetSequencerChannels()".
EricLew	0:80ee8f3b695e	2824	* @note Sequencer disabled is equivalent to sequencer of 1 rank:
EricLew	0:80ee8f3b695e	2825	* ADC conversion on only 1 channel.
EricLew	0:80ee8f3b695e	2826	* @note On this STM32 family, setting of this feature is conditioned to
EricLew	0:80ee8f3b695e	2827	* ADC state:
EricLew	0:80ee8f3b695e	2828	* ADC must be disabled or enabled without conversion on going
EricLew	0:80ee8f3b695e	2829	* on group regular.
EricLew	0:80ee8f3b695e	2830	* @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength
EricLew	0:80ee8f3b695e	2831	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	2832	* @param SequencerNbRanks This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2833	* @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
EricLew	0:80ee8f3b695e	2834	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
EricLew	0:80ee8f3b695e	2835	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
EricLew	0:80ee8f3b695e	2836	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
EricLew	0:80ee8f3b695e	2837	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
EricLew	0:80ee8f3b695e	2838	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
EricLew	0:80ee8f3b695e	2839	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
EricLew	0:80ee8f3b695e	2840	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
EricLew	0:80ee8f3b695e	2841	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
EricLew	0:80ee8f3b695e	2842	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
EricLew	0:80ee8f3b695e	2843	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
EricLew	0:80ee8f3b695e	2844	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
EricLew	0:80ee8f3b695e	2845	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
EricLew	0:80ee8f3b695e	2846	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
EricLew	0:80ee8f3b695e	2847	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
EricLew	0:80ee8f3b695e	2848	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
EricLew	0:80ee8f3b695e	2849	* @retval None
EricLew	0:80ee8f3b695e	2850	*/
EricLew	0:80ee8f3b695e	2851	__STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
EricLew	0:80ee8f3b695e	2852	{
EricLew	0:80ee8f3b695e	2853	MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks);
EricLew	0:80ee8f3b695e	2854	}
EricLew	0:80ee8f3b695e	2855
EricLew	0:80ee8f3b695e	2856	/**
EricLew	0:80ee8f3b695e	2857	* @brief Get ADC group regular sequencer length and scan direction.
EricLew	0:80ee8f3b695e	2858	* * For devices with sequencer fully configurable
EricLew	0:80ee8f3b695e	2859	* (function "LL_ADC_REG_SetSequencerRanks()" available):
EricLew	0:80ee8f3b695e	2860	* sequencer length and each rank affectation to a channel
EricLew	0:80ee8f3b695e	2861	* are configurable.
EricLew	0:80ee8f3b695e	2862	* This function performs:
EricLew	0:80ee8f3b695e	2863	* - Sequence length: Set number of ranks in the scan sequence.
EricLew	0:80ee8f3b695e	2864	* - Sequence direction: Unless specified in parameters, sequencer
EricLew	0:80ee8f3b695e	2865	* scan direction is forward (from rank 1 to rank n).
EricLew	0:80ee8f3b695e	2866	* Sequencer ranks are selected using
EricLew	0:80ee8f3b695e	2867	* function "LL_ADC_REG_SetSequencerRanks()".
EricLew	0:80ee8f3b695e	2868	* * For devices with sequencer not fully configurable
EricLew	0:80ee8f3b695e	2869	* (function "LL_ADC_REG_SetSequencerChannels()" available):
EricLew	0:80ee8f3b695e	2870	* sequencer length and each rank affectation to a channel
EricLew	0:80ee8f3b695e	2871	* are defined by channel number.
EricLew	0:80ee8f3b695e	2872	* This function performs:
EricLew	0:80ee8f3b695e	2873	* - Sequence length: Number of ranks in the scan sequence is
EricLew	0:80ee8f3b695e	2874	* defined by number of channels set in the sequence,
EricLew	0:80ee8f3b695e	2875	* rank of each channel is fixed by channel HW number.
EricLew	0:80ee8f3b695e	2876	* (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
EricLew	0:80ee8f3b695e	2877	* - Sequence direction: Unless specified in parameters, sequencer
EricLew	0:80ee8f3b695e	2878	* scan direction is forward (from lowest channel number to
EricLew	0:80ee8f3b695e	2879	* highest channel number).
EricLew	0:80ee8f3b695e	2880	* Sequencer ranks are selected using
EricLew	0:80ee8f3b695e	2881	* function "LL_ADC_REG_SetSequencerChannels()".
EricLew	0:80ee8f3b695e	2882	* @note Sequencer disabled is equivalent to sequencer of 1 rank:
EricLew	0:80ee8f3b695e	2883	* ADC conversion on only 1 channel.
EricLew	0:80ee8f3b695e	2884	* @rmtoll SQR1 L LL_ADC_REG_GetSequencerLength
EricLew	0:80ee8f3b695e	2885	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	2886	* @retval Returned value can be one of the following values:
EricLew	0:80ee8f3b695e	2887	* @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
EricLew	0:80ee8f3b695e	2888	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
EricLew	0:80ee8f3b695e	2889	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
EricLew	0:80ee8f3b695e	2890	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
EricLew	0:80ee8f3b695e	2891	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
EricLew	0:80ee8f3b695e	2892	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
EricLew	0:80ee8f3b695e	2893	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
EricLew	0:80ee8f3b695e	2894	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
EricLew	0:80ee8f3b695e	2895	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
EricLew	0:80ee8f3b695e	2896	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
EricLew	0:80ee8f3b695e	2897	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
EricLew	0:80ee8f3b695e	2898	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
EricLew	0:80ee8f3b695e	2899	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
EricLew	0:80ee8f3b695e	2900	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
EricLew	0:80ee8f3b695e	2901	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
EricLew	0:80ee8f3b695e	2902	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
EricLew	0:80ee8f3b695e	2903	*/
EricLew	0:80ee8f3b695e	2904	__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	2905	{
EricLew	0:80ee8f3b695e	2906	return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L));
EricLew	0:80ee8f3b695e	2907	}
EricLew	0:80ee8f3b695e	2908
EricLew	0:80ee8f3b695e	2909	/**
EricLew	0:80ee8f3b695e	2910	* @brief Set ADC group regular sequencer discontinuous mode:
EricLew	0:80ee8f3b695e	2911	* sequence subdivided and scan conversions interrupted every selected
EricLew	0:80ee8f3b695e	2912	* number of ranks.
EricLew	0:80ee8f3b695e	2913	* @note It is not possible to enable both ADC continuous mode
EricLew	0:80ee8f3b695e	2914	* and ADC group regular discontinuous mode.
EricLew	0:80ee8f3b695e	2915	* @note It is not possible to enable both ADC auto-injected mode
EricLew	0:80ee8f3b695e	2916	* and ADC group regular discontinuous mode.
EricLew	0:80ee8f3b695e	2917	* @note On this STM32 family, setting of this feature is conditioned to
EricLew	0:80ee8f3b695e	2918	* ADC state:
EricLew	0:80ee8f3b695e	2919	* ADC must be disabled or enabled without conversion on going
EricLew	0:80ee8f3b695e	2920	* on group regular.
EricLew	0:80ee8f3b695e	2921	* @rmtoll CFGR DISCEN LL_ADC_REG_SetSequencerDiscont\n
EricLew	0:80ee8f3b695e	2922	* CFGR DISCNUM LL_ADC_REG_SetSequencerDiscont
EricLew	0:80ee8f3b695e	2923	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	2924	* @param SeqDiscont This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2925	* @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
EricLew	0:80ee8f3b695e	2926	* @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
EricLew	0:80ee8f3b695e	2927	* @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
EricLew	0:80ee8f3b695e	2928	* @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
EricLew	0:80ee8f3b695e	2929	* @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
EricLew	0:80ee8f3b695e	2930	* @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
EricLew	0:80ee8f3b695e	2931	* @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
EricLew	0:80ee8f3b695e	2932	* @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
EricLew	0:80ee8f3b695e	2933	* @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
EricLew	0:80ee8f3b695e	2934	* @retval None
EricLew	0:80ee8f3b695e	2935	*/
EricLew	0:80ee8f3b695e	2936	__STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
EricLew	0:80ee8f3b695e	2937	{
EricLew	0:80ee8f3b695e	2938	MODIFY_REG(ADCx->CFGR, ADC_CFGR_DISCEN \| ADC_CFGR_DISCNUM, SeqDiscont);
EricLew	0:80ee8f3b695e	2939	}
EricLew	0:80ee8f3b695e	2940
EricLew	0:80ee8f3b695e	2941	/**
EricLew	0:80ee8f3b695e	2942	* @brief Get ADC group regular sequencer discontinuous mode:
EricLew	0:80ee8f3b695e	2943	* sequence subdivided and scan conversions interrupted every selected
EricLew	0:80ee8f3b695e	2944	* number of ranks.
EricLew	0:80ee8f3b695e	2945	* @rmtoll CFGR DISCEN LL_ADC_REG_GetSequencerDiscont\n
EricLew	0:80ee8f3b695e	2946	* CFGR DISCNUM LL_ADC_REG_GetSequencerDiscont
EricLew	0:80ee8f3b695e	2947	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	2948	* @retval Returned value can be one of the following values:
EricLew	0:80ee8f3b695e	2949	* @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
EricLew	0:80ee8f3b695e	2950	* @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
EricLew	0:80ee8f3b695e	2951	* @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
EricLew	0:80ee8f3b695e	2952	* @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
EricLew	0:80ee8f3b695e	2953	* @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
EricLew	0:80ee8f3b695e	2954	* @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
EricLew	0:80ee8f3b695e	2955	* @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
EricLew	0:80ee8f3b695e	2956	* @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
EricLew	0:80ee8f3b695e	2957	* @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
EricLew	0:80ee8f3b695e	2958	*/
EricLew	0:80ee8f3b695e	2959	__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	2960	{
EricLew	0:80ee8f3b695e	2961	return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DISCEN \| ADC_CFGR_DISCNUM));
EricLew	0:80ee8f3b695e	2962	}
EricLew	0:80ee8f3b695e	2963
EricLew	0:80ee8f3b695e	2964	/**
EricLew	0:80ee8f3b695e	2965	* @brief Set ADC group regular sequence: channel on the selected
EricLew	0:80ee8f3b695e	2966	* scan sequence rank.
EricLew	0:80ee8f3b695e	2967	* This function performs:
EricLew	0:80ee8f3b695e	2968	* - Channels ordering into each rank of scan sequence:
EricLew	0:80ee8f3b695e	2969	* whatever channel can be placed into whatever rank.
EricLew	0:80ee8f3b695e	2970	* @note On this STM32 family, ADC group regular sequencer is
EricLew	0:80ee8f3b695e	2971	* fully configurable: sequencer length and each rank
EricLew	0:80ee8f3b695e	2972	* affectation to a channel are configurable.
EricLew	0:80ee8f3b695e	2973	* Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
EricLew	0:80ee8f3b695e	2974	* @note Depending on devices and packages, some channels may not be available.
EricLew	0:80ee8f3b695e	2975	* Refer to device datasheet for channels availability.
EricLew	0:80ee8f3b695e	2976	* @note On this STM32 family, to measure internal channels (VrefInt,
EricLew	0:80ee8f3b695e	2977	* TempSensor, ...), measurement paths to internal channels must be
EricLew	0:80ee8f3b695e	2978	* enabled separately.
EricLew	0:80ee8f3b695e	2979	* This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
EricLew	0:80ee8f3b695e	2980	* @note On this STM32 family, setting of this feature is conditioned to
EricLew	0:80ee8f3b695e	2981	* ADC state:
EricLew	0:80ee8f3b695e	2982	* ADC must be disabled or enabled without conversion on going
EricLew	0:80ee8f3b695e	2983	* on group regular.
EricLew	0:80ee8f3b695e	2984	* @rmtoll SQR1 SQ1 LL_ADC_REG_SetSequencerRanks\n
EricLew	0:80ee8f3b695e	2985	* SQR1 SQ2 LL_ADC_REG_SetSequencerRanks\n
EricLew	0:80ee8f3b695e	2986	* SQR1 SQ3 LL_ADC_REG_SetSequencerRanks\n
EricLew	0:80ee8f3b695e	2987	* SQR1 SQ4 LL_ADC_REG_SetSequencerRanks\n
EricLew	0:80ee8f3b695e	2988	* SQR2 SQ5 LL_ADC_REG_SetSequencerRanks\n
EricLew	0:80ee8f3b695e	2989	* SQR2 SQ6 LL_ADC_REG_SetSequencerRanks\n
EricLew	0:80ee8f3b695e	2990	* SQR2 SQ7 LL_ADC_REG_SetSequencerRanks\n
EricLew	0:80ee8f3b695e	2991	* SQR2 SQ8 LL_ADC_REG_SetSequencerRanks\n
EricLew	0:80ee8f3b695e	2992	* SQR2 SQ9 LL_ADC_REG_SetSequencerRanks\n
EricLew	0:80ee8f3b695e	2993	* SQR3 SQ10 LL_ADC_REG_SetSequencerRanks\n
EricLew	0:80ee8f3b695e	2994	* SQR3 SQ11 LL_ADC_REG_SetSequencerRanks\n
EricLew	0:80ee8f3b695e	2995	* SQR3 SQ12 LL_ADC_REG_SetSequencerRanks\n
EricLew	0:80ee8f3b695e	2996	* SQR3 SQ13 LL_ADC_REG_SetSequencerRanks\n
EricLew	0:80ee8f3b695e	2997	* SQR3 SQ14 LL_ADC_REG_SetSequencerRanks\n
EricLew	0:80ee8f3b695e	2998	* SQR4 SQ15 LL_ADC_REG_SetSequencerRanks\n
EricLew	0:80ee8f3b695e	2999	* SQR4 SQ16 LL_ADC_REG_SetSequencerRanks
EricLew	0:80ee8f3b695e	3000	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	3001	* @param Rank This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	3002	* @arg @ref LL_ADC_REG_RANK_1
EricLew	0:80ee8f3b695e	3003	* @arg @ref LL_ADC_REG_RANK_2
EricLew	0:80ee8f3b695e	3004	* @arg @ref LL_ADC_REG_RANK_3
EricLew	0:80ee8f3b695e	3005	* @arg @ref LL_ADC_REG_RANK_4
EricLew	0:80ee8f3b695e	3006	* @arg @ref LL_ADC_REG_RANK_5
EricLew	0:80ee8f3b695e	3007	* @arg @ref LL_ADC_REG_RANK_6
EricLew	0:80ee8f3b695e	3008	* @arg @ref LL_ADC_REG_RANK_7
EricLew	0:80ee8f3b695e	3009	* @arg @ref LL_ADC_REG_RANK_8
EricLew	0:80ee8f3b695e	3010	* @arg @ref LL_ADC_REG_RANK_9
EricLew	0:80ee8f3b695e	3011	* @arg @ref LL_ADC_REG_RANK_10
EricLew	0:80ee8f3b695e	3012	* @arg @ref LL_ADC_REG_RANK_11
EricLew	0:80ee8f3b695e	3013	* @arg @ref LL_ADC_REG_RANK_12
EricLew	0:80ee8f3b695e	3014	* @arg @ref LL_ADC_REG_RANK_13
EricLew	0:80ee8f3b695e	3015	* @arg @ref LL_ADC_REG_RANK_14
EricLew	0:80ee8f3b695e	3016	* @arg @ref LL_ADC_REG_RANK_15
EricLew	0:80ee8f3b695e	3017	* @arg @ref LL_ADC_REG_RANK_16
EricLew	0:80ee8f3b695e	3018	* @param Channel This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	3019	* @arg @ref LL_ADC_CHANNEL_0
EricLew	0:80ee8f3b695e	3020	* @arg @ref LL_ADC_CHANNEL_1 (5)
EricLew	0:80ee8f3b695e	3021	* @arg @ref LL_ADC_CHANNEL_2 (5)
EricLew	0:80ee8f3b695e	3022	* @arg @ref LL_ADC_CHANNEL_3 (5)
EricLew	0:80ee8f3b695e	3023	* @arg @ref LL_ADC_CHANNEL_4 (5)
EricLew	0:80ee8f3b695e	3024	* @arg @ref LL_ADC_CHANNEL_5 (5)
EricLew	0:80ee8f3b695e	3025	* @arg @ref LL_ADC_CHANNEL_6
EricLew	0:80ee8f3b695e	3026	* @arg @ref LL_ADC_CHANNEL_7
EricLew	0:80ee8f3b695e	3027	* @arg @ref LL_ADC_CHANNEL_8
EricLew	0:80ee8f3b695e	3028	* @arg @ref LL_ADC_CHANNEL_9
EricLew	0:80ee8f3b695e	3029	* @arg @ref LL_ADC_CHANNEL_10
EricLew	0:80ee8f3b695e	3030	* @arg @ref LL_ADC_CHANNEL_11
EricLew	0:80ee8f3b695e	3031	* @arg @ref LL_ADC_CHANNEL_12
EricLew	0:80ee8f3b695e	3032	* @arg @ref LL_ADC_CHANNEL_13
EricLew	0:80ee8f3b695e	3033	* @arg @ref LL_ADC_CHANNEL_14
EricLew	0:80ee8f3b695e	3034	* @arg @ref LL_ADC_CHANNEL_15
EricLew	0:80ee8f3b695e	3035	* @arg @ref LL_ADC_CHANNEL_16
EricLew	0:80ee8f3b695e	3036	* @arg @ref LL_ADC_CHANNEL_17
EricLew	0:80ee8f3b695e	3037	* @arg @ref LL_ADC_CHANNEL_18
EricLew	0:80ee8f3b695e	3038	* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
EricLew	0:80ee8f3b695e	3039	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
EricLew	0:80ee8f3b695e	3040	* @arg @ref LL_ADC_CHANNEL_VBAT (4)
EricLew	0:80ee8f3b695e	3041	* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
EricLew	0:80ee8f3b695e	3042	* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
EricLew	0:80ee8f3b695e	3043	* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)
EricLew	0:80ee8f3b695e	3044	* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)
EricLew	0:80ee8f3b695e	3045	* (1) On STM32L4, parameter available only on ADC instance: ADC1.
EricLew	0:80ee8f3b695e	3046	* (2) On STM32L4, parameter available only on ADC instance: ADC2.
EricLew	0:80ee8f3b695e	3047	* (3) On STM32L4, parameter available only on ADC instance: ADC3.
EricLew	0:80ee8f3b695e	3048	* (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.
EricLew	0:80ee8f3b695e	3049	* (5) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
EricLew	0:80ee8f3b695e	3050	* Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
EricLew	0:80ee8f3b695e	3051	* @retval None
EricLew	0:80ee8f3b695e	3052	*/
EricLew	0:80ee8f3b695e	3053	__STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
EricLew	0:80ee8f3b695e	3054	{
EricLew	0:80ee8f3b695e	3055	/* Set bits with content of parameter "Channel" with bits position */
EricLew	0:80ee8f3b695e	3056	/* in register and register position depending on parameter "Rank". */
EricLew	0:80ee8f3b695e	3057	/* Parameters "Rank" and "Channel" are used with masks because containing */
EricLew	0:80ee8f3b695e	3058	/* other bits reserved for other purpose. */
EricLew	0:80ee8f3b695e	3059	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
EricLew	0:80ee8f3b695e	3060
EricLew	0:80ee8f3b695e	3061	MODIFY_REG(*preg,
EricLew	0:80ee8f3b695e	3062	ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
EricLew	0:80ee8f3b695e	3063	(Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> (POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) - (Rank & ADC_REG_RANK_ID_SQRX_MASK)));
EricLew	0:80ee8f3b695e	3064	}
EricLew	0:80ee8f3b695e	3065
EricLew	0:80ee8f3b695e	3066	/**
EricLew	0:80ee8f3b695e	3067	* @brief Get ADC group regular sequence: channel on the selected
EricLew	0:80ee8f3b695e	3068	* scan sequence rank.
EricLew	0:80ee8f3b695e	3069	* @note On this STM32 family, ADC group regular sequencer is
EricLew	0:80ee8f3b695e	3070	* fully configurable: sequencer length and each rank
EricLew	0:80ee8f3b695e	3071	* affectation to a channel are configurable.
EricLew	0:80ee8f3b695e	3072	* Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
EricLew	0:80ee8f3b695e	3073	* @note Depending on devices and packages, some channels may not be available.
EricLew	0:80ee8f3b695e	3074	* Refer to device datasheet for channels availability.
EricLew	0:80ee8f3b695e	3075	* @note Usage of the returned channel number:
EricLew	0:80ee8f3b695e	3076	* - To reinject this channel into another function LL_ADC_xxx:
EricLew	0:80ee8f3b695e	3077	* the returned channel number is only partly formatted on definition
EricLew	0:80ee8f3b695e	3078	* of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
EricLew	0:80ee8f3b695e	3079	* with literals LL_ADC_CHANNEL_x, then the selected
EricLew	0:80ee8f3b695e	3080	* literal LL_ADC_CHANNEL_x can be used as parameter for another
EricLew	0:80ee8f3b695e	3081	* function.
EricLew	0:80ee8f3b695e	3082	* - To get the channel number in decimal format:
EricLew	0:80ee8f3b695e	3083	* process the returned value with the helper macro
EricLew	0:80ee8f3b695e	3084	* @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
EricLew	0:80ee8f3b695e	3085	* @rmtoll SQR1 SQ1 LL_ADC_REG_GetSequencerRanks\n
EricLew	0:80ee8f3b695e	3086	* SQR1 SQ2 LL_ADC_REG_GetSequencerRanks\n
EricLew	0:80ee8f3b695e	3087	* SQR1 SQ3 LL_ADC_REG_GetSequencerRanks\n
EricLew	0:80ee8f3b695e	3088	* SQR1 SQ4 LL_ADC_REG_GetSequencerRanks\n
EricLew	0:80ee8f3b695e	3089	* SQR2 SQ5 LL_ADC_REG_GetSequencerRanks\n
EricLew	0:80ee8f3b695e	3090	* SQR2 SQ6 LL_ADC_REG_GetSequencerRanks\n
EricLew	0:80ee8f3b695e	3091	* SQR2 SQ7 LL_ADC_REG_GetSequencerRanks\n
EricLew	0:80ee8f3b695e	3092	* SQR2 SQ8 LL_ADC_REG_GetSequencerRanks\n
EricLew	0:80ee8f3b695e	3093	* SQR2 SQ9 LL_ADC_REG_GetSequencerRanks\n
EricLew	0:80ee8f3b695e	3094	* SQR3 SQ10 LL_ADC_REG_GetSequencerRanks\n
EricLew	0:80ee8f3b695e	3095	* SQR3 SQ11 LL_ADC_REG_GetSequencerRanks\n
EricLew	0:80ee8f3b695e	3096	* SQR3 SQ12 LL_ADC_REG_GetSequencerRanks\n
EricLew	0:80ee8f3b695e	3097	* SQR3 SQ13 LL_ADC_REG_GetSequencerRanks\n
EricLew	0:80ee8f3b695e	3098	* SQR3 SQ14 LL_ADC_REG_GetSequencerRanks\n
EricLew	0:80ee8f3b695e	3099	* SQR4 SQ15 LL_ADC_REG_GetSequencerRanks\n
EricLew	0:80ee8f3b695e	3100	* SQR4 SQ16 LL_ADC_REG_GetSequencerRanks
EricLew	0:80ee8f3b695e	3101	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	3102	* @param Rank This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	3103	* @arg @ref LL_ADC_REG_RANK_1
EricLew	0:80ee8f3b695e	3104	* @arg @ref LL_ADC_REG_RANK_2
EricLew	0:80ee8f3b695e	3105	* @arg @ref LL_ADC_REG_RANK_3
EricLew	0:80ee8f3b695e	3106	* @arg @ref LL_ADC_REG_RANK_4
EricLew	0:80ee8f3b695e	3107	* @arg @ref LL_ADC_REG_RANK_5
EricLew	0:80ee8f3b695e	3108	* @arg @ref LL_ADC_REG_RANK_6
EricLew	0:80ee8f3b695e	3109	* @arg @ref LL_ADC_REG_RANK_7
EricLew	0:80ee8f3b695e	3110	* @arg @ref LL_ADC_REG_RANK_8
EricLew	0:80ee8f3b695e	3111	* @arg @ref LL_ADC_REG_RANK_9
EricLew	0:80ee8f3b695e	3112	* @arg @ref LL_ADC_REG_RANK_10
EricLew	0:80ee8f3b695e	3113	* @arg @ref LL_ADC_REG_RANK_11
EricLew	0:80ee8f3b695e	3114	* @arg @ref LL_ADC_REG_RANK_12
EricLew	0:80ee8f3b695e	3115	* @arg @ref LL_ADC_REG_RANK_13
EricLew	0:80ee8f3b695e	3116	* @arg @ref LL_ADC_REG_RANK_14
EricLew	0:80ee8f3b695e	3117	* @arg @ref LL_ADC_REG_RANK_15
EricLew	0:80ee8f3b695e	3118	* @arg @ref LL_ADC_REG_RANK_16
EricLew	0:80ee8f3b695e	3119	* @retval Returned value can be one of the following values:
EricLew	0:80ee8f3b695e	3120	* @arg @ref LL_ADC_CHANNEL_0
EricLew	0:80ee8f3b695e	3121	* @arg @ref LL_ADC_CHANNEL_1 (5)
EricLew	0:80ee8f3b695e	3122	* @arg @ref LL_ADC_CHANNEL_2 (5)
EricLew	0:80ee8f3b695e	3123	* @arg @ref LL_ADC_CHANNEL_3 (5)
EricLew	0:80ee8f3b695e	3124	* @arg @ref LL_ADC_CHANNEL_4 (5)
EricLew	0:80ee8f3b695e	3125	* @arg @ref LL_ADC_CHANNEL_5 (5)
EricLew	0:80ee8f3b695e	3126	* @arg @ref LL_ADC_CHANNEL_6
EricLew	0:80ee8f3b695e	3127	* @arg @ref LL_ADC_CHANNEL_7
EricLew	0:80ee8f3b695e	3128	* @arg @ref LL_ADC_CHANNEL_8
EricLew	0:80ee8f3b695e	3129	* @arg @ref LL_ADC_CHANNEL_9
EricLew	0:80ee8f3b695e	3130	* @arg @ref LL_ADC_CHANNEL_10
EricLew	0:80ee8f3b695e	3131	* @arg @ref LL_ADC_CHANNEL_11
EricLew	0:80ee8f3b695e	3132	* @arg @ref LL_ADC_CHANNEL_12
EricLew	0:80ee8f3b695e	3133	* @arg @ref LL_ADC_CHANNEL_13
EricLew	0:80ee8f3b695e	3134	* @arg @ref LL_ADC_CHANNEL_14
EricLew	0:80ee8f3b695e	3135	* @arg @ref LL_ADC_CHANNEL_15
EricLew	0:80ee8f3b695e	3136	* @arg @ref LL_ADC_CHANNEL_16
EricLew	0:80ee8f3b695e	3137	* @arg @ref LL_ADC_CHANNEL_17
EricLew	0:80ee8f3b695e	3138	* @arg @ref LL_ADC_CHANNEL_18
EricLew	0:80ee8f3b695e	3139	* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
EricLew	0:80ee8f3b695e	3140	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
EricLew	0:80ee8f3b695e	3141	* @arg @ref LL_ADC_CHANNEL_VBAT (4)
EricLew	0:80ee8f3b695e	3142	* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
EricLew	0:80ee8f3b695e	3143	* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
EricLew	0:80ee8f3b695e	3144	* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)
EricLew	0:80ee8f3b695e	3145	* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)
EricLew	0:80ee8f3b695e	3146	* (1) On STM32L4, parameter available only on ADC instance: ADC1.
EricLew	0:80ee8f3b695e	3147	* (2) On STM32L4, parameter available only on ADC instance: ADC2.
EricLew	0:80ee8f3b695e	3148	* (3) On STM32L4, parameter available only on ADC instance: ADC3.
EricLew	0:80ee8f3b695e	3149	* (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.
EricLew	0:80ee8f3b695e	3150	* (5) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
EricLew	0:80ee8f3b695e	3151	* Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
EricLew	0:80ee8f3b695e	3152	* (1, 2, 3, 4) For ADC channel read back from ADC register,
EricLew	0:80ee8f3b695e	3153	* comparison with internal channel parameter to be done
EricLew	0:80ee8f3b695e	3154	* using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
EricLew	0:80ee8f3b695e	3155	*/
EricLew	0:80ee8f3b695e	3156	__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
EricLew	0:80ee8f3b695e	3157	{
EricLew	0:80ee8f3b695e	3158	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
EricLew	0:80ee8f3b695e	3159
EricLew	0:80ee8f3b695e	3160	return (uint32_t) (READ_BIT(*preg,
EricLew	0:80ee8f3b695e	3161	ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
EricLew	0:80ee8f3b695e	3162	<< (POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) - (Rank & ADC_REG_RANK_ID_SQRX_MASK))
EricLew	0:80ee8f3b695e	3163	);
EricLew	0:80ee8f3b695e	3164	}
EricLew	0:80ee8f3b695e	3165
EricLew	0:80ee8f3b695e	3166	/**
EricLew	0:80ee8f3b695e	3167	* @}
EricLew	0:80ee8f3b695e	3168	*/
EricLew	0:80ee8f3b695e	3169
EricLew	0:80ee8f3b695e	3170	/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected
EricLew	0:80ee8f3b695e	3171	* @{
EricLew	0:80ee8f3b695e	3172	*/
EricLew	0:80ee8f3b695e	3173
EricLew	0:80ee8f3b695e	3174	/**
EricLew	0:80ee8f3b695e	3175	* @brief Set ADC group injected conversion trigger source:
EricLew	0:80ee8f3b695e	3176	* internal (SW start) or external from timer or external interrupt.
EricLew	0:80ee8f3b695e	3177	* @note Setting trigger source to external trigger also set trigger polarity
EricLew	0:80ee8f3b695e	3178	* to rising edge
EricLew	0:80ee8f3b695e	3179	* (default setting for compatibility with some ADC on other
EricLew	0:80ee8f3b695e	3180	* STM32 families having this setting set by HW default value).
EricLew	0:80ee8f3b695e	3181	* In case of need to modify trigger edge, use
EricLew	0:80ee8f3b695e	3182	* function @ref LL_ADC_INJ_SetTrigEdge().
EricLew	0:80ee8f3b695e	3183	* @note On this STM32 family, setting of this feature is conditioned to
EricLew	0:80ee8f3b695e	3184	* ADC state:
EricLew	0:80ee8f3b695e	3185	* ADC must not be disabled. Can be enabled with or without conversion
EricLew	0:80ee8f3b695e	3186	* on going on either groups regular or injected.
EricLew	0:80ee8f3b695e	3187	* @rmtoll JSQR JEXTSEL LL_ADC_INJ_SetTrigSource\n
EricLew	0:80ee8f3b695e	3188	* JSQR JEXTEN LL_ADC_INJ_SetTrigSource
EricLew	0:80ee8f3b695e	3189	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	3190	* @param TriggerSource This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	3191	* @arg @ref LL_ADC_INJ_TRIG_SW_START
EricLew	0:80ee8f3b695e	3192	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
EricLew	0:80ee8f3b695e	3193	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
EricLew	0:80ee8f3b695e	3194	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CC4
EricLew	0:80ee8f3b695e	3195	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
EricLew	0:80ee8f3b695e	3196	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CC1
EricLew	0:80ee8f3b695e	3197	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
EricLew	0:80ee8f3b695e	3198	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CC1
EricLew	0:80ee8f3b695e	3199	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CC3
EricLew	0:80ee8f3b695e	3200	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CC4
EricLew	0:80ee8f3b695e	3201	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
EricLew	0:80ee8f3b695e	3202	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
EricLew	0:80ee8f3b695e	3203	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CC4
EricLew	0:80ee8f3b695e	3204	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
EricLew	0:80ee8f3b695e	3205	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
EricLew	0:80ee8f3b695e	3206	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
EricLew	0:80ee8f3b695e	3207	* @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
EricLew	0:80ee8f3b695e	3208	* @retval None
EricLew	0:80ee8f3b695e	3209	*/
EricLew	0:80ee8f3b695e	3210	__STATIC_INLINE void LL_ADC_INJ_SetTrigSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
EricLew	0:80ee8f3b695e	3211	{
EricLew	0:80ee8f3b695e	3212	MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTSEL \| ADC_JSQR_JEXTEN, TriggerSource);
EricLew	0:80ee8f3b695e	3213	}
EricLew	0:80ee8f3b695e	3214
EricLew	0:80ee8f3b695e	3215	/**
EricLew	0:80ee8f3b695e	3216	* @brief Get ADC group injected conversion trigger source:
EricLew	0:80ee8f3b695e	3217	* internal (SW start) or external from timer or external interrupt.
EricLew	0:80ee8f3b695e	3218	* @note To determine whether group injected trigger source is
EricLew	0:80ee8f3b695e	3219	* internal (SW start) or external, without detail
EricLew	0:80ee8f3b695e	3220	* of which peripheral is selected as external trigger,
EricLew	0:80ee8f3b695e	3221	* (equivalent to
EricLew	0:80ee8f3b695e	3222	* " if(LL_ADC_INJ_GetTrigSource(ADC1) == LL_ADC_INJ_TRIG_SW_START) ")
EricLew	0:80ee8f3b695e	3223	* use function @ref LL_ADC_INJ_IsTrigSourceSWStart.
EricLew	0:80ee8f3b695e	3224	* @rmtoll JSQR JEXTSEL LL_ADC_INJ_GetTrigSource\n
EricLew	0:80ee8f3b695e	3225	* JSQR JEXTEN LL_ADC_INJ_GetTrigSource
EricLew	0:80ee8f3b695e	3226	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	3227	* @retval Returned value can be one of the following values:
EricLew	0:80ee8f3b695e	3228	* @arg @ref LL_ADC_INJ_TRIG_SW_START
EricLew	0:80ee8f3b695e	3229	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
EricLew	0:80ee8f3b695e	3230	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
EricLew	0:80ee8f3b695e	3231	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CC4
EricLew	0:80ee8f3b695e	3232	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
EricLew	0:80ee8f3b695e	3233	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CC1
EricLew	0:80ee8f3b695e	3234	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
EricLew	0:80ee8f3b695e	3235	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CC1
EricLew	0:80ee8f3b695e	3236	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CC3
EricLew	0:80ee8f3b695e	3237	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CC4
EricLew	0:80ee8f3b695e	3238	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
EricLew	0:80ee8f3b695e	3239	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
EricLew	0:80ee8f3b695e	3240	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CC4
EricLew	0:80ee8f3b695e	3241	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
EricLew	0:80ee8f3b695e	3242	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
EricLew	0:80ee8f3b695e	3243	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
EricLew	0:80ee8f3b695e	3244	* @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
EricLew	0:80ee8f3b695e	3245	*/
EricLew	0:80ee8f3b695e	3246	__STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigSource(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	3247	{
EricLew	0:80ee8f3b695e	3248	register uint32_t TriggerSource = READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL \| ADC_JSQR_JEXTEN);
EricLew	0:80ee8f3b695e	3249
EricLew	0:80ee8f3b695e	3250	/* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
EricLew	0:80ee8f3b695e	3251	/* corresponding to ADC_JSQR_JEXTEN {0; 1; 2; 3}. */
EricLew	0:80ee8f3b695e	3252	register uint32_t ShiftJexten = ((TriggerSource & ADC_JSQR_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2));
EricLew	0:80ee8f3b695e	3253
EricLew	0:80ee8f3b695e	3254	/* Set bitfield corresponding to ADC_JSQR_JEXTEN and ADC_JSQR_JEXTSEL */
EricLew	0:80ee8f3b695e	3255	/* to match with triggers literals definition. */
EricLew	0:80ee8f3b695e	3256	return ((TriggerSource
EricLew	0:80ee8f3b695e	3257	& (ADC_INJ_TRIG_SOURCE_MASK >> ShiftJexten) & ADC_JSQR_JEXTSEL)
EricLew	0:80ee8f3b695e	3258	\| ((ADC_INJ_TRIG_EDGE_MASK >> ShiftJexten) & ADC_JSQR_JEXTEN)
EricLew	0:80ee8f3b695e	3259	);
EricLew	0:80ee8f3b695e	3260	}
EricLew	0:80ee8f3b695e	3261
EricLew	0:80ee8f3b695e	3262	/**
EricLew	0:80ee8f3b695e	3263	* @brief Get ADC group injected conversion trigger source:
EricLew	0:80ee8f3b695e	3264	* (0: trigger source external trigger, 1: trigger source SW start).
EricLew	0:80ee8f3b695e	3265	* @note In case of group injected trigger source set to external trigger,
EricLew	0:80ee8f3b695e	3266	* to determine which peripheral is selected as external trigger,
EricLew	0:80ee8f3b695e	3267	* use function @ref LL_ADC_INJ_GetTrigSource.
EricLew	0:80ee8f3b695e	3268	* @rmtoll JSQR JEXTEN LL_ADC_INJ_IsTrigSourceSWStart
EricLew	0:80ee8f3b695e	3269	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	3270	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	3271	*/
EricLew	0:80ee8f3b695e	3272	__STATIC_INLINE uint32_t LL_ADC_INJ_IsTrigSourceSWStart(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	3273	{
EricLew	0:80ee8f3b695e	3274	return (READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN) == (LL_ADC_INJ_TRIG_SW_START & ADC_JSQR_JEXTEN));
EricLew	0:80ee8f3b695e	3275	}
EricLew	0:80ee8f3b695e	3276
EricLew	0:80ee8f3b695e	3277	/**
EricLew	0:80ee8f3b695e	3278	* @brief Set ADC group injected conversion trigger polarity.
EricLew	0:80ee8f3b695e	3279	* Applicable only for trigger source set to external trigger.
EricLew	0:80ee8f3b695e	3280	* @note On this STM32 family, setting of this feature is conditioned to
EricLew	0:80ee8f3b695e	3281	* ADC state:
EricLew	0:80ee8f3b695e	3282	* ADC must not be disabled. Can be enabled with or without conversion
EricLew	0:80ee8f3b695e	3283	* on going on either groups regular or injected.
EricLew	0:80ee8f3b695e	3284	* @rmtoll JSQR JEXTEN LL_ADC_INJ_SetTrigEdge
EricLew	0:80ee8f3b695e	3285	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	3286	* @param ExternalTriggerEdge This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	3287	* @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
EricLew	0:80ee8f3b695e	3288	* @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
EricLew	0:80ee8f3b695e	3289	* @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
EricLew	0:80ee8f3b695e	3290	* @retval None
EricLew	0:80ee8f3b695e	3291	*/
EricLew	0:80ee8f3b695e	3292	__STATIC_INLINE void LL_ADC_INJ_SetTrigEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
EricLew	0:80ee8f3b695e	3293	{
EricLew	0:80ee8f3b695e	3294	MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTEN, ExternalTriggerEdge);
EricLew	0:80ee8f3b695e	3295	}
EricLew	0:80ee8f3b695e	3296
EricLew	0:80ee8f3b695e	3297	/**
EricLew	0:80ee8f3b695e	3298	* @brief Get ADC group injected conversion trigger polarity.
EricLew	0:80ee8f3b695e	3299	* Applicable only for trigger source set to external trigger.
EricLew	0:80ee8f3b695e	3300	* @rmtoll JSQR JEXTEN LL_ADC_INJ_GetTrigEdge
EricLew	0:80ee8f3b695e	3301	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	3302	* @retval Returned value can be one of the following values:
EricLew	0:80ee8f3b695e	3303	* @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
EricLew	0:80ee8f3b695e	3304	* @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
EricLew	0:80ee8f3b695e	3305	* @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
EricLew	0:80ee8f3b695e	3306	*/
EricLew	0:80ee8f3b695e	3307	__STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigEdge(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	3308	{
EricLew	0:80ee8f3b695e	3309	return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN));
EricLew	0:80ee8f3b695e	3310	}
EricLew	0:80ee8f3b695e	3311
EricLew	0:80ee8f3b695e	3312	/**
EricLew	0:80ee8f3b695e	3313	* @brief Set ADC group injected conversion trigger:
EricLew	0:80ee8f3b695e	3314	* independent or from ADC group regular.
EricLew	0:80ee8f3b695e	3315	* @note It is not possible to enable both ADC auto-injected mode
EricLew	0:80ee8f3b695e	3316	* and ADC group injected discontinuous mode.
EricLew	0:80ee8f3b695e	3317	* @note On this STM32 family, setting of this feature is conditioned to
EricLew	0:80ee8f3b695e	3318	* ADC state:
EricLew	0:80ee8f3b695e	3319	* ADC must be disabled or enabled without conversion on going
EricLew	0:80ee8f3b695e	3320	* on either groups regular or injected.
EricLew	0:80ee8f3b695e	3321	* @rmtoll CFGR JAUTO LL_ADC_INJ_SetTrigAuto
EricLew	0:80ee8f3b695e	3322	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	3323	* @param InjTrigAuto This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	3324	* @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
EricLew	0:80ee8f3b695e	3325	* @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
EricLew	0:80ee8f3b695e	3326	* @retval None
EricLew	0:80ee8f3b695e	3327	*/
EricLew	0:80ee8f3b695e	3328	__STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t InjTrigAuto)
EricLew	0:80ee8f3b695e	3329	{
EricLew	0:80ee8f3b695e	3330	MODIFY_REG(ADCx->CFGR, ADC_CFGR_JAUTO, InjTrigAuto);
EricLew	0:80ee8f3b695e	3331	}
EricLew	0:80ee8f3b695e	3332
EricLew	0:80ee8f3b695e	3333	/**
EricLew	0:80ee8f3b695e	3334	* @brief Get ADC group injected conversion trigger:
EricLew	0:80ee8f3b695e	3335	* independent or from ADC group regular.
EricLew	0:80ee8f3b695e	3336	* @rmtoll CFGR JAUTO LL_ADC_INJ_GetTrigAuto
EricLew	0:80ee8f3b695e	3337	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	3338	* @retval Returned value can be one of the following values:
EricLew	0:80ee8f3b695e	3339	* @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
EricLew	0:80ee8f3b695e	3340	* @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
EricLew	0:80ee8f3b695e	3341	*/
EricLew	0:80ee8f3b695e	3342	__STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	3343	{
EricLew	0:80ee8f3b695e	3344	return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JAUTO));
EricLew	0:80ee8f3b695e	3345	}
EricLew	0:80ee8f3b695e	3346
EricLew	0:80ee8f3b695e	3347	/**
EricLew	0:80ee8f3b695e	3348	* @brief Set ADC group injected contexts queue mode.
EricLew	0:80ee8f3b695e	3349	* A context is a setting of injected group sequencer:
EricLew	0:80ee8f3b695e	3350	* * injected group trigger
EricLew	0:80ee8f3b695e	3351	* * sequencer length
EricLew	0:80ee8f3b695e	3352	* * sequencer ranks
EricLew	0:80ee8f3b695e	3353	* If contexts queue is disabled:
EricLew	0:80ee8f3b695e	3354	* * only 1 sequence can be configured
EricLew	0:80ee8f3b695e	3355	* and is active perpetually.
EricLew	0:80ee8f3b695e	3356	* If contexts queue is enabled:
EricLew	0:80ee8f3b695e	3357	* * up to 2 contexts can be queued
EricLew	0:80ee8f3b695e	3358	* and are checked in and out as a FIFO stack (first-in, first-out).
EricLew	0:80ee8f3b695e	3359	* * If a new context is set when queues is full, error is triggered
EricLew	0:80ee8f3b695e	3360	* by interruption "Injected Queue Overflow".
EricLew	0:80ee8f3b695e	3361	* * Two behaviours are possible when all contexts have been processed:
EricLew	0:80ee8f3b695e	3362	* the contexts queue can maintain the last context active perpetually
EricLew	0:80ee8f3b695e	3363	* or can be empty and injected group triggers are disabled.
EricLew	0:80ee8f3b695e	3364	* * Triggers can be only external (not internal SW start)
EricLew	0:80ee8f3b695e	3365	* * Caution: The sequence must be fully configured in one time
EricLew	0:80ee8f3b695e	3366	* (one write of register JSQR makes a check-in of a new context
EricLew	0:80ee8f3b695e	3367	* into the queue).
EricLew	0:80ee8f3b695e	3368	* Therefore functions to set separately injected trigger and
EricLew	0:80ee8f3b695e	3369	* sequencer channels cannot be used, register JSQR must be set
EricLew	0:80ee8f3b695e	3370	* using function @ref LL_ADC_INJ_ConfigQueueContext().
EricLew	0:80ee8f3b695e	3371	* @note This parameter can be modified only when no conversion is on going
EricLew	0:80ee8f3b695e	3372	* on either groups regular or injected.
EricLew	0:80ee8f3b695e	3373	* @note A modification of the context mode (bit JQDIS) causes the contexts
EricLew	0:80ee8f3b695e	3374	* queue to be flushed and the register JSQR is cleared.
EricLew	0:80ee8f3b695e	3375	* @note On this STM32 family, setting of this feature is conditioned to
EricLew	0:80ee8f3b695e	3376	* ADC state:
EricLew	0:80ee8f3b695e	3377	* ADC must be disabled or enabled without conversion on going
EricLew	0:80ee8f3b695e	3378	* on either groups regular or injected.
EricLew	0:80ee8f3b695e	3379	* @rmtoll CFGR JQM LL_ADC_INJ_SetQueueMode\n
EricLew	0:80ee8f3b695e	3380	* CFGR JQDIS LL_ADC_INJ_SetQueueMode
EricLew	0:80ee8f3b695e	3381	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	3382	* @param QueueMode This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	3383	* @arg @ref LL_ADC_INJ_QUEUE_DISABLE
EricLew	0:80ee8f3b695e	3384	* @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE
EricLew	0:80ee8f3b695e	3385	* @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY
EricLew	0:80ee8f3b695e	3386	* @retval None
EricLew	0:80ee8f3b695e	3387	*/
EricLew	0:80ee8f3b695e	3388	__STATIC_INLINE void LL_ADC_INJ_SetQueueMode(ADC_TypeDef *ADCx, uint32_t QueueMode)
EricLew	0:80ee8f3b695e	3389	{
EricLew	0:80ee8f3b695e	3390	MODIFY_REG(ADCx->CFGR, ADC_CFGR_JQM \| ADC_CFGR_JQDIS, QueueMode);
EricLew	0:80ee8f3b695e	3391	}
EricLew	0:80ee8f3b695e	3392
EricLew	0:80ee8f3b695e	3393	/**
EricLew	0:80ee8f3b695e	3394	* @brief Get ADC group injected context queue mode.
EricLew	0:80ee8f3b695e	3395	* @rmtoll CFGR JQM LL_ADC_INJ_GetQueueMode\n
EricLew	0:80ee8f3b695e	3396	* CFGR JQDIS LL_ADC_INJ_GetQueueMode
EricLew	0:80ee8f3b695e	3397	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	3398	* @retval Returned value can be one of the following values:
EricLew	0:80ee8f3b695e	3399	* @arg @ref LL_ADC_INJ_QUEUE_DISABLE
EricLew	0:80ee8f3b695e	3400	* @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE
EricLew	0:80ee8f3b695e	3401	* @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY
EricLew	0:80ee8f3b695e	3402	*/
EricLew	0:80ee8f3b695e	3403	__STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	3404	{
EricLew	0:80ee8f3b695e	3405	return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JQM \| ADC_CFGR_JQDIS));
EricLew	0:80ee8f3b695e	3406	}
EricLew	0:80ee8f3b695e	3407
EricLew	0:80ee8f3b695e	3408	/**
EricLew	0:80ee8f3b695e	3409	* @brief Set ADC group injected sequencer length and scan direction.
EricLew	0:80ee8f3b695e	3410	* * Sequence length: Set number of ranks in the sequence.
EricLew	0:80ee8f3b695e	3411	* * Sequence direction: Unless specified in parameters, sequencer
EricLew	0:80ee8f3b695e	3412	* scan direction is forward (from rank 1 to rank n).
EricLew	0:80ee8f3b695e	3413	* @note Sequencer disabled is equivalent to sequencer of 1 rank:
EricLew	0:80ee8f3b695e	3414	* ADC conversion on only 1 channel.
EricLew	0:80ee8f3b695e	3415	* @note On this STM32 family, setting of this feature is conditioned to
EricLew	0:80ee8f3b695e	3416	* ADC state:
EricLew	0:80ee8f3b695e	3417	* ADC must not be disabled. Can be enabled with or without conversion
EricLew	0:80ee8f3b695e	3418	* on going on either groups regular or injected.
EricLew	0:80ee8f3b695e	3419	* @rmtoll JSQR JL LL_ADC_INJ_SetSequencerLength
EricLew	0:80ee8f3b695e	3420	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	3421	* @param SequencerNbRanks This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	3422	* @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
EricLew	0:80ee8f3b695e	3423	* @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
EricLew	0:80ee8f3b695e	3424	* @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
EricLew	0:80ee8f3b695e	3425	* @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
EricLew	0:80ee8f3b695e	3426	* @retval None
EricLew	0:80ee8f3b695e	3427	*/
EricLew	0:80ee8f3b695e	3428	__STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
EricLew	0:80ee8f3b695e	3429	{
EricLew	0:80ee8f3b695e	3430	MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks);
EricLew	0:80ee8f3b695e	3431	}
EricLew	0:80ee8f3b695e	3432
EricLew	0:80ee8f3b695e	3433	/**
EricLew	0:80ee8f3b695e	3434	* @brief Get ADC group injected sequencer length and scan direction.
EricLew	0:80ee8f3b695e	3435	* * Sequence length: Set number of ranks in the sequence.
EricLew	0:80ee8f3b695e	3436	* * Sequence direction: Unless specified in parameters, sequencer
EricLew	0:80ee8f3b695e	3437	* scan direction is forward (from rank 1 to rank n).
EricLew	0:80ee8f3b695e	3438	* @note Sequencer disabled is equivalent to sequencer of 1 rank:
EricLew	0:80ee8f3b695e	3439	* ADC conversion on only 1 channel.
EricLew	0:80ee8f3b695e	3440	* @rmtoll JSQR JL LL_ADC_INJ_GetSequencerLength
EricLew	0:80ee8f3b695e	3441	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	3442	* @retval Returned value can be one of the following values:
EricLew	0:80ee8f3b695e	3443	* @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
EricLew	0:80ee8f3b695e	3444	* @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
EricLew	0:80ee8f3b695e	3445	* @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
EricLew	0:80ee8f3b695e	3446	* @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
EricLew	0:80ee8f3b695e	3447	*/
EricLew	0:80ee8f3b695e	3448	__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	3449	{
EricLew	0:80ee8f3b695e	3450	return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL));
EricLew	0:80ee8f3b695e	3451	}
EricLew	0:80ee8f3b695e	3452
EricLew	0:80ee8f3b695e	3453	/**
EricLew	0:80ee8f3b695e	3454	* @brief Set ADC group injected sequencer discontinuous mode:
EricLew	0:80ee8f3b695e	3455	* sequence subdivided and scan conversions interrupted every selected
EricLew	0:80ee8f3b695e	3456	* number of ranks.
EricLew	0:80ee8f3b695e	3457	* @note It is not possible to enable both ADC auto-injected mode
EricLew	0:80ee8f3b695e	3458	* and ADC group injected discontinuous mode.
EricLew	0:80ee8f3b695e	3459	* @rmtoll CFGR JDISCEN LL_ADC_INJ_SetSequencerDiscont
EricLew	0:80ee8f3b695e	3460	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	3461	* @param SeqDiscont This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	3462	* @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
EricLew	0:80ee8f3b695e	3463	* @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
EricLew	0:80ee8f3b695e	3464	* @retval None
EricLew	0:80ee8f3b695e	3465	*/
EricLew	0:80ee8f3b695e	3466	__STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
EricLew	0:80ee8f3b695e	3467	{
EricLew	0:80ee8f3b695e	3468	MODIFY_REG(ADCx->CFGR, ADC_CFGR_JDISCEN, SeqDiscont);
EricLew	0:80ee8f3b695e	3469	}
EricLew	0:80ee8f3b695e	3470
EricLew	0:80ee8f3b695e	3471	/**
EricLew	0:80ee8f3b695e	3472	* @brief Get ADC group injected sequencer discontinuous mode:
EricLew	0:80ee8f3b695e	3473	* sequence subdivided and scan conversions interrupted every selected
EricLew	0:80ee8f3b695e	3474	* number of ranks.
EricLew	0:80ee8f3b695e	3475	* @rmtoll CFGR JDISCEN LL_ADC_INJ_GetSequencerDiscont
EricLew	0:80ee8f3b695e	3476	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	3477	* @retval Returned value can be one of the following values:
EricLew	0:80ee8f3b695e	3478	* @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
EricLew	0:80ee8f3b695e	3479	* @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
EricLew	0:80ee8f3b695e	3480	*/
EricLew	0:80ee8f3b695e	3481	__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	3482	{
EricLew	0:80ee8f3b695e	3483	return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JDISCEN));
EricLew	0:80ee8f3b695e	3484	}
EricLew	0:80ee8f3b695e	3485
EricLew	0:80ee8f3b695e	3486	/**
EricLew	0:80ee8f3b695e	3487	* @brief Set ADC group injected sequence: channel on the selected
EricLew	0:80ee8f3b695e	3488	* sequence rank.
EricLew	0:80ee8f3b695e	3489	* @note Depending on devices and packages, some channels may not be available.
EricLew	0:80ee8f3b695e	3490	* Refer to device datasheet for channels availability.
EricLew	0:80ee8f3b695e	3491	* @note On this STM32 family, to measure internal channels (VrefInt,
EricLew	0:80ee8f3b695e	3492	* TempSensor, ...), measurement paths to internal channels must be
EricLew	0:80ee8f3b695e	3493	* enabled separately.
EricLew	0:80ee8f3b695e	3494	* This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
EricLew	0:80ee8f3b695e	3495	* @note On this STM32 family, some fast channels are available: fast analog inputs
EricLew	0:80ee8f3b695e	3496	* coming from GPIO pads (ADC_IN1..5).
EricLew	0:80ee8f3b695e	3497	* @note On this STM32 family, setting of this feature is conditioned to
EricLew	0:80ee8f3b695e	3498	* ADC state:
EricLew	0:80ee8f3b695e	3499	* ADC must not be disabled. Can be enabled with or without conversion
EricLew	0:80ee8f3b695e	3500	* on going on either groups regular or injected.
EricLew	0:80ee8f3b695e	3501	* @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n
EricLew	0:80ee8f3b695e	3502	* JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n
EricLew	0:80ee8f3b695e	3503	* JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n
EricLew	0:80ee8f3b695e	3504	* JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks
EricLew	0:80ee8f3b695e	3505	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	3506	* @param Rank This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	3507	* @arg @ref LL_ADC_INJ_RANK_1
EricLew	0:80ee8f3b695e	3508	* @arg @ref LL_ADC_INJ_RANK_2
EricLew	0:80ee8f3b695e	3509	* @arg @ref LL_ADC_INJ_RANK_3
EricLew	0:80ee8f3b695e	3510	* @arg @ref LL_ADC_INJ_RANK_4
EricLew	0:80ee8f3b695e	3511	* @param Channel This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	3512	* @arg @ref LL_ADC_CHANNEL_0
EricLew	0:80ee8f3b695e	3513	* @arg @ref LL_ADC_CHANNEL_1 (5)
EricLew	0:80ee8f3b695e	3514	* @arg @ref LL_ADC_CHANNEL_2 (5)
EricLew	0:80ee8f3b695e	3515	* @arg @ref LL_ADC_CHANNEL_3 (5)
EricLew	0:80ee8f3b695e	3516	* @arg @ref LL_ADC_CHANNEL_4 (5)
EricLew	0:80ee8f3b695e	3517	* @arg @ref LL_ADC_CHANNEL_5 (5)
EricLew	0:80ee8f3b695e	3518	* @arg @ref LL_ADC_CHANNEL_6
EricLew	0:80ee8f3b695e	3519	* @arg @ref LL_ADC_CHANNEL_7
EricLew	0:80ee8f3b695e	3520	* @arg @ref LL_ADC_CHANNEL_8
EricLew	0:80ee8f3b695e	3521	* @arg @ref LL_ADC_CHANNEL_9
EricLew	0:80ee8f3b695e	3522	* @arg @ref LL_ADC_CHANNEL_10
EricLew	0:80ee8f3b695e	3523	* @arg @ref LL_ADC_CHANNEL_11
EricLew	0:80ee8f3b695e	3524	* @arg @ref LL_ADC_CHANNEL_12
EricLew	0:80ee8f3b695e	3525	* @arg @ref LL_ADC_CHANNEL_13
EricLew	0:80ee8f3b695e	3526	* @arg @ref LL_ADC_CHANNEL_14
EricLew	0:80ee8f3b695e	3527	* @arg @ref LL_ADC_CHANNEL_15
EricLew	0:80ee8f3b695e	3528	* @arg @ref LL_ADC_CHANNEL_16
EricLew	0:80ee8f3b695e	3529	* @arg @ref LL_ADC_CHANNEL_17
EricLew	0:80ee8f3b695e	3530	* @arg @ref LL_ADC_CHANNEL_18
EricLew	0:80ee8f3b695e	3531	* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
EricLew	0:80ee8f3b695e	3532	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
EricLew	0:80ee8f3b695e	3533	* @arg @ref LL_ADC_CHANNEL_VBAT (4)
EricLew	0:80ee8f3b695e	3534	* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
EricLew	0:80ee8f3b695e	3535	* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
EricLew	0:80ee8f3b695e	3536	* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)
EricLew	0:80ee8f3b695e	3537	* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)
EricLew	0:80ee8f3b695e	3538	* (1) On STM32L4, parameter available only on ADC instance: ADC1.
EricLew	0:80ee8f3b695e	3539	* (2) On STM32L4, parameter available only on ADC instance: ADC2.
EricLew	0:80ee8f3b695e	3540	* (3) On STM32L4, parameter available only on ADC instance: ADC3.
EricLew	0:80ee8f3b695e	3541	* (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.
EricLew	0:80ee8f3b695e	3542	* (5) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
EricLew	0:80ee8f3b695e	3543	* Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
EricLew	0:80ee8f3b695e	3544	* @retval None
EricLew	0:80ee8f3b695e	3545	*/
EricLew	0:80ee8f3b695e	3546	__STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
EricLew	0:80ee8f3b695e	3547	{
EricLew	0:80ee8f3b695e	3548	/* Set bits with content of parameter "Channel" with bits position */
EricLew	0:80ee8f3b695e	3549	/* in register depending on parameter "Rank". */
EricLew	0:80ee8f3b695e	3550	/* Parameters "Rank" and "Channel" are used with masks because containing */
EricLew	0:80ee8f3b695e	3551	/* other bits reserved for other purpose. */
EricLew	0:80ee8f3b695e	3552	MODIFY_REG(ADCx->JSQR,
EricLew	0:80ee8f3b695e	3553	ADC_CHANNEL_ID_NUMBER_MASK >> (POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) - (Rank & ADC_INJ_RANK_ID_JSQR_MASK)),
EricLew	0:80ee8f3b695e	3554	(Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> (POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) - (Rank & ADC_INJ_RANK_ID_JSQR_MASK)));
EricLew	0:80ee8f3b695e	3555	}
EricLew	0:80ee8f3b695e	3556
EricLew	0:80ee8f3b695e	3557	/**
EricLew	0:80ee8f3b695e	3558	* @brief Get ADC group injected sequence: channel on the selected
EricLew	0:80ee8f3b695e	3559	* sequence rank.
EricLew	0:80ee8f3b695e	3560	* @note Depending on devices and packages, some channels may not be available.
EricLew	0:80ee8f3b695e	3561	* Refer to device datasheet for channels availability.
EricLew	0:80ee8f3b695e	3562	* @note Usage of the returned channel number:
EricLew	0:80ee8f3b695e	3563	* - To reinject this channel into another function LL_ADC_xxx:
EricLew	0:80ee8f3b695e	3564	* the returned channel number is only partly formatted on definition
EricLew	0:80ee8f3b695e	3565	* of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
EricLew	0:80ee8f3b695e	3566	* with literals LL_ADC_CHANNEL_x, then the selected
EricLew	0:80ee8f3b695e	3567	* literal LL_ADC_CHANNEL_x can be used as parameter for another
EricLew	0:80ee8f3b695e	3568	* function.
EricLew	0:80ee8f3b695e	3569	* - To get the channel number in decimal format:
EricLew	0:80ee8f3b695e	3570	* process the returned value with the helper macro
EricLew	0:80ee8f3b695e	3571	* @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
EricLew	0:80ee8f3b695e	3572	* @rmtoll JSQR JSQ1 LL_ADC_INJ_GetSequencerRanks\n
EricLew	0:80ee8f3b695e	3573	* JSQR JSQ2 LL_ADC_INJ_GetSequencerRanks\n
EricLew	0:80ee8f3b695e	3574	* JSQR JSQ3 LL_ADC_INJ_GetSequencerRanks\n
EricLew	0:80ee8f3b695e	3575	* JSQR JSQ4 LL_ADC_INJ_GetSequencerRanks
EricLew	0:80ee8f3b695e	3576	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	3577	* @param Rank This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	3578	* @arg @ref LL_ADC_INJ_RANK_1
EricLew	0:80ee8f3b695e	3579	* @arg @ref LL_ADC_INJ_RANK_2
EricLew	0:80ee8f3b695e	3580	* @arg @ref LL_ADC_INJ_RANK_3
EricLew	0:80ee8f3b695e	3581	* @arg @ref LL_ADC_INJ_RANK_4
EricLew	0:80ee8f3b695e	3582	* @retval Returned value can be one of the following values:
EricLew	0:80ee8f3b695e	3583	* @arg @ref LL_ADC_CHANNEL_0
EricLew	0:80ee8f3b695e	3584	* @arg @ref LL_ADC_CHANNEL_1 (5)
EricLew	0:80ee8f3b695e	3585	* @arg @ref LL_ADC_CHANNEL_2 (5)
EricLew	0:80ee8f3b695e	3586	* @arg @ref LL_ADC_CHANNEL_3 (5)
EricLew	0:80ee8f3b695e	3587	* @arg @ref LL_ADC_CHANNEL_4 (5)
EricLew	0:80ee8f3b695e	3588	* @arg @ref LL_ADC_CHANNEL_5 (5)
EricLew	0:80ee8f3b695e	3589	* @arg @ref LL_ADC_CHANNEL_6
EricLew	0:80ee8f3b695e	3590	* @arg @ref LL_ADC_CHANNEL_7
EricLew	0:80ee8f3b695e	3591	* @arg @ref LL_ADC_CHANNEL_8
EricLew	0:80ee8f3b695e	3592	* @arg @ref LL_ADC_CHANNEL_9
EricLew	0:80ee8f3b695e	3593	* @arg @ref LL_ADC_CHANNEL_10
EricLew	0:80ee8f3b695e	3594	* @arg @ref LL_ADC_CHANNEL_11
EricLew	0:80ee8f3b695e	3595	* @arg @ref LL_ADC_CHANNEL_12
EricLew	0:80ee8f3b695e	3596	* @arg @ref LL_ADC_CHANNEL_13
EricLew	0:80ee8f3b695e	3597	* @arg @ref LL_ADC_CHANNEL_14
EricLew	0:80ee8f3b695e	3598	* @arg @ref LL_ADC_CHANNEL_15
EricLew	0:80ee8f3b695e	3599	* @arg @ref LL_ADC_CHANNEL_16
EricLew	0:80ee8f3b695e	3600	* @arg @ref LL_ADC_CHANNEL_17
EricLew	0:80ee8f3b695e	3601	* @arg @ref LL_ADC_CHANNEL_18
EricLew	0:80ee8f3b695e	3602	* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
EricLew	0:80ee8f3b695e	3603	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
EricLew	0:80ee8f3b695e	3604	* @arg @ref LL_ADC_CHANNEL_VBAT (4)
EricLew	0:80ee8f3b695e	3605	* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
EricLew	0:80ee8f3b695e	3606	* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
EricLew	0:80ee8f3b695e	3607	* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)
EricLew	0:80ee8f3b695e	3608	* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)
EricLew	0:80ee8f3b695e	3609	* (1) On STM32L4, parameter available only on ADC instance: ADC1.
EricLew	0:80ee8f3b695e	3610	* (2) On STM32L4, parameter available only on ADC instance: ADC2.
EricLew	0:80ee8f3b695e	3611	* (3) On STM32L4, parameter available only on ADC instance: ADC3.
EricLew	0:80ee8f3b695e	3612	* (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.
EricLew	0:80ee8f3b695e	3613	* (5) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
EricLew	0:80ee8f3b695e	3614	* Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
EricLew	0:80ee8f3b695e	3615	* (1, 2, 3, 4) For ADC channel read back from ADC register,
EricLew	0:80ee8f3b695e	3616	* comparison with internal channel parameter to be done
EricLew	0:80ee8f3b695e	3617	* using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
EricLew	0:80ee8f3b695e	3618	*/
EricLew	0:80ee8f3b695e	3619	__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
EricLew	0:80ee8f3b695e	3620	{
EricLew	0:80ee8f3b695e	3621	return (uint32_t)(READ_BIT(ADCx->JSQR,
EricLew	0:80ee8f3b695e	3622	ADC_CHANNEL_ID_NUMBER_MASK >> (POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) - (Rank & ADC_INJ_RANK_ID_JSQR_MASK)))
EricLew	0:80ee8f3b695e	3623	<< (POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) - (Rank & ADC_INJ_RANK_ID_JSQR_MASK))
EricLew	0:80ee8f3b695e	3624	);
EricLew	0:80ee8f3b695e	3625	}
EricLew	0:80ee8f3b695e	3626
EricLew	0:80ee8f3b695e	3627	/**
EricLew	0:80ee8f3b695e	3628	* @brief Set one context on ADC group injected that will be checked in
EricLew	0:80ee8f3b695e	3629	* contexts queue.
EricLew	0:80ee8f3b695e	3630	* A context is a setting of injected group sequencer:
EricLew	0:80ee8f3b695e	3631	* * injected group trigger
EricLew	0:80ee8f3b695e	3632	* * sequencer length
EricLew	0:80ee8f3b695e	3633	* * sequencer ranks
EricLew	0:80ee8f3b695e	3634	* This function is intended to be used when contexts queue is enabled,
EricLew	0:80ee8f3b695e	3635	* because the sequence must be fully configured in one time
EricLew	0:80ee8f3b695e	3636	* (functions to set separately injected trigger and sequencer channels
EricLew	0:80ee8f3b695e	3637	* cannot be used):
EricLew	0:80ee8f3b695e	3638	* Refer to function @ref LL_ADC_INJ_SetQueueMode().
EricLew	0:80ee8f3b695e	3639	* @note In the contexts queue, only the active context can be read.
EricLew	0:80ee8f3b695e	3640	* The parameters of this function can be read using functions:
EricLew	0:80ee8f3b695e	3641	* - @ref LL_ADC_INJ_GetTrigSource()
EricLew	0:80ee8f3b695e	3642	* - @ref LL_ADC_INJ_GetTrigEdge()
EricLew	0:80ee8f3b695e	3643	* - @ref LL_ADC_INJ_GetSequencerRanks()
EricLew	0:80ee8f3b695e	3644	* @note On this STM32 family, to measure internal channels (VrefInt,
EricLew	0:80ee8f3b695e	3645	* TempSensor, ...), measurement paths to internal channels must be
EricLew	0:80ee8f3b695e	3646	* enabled separately.
EricLew	0:80ee8f3b695e	3647	* This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
EricLew	0:80ee8f3b695e	3648	* @note On this STM32 family, some fast channels are available: fast analog inputs
EricLew	0:80ee8f3b695e	3649	* coming from GPIO pads (ADC_IN1..5).
EricLew	0:80ee8f3b695e	3650	* @note On this STM32 family, setting of this feature is conditioned to
EricLew	0:80ee8f3b695e	3651	* ADC state:
EricLew	0:80ee8f3b695e	3652	* ADC must not be disabled. Can be enabled with or without conversion
EricLew	0:80ee8f3b695e	3653	* on going on either groups regular or injected.
EricLew	0:80ee8f3b695e	3654	* @rmtoll JSQR JEXTSEL LL_ADC_INJ_ConfigQueueContext\n
EricLew	0:80ee8f3b695e	3655	* JSQR JEXTEN LL_ADC_INJ_ConfigQueueContext\n
EricLew	0:80ee8f3b695e	3656	* JSQR JL LL_ADC_INJ_ConfigQueueContext\n
EricLew	0:80ee8f3b695e	3657	* JSQR JSQ1 LL_ADC_INJ_ConfigQueueContext\n
EricLew	0:80ee8f3b695e	3658	* JSQR JSQ2 LL_ADC_INJ_ConfigQueueContext\n
EricLew	0:80ee8f3b695e	3659	* JSQR JSQ3 LL_ADC_INJ_ConfigQueueContext\n
EricLew	0:80ee8f3b695e	3660	* JSQR JSQ4 LL_ADC_INJ_ConfigQueueContext
EricLew	0:80ee8f3b695e	3661	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	3662	* @param TriggerSource This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	3663	* @arg @ref LL_ADC_INJ_TRIG_SW_START
EricLew	0:80ee8f3b695e	3664	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
EricLew	0:80ee8f3b695e	3665	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CC4
EricLew	0:80ee8f3b695e	3666	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
EricLew	0:80ee8f3b695e	3667	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CC1
EricLew	0:80ee8f3b695e	3668	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CC4
EricLew	0:80ee8f3b695e	3669	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
EricLew	0:80ee8f3b695e	3670	* @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
EricLew	0:80ee8f3b695e	3671	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CC4
EricLew	0:80ee8f3b695e	3672	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
EricLew	0:80ee8f3b695e	3673	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
EricLew	0:80ee8f3b695e	3674	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
EricLew	0:80ee8f3b695e	3675	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CC3
EricLew	0:80ee8f3b695e	3676	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
EricLew	0:80ee8f3b695e	3677	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CC1
EricLew	0:80ee8f3b695e	3678	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
EricLew	0:80ee8f3b695e	3679	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
EricLew	0:80ee8f3b695e	3680	* @param ExternalTriggerEdge This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	3681	* @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
EricLew	0:80ee8f3b695e	3682	* @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
EricLew	0:80ee8f3b695e	3683	* @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
EricLew	0:80ee8f3b695e	3684	* @param SequencerNbRanks This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	3685	* @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
EricLew	0:80ee8f3b695e	3686	* @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
EricLew	0:80ee8f3b695e	3687	* @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
EricLew	0:80ee8f3b695e	3688	* @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
EricLew	0:80ee8f3b695e	3689	* @param Rank1_Channel This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	3690	* @arg @ref LL_ADC_CHANNEL_0
EricLew	0:80ee8f3b695e	3691	* @arg @ref LL_ADC_CHANNEL_1 (5)
EricLew	0:80ee8f3b695e	3692	* @arg @ref LL_ADC_CHANNEL_2 (5)
EricLew	0:80ee8f3b695e	3693	* @arg @ref LL_ADC_CHANNEL_3 (5)
EricLew	0:80ee8f3b695e	3694	* @arg @ref LL_ADC_CHANNEL_4 (5)
EricLew	0:80ee8f3b695e	3695	* @arg @ref LL_ADC_CHANNEL_5 (5)
EricLew	0:80ee8f3b695e	3696	* @arg @ref LL_ADC_CHANNEL_6
EricLew	0:80ee8f3b695e	3697	* @arg @ref LL_ADC_CHANNEL_7
EricLew	0:80ee8f3b695e	3698	* @arg @ref LL_ADC_CHANNEL_8
EricLew	0:80ee8f3b695e	3699	* @arg @ref LL_ADC_CHANNEL_9
EricLew	0:80ee8f3b695e	3700	* @arg @ref LL_ADC_CHANNEL_10
EricLew	0:80ee8f3b695e	3701	* @arg @ref LL_ADC_CHANNEL_11
EricLew	0:80ee8f3b695e	3702	* @arg @ref LL_ADC_CHANNEL_12
EricLew	0:80ee8f3b695e	3703	* @arg @ref LL_ADC_CHANNEL_13
EricLew	0:80ee8f3b695e	3704	* @arg @ref LL_ADC_CHANNEL_14
EricLew	0:80ee8f3b695e	3705	* @arg @ref LL_ADC_CHANNEL_15
EricLew	0:80ee8f3b695e	3706	* @arg @ref LL_ADC_CHANNEL_16
EricLew	0:80ee8f3b695e	3707	* @arg @ref LL_ADC_CHANNEL_17
EricLew	0:80ee8f3b695e	3708	* @arg @ref LL_ADC_CHANNEL_18
EricLew	0:80ee8f3b695e	3709	* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
EricLew	0:80ee8f3b695e	3710	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
EricLew	0:80ee8f3b695e	3711	* @arg @ref LL_ADC_CHANNEL_VBAT (4)
EricLew	0:80ee8f3b695e	3712	* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
EricLew	0:80ee8f3b695e	3713	* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
EricLew	0:80ee8f3b695e	3714	* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)
EricLew	0:80ee8f3b695e	3715	* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)
EricLew	0:80ee8f3b695e	3716	* (1) On STM32L4, parameter available only on ADC instance: ADC1.
EricLew	0:80ee8f3b695e	3717	* (2) On STM32L4, parameter available only on ADC instance: ADC2.
EricLew	0:80ee8f3b695e	3718	* (3) On STM32L4, parameter available only on ADC instance: ADC3.
EricLew	0:80ee8f3b695e	3719	* (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.
EricLew	0:80ee8f3b695e	3720	* (5) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
EricLew	0:80ee8f3b695e	3721	* Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
EricLew	0:80ee8f3b695e	3722	* @param Rank2_Channel This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	3723	* @arg @ref LL_ADC_CHANNEL_0
EricLew	0:80ee8f3b695e	3724	* @arg @ref LL_ADC_CHANNEL_1 (5)
EricLew	0:80ee8f3b695e	3725	* @arg @ref LL_ADC_CHANNEL_2 (5)
EricLew	0:80ee8f3b695e	3726	* @arg @ref LL_ADC_CHANNEL_3 (5)
EricLew	0:80ee8f3b695e	3727	* @arg @ref LL_ADC_CHANNEL_4 (5)
EricLew	0:80ee8f3b695e	3728	* @arg @ref LL_ADC_CHANNEL_5 (5)
EricLew	0:80ee8f3b695e	3729	* @arg @ref LL_ADC_CHANNEL_6
EricLew	0:80ee8f3b695e	3730	* @arg @ref LL_ADC_CHANNEL_7
EricLew	0:80ee8f3b695e	3731	* @arg @ref LL_ADC_CHANNEL_8
EricLew	0:80ee8f3b695e	3732	* @arg @ref LL_ADC_CHANNEL_9
EricLew	0:80ee8f3b695e	3733	* @arg @ref LL_ADC_CHANNEL_10
EricLew	0:80ee8f3b695e	3734	* @arg @ref LL_ADC_CHANNEL_11
EricLew	0:80ee8f3b695e	3735	* @arg @ref LL_ADC_CHANNEL_12
EricLew	0:80ee8f3b695e	3736	* @arg @ref LL_ADC_CHANNEL_13
EricLew	0:80ee8f3b695e	3737	* @arg @ref LL_ADC_CHANNEL_14
EricLew	0:80ee8f3b695e	3738	* @arg @ref LL_ADC_CHANNEL_15
EricLew	0:80ee8f3b695e	3739	* @arg @ref LL_ADC_CHANNEL_16
EricLew	0:80ee8f3b695e	3740	* @arg @ref LL_ADC_CHANNEL_17
EricLew	0:80ee8f3b695e	3741	* @arg @ref LL_ADC_CHANNEL_18
EricLew	0:80ee8f3b695e	3742	* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
EricLew	0:80ee8f3b695e	3743	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
EricLew	0:80ee8f3b695e	3744	* @arg @ref LL_ADC_CHANNEL_VBAT (4)
EricLew	0:80ee8f3b695e	3745	* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
EricLew	0:80ee8f3b695e	3746	* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
EricLew	0:80ee8f3b695e	3747	* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)
EricLew	0:80ee8f3b695e	3748	* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)
EricLew	0:80ee8f3b695e	3749	* (1) On STM32L4, parameter available only on ADC instance: ADC1.
EricLew	0:80ee8f3b695e	3750	* (2) On STM32L4, parameter available only on ADC instance: ADC2.
EricLew	0:80ee8f3b695e	3751	* (3) On STM32L4, parameter available only on ADC instance: ADC3.
EricLew	0:80ee8f3b695e	3752	* (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.
EricLew	0:80ee8f3b695e	3753	* (5) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
EricLew	0:80ee8f3b695e	3754	* Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
EricLew	0:80ee8f3b695e	3755	* @param Rank3_Channel This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	3756	* @arg @ref LL_ADC_CHANNEL_0
EricLew	0:80ee8f3b695e	3757	* @arg @ref LL_ADC_CHANNEL_1 (5)
EricLew	0:80ee8f3b695e	3758	* @arg @ref LL_ADC_CHANNEL_2 (5)
EricLew	0:80ee8f3b695e	3759	* @arg @ref LL_ADC_CHANNEL_3 (5)
EricLew	0:80ee8f3b695e	3760	* @arg @ref LL_ADC_CHANNEL_4 (5)
EricLew	0:80ee8f3b695e	3761	* @arg @ref LL_ADC_CHANNEL_5 (5)
EricLew	0:80ee8f3b695e	3762	* @arg @ref LL_ADC_CHANNEL_6
EricLew	0:80ee8f3b695e	3763	* @arg @ref LL_ADC_CHANNEL_7
EricLew	0:80ee8f3b695e	3764	* @arg @ref LL_ADC_CHANNEL_8
EricLew	0:80ee8f3b695e	3765	* @arg @ref LL_ADC_CHANNEL_9
EricLew	0:80ee8f3b695e	3766	* @arg @ref LL_ADC_CHANNEL_10
EricLew	0:80ee8f3b695e	3767	* @arg @ref LL_ADC_CHANNEL_11
EricLew	0:80ee8f3b695e	3768	* @arg @ref LL_ADC_CHANNEL_12
EricLew	0:80ee8f3b695e	3769	* @arg @ref LL_ADC_CHANNEL_13
EricLew	0:80ee8f3b695e	3770	* @arg @ref LL_ADC_CHANNEL_14
EricLew	0:80ee8f3b695e	3771	* @arg @ref LL_ADC_CHANNEL_15
EricLew	0:80ee8f3b695e	3772	* @arg @ref LL_ADC_CHANNEL_16
EricLew	0:80ee8f3b695e	3773	* @arg @ref LL_ADC_CHANNEL_17
EricLew	0:80ee8f3b695e	3774	* @arg @ref LL_ADC_CHANNEL_18
EricLew	0:80ee8f3b695e	3775	* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
EricLew	0:80ee8f3b695e	3776	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
EricLew	0:80ee8f3b695e	3777	* @arg @ref LL_ADC_CHANNEL_VBAT (4)
EricLew	0:80ee8f3b695e	3778	* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
EricLew	0:80ee8f3b695e	3779	* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
EricLew	0:80ee8f3b695e	3780	* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)
EricLew	0:80ee8f3b695e	3781	* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)
EricLew	0:80ee8f3b695e	3782	* (1) On STM32L4, parameter available only on ADC instance: ADC1.
EricLew	0:80ee8f3b695e	3783	* (2) On STM32L4, parameter available only on ADC instance: ADC2.
EricLew	0:80ee8f3b695e	3784	* (3) On STM32L4, parameter available only on ADC instance: ADC3.
EricLew	0:80ee8f3b695e	3785	* (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.
EricLew	0:80ee8f3b695e	3786	* (5) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
EricLew	0:80ee8f3b695e	3787	* Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
EricLew	0:80ee8f3b695e	3788	* @param Rank4_Channel This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	3789	* @arg @ref LL_ADC_CHANNEL_0
EricLew	0:80ee8f3b695e	3790	* @arg @ref LL_ADC_CHANNEL_1 (5)
EricLew	0:80ee8f3b695e	3791	* @arg @ref LL_ADC_CHANNEL_2 (5)
EricLew	0:80ee8f3b695e	3792	* @arg @ref LL_ADC_CHANNEL_3 (5)
EricLew	0:80ee8f3b695e	3793	* @arg @ref LL_ADC_CHANNEL_4 (5)
EricLew	0:80ee8f3b695e	3794	* @arg @ref LL_ADC_CHANNEL_5 (5)
EricLew	0:80ee8f3b695e	3795	* @arg @ref LL_ADC_CHANNEL_6
EricLew	0:80ee8f3b695e	3796	* @arg @ref LL_ADC_CHANNEL_7
EricLew	0:80ee8f3b695e	3797	* @arg @ref LL_ADC_CHANNEL_8
EricLew	0:80ee8f3b695e	3798	* @arg @ref LL_ADC_CHANNEL_9
EricLew	0:80ee8f3b695e	3799	* @arg @ref LL_ADC_CHANNEL_10
EricLew	0:80ee8f3b695e	3800	* @arg @ref LL_ADC_CHANNEL_11
EricLew	0:80ee8f3b695e	3801	* @arg @ref LL_ADC_CHANNEL_12
EricLew	0:80ee8f3b695e	3802	* @arg @ref LL_ADC_CHANNEL_13
EricLew	0:80ee8f3b695e	3803	* @arg @ref LL_ADC_CHANNEL_14
EricLew	0:80ee8f3b695e	3804	* @arg @ref LL_ADC_CHANNEL_15
EricLew	0:80ee8f3b695e	3805	* @arg @ref LL_ADC_CHANNEL_16
EricLew	0:80ee8f3b695e	3806	* @arg @ref LL_ADC_CHANNEL_17
EricLew	0:80ee8f3b695e	3807	* @arg @ref LL_ADC_CHANNEL_18
EricLew	0:80ee8f3b695e	3808	* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
EricLew	0:80ee8f3b695e	3809	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
EricLew	0:80ee8f3b695e	3810	* @arg @ref LL_ADC_CHANNEL_VBAT (4)
EricLew	0:80ee8f3b695e	3811	* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
EricLew	0:80ee8f3b695e	3812	* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
EricLew	0:80ee8f3b695e	3813	* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)
EricLew	0:80ee8f3b695e	3814	* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)
EricLew	0:80ee8f3b695e	3815	* (1) On STM32L4, parameter available only on ADC instance: ADC1.
EricLew	0:80ee8f3b695e	3816	* (2) On STM32L4, parameter available only on ADC instance: ADC2.
EricLew	0:80ee8f3b695e	3817	* (3) On STM32L4, parameter available only on ADC instance: ADC3.
EricLew	0:80ee8f3b695e	3818	* (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.
EricLew	0:80ee8f3b695e	3819	* (5) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
EricLew	0:80ee8f3b695e	3820	* Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
EricLew	0:80ee8f3b695e	3821	* @retval None
EricLew	0:80ee8f3b695e	3822	*/
EricLew	0:80ee8f3b695e	3823	__STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx,
EricLew	0:80ee8f3b695e	3824	uint32_t TriggerSource,
EricLew	0:80ee8f3b695e	3825	uint32_t ExternalTriggerEdge,
EricLew	0:80ee8f3b695e	3826	uint32_t SequencerNbRanks,
EricLew	0:80ee8f3b695e	3827	uint32_t Rank1_Channel,
EricLew	0:80ee8f3b695e	3828	uint32_t Rank2_Channel,
EricLew	0:80ee8f3b695e	3829	uint32_t Rank3_Channel,
EricLew	0:80ee8f3b695e	3830	uint32_t Rank4_Channel)
EricLew	0:80ee8f3b695e	3831	{
EricLew	0:80ee8f3b695e	3832	/* Set bits with content of parameter "Rankx_Channel" with bits position */
EricLew	0:80ee8f3b695e	3833	/* in register depending on literal "LL_ADC_INJ_RANK_x". */
EricLew	0:80ee8f3b695e	3834	/* Parameters "Rankx_Channel" and "LL_ADC_INJ_RANK_x" are used with masks */
EricLew	0:80ee8f3b695e	3835	/* because containing other bits reserved for other purpose. */
EricLew	0:80ee8f3b695e	3836	MODIFY_REG(ADCx->JSQR ,
EricLew	0:80ee8f3b695e	3837	ADC_JSQR_JEXTSEL \|
EricLew	0:80ee8f3b695e	3838	ADC_JSQR_JEXTEN \|
EricLew	0:80ee8f3b695e	3839	ADC_JSQR_JSQ4 \|
EricLew	0:80ee8f3b695e	3840	ADC_JSQR_JSQ3 \|
EricLew	0:80ee8f3b695e	3841	ADC_JSQR_JSQ2 \|
EricLew	0:80ee8f3b695e	3842	ADC_JSQR_JSQ1 \|
EricLew	0:80ee8f3b695e	3843	ADC_JSQR_JL ,
EricLew	0:80ee8f3b695e	3844	TriggerSource \|
EricLew	0:80ee8f3b695e	3845	ExternalTriggerEdge \|
EricLew	0:80ee8f3b695e	3846	((Rank4_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> (POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) - (LL_ADC_INJ_RANK_4 & ADC_INJ_RANK_ID_JSQR_MASK))) \|
EricLew	0:80ee8f3b695e	3847	((Rank3_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> (POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) - (LL_ADC_INJ_RANK_3 & ADC_INJ_RANK_ID_JSQR_MASK))) \|
EricLew	0:80ee8f3b695e	3848	((Rank2_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> (POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) - (LL_ADC_INJ_RANK_2 & ADC_INJ_RANK_ID_JSQR_MASK))) \|
EricLew	0:80ee8f3b695e	3849	((Rank1_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> (POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) - (LL_ADC_INJ_RANK_1 & ADC_INJ_RANK_ID_JSQR_MASK))) \|
EricLew	0:80ee8f3b695e	3850	SequencerNbRanks
EricLew	0:80ee8f3b695e	3851	);
EricLew	0:80ee8f3b695e	3852	}
EricLew	0:80ee8f3b695e	3853
EricLew	0:80ee8f3b695e	3854	/**
EricLew	0:80ee8f3b695e	3855	* @}
EricLew	0:80ee8f3b695e	3856	*/
EricLew	0:80ee8f3b695e	3857
EricLew	0:80ee8f3b695e	3858	/** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels
EricLew	0:80ee8f3b695e	3859	* @{
EricLew	0:80ee8f3b695e	3860	*/
EricLew	0:80ee8f3b695e	3861
EricLew	0:80ee8f3b695e	3862	/**
EricLew	0:80ee8f3b695e	3863	* @brief Set sampling time of the selected ADC channel.
EricLew	0:80ee8f3b695e	3864	* Unit: ADC clock cycles.
EricLew	0:80ee8f3b695e	3865	* On this device, sampling time is on channel scope: independently
EricLew	0:80ee8f3b695e	3866	* of channel mapped on ADC group regular or injected.
EricLew	0:80ee8f3b695e	3867	* @note In case of internal channel (VrefInt, TempSensor, ...) to be
EricLew	0:80ee8f3b695e	3868	* converted:
EricLew	0:80ee8f3b695e	3869	* sampling time constraints must be respected (sampling time can be
EricLew	0:80ee8f3b695e	3870	* adjusted in function of ADC clock frequency and sampling time
EricLew	0:80ee8f3b695e	3871	* setting).
EricLew	0:80ee8f3b695e	3872	* Refer to device datasheet for timings values (parameters TS_vrefint,
EricLew	0:80ee8f3b695e	3873	* TS_temp, ...).
EricLew	0:80ee8f3b695e	3874	* @note Conversion time is the addition of sampling time and processing time.
EricLew	0:80ee8f3b695e	3875	* On this STM32 family, ADC processing time is:
EricLew	0:80ee8f3b695e	3876	* - 12.5 ADC clock cycles at ADC resolution 12 bits
EricLew	0:80ee8f3b695e	3877	* - 10.5 ADC clock cycles at ADC resolution 10 bits
EricLew	0:80ee8f3b695e	3878	* - 8.5 ADC clock cycles at ADC resolution 8 bits
EricLew	0:80ee8f3b695e	3879	* - 6.5 ADC clock cycles at ADC resolution 6 bits
EricLew	0:80ee8f3b695e	3880	* @note On this STM32 family, setting of this feature is conditioned to
EricLew	0:80ee8f3b695e	3881	* ADC state:
EricLew	0:80ee8f3b695e	3882	* ADC must be disabled or enabled without conversion on going
EricLew	0:80ee8f3b695e	3883	* on either groups regular or injected.
EricLew	0:80ee8f3b695e	3884	* @rmtoll SMPR1 SMP0 LL_ADC_SetChannelSamplingTime\n
EricLew	0:80ee8f3b695e	3885	* SMPR1 SMP1 LL_ADC_SetChannelSamplingTime\n
EricLew	0:80ee8f3b695e	3886	* SMPR1 SMP2 LL_ADC_SetChannelSamplingTime\n
EricLew	0:80ee8f3b695e	3887	* SMPR1 SMP3 LL_ADC_SetChannelSamplingTime\n
EricLew	0:80ee8f3b695e	3888	* SMPR1 SMP4 LL_ADC_SetChannelSamplingTime\n
EricLew	0:80ee8f3b695e	3889	* SMPR1 SMP5 LL_ADC_SetChannelSamplingTime\n
EricLew	0:80ee8f3b695e	3890	* SMPR1 SMP6 LL_ADC_SetChannelSamplingTime\n
EricLew	0:80ee8f3b695e	3891	* SMPR1 SMP7 LL_ADC_SetChannelSamplingTime\n
EricLew	0:80ee8f3b695e	3892	* SMPR1 SMP8 LL_ADC_SetChannelSamplingTime\n
EricLew	0:80ee8f3b695e	3893	* SMPR1 SMP9 LL_ADC_SetChannelSamplingTime\n
EricLew	0:80ee8f3b695e	3894	* SMPR2 SMP10 LL_ADC_SetChannelSamplingTime\n
EricLew	0:80ee8f3b695e	3895	* SMPR2 SMP11 LL_ADC_SetChannelSamplingTime\n
EricLew	0:80ee8f3b695e	3896	* SMPR2 SMP12 LL_ADC_SetChannelSamplingTime\n
EricLew	0:80ee8f3b695e	3897	* SMPR2 SMP13 LL_ADC_SetChannelSamplingTime\n
EricLew	0:80ee8f3b695e	3898	* SMPR2 SMP14 LL_ADC_SetChannelSamplingTime\n
EricLew	0:80ee8f3b695e	3899	* SMPR2 SMP15 LL_ADC_SetChannelSamplingTime\n
EricLew	0:80ee8f3b695e	3900	* SMPR2 SMP16 LL_ADC_SetChannelSamplingTime\n
EricLew	0:80ee8f3b695e	3901	* SMPR2 SMP17 LL_ADC_SetChannelSamplingTime\n
EricLew	0:80ee8f3b695e	3902	* SMPR2 SMP18 LL_ADC_SetChannelSamplingTime
EricLew	0:80ee8f3b695e	3903	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	3904	* @param Channel This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	3905	* @arg @ref LL_ADC_CHANNEL_0
EricLew	0:80ee8f3b695e	3906	* @arg @ref LL_ADC_CHANNEL_1 (5)
EricLew	0:80ee8f3b695e	3907	* @arg @ref LL_ADC_CHANNEL_2 (5)
EricLew	0:80ee8f3b695e	3908	* @arg @ref LL_ADC_CHANNEL_3 (5)
EricLew	0:80ee8f3b695e	3909	* @arg @ref LL_ADC_CHANNEL_4 (5)
EricLew	0:80ee8f3b695e	3910	* @arg @ref LL_ADC_CHANNEL_5 (5)
EricLew	0:80ee8f3b695e	3911	* @arg @ref LL_ADC_CHANNEL_6
EricLew	0:80ee8f3b695e	3912	* @arg @ref LL_ADC_CHANNEL_7
EricLew	0:80ee8f3b695e	3913	* @arg @ref LL_ADC_CHANNEL_8
EricLew	0:80ee8f3b695e	3914	* @arg @ref LL_ADC_CHANNEL_9
EricLew	0:80ee8f3b695e	3915	* @arg @ref LL_ADC_CHANNEL_10
EricLew	0:80ee8f3b695e	3916	* @arg @ref LL_ADC_CHANNEL_11
EricLew	0:80ee8f3b695e	3917	* @arg @ref LL_ADC_CHANNEL_12
EricLew	0:80ee8f3b695e	3918	* @arg @ref LL_ADC_CHANNEL_13
EricLew	0:80ee8f3b695e	3919	* @arg @ref LL_ADC_CHANNEL_14
EricLew	0:80ee8f3b695e	3920	* @arg @ref LL_ADC_CHANNEL_15
EricLew	0:80ee8f3b695e	3921	* @arg @ref LL_ADC_CHANNEL_16
EricLew	0:80ee8f3b695e	3922	* @arg @ref LL_ADC_CHANNEL_17
EricLew	0:80ee8f3b695e	3923	* @arg @ref LL_ADC_CHANNEL_18
EricLew	0:80ee8f3b695e	3924	* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
EricLew	0:80ee8f3b695e	3925	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
EricLew	0:80ee8f3b695e	3926	* @arg @ref LL_ADC_CHANNEL_VBAT (4)
EricLew	0:80ee8f3b695e	3927	* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
EricLew	0:80ee8f3b695e	3928	* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
EricLew	0:80ee8f3b695e	3929	* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)
EricLew	0:80ee8f3b695e	3930	* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)
EricLew	0:80ee8f3b695e	3931	* (1) On STM32L4, parameter available only on ADC instance: ADC1.
EricLew	0:80ee8f3b695e	3932	* (2) On STM32L4, parameter available only on ADC instance: ADC2.
EricLew	0:80ee8f3b695e	3933	* (3) On STM32L4, parameter available only on ADC instance: ADC3.
EricLew	0:80ee8f3b695e	3934	* (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.
EricLew	0:80ee8f3b695e	3935	* (5) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
EricLew	0:80ee8f3b695e	3936	* Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
EricLew	0:80ee8f3b695e	3937	* @param SamplingTime This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	3938	* @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5
EricLew	0:80ee8f3b695e	3939	* @arg @ref LL_ADC_SAMPLINGTIME_6CYCLES_5
EricLew	0:80ee8f3b695e	3940	* @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5
EricLew	0:80ee8f3b695e	3941	* @arg @ref LL_ADC_SAMPLINGTIME_24CYCLES_5
EricLew	0:80ee8f3b695e	3942	* @arg @ref LL_ADC_SAMPLINGTIME_47CYCLES_5
EricLew	0:80ee8f3b695e	3943	* @arg @ref LL_ADC_SAMPLINGTIME_92CYCLES_5
EricLew	0:80ee8f3b695e	3944	* @arg @ref LL_ADC_SAMPLINGTIME_247CYCLES_5
EricLew	0:80ee8f3b695e	3945	* @arg @ref LL_ADC_SAMPLINGTIME_640CYCLES_5
EricLew	0:80ee8f3b695e	3946	* @retval None
EricLew	0:80ee8f3b695e	3947	*/
EricLew	0:80ee8f3b695e	3948	__STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
EricLew	0:80ee8f3b695e	3949	{
EricLew	0:80ee8f3b695e	3950	/* Set bits with content of parameter "SamplingTime" with bits position */
EricLew	0:80ee8f3b695e	3951	/* in register and register position depending on parameter "Channel". */
EricLew	0:80ee8f3b695e	3952	/* Parameter "Channel" is used with masks because containing */
EricLew	0:80ee8f3b695e	3953	/* other bits reserved for other purpose. */
EricLew	0:80ee8f3b695e	3954	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
EricLew	0:80ee8f3b695e	3955
EricLew	0:80ee8f3b695e	3956	MODIFY_REG(*preg,
EricLew	0:80ee8f3b695e	3957	ADC_SMPR1_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK),
EricLew	0:80ee8f3b695e	3958	SamplingTime << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK));
EricLew	0:80ee8f3b695e	3959	}
EricLew	0:80ee8f3b695e	3960
EricLew	0:80ee8f3b695e	3961	/**
EricLew	0:80ee8f3b695e	3962	* @brief Get sampling time of the selected ADC channel.
EricLew	0:80ee8f3b695e	3963	* Unit: ADC clock cycles.
EricLew	0:80ee8f3b695e	3964	* On this device, sampling time is on channel scope: independently
EricLew	0:80ee8f3b695e	3965	* of channel mapped on ADC group regular or injected.
EricLew	0:80ee8f3b695e	3966	* @note Conversion time is the addition of sampling time and processing time.
EricLew	0:80ee8f3b695e	3967	* On this STM32 family, ADC processing time is:
EricLew	0:80ee8f3b695e	3968	* - 12.5 ADC clock cycles at ADC resolution 12 bits
EricLew	0:80ee8f3b695e	3969	* - 10.5 ADC clock cycles at ADC resolution 10 bits
EricLew	0:80ee8f3b695e	3970	* - 8.5 ADC clock cycles at ADC resolution 8 bits
EricLew	0:80ee8f3b695e	3971	* - 6.5 ADC clock cycles at ADC resolution 6 bits
EricLew	0:80ee8f3b695e	3972	* @rmtoll SMPR1 SMP0 LL_ADC_GetChannelSamplingTime\n
EricLew	0:80ee8f3b695e	3973	* SMPR1 SMP1 LL_ADC_GetChannelSamplingTime\n
EricLew	0:80ee8f3b695e	3974	* SMPR1 SMP2 LL_ADC_GetChannelSamplingTime\n
EricLew	0:80ee8f3b695e	3975	* SMPR1 SMP3 LL_ADC_GetChannelSamplingTime\n
EricLew	0:80ee8f3b695e	3976	* SMPR1 SMP4 LL_ADC_GetChannelSamplingTime\n
EricLew	0:80ee8f3b695e	3977	* SMPR1 SMP5 LL_ADC_GetChannelSamplingTime\n
EricLew	0:80ee8f3b695e	3978	* SMPR1 SMP6 LL_ADC_GetChannelSamplingTime\n
EricLew	0:80ee8f3b695e	3979	* SMPR1 SMP7 LL_ADC_GetChannelSamplingTime\n
EricLew	0:80ee8f3b695e	3980	* SMPR1 SMP8 LL_ADC_GetChannelSamplingTime\n
EricLew	0:80ee8f3b695e	3981	* SMPR1 SMP9 LL_ADC_GetChannelSamplingTime\n
EricLew	0:80ee8f3b695e	3982	* SMPR2 SMP10 LL_ADC_GetChannelSamplingTime\n
EricLew	0:80ee8f3b695e	3983	* SMPR2 SMP11 LL_ADC_GetChannelSamplingTime\n
EricLew	0:80ee8f3b695e	3984	* SMPR2 SMP12 LL_ADC_GetChannelSamplingTime\n
EricLew	0:80ee8f3b695e	3985	* SMPR2 SMP13 LL_ADC_GetChannelSamplingTime\n
EricLew	0:80ee8f3b695e	3986	* SMPR2 SMP14 LL_ADC_GetChannelSamplingTime\n
EricLew	0:80ee8f3b695e	3987	* SMPR2 SMP15 LL_ADC_GetChannelSamplingTime\n
EricLew	0:80ee8f3b695e	3988	* SMPR2 SMP16 LL_ADC_GetChannelSamplingTime\n
EricLew	0:80ee8f3b695e	3989	* SMPR2 SMP17 LL_ADC_GetChannelSamplingTime\n
EricLew	0:80ee8f3b695e	3990	* SMPR2 SMP18 LL_ADC_GetChannelSamplingTime
EricLew	0:80ee8f3b695e	3991	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	3992	* @param Channel This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	3993	* @arg @ref LL_ADC_CHANNEL_0
EricLew	0:80ee8f3b695e	3994	* @arg @ref LL_ADC_CHANNEL_1 (5)
EricLew	0:80ee8f3b695e	3995	* @arg @ref LL_ADC_CHANNEL_2 (5)
EricLew	0:80ee8f3b695e	3996	* @arg @ref LL_ADC_CHANNEL_3 (5)
EricLew	0:80ee8f3b695e	3997	* @arg @ref LL_ADC_CHANNEL_4 (5)
EricLew	0:80ee8f3b695e	3998	* @arg @ref LL_ADC_CHANNEL_5 (5)
EricLew	0:80ee8f3b695e	3999	* @arg @ref LL_ADC_CHANNEL_6
EricLew	0:80ee8f3b695e	4000	* @arg @ref LL_ADC_CHANNEL_7
EricLew	0:80ee8f3b695e	4001	* @arg @ref LL_ADC_CHANNEL_8
EricLew	0:80ee8f3b695e	4002	* @arg @ref LL_ADC_CHANNEL_9
EricLew	0:80ee8f3b695e	4003	* @arg @ref LL_ADC_CHANNEL_10
EricLew	0:80ee8f3b695e	4004	* @arg @ref LL_ADC_CHANNEL_11
EricLew	0:80ee8f3b695e	4005	* @arg @ref LL_ADC_CHANNEL_12
EricLew	0:80ee8f3b695e	4006	* @arg @ref LL_ADC_CHANNEL_13
EricLew	0:80ee8f3b695e	4007	* @arg @ref LL_ADC_CHANNEL_14
EricLew	0:80ee8f3b695e	4008	* @arg @ref LL_ADC_CHANNEL_15
EricLew	0:80ee8f3b695e	4009	* @arg @ref LL_ADC_CHANNEL_16
EricLew	0:80ee8f3b695e	4010	* @arg @ref LL_ADC_CHANNEL_17
EricLew	0:80ee8f3b695e	4011	* @arg @ref LL_ADC_CHANNEL_18
EricLew	0:80ee8f3b695e	4012	* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
EricLew	0:80ee8f3b695e	4013	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
EricLew	0:80ee8f3b695e	4014	* @arg @ref LL_ADC_CHANNEL_VBAT (4)
EricLew	0:80ee8f3b695e	4015	* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
EricLew	0:80ee8f3b695e	4016	* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
EricLew	0:80ee8f3b695e	4017	* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)
EricLew	0:80ee8f3b695e	4018	* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)
EricLew	0:80ee8f3b695e	4019	* (1) On STM32L4, parameter available only on ADC instance: ADC1.
EricLew	0:80ee8f3b695e	4020	* (2) On STM32L4, parameter available only on ADC instance: ADC2.
EricLew	0:80ee8f3b695e	4021	* (3) On STM32L4, parameter available only on ADC instance: ADC3.
EricLew	0:80ee8f3b695e	4022	* (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.
EricLew	0:80ee8f3b695e	4023	* (5) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
EricLew	0:80ee8f3b695e	4024	* Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
EricLew	0:80ee8f3b695e	4025	* @retval Returned value can be one of the following values:
EricLew	0:80ee8f3b695e	4026	* @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5
EricLew	0:80ee8f3b695e	4027	* @arg @ref LL_ADC_SAMPLINGTIME_6CYCLES_5
EricLew	0:80ee8f3b695e	4028	* @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5
EricLew	0:80ee8f3b695e	4029	* @arg @ref LL_ADC_SAMPLINGTIME_24CYCLES_5
EricLew	0:80ee8f3b695e	4030	* @arg @ref LL_ADC_SAMPLINGTIME_47CYCLES_5
EricLew	0:80ee8f3b695e	4031	* @arg @ref LL_ADC_SAMPLINGTIME_92CYCLES_5
EricLew	0:80ee8f3b695e	4032	* @arg @ref LL_ADC_SAMPLINGTIME_247CYCLES_5
EricLew	0:80ee8f3b695e	4033	* @arg @ref LL_ADC_SAMPLINGTIME_640CYCLES_5
EricLew	0:80ee8f3b695e	4034	*/
EricLew	0:80ee8f3b695e	4035	__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel)
EricLew	0:80ee8f3b695e	4036	{
EricLew	0:80ee8f3b695e	4037	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
EricLew	0:80ee8f3b695e	4038
EricLew	0:80ee8f3b695e	4039	return (uint32_t)(READ_BIT(*preg,
EricLew	0:80ee8f3b695e	4040	ADC_SMPR1_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK))
EricLew	0:80ee8f3b695e	4041	>> __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)
EricLew	0:80ee8f3b695e	4042	);
EricLew	0:80ee8f3b695e	4043	}
EricLew	0:80ee8f3b695e	4044
EricLew	0:80ee8f3b695e	4045	/**
EricLew	0:80ee8f3b695e	4046	* @brief Set mode single-ended or differential input of the selected
EricLew	0:80ee8f3b695e	4047	* ADC channel.
EricLew	0:80ee8f3b695e	4048	* Channel ending is on channel scope: independently of channel mapped
EricLew	0:80ee8f3b695e	4049	* on ADC group regular or injected.
EricLew	0:80ee8f3b695e	4050	* In differential mode: Differential measurement is carried out
EricLew	0:80ee8f3b695e	4051	* between the selected channel 'i' (positive input) and
EricLew	0:80ee8f3b695e	4052	* channel 'i+1' (negative input). Only channel 'i' has to be
EricLew	0:80ee8f3b695e	4053	* configured, channel 'i+1' is configured automatically.
EricLew	0:80ee8f3b695e	4054	* @note Refer to Reference Manual to ensure the selected channel is available
EricLew	0:80ee8f3b695e	4055	* in differential mode.
EricLew	0:80ee8f3b695e	4056	* For example, internal channels (VrefInt, TempSensor, ...) are
EricLew	0:80ee8f3b695e	4057	* not available in differential mode.
EricLew	0:80ee8f3b695e	4058	* @note When configuring a channel 'i' in differential mode,
EricLew	0:80ee8f3b695e	4059	* the channel 'i+1' is not usable separately.
EricLew	0:80ee8f3b695e	4060	* @note On STM32L4, channels 15, 16, 17, 18 of ADC1, ADC2, ADC3 (if available)
EricLew	0:80ee8f3b695e	4061	* are internally fixed to single-ended inputs configuration.
EricLew	0:80ee8f3b695e	4062	* @note On this STM32 family, setting of this feature is conditioned to
EricLew	0:80ee8f3b695e	4063	* ADC state:
EricLew	0:80ee8f3b695e	4064	* ADC must be ADC disabled.
EricLew	0:80ee8f3b695e	4065	* @note One or several values can be selected.
EricLew	0:80ee8f3b695e	4066	* Example: (LL_ADC_CHANNEL_4 \| LL_ADC_CHANNEL_12 \| ...)
EricLew	0:80ee8f3b695e	4067	* @rmtoll DIFSEL DIFSEL LL_ADC_GetChannelSamplingTime
EricLew	0:80ee8f3b695e	4068	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	4069	* @param Channel This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	4070	* @arg @ref LL_ADC_CHANNEL_1
EricLew	0:80ee8f3b695e	4071	* @arg @ref LL_ADC_CHANNEL_2
EricLew	0:80ee8f3b695e	4072	* @arg @ref LL_ADC_CHANNEL_3
EricLew	0:80ee8f3b695e	4073	* @arg @ref LL_ADC_CHANNEL_4
EricLew	0:80ee8f3b695e	4074	* @arg @ref LL_ADC_CHANNEL_5
EricLew	0:80ee8f3b695e	4075	* @arg @ref LL_ADC_CHANNEL_6
EricLew	0:80ee8f3b695e	4076	* @arg @ref LL_ADC_CHANNEL_7
EricLew	0:80ee8f3b695e	4077	* @arg @ref LL_ADC_CHANNEL_8
EricLew	0:80ee8f3b695e	4078	* @arg @ref LL_ADC_CHANNEL_9
EricLew	0:80ee8f3b695e	4079	* @arg @ref LL_ADC_CHANNEL_10
EricLew	0:80ee8f3b695e	4080	* @arg @ref LL_ADC_CHANNEL_11
EricLew	0:80ee8f3b695e	4081	* @arg @ref LL_ADC_CHANNEL_12
EricLew	0:80ee8f3b695e	4082	* @arg @ref LL_ADC_CHANNEL_13
EricLew	0:80ee8f3b695e	4083	* @arg @ref LL_ADC_CHANNEL_14
EricLew	0:80ee8f3b695e	4084	* @param SingleDiff This parameter can be a combination of the following values:
EricLew	0:80ee8f3b695e	4085	* @arg @ref LL_ADC_SINGLE_ENDED
EricLew	0:80ee8f3b695e	4086	* @arg @ref LL_ADC_DIFFERENTIAL_ENDED
EricLew	0:80ee8f3b695e	4087	* @retval None
EricLew	0:80ee8f3b695e	4088	*/
EricLew	0:80ee8f3b695e	4089	__STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff)
EricLew	0:80ee8f3b695e	4090	{
EricLew	0:80ee8f3b695e	4091	/* Bits of channels in single or differential mode are set only for */
EricLew	0:80ee8f3b695e	4092	/* differential mode (for single mode, mask of bits allowed to be set is */
EricLew	0:80ee8f3b695e	4093	/* shifted out of range of bits of channels in single or differential mode. */
EricLew	0:80ee8f3b695e	4094	MODIFY_REG(ADCx->DIFSEL,
EricLew	0:80ee8f3b695e	4095	Channel & ADC_SINGLEDIFF_CHANNEL_MASK,
EricLew	0:80ee8f3b695e	4096	(Channel & ADC_SINGLEDIFF_CHANNEL_MASK) & (ADC_DIFSEL_DIFSEL << (SingleDiff & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK)));
EricLew	0:80ee8f3b695e	4097	}
EricLew	0:80ee8f3b695e	4098
EricLew	0:80ee8f3b695e	4099	/**
EricLew	0:80ee8f3b695e	4100	* @brief Get mode single-ended or differential input of the selected
EricLew	0:80ee8f3b695e	4101	* ADC channel.
EricLew	0:80ee8f3b695e	4102	* @note When configuring a channel 'i' in differential mode,
EricLew	0:80ee8f3b695e	4103	* the channel 'i+1' is not usable separately.
EricLew	0:80ee8f3b695e	4104	* Therefore, to ensure a channel is configured in single-ended mode,
EricLew	0:80ee8f3b695e	4105	* the configuration of channel itself and the channel 'i-1' must be
EricLew	0:80ee8f3b695e	4106	* read back (to ensure that the selected channel channel has not been
EricLew	0:80ee8f3b695e	4107	* configured in differential mode by the previous channel).
EricLew	0:80ee8f3b695e	4108	* @note Refer to Reference Manual to ensure the selected channel is available
EricLew	0:80ee8f3b695e	4109	* in differential mode.
EricLew	0:80ee8f3b695e	4110	* For example, internal channels (VrefInt, TempSensor, ...) are
EricLew	0:80ee8f3b695e	4111	* not available in differential mode.
EricLew	0:80ee8f3b695e	4112	* @note When configuring a channel 'i' in differential mode,
EricLew	0:80ee8f3b695e	4113	* the channel 'i+1' is not usable separately.
EricLew	0:80ee8f3b695e	4114	* @note On STM32L4, channels 15, 16, 17, 18 of ADC1, ADC2, ADC3 (if available)
EricLew	0:80ee8f3b695e	4115	* are internally fixed to single-ended inputs configuration.
EricLew	0:80ee8f3b695e	4116	* @note One or several values can be selected. In this case, the value
EricLew	0:80ee8f3b695e	4117	* returned is null if all channels are in single ended-mode.
EricLew	0:80ee8f3b695e	4118	* Example: (LL_ADC_CHANNEL_4 \| LL_ADC_CHANNEL_12 \| ...)
EricLew	0:80ee8f3b695e	4119	* @rmtoll DIFSEL DIFSEL LL_ADC_GetChannelSamplingTime
EricLew	0:80ee8f3b695e	4120	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	4121	* @param Channel This parameter can be a combination of the following values:
EricLew	0:80ee8f3b695e	4122	* @arg @ref LL_ADC_CHANNEL_0
EricLew	0:80ee8f3b695e	4123	* @arg @ref LL_ADC_CHANNEL_1
EricLew	0:80ee8f3b695e	4124	* @arg @ref LL_ADC_CHANNEL_2
EricLew	0:80ee8f3b695e	4125	* @arg @ref LL_ADC_CHANNEL_3
EricLew	0:80ee8f3b695e	4126	* @arg @ref LL_ADC_CHANNEL_4
EricLew	0:80ee8f3b695e	4127	* @arg @ref LL_ADC_CHANNEL_5
EricLew	0:80ee8f3b695e	4128	* @arg @ref LL_ADC_CHANNEL_6
EricLew	0:80ee8f3b695e	4129	* @arg @ref LL_ADC_CHANNEL_7
EricLew	0:80ee8f3b695e	4130	* @arg @ref LL_ADC_CHANNEL_8
EricLew	0:80ee8f3b695e	4131	* @arg @ref LL_ADC_CHANNEL_9
EricLew	0:80ee8f3b695e	4132	* @arg @ref LL_ADC_CHANNEL_10
EricLew	0:80ee8f3b695e	4133	* @arg @ref LL_ADC_CHANNEL_11
EricLew	0:80ee8f3b695e	4134	* @arg @ref LL_ADC_CHANNEL_12
EricLew	0:80ee8f3b695e	4135	* @arg @ref LL_ADC_CHANNEL_13
EricLew	0:80ee8f3b695e	4136	* @arg @ref LL_ADC_CHANNEL_14
EricLew	0:80ee8f3b695e	4137	* @retval 0: channel in single-ended mode, else: channel in differential mode
EricLew	0:80ee8f3b695e	4138	*/
EricLew	0:80ee8f3b695e	4139	__STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel)
EricLew	0:80ee8f3b695e	4140	{
EricLew	0:80ee8f3b695e	4141	return (uint32_t)(READ_BIT(ADCx->DIFSEL, (Channel & ADC_SINGLEDIFF_CHANNEL_MASK)));
EricLew	0:80ee8f3b695e	4142	}
EricLew	0:80ee8f3b695e	4143
EricLew	0:80ee8f3b695e	4144	/**
EricLew	0:80ee8f3b695e	4145	* @}
EricLew	0:80ee8f3b695e	4146	*/
EricLew	0:80ee8f3b695e	4147
EricLew	0:80ee8f3b695e	4148	/** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog
EricLew	0:80ee8f3b695e	4149	* @{
EricLew	0:80ee8f3b695e	4150	*/
EricLew	0:80ee8f3b695e	4151
EricLew	0:80ee8f3b695e	4152	/**
EricLew	0:80ee8f3b695e	4153	* @brief Set ADC analog watchdog monitored channels:
EricLew	0:80ee8f3b695e	4154	* a single channel, multiple channels or all channels,
EricLew	0:80ee8f3b695e	4155	* on ADC groups regular and-or injected.
EricLew	0:80ee8f3b695e	4156	* @note Once monitored channels are selected, analog watchdog
EricLew	0:80ee8f3b695e	4157	* is enabled.
EricLew	0:80ee8f3b695e	4158	* @note In case of need to define a single channel to monitor
EricLew	0:80ee8f3b695e	4159	* with analog watchdog from sequencer channel definition,
EricLew	0:80ee8f3b695e	4160	* use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
EricLew	0:80ee8f3b695e	4161	* @note On this STM32 family, there are 2 kinds of analog watchdog
EricLew	0:80ee8f3b695e	4162	* instance:
EricLew	0:80ee8f3b695e	4163	* - AWD standard (instance AWD1):
EricLew	0:80ee8f3b695e	4164	* - channels monitored: can monitor 1 channel or all channels.
EricLew	0:80ee8f3b695e	4165	* - groups monitored: ADC groups regular and-or injected.
EricLew	0:80ee8f3b695e	4166	* - resolution: resolution is not limited (corresponds to
EricLew	0:80ee8f3b695e	4167	* ADC resolution configured).
EricLew	0:80ee8f3b695e	4168	* - AWD flexible (instances AWD2, AWD3):
EricLew	0:80ee8f3b695e	4169	* - channels monitored: flexible on channels monitored, selection is
EricLew	0:80ee8f3b695e	4170	* channel wise, from from 1 to all channels.
EricLew	0:80ee8f3b695e	4171	* Specificity of this analog watchdog: Multiple channels can
EricLew	0:80ee8f3b695e	4172	* be selected. For example:
EricLew	0:80ee8f3b695e	4173	* (LL_ADC_AWD_CHANNEL4_REG_INJ \| LL_ADC_AWD_CHANNEL5_REG_INJ \| ...)
EricLew	0:80ee8f3b695e	4174	* - groups monitored: not selection possible (monitoring on both
EricLew	0:80ee8f3b695e	4175	* groups regular and injected).
EricLew	0:80ee8f3b695e	4176	* Channels selected are monitored on regular and injected groups:
EricLew	0:80ee8f3b695e	4177	* LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
EricLew	0:80ee8f3b695e	4178	* LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
EricLew	0:80ee8f3b695e	4179	* - resolution: resolution is limited to 8 bits: if ADC resolution is
EricLew	0:80ee8f3b695e	4180	* 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
EricLew	0:80ee8f3b695e	4181	* the 2 LSB are ignored.
EricLew	0:80ee8f3b695e	4182	* @note On this STM32 family, setting of this feature is conditioned to
EricLew	0:80ee8f3b695e	4183	* ADC state:
EricLew	0:80ee8f3b695e	4184	* ADC must be disabled or enabled without conversion on going
EricLew	0:80ee8f3b695e	4185	* on either groups regular or injected.
EricLew	0:80ee8f3b695e	4186	* @rmtoll CFGR AWD1CH LL_ADC_SetAnalogWDMonitChannels\n
EricLew	0:80ee8f3b695e	4187	* CFGR AWD1SGL LL_ADC_SetAnalogWDMonitChannels\n
EricLew	0:80ee8f3b695e	4188	* CFGR AWD1EN LL_ADC_SetAnalogWDMonitChannels\n
EricLew	0:80ee8f3b695e	4189	* CFGR JAWD1EN LL_ADC_SetAnalogWDMonitChannels\n
EricLew	0:80ee8f3b695e	4190	* AWD2CR AWD2CH LL_ADC_SetAnalogWDMonitChannels\n
EricLew	0:80ee8f3b695e	4191	* AWD3CR AWD3CH LL_ADC_SetAnalogWDMonitChannels
EricLew	0:80ee8f3b695e	4192	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	4193	* @param AWDy This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	4194	* @arg @ref LL_ADC_AWD1
EricLew	0:80ee8f3b695e	4195	* @arg @ref LL_ADC_AWD2
EricLew	0:80ee8f3b695e	4196	* @arg @ref LL_ADC_AWD3
EricLew	0:80ee8f3b695e	4197	* @param AWDChannelGroup This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	4198	* @arg @ref LL_ADC_AWD_DISABLE
EricLew	0:80ee8f3b695e	4199	* @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
EricLew	0:80ee8f3b695e	4200	* @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
EricLew	0:80ee8f3b695e	4201	* @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
EricLew	0:80ee8f3b695e	4202	* @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
EricLew	0:80ee8f3b695e	4203	* @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
EricLew	0:80ee8f3b695e	4204	* @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
EricLew	0:80ee8f3b695e	4205	* @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
EricLew	0:80ee8f3b695e	4206	* @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
EricLew	0:80ee8f3b695e	4207	* @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
EricLew	0:80ee8f3b695e	4208	* @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
EricLew	0:80ee8f3b695e	4209	* @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
EricLew	0:80ee8f3b695e	4210	* @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
EricLew	0:80ee8f3b695e	4211	* @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
EricLew	0:80ee8f3b695e	4212	* @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
EricLew	0:80ee8f3b695e	4213	* @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
EricLew	0:80ee8f3b695e	4214	* @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
EricLew	0:80ee8f3b695e	4215	* @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
EricLew	0:80ee8f3b695e	4216	* @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
EricLew	0:80ee8f3b695e	4217	* @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
EricLew	0:80ee8f3b695e	4218	* @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
EricLew	0:80ee8f3b695e	4219	* @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
EricLew	0:80ee8f3b695e	4220	* @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
EricLew	0:80ee8f3b695e	4221	* @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
EricLew	0:80ee8f3b695e	4222	* @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
EricLew	0:80ee8f3b695e	4223	* @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
EricLew	0:80ee8f3b695e	4224	* @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
EricLew	0:80ee8f3b695e	4225	* @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
EricLew	0:80ee8f3b695e	4226	* @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
EricLew	0:80ee8f3b695e	4227	* @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
EricLew	0:80ee8f3b695e	4228	* @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
EricLew	0:80ee8f3b695e	4229	* @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
EricLew	0:80ee8f3b695e	4230	* @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
EricLew	0:80ee8f3b695e	4231	* @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
EricLew	0:80ee8f3b695e	4232	* @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
EricLew	0:80ee8f3b695e	4233	* @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
EricLew	0:80ee8f3b695e	4234	* @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
EricLew	0:80ee8f3b695e	4235	* @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
EricLew	0:80ee8f3b695e	4236	* @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
EricLew	0:80ee8f3b695e	4237	* @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
EricLew	0:80ee8f3b695e	4238	* @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
EricLew	0:80ee8f3b695e	4239	* @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
EricLew	0:80ee8f3b695e	4240	* @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
EricLew	0:80ee8f3b695e	4241	* @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
EricLew	0:80ee8f3b695e	4242	* @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
EricLew	0:80ee8f3b695e	4243	* @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
EricLew	0:80ee8f3b695e	4244	* @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
EricLew	0:80ee8f3b695e	4245	* @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
EricLew	0:80ee8f3b695e	4246	* @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
EricLew	0:80ee8f3b695e	4247	* @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
EricLew	0:80ee8f3b695e	4248	* @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
EricLew	0:80ee8f3b695e	4249	* @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
EricLew	0:80ee8f3b695e	4250	* @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
EricLew	0:80ee8f3b695e	4251	* @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
EricLew	0:80ee8f3b695e	4252	* @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
EricLew	0:80ee8f3b695e	4253	* @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
EricLew	0:80ee8f3b695e	4254	* @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
EricLew	0:80ee8f3b695e	4255	* @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
EricLew	0:80ee8f3b695e	4256	* @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
EricLew	0:80ee8f3b695e	4257	* @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
EricLew	0:80ee8f3b695e	4258	* @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
EricLew	0:80ee8f3b695e	4259	* @arg @ref LL_ADC_AWD_CH_VREFINT_REG (0)(1)
EricLew	0:80ee8f3b695e	4260	* @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (0)(1)
EricLew	0:80ee8f3b695e	4261	* @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
EricLew	0:80ee8f3b695e	4262	* @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (0)(4)
EricLew	0:80ee8f3b695e	4263	* @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (4)(4)
EricLew	0:80ee8f3b695e	4264	* @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (4)
EricLew	0:80ee8f3b695e	4265	* @arg @ref LL_ADC_AWD_CH_VBAT_REG (0)(4)
EricLew	0:80ee8f3b695e	4266	* @arg @ref LL_ADC_AWD_CH_VBAT_INJ (0)(4)
EricLew	0:80ee8f3b695e	4267	* @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (4)
EricLew	0:80ee8f3b695e	4268	* @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG (0)(2)
EricLew	0:80ee8f3b695e	4269	* @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ (0)(2)
EricLew	0:80ee8f3b695e	4270	* @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ (2)
EricLew	0:80ee8f3b695e	4271	* @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG (0)(2)
EricLew	0:80ee8f3b695e	4272	* @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ (0)(2)
EricLew	0:80ee8f3b695e	4273	* @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ (2)
EricLew	0:80ee8f3b695e	4274	* @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC3_REG (0)(3)
EricLew	0:80ee8f3b695e	4275	* @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC3_INJ (0)(3)
EricLew	0:80ee8f3b695e	4276	* @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC3_REG_INJ (3)
EricLew	0:80ee8f3b695e	4277	* @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC3_REG (0)(3)
EricLew	0:80ee8f3b695e	4278	* @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC3_INJ (0)(3)
EricLew	0:80ee8f3b695e	4279	* @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC3_REG_INJ (3)
EricLew	0:80ee8f3b695e	4280	* (0) On STM32L4, parameter available only on analog watchdog number: AWD1.
EricLew	0:80ee8f3b695e	4281	* (1) On STM32L4, parameter available only on ADC instance: ADC1.
EricLew	0:80ee8f3b695e	4282	* (2) On STM32L4, parameter available only on ADC instance: ADC2.
EricLew	0:80ee8f3b695e	4283	* (3) On STM32L4, parameter available only on ADC instance: ADC3.
EricLew	0:80ee8f3b695e	4284	* (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.
EricLew	0:80ee8f3b695e	4285	* @retval None
EricLew	0:80ee8f3b695e	4286	*/
EricLew	0:80ee8f3b695e	4287	__STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup)
EricLew	0:80ee8f3b695e	4288	{
EricLew	0:80ee8f3b695e	4289	/* Set bits with content of parameter "AWDChannelGroup" with bits position */
EricLew	0:80ee8f3b695e	4290	/* in register and register position depending on parameter "AWDy". */
EricLew	0:80ee8f3b695e	4291	/* Parameters "AWDChannelGroup" and "AWDy" are used with masks because */
EricLew	0:80ee8f3b695e	4292	/* containing other bits reserved for other purpose. */
EricLew	0:80ee8f3b695e	4293	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, __ADC_MASK_SHIFT(AWDy, ADC_AWD_CRX_REGOFFSET_MASK)
EricLew	0:80ee8f3b695e	4294	+ ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));
EricLew	0:80ee8f3b695e	4295
EricLew	0:80ee8f3b695e	4296	MODIFY_REG(*preg,
EricLew	0:80ee8f3b695e	4297	(AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK),
EricLew	0:80ee8f3b695e	4298	AWDChannelGroup & AWDy);
EricLew	0:80ee8f3b695e	4299	}
EricLew	0:80ee8f3b695e	4300
EricLew	0:80ee8f3b695e	4301	/**
EricLew	0:80ee8f3b695e	4302	* @brief Get ADC analog watchdog monitored channel.
EricLew	0:80ee8f3b695e	4303	* @note Usage of the returned channel number:
EricLew	0:80ee8f3b695e	4304	* - To reinject this channel into another function LL_ADC_xxx:
EricLew	0:80ee8f3b695e	4305	* the returned channel number is only partly formatted on definition
EricLew	0:80ee8f3b695e	4306	* of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
EricLew	0:80ee8f3b695e	4307	* with literals LL_ADC_CHANNEL_x, then the selected
EricLew	0:80ee8f3b695e	4308	* literal LL_ADC_CHANNEL_x can be used as parameter for another
EricLew	0:80ee8f3b695e	4309	* function.
EricLew	0:80ee8f3b695e	4310	* - To get the channel number in decimal format:
EricLew	0:80ee8f3b695e	4311	* process the returned value with the helper macro
EricLew	0:80ee8f3b695e	4312	* @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
EricLew	0:80ee8f3b695e	4313	* Applicable only when the analog watchdog is set to monitor
EricLew	0:80ee8f3b695e	4314	* one channel.
EricLew	0:80ee8f3b695e	4315	* @note On this STM32 family, there are 2 kinds of analog watchdog
EricLew	0:80ee8f3b695e	4316	* instance:
EricLew	0:80ee8f3b695e	4317	* - AWD standard (instance AWD1):
EricLew	0:80ee8f3b695e	4318	* - channels monitored: can monitor 1 channel or all channels.
EricLew	0:80ee8f3b695e	4319	* - groups monitored: ADC groups regular and-or injected.
EricLew	0:80ee8f3b695e	4320	* - resolution: resolution is not limited (corresponds to
EricLew	0:80ee8f3b695e	4321	* ADC resolution configured).
EricLew	0:80ee8f3b695e	4322	* - AWD flexible (instances AWD2, AWD3):
EricLew	0:80ee8f3b695e	4323	* - channels monitored: flexible on channels monitored, selection is
EricLew	0:80ee8f3b695e	4324	* channel wise, from from 1 to all channels.
EricLew	0:80ee8f3b695e	4325	* Specificity of this analog watchdog: Multiple channels can
EricLew	0:80ee8f3b695e	4326	* be selected. For example:
EricLew	0:80ee8f3b695e	4327	* (LL_ADC_AWD_CHANNEL4_REG_INJ \| LL_ADC_AWD_CHANNEL5_REG_INJ \| ...)
EricLew	0:80ee8f3b695e	4328	* - groups monitored: not selection possible (monitoring on both
EricLew	0:80ee8f3b695e	4329	* groups regular and injected).
EricLew	0:80ee8f3b695e	4330	* Channels selected are monitored on regular and injected groups:
EricLew	0:80ee8f3b695e	4331	* LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
EricLew	0:80ee8f3b695e	4332	* LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
EricLew	0:80ee8f3b695e	4333	* - resolution: resolution is limited to 8 bits: if ADC resolution is
EricLew	0:80ee8f3b695e	4334	* 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
EricLew	0:80ee8f3b695e	4335	* the 2 LSB are ignored.
EricLew	0:80ee8f3b695e	4336	* @note On this STM32 family, setting of this feature is conditioned to
EricLew	0:80ee8f3b695e	4337	* ADC state:
EricLew	0:80ee8f3b695e	4338	* ADC must be disabled or enabled without conversion on going
EricLew	0:80ee8f3b695e	4339	* on either groups regular or injected.
EricLew	0:80ee8f3b695e	4340	* @rmtoll CFGR AWD1CH LL_ADC_GetAnalogWDMonitChannels\n
EricLew	0:80ee8f3b695e	4341	* CFGR AWD1SGL LL_ADC_GetAnalogWDMonitChannels\n
EricLew	0:80ee8f3b695e	4342	* CFGR AWD1EN LL_ADC_GetAnalogWDMonitChannels\n
EricLew	0:80ee8f3b695e	4343	* CFGR JAWD1EN LL_ADC_GetAnalogWDMonitChannels\n
EricLew	0:80ee8f3b695e	4344	* AWD2CR AWD2CH LL_ADC_GetAnalogWDMonitChannels\n
EricLew	0:80ee8f3b695e	4345	* AWD3CR AWD3CH LL_ADC_GetAnalogWDMonitChannels
EricLew	0:80ee8f3b695e	4346	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	4347	* @param AWDy This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	4348	* @arg @ref LL_ADC_AWD1
EricLew	0:80ee8f3b695e	4349	* @arg @ref LL_ADC_AWD2
EricLew	0:80ee8f3b695e	4350	* @arg @ref LL_ADC_AWD3
EricLew	0:80ee8f3b695e	4351	* @retval Returned value can be one of the following values:
EricLew	0:80ee8f3b695e	4352	* @arg @ref LL_ADC_AWD_DISABLE
EricLew	0:80ee8f3b695e	4353	* @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
EricLew	0:80ee8f3b695e	4354	* @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
EricLew	0:80ee8f3b695e	4355	* @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
EricLew	0:80ee8f3b695e	4356	* @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
EricLew	0:80ee8f3b695e	4357	* @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
EricLew	0:80ee8f3b695e	4358	* @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
EricLew	0:80ee8f3b695e	4359	* @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
EricLew	0:80ee8f3b695e	4360	* @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
EricLew	0:80ee8f3b695e	4361	* @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
EricLew	0:80ee8f3b695e	4362	* @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
EricLew	0:80ee8f3b695e	4363	* @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
EricLew	0:80ee8f3b695e	4364	* @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
EricLew	0:80ee8f3b695e	4365	* @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
EricLew	0:80ee8f3b695e	4366	* @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
EricLew	0:80ee8f3b695e	4367	* @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
EricLew	0:80ee8f3b695e	4368	* @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
EricLew	0:80ee8f3b695e	4369	* @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
EricLew	0:80ee8f3b695e	4370	* @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
EricLew	0:80ee8f3b695e	4371	* @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
EricLew	0:80ee8f3b695e	4372	* @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
EricLew	0:80ee8f3b695e	4373	* @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
EricLew	0:80ee8f3b695e	4374	* @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
EricLew	0:80ee8f3b695e	4375	* @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
EricLew	0:80ee8f3b695e	4376	* @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
EricLew	0:80ee8f3b695e	4377	* @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
EricLew	0:80ee8f3b695e	4378	* @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
EricLew	0:80ee8f3b695e	4379	* @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
EricLew	0:80ee8f3b695e	4380	* @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
EricLew	0:80ee8f3b695e	4381	* @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
EricLew	0:80ee8f3b695e	4382	* @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
EricLew	0:80ee8f3b695e	4383	* @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
EricLew	0:80ee8f3b695e	4384	* @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
EricLew	0:80ee8f3b695e	4385	* @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
EricLew	0:80ee8f3b695e	4386	* @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
EricLew	0:80ee8f3b695e	4387	* @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
EricLew	0:80ee8f3b695e	4388	* @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
EricLew	0:80ee8f3b695e	4389	* @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
EricLew	0:80ee8f3b695e	4390	* @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
EricLew	0:80ee8f3b695e	4391	* @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
EricLew	0:80ee8f3b695e	4392	* @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
EricLew	0:80ee8f3b695e	4393	* @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
EricLew	0:80ee8f3b695e	4394	* @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
EricLew	0:80ee8f3b695e	4395	* @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
EricLew	0:80ee8f3b695e	4396	* @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
EricLew	0:80ee8f3b695e	4397	* @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
EricLew	0:80ee8f3b695e	4398	* @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
EricLew	0:80ee8f3b695e	4399	* @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
EricLew	0:80ee8f3b695e	4400	* @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
EricLew	0:80ee8f3b695e	4401	* @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
EricLew	0:80ee8f3b695e	4402	* @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
EricLew	0:80ee8f3b695e	4403	* @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
EricLew	0:80ee8f3b695e	4404	* @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
EricLew	0:80ee8f3b695e	4405	* @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
EricLew	0:80ee8f3b695e	4406	* @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
EricLew	0:80ee8f3b695e	4407	* @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
EricLew	0:80ee8f3b695e	4408	* @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
EricLew	0:80ee8f3b695e	4409	* @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
EricLew	0:80ee8f3b695e	4410	* @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
EricLew	0:80ee8f3b695e	4411	* @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
EricLew	0:80ee8f3b695e	4412	* @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
EricLew	0:80ee8f3b695e	4413	* @arg @ref LL_ADC_AWD_CH_VREFINT_REG (0)(1)
EricLew	0:80ee8f3b695e	4414	* @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (0)(1)
EricLew	0:80ee8f3b695e	4415	* @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
EricLew	0:80ee8f3b695e	4416	* @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (0)(4)
EricLew	0:80ee8f3b695e	4417	* @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (4)(4)
EricLew	0:80ee8f3b695e	4418	* @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (4)
EricLew	0:80ee8f3b695e	4419	* @arg @ref LL_ADC_AWD_CH_VBAT_REG (0)(4)
EricLew	0:80ee8f3b695e	4420	* @arg @ref LL_ADC_AWD_CH_VBAT_INJ (0)(4)
EricLew	0:80ee8f3b695e	4421	* @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (4)
EricLew	0:80ee8f3b695e	4422	* @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG (0)(2)
EricLew	0:80ee8f3b695e	4423	* @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ (0)(2)
EricLew	0:80ee8f3b695e	4424	* @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ (2)
EricLew	0:80ee8f3b695e	4425	* @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG (0)(2)
EricLew	0:80ee8f3b695e	4426	* @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ (0)(2)
EricLew	0:80ee8f3b695e	4427	* @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ (2)
EricLew	0:80ee8f3b695e	4428	* @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC3_REG (0)(3)
EricLew	0:80ee8f3b695e	4429	* @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC3_INJ (0)(3)
EricLew	0:80ee8f3b695e	4430	* @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC3_REG_INJ (3)
EricLew	0:80ee8f3b695e	4431	* @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC3_REG (0)(3)
EricLew	0:80ee8f3b695e	4432	* @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC3_INJ (0)(3)
EricLew	0:80ee8f3b695e	4433	* @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC3_REG_INJ (3)
EricLew	0:80ee8f3b695e	4434	* (0) On STM32L4, parameter available only on analog watchdog number: AWD1.
EricLew	0:80ee8f3b695e	4435	* (1) On STM32L4, parameter available only on ADC instance: ADC1.
EricLew	0:80ee8f3b695e	4436	* (2) On STM32L4, parameter available only on ADC instance: ADC2.
EricLew	0:80ee8f3b695e	4437	* (3) On STM32L4, parameter available only on ADC instance: ADC3.
EricLew	0:80ee8f3b695e	4438	* (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.
EricLew	0:80ee8f3b695e	4439	*/
EricLew	0:80ee8f3b695e	4440	__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy)
EricLew	0:80ee8f3b695e	4441	{
EricLew	0:80ee8f3b695e	4442	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, __ADC_MASK_SHIFT(AWDy, ADC_AWD_CRX_REGOFFSET_MASK)
EricLew	0:80ee8f3b695e	4443	+ ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));
EricLew	0:80ee8f3b695e	4444
EricLew	0:80ee8f3b695e	4445	return (uint32_t)(READ_BIT(*preg,
EricLew	0:80ee8f3b695e	4446	AWDy)
EricLew	0:80ee8f3b695e	4447	);
EricLew	0:80ee8f3b695e	4448	}
EricLew	0:80ee8f3b695e	4449
EricLew	0:80ee8f3b695e	4450	/**
EricLew	0:80ee8f3b695e	4451	* @brief Set ADC analog watchdog thresholds value of both thresholds
EricLew	0:80ee8f3b695e	4452	* high and low.
EricLew	0:80ee8f3b695e	4453	* @note If value of only one threshold high or low must be set,
EricLew	0:80ee8f3b695e	4454	* use function @ref LL_ADC_SetAnalogWDThresholds().
EricLew	0:80ee8f3b695e	4455	* @note On this STM32 family, there are 2 kinds of analog watchdog
EricLew	0:80ee8f3b695e	4456	* instance:
EricLew	0:80ee8f3b695e	4457	* - AWD standard (instance AWD1):
EricLew	0:80ee8f3b695e	4458	* - channels monitored: can monitor 1 channel or all channels.
EricLew	0:80ee8f3b695e	4459	* - groups monitored: ADC groups regular and-or injected.
EricLew	0:80ee8f3b695e	4460	* - resolution: resolution is not limited (corresponds to
EricLew	0:80ee8f3b695e	4461	* ADC resolution configured).
EricLew	0:80ee8f3b695e	4462	* - AWD flexible (instances AWD2, AWD3):
EricLew	0:80ee8f3b695e	4463	* - channels monitored: flexible on channels monitored, selection is
EricLew	0:80ee8f3b695e	4464	* channel wise, from from 1 to all channels.
EricLew	0:80ee8f3b695e	4465	* Specificity of this analog watchdog: Multiple channels can
EricLew	0:80ee8f3b695e	4466	* be selected. For example:
EricLew	0:80ee8f3b695e	4467	* (LL_ADC_AWD_CHANNEL4_REG_INJ \| LL_ADC_AWD_CHANNEL5_REG_INJ \| ...)
EricLew	0:80ee8f3b695e	4468	* - groups monitored: not selection possible (monitoring on both
EricLew	0:80ee8f3b695e	4469	* groups regular and injected).
EricLew	0:80ee8f3b695e	4470	* Channels selected are monitored on regular and injected groups:
EricLew	0:80ee8f3b695e	4471	* LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
EricLew	0:80ee8f3b695e	4472	* LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
EricLew	0:80ee8f3b695e	4473	* - resolution: resolution is limited to 8 bits: if ADC resolution is
EricLew	0:80ee8f3b695e	4474	* 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
EricLew	0:80ee8f3b695e	4475	* the 2 LSB are ignored.
EricLew	0:80ee8f3b695e	4476	* @note On this STM32 family, setting of this feature is conditioned to
EricLew	0:80ee8f3b695e	4477	* ADC state:
EricLew	0:80ee8f3b695e	4478	* ADC must be disabled or enabled without conversion on going
EricLew	0:80ee8f3b695e	4479	* on either groups regular or injected.
EricLew	0:80ee8f3b695e	4480	* @rmtoll TR1 HT1 LL_ADC_ConfigAnalogWDThresholds\n
EricLew	0:80ee8f3b695e	4481	* TR2 HT2 LL_ADC_ConfigAnalogWDThresholds\n
EricLew	0:80ee8f3b695e	4482	* TR3 HT3 LL_ADC_ConfigAnalogWDThresholds\n
EricLew	0:80ee8f3b695e	4483	* TR1 LT1 LL_ADC_ConfigAnalogWDThresholds\n
EricLew	0:80ee8f3b695e	4484	* TR2 LT2 LL_ADC_ConfigAnalogWDThresholds\n
EricLew	0:80ee8f3b695e	4485	* TR3 LT3 LL_ADC_ConfigAnalogWDThresholds
EricLew	0:80ee8f3b695e	4486	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	4487	* @param AWDy This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	4488	* @arg @ref LL_ADC_AWD1
EricLew	0:80ee8f3b695e	4489	* @arg @ref LL_ADC_AWD2
EricLew	0:80ee8f3b695e	4490	* @arg @ref LL_ADC_AWD3
EricLew	0:80ee8f3b695e	4491	* @param AWDThresholdHighValue For AWD1: 0x000...0xFFF, for AWD2, AWD3: 0x00...0xFF
EricLew	0:80ee8f3b695e	4492	* @param AWDThresholdLowValue For AWD1: 0x000...0xFFF, for AWD2, AWD3: 0x00...0xFF
EricLew	0:80ee8f3b695e	4493	* @retval None
EricLew	0:80ee8f3b695e	4494	*/
EricLew	0:80ee8f3b695e	4495	__STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef* ADCx, uint32_t AWDy, uint32_t AWDThresholdHighValue, uint32_t AWDThresholdLowValue)
EricLew	0:80ee8f3b695e	4496	{
EricLew	0:80ee8f3b695e	4497	/* Set bits with content of parameter "AWDThresholdxxxValue" with bits */
EricLew	0:80ee8f3b695e	4498	/* position in register and register position depending on parameter */
EricLew	0:80ee8f3b695e	4499	/* "AWDy". */
EricLew	0:80ee8f3b695e	4500	/* Parameters "AWDy" and "AWDThresholdxxxValue" are used with masks because */
EricLew	0:80ee8f3b695e	4501	/* containing other bits reserved for other purpose. */
EricLew	0:80ee8f3b695e	4502	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, __ADC_MASK_SHIFT(AWDy, ADC_AWD_TRX_REGOFFSET_MASK));
EricLew	0:80ee8f3b695e	4503
EricLew	0:80ee8f3b695e	4504	MODIFY_REG(*preg,
EricLew	0:80ee8f3b695e	4505	ADC_TR1_HT1 \| ADC_TR1_LT1,
EricLew	0:80ee8f3b695e	4506	(AWDThresholdHighValue << ADC_TR1_HT1_BITOFFSET_POS) \| AWDThresholdLowValue);
EricLew	0:80ee8f3b695e	4507	}
EricLew	0:80ee8f3b695e	4508
EricLew	0:80ee8f3b695e	4509	/**
EricLew	0:80ee8f3b695e	4510	* @brief Set ADC analog watchdog threshold value of threshold
EricLew	0:80ee8f3b695e	4511	* high or low.
EricLew	0:80ee8f3b695e	4512	* @note If values of both thresholds high or low must be set,
EricLew	0:80ee8f3b695e	4513	* use function @ref LL_ADC_ConfigAnalogWDThresholds().
EricLew	0:80ee8f3b695e	4514	* @note On this STM32 family, there are 2 kinds of analog watchdog
EricLew	0:80ee8f3b695e	4515	* instance:
EricLew	0:80ee8f3b695e	4516	* - AWD standard (instance AWD1):
EricLew	0:80ee8f3b695e	4517	* - channels monitored: can monitor 1 channel or all channels.
EricLew	0:80ee8f3b695e	4518	* - groups monitored: ADC groups regular and-or injected.
EricLew	0:80ee8f3b695e	4519	* - resolution: resolution is not limited (corresponds to
EricLew	0:80ee8f3b695e	4520	* ADC resolution configured).
EricLew	0:80ee8f3b695e	4521	* - AWD flexible (instances AWD2, AWD3):
EricLew	0:80ee8f3b695e	4522	* - channels monitored: flexible on channels monitored, selection is
EricLew	0:80ee8f3b695e	4523	* channel wise, from from 1 to all channels.
EricLew	0:80ee8f3b695e	4524	* Specificity of this analog watchdog: Multiple channels can
EricLew	0:80ee8f3b695e	4525	* be selected. For example:
EricLew	0:80ee8f3b695e	4526	* (LL_ADC_AWD_CHANNEL4_REG_INJ \| LL_ADC_AWD_CHANNEL5_REG_INJ \| ...)
EricLew	0:80ee8f3b695e	4527	* - groups monitored: not selection possible (monitoring on both
EricLew	0:80ee8f3b695e	4528	* groups regular and injected).
EricLew	0:80ee8f3b695e	4529	* Channels selected are monitored on regular and injected groups:
EricLew	0:80ee8f3b695e	4530	* LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
EricLew	0:80ee8f3b695e	4531	* LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
EricLew	0:80ee8f3b695e	4532	* - resolution: resolution is limited to 8 bits: if ADC resolution is
EricLew	0:80ee8f3b695e	4533	* 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
EricLew	0:80ee8f3b695e	4534	* the 2 LSB are ignored.
EricLew	0:80ee8f3b695e	4535	* @note On this STM32 family, setting of this feature is conditioned to
EricLew	0:80ee8f3b695e	4536	* ADC state:
EricLew	0:80ee8f3b695e	4537	* ADC must be disabled or enabled without conversion on going
EricLew	0:80ee8f3b695e	4538	* on either groups regular or injected.
EricLew	0:80ee8f3b695e	4539	* @rmtoll TR1 HT1 LL_ADC_SetAnalogWDThresholds\n
EricLew	0:80ee8f3b695e	4540	* TR2 HT2 LL_ADC_SetAnalogWDThresholds\n
EricLew	0:80ee8f3b695e	4541	* TR3 HT3 LL_ADC_SetAnalogWDThresholds\n
EricLew	0:80ee8f3b695e	4542	* TR1 LT1 LL_ADC_SetAnalogWDThresholds\n
EricLew	0:80ee8f3b695e	4543	* TR2 LT2 LL_ADC_SetAnalogWDThresholds\n
EricLew	0:80ee8f3b695e	4544	* TR3 LT3 LL_ADC_SetAnalogWDThresholds
EricLew	0:80ee8f3b695e	4545	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	4546	* @param AWDy This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	4547	* @arg @ref LL_ADC_AWD1
EricLew	0:80ee8f3b695e	4548	* @arg @ref LL_ADC_AWD2
EricLew	0:80ee8f3b695e	4549	* @arg @ref LL_ADC_AWD3
EricLew	0:80ee8f3b695e	4550	* @param AWDThresholdsHighLow This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	4551	* @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
EricLew	0:80ee8f3b695e	4552	* @arg @ref LL_ADC_AWD_THRESHOLD_LOW
EricLew	0:80ee8f3b695e	4553	* @param AWDThresholdValue: For AWD1: 0x000...0xFFF, for AWD2, AWD3: 0x00...0xFF
EricLew	0:80ee8f3b695e	4554	* @retval None
EricLew	0:80ee8f3b695e	4555	*/
EricLew	0:80ee8f3b695e	4556	__STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef* ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)
EricLew	0:80ee8f3b695e	4557	{
EricLew	0:80ee8f3b695e	4558	/* Set bits with content of parameter "AWDThresholdValue" with bits */
EricLew	0:80ee8f3b695e	4559	/* position in register and register position depending on parameters */
EricLew	0:80ee8f3b695e	4560	/* "AWDThresholdsHighLow" and "AWDy". */
EricLew	0:80ee8f3b695e	4561	/* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */
EricLew	0:80ee8f3b695e	4562	/* containing other bits reserved for other purpose. */
EricLew	0:80ee8f3b695e	4563	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, __ADC_MASK_SHIFT(AWDy, ADC_AWD_TRX_REGOFFSET_MASK));
EricLew	0:80ee8f3b695e	4564
EricLew	0:80ee8f3b695e	4565	MODIFY_REG(*preg,
EricLew	0:80ee8f3b695e	4566	AWDThresholdsHighLow,
EricLew	0:80ee8f3b695e	4567	AWDThresholdValue << POSITION_VAL(AWDThresholdsHighLow));
EricLew	0:80ee8f3b695e	4568	}
EricLew	0:80ee8f3b695e	4569
EricLew	0:80ee8f3b695e	4570	/**
EricLew	0:80ee8f3b695e	4571	* @brief Get ADC analog watchdog threshold value of threshold high,
EricLew	0:80ee8f3b695e	4572	* threshold low or raw data with ADC thresholds high and low concatenated.
EricLew	0:80ee8f3b695e	4573	* @note If raw data with raw data with ADC thresholds high and low is retrieved,
EricLew	0:80ee8f3b695e	4574	* the data of each threshold high or low can still be isolated
EricLew	0:80ee8f3b695e	4575	* using helper macro:
EricLew	0:80ee8f3b695e	4576	* @ref __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW().
EricLew	0:80ee8f3b695e	4577	* @rmtoll TR1 HT1 LL_ADC_GetAnalogWDThresholds\n
EricLew	0:80ee8f3b695e	4578	* TR2 HT2 LL_ADC_GetAnalogWDThresholds\n
EricLew	0:80ee8f3b695e	4579	* TR3 HT3 LL_ADC_GetAnalogWDThresholds\n
EricLew	0:80ee8f3b695e	4580	* TR1 LT1 LL_ADC_GetAnalogWDThresholds\n
EricLew	0:80ee8f3b695e	4581	* TR2 LT2 LL_ADC_GetAnalogWDThresholds\n
EricLew	0:80ee8f3b695e	4582	* TR3 LT3 LL_ADC_GetAnalogWDThresholds
EricLew	0:80ee8f3b695e	4583	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	4584	* @param AWDy This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	4585	* @arg @ref LL_ADC_AWD1
EricLew	0:80ee8f3b695e	4586	* @arg @ref LL_ADC_AWD2
EricLew	0:80ee8f3b695e	4587	* @arg @ref LL_ADC_AWD3
EricLew	0:80ee8f3b695e	4588	* @param AWDThresholdsHighLow This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	4589	* @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
EricLew	0:80ee8f3b695e	4590	* @arg @ref LL_ADC_AWD_THRESHOLD_LOW
EricLew	0:80ee8f3b695e	4591	* @arg @ref LL_ADC_AWD_THRESHOLDS_HIGH_LOW
EricLew	0:80ee8f3b695e	4592	* @retval For AWD1: 0x000...0xFFF, for AWD2, AWD3: 0x00...0xFF
EricLew	0:80ee8f3b695e	4593	*/
EricLew	0:80ee8f3b695e	4594	__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow)
EricLew	0:80ee8f3b695e	4595	{
EricLew	0:80ee8f3b695e	4596	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, __ADC_MASK_SHIFT(AWDy, ADC_AWD_TRX_REGOFFSET_MASK));
EricLew	0:80ee8f3b695e	4597
EricLew	0:80ee8f3b695e	4598	return (uint32_t)(READ_BIT(*preg,
EricLew	0:80ee8f3b695e	4599	(AWDThresholdsHighLow \| ADC_TR1_LT1))
EricLew	0:80ee8f3b695e	4600	>> POSITION_VAL(AWDThresholdsHighLow)
EricLew	0:80ee8f3b695e	4601	);
EricLew	0:80ee8f3b695e	4602	}
EricLew	0:80ee8f3b695e	4603
EricLew	0:80ee8f3b695e	4604	/**
EricLew	0:80ee8f3b695e	4605	* @}
EricLew	0:80ee8f3b695e	4606	*/
EricLew	0:80ee8f3b695e	4607
EricLew	0:80ee8f3b695e	4608	/** @defgroup ADC_LL_EF_Configuration_ADC_oversampling Configuration of ADC transversal scope: oversampling
EricLew	0:80ee8f3b695e	4609	* @{
EricLew	0:80ee8f3b695e	4610	*/
EricLew	0:80ee8f3b695e	4611
EricLew	0:80ee8f3b695e	4612	/**
EricLew	0:80ee8f3b695e	4613	* @brief Set ADC oversampling scope: ADC groups regular and-or injected
EricLew	0:80ee8f3b695e	4614	* (availability of ADC group injected depends on devices).
EricLew	0:80ee8f3b695e	4615	* If both groups regular and injected are selected,
EricLew	0:80ee8f3b695e	4616	* specify behaviour of ADC group injected interrupting
EricLew	0:80ee8f3b695e	4617	* group regular: when ADC group injected is triggered,
EricLew	0:80ee8f3b695e	4618	* the oversampling on ADC group regular is either
EricLew	0:80ee8f3b695e	4619	* temporary stopped and continued, or resumed from start
EricLew	0:80ee8f3b695e	4620	* (oversampler buffer reset).
EricLew	0:80ee8f3b695e	4621	* @note On this STM32 family, setting of this feature is conditioned to
EricLew	0:80ee8f3b695e	4622	* ADC state:
EricLew	0:80ee8f3b695e	4623	* ADC must be disabled or enabled without conversion on going
EricLew	0:80ee8f3b695e	4624	* on either groups regular or injected.
EricLew	0:80ee8f3b695e	4625	* @rmtoll CFGR2 ROVSE LL_ADC_SetOverSamplingScope\n
EricLew	0:80ee8f3b695e	4626	* CFGR2 JOVSE LL_ADC_SetOverSamplingScope\n
EricLew	0:80ee8f3b695e	4627	* CFGR2 ROVSM LL_ADC_SetOverSamplingScope
EricLew	0:80ee8f3b695e	4628	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	4629	* @param OvsScope This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	4630	* @arg @ref LL_ADC_OVS_DISABLE
EricLew	0:80ee8f3b695e	4631	* @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
EricLew	0:80ee8f3b695e	4632	* @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED
EricLew	0:80ee8f3b695e	4633	* @arg @ref LL_ADC_OVS_GRP_INJECTED
EricLew	0:80ee8f3b695e	4634	* @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED
EricLew	0:80ee8f3b695e	4635	* @retval None
EricLew	0:80ee8f3b695e	4636	*/
EricLew	0:80ee8f3b695e	4637	__STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx, uint32_t OvsScope)
EricLew	0:80ee8f3b695e	4638	{
EricLew	0:80ee8f3b695e	4639	MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_ROVSE \| ADC_CFGR2_JOVSE \| ADC_CFGR2_ROVSM, OvsScope);
EricLew	0:80ee8f3b695e	4640	}
EricLew	0:80ee8f3b695e	4641
EricLew	0:80ee8f3b695e	4642	/**
EricLew	0:80ee8f3b695e	4643	* @brief Get ADC oversampling scope: ADC groups regular and-or injected
EricLew	0:80ee8f3b695e	4644	* (availability of ADC group injected depends on devices).
EricLew	0:80ee8f3b695e	4645	* If both groups regular and injected are selected,
EricLew	0:80ee8f3b695e	4646	* specify behaviour of ADC group injected interrupting
EricLew	0:80ee8f3b695e	4647	* group regular: when ADC group injected is triggered,
EricLew	0:80ee8f3b695e	4648	* the oversampling on ADC group regular is either
EricLew	0:80ee8f3b695e	4649	* temporary stopped and continued, or resumed from start
EricLew	0:80ee8f3b695e	4650	* (oversampler buffer reset).
EricLew	0:80ee8f3b695e	4651	* @rmtoll CFGR2 ROVSE LL_ADC_GetOverSamplingScope\n
EricLew	0:80ee8f3b695e	4652	* CFGR2 JOVSE LL_ADC_GetOverSamplingScope\n
EricLew	0:80ee8f3b695e	4653	* CFGR2 ROVSM LL_ADC_GetOverSamplingScope
EricLew	0:80ee8f3b695e	4654	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	4655	* @retval Returned value can be one of the following values:
EricLew	0:80ee8f3b695e	4656	* @arg @ref LL_ADC_OVS_DISABLE
EricLew	0:80ee8f3b695e	4657	* @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
EricLew	0:80ee8f3b695e	4658	* @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED
EricLew	0:80ee8f3b695e	4659	* @arg @ref LL_ADC_OVS_GRP_INJECTED
EricLew	0:80ee8f3b695e	4660	* @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED
EricLew	0:80ee8f3b695e	4661	*/
EricLew	0:80ee8f3b695e	4662	__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	4663	{
EricLew	0:80ee8f3b695e	4664	return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_ROVSE \| ADC_CFGR2_JOVSE \| ADC_CFGR2_ROVSM));
EricLew	0:80ee8f3b695e	4665	}
EricLew	0:80ee8f3b695e	4666
EricLew	0:80ee8f3b695e	4667	/**
EricLew	0:80ee8f3b695e	4668	* @brief Set ADC oversampling discontinuous mode (triggered mode)
EricLew	0:80ee8f3b695e	4669	* on the selected ADC group: number of oversampled conversions
EricLew	0:80ee8f3b695e	4670	* are done either in:
EricLew	0:80ee8f3b695e	4671	* * continuous mode (all conversions of oversampling ratio
EricLew	0:80ee8f3b695e	4672	* are done from 1 trigger)
EricLew	0:80ee8f3b695e	4673	* * discontinuous mode (each conversion of oversampling ratio
EricLew	0:80ee8f3b695e	4674	* needs a trigger).
EricLew	0:80ee8f3b695e	4675	* @note On this STM32 family, setting of this feature is conditioned to
EricLew	0:80ee8f3b695e	4676	* ADC state:
EricLew	0:80ee8f3b695e	4677	* ADC must be disabled or enabled without conversion on going
EricLew	0:80ee8f3b695e	4678	* on group regular.
EricLew	0:80ee8f3b695e	4679	* @note On STM32L4, oversampling discontinuous mode (triggered mode)
EricLew	0:80ee8f3b695e	4680	* can be used only when oversampling is set on group regular only
EricLew	0:80ee8f3b695e	4681	* and in resumed mode.
EricLew	0:80ee8f3b695e	4682	* @rmtoll CFGR2 TROVS LL_ADC_SetOverSamplingDiscont
EricLew	0:80ee8f3b695e	4683	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	4684	* @param OverSamplingDiscont This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	4685	* @arg @ref LL_ADC_OVS_REG_CONT
EricLew	0:80ee8f3b695e	4686	* @arg @ref LL_ADC_OVS_REG_DISCONT
EricLew	0:80ee8f3b695e	4687	* @retval None
EricLew	0:80ee8f3b695e	4688	*/
EricLew	0:80ee8f3b695e	4689	__STATIC_INLINE void LL_ADC_SetOverSamplingDiscont(ADC_TypeDef *ADCx, uint32_t OverSamplingDiscont)
EricLew	0:80ee8f3b695e	4690	{
EricLew	0:80ee8f3b695e	4691	MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TROVS, OverSamplingDiscont);
EricLew	0:80ee8f3b695e	4692	}
EricLew	0:80ee8f3b695e	4693
EricLew	0:80ee8f3b695e	4694	/**
EricLew	0:80ee8f3b695e	4695	* @brief Get ADC oversampling discontinuous mode (triggered mode)
EricLew	0:80ee8f3b695e	4696	* on the selected ADC group: number of oversampled conversions
EricLew	0:80ee8f3b695e	4697	* are done either in:
EricLew	0:80ee8f3b695e	4698	* * continuous mode (all conversions of oversampling ratio
EricLew	0:80ee8f3b695e	4699	* are done from 1 trigger)
EricLew	0:80ee8f3b695e	4700	* * discontinuous mode (each conversion of oversampling ratio
EricLew	0:80ee8f3b695e	4701	* needs a trigger).
EricLew	0:80ee8f3b695e	4702	* @rmtoll CFGR2 TROVS LL_ADC_GetOverSamplingDiscont
EricLew	0:80ee8f3b695e	4703	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	4704	* @retval Returned value can be one of the following values:
EricLew	0:80ee8f3b695e	4705	* @arg @ref LL_ADC_OVS_REG_CONT
EricLew	0:80ee8f3b695e	4706	* @arg @ref LL_ADC_OVS_REG_DISCONT
EricLew	0:80ee8f3b695e	4707	*/
EricLew	0:80ee8f3b695e	4708	__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	4709	{
EricLew	0:80ee8f3b695e	4710	return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TROVS));
EricLew	0:80ee8f3b695e	4711	}
EricLew	0:80ee8f3b695e	4712
EricLew	0:80ee8f3b695e	4713	/**
EricLew	0:80ee8f3b695e	4714	* @brief Set ADC oversampling (impacting both ADC groups regular and injected)
EricLew	0:80ee8f3b695e	4715	* parameters:
EricLew	0:80ee8f3b695e	4716	* * ratio
EricLew	0:80ee8f3b695e	4717	* * shift
EricLew	0:80ee8f3b695e	4718	* @note On this STM32 family, setting of this feature is conditioned to
EricLew	0:80ee8f3b695e	4719	* ADC state:
EricLew	0:80ee8f3b695e	4720	* ADC must be disabled or enabled without conversion on going
EricLew	0:80ee8f3b695e	4721	* on either groups regular or injected.
EricLew	0:80ee8f3b695e	4722	* @rmtoll CFGR2 OVSS LL_ADC_ConfigOverSamplingRatioShift\n
EricLew	0:80ee8f3b695e	4723	* CFGR2 OVSR LL_ADC_ConfigOverSamplingRatioShift
EricLew	0:80ee8f3b695e	4724	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	4725	* @param Ratio This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	4726	* @arg @ref LL_ADC_OVS_RATIO_2
EricLew	0:80ee8f3b695e	4727	* @arg @ref LL_ADC_OVS_RATIO_4
EricLew	0:80ee8f3b695e	4728	* @arg @ref LL_ADC_OVS_RATIO_8
EricLew	0:80ee8f3b695e	4729	* @arg @ref LL_ADC_OVS_RATIO_16
EricLew	0:80ee8f3b695e	4730	* @arg @ref LL_ADC_OVS_RATIO_32
EricLew	0:80ee8f3b695e	4731	* @arg @ref LL_ADC_OVS_RATIO_64
EricLew	0:80ee8f3b695e	4732	* @arg @ref LL_ADC_OVS_RATIO_128
EricLew	0:80ee8f3b695e	4733	* @arg @ref LL_ADC_OVS_RATIO_256
EricLew	0:80ee8f3b695e	4734	* @param Shift This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	4735	* @arg @ref LL_ADC_OVS_DATA_SHIFT_NONE
EricLew	0:80ee8f3b695e	4736	* @arg @ref LL_ADC_OVS_DATA_SHIFT_1
EricLew	0:80ee8f3b695e	4737	* @arg @ref LL_ADC_OVS_DATA_SHIFT_2
EricLew	0:80ee8f3b695e	4738	* @arg @ref LL_ADC_OVS_DATA_SHIFT_3
EricLew	0:80ee8f3b695e	4739	* @arg @ref LL_ADC_OVS_DATA_SHIFT_4
EricLew	0:80ee8f3b695e	4740	* @arg @ref LL_ADC_OVS_DATA_SHIFT_5
EricLew	0:80ee8f3b695e	4741	* @arg @ref LL_ADC_OVS_DATA_SHIFT_6
EricLew	0:80ee8f3b695e	4742	* @arg @ref LL_ADC_OVS_DATA_SHIFT_7
EricLew	0:80ee8f3b695e	4743	* @arg @ref LL_ADC_OVS_DATA_SHIFT_8
EricLew	0:80ee8f3b695e	4744	* @retval None
EricLew	0:80ee8f3b695e	4745	*/
EricLew	0:80ee8f3b695e	4746	__STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint32_t Ratio, uint32_t Shift)
EricLew	0:80ee8f3b695e	4747	{
EricLew	0:80ee8f3b695e	4748	MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS \| ADC_CFGR2_OVSR), (Shift \| Ratio));
EricLew	0:80ee8f3b695e	4749	}
EricLew	0:80ee8f3b695e	4750
EricLew	0:80ee8f3b695e	4751	/**
EricLew	0:80ee8f3b695e	4752	* @brief Get ADC oversampling (impacting both ADC groups regular and injected)
EricLew	0:80ee8f3b695e	4753	* parameters:
EricLew	0:80ee8f3b695e	4754	* * ratio
EricLew	0:80ee8f3b695e	4755	* @rmtoll CFGR2 OVSR LL_ADC_GetOverSamplingRatio
EricLew	0:80ee8f3b695e	4756	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	4757	* @retval Ratio This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	4758	* @arg @ref LL_ADC_OVS_RATIO_2
EricLew	0:80ee8f3b695e	4759	* @arg @ref LL_ADC_OVS_RATIO_4
EricLew	0:80ee8f3b695e	4760	* @arg @ref LL_ADC_OVS_RATIO_8
EricLew	0:80ee8f3b695e	4761	* @arg @ref LL_ADC_OVS_RATIO_16
EricLew	0:80ee8f3b695e	4762	* @arg @ref LL_ADC_OVS_RATIO_32
EricLew	0:80ee8f3b695e	4763	* @arg @ref LL_ADC_OVS_RATIO_64
EricLew	0:80ee8f3b695e	4764	* @arg @ref LL_ADC_OVS_RATIO_128
EricLew	0:80ee8f3b695e	4765	* @arg @ref LL_ADC_OVS_RATIO_256
EricLew	0:80ee8f3b695e	4766	*/
EricLew	0:80ee8f3b695e	4767	__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	4768	{
EricLew	0:80ee8f3b695e	4769	return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR));
EricLew	0:80ee8f3b695e	4770	}
EricLew	0:80ee8f3b695e	4771
EricLew	0:80ee8f3b695e	4772	/**
EricLew	0:80ee8f3b695e	4773	* @brief Get ADC oversampling (impacting both ADC groups regular and injected)
EricLew	0:80ee8f3b695e	4774	* parameters:
EricLew	0:80ee8f3b695e	4775	* * shift
EricLew	0:80ee8f3b695e	4776	* @rmtoll CFGR2 OVSS LL_ADC_GetOverSamplingShift
EricLew	0:80ee8f3b695e	4777	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	4778	* @retval Shift This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	4779	* @arg @ref LL_ADC_OVS_DATA_SHIFT_NONE
EricLew	0:80ee8f3b695e	4780	* @arg @ref LL_ADC_OVS_DATA_SHIFT_1
EricLew	0:80ee8f3b695e	4781	* @arg @ref LL_ADC_OVS_DATA_SHIFT_2
EricLew	0:80ee8f3b695e	4782	* @arg @ref LL_ADC_OVS_DATA_SHIFT_3
EricLew	0:80ee8f3b695e	4783	* @arg @ref LL_ADC_OVS_DATA_SHIFT_4
EricLew	0:80ee8f3b695e	4784	* @arg @ref LL_ADC_OVS_DATA_SHIFT_5
EricLew	0:80ee8f3b695e	4785	* @arg @ref LL_ADC_OVS_DATA_SHIFT_6
EricLew	0:80ee8f3b695e	4786	* @arg @ref LL_ADC_OVS_DATA_SHIFT_7
EricLew	0:80ee8f3b695e	4787	* @arg @ref LL_ADC_OVS_DATA_SHIFT_8
EricLew	0:80ee8f3b695e	4788	*/
EricLew	0:80ee8f3b695e	4789	__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	4790	{
EricLew	0:80ee8f3b695e	4791	return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSS));
EricLew	0:80ee8f3b695e	4792	}
EricLew	0:80ee8f3b695e	4793
EricLew	0:80ee8f3b695e	4794	/**
EricLew	0:80ee8f3b695e	4795	* @}
EricLew	0:80ee8f3b695e	4796	*/
EricLew	0:80ee8f3b695e	4797
EricLew	0:80ee8f3b695e	4798	/** @defgroup ADC_LL_EF_Configuration_ADC_Multimode Configuration of ADC hierarchical scope: multimode
EricLew	0:80ee8f3b695e	4799	* @{
EricLew	0:80ee8f3b695e	4800	*/
EricLew	0:80ee8f3b695e	4801
EricLew	0:80ee8f3b695e	4802	#if defined(ADC2)
EricLew	0:80ee8f3b695e	4803	/**
EricLew	0:80ee8f3b695e	4804	* @brief Set ADC multimode configuration to operate in independent mode
EricLew	0:80ee8f3b695e	4805	* or multimode (for devices with several ADC instances).
EricLew	0:80ee8f3b695e	4806	* If multimode configuration: the selected ADC instance is
EricLew	0:80ee8f3b695e	4807	* either master or slave depending on hardware.
EricLew	0:80ee8f3b695e	4808	* Refer to reference manual.
EricLew	0:80ee8f3b695e	4809	* @note On this STM32 family, setting of this feature is conditioned to
EricLew	0:80ee8f3b695e	4810	* ADC state:
EricLew	0:80ee8f3b695e	4811	* All ADC instances of the ADC common group must be disabled.
EricLew	0:80ee8f3b695e	4812	* This check can be done with function @ref LL_ADC_IsEnabled() for each
EricLew	0:80ee8f3b695e	4813	* ADC instance or by using helper macro
EricLew	0:80ee8f3b695e	4814	* @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
EricLew	0:80ee8f3b695e	4815	* @rmtoll CCR DUAL LL_ADC_SetMultimode
EricLew	0:80ee8f3b695e	4816	* @param ADCxy_COMMON ADC common instance
EricLew	0:80ee8f3b695e	4817	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
EricLew	0:80ee8f3b695e	4818	* @param Multimode This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	4819	* @arg @ref LL_ADC_MULTI_INDEPENDENT
EricLew	0:80ee8f3b695e	4820	* @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
EricLew	0:80ee8f3b695e	4821	* @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
EricLew	0:80ee8f3b695e	4822	* @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
EricLew	0:80ee8f3b695e	4823	* @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
EricLew	0:80ee8f3b695e	4824	* @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
EricLew	0:80ee8f3b695e	4825	* @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
EricLew	0:80ee8f3b695e	4826	* @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
EricLew	0:80ee8f3b695e	4827	* @retval None
EricLew	0:80ee8f3b695e	4828	*/
EricLew	0:80ee8f3b695e	4829	__STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode)
EricLew	0:80ee8f3b695e	4830	{
EricLew	0:80ee8f3b695e	4831	MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DUAL, Multimode);
EricLew	0:80ee8f3b695e	4832	}
EricLew	0:80ee8f3b695e	4833
EricLew	0:80ee8f3b695e	4834	/**
EricLew	0:80ee8f3b695e	4835	* @brief Get ADC multimode configuration to operate in independent mode
EricLew	0:80ee8f3b695e	4836	* or multimode (for devices with several ADC instances).
EricLew	0:80ee8f3b695e	4837	* If multimode configuration: the selected ADC instance is
EricLew	0:80ee8f3b695e	4838	* either master or slave depending on hardware.
EricLew	0:80ee8f3b695e	4839	* Refer to reference manual.
EricLew	0:80ee8f3b695e	4840	* @rmtoll CCR DUAL LL_ADC_GetMultimode
EricLew	0:80ee8f3b695e	4841	* @param ADCxy_COMMON ADC common instance
EricLew	0:80ee8f3b695e	4842	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
EricLew	0:80ee8f3b695e	4843	* @retval Returned value can be one of the following values:
EricLew	0:80ee8f3b695e	4844	* @arg @ref LL_ADC_MULTI_INDEPENDENT
EricLew	0:80ee8f3b695e	4845	* @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
EricLew	0:80ee8f3b695e	4846	* @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
EricLew	0:80ee8f3b695e	4847	* @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
EricLew	0:80ee8f3b695e	4848	* @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
EricLew	0:80ee8f3b695e	4849	* @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
EricLew	0:80ee8f3b695e	4850	* @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
EricLew	0:80ee8f3b695e	4851	* @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
EricLew	0:80ee8f3b695e	4852	*/
EricLew	0:80ee8f3b695e	4853	__STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON)
EricLew	0:80ee8f3b695e	4854	{
EricLew	0:80ee8f3b695e	4855	return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL));
EricLew	0:80ee8f3b695e	4856	}
EricLew	0:80ee8f3b695e	4857
EricLew	0:80ee8f3b695e	4858	/**
EricLew	0:80ee8f3b695e	4859	* @brief Set ADC multimode conversion data transfer: no transfer
EricLew	0:80ee8f3b695e	4860	* or transfer by DMA.
EricLew	0:80ee8f3b695e	4861	* If ADC multimode transfer by DMA is not selected:
EricLew	0:80ee8f3b695e	4862	* each ADC uses its own DMA channel, with its individual
EricLew	0:80ee8f3b695e	4863	* DMA transfer settings.
EricLew	0:80ee8f3b695e	4864	* If ADC multimode transfer by DMA is selected:
EricLew	0:80ee8f3b695e	4865	* One DMA channel is used for both ADC (DMA of ADC master)
EricLew	0:80ee8f3b695e	4866	* Specifies the DMA requests mode:
EricLew	0:80ee8f3b695e	4867	* * Limited mode (One shot mode): DMA transfer requests are stopped
EricLew	0:80ee8f3b695e	4868	* when number of DMA data transfers (number of
EricLew	0:80ee8f3b695e	4869	* ADC conversions) is reached.
EricLew	0:80ee8f3b695e	4870	* This ADC mode is intended to be used with DMA mode non-circular.
EricLew	0:80ee8f3b695e	4871	* * Unlimited mode: DMA transfer requests are unlimited,
EricLew	0:80ee8f3b695e	4872	* whatever number of DMA data transfers (number of
EricLew	0:80ee8f3b695e	4873	* ADC conversions).
EricLew	0:80ee8f3b695e	4874	* This ADC mode is intended to be used with DMA mode circular.
EricLew	0:80ee8f3b695e	4875	* @note If ADC DMA requests mode is set to unlimited and DMA is set to
EricLew	0:80ee8f3b695e	4876	* mode non-circular:
EricLew	0:80ee8f3b695e	4877	* when DMA transfers size will be reached, DMA will stop transfers of
EricLew	0:80ee8f3b695e	4878	* ADC conversions data ADC will raise an overrun error
EricLew	0:80ee8f3b695e	4879	* (overrun flag and interruption if enabled).
EricLew	0:80ee8f3b695e	4880	* @note How to retrieve multimode conversion data:
EricLew	0:80ee8f3b695e	4881	* Whatever multimode transfer by DMA setting: using function
EricLew	0:80ee8f3b695e	4882	* @ref LL_ADC_REG_ReadMultiConversionData32().
EricLew	0:80ee8f3b695e	4883	* If ADC multimode transfer by DMA is selected: conversion data
EricLew	0:80ee8f3b695e	4884	* is a raw data with ADC master and slave concatenated.
EricLew	0:80ee8f3b695e	4885	* A macro is available to get the conversion data of
EricLew	0:80ee8f3b695e	4886	* ADC master or ADC slave: see helper macro
EricLew	0:80ee8f3b695e	4887	* @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
EricLew	0:80ee8f3b695e	4888	* @note On this STM32 family, setting of this feature is conditioned to
EricLew	0:80ee8f3b695e	4889	* ADC state:
EricLew	0:80ee8f3b695e	4890	* All ADC instances of the ADC common group must be disabled
EricLew	0:80ee8f3b695e	4891	* or enabled without conversion on going on group regular.
EricLew	0:80ee8f3b695e	4892	* @rmtoll CCR MDMA LL_ADC_SetMultiDMATransfer\n
EricLew	0:80ee8f3b695e	4893	* CCR DMACFG LL_ADC_SetMultiDMATransfer
EricLew	0:80ee8f3b695e	4894	* @param ADCxy_COMMON ADC common instance
EricLew	0:80ee8f3b695e	4895	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
EricLew	0:80ee8f3b695e	4896	* @param DMATransfer This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	4897	* @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
EricLew	0:80ee8f3b695e	4898	* @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B
EricLew	0:80ee8f3b695e	4899	* @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B
EricLew	0:80ee8f3b695e	4900	* @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B
EricLew	0:80ee8f3b695e	4901	* @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B
EricLew	0:80ee8f3b695e	4902	* @retval None
EricLew	0:80ee8f3b695e	4903	*/
EricLew	0:80ee8f3b695e	4904	__STATIC_INLINE void LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t DMATransfer)
EricLew	0:80ee8f3b695e	4905	{
EricLew	0:80ee8f3b695e	4906	MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_MDMA \| ADC_CCR_DMACFG, DMATransfer);
EricLew	0:80ee8f3b695e	4907	}
EricLew	0:80ee8f3b695e	4908
EricLew	0:80ee8f3b695e	4909	/**
EricLew	0:80ee8f3b695e	4910	* @brief Get ADC multimode conversion data transfer: no transfer
EricLew	0:80ee8f3b695e	4911	* or transfer by DMA.
EricLew	0:80ee8f3b695e	4912	* If ADC multimode transfer by DMA is not selected:
EricLew	0:80ee8f3b695e	4913	* each ADC uses its own DMA channel, with its individual
EricLew	0:80ee8f3b695e	4914	* DMA transfer settings.
EricLew	0:80ee8f3b695e	4915	* If ADC multimode transfer by DMA is selected:
EricLew	0:80ee8f3b695e	4916	* One DMA channel is used for both ADC (DMA of ADC master)
EricLew	0:80ee8f3b695e	4917	* Specifies the DMA requests mode:
EricLew	0:80ee8f3b695e	4918	* * Limited mode (One shot mode): DMA transfer requests are stopped
EricLew	0:80ee8f3b695e	4919	* when number of DMA data transfers (number of
EricLew	0:80ee8f3b695e	4920	* ADC conversions) is reached.
EricLew	0:80ee8f3b695e	4921	* This ADC mode is intended to be used with DMA mode non-circular.
EricLew	0:80ee8f3b695e	4922	* * Unlimited mode: DMA transfer requests are unlimited,
EricLew	0:80ee8f3b695e	4923	* whatever number of DMA data transfers (number of
EricLew	0:80ee8f3b695e	4924	* ADC conversions).
EricLew	0:80ee8f3b695e	4925	* This ADC mode is intended to be used with DMA mode circular.
EricLew	0:80ee8f3b695e	4926	* @note If ADC DMA requests mode is set to unlimited and DMA is set to
EricLew	0:80ee8f3b695e	4927	* mode non-circular:
EricLew	0:80ee8f3b695e	4928	* when DMA transfers size will be reached, DMA will stop transfers of
EricLew	0:80ee8f3b695e	4929	* ADC conversions data ADC will raise an overrun error
EricLew	0:80ee8f3b695e	4930	* (overrun flag and interruption if enabled).
EricLew	0:80ee8f3b695e	4931	* @note How to retrieve multimode conversion data:
EricLew	0:80ee8f3b695e	4932	* Whatever multimode transfer by DMA setting: using function
EricLew	0:80ee8f3b695e	4933	* @ref LL_ADC_REG_ReadMultiConversionData32().
EricLew	0:80ee8f3b695e	4934	* If ADC multimode transfer by DMA is selected: conversion data
EricLew	0:80ee8f3b695e	4935	* is a raw data with ADC master and slave concatenated.
EricLew	0:80ee8f3b695e	4936	* A macro is available to get the conversion data of
EricLew	0:80ee8f3b695e	4937	* ADC master or ADC slave: see helper macro
EricLew	0:80ee8f3b695e	4938	* @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
EricLew	0:80ee8f3b695e	4939	* @rmtoll CCR MDMA LL_ADC_GetMultiDMATransfer\n
EricLew	0:80ee8f3b695e	4940	* CCR DMACFG LL_ADC_GetMultiDMATransfer
EricLew	0:80ee8f3b695e	4941	* @param ADCxy_COMMON ADC common instance
EricLew	0:80ee8f3b695e	4942	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
EricLew	0:80ee8f3b695e	4943	* @retval Returned value can be one of the following values:
EricLew	0:80ee8f3b695e	4944	* @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
EricLew	0:80ee8f3b695e	4945	* @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B
EricLew	0:80ee8f3b695e	4946	* @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B
EricLew	0:80ee8f3b695e	4947	* @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B
EricLew	0:80ee8f3b695e	4948	* @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B
EricLew	0:80ee8f3b695e	4949	*/
EricLew	0:80ee8f3b695e	4950	__STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON)
EricLew	0:80ee8f3b695e	4951	{
EricLew	0:80ee8f3b695e	4952	return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_MDMA \| ADC_CCR_DMACFG));
EricLew	0:80ee8f3b695e	4953	}
EricLew	0:80ee8f3b695e	4954
EricLew	0:80ee8f3b695e	4955	/**
EricLew	0:80ee8f3b695e	4956	* @brief Set ADC multimode delay between 2 sampling phases.
EricLew	0:80ee8f3b695e	4957	* @note The sampling delay range depends on ADC resolution:
EricLew	0:80ee8f3b695e	4958	* - ADC resolution 12 bits can have maximum delay of 12 cycles.
EricLew	0:80ee8f3b695e	4959	* - ADC resolution 10 bits can have maximum delay of 10 cycles.
EricLew	0:80ee8f3b695e	4960	* - ADC resolution 8 bits can have maximum delay of 8 cycles.
EricLew	0:80ee8f3b695e	4961	* - ADC resolution 6 bits can have maximum delay of 6 cycles.
EricLew	0:80ee8f3b695e	4962	* @note On this STM32 family, setting of this feature is conditioned to
EricLew	0:80ee8f3b695e	4963	* ADC state:
EricLew	0:80ee8f3b695e	4964	* All ADC instances of the ADC common group must be disabled.
EricLew	0:80ee8f3b695e	4965	* This check can be done with function @ref LL_ADC_IsEnabled() for each
EricLew	0:80ee8f3b695e	4966	* ADC instance or by using helper macro helper macro
EricLew	0:80ee8f3b695e	4967	* @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
EricLew	0:80ee8f3b695e	4968	* @rmtoll CCR DELAY LL_ADC_SetMultiTwoSamplingDelay
EricLew	0:80ee8f3b695e	4969	* @param ADCxy_COMMON ADC common instance
EricLew	0:80ee8f3b695e	4970	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
EricLew	0:80ee8f3b695e	4971	* @param TwoSamplingDelay This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	4972	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE
EricLew	0:80ee8f3b695e	4973	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES
EricLew	0:80ee8f3b695e	4974	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES
EricLew	0:80ee8f3b695e	4975	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES
EricLew	0:80ee8f3b695e	4976	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
EricLew	0:80ee8f3b695e	4977	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (1)
EricLew	0:80ee8f3b695e	4978	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES (1)
EricLew	0:80ee8f3b695e	4979	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES (2)
EricLew	0:80ee8f3b695e	4980	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (2)
EricLew	0:80ee8f3b695e	4981	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (2)
EricLew	0:80ee8f3b695e	4982	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (3)
EricLew	0:80ee8f3b695e	4983	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (3)
EricLew	0:80ee8f3b695e	4984	* (1) Parameter available only if ADC resolution is 12, 10 or 8 bits.
EricLew	0:80ee8f3b695e	4985	* (2) Parameter available only if ADC resolution is 12 or 10 bits.
EricLew	0:80ee8f3b695e	4986	* (3) Parameter available only if ADC resolution is 12 bits.
EricLew	0:80ee8f3b695e	4987	* @retval None
EricLew	0:80ee8f3b695e	4988	*/
EricLew	0:80ee8f3b695e	4989	__STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t TwoSamplingDelay)
EricLew	0:80ee8f3b695e	4990	{
EricLew	0:80ee8f3b695e	4991	MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DELAY, TwoSamplingDelay);
EricLew	0:80ee8f3b695e	4992	}
EricLew	0:80ee8f3b695e	4993
EricLew	0:80ee8f3b695e	4994	/**
EricLew	0:80ee8f3b695e	4995	* @brief Get ADC multimode delay between 2 sampling phases.
EricLew	0:80ee8f3b695e	4996	* @rmtoll CCR DELAY LL_ADC_GetMultiTwoSamplingDelay
EricLew	0:80ee8f3b695e	4997	* @param ADCxy_COMMON ADC common instance
EricLew	0:80ee8f3b695e	4998	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
EricLew	0:80ee8f3b695e	4999	* @retval Returned value can be one of the following values:
EricLew	0:80ee8f3b695e	5000	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE
EricLew	0:80ee8f3b695e	5001	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES
EricLew	0:80ee8f3b695e	5002	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES
EricLew	0:80ee8f3b695e	5003	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES
EricLew	0:80ee8f3b695e	5004	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
EricLew	0:80ee8f3b695e	5005	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (1)
EricLew	0:80ee8f3b695e	5006	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES (1)
EricLew	0:80ee8f3b695e	5007	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES (2)
EricLew	0:80ee8f3b695e	5008	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (2)
EricLew	0:80ee8f3b695e	5009	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (2)
EricLew	0:80ee8f3b695e	5010	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (3)
EricLew	0:80ee8f3b695e	5011	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (3)
EricLew	0:80ee8f3b695e	5012	* (1) Parameter available only if ADC resolution is 12, 10 or 8 bits.
EricLew	0:80ee8f3b695e	5013	* (2) Parameter available only if ADC resolution is 12 or 10 bits.
EricLew	0:80ee8f3b695e	5014	* (3) Parameter available only if ADC resolution is 12 bits.
EricLew	0:80ee8f3b695e	5015	*/
EricLew	0:80ee8f3b695e	5016	__STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON)
EricLew	0:80ee8f3b695e	5017	{
EricLew	0:80ee8f3b695e	5018	return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DELAY));
EricLew	0:80ee8f3b695e	5019	}
EricLew	0:80ee8f3b695e	5020	#endif /* ADC2 */
EricLew	0:80ee8f3b695e	5021
EricLew	0:80ee8f3b695e	5022	/**
EricLew	0:80ee8f3b695e	5023	* @}
EricLew	0:80ee8f3b695e	5024	*/
EricLew	0:80ee8f3b695e	5025
EricLew	0:80ee8f3b695e	5026	/** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance
EricLew	0:80ee8f3b695e	5027	* @{
EricLew	0:80ee8f3b695e	5028	*/
EricLew	0:80ee8f3b695e	5029
EricLew	0:80ee8f3b695e	5030	/**
EricLew	0:80ee8f3b695e	5031	* @brief Put ADC instance in deep power down state.
EricLew	0:80ee8f3b695e	5032	* @note In case of ADC calibration necessary: When ADC is in deep-power-down
EricLew	0:80ee8f3b695e	5033	* state, the internal analog calibration is lost. After exiting from
EricLew	0:80ee8f3b695e	5034	* deep power down, calibration must be relaunched or calibration factor
EricLew	0:80ee8f3b695e	5035	* (preliminarily saved) must be set back into calibration register.
EricLew	0:80ee8f3b695e	5036	* @note On this STM32 family, setting of this feature is conditioned to
EricLew	0:80ee8f3b695e	5037	* ADC state:
EricLew	0:80ee8f3b695e	5038	* ADC must be ADC disabled.
EricLew	0:80ee8f3b695e	5039	* @rmtoll CR DEEPPWD LL_ADC_EnableDeepPowerDown
EricLew	0:80ee8f3b695e	5040	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	5041	* @retval None
EricLew	0:80ee8f3b695e	5042	*/
EricLew	0:80ee8f3b695e	5043	__STATIC_INLINE void LL_ADC_EnableDeepPowerDown(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	5044	{
EricLew	0:80ee8f3b695e	5045	/* Note: Write register with some additional bits forced to state reset */
EricLew	0:80ee8f3b695e	5046	/* instead of modifying only the selected bit for this function, */
EricLew	0:80ee8f3b695e	5047	/* to not interfere with bits with HW property "rs". */
EricLew	0:80ee8f3b695e	5048	MODIFY_REG(ADCx->CR,
EricLew	0:80ee8f3b695e	5049	ADC_CR_BITS_PROPERTY_RS,
EricLew	0:80ee8f3b695e	5050	ADC_CR_DEEPPWD);
EricLew	0:80ee8f3b695e	5051	}
EricLew	0:80ee8f3b695e	5052
EricLew	0:80ee8f3b695e	5053	/**
EricLew	0:80ee8f3b695e	5054	* @brief Disable ADC deep power down mode.
EricLew	0:80ee8f3b695e	5055	* @note In case of ADC calibration necessary: When ADC is in deep-power-down
EricLew	0:80ee8f3b695e	5056	* state, the internal analog calibration is lost. After exiting from
EricLew	0:80ee8f3b695e	5057	* deep power down, calibration must be relaunched or calibration factor
EricLew	0:80ee8f3b695e	5058	* (preliminarily saved) must be set back into calibration register.
EricLew	0:80ee8f3b695e	5059	* @note On this STM32 family, setting of this feature is conditioned to
EricLew	0:80ee8f3b695e	5060	* ADC state:
EricLew	0:80ee8f3b695e	5061	* ADC must be ADC disabled.
EricLew	0:80ee8f3b695e	5062	* @rmtoll CR DEEPPWD LL_ADC_DisableDeepPowerDown
EricLew	0:80ee8f3b695e	5063	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	5064	* @retval None
EricLew	0:80ee8f3b695e	5065	*/
EricLew	0:80ee8f3b695e	5066	__STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	5067	{
EricLew	0:80ee8f3b695e	5068	/* Note: Write register with some additional bits forced to state reset */
EricLew	0:80ee8f3b695e	5069	/* instead of modifying only the selected bit for this function, */
EricLew	0:80ee8f3b695e	5070	/* to not interfere with bits with HW property "rs". */
EricLew	0:80ee8f3b695e	5071	CLEAR_BIT(ADCx->CR, (ADC_CR_DEEPPWD \| ADC_CR_BITS_PROPERTY_RS));
EricLew	0:80ee8f3b695e	5072	}
EricLew	0:80ee8f3b695e	5073
EricLew	0:80ee8f3b695e	5074	/**
EricLew	0:80ee8f3b695e	5075	* @brief Get the selected ADC instance deep power down state.
EricLew	0:80ee8f3b695e	5076	* (0: deep power down is disabled, 1: deep power down is enabled)
EricLew	0:80ee8f3b695e	5077	* @rmtoll CR DEEPPWD LL_ADC_IsDeepPowerDownEnabled
EricLew	0:80ee8f3b695e	5078	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	5079	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	5080	*/
EricLew	0:80ee8f3b695e	5081	__STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	5082	{
EricLew	0:80ee8f3b695e	5083	return (READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD));
EricLew	0:80ee8f3b695e	5084	}
EricLew	0:80ee8f3b695e	5085
EricLew	0:80ee8f3b695e	5086	/**
EricLew	0:80ee8f3b695e	5087	* @brief Enable ADC instance internal voltage regulator.
EricLew	0:80ee8f3b695e	5088	* @note On this STM32 family, after ADC internal voltage regulator enable,
EricLew	0:80ee8f3b695e	5089	* a delay for ADC internal voltage regulator stabilization
EricLew	0:80ee8f3b695e	5090	* is required before performing a ADC calibration or ADC enable.
EricLew	0:80ee8f3b695e	5091	* Refer to device datasheet, parameter tADCVREG_STUP.
EricLew	0:80ee8f3b695e	5092	* @note On this STM32 family, setting of this feature is conditioned to
EricLew	0:80ee8f3b695e	5093	* ADC state:
EricLew	0:80ee8f3b695e	5094	* ADC must be ADC disabled.
EricLew	0:80ee8f3b695e	5095	* @rmtoll CR ADVREGEN LL_ADC_EnableInternalRegulator
EricLew	0:80ee8f3b695e	5096	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	5097	* @retval None
EricLew	0:80ee8f3b695e	5098	*/
EricLew	0:80ee8f3b695e	5099	__STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	5100	{
EricLew	0:80ee8f3b695e	5101	/* Note: Write register with some additional bits forced to state reset */
EricLew	0:80ee8f3b695e	5102	/* instead of modifying only the selected bit for this function, */
EricLew	0:80ee8f3b695e	5103	/* to not interfere with bits with HW property "rs". */
EricLew	0:80ee8f3b695e	5104	MODIFY_REG(ADCx->CR,
EricLew	0:80ee8f3b695e	5105	ADC_CR_BITS_PROPERTY_RS,
EricLew	0:80ee8f3b695e	5106	ADC_CR_ADVREGEN);
EricLew	0:80ee8f3b695e	5107	}
EricLew	0:80ee8f3b695e	5108
EricLew	0:80ee8f3b695e	5109	/**
EricLew	0:80ee8f3b695e	5110	* @brief Disable ADC internal voltage regulator.
EricLew	0:80ee8f3b695e	5111	* @note On this STM32 family, setting of this feature is conditioned to
EricLew	0:80ee8f3b695e	5112	* ADC state:
EricLew	0:80ee8f3b695e	5113	* ADC must be ADC disabled.
EricLew	0:80ee8f3b695e	5114	* @rmtoll CR ADVREGEN LL_ADC_DisableInternalRegulator
EricLew	0:80ee8f3b695e	5115	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	5116	* @retval None
EricLew	0:80ee8f3b695e	5117	*/
EricLew	0:80ee8f3b695e	5118	__STATIC_INLINE void LL_ADC_DisableInternalRegulator(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	5119	{
EricLew	0:80ee8f3b695e	5120	CLEAR_BIT(ADCx->CR, (ADC_CR_ADVREGEN \| ADC_CR_BITS_PROPERTY_RS));
EricLew	0:80ee8f3b695e	5121	}
EricLew	0:80ee8f3b695e	5122
EricLew	0:80ee8f3b695e	5123	/**
EricLew	0:80ee8f3b695e	5124	* @brief Get the selected ADC instance internal voltage regulator state.
EricLew	0:80ee8f3b695e	5125	* (0: internal regulator is disabled, 1: internal regulator is
EricLew	0:80ee8f3b695e	5126	* enabled).
EricLew	0:80ee8f3b695e	5127	* @rmtoll CR ADVREGEN LL_ADC_IsInternalRegulatorEnabled
EricLew	0:80ee8f3b695e	5128	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	5129	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	5130	*/
EricLew	0:80ee8f3b695e	5131	__STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	5132	{
EricLew	0:80ee8f3b695e	5133	return (READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN));
EricLew	0:80ee8f3b695e	5134	}
EricLew	0:80ee8f3b695e	5135
EricLew	0:80ee8f3b695e	5136	/**
EricLew	0:80ee8f3b695e	5137	* @brief Enable the selected ADC instance.
EricLew	0:80ee8f3b695e	5138	* @note On this STM32 family, after ADC enable, a delay for
EricLew	0:80ee8f3b695e	5139	* ADC internal analog stabilization is required before performing a
EricLew	0:80ee8f3b695e	5140	* ADC conversion start.
EricLew	0:80ee8f3b695e	5141	* Refer to device datasheet, parameter tSTAB.
EricLew	0:80ee8f3b695e	5142	* @note On this STM32 family, flag LL_ADC_ISR_ADRDY is raised when the ADC
EricLew	0:80ee8f3b695e	5143	* is enabled and when conversion clock (not core clock) is active.
EricLew	0:80ee8f3b695e	5144	* @note On this STM32 family, setting of this feature is conditioned to
EricLew	0:80ee8f3b695e	5145	* ADC state:
EricLew	0:80ee8f3b695e	5146	* ADC must be ADC disabled and ADC internal voltage regulator enabled.
EricLew	0:80ee8f3b695e	5147	* @rmtoll CR ADEN LL_ADC_Enable
EricLew	0:80ee8f3b695e	5148	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	5149	* @retval None
EricLew	0:80ee8f3b695e	5150	*/
EricLew	0:80ee8f3b695e	5151	__STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	5152	{
EricLew	0:80ee8f3b695e	5153	/* Note: Write register with some additional bits forced to state reset */
EricLew	0:80ee8f3b695e	5154	/* instead of modifying only the selected bit for this function, */
EricLew	0:80ee8f3b695e	5155	/* to not interfere with bits with HW property "rs". */
EricLew	0:80ee8f3b695e	5156	MODIFY_REG(ADCx->CR,
EricLew	0:80ee8f3b695e	5157	ADC_CR_BITS_PROPERTY_RS,
EricLew	0:80ee8f3b695e	5158	ADC_CR_ADEN);
EricLew	0:80ee8f3b695e	5159	}
EricLew	0:80ee8f3b695e	5160
EricLew	0:80ee8f3b695e	5161	/**
EricLew	0:80ee8f3b695e	5162	* @brief Disable the selected ADC instance.
EricLew	0:80ee8f3b695e	5163	* @note On this STM32 family, setting of this feature is conditioned to
EricLew	0:80ee8f3b695e	5164	* ADC state:
EricLew	0:80ee8f3b695e	5165	* ADC must be not disabled. Must be enabled without conversion on going
EricLew	0:80ee8f3b695e	5166	* on either groups regular or injected.
EricLew	0:80ee8f3b695e	5167	* @rmtoll CR ADDIS LL_ADC_Disable
EricLew	0:80ee8f3b695e	5168	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	5169	* @retval None
EricLew	0:80ee8f3b695e	5170	*/
EricLew	0:80ee8f3b695e	5171	__STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	5172	{
EricLew	0:80ee8f3b695e	5173	/* Note: Write register with some additional bits forced to state reset */
EricLew	0:80ee8f3b695e	5174	/* instead of modifying only the selected bit for this function, */
EricLew	0:80ee8f3b695e	5175	/* to not interfere with bits with HW property "rs". */
EricLew	0:80ee8f3b695e	5176	MODIFY_REG(ADCx->CR,
EricLew	0:80ee8f3b695e	5177	ADC_CR_BITS_PROPERTY_RS,
EricLew	0:80ee8f3b695e	5178	ADC_CR_ADDIS);
EricLew	0:80ee8f3b695e	5179	}
EricLew	0:80ee8f3b695e	5180
EricLew	0:80ee8f3b695e	5181	/**
EricLew	0:80ee8f3b695e	5182	* @brief Get the selected ADC instance enable state.
EricLew	0:80ee8f3b695e	5183	* (0: ADC is disabled, 1: ADC is enabled).
EricLew	0:80ee8f3b695e	5184	* @note On this STM32 family, flag LL_ADC_ISR_ADRDY is raised when the ADC
EricLew	0:80ee8f3b695e	5185	* is enabled and when conversion clock (not core clock) is active.
EricLew	0:80ee8f3b695e	5186	* @rmtoll CR ADEN LL_ADC_IsEnabled
EricLew	0:80ee8f3b695e	5187	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	5188	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	5189	*/
EricLew	0:80ee8f3b695e	5190	__STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	5191	{
EricLew	0:80ee8f3b695e	5192	return (READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN));
EricLew	0:80ee8f3b695e	5193	}
EricLew	0:80ee8f3b695e	5194
EricLew	0:80ee8f3b695e	5195	/**
EricLew	0:80ee8f3b695e	5196	* @brief Get the selected ADC instance disable state.
EricLew	0:80ee8f3b695e	5197	* (0: no ADC disable command on going)
EricLew	0:80ee8f3b695e	5198	* @rmtoll CR ADDIS LL_ADC_IsDisableOngoing
EricLew	0:80ee8f3b695e	5199	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	5200	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	5201	*/
EricLew	0:80ee8f3b695e	5202	__STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	5203	{
EricLew	0:80ee8f3b695e	5204	return (READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS));
EricLew	0:80ee8f3b695e	5205	}
EricLew	0:80ee8f3b695e	5206
EricLew	0:80ee8f3b695e	5207	/**
EricLew	0:80ee8f3b695e	5208	* @brief Start ADC calibration in the mode single-ended
EricLew	0:80ee8f3b695e	5209	* or differential (for devices with differential mode available).
EricLew	0:80ee8f3b695e	5210	* @note On this STM32 family, a delay of 4 ADC clock cycles is required
EricLew	0:80ee8f3b695e	5211	* between ADC end of calibration and ADC enable.
EricLew	0:80ee8f3b695e	5212	* @note On this STM32 family, setting of this feature is conditioned to
EricLew	0:80ee8f3b695e	5213	* ADC state:
EricLew	0:80ee8f3b695e	5214	* ADC must be ADC disabled.
EricLew	0:80ee8f3b695e	5215	* @rmtoll CR ADCAL LL_ADC_StartCalibration\n
EricLew	0:80ee8f3b695e	5216	* CR ADCALDIF LL_ADC_StartCalibration
EricLew	0:80ee8f3b695e	5217	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	5218	* @param SingleDiff This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	5219	* @arg @ref LL_ADC_SINGLE_ENDED
EricLew	0:80ee8f3b695e	5220	* @arg @ref LL_ADC_DIFFERENTIAL_ENDED
EricLew	0:80ee8f3b695e	5221	* @retval None
EricLew	0:80ee8f3b695e	5222	*/
EricLew	0:80ee8f3b695e	5223	__STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx, uint32_t SingleDiff)
EricLew	0:80ee8f3b695e	5224	{
EricLew	0:80ee8f3b695e	5225	/* Note: Write register with some additional bits forced to state reset */
EricLew	0:80ee8f3b695e	5226	/* instead of modifying only the selected bit for this function, */
EricLew	0:80ee8f3b695e	5227	/* to not interfere with bits with HW property "rs". */
EricLew	0:80ee8f3b695e	5228	MODIFY_REG(ADCx->CR,
EricLew	0:80ee8f3b695e	5229	ADC_CR_ADCALDIF \| ADC_CR_BITS_PROPERTY_RS,
EricLew	0:80ee8f3b695e	5230	ADC_CR_ADCAL \| (SingleDiff & ADC_SINGLEDIFF_CALIB_START_MASK));
EricLew	0:80ee8f3b695e	5231	}
EricLew	0:80ee8f3b695e	5232
EricLew	0:80ee8f3b695e	5233	/**
EricLew	0:80ee8f3b695e	5234	* @brief Get ADC calibration state.
EricLew	0:80ee8f3b695e	5235	* (0: calibration complete, 1: calibration in progress)
EricLew	0:80ee8f3b695e	5236	* @rmtoll CR ADCAL LL_ADC_IsCalibrationOnGoing
EricLew	0:80ee8f3b695e	5237	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	5238	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	5239	*/
EricLew	0:80ee8f3b695e	5240	__STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	5241	{
EricLew	0:80ee8f3b695e	5242	return (READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL));
EricLew	0:80ee8f3b695e	5243	}
EricLew	0:80ee8f3b695e	5244
EricLew	0:80ee8f3b695e	5245	/**
EricLew	0:80ee8f3b695e	5246	* @}
EricLew	0:80ee8f3b695e	5247	*/
EricLew	0:80ee8f3b695e	5248
EricLew	0:80ee8f3b695e	5249	/** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular
EricLew	0:80ee8f3b695e	5250	* @{
EricLew	0:80ee8f3b695e	5251	*/
EricLew	0:80ee8f3b695e	5252
EricLew	0:80ee8f3b695e	5253	/**
EricLew	0:80ee8f3b695e	5254	* @brief Start ADC group regular conversion.
EricLew	0:80ee8f3b695e	5255	* @note On this STM32 family, this function is relevant for both
EricLew	0:80ee8f3b695e	5256	* internal trigger (SW start) and external trigger:
EricLew	0:80ee8f3b695e	5257	* - If ADC trigger has been set to software start, ADC conversion
EricLew	0:80ee8f3b695e	5258	* starts immediately.
EricLew	0:80ee8f3b695e	5259	* - If ADC trigger has been set to external trigger, ADC conversion
EricLew	0:80ee8f3b695e	5260	* will start at next trigger event (on the selected trigger edge)
EricLew	0:80ee8f3b695e	5261	* following the ADC start conversion command.
EricLew	0:80ee8f3b695e	5262	* @note On this STM32 family, setting of this feature is conditioned to
EricLew	0:80ee8f3b695e	5263	* ADC state:
EricLew	0:80ee8f3b695e	5264	* ADC must be enabled without conversion on going on group regular,
EricLew	0:80ee8f3b695e	5265	* without conversion stop command on going on group regular.
EricLew	0:80ee8f3b695e	5266	* @rmtoll CR ADSTART LL_ADC_REG_StartConversion
EricLew	0:80ee8f3b695e	5267	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	5268	* @retval None
EricLew	0:80ee8f3b695e	5269	*/
EricLew	0:80ee8f3b695e	5270	__STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	5271	{
EricLew	0:80ee8f3b695e	5272	/* Note: Write register with some additional bits forced to state reset */
EricLew	0:80ee8f3b695e	5273	/* instead of modifying only the selected bit for this function, */
EricLew	0:80ee8f3b695e	5274	/* to not interfere with bits with HW property "rs". */
EricLew	0:80ee8f3b695e	5275	MODIFY_REG(ADCx->CR,
EricLew	0:80ee8f3b695e	5276	ADC_CR_BITS_PROPERTY_RS,
EricLew	0:80ee8f3b695e	5277	ADC_CR_ADSTART);
EricLew	0:80ee8f3b695e	5278	}
EricLew	0:80ee8f3b695e	5279
EricLew	0:80ee8f3b695e	5280	/**
EricLew	0:80ee8f3b695e	5281	* @brief Stop ADC group regular conversion.
EricLew	0:80ee8f3b695e	5282	* @note On this STM32 family, setting of this feature is conditioned to
EricLew	0:80ee8f3b695e	5283	* ADC state:
EricLew	0:80ee8f3b695e	5284	* ADC must be enabled with conversion on going on group regular,
EricLew	0:80ee8f3b695e	5285	* without ADC disable command on going.
EricLew	0:80ee8f3b695e	5286	* @rmtoll CR ADSTP LL_ADC_REG_StopConversion
EricLew	0:80ee8f3b695e	5287	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	5288	* @retval None
EricLew	0:80ee8f3b695e	5289	*/
EricLew	0:80ee8f3b695e	5290	__STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	5291	{
EricLew	0:80ee8f3b695e	5292	/* Note: Write register with some additional bits forced to state reset */
EricLew	0:80ee8f3b695e	5293	/* instead of modifying only the selected bit for this function, */
EricLew	0:80ee8f3b695e	5294	/* to not interfere with bits with HW property "rs". */
EricLew	0:80ee8f3b695e	5295	MODIFY_REG(ADCx->CR,
EricLew	0:80ee8f3b695e	5296	ADC_CR_BITS_PROPERTY_RS,
EricLew	0:80ee8f3b695e	5297	ADC_CR_ADSTP);
EricLew	0:80ee8f3b695e	5298	}
EricLew	0:80ee8f3b695e	5299
EricLew	0:80ee8f3b695e	5300	/**
EricLew	0:80ee8f3b695e	5301	* @brief Get ADC group regular conversion state.
EricLew	0:80ee8f3b695e	5302	* (0: no conversion is on going on ADC group regular)
EricLew	0:80ee8f3b695e	5303	* @rmtoll CR ADSTART LL_ADC_REG_IsConversionOngoing
EricLew	0:80ee8f3b695e	5304	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	5305	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	5306	*/
EricLew	0:80ee8f3b695e	5307	__STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	5308	{
EricLew	0:80ee8f3b695e	5309	return (READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART));
EricLew	0:80ee8f3b695e	5310	}
EricLew	0:80ee8f3b695e	5311
EricLew	0:80ee8f3b695e	5312	/**
EricLew	0:80ee8f3b695e	5313	* @brief Get ADC group regular command of conversion stop state
EricLew	0:80ee8f3b695e	5314	* (0: no command of conversion stop is on going on ADC group regular).
EricLew	0:80ee8f3b695e	5315	* @rmtoll CR ADSTP LL_ADC_REG_IsStopConversionOngoing
EricLew	0:80ee8f3b695e	5316	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	5317	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	5318	*/
EricLew	0:80ee8f3b695e	5319	__STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	5320	{
EricLew	0:80ee8f3b695e	5321	return (READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP));
EricLew	0:80ee8f3b695e	5322	}
EricLew	0:80ee8f3b695e	5323
EricLew	0:80ee8f3b695e	5324	/**
EricLew	0:80ee8f3b695e	5325	* @brief Get ADC group regular conversion data, range fit for
EricLew	0:80ee8f3b695e	5326	* all ADC configurations: all ADC resolutions and
EricLew	0:80ee8f3b695e	5327	* all oversampling increased data width (for devices
EricLew	0:80ee8f3b695e	5328	* with feature oversampling).
EricLew	0:80ee8f3b695e	5329	* @rmtoll DR RDATA LL_ADC_REG_ReadConversionData32
EricLew	0:80ee8f3b695e	5330	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	5331	* @retval 0x00000000...0xFFFFFFFF
EricLew	0:80ee8f3b695e	5332	*/
EricLew	0:80ee8f3b695e	5333	__STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	5334	{
EricLew	0:80ee8f3b695e	5335	return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
EricLew	0:80ee8f3b695e	5336	}
EricLew	0:80ee8f3b695e	5337
EricLew	0:80ee8f3b695e	5338	/**
EricLew	0:80ee8f3b695e	5339	* @brief Get ADC group regular conversion data, range fit for
EricLew	0:80ee8f3b695e	5340	* ADC resolution 12 bits.
EricLew	0:80ee8f3b695e	5341	* @note For devices with feature oversampling: Oversampling
EricLew	0:80ee8f3b695e	5342	* can increase data width, function for extended range
EricLew	0:80ee8f3b695e	5343	* may be needed: @ref LL_ADC_REG_ReadConversionData32.
EricLew	0:80ee8f3b695e	5344	* @rmtoll DR RDATA LL_ADC_REG_ReadConversionData12
EricLew	0:80ee8f3b695e	5345	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	5346	* @retval 0x000...0xFFF
EricLew	0:80ee8f3b695e	5347	*/
EricLew	0:80ee8f3b695e	5348	__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	5349	{
EricLew	0:80ee8f3b695e	5350	return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
EricLew	0:80ee8f3b695e	5351	}
EricLew	0:80ee8f3b695e	5352
EricLew	0:80ee8f3b695e	5353	/**
EricLew	0:80ee8f3b695e	5354	* @brief Get ADC group regular conversion data, range fit for
EricLew	0:80ee8f3b695e	5355	* ADC resolution 10 bits.
EricLew	0:80ee8f3b695e	5356	* @note For devices with feature oversampling: Oversampling
EricLew	0:80ee8f3b695e	5357	* can increase data width, function for extended range
EricLew	0:80ee8f3b695e	5358	* may be needed: @ref LL_ADC_REG_ReadConversionData32.
EricLew	0:80ee8f3b695e	5359	* @rmtoll DR RDATA LL_ADC_REG_ReadConversionData10
EricLew	0:80ee8f3b695e	5360	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	5361	* @retval 0x000...0x3FF
EricLew	0:80ee8f3b695e	5362	*/
EricLew	0:80ee8f3b695e	5363	__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	5364	{
EricLew	0:80ee8f3b695e	5365	return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
EricLew	0:80ee8f3b695e	5366	}
EricLew	0:80ee8f3b695e	5367
EricLew	0:80ee8f3b695e	5368	/**
EricLew	0:80ee8f3b695e	5369	* @brief Get ADC group regular conversion data, range fit for
EricLew	0:80ee8f3b695e	5370	* ADC resolution 8 bits.
EricLew	0:80ee8f3b695e	5371	* @note For devices with feature oversampling: Oversampling
EricLew	0:80ee8f3b695e	5372	* can increase data width, function for extended range
EricLew	0:80ee8f3b695e	5373	* may be needed: @ref LL_ADC_REG_ReadConversionData32.
EricLew	0:80ee8f3b695e	5374	* @rmtoll DR RDATA LL_ADC_REG_ReadConversionData8
EricLew	0:80ee8f3b695e	5375	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	5376	* @retval 0x00...0xFF
EricLew	0:80ee8f3b695e	5377	*/
EricLew	0:80ee8f3b695e	5378	__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	5379	{
EricLew	0:80ee8f3b695e	5380	return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
EricLew	0:80ee8f3b695e	5381	}
EricLew	0:80ee8f3b695e	5382
EricLew	0:80ee8f3b695e	5383	/**
EricLew	0:80ee8f3b695e	5384	* @brief Get ADC group regular conversion data, range fit for
EricLew	0:80ee8f3b695e	5385	* ADC resolution 6 bits.
EricLew	0:80ee8f3b695e	5386	* @note For devices with feature oversampling: Oversampling
EricLew	0:80ee8f3b695e	5387	* can increase data width, function for extended range
EricLew	0:80ee8f3b695e	5388	* may be needed: @ref LL_ADC_REG_ReadConversionData32.
EricLew	0:80ee8f3b695e	5389	* @rmtoll DR RDATA LL_ADC_REG_ReadConversionData6
EricLew	0:80ee8f3b695e	5390	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	5391	* @retval 0x00...0x3F
EricLew	0:80ee8f3b695e	5392	*/
EricLew	0:80ee8f3b695e	5393	__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	5394	{
EricLew	0:80ee8f3b695e	5395	return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
EricLew	0:80ee8f3b695e	5396	}
EricLew	0:80ee8f3b695e	5397
EricLew	0:80ee8f3b695e	5398	#if defined(ADC2)
EricLew	0:80ee8f3b695e	5399	/**
EricLew	0:80ee8f3b695e	5400	* @brief Get ADC multimode conversion data of ADC master, ADC slave
EricLew	0:80ee8f3b695e	5401	* or raw data with ADC master and slave concatenated.
EricLew	0:80ee8f3b695e	5402	* @note If raw data with ADC master and slave concatenated is retrieved,
EricLew	0:80ee8f3b695e	5403	* a macro is available to get the conversion data of
EricLew	0:80ee8f3b695e	5404	* ADC master or ADC slave: see helper macro
EricLew	0:80ee8f3b695e	5405	* @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
EricLew	0:80ee8f3b695e	5406	* (however this macro is mainly intended for multimode
EricLew	0:80ee8f3b695e	5407	* transfer by DMA, because this function can do the same
EricLew	0:80ee8f3b695e	5408	* by getting multimode conversion data of ADC master or ADC slave
EricLew	0:80ee8f3b695e	5409	* separately).
EricLew	0:80ee8f3b695e	5410	* @rmtoll CDR RDATA_MST LL_ADC_REG_ReadMultiConversionData32\n
EricLew	0:80ee8f3b695e	5411	* CDR RDATA_SLV LL_ADC_REG_ReadMultiConversionData32
EricLew	0:80ee8f3b695e	5412	* @param ADCxy_COMMON ADC common instance
EricLew	0:80ee8f3b695e	5413	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
EricLew	0:80ee8f3b695e	5414	* @param ConvData This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	5415	* @arg @ref LL_ADC_MULTI_MASTER
EricLew	0:80ee8f3b695e	5416	* @arg @ref LL_ADC_MULTI_SLAVE
EricLew	0:80ee8f3b695e	5417	* @arg @ref LL_ADC_MULTI_MASTER_SLAVE
EricLew	0:80ee8f3b695e	5418	* @retval 0x00000000...0xFFFFFFFF
EricLew	0:80ee8f3b695e	5419	*/
EricLew	0:80ee8f3b695e	5420	__STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t ConvData)
EricLew	0:80ee8f3b695e	5421	{
EricLew	0:80ee8f3b695e	5422	return (uint32_t)(READ_BIT(ADCxy_COMMON->CDR,
EricLew	0:80ee8f3b695e	5423	(ConvData \| ADC_CDR_RDATA_SLV))
EricLew	0:80ee8f3b695e	5424	>> POSITION_VAL(ConvData)
EricLew	0:80ee8f3b695e	5425	);
EricLew	0:80ee8f3b695e	5426	}
EricLew	0:80ee8f3b695e	5427	#endif /* ADC2 */
EricLew	0:80ee8f3b695e	5428
EricLew	0:80ee8f3b695e	5429	/**
EricLew	0:80ee8f3b695e	5430	* @}
EricLew	0:80ee8f3b695e	5431	*/
EricLew	0:80ee8f3b695e	5432
EricLew	0:80ee8f3b695e	5433	/** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected
EricLew	0:80ee8f3b695e	5434	* @{
EricLew	0:80ee8f3b695e	5435	*/
EricLew	0:80ee8f3b695e	5436
EricLew	0:80ee8f3b695e	5437	/**
EricLew	0:80ee8f3b695e	5438	* @brief Start ADC group injected conversion.
EricLew	0:80ee8f3b695e	5439	* @note On this STM32 family, this function is relevant for both
EricLew	0:80ee8f3b695e	5440	* internal trigger (SW start) and external trigger:
EricLew	0:80ee8f3b695e	5441	* - If ADC trigger has been set to software start, ADC conversion
EricLew	0:80ee8f3b695e	5442	* starts immediately.
EricLew	0:80ee8f3b695e	5443	* - If ADC trigger has been set to external trigger, ADC conversion
EricLew	0:80ee8f3b695e	5444	* will start at next trigger event (on the selected trigger edge)
EricLew	0:80ee8f3b695e	5445	* following the ADC start conversion command.
EricLew	0:80ee8f3b695e	5446	* @note On this STM32 family, setting of this feature is conditioned to
EricLew	0:80ee8f3b695e	5447	* ADC state:
EricLew	0:80ee8f3b695e	5448	* ADC must be enabled without conversion on going on group injected,
EricLew	0:80ee8f3b695e	5449	* without conversion stop command on going on group injected.
EricLew	0:80ee8f3b695e	5450	* @rmtoll CR JADSTART LL_ADC_INJ_StartConversion
EricLew	0:80ee8f3b695e	5451	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	5452	* @retval None
EricLew	0:80ee8f3b695e	5453	*/
EricLew	0:80ee8f3b695e	5454	__STATIC_INLINE void LL_ADC_INJ_StartConversion(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	5455	{
EricLew	0:80ee8f3b695e	5456	/* Note: Write register with some additional bits forced to state reset */
EricLew	0:80ee8f3b695e	5457	/* instead of modifying only the selected bit for this function, */
EricLew	0:80ee8f3b695e	5458	/* to not interfere with bits with HW property "rs". */
EricLew	0:80ee8f3b695e	5459	MODIFY_REG(ADCx->CR,
EricLew	0:80ee8f3b695e	5460	ADC_CR_BITS_PROPERTY_RS,
EricLew	0:80ee8f3b695e	5461	ADC_CR_JADSTART);
EricLew	0:80ee8f3b695e	5462	}
EricLew	0:80ee8f3b695e	5463
EricLew	0:80ee8f3b695e	5464	/**
EricLew	0:80ee8f3b695e	5465	* @brief Stop ADC group injected conversion.
EricLew	0:80ee8f3b695e	5466	* @note On this STM32 family, setting of this feature is conditioned to
EricLew	0:80ee8f3b695e	5467	* ADC state:
EricLew	0:80ee8f3b695e	5468	* ADC must be enabled with conversion on going on group injected,
EricLew	0:80ee8f3b695e	5469	* without ADC disable command on going.
EricLew	0:80ee8f3b695e	5470	* @rmtoll CR JADSTP LL_ADC_INJ_StopConversion
EricLew	0:80ee8f3b695e	5471	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	5472	* @retval None
EricLew	0:80ee8f3b695e	5473	*/
EricLew	0:80ee8f3b695e	5474	__STATIC_INLINE void LL_ADC_INJ_StopConversion(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	5475	{
EricLew	0:80ee8f3b695e	5476	/* Note: Write register with some additional bits forced to state reset */
EricLew	0:80ee8f3b695e	5477	/* instead of modifying only the selected bit for this function, */
EricLew	0:80ee8f3b695e	5478	/* to not interfere with bits with HW property "rs". */
EricLew	0:80ee8f3b695e	5479	MODIFY_REG(ADCx->CR,
EricLew	0:80ee8f3b695e	5480	ADC_CR_BITS_PROPERTY_RS,
EricLew	0:80ee8f3b695e	5481	ADC_CR_JADSTP);
EricLew	0:80ee8f3b695e	5482	}
EricLew	0:80ee8f3b695e	5483
EricLew	0:80ee8f3b695e	5484	/**
EricLew	0:80ee8f3b695e	5485	* @brief Get ADC group injected conversion state.
EricLew	0:80ee8f3b695e	5486	* (0: no conversion is on going on ADC group injected)
EricLew	0:80ee8f3b695e	5487	* @rmtoll CR JADSTART LL_ADC_INJ_IsConversionOngoing
EricLew	0:80ee8f3b695e	5488	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	5489	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	5490	*/
EricLew	0:80ee8f3b695e	5491	__STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	5492	{
EricLew	0:80ee8f3b695e	5493	return (READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART));
EricLew	0:80ee8f3b695e	5494	}
EricLew	0:80ee8f3b695e	5495
EricLew	0:80ee8f3b695e	5496	/**
EricLew	0:80ee8f3b695e	5497	* @brief Get ADC group injected command of conversion stop state
EricLew	0:80ee8f3b695e	5498	* (0: no command of conversion stop is on going on ADC group injected).
EricLew	0:80ee8f3b695e	5499	* @rmtoll CR JADSTP LL_ADC_INJ_IsStopConversionOngoing
EricLew	0:80ee8f3b695e	5500	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	5501	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	5502	*/
EricLew	0:80ee8f3b695e	5503	__STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	5504	{
EricLew	0:80ee8f3b695e	5505	return (READ_BIT(ADCx->CR, ADC_CR_JADSTP) == (ADC_CR_JADSTP));
EricLew	0:80ee8f3b695e	5506	}
EricLew	0:80ee8f3b695e	5507
EricLew	0:80ee8f3b695e	5508	/**
EricLew	0:80ee8f3b695e	5509	* @brief Get ADC group regular conversion data, range fit for
EricLew	0:80ee8f3b695e	5510	* all ADC configurations: all ADC resolutions and
EricLew	0:80ee8f3b695e	5511	* all oversampling increased data width (for devices
EricLew	0:80ee8f3b695e	5512	* with feature oversampling).
EricLew	0:80ee8f3b695e	5513	* @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData32\n
EricLew	0:80ee8f3b695e	5514	* JDR2 JDATA LL_ADC_INJ_ReadConversionData32\n
EricLew	0:80ee8f3b695e	5515	* JDR3 JDATA LL_ADC_INJ_ReadConversionData32\n
EricLew	0:80ee8f3b695e	5516	* JDR4 JDATA LL_ADC_INJ_ReadConversionData32
EricLew	0:80ee8f3b695e	5517	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	5518	* @param Rank This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	5519	* @arg @ref LL_ADC_INJ_RANK_1
EricLew	0:80ee8f3b695e	5520	* @arg @ref LL_ADC_INJ_RANK_2
EricLew	0:80ee8f3b695e	5521	* @arg @ref LL_ADC_INJ_RANK_3
EricLew	0:80ee8f3b695e	5522	* @arg @ref LL_ADC_INJ_RANK_4
EricLew	0:80ee8f3b695e	5523	* @retval 0x00000000...0xFFFFFFFF
EricLew	0:80ee8f3b695e	5524	*/
EricLew	0:80ee8f3b695e	5525	__STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank)
EricLew	0:80ee8f3b695e	5526	{
EricLew	0:80ee8f3b695e	5527	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
EricLew	0:80ee8f3b695e	5528
EricLew	0:80ee8f3b695e	5529	return (uint32_t)(READ_BIT(*preg,
EricLew	0:80ee8f3b695e	5530	ADC_JDR1_JDATA)
EricLew	0:80ee8f3b695e	5531	);
EricLew	0:80ee8f3b695e	5532	}
EricLew	0:80ee8f3b695e	5533
EricLew	0:80ee8f3b695e	5534	/**
EricLew	0:80ee8f3b695e	5535	* @brief Get ADC group injected conversion data, range fit for
EricLew	0:80ee8f3b695e	5536	* ADC resolution 12 bits.
EricLew	0:80ee8f3b695e	5537	* @note For devices with feature oversampling: Oversampling
EricLew	0:80ee8f3b695e	5538	* can increase data width, function for extended range
EricLew	0:80ee8f3b695e	5539	* may be needed: @ref LL_ADC_INJ_ReadConversionData32.
EricLew	0:80ee8f3b695e	5540	* @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData12\n
EricLew	0:80ee8f3b695e	5541	* JDR2 JDATA LL_ADC_INJ_ReadConversionData12\n
EricLew	0:80ee8f3b695e	5542	* JDR3 JDATA LL_ADC_INJ_ReadConversionData12\n
EricLew	0:80ee8f3b695e	5543	* JDR4 JDATA LL_ADC_INJ_ReadConversionData12
EricLew	0:80ee8f3b695e	5544	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	5545	* @param Rank This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	5546	* @arg @ref LL_ADC_INJ_RANK_1
EricLew	0:80ee8f3b695e	5547	* @arg @ref LL_ADC_INJ_RANK_2
EricLew	0:80ee8f3b695e	5548	* @arg @ref LL_ADC_INJ_RANK_3
EricLew	0:80ee8f3b695e	5549	* @arg @ref LL_ADC_INJ_RANK_4
EricLew	0:80ee8f3b695e	5550	* @retval 0x000...0xFFF
EricLew	0:80ee8f3b695e	5551	*/
EricLew	0:80ee8f3b695e	5552	__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank)
EricLew	0:80ee8f3b695e	5553	{
EricLew	0:80ee8f3b695e	5554	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
EricLew	0:80ee8f3b695e	5555
EricLew	0:80ee8f3b695e	5556	return (uint16_t)(READ_BIT(*preg,
EricLew	0:80ee8f3b695e	5557	ADC_JDR1_JDATA)
EricLew	0:80ee8f3b695e	5558	);
EricLew	0:80ee8f3b695e	5559	}
EricLew	0:80ee8f3b695e	5560
EricLew	0:80ee8f3b695e	5561	/**
EricLew	0:80ee8f3b695e	5562	* @brief Get ADC group injected conversion data, range fit for
EricLew	0:80ee8f3b695e	5563	* ADC resolution 10 bits.
EricLew	0:80ee8f3b695e	5564	* @note For devices with feature oversampling: Oversampling
EricLew	0:80ee8f3b695e	5565	* can increase data width, function for extended range
EricLew	0:80ee8f3b695e	5566	* may be needed: @ref LL_ADC_INJ_ReadConversionData32.
EricLew	0:80ee8f3b695e	5567	* @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData10\n
EricLew	0:80ee8f3b695e	5568	* JDR2 JDATA LL_ADC_INJ_ReadConversionData10\n
EricLew	0:80ee8f3b695e	5569	* JDR3 JDATA LL_ADC_INJ_ReadConversionData10\n
EricLew	0:80ee8f3b695e	5570	* JDR4 JDATA LL_ADC_INJ_ReadConversionData10
EricLew	0:80ee8f3b695e	5571	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	5572	* @param Rank This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	5573	* @arg @ref LL_ADC_INJ_RANK_1
EricLew	0:80ee8f3b695e	5574	* @arg @ref LL_ADC_INJ_RANK_2
EricLew	0:80ee8f3b695e	5575	* @arg @ref LL_ADC_INJ_RANK_3
EricLew	0:80ee8f3b695e	5576	* @arg @ref LL_ADC_INJ_RANK_4
EricLew	0:80ee8f3b695e	5577	* @retval 0x000...0x3FF
EricLew	0:80ee8f3b695e	5578	*/
EricLew	0:80ee8f3b695e	5579	__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank)
EricLew	0:80ee8f3b695e	5580	{
EricLew	0:80ee8f3b695e	5581	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
EricLew	0:80ee8f3b695e	5582
EricLew	0:80ee8f3b695e	5583	return (uint16_t)(READ_BIT(*preg,
EricLew	0:80ee8f3b695e	5584	ADC_JDR1_JDATA)
EricLew	0:80ee8f3b695e	5585	);
EricLew	0:80ee8f3b695e	5586	}
EricLew	0:80ee8f3b695e	5587
EricLew	0:80ee8f3b695e	5588	/**
EricLew	0:80ee8f3b695e	5589	* @brief Get ADC group injected conversion data, range fit for
EricLew	0:80ee8f3b695e	5590	* ADC resolution 8 bits.
EricLew	0:80ee8f3b695e	5591	* @note For devices with feature oversampling: Oversampling
EricLew	0:80ee8f3b695e	5592	* can increase data width, function for extended range
EricLew	0:80ee8f3b695e	5593	* may be needed: @ref LL_ADC_INJ_ReadConversionData32.
EricLew	0:80ee8f3b695e	5594	* @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData8\n
EricLew	0:80ee8f3b695e	5595	* JDR2 JDATA LL_ADC_INJ_ReadConversionData8\n
EricLew	0:80ee8f3b695e	5596	* JDR3 JDATA LL_ADC_INJ_ReadConversionData8\n
EricLew	0:80ee8f3b695e	5597	* JDR4 JDATA LL_ADC_INJ_ReadConversionData8
EricLew	0:80ee8f3b695e	5598	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	5599	* @param Rank This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	5600	* @arg @ref LL_ADC_INJ_RANK_1
EricLew	0:80ee8f3b695e	5601	* @arg @ref LL_ADC_INJ_RANK_2
EricLew	0:80ee8f3b695e	5602	* @arg @ref LL_ADC_INJ_RANK_3
EricLew	0:80ee8f3b695e	5603	* @arg @ref LL_ADC_INJ_RANK_4
EricLew	0:80ee8f3b695e	5604	* @retval 0x00...0xFF
EricLew	0:80ee8f3b695e	5605	*/
EricLew	0:80ee8f3b695e	5606	__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank)
EricLew	0:80ee8f3b695e	5607	{
EricLew	0:80ee8f3b695e	5608	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
EricLew	0:80ee8f3b695e	5609
EricLew	0:80ee8f3b695e	5610	return (uint8_t)(READ_BIT(*preg,
EricLew	0:80ee8f3b695e	5611	ADC_JDR1_JDATA)
EricLew	0:80ee8f3b695e	5612	);
EricLew	0:80ee8f3b695e	5613	}
EricLew	0:80ee8f3b695e	5614
EricLew	0:80ee8f3b695e	5615	/**
EricLew	0:80ee8f3b695e	5616	* @brief Get ADC group injected conversion data, range fit for
EricLew	0:80ee8f3b695e	5617	* ADC resolution 6 bits.
EricLew	0:80ee8f3b695e	5618	* @note For devices with feature oversampling: Oversampling
EricLew	0:80ee8f3b695e	5619	* can increase data width, function for extended range
EricLew	0:80ee8f3b695e	5620	* may be needed: @ref LL_ADC_INJ_ReadConversionData32.
EricLew	0:80ee8f3b695e	5621	* @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData6\n
EricLew	0:80ee8f3b695e	5622	* JDR2 JDATA LL_ADC_INJ_ReadConversionData6\n
EricLew	0:80ee8f3b695e	5623	* JDR3 JDATA LL_ADC_INJ_ReadConversionData6\n
EricLew	0:80ee8f3b695e	5624	* JDR4 JDATA LL_ADC_INJ_ReadConversionData6
EricLew	0:80ee8f3b695e	5625	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	5626	* @param Rank This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	5627	* @arg @ref LL_ADC_INJ_RANK_1
EricLew	0:80ee8f3b695e	5628	* @arg @ref LL_ADC_INJ_RANK_2
EricLew	0:80ee8f3b695e	5629	* @arg @ref LL_ADC_INJ_RANK_3
EricLew	0:80ee8f3b695e	5630	* @arg @ref LL_ADC_INJ_RANK_4
EricLew	0:80ee8f3b695e	5631	* @retval 0x00...0x3F
EricLew	0:80ee8f3b695e	5632	*/
EricLew	0:80ee8f3b695e	5633	__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(ADC_TypeDef *ADCx, uint32_t Rank)
EricLew	0:80ee8f3b695e	5634	{
EricLew	0:80ee8f3b695e	5635	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
EricLew	0:80ee8f3b695e	5636
EricLew	0:80ee8f3b695e	5637	return (uint8_t)(READ_BIT(*preg,
EricLew	0:80ee8f3b695e	5638	ADC_JDR1_JDATA)
EricLew	0:80ee8f3b695e	5639	);
EricLew	0:80ee8f3b695e	5640	}
EricLew	0:80ee8f3b695e	5641
EricLew	0:80ee8f3b695e	5642	/**
EricLew	0:80ee8f3b695e	5643	* @}
EricLew	0:80ee8f3b695e	5644	*/
EricLew	0:80ee8f3b695e	5645
EricLew	0:80ee8f3b695e	5646	/** @defgroup ADC_LL_EF_FLAG_Management ADC flag management
EricLew	0:80ee8f3b695e	5647	* @{
EricLew	0:80ee8f3b695e	5648	*/
EricLew	0:80ee8f3b695e	5649
EricLew	0:80ee8f3b695e	5650	/**
EricLew	0:80ee8f3b695e	5651	* @brief Get flag ADC ready.
EricLew	0:80ee8f3b695e	5652	* @rmtoll ISR ADRDY LL_ADC_IsActiveFlag_ADRDY
EricLew	0:80ee8f3b695e	5653	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	5654	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	5655	*/
EricLew	0:80ee8f3b695e	5656	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	5657	{
EricLew	0:80ee8f3b695e	5658	return (READ_BIT(ADCx->ISR, ADC_ISR_ADRDY) == (ADC_ISR_ADRDY));
EricLew	0:80ee8f3b695e	5659	}
EricLew	0:80ee8f3b695e	5660
EricLew	0:80ee8f3b695e	5661	/**
EricLew	0:80ee8f3b695e	5662	* @brief Get flag ADC group regular end of unitary conversion.
EricLew	0:80ee8f3b695e	5663	* @rmtoll ISR EOC LL_ADC_IsActiveFlag_EOC
EricLew	0:80ee8f3b695e	5664	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	5665	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	5666	*/
EricLew	0:80ee8f3b695e	5667	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	5668	{
EricLew	0:80ee8f3b695e	5669	return (READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC));
EricLew	0:80ee8f3b695e	5670	}
EricLew	0:80ee8f3b695e	5671
EricLew	0:80ee8f3b695e	5672	/**
EricLew	0:80ee8f3b695e	5673	* @brief Get flag ADC group regular end of sequence conversions.
EricLew	0:80ee8f3b695e	5674	* @rmtoll ISR EOS LL_ADC_IsActiveFlag_EOS
EricLew	0:80ee8f3b695e	5675	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	5676	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	5677	*/
EricLew	0:80ee8f3b695e	5678	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	5679	{
EricLew	0:80ee8f3b695e	5680	return (READ_BIT(ADCx->ISR, ADC_ISR_EOS) == (ADC_ISR_EOS));
EricLew	0:80ee8f3b695e	5681	}
EricLew	0:80ee8f3b695e	5682
EricLew	0:80ee8f3b695e	5683	/**
EricLew	0:80ee8f3b695e	5684	* @brief Get flag ADC group regular overrun.
EricLew	0:80ee8f3b695e	5685	* @rmtoll ISR OVR LL_ADC_IsActiveFlag_OVR
EricLew	0:80ee8f3b695e	5686	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	5687	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	5688	*/
EricLew	0:80ee8f3b695e	5689	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	5690	{
EricLew	0:80ee8f3b695e	5691	return (READ_BIT(ADCx->ISR, ADC_ISR_OVR) == (ADC_ISR_OVR));
EricLew	0:80ee8f3b695e	5692	}
EricLew	0:80ee8f3b695e	5693
EricLew	0:80ee8f3b695e	5694	/**
EricLew	0:80ee8f3b695e	5695	* @brief Get flag ADC group regular end of sampling phase.
EricLew	0:80ee8f3b695e	5696	* @rmtoll ISR EOSMP LL_ADC_IsActiveFlag_EOSMP
EricLew	0:80ee8f3b695e	5697	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	5698	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	5699	*/
EricLew	0:80ee8f3b695e	5700	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	5701	{
EricLew	0:80ee8f3b695e	5702	return (READ_BIT(ADCx->ISR, ADC_ISR_EOSMP) == (ADC_ISR_EOSMP));
EricLew	0:80ee8f3b695e	5703	}
EricLew	0:80ee8f3b695e	5704
EricLew	0:80ee8f3b695e	5705	/**
EricLew	0:80ee8f3b695e	5706	* @brief Get flag ADC group injected end of unitary conversion.
EricLew	0:80ee8f3b695e	5707	* @rmtoll ISR JEOC LL_ADC_IsActiveFlag_JEOC
EricLew	0:80ee8f3b695e	5708	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	5709	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	5710	*/
EricLew	0:80ee8f3b695e	5711	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	5712	{
EricLew	0:80ee8f3b695e	5713	return (READ_BIT(ADCx->ISR, ADC_ISR_JEOC) == (ADC_ISR_JEOC));
EricLew	0:80ee8f3b695e	5714	}
EricLew	0:80ee8f3b695e	5715
EricLew	0:80ee8f3b695e	5716	/**
EricLew	0:80ee8f3b695e	5717	* @brief Get flag ADC group injected end of sequence conversions.
EricLew	0:80ee8f3b695e	5718	* @rmtoll ISR JEOS LL_ADC_IsActiveFlag_JEOS
EricLew	0:80ee8f3b695e	5719	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	5720	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	5721	*/
EricLew	0:80ee8f3b695e	5722	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	5723	{
EricLew	0:80ee8f3b695e	5724	return (READ_BIT(ADCx->ISR, ADC_ISR_JEOS) == (ADC_ISR_JEOS));
EricLew	0:80ee8f3b695e	5725	}
EricLew	0:80ee8f3b695e	5726
EricLew	0:80ee8f3b695e	5727	/**
EricLew	0:80ee8f3b695e	5728	* @brief Get flag ADC group injected contexts queue overflow.
EricLew	0:80ee8f3b695e	5729	* @rmtoll ISR JQOVF LL_ADC_IsActiveFlag_JQOVF
EricLew	0:80ee8f3b695e	5730	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	5731	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	5732	*/
EricLew	0:80ee8f3b695e	5733	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JQOVF(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	5734	{
EricLew	0:80ee8f3b695e	5735	return (READ_BIT(ADCx->ISR, ADC_ISR_JQOVF) == (ADC_ISR_JQOVF));
EricLew	0:80ee8f3b695e	5736	}
EricLew	0:80ee8f3b695e	5737
EricLew	0:80ee8f3b695e	5738	/**
EricLew	0:80ee8f3b695e	5739	* @brief Get flag ADC analog watchdog 1 flag
EricLew	0:80ee8f3b695e	5740	* @rmtoll ISR AWD1 LL_ADC_IsActiveFlag_AWD1
EricLew	0:80ee8f3b695e	5741	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	5742	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	5743	*/
EricLew	0:80ee8f3b695e	5744	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	5745	{
EricLew	0:80ee8f3b695e	5746	return (READ_BIT(ADCx->ISR, ADC_ISR_AWD1) == (ADC_ISR_AWD1));
EricLew	0:80ee8f3b695e	5747	}
EricLew	0:80ee8f3b695e	5748
EricLew	0:80ee8f3b695e	5749	/**
EricLew	0:80ee8f3b695e	5750	* @brief Get flag ADC analog watchdog 2.
EricLew	0:80ee8f3b695e	5751	* @rmtoll ISR AWD2 LL_ADC_IsActiveFlag_AWD2
EricLew	0:80ee8f3b695e	5752	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	5753	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	5754	*/
EricLew	0:80ee8f3b695e	5755	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	5756	{
EricLew	0:80ee8f3b695e	5757	return (READ_BIT(ADCx->ISR, ADC_ISR_AWD2) == (ADC_ISR_AWD2));
EricLew	0:80ee8f3b695e	5758	}
EricLew	0:80ee8f3b695e	5759
EricLew	0:80ee8f3b695e	5760	/**
EricLew	0:80ee8f3b695e	5761	* @brief Get flag ADC analog watchdog 3.
EricLew	0:80ee8f3b695e	5762	* @rmtoll ISR AWD3 LL_ADC_IsActiveFlag_AWD3
EricLew	0:80ee8f3b695e	5763	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	5764	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	5765	*/
EricLew	0:80ee8f3b695e	5766	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	5767	{
EricLew	0:80ee8f3b695e	5768	return (READ_BIT(ADCx->ISR, ADC_ISR_AWD3) == (ADC_ISR_AWD3));
EricLew	0:80ee8f3b695e	5769	}
EricLew	0:80ee8f3b695e	5770
EricLew	0:80ee8f3b695e	5771	/**
EricLew	0:80ee8f3b695e	5772	* @brief Clear flag ADC ready.
EricLew	0:80ee8f3b695e	5773	* @rmtoll ISR ADRDY LL_ADC_ClearFlag_ADRDY
EricLew	0:80ee8f3b695e	5774	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	5775	* @retval None
EricLew	0:80ee8f3b695e	5776	*/
EricLew	0:80ee8f3b695e	5777	__STATIC_INLINE void LL_ADC_ClearFlag_ADRDY(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	5778	{
EricLew	0:80ee8f3b695e	5779	WRITE_REG(ADCx->ISR, ADC_ISR_ADRDY);
EricLew	0:80ee8f3b695e	5780	}
EricLew	0:80ee8f3b695e	5781
EricLew	0:80ee8f3b695e	5782	/**
EricLew	0:80ee8f3b695e	5783	* @brief Clear flag ADC group regular end of unitary conversion.
EricLew	0:80ee8f3b695e	5784	* @rmtoll ISR EOC LL_ADC_ClearFlag_EOC
EricLew	0:80ee8f3b695e	5785	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	5786	* @retval None
EricLew	0:80ee8f3b695e	5787	*/
EricLew	0:80ee8f3b695e	5788	__STATIC_INLINE void LL_ADC_ClearFlag_EOC(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	5789	{
EricLew	0:80ee8f3b695e	5790	WRITE_REG(ADCx->ISR, ADC_ISR_EOC);
EricLew	0:80ee8f3b695e	5791	}
EricLew	0:80ee8f3b695e	5792
EricLew	0:80ee8f3b695e	5793	/**
EricLew	0:80ee8f3b695e	5794	* @brief Clear flag ADC group regular end of sequence conversions.
EricLew	0:80ee8f3b695e	5795	* @rmtoll ISR EOS LL_ADC_ClearFlag_EOS
EricLew	0:80ee8f3b695e	5796	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	5797	* @retval None
EricLew	0:80ee8f3b695e	5798	*/
EricLew	0:80ee8f3b695e	5799	__STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	5800	{
EricLew	0:80ee8f3b695e	5801	WRITE_REG(ADCx->ISR, ADC_ISR_EOS);
EricLew	0:80ee8f3b695e	5802	}
EricLew	0:80ee8f3b695e	5803
EricLew	0:80ee8f3b695e	5804	/**
EricLew	0:80ee8f3b695e	5805	* @brief Clear flag ADC group regular overrun.
EricLew	0:80ee8f3b695e	5806	* @rmtoll ISR OVR LL_ADC_ClearFlag_OVR
EricLew	0:80ee8f3b695e	5807	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	5808	* @retval None
EricLew	0:80ee8f3b695e	5809	*/
EricLew	0:80ee8f3b695e	5810	__STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	5811	{
EricLew	0:80ee8f3b695e	5812	WRITE_REG(ADCx->ISR, ADC_ISR_OVR);
EricLew	0:80ee8f3b695e	5813	}
EricLew	0:80ee8f3b695e	5814
EricLew	0:80ee8f3b695e	5815	/**
EricLew	0:80ee8f3b695e	5816	* @brief Clear flag ADC group regular end of sampling phase.
EricLew	0:80ee8f3b695e	5817	* @rmtoll ISR EOSMP LL_ADC_ClearFlag_EOSMP
EricLew	0:80ee8f3b695e	5818	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	5819	* @retval None
EricLew	0:80ee8f3b695e	5820	*/
EricLew	0:80ee8f3b695e	5821	__STATIC_INLINE void LL_ADC_ClearFlag_EOSMP(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	5822	{
EricLew	0:80ee8f3b695e	5823	WRITE_REG(ADCx->ISR, ADC_ISR_EOSMP);
EricLew	0:80ee8f3b695e	5824	}
EricLew	0:80ee8f3b695e	5825
EricLew	0:80ee8f3b695e	5826	/**
EricLew	0:80ee8f3b695e	5827	* @brief Clear flag ADC group injected end of unitary conversion.
EricLew	0:80ee8f3b695e	5828	* @rmtoll ISR JEOC LL_ADC_ClearFlag_JEOC
EricLew	0:80ee8f3b695e	5829	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	5830	* @retval None
EricLew	0:80ee8f3b695e	5831	*/
EricLew	0:80ee8f3b695e	5832	__STATIC_INLINE void LL_ADC_ClearFlag_JEOC(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	5833	{
EricLew	0:80ee8f3b695e	5834	WRITE_REG(ADCx->ISR, ADC_ISR_JEOC);
EricLew	0:80ee8f3b695e	5835	}
EricLew	0:80ee8f3b695e	5836
EricLew	0:80ee8f3b695e	5837	/**
EricLew	0:80ee8f3b695e	5838	* @brief Clear flag ADC group injected end of sequence conversions.
EricLew	0:80ee8f3b695e	5839	* @rmtoll ISR JEOS LL_ADC_ClearFlag_JEOS
EricLew	0:80ee8f3b695e	5840	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	5841	* @retval None
EricLew	0:80ee8f3b695e	5842	*/
EricLew	0:80ee8f3b695e	5843	__STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	5844	{
EricLew	0:80ee8f3b695e	5845	WRITE_REG(ADCx->ISR, ADC_ISR_JEOS);
EricLew	0:80ee8f3b695e	5846	}
EricLew	0:80ee8f3b695e	5847
EricLew	0:80ee8f3b695e	5848	/**
EricLew	0:80ee8f3b695e	5849	* @brief Clear flag ADC group injected contexts queue overflow.
EricLew	0:80ee8f3b695e	5850	* @rmtoll ISR JQOVF LL_ADC_ClearFlag_JQOVF
EricLew	0:80ee8f3b695e	5851	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	5852	* @retval None
EricLew	0:80ee8f3b695e	5853	*/
EricLew	0:80ee8f3b695e	5854	__STATIC_INLINE void LL_ADC_ClearFlag_JQOVF(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	5855	{
EricLew	0:80ee8f3b695e	5856	WRITE_REG(ADCx->ISR, ADC_ISR_JQOVF);
EricLew	0:80ee8f3b695e	5857	}
EricLew	0:80ee8f3b695e	5858
EricLew	0:80ee8f3b695e	5859	/**
EricLew	0:80ee8f3b695e	5860	* @brief Clear flag ADC analog watchdog 1.
EricLew	0:80ee8f3b695e	5861	* @rmtoll ISR AWD1 LL_ADC_ClearFlag_AWD1
EricLew	0:80ee8f3b695e	5862	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	5863	* @retval None
EricLew	0:80ee8f3b695e	5864	*/
EricLew	0:80ee8f3b695e	5865	__STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	5866	{
EricLew	0:80ee8f3b695e	5867	WRITE_REG(ADCx->ISR, ADC_ISR_AWD1);
EricLew	0:80ee8f3b695e	5868	}
EricLew	0:80ee8f3b695e	5869
EricLew	0:80ee8f3b695e	5870	/**
EricLew	0:80ee8f3b695e	5871	* @brief Clear flag ADC analog watchdog 2.
EricLew	0:80ee8f3b695e	5872	* @rmtoll ISR AWD2 LL_ADC_ClearFlag_AWD2
EricLew	0:80ee8f3b695e	5873	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	5874	* @retval None
EricLew	0:80ee8f3b695e	5875	*/
EricLew	0:80ee8f3b695e	5876	__STATIC_INLINE void LL_ADC_ClearFlag_AWD2(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	5877	{
EricLew	0:80ee8f3b695e	5878	WRITE_REG(ADCx->ISR, ADC_ISR_AWD2);
EricLew	0:80ee8f3b695e	5879	}
EricLew	0:80ee8f3b695e	5880
EricLew	0:80ee8f3b695e	5881	/**
EricLew	0:80ee8f3b695e	5882	* @brief Clear flag ADC analog watchdog 3.
EricLew	0:80ee8f3b695e	5883	* @rmtoll ISR AWD3 LL_ADC_ClearFlag_AWD3
EricLew	0:80ee8f3b695e	5884	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	5885	* @retval None
EricLew	0:80ee8f3b695e	5886	*/
EricLew	0:80ee8f3b695e	5887	__STATIC_INLINE void LL_ADC_ClearFlag_AWD3(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	5888	{
EricLew	0:80ee8f3b695e	5889	WRITE_REG(ADCx->ISR, ADC_ISR_AWD3);
EricLew	0:80ee8f3b695e	5890	}
EricLew	0:80ee8f3b695e	5891
EricLew	0:80ee8f3b695e	5892	#if defined(ADC2)
EricLew	0:80ee8f3b695e	5893	/**
EricLew	0:80ee8f3b695e	5894	* @brief Get flag multimode ADC ready of the ADC master.
EricLew	0:80ee8f3b695e	5895	* @rmtoll CSR ADRDY_MST LL_ADC_IsActiveFlag_MST_ADRDY
EricLew	0:80ee8f3b695e	5896	* @param ADCxy_COMMON ADC common instance
EricLew	0:80ee8f3b695e	5897	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
EricLew	0:80ee8f3b695e	5898	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	5899	*/
EricLew	0:80ee8f3b695e	5900	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON)
EricLew	0:80ee8f3b695e	5901	{
EricLew	0:80ee8f3b695e	5902	return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_ADRDY_MST) == (ADC_CSR_ADRDY_MST));
EricLew	0:80ee8f3b695e	5903	}
EricLew	0:80ee8f3b695e	5904
EricLew	0:80ee8f3b695e	5905	/**
EricLew	0:80ee8f3b695e	5906	* @brief Get flag multimode ADC ready of the ADC slave.
EricLew	0:80ee8f3b695e	5907	* @rmtoll CSR ADRDY_SLV LL_ADC_IsActiveFlag_SLV_ADRDY
EricLew	0:80ee8f3b695e	5908	* @param ADCxy_COMMON ADC common instance
EricLew	0:80ee8f3b695e	5909	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
EricLew	0:80ee8f3b695e	5910	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	5911	*/
EricLew	0:80ee8f3b695e	5912	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON)
EricLew	0:80ee8f3b695e	5913	{
EricLew	0:80ee8f3b695e	5914	return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_ADRDY_SLV) == (ADC_CSR_ADRDY_SLV));
EricLew	0:80ee8f3b695e	5915	}
EricLew	0:80ee8f3b695e	5916
EricLew	0:80ee8f3b695e	5917	/**
EricLew	0:80ee8f3b695e	5918	* @brief Get flag multimode ADC group regular end of unitary conversion of the ADC master.
EricLew	0:80ee8f3b695e	5919	* @rmtoll CSR EOC_MST LL_ADC_IsActiveFlag_MST_EOC
EricLew	0:80ee8f3b695e	5920	* @param ADCxy_COMMON ADC common instance
EricLew	0:80ee8f3b695e	5921	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
EricLew	0:80ee8f3b695e	5922	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	5923	*/
EricLew	0:80ee8f3b695e	5924	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOC(ADC_Common_TypeDef *ADCxy_COMMON)
EricLew	0:80ee8f3b695e	5925	{
EricLew	0:80ee8f3b695e	5926	return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_EOC_SLV) == (ADC_CSR_EOC_SLV));
EricLew	0:80ee8f3b695e	5927	}
EricLew	0:80ee8f3b695e	5928
EricLew	0:80ee8f3b695e	5929	/**
EricLew	0:80ee8f3b695e	5930	* @brief Get flag multimode ADC group regular end of unitary conversion of the ADC slave.
EricLew	0:80ee8f3b695e	5931	* @rmtoll CSR EOC_SLV LL_ADC_IsActiveFlag_SLV_EOC
EricLew	0:80ee8f3b695e	5932	* @param ADCxy_COMMON ADC common instance
EricLew	0:80ee8f3b695e	5933	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
EricLew	0:80ee8f3b695e	5934	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	5935	*/
EricLew	0:80ee8f3b695e	5936	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOC(ADC_Common_TypeDef *ADCxy_COMMON)
EricLew	0:80ee8f3b695e	5937	{
EricLew	0:80ee8f3b695e	5938	return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_EOC_SLV) == (ADC_CSR_EOC_SLV));
EricLew	0:80ee8f3b695e	5939	}
EricLew	0:80ee8f3b695e	5940
EricLew	0:80ee8f3b695e	5941	/**
EricLew	0:80ee8f3b695e	5942	* @brief Get flag multimode ADC group regular end of sequence conversions of the ADC master.
EricLew	0:80ee8f3b695e	5943	* @rmtoll CSR EOS_MST LL_ADC_IsActiveFlag_MST_EOS
EricLew	0:80ee8f3b695e	5944	* @param ADCxy_COMMON ADC common instance
EricLew	0:80ee8f3b695e	5945	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
EricLew	0:80ee8f3b695e	5946	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	5947	*/
EricLew	0:80ee8f3b695e	5948	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOS(ADC_Common_TypeDef *ADCxy_COMMON)
EricLew	0:80ee8f3b695e	5949	{
EricLew	0:80ee8f3b695e	5950	return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_EOS_MST) == (ADC_CSR_EOS_MST));
EricLew	0:80ee8f3b695e	5951	}
EricLew	0:80ee8f3b695e	5952
EricLew	0:80ee8f3b695e	5953	/**
EricLew	0:80ee8f3b695e	5954	* @brief Get flag multimode ADC group regular end of sequence conversions of the ADC slave.
EricLew	0:80ee8f3b695e	5955	* @rmtoll CSR EOS_SLV LL_ADC_IsActiveFlag_SLV_EOS
EricLew	0:80ee8f3b695e	5956	* @param ADCxy_COMMON ADC common instance
EricLew	0:80ee8f3b695e	5957	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
EricLew	0:80ee8f3b695e	5958	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	5959	*/
EricLew	0:80ee8f3b695e	5960	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOS(ADC_Common_TypeDef *ADCxy_COMMON)
EricLew	0:80ee8f3b695e	5961	{
EricLew	0:80ee8f3b695e	5962	return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_EOS_SLV) == (ADC_CSR_EOS_SLV));
EricLew	0:80ee8f3b695e	5963	}
EricLew	0:80ee8f3b695e	5964
EricLew	0:80ee8f3b695e	5965	/**
EricLew	0:80ee8f3b695e	5966	* @brief Get flag multimode ADC group regular overrun of the ADC master.
EricLew	0:80ee8f3b695e	5967	* @rmtoll CSR OVR_MST LL_ADC_IsActiveFlag_MST_OVR
EricLew	0:80ee8f3b695e	5968	* @param ADCxy_COMMON ADC common instance
EricLew	0:80ee8f3b695e	5969	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
EricLew	0:80ee8f3b695e	5970	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	5971	*/
EricLew	0:80ee8f3b695e	5972	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
EricLew	0:80ee8f3b695e	5973	{
EricLew	0:80ee8f3b695e	5974	return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_OVR_MST) == (ADC_CSR_OVR_MST));
EricLew	0:80ee8f3b695e	5975	}
EricLew	0:80ee8f3b695e	5976
EricLew	0:80ee8f3b695e	5977	/**
EricLew	0:80ee8f3b695e	5978	* @brief Get flag multimode ADC group regular overrun of the ADC slave.
EricLew	0:80ee8f3b695e	5979	* @rmtoll CSR OVR_SLV LL_ADC_IsActiveFlag_SLV_OVR
EricLew	0:80ee8f3b695e	5980	* @param ADCxy_COMMON ADC common instance
EricLew	0:80ee8f3b695e	5981	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
EricLew	0:80ee8f3b695e	5982	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	5983	*/
EricLew	0:80ee8f3b695e	5984	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
EricLew	0:80ee8f3b695e	5985	{
EricLew	0:80ee8f3b695e	5986	return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_OVR_SLV) == (ADC_CSR_OVR_SLV));
EricLew	0:80ee8f3b695e	5987	}
EricLew	0:80ee8f3b695e	5988
EricLew	0:80ee8f3b695e	5989	/**
EricLew	0:80ee8f3b695e	5990	* @brief Get flag multimode ADC group regular end of sampling of the ADC master.
EricLew	0:80ee8f3b695e	5991	* @rmtoll CSR EOSMP_MST LL_ADC_IsActiveFlag_MST_EOSMP
EricLew	0:80ee8f3b695e	5992	* @param ADCxy_COMMON ADC common instance
EricLew	0:80ee8f3b695e	5993	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
EricLew	0:80ee8f3b695e	5994	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	5995	*/
EricLew	0:80ee8f3b695e	5996	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON)
EricLew	0:80ee8f3b695e	5997	{
EricLew	0:80ee8f3b695e	5998	return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_EOSMP_MST) == (ADC_CSR_EOSMP_MST));
EricLew	0:80ee8f3b695e	5999	}
EricLew	0:80ee8f3b695e	6000
EricLew	0:80ee8f3b695e	6001	/**
EricLew	0:80ee8f3b695e	6002	* @brief Get flag multimode ADC group regular end of sampling of the ADC slave.
EricLew	0:80ee8f3b695e	6003	* @rmtoll CSR EOSMP_SLV LL_ADC_IsActiveFlag_SLV_EOSMP
EricLew	0:80ee8f3b695e	6004	* @param ADCxy_COMMON ADC common instance
EricLew	0:80ee8f3b695e	6005	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
EricLew	0:80ee8f3b695e	6006	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	6007	*/
EricLew	0:80ee8f3b695e	6008	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON)
EricLew	0:80ee8f3b695e	6009	{
EricLew	0:80ee8f3b695e	6010	return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_EOSMP_SLV) == (ADC_CSR_EOSMP_SLV));
EricLew	0:80ee8f3b695e	6011	}
EricLew	0:80ee8f3b695e	6012
EricLew	0:80ee8f3b695e	6013	/**
EricLew	0:80ee8f3b695e	6014	* @brief Get flag multimode ADC group injected end of unitary conversion of the ADC master.
EricLew	0:80ee8f3b695e	6015	* @rmtoll CSR JEOC_MST LL_ADC_IsActiveFlag_MST_JEOC
EricLew	0:80ee8f3b695e	6016	* @param ADCxy_COMMON ADC common instance
EricLew	0:80ee8f3b695e	6017	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
EricLew	0:80ee8f3b695e	6018	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	6019	*/
EricLew	0:80ee8f3b695e	6020	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOC(ADC_Common_TypeDef *ADCxy_COMMON)
EricLew	0:80ee8f3b695e	6021	{
EricLew	0:80ee8f3b695e	6022	return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_JEOC_MST) == (ADC_CSR_JEOC_MST));
EricLew	0:80ee8f3b695e	6023	}
EricLew	0:80ee8f3b695e	6024
EricLew	0:80ee8f3b695e	6025	/**
EricLew	0:80ee8f3b695e	6026	* @brief Get flag multimode ADC group injected end of unitary conversion of the ADC slave.
EricLew	0:80ee8f3b695e	6027	* @rmtoll CSR JEOC_SLV LL_ADC_IsActiveFlag_SLV_JEOC
EricLew	0:80ee8f3b695e	6028	* @param ADCxy_COMMON ADC common instance
EricLew	0:80ee8f3b695e	6029	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
EricLew	0:80ee8f3b695e	6030	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	6031	*/
EricLew	0:80ee8f3b695e	6032	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOC(ADC_Common_TypeDef *ADCxy_COMMON)
EricLew	0:80ee8f3b695e	6033	{
EricLew	0:80ee8f3b695e	6034	return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_JEOC_SLV) == (ADC_CSR_JEOC_SLV));
EricLew	0:80ee8f3b695e	6035	}
EricLew	0:80ee8f3b695e	6036
EricLew	0:80ee8f3b695e	6037	/**
EricLew	0:80ee8f3b695e	6038	* @brief Get flag multimode ADC group injected end of sequence conversions of the ADC master.
EricLew	0:80ee8f3b695e	6039	* @rmtoll CSR JEOS_MST LL_ADC_IsActiveFlag_MST_JEOS
EricLew	0:80ee8f3b695e	6040	* @param ADCxy_COMMON ADC common instance
EricLew	0:80ee8f3b695e	6041	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
EricLew	0:80ee8f3b695e	6042	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	6043	*/
EricLew	0:80ee8f3b695e	6044	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
EricLew	0:80ee8f3b695e	6045	{
EricLew	0:80ee8f3b695e	6046	return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_JEOS_MST) == (ADC_CSR_JEOS_MST));
EricLew	0:80ee8f3b695e	6047	}
EricLew	0:80ee8f3b695e	6048
EricLew	0:80ee8f3b695e	6049	/**
EricLew	0:80ee8f3b695e	6050	* @brief Get flag multimode ADC group injected end of sequence conversions of the ADC slave.
EricLew	0:80ee8f3b695e	6051	* @rmtoll CSR JEOS_SLV LL_ADC_IsActiveFlag_SLV_JEOS
EricLew	0:80ee8f3b695e	6052	* @param ADCxy_COMMON ADC common instance
EricLew	0:80ee8f3b695e	6053	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
EricLew	0:80ee8f3b695e	6054	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	6055	*/
EricLew	0:80ee8f3b695e	6056	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
EricLew	0:80ee8f3b695e	6057	{
EricLew	0:80ee8f3b695e	6058	return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_JEOS_SLV) == (ADC_CSR_JEOS_SLV));
EricLew	0:80ee8f3b695e	6059	}
EricLew	0:80ee8f3b695e	6060
EricLew	0:80ee8f3b695e	6061	/**
EricLew	0:80ee8f3b695e	6062	* @brief Get flag multimode ADC group injected context queue overflow of the ADC master.
EricLew	0:80ee8f3b695e	6063	* @rmtoll CSR JQOVF_MST LL_ADC_IsActiveFlag_MST_JQOVF
EricLew	0:80ee8f3b695e	6064	* @param ADCxy_COMMON ADC common instance
EricLew	0:80ee8f3b695e	6065	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
EricLew	0:80ee8f3b695e	6066	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	6067	*/
EricLew	0:80ee8f3b695e	6068	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON)
EricLew	0:80ee8f3b695e	6069	{
EricLew	0:80ee8f3b695e	6070	return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_JQOVF_MST) == (ADC_CSR_JQOVF_MST));
EricLew	0:80ee8f3b695e	6071	}
EricLew	0:80ee8f3b695e	6072
EricLew	0:80ee8f3b695e	6073	/**
EricLew	0:80ee8f3b695e	6074	* @brief Get flag multimode ADC group injected context queue overflow of the ADC slave.
EricLew	0:80ee8f3b695e	6075	* @rmtoll CSR JQOVF_SLV LL_ADC_IsActiveFlag_SLV_JQOVF
EricLew	0:80ee8f3b695e	6076	* @param ADCxy_COMMON ADC common instance
EricLew	0:80ee8f3b695e	6077	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
EricLew	0:80ee8f3b695e	6078	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	6079	*/
EricLew	0:80ee8f3b695e	6080	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON)
EricLew	0:80ee8f3b695e	6081	{
EricLew	0:80ee8f3b695e	6082	return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_JQOVF_SLV) == (ADC_CSR_JQOVF_SLV));
EricLew	0:80ee8f3b695e	6083	}
EricLew	0:80ee8f3b695e	6084
EricLew	0:80ee8f3b695e	6085	/**
EricLew	0:80ee8f3b695e	6086	* @brief Get flag multimode ADC analog watchdog 1 of the ADC master.
EricLew	0:80ee8f3b695e	6087	* @rmtoll CSR AWD1_MST LL_ADC_IsActiveFlag_MST_AWD1
EricLew	0:80ee8f3b695e	6088	* @param ADCxy_COMMON ADC common instance
EricLew	0:80ee8f3b695e	6089	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
EricLew	0:80ee8f3b695e	6090	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	6091	*/
EricLew	0:80ee8f3b695e	6092	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
EricLew	0:80ee8f3b695e	6093	{
EricLew	0:80ee8f3b695e	6094	return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_AWD1_MST) == (ADC_CSR_AWD1_MST));
EricLew	0:80ee8f3b695e	6095	}
EricLew	0:80ee8f3b695e	6096
EricLew	0:80ee8f3b695e	6097	/**
EricLew	0:80ee8f3b695e	6098	* @brief Get flag multimode analog watchdog 1 of the ADC slave.
EricLew	0:80ee8f3b695e	6099	* @rmtoll CSR AWD1_SLV LL_ADC_IsActiveFlag_SLV_AWD1
EricLew	0:80ee8f3b695e	6100	* @param ADCxy_COMMON ADC common instance
EricLew	0:80ee8f3b695e	6101	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
EricLew	0:80ee8f3b695e	6102	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	6103	*/
EricLew	0:80ee8f3b695e	6104	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
EricLew	0:80ee8f3b695e	6105	{
EricLew	0:80ee8f3b695e	6106	return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_AWD1_SLV) == (ADC_CSR_AWD1_SLV));
EricLew	0:80ee8f3b695e	6107	}
EricLew	0:80ee8f3b695e	6108
EricLew	0:80ee8f3b695e	6109	/**
EricLew	0:80ee8f3b695e	6110	* @brief Get flag multimode ADC analog watchdog 2 of the ADC master.
EricLew	0:80ee8f3b695e	6111	* @rmtoll CSR AWD2_MST LL_ADC_IsActiveFlag_MST_AWD2
EricLew	0:80ee8f3b695e	6112	* @param ADCxy_COMMON ADC common instance
EricLew	0:80ee8f3b695e	6113	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
EricLew	0:80ee8f3b695e	6114	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	6115	*/
EricLew	0:80ee8f3b695e	6116	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD2(ADC_Common_TypeDef *ADCxy_COMMON)
EricLew	0:80ee8f3b695e	6117	{
EricLew	0:80ee8f3b695e	6118	return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_AWD2_MST) == (ADC_CSR_AWD2_MST));
EricLew	0:80ee8f3b695e	6119	}
EricLew	0:80ee8f3b695e	6120
EricLew	0:80ee8f3b695e	6121	/**
EricLew	0:80ee8f3b695e	6122	* @brief Get flag multimode ADC analog watchdog 2 of the ADC slave.
EricLew	0:80ee8f3b695e	6123	* @rmtoll CSR AWD2_SLV LL_ADC_IsActiveFlag_SLV_AWD2
EricLew	0:80ee8f3b695e	6124	* @param ADCxy_COMMON ADC common instance
EricLew	0:80ee8f3b695e	6125	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
EricLew	0:80ee8f3b695e	6126	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	6127	*/
EricLew	0:80ee8f3b695e	6128	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD2(ADC_Common_TypeDef *ADCxy_COMMON)
EricLew	0:80ee8f3b695e	6129	{
EricLew	0:80ee8f3b695e	6130	return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_AWD2_SLV) == (ADC_CSR_AWD2_SLV));
EricLew	0:80ee8f3b695e	6131	}
EricLew	0:80ee8f3b695e	6132
EricLew	0:80ee8f3b695e	6133	/**
EricLew	0:80ee8f3b695e	6134	* @brief Get flag multimode ADC analog watchdog 3 of the ADC master.
EricLew	0:80ee8f3b695e	6135	* @rmtoll CSR AWD3_MST LL_ADC_IsActiveFlag_MST_AWD3
EricLew	0:80ee8f3b695e	6136	* @param ADCxy_COMMON ADC common instance
EricLew	0:80ee8f3b695e	6137	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
EricLew	0:80ee8f3b695e	6138	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	6139	*/
EricLew	0:80ee8f3b695e	6140	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD3(ADC_Common_TypeDef *ADCxy_COMMON)
EricLew	0:80ee8f3b695e	6141	{
EricLew	0:80ee8f3b695e	6142	return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_AWD3_MST) == (ADC_CSR_AWD3_MST));
EricLew	0:80ee8f3b695e	6143	}
EricLew	0:80ee8f3b695e	6144
EricLew	0:80ee8f3b695e	6145	/**
EricLew	0:80ee8f3b695e	6146	* @brief Get flag multimode ADC analog watchdog 3 of the ADC slave.
EricLew	0:80ee8f3b695e	6147	* @rmtoll CSR AWD3_SLV LL_ADC_IsActiveFlag_SLV_AWD3
EricLew	0:80ee8f3b695e	6148	* @param ADCxy_COMMON ADC common instance
EricLew	0:80ee8f3b695e	6149	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
EricLew	0:80ee8f3b695e	6150	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	6151	*/
EricLew	0:80ee8f3b695e	6152	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD3(ADC_Common_TypeDef *ADCxy_COMMON)
EricLew	0:80ee8f3b695e	6153	{
EricLew	0:80ee8f3b695e	6154	return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_AWD3_SLV) == (ADC_CSR_AWD3_SLV));
EricLew	0:80ee8f3b695e	6155	}
EricLew	0:80ee8f3b695e	6156	#endif /* ADC2 */
EricLew	0:80ee8f3b695e	6157
EricLew	0:80ee8f3b695e	6158	/**
EricLew	0:80ee8f3b695e	6159	* @}
EricLew	0:80ee8f3b695e	6160	*/
EricLew	0:80ee8f3b695e	6161
EricLew	0:80ee8f3b695e	6162	/** @defgroup ADC_LL_EF_IT_Management ADC IT management
EricLew	0:80ee8f3b695e	6163	* @{
EricLew	0:80ee8f3b695e	6164	*/
EricLew	0:80ee8f3b695e	6165
EricLew	0:80ee8f3b695e	6166	/**
EricLew	0:80ee8f3b695e	6167	* @brief Enable ADC ready.
EricLew	0:80ee8f3b695e	6168	* @rmtoll IER ADRDYIE LL_ADC_EnableIT_ADRDY
EricLew	0:80ee8f3b695e	6169	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	6170	* @retval None
EricLew	0:80ee8f3b695e	6171	*/
EricLew	0:80ee8f3b695e	6172	__STATIC_INLINE void LL_ADC_EnableIT_ADRDY(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	6173	{
EricLew	0:80ee8f3b695e	6174	SET_BIT(ADCx->IER, ADC_IER_ADRDY);
EricLew	0:80ee8f3b695e	6175	}
EricLew	0:80ee8f3b695e	6176
EricLew	0:80ee8f3b695e	6177	/**
EricLew	0:80ee8f3b695e	6178	* @brief Enable interruption ADC group regular end of unitary conversion.
EricLew	0:80ee8f3b695e	6179	* @rmtoll IER EOCIE LL_ADC_EnableIT_EOC
EricLew	0:80ee8f3b695e	6180	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	6181	* @retval None
EricLew	0:80ee8f3b695e	6182	*/
EricLew	0:80ee8f3b695e	6183	__STATIC_INLINE void LL_ADC_EnableIT_EOC(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	6184	{
EricLew	0:80ee8f3b695e	6185	SET_BIT(ADCx->IER, ADC_IER_EOC);
EricLew	0:80ee8f3b695e	6186	}
EricLew	0:80ee8f3b695e	6187
EricLew	0:80ee8f3b695e	6188	/**
EricLew	0:80ee8f3b695e	6189	* @brief Enable interruption ADC group regular end of sequence conversions.
EricLew	0:80ee8f3b695e	6190	* @rmtoll IER EOSIE LL_ADC_EnableIT_EOS
EricLew	0:80ee8f3b695e	6191	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	6192	* @retval None
EricLew	0:80ee8f3b695e	6193	*/
EricLew	0:80ee8f3b695e	6194	__STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	6195	{
EricLew	0:80ee8f3b695e	6196	SET_BIT(ADCx->IER, ADC_IER_EOS);
EricLew	0:80ee8f3b695e	6197	}
EricLew	0:80ee8f3b695e	6198
EricLew	0:80ee8f3b695e	6199	/**
EricLew	0:80ee8f3b695e	6200	* @brief Enable ADC group regular interruption overrun.
EricLew	0:80ee8f3b695e	6201	* @rmtoll IER OVRIE LL_ADC_EnableIT_OVR
EricLew	0:80ee8f3b695e	6202	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	6203	* @retval None
EricLew	0:80ee8f3b695e	6204	*/
EricLew	0:80ee8f3b695e	6205	__STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	6206	{
EricLew	0:80ee8f3b695e	6207	SET_BIT(ADCx->IER, ADC_IER_OVR);
EricLew	0:80ee8f3b695e	6208	}
EricLew	0:80ee8f3b695e	6209
EricLew	0:80ee8f3b695e	6210	/**
EricLew	0:80ee8f3b695e	6211	* @brief Enable interruption ADC group regular end of sampling.
EricLew	0:80ee8f3b695e	6212	* @rmtoll IER EOSMPIE LL_ADC_EnableIT_EOSMP
EricLew	0:80ee8f3b695e	6213	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	6214	* @retval None
EricLew	0:80ee8f3b695e	6215	*/
EricLew	0:80ee8f3b695e	6216	__STATIC_INLINE void LL_ADC_EnableIT_EOSMP(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	6217	{
EricLew	0:80ee8f3b695e	6218	SET_BIT(ADCx->IER, ADC_IER_EOSMP);
EricLew	0:80ee8f3b695e	6219	}
EricLew	0:80ee8f3b695e	6220
EricLew	0:80ee8f3b695e	6221	/**
EricLew	0:80ee8f3b695e	6222	* @brief Enable interruption ADC group injected end of unitary conversion.
EricLew	0:80ee8f3b695e	6223	* @rmtoll IER JEOCIE LL_ADC_EnableIT_JEOC
EricLew	0:80ee8f3b695e	6224	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	6225	* @retval None
EricLew	0:80ee8f3b695e	6226	*/
EricLew	0:80ee8f3b695e	6227	__STATIC_INLINE void LL_ADC_EnableIT_JEOC(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	6228	{
EricLew	0:80ee8f3b695e	6229	SET_BIT(ADCx->IER, ADC_IER_JEOC);
EricLew	0:80ee8f3b695e	6230	}
EricLew	0:80ee8f3b695e	6231
EricLew	0:80ee8f3b695e	6232	/**
EricLew	0:80ee8f3b695e	6233	* @brief Enable interruption ADC group injected end of sequence conversions.
EricLew	0:80ee8f3b695e	6234	* @rmtoll IER JEOSIE LL_ADC_EnableIT_JEOS
EricLew	0:80ee8f3b695e	6235	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	6236	* @retval None
EricLew	0:80ee8f3b695e	6237	*/
EricLew	0:80ee8f3b695e	6238	__STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	6239	{
EricLew	0:80ee8f3b695e	6240	SET_BIT(ADCx->IER, ADC_IER_JEOS);
EricLew	0:80ee8f3b695e	6241	}
EricLew	0:80ee8f3b695e	6242
EricLew	0:80ee8f3b695e	6243	/**
EricLew	0:80ee8f3b695e	6244	* @brief Enable interruption ADC group injected context queue overflow.
EricLew	0:80ee8f3b695e	6245	* @rmtoll IER JQOVFIE LL_ADC_EnableIT_JQOVF
EricLew	0:80ee8f3b695e	6246	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	6247	* @retval None
EricLew	0:80ee8f3b695e	6248	*/
EricLew	0:80ee8f3b695e	6249	__STATIC_INLINE void LL_ADC_EnableIT_JQOVF(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	6250	{
EricLew	0:80ee8f3b695e	6251	SET_BIT(ADCx->IER, ADC_IER_JQOVF);
EricLew	0:80ee8f3b695e	6252	}
EricLew	0:80ee8f3b695e	6253
EricLew	0:80ee8f3b695e	6254	/**
EricLew	0:80ee8f3b695e	6255	* @brief Enable interruption ADC analog watchdog 1.
EricLew	0:80ee8f3b695e	6256	* @rmtoll IER AWD1IE LL_ADC_EnableIT_AWD1
EricLew	0:80ee8f3b695e	6257	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	6258	* @retval None
EricLew	0:80ee8f3b695e	6259	*/
EricLew	0:80ee8f3b695e	6260	__STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	6261	{
EricLew	0:80ee8f3b695e	6262	SET_BIT(ADCx->IER, ADC_IER_AWD1);
EricLew	0:80ee8f3b695e	6263	}
EricLew	0:80ee8f3b695e	6264
EricLew	0:80ee8f3b695e	6265	/**
EricLew	0:80ee8f3b695e	6266	* @brief Enable interruption ADC analog watchdog 2.
EricLew	0:80ee8f3b695e	6267	* @rmtoll IER AWD2IE LL_ADC_EnableIT_AWD2
EricLew	0:80ee8f3b695e	6268	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	6269	* @retval None
EricLew	0:80ee8f3b695e	6270	*/
EricLew	0:80ee8f3b695e	6271	__STATIC_INLINE void LL_ADC_EnableIT_AWD2(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	6272	{
EricLew	0:80ee8f3b695e	6273	SET_BIT(ADCx->IER, ADC_IER_AWD2);
EricLew	0:80ee8f3b695e	6274	}
EricLew	0:80ee8f3b695e	6275
EricLew	0:80ee8f3b695e	6276	/**
EricLew	0:80ee8f3b695e	6277	* @brief Enable interruption ADC analog watchdog 3.
EricLew	0:80ee8f3b695e	6278	* @rmtoll IER AWD3IE LL_ADC_EnableIT_AWD3
EricLew	0:80ee8f3b695e	6279	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	6280	* @retval None
EricLew	0:80ee8f3b695e	6281	*/
EricLew	0:80ee8f3b695e	6282	__STATIC_INLINE void LL_ADC_EnableIT_AWD3(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	6283	{
EricLew	0:80ee8f3b695e	6284	SET_BIT(ADCx->IER, ADC_IER_AWD3);
EricLew	0:80ee8f3b695e	6285	}
EricLew	0:80ee8f3b695e	6286
EricLew	0:80ee8f3b695e	6287	/**
EricLew	0:80ee8f3b695e	6288	* @brief Disable interruption ADC ready.
EricLew	0:80ee8f3b695e	6289	* @rmtoll IER ADRDYIE LL_ADC_DisableIT_ADRDY
EricLew	0:80ee8f3b695e	6290	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	6291	* @retval None
EricLew	0:80ee8f3b695e	6292	*/
EricLew	0:80ee8f3b695e	6293	__STATIC_INLINE void LL_ADC_DisableIT_ADRDY(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	6294	{
EricLew	0:80ee8f3b695e	6295	CLEAR_BIT(ADCx->IER, ADC_IER_ADRDY);
EricLew	0:80ee8f3b695e	6296	}
EricLew	0:80ee8f3b695e	6297
EricLew	0:80ee8f3b695e	6298	/**
EricLew	0:80ee8f3b695e	6299	* @brief Disable interruption ADC group regular end of unitary conversion.
EricLew	0:80ee8f3b695e	6300	* @rmtoll IER EOCIE LL_ADC_DisableIT_EOC
EricLew	0:80ee8f3b695e	6301	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	6302	* @retval None
EricLew	0:80ee8f3b695e	6303	*/
EricLew	0:80ee8f3b695e	6304	__STATIC_INLINE void LL_ADC_DisableIT_EOC(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	6305	{
EricLew	0:80ee8f3b695e	6306	CLEAR_BIT(ADCx->IER, ADC_IER_EOC);
EricLew	0:80ee8f3b695e	6307	}
EricLew	0:80ee8f3b695e	6308
EricLew	0:80ee8f3b695e	6309	/**
EricLew	0:80ee8f3b695e	6310	* @brief Disable interruption ADC group regular end of sequence conversions.
EricLew	0:80ee8f3b695e	6311	* @rmtoll IER EOSIE LL_ADC_DisableIT_EOS
EricLew	0:80ee8f3b695e	6312	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	6313	* @retval None
EricLew	0:80ee8f3b695e	6314	*/
EricLew	0:80ee8f3b695e	6315	__STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	6316	{
EricLew	0:80ee8f3b695e	6317	CLEAR_BIT(ADCx->IER, ADC_IER_EOS);
EricLew	0:80ee8f3b695e	6318	}
EricLew	0:80ee8f3b695e	6319
EricLew	0:80ee8f3b695e	6320	/**
EricLew	0:80ee8f3b695e	6321	* @brief Disable interruption ADC group regular overrun.
EricLew	0:80ee8f3b695e	6322	* @rmtoll IER OVRIE LL_ADC_DisableIT_OVR
EricLew	0:80ee8f3b695e	6323	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	6324	* @retval None
EricLew	0:80ee8f3b695e	6325	*/
EricLew	0:80ee8f3b695e	6326	__STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	6327	{
EricLew	0:80ee8f3b695e	6328	CLEAR_BIT(ADCx->IER, ADC_IER_OVR);
EricLew	0:80ee8f3b695e	6329	}
EricLew	0:80ee8f3b695e	6330
EricLew	0:80ee8f3b695e	6331	/**
EricLew	0:80ee8f3b695e	6332	* @brief Disable interruption ADC group regular end of sampling.
EricLew	0:80ee8f3b695e	6333	* @rmtoll IER EOSMPIE LL_ADC_DisableIT_EOSMP
EricLew	0:80ee8f3b695e	6334	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	6335	* @retval None
EricLew	0:80ee8f3b695e	6336	*/
EricLew	0:80ee8f3b695e	6337	__STATIC_INLINE void LL_ADC_DisableIT_EOSMP(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	6338	{
EricLew	0:80ee8f3b695e	6339	CLEAR_BIT(ADCx->IER, ADC_IER_EOSMP);
EricLew	0:80ee8f3b695e	6340	}
EricLew	0:80ee8f3b695e	6341
EricLew	0:80ee8f3b695e	6342	/**
EricLew	0:80ee8f3b695e	6343	* @brief Disable interruption ADC group regular end of unitary conversion.
EricLew	0:80ee8f3b695e	6344	* @rmtoll IER JEOCIE LL_ADC_DisableIT_JEOC
EricLew	0:80ee8f3b695e	6345	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	6346	* @retval None
EricLew	0:80ee8f3b695e	6347	*/
EricLew	0:80ee8f3b695e	6348	__STATIC_INLINE void LL_ADC_DisableIT_JEOC(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	6349	{
EricLew	0:80ee8f3b695e	6350	CLEAR_BIT(ADCx->IER, ADC_IER_JEOC);
EricLew	0:80ee8f3b695e	6351	}
EricLew	0:80ee8f3b695e	6352
EricLew	0:80ee8f3b695e	6353	/**
EricLew	0:80ee8f3b695e	6354	* @brief Disable interruption ADC group injected end of sequence conversions.
EricLew	0:80ee8f3b695e	6355	* @rmtoll IER JEOSIE LL_ADC_DisableIT_JEOS
EricLew	0:80ee8f3b695e	6356	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	6357	* @retval None
EricLew	0:80ee8f3b695e	6358	*/
EricLew	0:80ee8f3b695e	6359	__STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	6360	{
EricLew	0:80ee8f3b695e	6361	CLEAR_BIT(ADCx->IER, ADC_IER_JEOS);
EricLew	0:80ee8f3b695e	6362	}
EricLew	0:80ee8f3b695e	6363
EricLew	0:80ee8f3b695e	6364	/**
EricLew	0:80ee8f3b695e	6365	* @brief Disable interruption ADC group injected context queue overflow.
EricLew	0:80ee8f3b695e	6366	* @rmtoll IER JQOVFIE LL_ADC_DisableIT_JQOVF
EricLew	0:80ee8f3b695e	6367	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	6368	* @retval None
EricLew	0:80ee8f3b695e	6369	*/
EricLew	0:80ee8f3b695e	6370	__STATIC_INLINE void LL_ADC_DisableIT_JQOVF(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	6371	{
EricLew	0:80ee8f3b695e	6372	CLEAR_BIT(ADCx->IER, ADC_IER_JQOVF);
EricLew	0:80ee8f3b695e	6373	}
EricLew	0:80ee8f3b695e	6374
EricLew	0:80ee8f3b695e	6375	/**
EricLew	0:80ee8f3b695e	6376	* @brief Disable interruption ADC analog watchdog 1.
EricLew	0:80ee8f3b695e	6377	* @rmtoll IER AWD1IE LL_ADC_DisableIT_AWD1
EricLew	0:80ee8f3b695e	6378	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	6379	* @retval None
EricLew	0:80ee8f3b695e	6380	*/
EricLew	0:80ee8f3b695e	6381	__STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	6382	{
EricLew	0:80ee8f3b695e	6383	CLEAR_BIT(ADCx->IER, ADC_IER_AWD1);
EricLew	0:80ee8f3b695e	6384	}
EricLew	0:80ee8f3b695e	6385
EricLew	0:80ee8f3b695e	6386	/**
EricLew	0:80ee8f3b695e	6387	* @brief Disable interruption ADC analog watchdog 2.
EricLew	0:80ee8f3b695e	6388	* @rmtoll IER AWD2IE LL_ADC_DisableIT_AWD2
EricLew	0:80ee8f3b695e	6389	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	6390	* @retval None
EricLew	0:80ee8f3b695e	6391	*/
EricLew	0:80ee8f3b695e	6392	__STATIC_INLINE void LL_ADC_DisableIT_AWD2(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	6393	{
EricLew	0:80ee8f3b695e	6394	CLEAR_BIT(ADCx->IER, ADC_IER_AWD2);
EricLew	0:80ee8f3b695e	6395	}
EricLew	0:80ee8f3b695e	6396
EricLew	0:80ee8f3b695e	6397	/**
EricLew	0:80ee8f3b695e	6398	* @brief Disable interruption ADC analog watchdog 3.
EricLew	0:80ee8f3b695e	6399	* @rmtoll IER AWD3IE LL_ADC_DisableIT_AWD3
EricLew	0:80ee8f3b695e	6400	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	6401	* @retval None
EricLew	0:80ee8f3b695e	6402	*/
EricLew	0:80ee8f3b695e	6403	__STATIC_INLINE void LL_ADC_DisableIT_AWD3(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	6404	{
EricLew	0:80ee8f3b695e	6405	CLEAR_BIT(ADCx->IER, ADC_IER_AWD3);
EricLew	0:80ee8f3b695e	6406	}
EricLew	0:80ee8f3b695e	6407
EricLew	0:80ee8f3b695e	6408	/**
EricLew	0:80ee8f3b695e	6409	* @brief Get state of interruption ADC ready.
EricLew	0:80ee8f3b695e	6410	* (0: interrupt disabled, 1: interrupt enabled)
EricLew	0:80ee8f3b695e	6411	* @rmtoll IER ADRDYIE LL_ADC_IsEnabledIT_ADRDY
EricLew	0:80ee8f3b695e	6412	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	6413	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	6414	*/
EricLew	0:80ee8f3b695e	6415	__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	6416	{
EricLew	0:80ee8f3b695e	6417	return (READ_BIT(ADCx->IER, ADC_IER_ADRDY) == (ADC_IER_ADRDY));
EricLew	0:80ee8f3b695e	6418	}
EricLew	0:80ee8f3b695e	6419
EricLew	0:80ee8f3b695e	6420	/**
EricLew	0:80ee8f3b695e	6421	* @brief Get state of interruption ADC group regular end of unitary conversion.
EricLew	0:80ee8f3b695e	6422	* (0: interrupt disabled, 1: interrupt enabled)
EricLew	0:80ee8f3b695e	6423	* @rmtoll IER EOCIE LL_ADC_IsEnabledIT_EOC
EricLew	0:80ee8f3b695e	6424	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	6425	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	6426	*/
EricLew	0:80ee8f3b695e	6427	__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	6428	{
EricLew	0:80ee8f3b695e	6429	return (READ_BIT(ADCx->IER, ADC_IER_EOC) == (ADC_IER_EOC));
EricLew	0:80ee8f3b695e	6430	}
EricLew	0:80ee8f3b695e	6431
EricLew	0:80ee8f3b695e	6432	/**
EricLew	0:80ee8f3b695e	6433	* @brief Get state of interruption ADC group regular end of sequence conversions.
EricLew	0:80ee8f3b695e	6434	* (0: interrupt disabled, 1: interrupt enabled)
EricLew	0:80ee8f3b695e	6435	* @rmtoll IER EOSIE LL_ADC_IsEnabledIT_EOS
EricLew	0:80ee8f3b695e	6436	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	6437	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	6438	*/
EricLew	0:80ee8f3b695e	6439	__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	6440	{
EricLew	0:80ee8f3b695e	6441	return (READ_BIT(ADCx->IER, ADC_IER_EOS) == (ADC_IER_EOS));
EricLew	0:80ee8f3b695e	6442	}
EricLew	0:80ee8f3b695e	6443
EricLew	0:80ee8f3b695e	6444	/**
EricLew	0:80ee8f3b695e	6445	* @brief Get state of interruption ADC group regular overrun.
EricLew	0:80ee8f3b695e	6446	* (0: interrupt disabled, 1: interrupt enabled)
EricLew	0:80ee8f3b695e	6447	* @rmtoll IER OVRIE LL_ADC_IsEnabledIT_OVR
EricLew	0:80ee8f3b695e	6448	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	6449	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	6450	*/
EricLew	0:80ee8f3b695e	6451	__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	6452	{
EricLew	0:80ee8f3b695e	6453	return (READ_BIT(ADCx->IER, ADC_IER_OVR) == (ADC_IER_OVR));
EricLew	0:80ee8f3b695e	6454	}
EricLew	0:80ee8f3b695e	6455
EricLew	0:80ee8f3b695e	6456	/**
EricLew	0:80ee8f3b695e	6457	* @brief Get state of interruption ADC group regular end of sampling.
EricLew	0:80ee8f3b695e	6458	* (0: interrupt disabled, 1: interrupt enabled)
EricLew	0:80ee8f3b695e	6459	* @rmtoll IER EOSMPIE LL_ADC_IsEnabledIT_EOSMP
EricLew	0:80ee8f3b695e	6460	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	6461	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	6462	*/
EricLew	0:80ee8f3b695e	6463	__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	6464	{
EricLew	0:80ee8f3b695e	6465	return (READ_BIT(ADCx->IER, ADC_IER_EOSMP) == (ADC_IER_EOSMP));
EricLew	0:80ee8f3b695e	6466	}
EricLew	0:80ee8f3b695e	6467
EricLew	0:80ee8f3b695e	6468	/**
EricLew	0:80ee8f3b695e	6469	* @brief Get state of interruption ADC group injected end of unitary conversion.
EricLew	0:80ee8f3b695e	6470	* (0: interrupt disabled, 1: interrupt enabled)
EricLew	0:80ee8f3b695e	6471	* @rmtoll IER JEOCIE LL_ADC_IsEnabledIT_JEOC
EricLew	0:80ee8f3b695e	6472	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	6473	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	6474	*/
EricLew	0:80ee8f3b695e	6475	__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	6476	{
EricLew	0:80ee8f3b695e	6477	return (READ_BIT(ADCx->IER, ADC_IER_JEOC) == (ADC_IER_JEOC));
EricLew	0:80ee8f3b695e	6478	}
EricLew	0:80ee8f3b695e	6479
EricLew	0:80ee8f3b695e	6480	/**
EricLew	0:80ee8f3b695e	6481	* @brief Get state of interruption ADC group injected end of sequence conversions.
EricLew	0:80ee8f3b695e	6482	* (0: interrupt disabled, 1: interrupt enabled)
EricLew	0:80ee8f3b695e	6483	* @rmtoll IER JEOSIE LL_ADC_IsEnabledIT_JEOS
EricLew	0:80ee8f3b695e	6484	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	6485	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	6486	*/
EricLew	0:80ee8f3b695e	6487	__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	6488	{
EricLew	0:80ee8f3b695e	6489	return (READ_BIT(ADCx->IER, ADC_IER_JEOS) == (ADC_IER_JEOS));
EricLew	0:80ee8f3b695e	6490	}
EricLew	0:80ee8f3b695e	6491
EricLew	0:80ee8f3b695e	6492	/**
EricLew	0:80ee8f3b695e	6493	* @brief Get state of interruption ADC group injected context queue overflow interrupt state
EricLew	0:80ee8f3b695e	6494	* (0: interrupt disabled, 1: interrupt enabled)
EricLew	0:80ee8f3b695e	6495	* @rmtoll IER JQOVFIE LL_ADC_IsEnabledIT_JQOVF
EricLew	0:80ee8f3b695e	6496	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	6497	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	6498	*/
EricLew	0:80ee8f3b695e	6499	__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JQOVF(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	6500	{
EricLew	0:80ee8f3b695e	6501	return (READ_BIT(ADCx->IER, ADC_IER_JQOVF) == (ADC_IER_JQOVF));
EricLew	0:80ee8f3b695e	6502	}
EricLew	0:80ee8f3b695e	6503
EricLew	0:80ee8f3b695e	6504	/**
EricLew	0:80ee8f3b695e	6505	* @brief Get state of interruption ADC analog watchdog 1.
EricLew	0:80ee8f3b695e	6506	* (0: interrupt disabled, 1: interrupt enabled)
EricLew	0:80ee8f3b695e	6507	* @rmtoll IER AWD1IE LL_ADC_IsEnabledIT_AWD1
EricLew	0:80ee8f3b695e	6508	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	6509	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	6510	*/
EricLew	0:80ee8f3b695e	6511	__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	6512	{
EricLew	0:80ee8f3b695e	6513	return (READ_BIT(ADCx->IER, ADC_IER_AWD1) == (ADC_IER_AWD1));
EricLew	0:80ee8f3b695e	6514	}
EricLew	0:80ee8f3b695e	6515
EricLew	0:80ee8f3b695e	6516	/**
EricLew	0:80ee8f3b695e	6517	* @brief Get state of interruption Get ADC analog watchdog 2.
EricLew	0:80ee8f3b695e	6518	* (0: interrupt disabled, 1: interrupt enabled)
EricLew	0:80ee8f3b695e	6519	* @rmtoll IER AWD2IE LL_ADC_IsEnabledIT_AWD2
EricLew	0:80ee8f3b695e	6520	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	6521	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	6522	*/
EricLew	0:80ee8f3b695e	6523	__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	6524	{
EricLew	0:80ee8f3b695e	6525	return (READ_BIT(ADCx->IER, ADC_IER_AWD2) == (ADC_IER_AWD2));
EricLew	0:80ee8f3b695e	6526	}
EricLew	0:80ee8f3b695e	6527
EricLew	0:80ee8f3b695e	6528	/**
EricLew	0:80ee8f3b695e	6529	* @brief Get state of interruption Get ADC analog watchdog 3.
EricLew	0:80ee8f3b695e	6530	* (0: interrupt disabled, 1: interrupt enabled)
EricLew	0:80ee8f3b695e	6531	* @rmtoll IER AWD3IE LL_ADC_IsEnabledIT_AWD3
EricLew	0:80ee8f3b695e	6532	* @param ADCx ADC instance
EricLew	0:80ee8f3b695e	6533	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	6534	*/
EricLew	0:80ee8f3b695e	6535	__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(ADC_TypeDef *ADCx)
EricLew	0:80ee8f3b695e	6536	{
EricLew	0:80ee8f3b695e	6537	return (READ_BIT(ADCx->IER, ADC_IER_AWD3) == (ADC_IER_AWD3));
EricLew	0:80ee8f3b695e	6538	}
EricLew	0:80ee8f3b695e	6539
EricLew	0:80ee8f3b695e	6540	/**
EricLew	0:80ee8f3b695e	6541	* @}
EricLew	0:80ee8f3b695e	6542	*/
EricLew	0:80ee8f3b695e	6543
EricLew	0:80ee8f3b695e	6544
EricLew	0:80ee8f3b695e	6545	/**
EricLew	0:80ee8f3b695e	6546	* @}
EricLew	0:80ee8f3b695e	6547	*/
EricLew	0:80ee8f3b695e	6548
EricLew	0:80ee8f3b695e	6549	/**
EricLew	0:80ee8f3b695e	6550	* @}
EricLew	0:80ee8f3b695e	6551	*/
EricLew	0:80ee8f3b695e	6552
EricLew	0:80ee8f3b695e	6553	#endif /* ADC1 \|\| ADC2 \|\| ADC3 */
EricLew	0:80ee8f3b695e	6554
EricLew	0:80ee8f3b695e	6555	/**
EricLew	0:80ee8f3b695e	6556	* @}
EricLew	0:80ee8f3b695e	6557	*/
EricLew	0:80ee8f3b695e	6558
EricLew	0:80ee8f3b695e	6559	#ifdef __cplusplus
EricLew	0:80ee8f3b695e	6560	}
EricLew	0:80ee8f3b695e	6561	#endif
EricLew	0:80ee8f3b695e	6562
EricLew	0:80ee8f3b695e	6563	#endif /* __STM32L4xx_LL_ADC_H */
EricLew	0:80ee8f3b695e	6564
EricLew	0:80ee8f3b695e	6565	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
EricLew	0:80ee8f3b695e	6566

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Type:	Library
Created:	12 Nov 2015
Imports:	198
Forks:	0
Commits:	3
Dependents:	4
Dependencies:	0
Followers:	14

Inc/stm32l4xx_ll_adc.h@2:7aef7655b0a8, 2015-11-25 (annotated)

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