Eric Lewiston / STM32L4xx_HAL_Driver

Hal Drivers for L4

Dependents:   BSP OneHopeOnePrayer FINAL_AUDIO_RECORD AudioDemo

Fork of STM32L4xx_HAL_Driver by Senior Design: Sound Monitor

Inc/stm32l4xx_hal_sram.h@2:7aef7655b0a8, 2015-11-25 (annotated)

Committer:
EricLew
Date:
Wed Nov 25 17:30:43 2015 +0000
Revision:
2:7aef7655b0a8
Parent:
0:80ee8f3b695e 
commit;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
EricLew 0:80ee8f3b695e 1 /**
EricLew 0:80ee8f3b695e 2 ******************************************************************************
EricLew 0:80ee8f3b695e 3 * @file stm32l4xx_hal_sram.h
EricLew 0:80ee8f3b695e 4 * @author MCD Application Team
EricLew 0:80ee8f3b695e 5 * @version V1.1.0
EricLew 0:80ee8f3b695e 6 * @date 16-September-2015
EricLew 0:80ee8f3b695e 7 * @brief Header file of SRAM HAL module.
EricLew 0:80ee8f3b695e 8 ******************************************************************************
EricLew 0:80ee8f3b695e 9 * @attention
EricLew 0:80ee8f3b695e 10 *
EricLew 0:80ee8f3b695e 11 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
EricLew 0:80ee8f3b695e 12 *
EricLew 0:80ee8f3b695e 13 * Redistribution and use in source and binary forms, with or without modification,
EricLew 0:80ee8f3b695e 14 * are permitted provided that the following conditions are met:
EricLew 0:80ee8f3b695e 15 * 1. Redistributions of source code must retain the above copyright notice,
EricLew 0:80ee8f3b695e 16 * this list of conditions and the following disclaimer.
EricLew 0:80ee8f3b695e 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
EricLew 0:80ee8f3b695e 18 * this list of conditions and the following disclaimer in the documentation
EricLew 0:80ee8f3b695e 19 * and/or other materials provided with the distribution.
EricLew 0:80ee8f3b695e 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
EricLew 0:80ee8f3b695e 21 * may be used to endorse or promote products derived from this software
EricLew 0:80ee8f3b695e 22 * without specific prior written permission.
EricLew 0:80ee8f3b695e 23 *
EricLew 0:80ee8f3b695e 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
EricLew 0:80ee8f3b695e 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
EricLew 0:80ee8f3b695e 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
EricLew 0:80ee8f3b695e 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
EricLew 0:80ee8f3b695e 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
EricLew 0:80ee8f3b695e 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
EricLew 0:80ee8f3b695e 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
EricLew 0:80ee8f3b695e 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
EricLew 0:80ee8f3b695e 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
EricLew 0:80ee8f3b695e 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
EricLew 0:80ee8f3b695e 34 *
EricLew 0:80ee8f3b695e 35 ******************************************************************************
EricLew 0:80ee8f3b695e 36 */
EricLew 0:80ee8f3b695e 37
EricLew 0:80ee8f3b695e 38 /* Define to prevent recursive inclusion -------------------------------------*/
EricLew 0:80ee8f3b695e 39 #ifndef __STM32L4xx_HAL_SRAM_H
EricLew 0:80ee8f3b695e 40 #define __STM32L4xx_HAL_SRAM_H
EricLew 0:80ee8f3b695e 41
EricLew 0:80ee8f3b695e 42 #ifdef __cplusplus
EricLew 0:80ee8f3b695e 43 extern "C" {
EricLew 0:80ee8f3b695e 44 #endif
EricLew 0:80ee8f3b695e 45
EricLew 0:80ee8f3b695e 46 /* Includes ------------------------------------------------------------------*/
EricLew 0:80ee8f3b695e 47 #include "stm32l4xx_ll_fmc.h"
EricLew 0:80ee8f3b695e 48
EricLew 0:80ee8f3b695e 49 /** @addtogroup STM32L4xx_HAL_Driver
EricLew 0:80ee8f3b695e 50 * @{
EricLew 0:80ee8f3b695e 51 */
EricLew 0:80ee8f3b695e 52
EricLew 0:80ee8f3b695e 53 /** @addtogroup SRAM
EricLew 0:80ee8f3b695e 54 * @{
EricLew 0:80ee8f3b695e 55 */
EricLew 0:80ee8f3b695e 56
EricLew 0:80ee8f3b695e 57 /* Exported typedef ----------------------------------------------------------*/
EricLew 0:80ee8f3b695e 58
EricLew 0:80ee8f3b695e 59 /** @defgroup SRAM_Exported_Types SRAM Exported Types
EricLew 0:80ee8f3b695e 60 * @{
EricLew 0:80ee8f3b695e 61 */
EricLew 0:80ee8f3b695e 62 /**
EricLew 0:80ee8f3b695e 63 * @brief HAL SRAM State structures definition
EricLew 0:80ee8f3b695e 64 */
EricLew 0:80ee8f3b695e 65 typedef enum
EricLew 0:80ee8f3b695e 66 {
EricLew 0:80ee8f3b695e 67 HAL_SRAM_STATE_RESET = 0x00, /*!< SRAM not yet initialized or disabled */
EricLew 0:80ee8f3b695e 68 HAL_SRAM_STATE_READY = 0x01, /*!< SRAM initialized and ready for use */
EricLew 0:80ee8f3b695e 69 HAL_SRAM_STATE_BUSY = 0x02, /*!< SRAM internal process is ongoing */
EricLew 0:80ee8f3b695e 70 HAL_SRAM_STATE_ERROR = 0x03, /*!< SRAM error state */
EricLew 0:80ee8f3b695e 71 HAL_SRAM_STATE_PROTECTED = 0x04 /*!< SRAM peripheral NORSRAM device write protected */
EricLew 0:80ee8f3b695e 72
EricLew 0:80ee8f3b695e 73 }HAL_SRAM_StateTypeDef;
EricLew 0:80ee8f3b695e 74
EricLew 0:80ee8f3b695e 75 /**
EricLew 0:80ee8f3b695e 76 * @brief SRAM handle Structure definition
EricLew 0:80ee8f3b695e 77 */
EricLew 0:80ee8f3b695e 78 typedef struct
EricLew 0:80ee8f3b695e 79 {
EricLew 0:80ee8f3b695e 80 FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */
EricLew 0:80ee8f3b695e 81
EricLew 0:80ee8f3b695e 82 FMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */
EricLew 0:80ee8f3b695e 83
EricLew 0:80ee8f3b695e 84 FMC_NORSRAM_InitTypeDef Init; /*!< SRAM device control configuration parameters */
EricLew 0:80ee8f3b695e 85
EricLew 0:80ee8f3b695e 86 HAL_LockTypeDef Lock; /*!< SRAM locking object */
EricLew 0:80ee8f3b695e 87
EricLew 0:80ee8f3b695e 88 __IO HAL_SRAM_StateTypeDef State; /*!< SRAM device access state */
EricLew 0:80ee8f3b695e 89
EricLew 0:80ee8f3b695e 90 DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */
EricLew 0:80ee8f3b695e 91
EricLew 0:80ee8f3b695e 92 }SRAM_HandleTypeDef;
EricLew 0:80ee8f3b695e 93
EricLew 0:80ee8f3b695e 94 /**
EricLew 0:80ee8f3b695e 95 * @}
EricLew 0:80ee8f3b695e 96 */
EricLew 0:80ee8f3b695e 97
EricLew 0:80ee8f3b695e 98 /* Exported constants --------------------------------------------------------*/
EricLew 0:80ee8f3b695e 99 /* Exported macro ------------------------------------------------------------*/
EricLew 0:80ee8f3b695e 100
EricLew 0:80ee8f3b695e 101 /** @defgroup SRAM_Exported_Macros SRAM Exported Macros
EricLew 0:80ee8f3b695e 102 * @{
EricLew 0:80ee8f3b695e 103 */
EricLew 0:80ee8f3b695e 104
EricLew 0:80ee8f3b695e 105 /** @brief Reset SRAM handle state.
EricLew 0:80ee8f3b695e 106 * @param __HANDLE__: SRAM handle
EricLew 0:80ee8f3b695e 107 * @retval None
EricLew 0:80ee8f3b695e 108 */
EricLew 0:80ee8f3b695e 109 #define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET)
EricLew 0:80ee8f3b695e 110
EricLew 0:80ee8f3b695e 111 /**
EricLew 0:80ee8f3b695e 112 * @}
EricLew 0:80ee8f3b695e 113 */
EricLew 0:80ee8f3b695e 114
EricLew 0:80ee8f3b695e 115 /* Exported functions --------------------------------------------------------*/
EricLew 0:80ee8f3b695e 116 /** @addtogroup SRAM_Exported_Functions SRAM Exported Functions
EricLew 0:80ee8f3b695e 117 * @{
EricLew 0:80ee8f3b695e 118 */
EricLew 0:80ee8f3b695e 119
EricLew 0:80ee8f3b695e 120 /** @addtogroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
EricLew 0:80ee8f3b695e 121 * @{
EricLew 0:80ee8f3b695e 122 */
EricLew 0:80ee8f3b695e 123
EricLew 0:80ee8f3b695e 124 /* Initialization/de-initialization functions ********************************/
EricLew 0:80ee8f3b695e 125 HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);
EricLew 0:80ee8f3b695e 126 HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram);
EricLew 0:80ee8f3b695e 127 void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram);
EricLew 0:80ee8f3b695e 128 void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram);
EricLew 0:80ee8f3b695e 129
EricLew 0:80ee8f3b695e 130 void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
EricLew 0:80ee8f3b695e 131 void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
EricLew 0:80ee8f3b695e 132
EricLew 0:80ee8f3b695e 133 /**
EricLew 0:80ee8f3b695e 134 * @}
EricLew 0:80ee8f3b695e 135 */
EricLew 0:80ee8f3b695e 136
EricLew 0:80ee8f3b695e 137 /** @addtogroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
EricLew 0:80ee8f3b695e 138 * @{
EricLew 0:80ee8f3b695e 139 */
EricLew 0:80ee8f3b695e 140
EricLew 0:80ee8f3b695e 141 /* I/O operation functions ***************************************************/
EricLew 0:80ee8f3b695e 142 HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize);
EricLew 0:80ee8f3b695e 143 HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize);
EricLew 0:80ee8f3b695e 144 HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize);
EricLew 0:80ee8f3b695e 145 HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize);
EricLew 0:80ee8f3b695e 146 HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
EricLew 0:80ee8f3b695e 147 HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
EricLew 0:80ee8f3b695e 148 HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
EricLew 0:80ee8f3b695e 149 HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
EricLew 0:80ee8f3b695e 150
EricLew 0:80ee8f3b695e 151 /**
EricLew 0:80ee8f3b695e 152 * @}
EricLew 0:80ee8f3b695e 153 */
EricLew 0:80ee8f3b695e 154
EricLew 0:80ee8f3b695e 155 /** @addtogroup SRAM_Exported_Functions_Group3 Control functions
EricLew 0:80ee8f3b695e 156 * @{
EricLew 0:80ee8f3b695e 157 */
EricLew 0:80ee8f3b695e 158
EricLew 0:80ee8f3b695e 159 /* SRAM Control functions ****************************************************/
EricLew 0:80ee8f3b695e 160 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram);
EricLew 0:80ee8f3b695e 161 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram);
EricLew 0:80ee8f3b695e 162
EricLew 0:80ee8f3b695e 163 /**
EricLew 0:80ee8f3b695e 164 * @}
EricLew 0:80ee8f3b695e 165 */
EricLew 0:80ee8f3b695e 166
EricLew 0:80ee8f3b695e 167 /** @addtogroup SRAM_Exported_Functions_Group4 Peripheral State functions
EricLew 0:80ee8f3b695e 168 * @{
EricLew 0:80ee8f3b695e 169 */
EricLew 0:80ee8f3b695e 170
EricLew 0:80ee8f3b695e 171 /* SRAM Peripheral State functions ********************************************/
EricLew 0:80ee8f3b695e 172 HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram);
EricLew 0:80ee8f3b695e 173
EricLew 0:80ee8f3b695e 174 /**
EricLew 0:80ee8f3b695e 175 * @}
EricLew 0:80ee8f3b695e 176 */
EricLew 0:80ee8f3b695e 177
EricLew 0:80ee8f3b695e 178 /**
EricLew 0:80ee8f3b695e 179 * @}
EricLew 0:80ee8f3b695e 180 */
EricLew 0:80ee8f3b695e 181
EricLew 0:80ee8f3b695e 182 /**
EricLew 0:80ee8f3b695e 183 * @}
EricLew 0:80ee8f3b695e 184 */
EricLew 0:80ee8f3b695e 185
EricLew 0:80ee8f3b695e 186 /**
EricLew 0:80ee8f3b695e 187 * @}
EricLew 0:80ee8f3b695e 188 */
EricLew 0:80ee8f3b695e 189
EricLew 0:80ee8f3b695e 190 #ifdef __cplusplus
EricLew 0:80ee8f3b695e 191 }
EricLew 0:80ee8f3b695e 192 #endif
EricLew 0:80ee8f3b695e 193
EricLew 0:80ee8f3b695e 194 #endif /* __STM32L4xx_HAL_SRAM_H */
EricLew 0:80ee8f3b695e 195
EricLew 0:80ee8f3b695e 196 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
EricLew 0:80ee8f3b695e 197