STM32L4xx_HAL_Driver - Hal Drivers for L4

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Hal Drivers for L4

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Inc/stm32l4xx_hal_rcc.h@2:7aef7655b0a8, 2015-11-25 (annotated)

Committer:: EricLew
Date:: Wed Nov 25 17:30:43 2015 +0000
Revision:: 2:7aef7655b0a8
Parent:: 0:80ee8f3b695e

commit;

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User	Revision	Line number	New contents of line
EricLew	0:80ee8f3b695e	1	/**
EricLew	0:80ee8f3b695e	2	******************************************************************************
EricLew	0:80ee8f3b695e	3	* @file stm32l4xx_hal_rcc.h
EricLew	0:80ee8f3b695e	4	* @author MCD Application Team
EricLew	0:80ee8f3b695e	5	* @version V1.1.0
EricLew	0:80ee8f3b695e	6	* @date 16-September-2015
EricLew	0:80ee8f3b695e	7	* @brief Header file of RCC HAL module.
EricLew	0:80ee8f3b695e	8	******************************************************************************
EricLew	0:80ee8f3b695e	9	* @attention
EricLew	0:80ee8f3b695e	10	*
EricLew	0:80ee8f3b695e	11	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
EricLew	0:80ee8f3b695e	12	*
EricLew	0:80ee8f3b695e	13	* Redistribution and use in source and binary forms, with or without modification,
EricLew	0:80ee8f3b695e	14	* are permitted provided that the following conditions are met:
EricLew	0:80ee8f3b695e	15	* 1. Redistributions of source code must retain the above copyright notice,
EricLew	0:80ee8f3b695e	16	* this list of conditions and the following disclaimer.
EricLew	0:80ee8f3b695e	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
EricLew	0:80ee8f3b695e	18	* this list of conditions and the following disclaimer in the documentation
EricLew	0:80ee8f3b695e	19	* and/or other materials provided with the distribution.
EricLew	0:80ee8f3b695e	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
EricLew	0:80ee8f3b695e	21	* may be used to endorse or promote products derived from this software
EricLew	0:80ee8f3b695e	22	* without specific prior written permission.
EricLew	0:80ee8f3b695e	23	*
EricLew	0:80ee8f3b695e	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
EricLew	0:80ee8f3b695e	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
EricLew	0:80ee8f3b695e	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
EricLew	0:80ee8f3b695e	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
EricLew	0:80ee8f3b695e	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
EricLew	0:80ee8f3b695e	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
EricLew	0:80ee8f3b695e	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
EricLew	0:80ee8f3b695e	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
EricLew	0:80ee8f3b695e	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
EricLew	0:80ee8f3b695e	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
EricLew	0:80ee8f3b695e	34	*
EricLew	0:80ee8f3b695e	35	******************************************************************************
EricLew	0:80ee8f3b695e	36	*/
EricLew	0:80ee8f3b695e	37
EricLew	0:80ee8f3b695e	38	/* Define to prevent recursive inclusion -------------------------------------*/
EricLew	0:80ee8f3b695e	39	#ifndef __STM32L4xx_HAL_RCC_H
EricLew	0:80ee8f3b695e	40	#define __STM32L4xx_HAL_RCC_H
EricLew	0:80ee8f3b695e	41
EricLew	0:80ee8f3b695e	42	#ifdef __cplusplus
EricLew	0:80ee8f3b695e	43	extern "C" {
EricLew	0:80ee8f3b695e	44	#endif
EricLew	0:80ee8f3b695e	45
EricLew	0:80ee8f3b695e	46	/* Includes ------------------------------------------------------------------*/
EricLew	0:80ee8f3b695e	47	#include "stm32l4xx_hal_def.h"
EricLew	0:80ee8f3b695e	48
EricLew	0:80ee8f3b695e	49	/** @addtogroup STM32L4xx_HAL_Driver
EricLew	0:80ee8f3b695e	50	* @{
EricLew	0:80ee8f3b695e	51	*/
EricLew	0:80ee8f3b695e	52
EricLew	0:80ee8f3b695e	53	/** @addtogroup RCC
EricLew	0:80ee8f3b695e	54	* @{
EricLew	0:80ee8f3b695e	55	*/
EricLew	0:80ee8f3b695e	56
EricLew	0:80ee8f3b695e	57	/* Exported types ------------------------------------------------------------*/
EricLew	0:80ee8f3b695e	58	/** @defgroup RCC_Exported_Types RCC Exported Types
EricLew	0:80ee8f3b695e	59	* @{
EricLew	0:80ee8f3b695e	60	*/
EricLew	0:80ee8f3b695e	61
EricLew	0:80ee8f3b695e	62	/**
EricLew	0:80ee8f3b695e	63	* @brief RCC PLL configuration structure definition
EricLew	0:80ee8f3b695e	64	*/
EricLew	0:80ee8f3b695e	65	typedef struct
EricLew	0:80ee8f3b695e	66	{
EricLew	0:80ee8f3b695e	67	uint32_t PLLState; /*!< The new state of the PLL.
EricLew	0:80ee8f3b695e	68	This parameter can be a value of @ref RCC_PLL_Config */
EricLew	0:80ee8f3b695e	69
EricLew	0:80ee8f3b695e	70	uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.
EricLew	0:80ee8f3b695e	71	This parameter must be a value of @ref RCC_PLL_Clock_Source */
EricLew	0:80ee8f3b695e	72
EricLew	0:80ee8f3b695e	73	uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock.
EricLew	0:80ee8f3b695e	74	This parameter must be a number between Min_Data = 0 and Max_Data = 8 */
EricLew	0:80ee8f3b695e	75
EricLew	0:80ee8f3b695e	76	uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock.
EricLew	0:80ee8f3b695e	77	This parameter must be a number between Min_Data = 8 and Max_Data = 86 */
EricLew	0:80ee8f3b695e	78
EricLew	0:80ee8f3b695e	79	uint32_t PLLP; /*!< PLLP: Division factor for SAI clock.
EricLew	0:80ee8f3b695e	80	This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
EricLew	0:80ee8f3b695e	81
EricLew	0:80ee8f3b695e	82	uint32_t PLLQ; /*!< PLLQ: Division factor for SDMMC1, RNG and USB clocks.
EricLew	0:80ee8f3b695e	83	This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */
EricLew	0:80ee8f3b695e	84
EricLew	0:80ee8f3b695e	85	uint32_t PLLR; /*!< PLLR: Division for the main system clock.
EricLew	0:80ee8f3b695e	86	User have to set the PLLR parameter correctly to not exceed max frequency 80MHZ.
EricLew	0:80ee8f3b695e	87	This parameter must be a value of @ref RCC_PLLR_Clock_Divider */
EricLew	0:80ee8f3b695e	88
EricLew	0:80ee8f3b695e	89	}RCC_PLLInitTypeDef;
EricLew	0:80ee8f3b695e	90
EricLew	0:80ee8f3b695e	91	/**
EricLew	0:80ee8f3b695e	92	* @brief RCC Internal/External Oscillator (HSE, HSI, MSI, LSE and LSI) configuration structure definition
EricLew	0:80ee8f3b695e	93	*/
EricLew	0:80ee8f3b695e	94	typedef struct
EricLew	0:80ee8f3b695e	95	{
EricLew	0:80ee8f3b695e	96	uint32_t OscillatorType; /*!< The oscillators to be configured.
EricLew	0:80ee8f3b695e	97	This parameter can be a value of @ref RCC_Oscillator_Type */
EricLew	0:80ee8f3b695e	98
EricLew	0:80ee8f3b695e	99	uint32_t HSEState; /*!< The new state of the HSE.
EricLew	0:80ee8f3b695e	100	This parameter can be a value of @ref RCC_HSE_Config */
EricLew	0:80ee8f3b695e	101
EricLew	0:80ee8f3b695e	102	uint32_t LSEState; /*!< The new state of the LSE.
EricLew	0:80ee8f3b695e	103	This parameter can be a value of @ref RCC_LSE_Config */
EricLew	0:80ee8f3b695e	104
EricLew	0:80ee8f3b695e	105	uint32_t HSIState; /*!< The new state of the HSI.
EricLew	0:80ee8f3b695e	106	This parameter can be a value of @ref RCC_HSI_Config */
EricLew	0:80ee8f3b695e	107
EricLew	0:80ee8f3b695e	108	uint32_t HSICalibrationValue; /*!< The calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
EricLew	0:80ee8f3b695e	109	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
EricLew	0:80ee8f3b695e	110
EricLew	0:80ee8f3b695e	111	uint32_t LSIState; /*!< The new state of the LSI.
EricLew	0:80ee8f3b695e	112	This parameter can be a value of @ref RCC_LSI_Config */
EricLew	0:80ee8f3b695e	113
EricLew	0:80ee8f3b695e	114	uint32_t MSIState; /*!< The new state of the MSI.
EricLew	0:80ee8f3b695e	115	This parameter can be a value of @ref RCC_MSI_Config */
EricLew	0:80ee8f3b695e	116
EricLew	0:80ee8f3b695e	117	uint32_t MSICalibrationValue; /*!< The calibration trimming value (default is RCC_MSICALIBRATION_DEFAULT).
EricLew	0:80ee8f3b695e	118	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
EricLew	0:80ee8f3b695e	119
EricLew	0:80ee8f3b695e	120	uint32_t MSIClockRange; /*!< The MSI frequency range.
EricLew	0:80ee8f3b695e	121	This parameter can be a value of @ref RCC_MSI_Clock_Range */
EricLew	0:80ee8f3b695e	122
EricLew	0:80ee8f3b695e	123	RCC_PLLInitTypeDef PLL; /!< Main PLL structure parameters /
EricLew	0:80ee8f3b695e	124
EricLew	0:80ee8f3b695e	125	}RCC_OscInitTypeDef;
EricLew	0:80ee8f3b695e	126
EricLew	0:80ee8f3b695e	127	/**
EricLew	0:80ee8f3b695e	128	* @brief RCC System, AHB and APB busses clock configuration structure definition
EricLew	0:80ee8f3b695e	129	*/
EricLew	0:80ee8f3b695e	130	typedef struct
EricLew	0:80ee8f3b695e	131	{
EricLew	0:80ee8f3b695e	132	uint32_t ClockType; /*!< The clock to be configured.
EricLew	0:80ee8f3b695e	133	This parameter can be a value of @ref RCC_System_Clock_Type */
EricLew	0:80ee8f3b695e	134
EricLew	0:80ee8f3b695e	135	uint32_t SYSCLKSource; /*!< The clock source used as system clock (SYSCLK).
EricLew	0:80ee8f3b695e	136	This parameter can be a value of @ref RCC_System_Clock_Source */
EricLew	0:80ee8f3b695e	137
EricLew	0:80ee8f3b695e	138	uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
EricLew	0:80ee8f3b695e	139	This parameter can be a value of @ref RCC_AHB_Clock_Source */
EricLew	0:80ee8f3b695e	140
EricLew	0:80ee8f3b695e	141	uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
EricLew	0:80ee8f3b695e	142	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
EricLew	0:80ee8f3b695e	143
EricLew	0:80ee8f3b695e	144	uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
EricLew	0:80ee8f3b695e	145	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
EricLew	0:80ee8f3b695e	146
EricLew	0:80ee8f3b695e	147	}RCC_ClkInitTypeDef;
EricLew	0:80ee8f3b695e	148
EricLew	0:80ee8f3b695e	149	/**
EricLew	0:80ee8f3b695e	150	* @}
EricLew	0:80ee8f3b695e	151	*/
EricLew	0:80ee8f3b695e	152
EricLew	0:80ee8f3b695e	153	/* Exported constants --------------------------------------------------------*/
EricLew	0:80ee8f3b695e	154	/** @defgroup RCC_Exported_Constants RCC Exported Constants
EricLew	0:80ee8f3b695e	155	* @{
EricLew	0:80ee8f3b695e	156	*/
EricLew	0:80ee8f3b695e	157
EricLew	0:80ee8f3b695e	158	/** @defgroup RCC_Timeout_Value Timeout Values
EricLew	0:80ee8f3b695e	159	* @{
EricLew	0:80ee8f3b695e	160	*/
EricLew	0:80ee8f3b695e	161	#define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100)
EricLew	0:80ee8f3b695e	162	#define RCC_LSE_TIMEOUT_VALUE ((uint32_t)5000)
EricLew	0:80ee8f3b695e	163	/**
EricLew	0:80ee8f3b695e	164	* @}
EricLew	0:80ee8f3b695e	165	*/
EricLew	0:80ee8f3b695e	166
EricLew	0:80ee8f3b695e	167	/** @defgroup RCC_Oscillator_Type Oscillator Type
EricLew	0:80ee8f3b695e	168	* @{
EricLew	0:80ee8f3b695e	169	*/
EricLew	0:80ee8f3b695e	170	#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000) /!< Oscillator configuration unchanged /
EricLew	0:80ee8f3b695e	171	#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001) /!< HSE to configure /
EricLew	0:80ee8f3b695e	172	#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002) /!< HSI to configure /
EricLew	0:80ee8f3b695e	173	#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004) /!< LSE to configure /
EricLew	0:80ee8f3b695e	174	#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008) /!< LSI to configure /
EricLew	0:80ee8f3b695e	175	#define RCC_OSCILLATORTYPE_MSI ((uint32_t)0x00000010) /!< MSI to configure /
EricLew	0:80ee8f3b695e	176	/**
EricLew	0:80ee8f3b695e	177	* @}
EricLew	0:80ee8f3b695e	178	*/
EricLew	0:80ee8f3b695e	179
EricLew	0:80ee8f3b695e	180	/** @defgroup RCC_HSE_Config HSE Config
EricLew	0:80ee8f3b695e	181	* @{
EricLew	0:80ee8f3b695e	182	*/
EricLew	0:80ee8f3b695e	183	#define RCC_HSE_OFF ((uint32_t)0x00000000) /!< HSE clock deactivation /
EricLew	0:80ee8f3b695e	184	#define RCC_HSE_ON RCC_CR_HSEON /!< HSE clock activation /
EricLew	0:80ee8f3b695e	185	#define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP \| RCC_CR_HSEON)) /!< External clock source for HSE clock /
EricLew	0:80ee8f3b695e	186	/**
EricLew	0:80ee8f3b695e	187	* @}
EricLew	0:80ee8f3b695e	188	*/
EricLew	0:80ee8f3b695e	189
EricLew	0:80ee8f3b695e	190	/** @defgroup RCC_LSE_Config LSE Config
EricLew	0:80ee8f3b695e	191	* @{
EricLew	0:80ee8f3b695e	192	*/
EricLew	0:80ee8f3b695e	193	#define RCC_LSE_OFF ((uint32_t)0x00000000) /!< LSE clock deactivation /
EricLew	0:80ee8f3b695e	194	#define RCC_LSE_ON RCC_BDCR_LSEON /!< LSE clock activation /
EricLew	0:80ee8f3b695e	195	#define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP \| RCC_BDCR_LSEON)) /!< External clock source for LSE clock /
EricLew	0:80ee8f3b695e	196	/**
EricLew	0:80ee8f3b695e	197	* @}
EricLew	0:80ee8f3b695e	198	*/
EricLew	0:80ee8f3b695e	199
EricLew	0:80ee8f3b695e	200	/** @defgroup RCC_HSI_Config HSI Config
EricLew	0:80ee8f3b695e	201	* @{
EricLew	0:80ee8f3b695e	202	*/
EricLew	0:80ee8f3b695e	203	#define RCC_HSI_OFF ((uint32_t)0x00000000) /!< HSI clock deactivation /
EricLew	0:80ee8f3b695e	204	#define RCC_HSI_ON RCC_CR_HSION /!< HSI clock activation /
EricLew	0:80ee8f3b695e	205
EricLew	0:80ee8f3b695e	206	#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)16) /!< Default HSI calibration trimming value /
EricLew	0:80ee8f3b695e	207	/**
EricLew	0:80ee8f3b695e	208	* @}
EricLew	0:80ee8f3b695e	209	*/
EricLew	0:80ee8f3b695e	210
EricLew	0:80ee8f3b695e	211	/** @defgroup RCC_LSI_Config LSI Config
EricLew	0:80ee8f3b695e	212	* @{
EricLew	0:80ee8f3b695e	213	*/
EricLew	0:80ee8f3b695e	214	#define RCC_LSI_OFF ((uint32_t)0x00000000) /!< LSI clock deactivation /
EricLew	0:80ee8f3b695e	215	#define RCC_LSI_ON RCC_CSR_LSION /!< LSI clock activation /
EricLew	0:80ee8f3b695e	216	/**
EricLew	0:80ee8f3b695e	217	* @}
EricLew	0:80ee8f3b695e	218	*/
EricLew	0:80ee8f3b695e	219
EricLew	0:80ee8f3b695e	220	/** @defgroup RCC_MSI_Config MSI Config
EricLew	0:80ee8f3b695e	221	* @{
EricLew	0:80ee8f3b695e	222	*/
EricLew	0:80ee8f3b695e	223	#define RCC_MSI_OFF ((uint32_t)0x00000000) /!< MSI clock deactivation /
EricLew	0:80ee8f3b695e	224	#define RCC_MSI_ON RCC_CR_MSION /!< MSI clock activation /
EricLew	0:80ee8f3b695e	225
EricLew	0:80ee8f3b695e	226	#define RCC_MSICALIBRATION_DEFAULT ((uint32_t)0) /!< Default MSI calibration trimming value /
EricLew	0:80ee8f3b695e	227	/**
EricLew	0:80ee8f3b695e	228	* @}
EricLew	0:80ee8f3b695e	229	*/
EricLew	0:80ee8f3b695e	230
EricLew	0:80ee8f3b695e	231	/** @defgroup RCC_PLL_Config PLL Config
EricLew	0:80ee8f3b695e	232	* @{
EricLew	0:80ee8f3b695e	233	*/
EricLew	0:80ee8f3b695e	234	#define RCC_PLL_NONE ((uint32_t)0x00000000) /!< PLL configuration unchanged /
EricLew	0:80ee8f3b695e	235	#define RCC_PLL_OFF ((uint32_t)0x00000001) /!< PLL deactivation /
EricLew	0:80ee8f3b695e	236	#define RCC_PLL_ON ((uint32_t)0x00000002) /!< PLL activation /
EricLew	0:80ee8f3b695e	237	/**
EricLew	0:80ee8f3b695e	238	* @}
EricLew	0:80ee8f3b695e	239	*/
EricLew	0:80ee8f3b695e	240
EricLew	0:80ee8f3b695e	241	/** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider
EricLew	0:80ee8f3b695e	242	* @{
EricLew	0:80ee8f3b695e	243	*/
EricLew	0:80ee8f3b695e	244	#define RCC_PLLP_DIV7 ((uint32_t)0x00000007) /!< PLLP division factor = 7 /
EricLew	0:80ee8f3b695e	245	#define RCC_PLLP_DIV17 ((uint32_t)0x00000011) /!< PLLP division factor = 17 /
EricLew	0:80ee8f3b695e	246	/**
EricLew	0:80ee8f3b695e	247	* @}
EricLew	0:80ee8f3b695e	248	*/
EricLew	0:80ee8f3b695e	249
EricLew	0:80ee8f3b695e	250	/** @defgroup RCC_PLLQ_Clock_Divider PLLQ Clock Divider
EricLew	0:80ee8f3b695e	251	* @{
EricLew	0:80ee8f3b695e	252	*/
EricLew	0:80ee8f3b695e	253	#define RCC_PLLQ_DIV2 ((uint32_t)0x00000002) /!< PLLQ division factor = 2 /
EricLew	0:80ee8f3b695e	254	#define RCC_PLLQ_DIV4 ((uint32_t)0x00000004) /!< PLLQ division factor = 4 /
EricLew	0:80ee8f3b695e	255	#define RCC_PLLQ_DIV6 ((uint32_t)0x00000006) /!< PLLQ division factor = 6 /
EricLew	0:80ee8f3b695e	256	#define RCC_PLLQ_DIV8 ((uint32_t)0x00000008) /!< PLLQ division factor = 8 /
EricLew	0:80ee8f3b695e	257	/**
EricLew	0:80ee8f3b695e	258	* @}
EricLew	0:80ee8f3b695e	259	*/
EricLew	0:80ee8f3b695e	260
EricLew	0:80ee8f3b695e	261	/** @defgroup RCC_PLLR_Clock_Divider PLLR Clock Divider
EricLew	0:80ee8f3b695e	262	* @{
EricLew	0:80ee8f3b695e	263	*/
EricLew	0:80ee8f3b695e	264	#define RCC_PLLR_DIV2 ((uint32_t)0x00000002) /!< PLLR division factor = 2 /
EricLew	0:80ee8f3b695e	265	#define RCC_PLLR_DIV4 ((uint32_t)0x00000004) /!< PLLR division factor = 4 /
EricLew	0:80ee8f3b695e	266	#define RCC_PLLR_DIV6 ((uint32_t)0x00000006) /!< PLLR division factor = 6 /
EricLew	0:80ee8f3b695e	267	#define RCC_PLLR_DIV8 ((uint32_t)0x00000008) /!< PLLR division factor = 8 /
EricLew	0:80ee8f3b695e	268	/**
EricLew	0:80ee8f3b695e	269	* @}
EricLew	0:80ee8f3b695e	270	*/
EricLew	0:80ee8f3b695e	271
EricLew	0:80ee8f3b695e	272	/** @defgroup RCC_PLL_Clock_Source PLL Clock Source
EricLew	0:80ee8f3b695e	273	* @{
EricLew	0:80ee8f3b695e	274	*/
EricLew	0:80ee8f3b695e	275	#define RCC_PLLSOURCE_NONE ((uint32_t)0x00000000) /!< No clock selected as PLL entry clock source /
EricLew	0:80ee8f3b695e	276	#define RCC_PLLSOURCE_MSI RCC_PLLCFGR_PLLSRC_MSI /!< MSI clock selected as PLL entry clock source /
EricLew	0:80ee8f3b695e	277	#define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /!< HSI clock selected as PLL entry clock source /
EricLew	0:80ee8f3b695e	278	#define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /!< HSE clock selected as PLL entry clock source /
EricLew	0:80ee8f3b695e	279	/**
EricLew	0:80ee8f3b695e	280	* @}
EricLew	0:80ee8f3b695e	281	*/
EricLew	0:80ee8f3b695e	282
EricLew	0:80ee8f3b695e	283	/** @defgroup RCC_PLL_Clock_Output PLL Clock Output
EricLew	0:80ee8f3b695e	284	* @{
EricLew	0:80ee8f3b695e	285	*/
EricLew	0:80ee8f3b695e	286	#define RCC_PLL_SAI3CLK RCC_PLLCFGR_PLLPEN /!< PLLSAI3CLK selection from main PLL /
EricLew	0:80ee8f3b695e	287	#define RCC_PLL_48M1CLK RCC_PLLCFGR_PLLQEN /!< PLL48M1CLK selection from main PLL /
EricLew	0:80ee8f3b695e	288	#define RCC_PLL_SYSCLK RCC_PLLCFGR_PLLREN /!< PLLCLK selection from main PLL /
EricLew	0:80ee8f3b695e	289	/**
EricLew	0:80ee8f3b695e	290	* @}
EricLew	0:80ee8f3b695e	291	*/
EricLew	0:80ee8f3b695e	292
EricLew	0:80ee8f3b695e	293	/** @defgroup RCC_PLLSAI1_Clock_Output PLLSAI1 Clock Output
EricLew	0:80ee8f3b695e	294	* @{
EricLew	0:80ee8f3b695e	295	*/
EricLew	0:80ee8f3b695e	296	#define RCC_PLLSAI1_SAI1CLK RCC_PLLSAI1CFGR_PLLSAI1PEN /!< PLLSAI1CLK selection from PLLSAI1 /
EricLew	0:80ee8f3b695e	297	#define RCC_PLLSAI1_48M2CLK RCC_PLLSAI1CFGR_PLLSAI1QEN /!< PLL48M2CLK selection from PLLSAI1 /
EricLew	0:80ee8f3b695e	298	#define RCC_PLLSAI1_ADC1CLK RCC_PLLSAI1CFGR_PLLSAI1REN /!< PLLADC1CLK selection from PLLSAI1 /
EricLew	0:80ee8f3b695e	299	/**
EricLew	0:80ee8f3b695e	300	* @}
EricLew	0:80ee8f3b695e	301	*/
EricLew	0:80ee8f3b695e	302
EricLew	0:80ee8f3b695e	303	/** @defgroup RCC_PLLSAI2_Clock_Output PLLSAI2 Clock Output
EricLew	0:80ee8f3b695e	304	* @{
EricLew	0:80ee8f3b695e	305	*/
EricLew	0:80ee8f3b695e	306	#define RCC_PLLSAI2_SAI2CLK RCC_PLLSAI2CFGR_PLLSAI2PEN /!< PLLSAI2CLK selection from PLLSAI2 /
EricLew	0:80ee8f3b695e	307	#define RCC_PLLSAI2_ADC2CLK RCC_PLLSAI2CFGR_PLLSAI2REN /!< PLLADC2CLK selection from PLLSAI2 /
EricLew	0:80ee8f3b695e	308	/**
EricLew	0:80ee8f3b695e	309	* @}
EricLew	0:80ee8f3b695e	310	*/
EricLew	0:80ee8f3b695e	311
EricLew	0:80ee8f3b695e	312	/** @defgroup RCC_MSI_Clock_Range MSI Clock Range
EricLew	0:80ee8f3b695e	313	* @{
EricLew	0:80ee8f3b695e	314	*/
EricLew	0:80ee8f3b695e	315	#define RCC_MSIRANGE_0 RCC_CR_MSIRANGE_0 /!< MSI = 100 KHz /
EricLew	0:80ee8f3b695e	316	#define RCC_MSIRANGE_1 RCC_CR_MSIRANGE_1 /!< MSI = 200 KHz /
EricLew	0:80ee8f3b695e	317	#define RCC_MSIRANGE_2 RCC_CR_MSIRANGE_2 /!< MSI = 400 KHz /
EricLew	0:80ee8f3b695e	318	#define RCC_MSIRANGE_3 RCC_CR_MSIRANGE_3 /!< MSI = 800 KHz /
EricLew	0:80ee8f3b695e	319	#define RCC_MSIRANGE_4 RCC_CR_MSIRANGE_4 /!< MSI = 1 MHz /
EricLew	0:80ee8f3b695e	320	#define RCC_MSIRANGE_5 RCC_CR_MSIRANGE_5 /!< MSI = 2 MHz /
EricLew	0:80ee8f3b695e	321	#define RCC_MSIRANGE_6 RCC_CR_MSIRANGE_6 /!< MSI = 4 MHz /
EricLew	0:80ee8f3b695e	322	#define RCC_MSIRANGE_7 RCC_CR_MSIRANGE_7 /!< MSI = 8 MHz /
EricLew	0:80ee8f3b695e	323	#define RCC_MSIRANGE_8 RCC_CR_MSIRANGE_8 /!< MSI = 16 MHz /
EricLew	0:80ee8f3b695e	324	#define RCC_MSIRANGE_9 RCC_CR_MSIRANGE_9 /!< MSI = 24 MHz /
EricLew	0:80ee8f3b695e	325	#define RCC_MSIRANGE_10 RCC_CR_MSIRANGE_10 /!< MSI = 32 MHz /
EricLew	0:80ee8f3b695e	326	#define RCC_MSIRANGE_11 RCC_CR_MSIRANGE_11 /!< MSI = 48 MHz /
EricLew	0:80ee8f3b695e	327	/**
EricLew	0:80ee8f3b695e	328	* @}
EricLew	0:80ee8f3b695e	329	*/
EricLew	0:80ee8f3b695e	330
EricLew	0:80ee8f3b695e	331	/** @defgroup RCC_System_Clock_Type System Clock Type
EricLew	0:80ee8f3b695e	332	* @{
EricLew	0:80ee8f3b695e	333	*/
EricLew	0:80ee8f3b695e	334	#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001) /!< SYSCLK to configure /
EricLew	0:80ee8f3b695e	335	#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002) /!< HCLK to configure /
EricLew	0:80ee8f3b695e	336	#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004) /!< PCLK1 to configure /
EricLew	0:80ee8f3b695e	337	#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008) /!< PCLK2 to configure /
EricLew	0:80ee8f3b695e	338	/**
EricLew	0:80ee8f3b695e	339	* @}
EricLew	0:80ee8f3b695e	340	*/
EricLew	0:80ee8f3b695e	341
EricLew	0:80ee8f3b695e	342	/** @defgroup RCC_System_Clock_Source System Clock Source
EricLew	0:80ee8f3b695e	343	* @{
EricLew	0:80ee8f3b695e	344	*/
EricLew	0:80ee8f3b695e	345	#define RCC_SYSCLKSOURCE_MSI RCC_CFGR_SW_MSI /!< MSI selection as system clock /
EricLew	0:80ee8f3b695e	346	#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /!< HSI selection as system clock /
EricLew	0:80ee8f3b695e	347	#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /!< HSE selection as system clock /
EricLew	0:80ee8f3b695e	348	#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /!< PLL selection as system clock /
EricLew	0:80ee8f3b695e	349	/**
EricLew	0:80ee8f3b695e	350	* @}
EricLew	0:80ee8f3b695e	351	*/
EricLew	0:80ee8f3b695e	352
EricLew	0:80ee8f3b695e	353	/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
EricLew	0:80ee8f3b695e	354	* @{
EricLew	0:80ee8f3b695e	355	*/
EricLew	0:80ee8f3b695e	356	#define RCC_SYSCLKSOURCE_STATUS_MSI RCC_CFGR_SWS_MSI /!< MSI used as system clock /
EricLew	0:80ee8f3b695e	357	#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /!< HSI used as system clock /
EricLew	0:80ee8f3b695e	358	#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /!< HSE used as system clock /
EricLew	0:80ee8f3b695e	359	#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /!< PLL used as system clock /
EricLew	0:80ee8f3b695e	360	/**
EricLew	0:80ee8f3b695e	361	* @}
EricLew	0:80ee8f3b695e	362	*/
EricLew	0:80ee8f3b695e	363
EricLew	0:80ee8f3b695e	364	/** @defgroup RCC_AHB_Clock_Source AHB Clock Source
EricLew	0:80ee8f3b695e	365	* @{
EricLew	0:80ee8f3b695e	366	*/
EricLew	0:80ee8f3b695e	367	#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /!< SYSCLK not divided /
EricLew	0:80ee8f3b695e	368	#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /!< SYSCLK divided by 2 /
EricLew	0:80ee8f3b695e	369	#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /!< SYSCLK divided by 4 /
EricLew	0:80ee8f3b695e	370	#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /!< SYSCLK divided by 8 /
EricLew	0:80ee8f3b695e	371	#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /!< SYSCLK divided by 16 /
EricLew	0:80ee8f3b695e	372	#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /!< SYSCLK divided by 64 /
EricLew	0:80ee8f3b695e	373	#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /!< SYSCLK divided by 128 /
EricLew	0:80ee8f3b695e	374	#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /!< SYSCLK divided by 256 /
EricLew	0:80ee8f3b695e	375	#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /!< SYSCLK divided by 512 /
EricLew	0:80ee8f3b695e	376	/**
EricLew	0:80ee8f3b695e	377	* @}
EricLew	0:80ee8f3b695e	378	*/
EricLew	0:80ee8f3b695e	379
EricLew	0:80ee8f3b695e	380	/** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source
EricLew	0:80ee8f3b695e	381	* @{
EricLew	0:80ee8f3b695e	382	*/
EricLew	0:80ee8f3b695e	383	#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /!< HCLK not divided /
EricLew	0:80ee8f3b695e	384	#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 /!< HCLK divided by 2 /
EricLew	0:80ee8f3b695e	385	#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 /!< HCLK divided by 4 /
EricLew	0:80ee8f3b695e	386	#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /!< HCLK divided by 8 /
EricLew	0:80ee8f3b695e	387	#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /!< HCLK divided by 16 /
EricLew	0:80ee8f3b695e	388	/**
EricLew	0:80ee8f3b695e	389	* @}
EricLew	0:80ee8f3b695e	390	*/
EricLew	0:80ee8f3b695e	391
EricLew	0:80ee8f3b695e	392	/** @defgroup RCC_RTC_Clock_Source RTC Clock Source
EricLew	0:80ee8f3b695e	393	* @{
EricLew	0:80ee8f3b695e	394	*/
EricLew	0:80ee8f3b695e	395	#define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /!< LSE oscillator clock used as RTC clock /
EricLew	0:80ee8f3b695e	396	#define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /!< LSI oscillator clock used as RTC clock /
EricLew	0:80ee8f3b695e	397	#define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /!< HSE oscillator clock divided by 32 used as RTC clock /
EricLew	0:80ee8f3b695e	398	/**
EricLew	0:80ee8f3b695e	399	* @}
EricLew	0:80ee8f3b695e	400	*/
EricLew	0:80ee8f3b695e	401
EricLew	0:80ee8f3b695e	402	/** @defgroup RCC_MCO_Index MCO Index
EricLew	0:80ee8f3b695e	403	* @{
EricLew	0:80ee8f3b695e	404	*/
EricLew	0:80ee8f3b695e	405	#define RCC_MCO1 ((uint32_t)0x00000000)
EricLew	0:80ee8f3b695e	406	#define RCC_MCO RCC_MCO1 /!< MCO1 to be compliant with other families with 2 MCOs/
EricLew	0:80ee8f3b695e	407	/**
EricLew	0:80ee8f3b695e	408	* @}
EricLew	0:80ee8f3b695e	409	*/
EricLew	0:80ee8f3b695e	410
EricLew	0:80ee8f3b695e	411	/** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source
EricLew	0:80ee8f3b695e	412	* @{
EricLew	0:80ee8f3b695e	413	*/
EricLew	0:80ee8f3b695e	414	#define RCC_MCO1SOURCE_NOCLOCK ((uint32_t)0x00000000) /!< MCO1 output disabled, no clock on MCO1 /
EricLew	0:80ee8f3b695e	415	#define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0 /!< SYSCLK selection as MCO1 source /
EricLew	0:80ee8f3b695e	416	#define RCC_MCO1SOURCE_MSI RCC_CFGR_MCOSEL_1 /!< MSI selection as MCO1 source /
EricLew	0:80ee8f3b695e	417	#define RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0\| RCC_CFGR_MCOSEL_1) /!< HSI selection as MCO1 source /
EricLew	0:80ee8f3b695e	418	#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2 /!< HSE selection as MCO1 source /
EricLew	0:80ee8f3b695e	419	#define RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0\|RCC_CFGR_MCOSEL_2) /!< PLLCLK selection as MCO1 source /
EricLew	0:80ee8f3b695e	420	#define RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1\|RCC_CFGR_MCOSEL_2) /!< LSI selection as MCO1 source /
EricLew	0:80ee8f3b695e	421	#define RCC_MCO1SOURCE_LSE (RCC_CFGR_MCOSEL_0\|RCC_CFGR_MCOSEL_1\|RCC_CFGR_MCOSEL_2) /!< LSE selection as MCO1 source /
EricLew	0:80ee8f3b695e	422	/**
EricLew	0:80ee8f3b695e	423	* @}
EricLew	0:80ee8f3b695e	424	*/
EricLew	0:80ee8f3b695e	425
EricLew	0:80ee8f3b695e	426	/** @defgroup RCC_MCOx_Clock_Prescaler MCO1 Clock Prescaler
EricLew	0:80ee8f3b695e	427	* @{
EricLew	0:80ee8f3b695e	428	*/
EricLew	0:80ee8f3b695e	429	#define RCC_MCODIV_1 RCC_CFGR_MCO_PRE_1 /!< MCO not divided /
EricLew	0:80ee8f3b695e	430	#define RCC_MCODIV_2 RCC_CFGR_MCO_PRE_2 /!< MCO divided by 2 /
EricLew	0:80ee8f3b695e	431	#define RCC_MCODIV_4 RCC_CFGR_MCO_PRE_4 /!< MCO divided by 4 /
EricLew	0:80ee8f3b695e	432	#define RCC_MCODIV_8 RCC_CFGR_MCO_PRE_8 /!< MCO divided by 8 /
EricLew	0:80ee8f3b695e	433	#define RCC_MCODIV_16 RCC_CFGR_MCO_PRE_16 /!< MCO divided by 16 /
EricLew	0:80ee8f3b695e	434	/**
EricLew	0:80ee8f3b695e	435	* @}
EricLew	0:80ee8f3b695e	436	*/
EricLew	0:80ee8f3b695e	437
EricLew	0:80ee8f3b695e	438	/** @defgroup RCC_Interrupt Interrupts
EricLew	0:80ee8f3b695e	439	* @{
EricLew	0:80ee8f3b695e	440	*/
EricLew	0:80ee8f3b695e	441	#define RCC_IT_LSIRDY RCC_CIFR_LSIRDYF /!< LSI Ready Interrupt flag /
EricLew	0:80ee8f3b695e	442	#define RCC_IT_LSERDY RCC_CIFR_LSERDYF /!< LSE Ready Interrupt flag /
EricLew	0:80ee8f3b695e	443	#define RCC_IT_MSIRDY RCC_CIFR_MSIRDYF /!< MSI Ready Interrupt flag /
EricLew	0:80ee8f3b695e	444	#define RCC_IT_HSIRDY RCC_CIFR_HSIRDYF /!< HSI16 Ready Interrupt flag /
EricLew	0:80ee8f3b695e	445	#define RCC_IT_HSERDY RCC_CIFR_HSERDYF /!< HSE Ready Interrupt flag /
EricLew	0:80ee8f3b695e	446	#define RCC_IT_PLLRDY RCC_CIFR_PLLRDYF /!< PLL Ready Interrupt flag /
EricLew	0:80ee8f3b695e	447	#define RCC_IT_PLLSAI1RDY RCC_CIFR_PLLSAI1RDYF /!< PLLSAI1 Ready Interrupt flag /
EricLew	0:80ee8f3b695e	448	#define RCC_IT_PLLSAI2RDY RCC_CIFR_PLLSAI2RDYF /!< PLLSAI2 Ready Interrupt flag /
EricLew	0:80ee8f3b695e	449	#define RCC_IT_CSS RCC_CIFR_CSSF /!< Clock Security System Interrupt flag /
EricLew	0:80ee8f3b695e	450	#define RCC_IT_LSECSS RCC_CIFR_LSECSSF /!< LSE Clock Security System Interrupt flag /
EricLew	0:80ee8f3b695e	451	/**
EricLew	0:80ee8f3b695e	452	* @}
EricLew	0:80ee8f3b695e	453	*/
EricLew	0:80ee8f3b695e	454
EricLew	0:80ee8f3b695e	455	/** @defgroup RCC_Flag Flags
EricLew	0:80ee8f3b695e	456	* Elements values convention: XXXYYYYYb
EricLew	0:80ee8f3b695e	457	* - YYYYY : Flag position in the register
EricLew	0:80ee8f3b695e	458	* - XXX : Register index
EricLew	0:80ee8f3b695e	459	* - 001: CR register
EricLew	0:80ee8f3b695e	460	* - 010: BDCR register
EricLew	0:80ee8f3b695e	461	* - 011: CSR register
EricLew	0:80ee8f3b695e	462	* @{
EricLew	0:80ee8f3b695e	463	*/
EricLew	0:80ee8f3b695e	464	/* Flags in the CR register */
EricLew	0:80ee8f3b695e	465	#define RCC_FLAG_MSIRDY ((uint32_t)((CR_REG_INDEX << 5) \| POSITION_VAL(RCC_CR_MSIRDY))) /!< MSI Ready flag /
EricLew	0:80ee8f3b695e	466	#define RCC_FLAG_HSIRDY ((uint32_t)((CR_REG_INDEX << 5) \| POSITION_VAL(RCC_CR_HSIRDY))) /!< HSI Ready flag /
EricLew	0:80ee8f3b695e	467	#define RCC_FLAG_HSERDY ((uint32_t)((CR_REG_INDEX << 5) \| POSITION_VAL(RCC_CR_HSERDY))) /!< HSE Ready flag /
EricLew	0:80ee8f3b695e	468	#define RCC_FLAG_PLLRDY ((uint32_t)((CR_REG_INDEX << 5) \| POSITION_VAL(RCC_CR_PLLRDY))) /!< PLL Ready flag /
EricLew	0:80ee8f3b695e	469	#define RCC_FLAG_PLLSAI1RDY ((uint32_t)((CR_REG_INDEX << 5) \| POSITION_VAL(RCC_CR_PLLSAI1RDY))) /!< PLLSAI1 Ready flag /
EricLew	0:80ee8f3b695e	470	#define RCC_FLAG_PLLSAI2RDY ((uint32_t)((CR_REG_INDEX << 5) \| POSITION_VAL(RCC_CR_PLLSAI2RDY))) /!< PLLSAI2 Ready flag /
EricLew	0:80ee8f3b695e	471
EricLew	0:80ee8f3b695e	472	/* Flags in the BDCR register */
EricLew	0:80ee8f3b695e	473	#define RCC_FLAG_LSERDY ((uint32_t)((BDCR_REG_INDEX << 5) \| POSITION_VAL(RCC_BDCR_LSERDY))) /!< LSE Ready flag /
EricLew	0:80ee8f3b695e	474	#define RCC_FLAG_LSECSSD ((uint32_t)((BDCR_REG_INDEX << 5) \| POSITION_VAL(RCC_BDCR_LSECSSD))) /!< LSE Clock Security System Interrupt flag /
EricLew	0:80ee8f3b695e	475
EricLew	0:80ee8f3b695e	476	/* Flags in the CSR register */
EricLew	0:80ee8f3b695e	477	#define RCC_FLAG_LSIRDY ((uint32_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_LSIRDY))) /!< LSI Ready flag /
EricLew	0:80ee8f3b695e	478	#define RCC_FLAG_RMVF ((uint32_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_RMVF))) /!< Remove reset flag /
EricLew	0:80ee8f3b695e	479	#define RCC_FLAG_FWRST ((uint32_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_FWRSTF))) /!< Firewall reset flag /
EricLew	0:80ee8f3b695e	480	#define RCC_FLAG_OBLRST ((uint32_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_OBLRSTF))) /!< Option Byte Loader reset flag /
EricLew	0:80ee8f3b695e	481	#define RCC_FLAG_PINRST ((uint32_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_PINRSTF))) /!< PIN reset flag /
EricLew	0:80ee8f3b695e	482	#define RCC_FLAG_BORRST ((uint32_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_BORRSTF))) /!< BOR reset flag /
EricLew	0:80ee8f3b695e	483	#define RCC_FLAG_SFTRST ((uint32_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_SFTRSTF))) /!< Software Reset flag /
EricLew	0:80ee8f3b695e	484	#define RCC_FLAG_IWDGRST ((uint32_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_IWDGRSTF))) /!< Independent Watchdog reset flag /
EricLew	0:80ee8f3b695e	485	#define RCC_FLAG_WWDGRST ((uint32_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_WWDGRSTF))) /!< Window watchdog reset flag /
EricLew	0:80ee8f3b695e	486	#define RCC_FLAG_LPWRRST ((uint32_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_LPWRRSTF))) /!< Low-Power reset flag /
EricLew	0:80ee8f3b695e	487
EricLew	0:80ee8f3b695e	488	/**
EricLew	0:80ee8f3b695e	489	* @}
EricLew	0:80ee8f3b695e	490	*/
EricLew	0:80ee8f3b695e	491
EricLew	0:80ee8f3b695e	492	/** @defgroup RCC_LSEDrive_Config LSE Drive Config
EricLew	0:80ee8f3b695e	493	* @{
EricLew	0:80ee8f3b695e	494	*/
EricLew	0:80ee8f3b695e	495	#define RCC_LSEDRIVE_LOW ((uint32_t)0x00000000) /!< LSE low drive capability /
EricLew	0:80ee8f3b695e	496	#define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /!< LSE medium low drive capability /
EricLew	0:80ee8f3b695e	497	#define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /!< LSE medium high drive capability /
EricLew	0:80ee8f3b695e	498	#define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /!< LSE high drive capability /
EricLew	0:80ee8f3b695e	499	/**
EricLew	0:80ee8f3b695e	500	* @}
EricLew	0:80ee8f3b695e	501	*/
EricLew	0:80ee8f3b695e	502
EricLew	0:80ee8f3b695e	503	/** @defgroup RCC_Stop_WakeUpClock Wake-Up from STOP Clock
EricLew	0:80ee8f3b695e	504	* @{
EricLew	0:80ee8f3b695e	505	*/
EricLew	0:80ee8f3b695e	506	#define RCC_STOP_WAKEUPCLOCK_MSI ((uint32_t)0x00000000) /!< MSI selection after wake-up from STOP /
EricLew	0:80ee8f3b695e	507	#define RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK /!< HSI selection after wake-up from STOP /
EricLew	0:80ee8f3b695e	508	/**
EricLew	0:80ee8f3b695e	509	* @}
EricLew	0:80ee8f3b695e	510	*/
EricLew	0:80ee8f3b695e	511
EricLew	0:80ee8f3b695e	512	/**
EricLew	0:80ee8f3b695e	513	* @}
EricLew	0:80ee8f3b695e	514	*/
EricLew	0:80ee8f3b695e	515
EricLew	0:80ee8f3b695e	516	/* Exported macros -----------------------------------------------------------*/
EricLew	0:80ee8f3b695e	517
EricLew	0:80ee8f3b695e	518	/** @defgroup RCC_Exported_Macros RCC Exported Macros
EricLew	0:80ee8f3b695e	519	* @{
EricLew	0:80ee8f3b695e	520	*/
EricLew	0:80ee8f3b695e	521
EricLew	0:80ee8f3b695e	522	/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
EricLew	0:80ee8f3b695e	523	* @brief Enable or disable the AHB1 peripheral clock.
EricLew	0:80ee8f3b695e	524	* @note After reset, the peripheral clock (used for registers read/write access)
EricLew	0:80ee8f3b695e	525	* is disabled and the application software has to enable this clock before
EricLew	0:80ee8f3b695e	526	* using it.
EricLew	0:80ee8f3b695e	527	* @{
EricLew	0:80ee8f3b695e	528	*/
EricLew	0:80ee8f3b695e	529
EricLew	0:80ee8f3b695e	530	#define __HAL_RCC_DMA1_CLK_ENABLE() do { \
EricLew	0:80ee8f3b695e	531	__IO uint32_t tmpreg; \
EricLew	0:80ee8f3b695e	532	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \
EricLew	0:80ee8f3b695e	533	/* Delay after an RCC peripheral clock enabling */ \
EricLew	0:80ee8f3b695e	534	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \
EricLew	0:80ee8f3b695e	535	UNUSED(tmpreg); \
EricLew	0:80ee8f3b695e	536	} while(0)
EricLew	0:80ee8f3b695e	537
EricLew	0:80ee8f3b695e	538	#define __HAL_RCC_DMA2_CLK_ENABLE() do { \
EricLew	0:80ee8f3b695e	539	__IO uint32_t tmpreg; \
EricLew	0:80ee8f3b695e	540	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \
EricLew	0:80ee8f3b695e	541	/* Delay after an RCC peripheral clock enabling */ \
EricLew	0:80ee8f3b695e	542	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \
EricLew	0:80ee8f3b695e	543	UNUSED(tmpreg); \
EricLew	0:80ee8f3b695e	544	} while(0)
EricLew	0:80ee8f3b695e	545
EricLew	0:80ee8f3b695e	546	#define __HAL_RCC_FLASH_CLK_ENABLE() do { \
EricLew	0:80ee8f3b695e	547	__IO uint32_t tmpreg; \
EricLew	0:80ee8f3b695e	548	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
EricLew	0:80ee8f3b695e	549	/* Delay after an RCC peripheral clock enabling */ \
EricLew	0:80ee8f3b695e	550	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
EricLew	0:80ee8f3b695e	551	UNUSED(tmpreg); \
EricLew	0:80ee8f3b695e	552	} while(0)
EricLew	0:80ee8f3b695e	553
EricLew	0:80ee8f3b695e	554	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
EricLew	0:80ee8f3b695e	555	__IO uint32_t tmpreg; \
EricLew	0:80ee8f3b695e	556	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
EricLew	0:80ee8f3b695e	557	/* Delay after an RCC peripheral clock enabling */ \
EricLew	0:80ee8f3b695e	558	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
EricLew	0:80ee8f3b695e	559	UNUSED(tmpreg); \
EricLew	0:80ee8f3b695e	560	} while(0)
EricLew	0:80ee8f3b695e	561
EricLew	0:80ee8f3b695e	562	#define __HAL_RCC_TSC_CLK_ENABLE() do { \
EricLew	0:80ee8f3b695e	563	__IO uint32_t tmpreg; \
EricLew	0:80ee8f3b695e	564	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \
EricLew	0:80ee8f3b695e	565	/* Delay after an RCC peripheral clock enabling */ \
EricLew	0:80ee8f3b695e	566	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \
EricLew	0:80ee8f3b695e	567	UNUSED(tmpreg); \
EricLew	0:80ee8f3b695e	568	} while(0)
EricLew	0:80ee8f3b695e	569
EricLew	0:80ee8f3b695e	570	#define __HAL_RCC_DMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN)
EricLew	0:80ee8f3b695e	571
EricLew	0:80ee8f3b695e	572	#define __HAL_RCC_DMA2_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN)
EricLew	0:80ee8f3b695e	573
EricLew	0:80ee8f3b695e	574	#define __HAL_RCC_FLASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN)
EricLew	0:80ee8f3b695e	575
EricLew	0:80ee8f3b695e	576	#define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN)
EricLew	0:80ee8f3b695e	577
EricLew	0:80ee8f3b695e	578	#define __HAL_RCC_TSC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN)
EricLew	0:80ee8f3b695e	579
EricLew	0:80ee8f3b695e	580	/**
EricLew	0:80ee8f3b695e	581	* @}
EricLew	0:80ee8f3b695e	582	*/
EricLew	0:80ee8f3b695e	583
EricLew	0:80ee8f3b695e	584	/** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
EricLew	0:80ee8f3b695e	585	* @brief Enable or disable the AHB2 peripheral clock.
EricLew	0:80ee8f3b695e	586	* @note After reset, the peripheral clock (used for registers read/write access)
EricLew	0:80ee8f3b695e	587	* is disabled and the application software has to enable this clock before
EricLew	0:80ee8f3b695e	588	* using it.
EricLew	0:80ee8f3b695e	589	* @{
EricLew	0:80ee8f3b695e	590	*/
EricLew	0:80ee8f3b695e	591
EricLew	0:80ee8f3b695e	592	#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
EricLew	0:80ee8f3b695e	593	__IO uint32_t tmpreg; \
EricLew	0:80ee8f3b695e	594	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \
EricLew	0:80ee8f3b695e	595	/* Delay after an RCC peripheral clock enabling */ \
EricLew	0:80ee8f3b695e	596	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \
EricLew	0:80ee8f3b695e	597	UNUSED(tmpreg); \
EricLew	0:80ee8f3b695e	598	} while(0)
EricLew	0:80ee8f3b695e	599
EricLew	0:80ee8f3b695e	600	#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
EricLew	0:80ee8f3b695e	601	__IO uint32_t tmpreg; \
EricLew	0:80ee8f3b695e	602	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \
EricLew	0:80ee8f3b695e	603	/* Delay after an RCC peripheral clock enabling */ \
EricLew	0:80ee8f3b695e	604	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \
EricLew	0:80ee8f3b695e	605	UNUSED(tmpreg); \
EricLew	0:80ee8f3b695e	606	} while(0)
EricLew	0:80ee8f3b695e	607
EricLew	0:80ee8f3b695e	608	#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
EricLew	0:80ee8f3b695e	609	__IO uint32_t tmpreg; \
EricLew	0:80ee8f3b695e	610	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \
EricLew	0:80ee8f3b695e	611	/* Delay after an RCC peripheral clock enabling */ \
EricLew	0:80ee8f3b695e	612	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \
EricLew	0:80ee8f3b695e	613	UNUSED(tmpreg); \
EricLew	0:80ee8f3b695e	614	} while(0)
EricLew	0:80ee8f3b695e	615
EricLew	0:80ee8f3b695e	616	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
EricLew	0:80ee8f3b695e	617	__IO uint32_t tmpreg; \
EricLew	0:80ee8f3b695e	618	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \
EricLew	0:80ee8f3b695e	619	/* Delay after an RCC peripheral clock enabling */ \
EricLew	0:80ee8f3b695e	620	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \
EricLew	0:80ee8f3b695e	621	UNUSED(tmpreg); \
EricLew	0:80ee8f3b695e	622	} while(0)
EricLew	0:80ee8f3b695e	623
EricLew	0:80ee8f3b695e	624	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
EricLew	0:80ee8f3b695e	625	__IO uint32_t tmpreg; \
EricLew	0:80ee8f3b695e	626	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \
EricLew	0:80ee8f3b695e	627	/* Delay after an RCC peripheral clock enabling */ \
EricLew	0:80ee8f3b695e	628	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \
EricLew	0:80ee8f3b695e	629	UNUSED(tmpreg); \
EricLew	0:80ee8f3b695e	630	} while(0)
EricLew	0:80ee8f3b695e	631
EricLew	0:80ee8f3b695e	632	#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
EricLew	0:80ee8f3b695e	633	__IO uint32_t tmpreg; \
EricLew	0:80ee8f3b695e	634	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \
EricLew	0:80ee8f3b695e	635	/* Delay after an RCC peripheral clock enabling */ \
EricLew	0:80ee8f3b695e	636	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \
EricLew	0:80ee8f3b695e	637	UNUSED(tmpreg); \
EricLew	0:80ee8f3b695e	638	} while(0)
EricLew	0:80ee8f3b695e	639
EricLew	0:80ee8f3b695e	640	#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
EricLew	0:80ee8f3b695e	641	__IO uint32_t tmpreg; \
EricLew	0:80ee8f3b695e	642	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \
EricLew	0:80ee8f3b695e	643	/* Delay after an RCC peripheral clock enabling */ \
EricLew	0:80ee8f3b695e	644	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \
EricLew	0:80ee8f3b695e	645	UNUSED(tmpreg); \
EricLew	0:80ee8f3b695e	646	} while(0)
EricLew	0:80ee8f3b695e	647
EricLew	0:80ee8f3b695e	648	#define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
EricLew	0:80ee8f3b695e	649	__IO uint32_t tmpreg; \
EricLew	0:80ee8f3b695e	650	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \
EricLew	0:80ee8f3b695e	651	/* Delay after an RCC peripheral clock enabling */ \
EricLew	0:80ee8f3b695e	652	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \
EricLew	0:80ee8f3b695e	653	UNUSED(tmpreg); \
EricLew	0:80ee8f3b695e	654	} while(0)
EricLew	0:80ee8f3b695e	655
EricLew	0:80ee8f3b695e	656	#if defined(STM32L475xx) \|\| defined(STM32L476xx) \|\| defined(STM32L485xx) \|\| defined(STM32L486xx)
EricLew	0:80ee8f3b695e	657
EricLew	0:80ee8f3b695e	658	#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do { \
EricLew	0:80ee8f3b695e	659	__IO uint32_t tmpreg; \
EricLew	0:80ee8f3b695e	660	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN); \
EricLew	0:80ee8f3b695e	661	/* Delay after an RCC peripheral clock enabling */ \
EricLew	0:80ee8f3b695e	662	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN); \
EricLew	0:80ee8f3b695e	663	UNUSED(tmpreg); \
EricLew	0:80ee8f3b695e	664	} while(0)
EricLew	0:80ee8f3b695e	665
EricLew	0:80ee8f3b695e	666	#endif /* STM32L475xx \|\| STM32L476xx \|\| STM32L485xx \|\| STM32L486xx */
EricLew	0:80ee8f3b695e	667
EricLew	0:80ee8f3b695e	668	#define __HAL_RCC_ADC_CLK_ENABLE() do { \
EricLew	0:80ee8f3b695e	669	__IO uint32_t tmpreg; \
EricLew	0:80ee8f3b695e	670	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN); \
EricLew	0:80ee8f3b695e	671	/* Delay after an RCC peripheral clock enabling */ \
EricLew	0:80ee8f3b695e	672	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN); \
EricLew	0:80ee8f3b695e	673	UNUSED(tmpreg); \
EricLew	0:80ee8f3b695e	674	} while(0)
EricLew	0:80ee8f3b695e	675
EricLew	0:80ee8f3b695e	676	#if defined(STM32L485xx) \|\| defined(STM32L486xx)
EricLew	0:80ee8f3b695e	677
EricLew	0:80ee8f3b695e	678	#define __HAL_RCC_AES_CLK_ENABLE() do { \
EricLew	0:80ee8f3b695e	679	__IO uint32_t tmpreg; \
EricLew	0:80ee8f3b695e	680	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \
EricLew	0:80ee8f3b695e	681	/* Delay after an RCC peripheral clock enabling */ \
EricLew	0:80ee8f3b695e	682	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \
EricLew	0:80ee8f3b695e	683	UNUSED(tmpreg); \
EricLew	0:80ee8f3b695e	684	} while(0)
EricLew	0:80ee8f3b695e	685
EricLew	0:80ee8f3b695e	686	#endif /* STM32L485xx \|\| STM32L486xx */
EricLew	0:80ee8f3b695e	687
EricLew	0:80ee8f3b695e	688	#define __HAL_RCC_RNG_CLK_ENABLE() do { \
EricLew	0:80ee8f3b695e	689	__IO uint32_t tmpreg; \
EricLew	0:80ee8f3b695e	690	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \
EricLew	0:80ee8f3b695e	691	/* Delay after an RCC peripheral clock enabling */ \
EricLew	0:80ee8f3b695e	692	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \
EricLew	0:80ee8f3b695e	693	UNUSED(tmpreg); \
EricLew	0:80ee8f3b695e	694	} while(0)
EricLew	0:80ee8f3b695e	695
EricLew	0:80ee8f3b695e	696	#define __HAL_RCC_GPIOA_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN)
EricLew	0:80ee8f3b695e	697
EricLew	0:80ee8f3b695e	698	#define __HAL_RCC_GPIOB_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN)
EricLew	0:80ee8f3b695e	699
EricLew	0:80ee8f3b695e	700	#define __HAL_RCC_GPIOC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN)
EricLew	0:80ee8f3b695e	701
EricLew	0:80ee8f3b695e	702	#define __HAL_RCC_GPIOD_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN)
EricLew	0:80ee8f3b695e	703
EricLew	0:80ee8f3b695e	704	#define __HAL_RCC_GPIOE_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN)
EricLew	0:80ee8f3b695e	705
EricLew	0:80ee8f3b695e	706	#define __HAL_RCC_GPIOF_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN)
EricLew	0:80ee8f3b695e	707
EricLew	0:80ee8f3b695e	708	#define __HAL_RCC_GPIOG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN)
EricLew	0:80ee8f3b695e	709
EricLew	0:80ee8f3b695e	710	#define __HAL_RCC_GPIOH_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN)
EricLew	0:80ee8f3b695e	711
EricLew	0:80ee8f3b695e	712	#if defined(STM32L475xx) \|\| defined(STM32L476xx) \|\| defined(STM32L485xx) \|\| defined(STM32L486xx)
EricLew	0:80ee8f3b695e	713
EricLew	0:80ee8f3b695e	714	#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);
EricLew	0:80ee8f3b695e	715
EricLew	0:80ee8f3b695e	716	#endif /* STM32L475xx \|\| STM32L476xx \|\| STM32L485xx \|\| STM32L486xx */
EricLew	0:80ee8f3b695e	717
EricLew	0:80ee8f3b695e	718	#define __HAL_RCC_ADC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN)
EricLew	0:80ee8f3b695e	719
EricLew	0:80ee8f3b695e	720	#if defined(STM32L485xx) \|\| defined(STM32L486xx)
EricLew	0:80ee8f3b695e	721
EricLew	0:80ee8f3b695e	722	#define __HAL_RCC_AES_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);
EricLew	0:80ee8f3b695e	723
EricLew	0:80ee8f3b695e	724	#endif /* STM32L485xx \|\| STM32L486xx */
EricLew	0:80ee8f3b695e	725
EricLew	0:80ee8f3b695e	726	#define __HAL_RCC_RNG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN)
EricLew	0:80ee8f3b695e	727
EricLew	0:80ee8f3b695e	728	/**
EricLew	0:80ee8f3b695e	729	* @}
EricLew	0:80ee8f3b695e	730	*/
EricLew	0:80ee8f3b695e	731
EricLew	0:80ee8f3b695e	732	/** @defgroup RCC_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
EricLew	0:80ee8f3b695e	733	* @brief Enable or disable the AHB3 peripheral clock.
EricLew	0:80ee8f3b695e	734	* @note After reset, the peripheral clock (used for registers read/write access)
EricLew	0:80ee8f3b695e	735	* is disabled and the application software has to enable this clock before
EricLew	0:80ee8f3b695e	736	* using it.
EricLew	0:80ee8f3b695e	737	* @{
EricLew	0:80ee8f3b695e	738	*/
EricLew	0:80ee8f3b695e	739
EricLew	0:80ee8f3b695e	740	#define __HAL_RCC_FMC_CLK_ENABLE() do { \
EricLew	0:80ee8f3b695e	741	__IO uint32_t tmpreg; \
EricLew	0:80ee8f3b695e	742	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \
EricLew	0:80ee8f3b695e	743	/* Delay after an RCC peripheral clock enabling */ \
EricLew	0:80ee8f3b695e	744	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \
EricLew	0:80ee8f3b695e	745	UNUSED(tmpreg); \
EricLew	0:80ee8f3b695e	746	} while(0)
EricLew	0:80ee8f3b695e	747
EricLew	0:80ee8f3b695e	748	#define __HAL_RCC_QSPI_CLK_ENABLE() do { \
EricLew	0:80ee8f3b695e	749	__IO uint32_t tmpreg; \
EricLew	0:80ee8f3b695e	750	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \
EricLew	0:80ee8f3b695e	751	/* Delay after an RCC peripheral clock enabling */ \
EricLew	0:80ee8f3b695e	752	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \
EricLew	0:80ee8f3b695e	753	UNUSED(tmpreg); \
EricLew	0:80ee8f3b695e	754	} while(0)
EricLew	0:80ee8f3b695e	755
EricLew	0:80ee8f3b695e	756	#define __HAL_RCC_FMC_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN)
EricLew	0:80ee8f3b695e	757
EricLew	0:80ee8f3b695e	758	#define __HAL_RCC_QSPI_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN)
EricLew	0:80ee8f3b695e	759
EricLew	0:80ee8f3b695e	760	/**
EricLew	0:80ee8f3b695e	761	* @}
EricLew	0:80ee8f3b695e	762	*/
EricLew	0:80ee8f3b695e	763
EricLew	0:80ee8f3b695e	764	/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
EricLew	0:80ee8f3b695e	765	* @brief Enable or disable the APB1 peripheral clock.
EricLew	0:80ee8f3b695e	766	* @note After reset, the peripheral clock (used for registers read/write access)
EricLew	0:80ee8f3b695e	767	* is disabled and the application software has to enable this clock before
EricLew	0:80ee8f3b695e	768	* using it.
EricLew	0:80ee8f3b695e	769	* @{
EricLew	0:80ee8f3b695e	770	*/
EricLew	0:80ee8f3b695e	771
EricLew	0:80ee8f3b695e	772	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
EricLew	0:80ee8f3b695e	773	__IO uint32_t tmpreg; \
EricLew	0:80ee8f3b695e	774	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \
EricLew	0:80ee8f3b695e	775	/* Delay after an RCC peripheral clock enabling */ \
EricLew	0:80ee8f3b695e	776	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \
EricLew	0:80ee8f3b695e	777	UNUSED(tmpreg); \
EricLew	0:80ee8f3b695e	778	} while(0)
EricLew	0:80ee8f3b695e	779
EricLew	0:80ee8f3b695e	780	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
EricLew	0:80ee8f3b695e	781	__IO uint32_t tmpreg; \
EricLew	0:80ee8f3b695e	782	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \
EricLew	0:80ee8f3b695e	783	/* Delay after an RCC peripheral clock enabling */ \
EricLew	0:80ee8f3b695e	784	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \
EricLew	0:80ee8f3b695e	785	UNUSED(tmpreg); \
EricLew	0:80ee8f3b695e	786	} while(0)
EricLew	0:80ee8f3b695e	787
EricLew	0:80ee8f3b695e	788	#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
EricLew	0:80ee8f3b695e	789	__IO uint32_t tmpreg; \
EricLew	0:80ee8f3b695e	790	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \
EricLew	0:80ee8f3b695e	791	/* Delay after an RCC peripheral clock enabling */ \
EricLew	0:80ee8f3b695e	792	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \
EricLew	0:80ee8f3b695e	793	UNUSED(tmpreg); \
EricLew	0:80ee8f3b695e	794	} while(0)
EricLew	0:80ee8f3b695e	795
EricLew	0:80ee8f3b695e	796	#define __HAL_RCC_TIM5_CLK_ENABLE() do { \
EricLew	0:80ee8f3b695e	797	__IO uint32_t tmpreg; \
EricLew	0:80ee8f3b695e	798	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \
EricLew	0:80ee8f3b695e	799	/* Delay after an RCC peripheral clock enabling */ \
EricLew	0:80ee8f3b695e	800	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \
EricLew	0:80ee8f3b695e	801	UNUSED(tmpreg); \
EricLew	0:80ee8f3b695e	802	} while(0)
EricLew	0:80ee8f3b695e	803
EricLew	0:80ee8f3b695e	804	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
EricLew	0:80ee8f3b695e	805	__IO uint32_t tmpreg; \
EricLew	0:80ee8f3b695e	806	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \
EricLew	0:80ee8f3b695e	807	/* Delay after an RCC peripheral clock enabling */ \
EricLew	0:80ee8f3b695e	808	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \
EricLew	0:80ee8f3b695e	809	UNUSED(tmpreg); \
EricLew	0:80ee8f3b695e	810	} while(0)
EricLew	0:80ee8f3b695e	811
EricLew	0:80ee8f3b695e	812	#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
EricLew	0:80ee8f3b695e	813	__IO uint32_t tmpreg; \
EricLew	0:80ee8f3b695e	814	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \
EricLew	0:80ee8f3b695e	815	/* Delay after an RCC peripheral clock enabling */ \
EricLew	0:80ee8f3b695e	816	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \
EricLew	0:80ee8f3b695e	817	UNUSED(tmpreg); \
EricLew	0:80ee8f3b695e	818	} while(0)
EricLew	0:80ee8f3b695e	819
EricLew	0:80ee8f3b695e	820	#if defined(STM32L476xx) \|\| defined(STM32L486xx)
EricLew	0:80ee8f3b695e	821	#define __HAL_RCC_LCD_CLK_ENABLE() do { \
EricLew	0:80ee8f3b695e	822	__IO uint32_t tmpreg; \
EricLew	0:80ee8f3b695e	823	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN); \
EricLew	0:80ee8f3b695e	824	/* Delay after an RCC peripheral clock enabling */ \
EricLew	0:80ee8f3b695e	825	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN); \
EricLew	0:80ee8f3b695e	826	UNUSED(tmpreg); \
EricLew	0:80ee8f3b695e	827	} while(0)
EricLew	0:80ee8f3b695e	828	#endif /* STM32L476xx \|\| STM32L486xx */
EricLew	0:80ee8f3b695e	829
EricLew	0:80ee8f3b695e	830	#define __HAL_RCC_WWDG_CLK_ENABLE() do { \
EricLew	0:80ee8f3b695e	831	__IO uint32_t tmpreg; \
EricLew	0:80ee8f3b695e	832	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \
EricLew	0:80ee8f3b695e	833	/* Delay after an RCC peripheral clock enabling */ \
EricLew	0:80ee8f3b695e	834	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \
EricLew	0:80ee8f3b695e	835	UNUSED(tmpreg); \
EricLew	0:80ee8f3b695e	836	} while(0)
EricLew	0:80ee8f3b695e	837
EricLew	0:80ee8f3b695e	838	#define __HAL_RCC_SPI2_CLK_ENABLE() do { \
EricLew	0:80ee8f3b695e	839	__IO uint32_t tmpreg; \
EricLew	0:80ee8f3b695e	840	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \
EricLew	0:80ee8f3b695e	841	/* Delay after an RCC peripheral clock enabling */ \
EricLew	0:80ee8f3b695e	842	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \
EricLew	0:80ee8f3b695e	843	UNUSED(tmpreg); \
EricLew	0:80ee8f3b695e	844	} while(0)
EricLew	0:80ee8f3b695e	845
EricLew	0:80ee8f3b695e	846	#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
EricLew	0:80ee8f3b695e	847	__IO uint32_t tmpreg; \
EricLew	0:80ee8f3b695e	848	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \
EricLew	0:80ee8f3b695e	849	/* Delay after an RCC peripheral clock enabling */ \
EricLew	0:80ee8f3b695e	850	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \
EricLew	0:80ee8f3b695e	851	UNUSED(tmpreg); \
EricLew	0:80ee8f3b695e	852	} while(0)
EricLew	0:80ee8f3b695e	853
EricLew	0:80ee8f3b695e	854	#define __HAL_RCC_USART2_CLK_ENABLE() do { \
EricLew	0:80ee8f3b695e	855	__IO uint32_t tmpreg; \
EricLew	0:80ee8f3b695e	856	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \
EricLew	0:80ee8f3b695e	857	/* Delay after an RCC peripheral clock enabling */ \
EricLew	0:80ee8f3b695e	858	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \
EricLew	0:80ee8f3b695e	859	UNUSED(tmpreg); \
EricLew	0:80ee8f3b695e	860	} while(0)
EricLew	0:80ee8f3b695e	861
EricLew	0:80ee8f3b695e	862	#define __HAL_RCC_USART3_CLK_ENABLE() do { \
EricLew	0:80ee8f3b695e	863	__IO uint32_t tmpreg; \
EricLew	0:80ee8f3b695e	864	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \
EricLew	0:80ee8f3b695e	865	/* Delay after an RCC peripheral clock enabling */ \
EricLew	0:80ee8f3b695e	866	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \
EricLew	0:80ee8f3b695e	867	UNUSED(tmpreg); \
EricLew	0:80ee8f3b695e	868	} while(0)
EricLew	0:80ee8f3b695e	869
EricLew	0:80ee8f3b695e	870	#define __HAL_RCC_UART4_CLK_ENABLE() do { \
EricLew	0:80ee8f3b695e	871	__IO uint32_t tmpreg; \
EricLew	0:80ee8f3b695e	872	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \
EricLew	0:80ee8f3b695e	873	/* Delay after an RCC peripheral clock enabling */ \
EricLew	0:80ee8f3b695e	874	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \
EricLew	0:80ee8f3b695e	875	UNUSED(tmpreg); \
EricLew	0:80ee8f3b695e	876	} while(0)
EricLew	0:80ee8f3b695e	877
EricLew	0:80ee8f3b695e	878	#define __HAL_RCC_UART5_CLK_ENABLE() do { \
EricLew	0:80ee8f3b695e	879	__IO uint32_t tmpreg; \
EricLew	0:80ee8f3b695e	880	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \
EricLew	0:80ee8f3b695e	881	/* Delay after an RCC peripheral clock enabling */ \
EricLew	0:80ee8f3b695e	882	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \
EricLew	0:80ee8f3b695e	883	UNUSED(tmpreg); \
EricLew	0:80ee8f3b695e	884	} while(0)
EricLew	0:80ee8f3b695e	885
EricLew	0:80ee8f3b695e	886	#define __HAL_RCC_I2C1_CLK_ENABLE() do { \
EricLew	0:80ee8f3b695e	887	__IO uint32_t tmpreg; \
EricLew	0:80ee8f3b695e	888	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \
EricLew	0:80ee8f3b695e	889	/* Delay after an RCC peripheral clock enabling */ \
EricLew	0:80ee8f3b695e	890	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \
EricLew	0:80ee8f3b695e	891	UNUSED(tmpreg); \
EricLew	0:80ee8f3b695e	892	} while(0)
EricLew	0:80ee8f3b695e	893
EricLew	0:80ee8f3b695e	894	#define __HAL_RCC_I2C2_CLK_ENABLE() do { \
EricLew	0:80ee8f3b695e	895	__IO uint32_t tmpreg; \
EricLew	0:80ee8f3b695e	896	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \
EricLew	0:80ee8f3b695e	897	/* Delay after an RCC peripheral clock enabling */ \
EricLew	0:80ee8f3b695e	898	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \
EricLew	0:80ee8f3b695e	899	UNUSED(tmpreg); \
EricLew	0:80ee8f3b695e	900	} while(0)
EricLew	0:80ee8f3b695e	901
EricLew	0:80ee8f3b695e	902	#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
EricLew	0:80ee8f3b695e	903	__IO uint32_t tmpreg; \
EricLew	0:80ee8f3b695e	904	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \
EricLew	0:80ee8f3b695e	905	/* Delay after an RCC peripheral clock enabling */ \
EricLew	0:80ee8f3b695e	906	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \
EricLew	0:80ee8f3b695e	907	UNUSED(tmpreg); \
EricLew	0:80ee8f3b695e	908	} while(0)
EricLew	0:80ee8f3b695e	909
EricLew	0:80ee8f3b695e	910	#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
EricLew	0:80ee8f3b695e	911	__IO uint32_t tmpreg; \
EricLew	0:80ee8f3b695e	912	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN); \
EricLew	0:80ee8f3b695e	913	/* Delay after an RCC peripheral clock enabling */ \
EricLew	0:80ee8f3b695e	914	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN); \
EricLew	0:80ee8f3b695e	915	UNUSED(tmpreg); \
EricLew	0:80ee8f3b695e	916	} while(0)
EricLew	0:80ee8f3b695e	917
EricLew	0:80ee8f3b695e	918	#define __HAL_RCC_PWR_CLK_ENABLE() do { \
EricLew	0:80ee8f3b695e	919	__IO uint32_t tmpreg; \
EricLew	0:80ee8f3b695e	920	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \
EricLew	0:80ee8f3b695e	921	/* Delay after an RCC peripheral clock enabling */ \
EricLew	0:80ee8f3b695e	922	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \
EricLew	0:80ee8f3b695e	923	UNUSED(tmpreg); \
EricLew	0:80ee8f3b695e	924	} while(0)
EricLew	0:80ee8f3b695e	925
EricLew	0:80ee8f3b695e	926	#define __HAL_RCC_DAC1_CLK_ENABLE() do { \
EricLew	0:80ee8f3b695e	927	__IO uint32_t tmpreg; \
EricLew	0:80ee8f3b695e	928	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN); \
EricLew	0:80ee8f3b695e	929	/* Delay after an RCC peripheral clock enabling */ \
EricLew	0:80ee8f3b695e	930	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN); \
EricLew	0:80ee8f3b695e	931	UNUSED(tmpreg); \
EricLew	0:80ee8f3b695e	932	} while(0)
EricLew	0:80ee8f3b695e	933
EricLew	0:80ee8f3b695e	934	#define __HAL_RCC_OPAMP_CLK_ENABLE() do { \
EricLew	0:80ee8f3b695e	935	__IO uint32_t tmpreg; \
EricLew	0:80ee8f3b695e	936	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN); \
EricLew	0:80ee8f3b695e	937	/* Delay after an RCC peripheral clock enabling */ \
EricLew	0:80ee8f3b695e	938	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN); \
EricLew	0:80ee8f3b695e	939	UNUSED(tmpreg); \
EricLew	0:80ee8f3b695e	940	} while(0)
EricLew	0:80ee8f3b695e	941
EricLew	0:80ee8f3b695e	942	#define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \
EricLew	0:80ee8f3b695e	943	__IO uint32_t tmpreg; \
EricLew	0:80ee8f3b695e	944	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \
EricLew	0:80ee8f3b695e	945	/* Delay after an RCC peripheral clock enabling */ \
EricLew	0:80ee8f3b695e	946	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \
EricLew	0:80ee8f3b695e	947	UNUSED(tmpreg); \
EricLew	0:80ee8f3b695e	948	} while(0)
EricLew	0:80ee8f3b695e	949
EricLew	0:80ee8f3b695e	950	#define __HAL_RCC_LPUART1_CLK_ENABLE() do { \
EricLew	0:80ee8f3b695e	951	__IO uint32_t tmpreg; \
EricLew	0:80ee8f3b695e	952	SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \
EricLew	0:80ee8f3b695e	953	/* Delay after an RCC peripheral clock enabling */ \
EricLew	0:80ee8f3b695e	954	tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \
EricLew	0:80ee8f3b695e	955	UNUSED(tmpreg); \
EricLew	0:80ee8f3b695e	956	} while(0)
EricLew	0:80ee8f3b695e	957
EricLew	0:80ee8f3b695e	958	#define __HAL_RCC_SWPMI1_CLK_ENABLE() do { \
EricLew	0:80ee8f3b695e	959	__IO uint32_t tmpreg; \
EricLew	0:80ee8f3b695e	960	SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN); \
EricLew	0:80ee8f3b695e	961	/* Delay after an RCC peripheral clock enabling */ \
EricLew	0:80ee8f3b695e	962	tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN); \
EricLew	0:80ee8f3b695e	963	UNUSED(tmpreg); \
EricLew	0:80ee8f3b695e	964	} while(0)
EricLew	0:80ee8f3b695e	965
EricLew	0:80ee8f3b695e	966	#define __HAL_RCC_LPTIM2_CLK_ENABLE() do { \
EricLew	0:80ee8f3b695e	967	__IO uint32_t tmpreg; \
EricLew	0:80ee8f3b695e	968	SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \
EricLew	0:80ee8f3b695e	969	/* Delay after an RCC peripheral clock enabling */ \
EricLew	0:80ee8f3b695e	970	tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \
EricLew	0:80ee8f3b695e	971	UNUSED(tmpreg); \
EricLew	0:80ee8f3b695e	972	} while(0)
EricLew	0:80ee8f3b695e	973
EricLew	0:80ee8f3b695e	974	#define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN)
EricLew	0:80ee8f3b695e	975
EricLew	0:80ee8f3b695e	976	#define __HAL_RCC_TIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN)
EricLew	0:80ee8f3b695e	977
EricLew	0:80ee8f3b695e	978	#define __HAL_RCC_TIM4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN)
EricLew	0:80ee8f3b695e	979
EricLew	0:80ee8f3b695e	980	#define __HAL_RCC_TIM5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN)
EricLew	0:80ee8f3b695e	981
EricLew	0:80ee8f3b695e	982	#define __HAL_RCC_TIM6_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN)
EricLew	0:80ee8f3b695e	983
EricLew	0:80ee8f3b695e	984	#define __HAL_RCC_TIM7_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN)
EricLew	0:80ee8f3b695e	985
EricLew	0:80ee8f3b695e	986	#if defined(STM32L476xx) \|\| defined(STM32L486xx)
EricLew	0:80ee8f3b695e	987	#define __HAL_RCC_LCD_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN);
EricLew	0:80ee8f3b695e	988	#endif /* STM32L476xx \|\| STM32L486xx */
EricLew	0:80ee8f3b695e	989
EricLew	0:80ee8f3b695e	990	#define __HAL_RCC_WWDG_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN)
EricLew	0:80ee8f3b695e	991
EricLew	0:80ee8f3b695e	992	#define __HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN)
EricLew	0:80ee8f3b695e	993
EricLew	0:80ee8f3b695e	994	#define __HAL_RCC_SPI3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN)
EricLew	0:80ee8f3b695e	995
EricLew	0:80ee8f3b695e	996	#define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN)
EricLew	0:80ee8f3b695e	997
EricLew	0:80ee8f3b695e	998	#define __HAL_RCC_USART3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN)
EricLew	0:80ee8f3b695e	999
EricLew	0:80ee8f3b695e	1000	#define __HAL_RCC_UART4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN)
EricLew	0:80ee8f3b695e	1001
EricLew	0:80ee8f3b695e	1002	#define __HAL_RCC_UART5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN)
EricLew	0:80ee8f3b695e	1003
EricLew	0:80ee8f3b695e	1004	#define __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN)
EricLew	0:80ee8f3b695e	1005
EricLew	0:80ee8f3b695e	1006	#define __HAL_RCC_I2C2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN)
EricLew	0:80ee8f3b695e	1007
EricLew	0:80ee8f3b695e	1008	#define __HAL_RCC_I2C3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN)
EricLew	0:80ee8f3b695e	1009
EricLew	0:80ee8f3b695e	1010	#define __HAL_RCC_CAN1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN)
EricLew	0:80ee8f3b695e	1011
EricLew	0:80ee8f3b695e	1012	#define __HAL_RCC_PWR_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN)
EricLew	0:80ee8f3b695e	1013
EricLew	0:80ee8f3b695e	1014	#define __HAL_RCC_DAC1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN)
EricLew	0:80ee8f3b695e	1015
EricLew	0:80ee8f3b695e	1016	#define __HAL_RCC_OPAMP_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN)
EricLew	0:80ee8f3b695e	1017
EricLew	0:80ee8f3b695e	1018	#define __HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN)
EricLew	0:80ee8f3b695e	1019
EricLew	0:80ee8f3b695e	1020	#define __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN)
EricLew	0:80ee8f3b695e	1021
EricLew	0:80ee8f3b695e	1022	#define __HAL_RCC_SWPMI1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN)
EricLew	0:80ee8f3b695e	1023
EricLew	0:80ee8f3b695e	1024	#define __HAL_RCC_LPTIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN)
EricLew	0:80ee8f3b695e	1025
EricLew	0:80ee8f3b695e	1026	/**
EricLew	0:80ee8f3b695e	1027	* @}
EricLew	0:80ee8f3b695e	1028	*/
EricLew	0:80ee8f3b695e	1029
EricLew	0:80ee8f3b695e	1030	/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
EricLew	0:80ee8f3b695e	1031	* @brief Enable or disable the APB2 peripheral clock.
EricLew	0:80ee8f3b695e	1032	* @note After reset, the peripheral clock (used for registers read/write access)
EricLew	0:80ee8f3b695e	1033	* is disabled and the application software has to enable this clock before
EricLew	0:80ee8f3b695e	1034	* using it.
EricLew	0:80ee8f3b695e	1035	* @{
EricLew	0:80ee8f3b695e	1036	*/
EricLew	0:80ee8f3b695e	1037
EricLew	0:80ee8f3b695e	1038	#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
EricLew	0:80ee8f3b695e	1039	__IO uint32_t tmpreg; \
EricLew	0:80ee8f3b695e	1040	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \
EricLew	0:80ee8f3b695e	1041	/* Delay after an RCC peripheral clock enabling */ \
EricLew	0:80ee8f3b695e	1042	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \
EricLew	0:80ee8f3b695e	1043	UNUSED(tmpreg); \
EricLew	0:80ee8f3b695e	1044	} while(0)
EricLew	0:80ee8f3b695e	1045
EricLew	0:80ee8f3b695e	1046	#define __HAL_RCC_FIREWALL_CLK_ENABLE() do { \
EricLew	0:80ee8f3b695e	1047	__IO uint32_t tmpreg; \
EricLew	0:80ee8f3b695e	1048	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN); \
EricLew	0:80ee8f3b695e	1049	/* Delay after an RCC peripheral clock enabling */ \
EricLew	0:80ee8f3b695e	1050	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN); \
EricLew	0:80ee8f3b695e	1051	UNUSED(tmpreg); \
EricLew	0:80ee8f3b695e	1052	} while(0)
EricLew	0:80ee8f3b695e	1053
EricLew	0:80ee8f3b695e	1054	#define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \
EricLew	0:80ee8f3b695e	1055	__IO uint32_t tmpreg; \
EricLew	0:80ee8f3b695e	1056	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN); \
EricLew	0:80ee8f3b695e	1057	/* Delay after an RCC peripheral clock enabling */ \
EricLew	0:80ee8f3b695e	1058	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN); \
EricLew	0:80ee8f3b695e	1059	UNUSED(tmpreg); \
EricLew	0:80ee8f3b695e	1060	} while(0)
EricLew	0:80ee8f3b695e	1061
EricLew	0:80ee8f3b695e	1062	#define __HAL_RCC_TIM1_CLK_ENABLE() do { \
EricLew	0:80ee8f3b695e	1063	__IO uint32_t tmpreg; \
EricLew	0:80ee8f3b695e	1064	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \
EricLew	0:80ee8f3b695e	1065	/* Delay after an RCC peripheral clock enabling */ \
EricLew	0:80ee8f3b695e	1066	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \
EricLew	0:80ee8f3b695e	1067	UNUSED(tmpreg); \
EricLew	0:80ee8f3b695e	1068	} while(0)
EricLew	0:80ee8f3b695e	1069
EricLew	0:80ee8f3b695e	1070	#define __HAL_RCC_SPI1_CLK_ENABLE() do { \
EricLew	0:80ee8f3b695e	1071	__IO uint32_t tmpreg; \
EricLew	0:80ee8f3b695e	1072	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \
EricLew	0:80ee8f3b695e	1073	/* Delay after an RCC peripheral clock enabling */ \
EricLew	0:80ee8f3b695e	1074	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \
EricLew	0:80ee8f3b695e	1075	UNUSED(tmpreg); \
EricLew	0:80ee8f3b695e	1076	} while(0)
EricLew	0:80ee8f3b695e	1077
EricLew	0:80ee8f3b695e	1078	#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
EricLew	0:80ee8f3b695e	1079	__IO uint32_t tmpreg; \
EricLew	0:80ee8f3b695e	1080	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \
EricLew	0:80ee8f3b695e	1081	/* Delay after an RCC peripheral clock enabling */ \
EricLew	0:80ee8f3b695e	1082	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \
EricLew	0:80ee8f3b695e	1083	UNUSED(tmpreg); \
EricLew	0:80ee8f3b695e	1084	} while(0)
EricLew	0:80ee8f3b695e	1085
EricLew	0:80ee8f3b695e	1086	#define __HAL_RCC_USART1_CLK_ENABLE() do { \
EricLew	0:80ee8f3b695e	1087	__IO uint32_t tmpreg; \
EricLew	0:80ee8f3b695e	1088	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \
EricLew	0:80ee8f3b695e	1089	/* Delay after an RCC peripheral clock enabling */ \
EricLew	0:80ee8f3b695e	1090	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \
EricLew	0:80ee8f3b695e	1091	UNUSED(tmpreg); \
EricLew	0:80ee8f3b695e	1092	} while(0)
EricLew	0:80ee8f3b695e	1093
EricLew	0:80ee8f3b695e	1094
EricLew	0:80ee8f3b695e	1095	#define __HAL_RCC_TIM15_CLK_ENABLE() do { \
EricLew	0:80ee8f3b695e	1096	__IO uint32_t tmpreg; \
EricLew	0:80ee8f3b695e	1097	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \
EricLew	0:80ee8f3b695e	1098	/* Delay after an RCC peripheral clock enabling */ \
EricLew	0:80ee8f3b695e	1099	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \
EricLew	0:80ee8f3b695e	1100	UNUSED(tmpreg); \
EricLew	0:80ee8f3b695e	1101	} while(0)
EricLew	0:80ee8f3b695e	1102
EricLew	0:80ee8f3b695e	1103	#define __HAL_RCC_TIM16_CLK_ENABLE() do { \
EricLew	0:80ee8f3b695e	1104	__IO uint32_t tmpreg; \
EricLew	0:80ee8f3b695e	1105	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \
EricLew	0:80ee8f3b695e	1106	/* Delay after an RCC peripheral clock enabling */ \
EricLew	0:80ee8f3b695e	1107	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \
EricLew	0:80ee8f3b695e	1108	UNUSED(tmpreg); \
EricLew	0:80ee8f3b695e	1109	} while(0)
EricLew	0:80ee8f3b695e	1110
EricLew	0:80ee8f3b695e	1111	#define __HAL_RCC_TIM17_CLK_ENABLE() do { \
EricLew	0:80ee8f3b695e	1112	__IO uint32_t tmpreg; \
EricLew	0:80ee8f3b695e	1113	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \
EricLew	0:80ee8f3b695e	1114	/* Delay after an RCC peripheral clock enabling */ \
EricLew	0:80ee8f3b695e	1115	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \
EricLew	0:80ee8f3b695e	1116	UNUSED(tmpreg); \
EricLew	0:80ee8f3b695e	1117	} while(0)
EricLew	0:80ee8f3b695e	1118
EricLew	0:80ee8f3b695e	1119	#define __HAL_RCC_SAI1_CLK_ENABLE() do { \
EricLew	0:80ee8f3b695e	1120	__IO uint32_t tmpreg; \
EricLew	0:80ee8f3b695e	1121	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \
EricLew	0:80ee8f3b695e	1122	/* Delay after an RCC peripheral clock enabling */ \
EricLew	0:80ee8f3b695e	1123	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \
EricLew	0:80ee8f3b695e	1124	UNUSED(tmpreg); \
EricLew	0:80ee8f3b695e	1125	} while(0)
EricLew	0:80ee8f3b695e	1126
EricLew	0:80ee8f3b695e	1127	#define __HAL_RCC_SAI2_CLK_ENABLE() do { \
EricLew	0:80ee8f3b695e	1128	__IO uint32_t tmpreg; \
EricLew	0:80ee8f3b695e	1129	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \
EricLew	0:80ee8f3b695e	1130	/* Delay after an RCC peripheral clock enabling */ \
EricLew	0:80ee8f3b695e	1131	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \
EricLew	0:80ee8f3b695e	1132	UNUSED(tmpreg); \
EricLew	0:80ee8f3b695e	1133	} while(0)
EricLew	0:80ee8f3b695e	1134
EricLew	0:80ee8f3b695e	1135	#define __HAL_RCC_DFSDM_CLK_ENABLE() do { \
EricLew	0:80ee8f3b695e	1136	__IO uint32_t tmpreg; \
EricLew	0:80ee8f3b695e	1137	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDMEN); \
EricLew	0:80ee8f3b695e	1138	/* Delay after an RCC peripheral clock enabling */ \
EricLew	0:80ee8f3b695e	1139	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDMEN); \
EricLew	0:80ee8f3b695e	1140	UNUSED(tmpreg); \
EricLew	0:80ee8f3b695e	1141	} while(0)
EricLew	0:80ee8f3b695e	1142
EricLew	0:80ee8f3b695e	1143	#define __HAL_RCC_SYSCFG_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN)
EricLew	0:80ee8f3b695e	1144
EricLew	0:80ee8f3b695e	1145	#define __HAL_RCC_SDMMC1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN)
EricLew	0:80ee8f3b695e	1146
EricLew	0:80ee8f3b695e	1147	#define __HAL_RCC_TIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN)
EricLew	0:80ee8f3b695e	1148
EricLew	0:80ee8f3b695e	1149	#define __HAL_RCC_SPI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN)
EricLew	0:80ee8f3b695e	1150
EricLew	0:80ee8f3b695e	1151	#define __HAL_RCC_TIM8_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN)
EricLew	0:80ee8f3b695e	1152
EricLew	0:80ee8f3b695e	1153	#define __HAL_RCC_USART1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN)
EricLew	0:80ee8f3b695e	1154
EricLew	0:80ee8f3b695e	1155	#define __HAL_RCC_TIM15_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN)
EricLew	0:80ee8f3b695e	1156
EricLew	0:80ee8f3b695e	1157	#define __HAL_RCC_TIM16_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN)
EricLew	0:80ee8f3b695e	1158
EricLew	0:80ee8f3b695e	1159	#define __HAL_RCC_TIM17_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN)
EricLew	0:80ee8f3b695e	1160
EricLew	0:80ee8f3b695e	1161	#define __HAL_RCC_SAI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN)
EricLew	0:80ee8f3b695e	1162
EricLew	0:80ee8f3b695e	1163	#define __HAL_RCC_SAI2_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN)
EricLew	0:80ee8f3b695e	1164
EricLew	0:80ee8f3b695e	1165	#define __HAL_RCC_DFSDM_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDMEN)
EricLew	0:80ee8f3b695e	1166
EricLew	0:80ee8f3b695e	1167	/**
EricLew	0:80ee8f3b695e	1168	* @}
EricLew	0:80ee8f3b695e	1169	*/
EricLew	0:80ee8f3b695e	1170
EricLew	0:80ee8f3b695e	1171	/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enabled or Disabled Status
EricLew	0:80ee8f3b695e	1172	* @brief Check whether the AHB1 peripheral clock is enabled or not.
EricLew	0:80ee8f3b695e	1173	* @note After reset, the peripheral clock (used for registers read/write access)
EricLew	0:80ee8f3b695e	1174	* is disabled and the application software has to enable this clock before
EricLew	0:80ee8f3b695e	1175	* using it.
EricLew	0:80ee8f3b695e	1176	* @{
EricLew	0:80ee8f3b695e	1177	*/
EricLew	0:80ee8f3b695e	1178
EricLew	0:80ee8f3b695e	1179	#define __HAL_RCC_DMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) != RESET)
EricLew	0:80ee8f3b695e	1180
EricLew	0:80ee8f3b695e	1181	#define __HAL_RCC_DMA2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) != RESET)
EricLew	0:80ee8f3b695e	1182
EricLew	0:80ee8f3b695e	1183	#define __HAL_RCC_FLASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) != RESET)
EricLew	0:80ee8f3b695e	1184
EricLew	0:80ee8f3b695e	1185	#define __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) != RESET)
EricLew	0:80ee8f3b695e	1186
EricLew	0:80ee8f3b695e	1187	#define __HAL_RCC_TSC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) != RESET)
EricLew	0:80ee8f3b695e	1188
EricLew	0:80ee8f3b695e	1189	#define __HAL_RCC_DMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) == RESET)
EricLew	0:80ee8f3b695e	1190
EricLew	0:80ee8f3b695e	1191	#define __HAL_RCC_DMA2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) == RESET)
EricLew	0:80ee8f3b695e	1192
EricLew	0:80ee8f3b695e	1193	#define __HAL_RCC_FLASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) == RESET)
EricLew	0:80ee8f3b695e	1194
EricLew	0:80ee8f3b695e	1195	#define __HAL_RCC_CRC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) == RESET)
EricLew	0:80ee8f3b695e	1196
EricLew	0:80ee8f3b695e	1197	#define __HAL_RCC_TSC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) == RESET)
EricLew	0:80ee8f3b695e	1198
EricLew	0:80ee8f3b695e	1199	/**
EricLew	0:80ee8f3b695e	1200	* @}
EricLew	0:80ee8f3b695e	1201	*/
EricLew	0:80ee8f3b695e	1202
EricLew	0:80ee8f3b695e	1203	/** @defgroup RCC_AHB2_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enabled or Disabled Status
EricLew	0:80ee8f3b695e	1204	* @brief Check whether the AHB2 peripheral clock is enabled or not.
EricLew	0:80ee8f3b695e	1205	* @note After reset, the peripheral clock (used for registers read/write access)
EricLew	0:80ee8f3b695e	1206	* is disabled and the application software has to enable this clock before
EricLew	0:80ee8f3b695e	1207	* using it.
EricLew	0:80ee8f3b695e	1208	* @{
EricLew	0:80ee8f3b695e	1209	*/
EricLew	0:80ee8f3b695e	1210
EricLew	0:80ee8f3b695e	1211	#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) != RESET)
EricLew	0:80ee8f3b695e	1212
EricLew	0:80ee8f3b695e	1213	#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != RESET)
EricLew	0:80ee8f3b695e	1214
EricLew	0:80ee8f3b695e	1215	#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != RESET)
EricLew	0:80ee8f3b695e	1216
EricLew	0:80ee8f3b695e	1217	#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) != RESET)
EricLew	0:80ee8f3b695e	1218
EricLew	0:80ee8f3b695e	1219	#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) != RESET)
EricLew	0:80ee8f3b695e	1220
EricLew	0:80ee8f3b695e	1221	#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) != RESET)
EricLew	0:80ee8f3b695e	1222
EricLew	0:80ee8f3b695e	1223	#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) != RESET)
EricLew	0:80ee8f3b695e	1224
EricLew	0:80ee8f3b695e	1225	#define __HAL_RCC_GPIOH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) != RESET)
EricLew	0:80ee8f3b695e	1226
EricLew	0:80ee8f3b695e	1227	#if defined(STM32L475xx) \|\| defined(STM32L476xx) \|\| defined(STM32L485xx) \|\| defined(STM32L486xx)
EricLew	0:80ee8f3b695e	1228	#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN) != RESET)
EricLew	0:80ee8f3b695e	1229	#endif /* STM32L475xx \|\| STM32L476xx \|\| STM32L485xx \|\| STM32L486xx */
EricLew	0:80ee8f3b695e	1230
EricLew	0:80ee8f3b695e	1231	#define __HAL_RCC_ADC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) != RESET)
EricLew	0:80ee8f3b695e	1232
EricLew	0:80ee8f3b695e	1233	#if defined(STM32L485xx) \|\| defined(STM32L486xx)
EricLew	0:80ee8f3b695e	1234	#define __HAL_RCC_AES_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) != RESET)
EricLew	0:80ee8f3b695e	1235	#endif /* STM32L485xx \|\| STM32L486xx */
EricLew	0:80ee8f3b695e	1236
EricLew	0:80ee8f3b695e	1237	#define __HAL_RCC_RNG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) != RESET)
EricLew	0:80ee8f3b695e	1238
EricLew	0:80ee8f3b695e	1239	#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) == RESET)
EricLew	0:80ee8f3b695e	1240
EricLew	0:80ee8f3b695e	1241	#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) == RESET)
EricLew	0:80ee8f3b695e	1242
EricLew	0:80ee8f3b695e	1243	#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) == RESET)
EricLew	0:80ee8f3b695e	1244
EricLew	0:80ee8f3b695e	1245	#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) == RESET)
EricLew	0:80ee8f3b695e	1246
EricLew	0:80ee8f3b695e	1247	#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) == RESET)
EricLew	0:80ee8f3b695e	1248
EricLew	0:80ee8f3b695e	1249	#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) == RESET)
EricLew	0:80ee8f3b695e	1250
EricLew	0:80ee8f3b695e	1251	#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) == RESET)
EricLew	0:80ee8f3b695e	1252
EricLew	0:80ee8f3b695e	1253	#define __HAL_RCC_GPIOH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) == RESET)
EricLew	0:80ee8f3b695e	1254
EricLew	0:80ee8f3b695e	1255	#if defined(STM32L475xx) \|\| defined(STM32L476xx) \|\| defined(STM32L485xx) \|\| defined(STM32L486xx)
EricLew	0:80ee8f3b695e	1256	#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN) == RESET)
EricLew	0:80ee8f3b695e	1257	#endif /* STM32L475xx \|\| STM32L476xx \|\| STM32L485xx \|\| STM32L486xx */
EricLew	0:80ee8f3b695e	1258
EricLew	0:80ee8f3b695e	1259	#define __HAL_RCC_ADC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) == RESET)
EricLew	0:80ee8f3b695e	1260
EricLew	0:80ee8f3b695e	1261	#if defined(STM32L485xx) \|\| defined(STM32L486xx)
EricLew	0:80ee8f3b695e	1262	#define __HAL_RCC_AES_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) == RESET)
EricLew	0:80ee8f3b695e	1263	#endif /* STM32L485xx \|\| STM32L486xx */
EricLew	0:80ee8f3b695e	1264
EricLew	0:80ee8f3b695e	1265	#define __HAL_RCC_RNG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) == RESET)
EricLew	0:80ee8f3b695e	1266
EricLew	0:80ee8f3b695e	1267	/**
EricLew	0:80ee8f3b695e	1268	* @}
EricLew	0:80ee8f3b695e	1269	*/
EricLew	0:80ee8f3b695e	1270
EricLew	0:80ee8f3b695e	1271	/** @defgroup RCC_AHB3_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enabled or Disabled Status
EricLew	0:80ee8f3b695e	1272	* @brief Check whether the AHB3 peripheral clock is enabled or not.
EricLew	0:80ee8f3b695e	1273	* @note After reset, the peripheral clock (used for registers read/write access)
EricLew	0:80ee8f3b695e	1274	* is disabled and the application software has to enable this clock before
EricLew	0:80ee8f3b695e	1275	* using it.
EricLew	0:80ee8f3b695e	1276	* @{
EricLew	0:80ee8f3b695e	1277	*/
EricLew	0:80ee8f3b695e	1278
EricLew	0:80ee8f3b695e	1279	#define __HAL_RCC_FMC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) != RESET)
EricLew	0:80ee8f3b695e	1280
EricLew	0:80ee8f3b695e	1281	#define __HAL_RCC_QSPI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) != RESET)
EricLew	0:80ee8f3b695e	1282
EricLew	0:80ee8f3b695e	1283	#define __HAL_RCC_FMC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) == RESET)
EricLew	0:80ee8f3b695e	1284
EricLew	0:80ee8f3b695e	1285	#define __HAL_RCC_QSPI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) == RESET)
EricLew	0:80ee8f3b695e	1286
EricLew	0:80ee8f3b695e	1287	/**
EricLew	0:80ee8f3b695e	1288	* @}
EricLew	0:80ee8f3b695e	1289	*/
EricLew	0:80ee8f3b695e	1290
EricLew	0:80ee8f3b695e	1291	/** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enabled or Disabled Status
EricLew	0:80ee8f3b695e	1292	* @brief Check whether the APB1 peripheral clock is enabled or not.
EricLew	0:80ee8f3b695e	1293	* @note After reset, the peripheral clock (used for registers read/write access)
EricLew	0:80ee8f3b695e	1294	* is disabled and the application software has to enable this clock before
EricLew	0:80ee8f3b695e	1295	* using it.
EricLew	0:80ee8f3b695e	1296	* @{
EricLew	0:80ee8f3b695e	1297	*/
EricLew	0:80ee8f3b695e	1298
EricLew	0:80ee8f3b695e	1299	#define __HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) != RESET)
EricLew	0:80ee8f3b695e	1300
EricLew	0:80ee8f3b695e	1301	#define __HAL_RCC_TIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) != RESET)
EricLew	0:80ee8f3b695e	1302
EricLew	0:80ee8f3b695e	1303	#define __HAL_RCC_TIM4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) != RESET)
EricLew	0:80ee8f3b695e	1304
EricLew	0:80ee8f3b695e	1305	#define __HAL_RCC_TIM5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) != RESET)
EricLew	0:80ee8f3b695e	1306
EricLew	0:80ee8f3b695e	1307	#define __HAL_RCC_TIM6_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) != RESET)
EricLew	0:80ee8f3b695e	1308
EricLew	0:80ee8f3b695e	1309	#define __HAL_RCC_TIM7_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) != RESET)
EricLew	0:80ee8f3b695e	1310
EricLew	0:80ee8f3b695e	1311	#if defined(STM32L476xx) \|\| defined(STM32L486xx)
EricLew	0:80ee8f3b695e	1312	#define __HAL_RCC_LCD_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN) != RESET)
EricLew	0:80ee8f3b695e	1313	#endif /* STM32L476xx \|\| STM32L486xx */
EricLew	0:80ee8f3b695e	1314
EricLew	0:80ee8f3b695e	1315	#define __HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) != RESET)
EricLew	0:80ee8f3b695e	1316
EricLew	0:80ee8f3b695e	1317	#define __HAL_RCC_SPI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) != RESET)
EricLew	0:80ee8f3b695e	1318
EricLew	0:80ee8f3b695e	1319	#define __HAL_RCC_SPI3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) != RESET)
EricLew	0:80ee8f3b695e	1320
EricLew	0:80ee8f3b695e	1321	#define __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) != RESET)
EricLew	0:80ee8f3b695e	1322
EricLew	0:80ee8f3b695e	1323	#define __HAL_RCC_USART3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) != RESET)
EricLew	0:80ee8f3b695e	1324
EricLew	0:80ee8f3b695e	1325	#define __HAL_RCC_UART4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) != RESET)
EricLew	0:80ee8f3b695e	1326
EricLew	0:80ee8f3b695e	1327	#define __HAL_RCC_UART5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) != RESET)
EricLew	0:80ee8f3b695e	1328
EricLew	0:80ee8f3b695e	1329	#define __HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) != RESET)
EricLew	0:80ee8f3b695e	1330
EricLew	0:80ee8f3b695e	1331	#define __HAL_RCC_I2C2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) != RESET)
EricLew	0:80ee8f3b695e	1332
EricLew	0:80ee8f3b695e	1333	#define __HAL_RCC_I2C3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) != RESET)
EricLew	0:80ee8f3b695e	1334
EricLew	0:80ee8f3b695e	1335	#define __HAL_RCC_CAN1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) != RESET)
EricLew	0:80ee8f3b695e	1336
EricLew	0:80ee8f3b695e	1337	#define __HAL_RCC_PWR_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) != RESET)
EricLew	0:80ee8f3b695e	1338
EricLew	0:80ee8f3b695e	1339	#define __HAL_RCC_DAC1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) != RESET)
EricLew	0:80ee8f3b695e	1340
EricLew	0:80ee8f3b695e	1341	#define __HAL_RCC_OPAMP_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) != RESET)
EricLew	0:80ee8f3b695e	1342
EricLew	0:80ee8f3b695e	1343	#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) != RESET)
EricLew	0:80ee8f3b695e	1344
EricLew	0:80ee8f3b695e	1345	#define __HAL_RCC_LPUART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) != RESET)
EricLew	0:80ee8f3b695e	1346
EricLew	0:80ee8f3b695e	1347	#define __HAL_RCC_SWPMI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN) != RESET)
EricLew	0:80ee8f3b695e	1348
EricLew	0:80ee8f3b695e	1349	#define __HAL_RCC_LPTIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) != RESET)
EricLew	0:80ee8f3b695e	1350
EricLew	0:80ee8f3b695e	1351	#define __HAL_RCC_TIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) == RESET)
EricLew	0:80ee8f3b695e	1352
EricLew	0:80ee8f3b695e	1353	#define __HAL_RCC_TIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) == RESET)
EricLew	0:80ee8f3b695e	1354
EricLew	0:80ee8f3b695e	1355	#define __HAL_RCC_TIM4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) == RESET)
EricLew	0:80ee8f3b695e	1356
EricLew	0:80ee8f3b695e	1357	#define __HAL_RCC_TIM5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) == RESET)
EricLew	0:80ee8f3b695e	1358
EricLew	0:80ee8f3b695e	1359	#define __HAL_RCC_TIM6_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) == RESET)
EricLew	0:80ee8f3b695e	1360
EricLew	0:80ee8f3b695e	1361	#define __HAL_RCC_TIM7_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) == RESET)
EricLew	0:80ee8f3b695e	1362
EricLew	0:80ee8f3b695e	1363	#if defined(STM32L476xx) \|\| defined(STM32L486xx)
EricLew	0:80ee8f3b695e	1364	#define __HAL_RCC_LCD_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN) == RESET)
EricLew	0:80ee8f3b695e	1365	#endif /* STM32L476xx \|\| STM32L486xx */
EricLew	0:80ee8f3b695e	1366
EricLew	0:80ee8f3b695e	1367	#define __HAL_RCC_WWDG_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) == RESET)
EricLew	0:80ee8f3b695e	1368
EricLew	0:80ee8f3b695e	1369	#define __HAL_RCC_SPI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) == RESET)
EricLew	0:80ee8f3b695e	1370
EricLew	0:80ee8f3b695e	1371	#define __HAL_RCC_SPI3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) == RESET)
EricLew	0:80ee8f3b695e	1372
EricLew	0:80ee8f3b695e	1373	#define __HAL_RCC_USART2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) == RESET)
EricLew	0:80ee8f3b695e	1374
EricLew	0:80ee8f3b695e	1375	#define __HAL_RCC_USART3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) == RESET)
EricLew	0:80ee8f3b695e	1376
EricLew	0:80ee8f3b695e	1377	#define __HAL_RCC_UART4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) == RESET)
EricLew	0:80ee8f3b695e	1378
EricLew	0:80ee8f3b695e	1379	#define __HAL_RCC_UART5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) == RESET)
EricLew	0:80ee8f3b695e	1380
EricLew	0:80ee8f3b695e	1381	#define __HAL_RCC_I2C1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) == RESET)
EricLew	0:80ee8f3b695e	1382
EricLew	0:80ee8f3b695e	1383	#define __HAL_RCC_I2C2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) == RESET)
EricLew	0:80ee8f3b695e	1384
EricLew	0:80ee8f3b695e	1385	#define __HAL_RCC_I2C3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) == RESET)
EricLew	0:80ee8f3b695e	1386
EricLew	0:80ee8f3b695e	1387	#define __HAL_RCC_CAN1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) == RESET)
EricLew	0:80ee8f3b695e	1388
EricLew	0:80ee8f3b695e	1389	#define __HAL_RCC_PWR_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) == RESET)
EricLew	0:80ee8f3b695e	1390
EricLew	0:80ee8f3b695e	1391	#define __HAL_RCC_DAC1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) == RESET)
EricLew	0:80ee8f3b695e	1392
EricLew	0:80ee8f3b695e	1393	#define __HAL_RCC_OPAMP_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) == RESET)
EricLew	0:80ee8f3b695e	1394
EricLew	0:80ee8f3b695e	1395	#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) == RESET)
EricLew	0:80ee8f3b695e	1396
EricLew	0:80ee8f3b695e	1397	#define __HAL_RCC_LPUART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) == RESET)
EricLew	0:80ee8f3b695e	1398
EricLew	0:80ee8f3b695e	1399	#define __HAL_RCC_SWPMI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN) == RESET)
EricLew	0:80ee8f3b695e	1400
EricLew	0:80ee8f3b695e	1401	#define __HAL_RCC_LPTIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) == RESET)
EricLew	0:80ee8f3b695e	1402
EricLew	0:80ee8f3b695e	1403	/**
EricLew	0:80ee8f3b695e	1404	* @}
EricLew	0:80ee8f3b695e	1405	*/
EricLew	0:80ee8f3b695e	1406
EricLew	0:80ee8f3b695e	1407	/** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enabled or Disabled Status
EricLew	0:80ee8f3b695e	1408	* @brief Check whether the APB2 peripheral clock is enabled or not.
EricLew	0:80ee8f3b695e	1409	* @note After reset, the peripheral clock (used for registers read/write access)
EricLew	0:80ee8f3b695e	1410	* is disabled and the application software has to enable this clock before
EricLew	0:80ee8f3b695e	1411	* using it.
EricLew	0:80ee8f3b695e	1412	* @{
EricLew	0:80ee8f3b695e	1413	*/
EricLew	0:80ee8f3b695e	1414
EricLew	0:80ee8f3b695e	1415	#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) != RESET)
EricLew	0:80ee8f3b695e	1416
EricLew	0:80ee8f3b695e	1417	#define __HAL_RCC_FIREWALL_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN) != RESET)
EricLew	0:80ee8f3b695e	1418
EricLew	0:80ee8f3b695e	1419	#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) != RESET)
EricLew	0:80ee8f3b695e	1420
EricLew	0:80ee8f3b695e	1421	#define __HAL_RCC_TIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) != RESET)
EricLew	0:80ee8f3b695e	1422
EricLew	0:80ee8f3b695e	1423	#define __HAL_RCC_SPI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) != RESET)
EricLew	0:80ee8f3b695e	1424
EricLew	0:80ee8f3b695e	1425	#define __HAL_RCC_TIM8_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) != RESET)
EricLew	0:80ee8f3b695e	1426
EricLew	0:80ee8f3b695e	1427	#define __HAL_RCC_USART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) != RESET)
EricLew	0:80ee8f3b695e	1428
EricLew	0:80ee8f3b695e	1429	#define __HAL_RCC_TIM15_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) != RESET)
EricLew	0:80ee8f3b695e	1430
EricLew	0:80ee8f3b695e	1431	#define __HAL_RCC_TIM16_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) != RESET)
EricLew	0:80ee8f3b695e	1432
EricLew	0:80ee8f3b695e	1433	#define __HAL_RCC_TIM17_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) != RESET)
EricLew	0:80ee8f3b695e	1434
EricLew	0:80ee8f3b695e	1435	#define __HAL_RCC_SAI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) != RESET)
EricLew	0:80ee8f3b695e	1436
EricLew	0:80ee8f3b695e	1437	#define __HAL_RCC_SAI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) != RESET)
EricLew	0:80ee8f3b695e	1438
EricLew	0:80ee8f3b695e	1439	#define __HAL_RCC_DFSDM_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDMEN) != RESET)
EricLew	0:80ee8f3b695e	1440
EricLew	0:80ee8f3b695e	1441	#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) == RESET)
EricLew	0:80ee8f3b695e	1442
EricLew	0:80ee8f3b695e	1443	#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) == RESET)
EricLew	0:80ee8f3b695e	1444
EricLew	0:80ee8f3b695e	1445	#define __HAL_RCC_TIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) == RESET)
EricLew	0:80ee8f3b695e	1446
EricLew	0:80ee8f3b695e	1447	#define __HAL_RCC_SPI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) == RESET)
EricLew	0:80ee8f3b695e	1448
EricLew	0:80ee8f3b695e	1449	#define __HAL_RCC_TIM8_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) == RESET)
EricLew	0:80ee8f3b695e	1450
EricLew	0:80ee8f3b695e	1451	#define __HAL_RCC_USART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) == RESET)
EricLew	0:80ee8f3b695e	1452
EricLew	0:80ee8f3b695e	1453	#define __HAL_RCC_TIM15_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) == RESET)
EricLew	0:80ee8f3b695e	1454
EricLew	0:80ee8f3b695e	1455	#define __HAL_RCC_TIM16_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) == RESET)
EricLew	0:80ee8f3b695e	1456
EricLew	0:80ee8f3b695e	1457	#define __HAL_RCC_TIM17_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) == RESET)
EricLew	0:80ee8f3b695e	1458
EricLew	0:80ee8f3b695e	1459	#define __HAL_RCC_SAI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) == RESET)
EricLew	0:80ee8f3b695e	1460
EricLew	0:80ee8f3b695e	1461	#define __HAL_RCC_SAI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) == RESET)
EricLew	0:80ee8f3b695e	1462
EricLew	0:80ee8f3b695e	1463	#define __HAL_RCC_DFSDM_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDMEN) == RESET)
EricLew	0:80ee8f3b695e	1464
EricLew	0:80ee8f3b695e	1465	/**
EricLew	0:80ee8f3b695e	1466	* @}
EricLew	0:80ee8f3b695e	1467	*/
EricLew	0:80ee8f3b695e	1468
EricLew	0:80ee8f3b695e	1469	/** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Peripheral Force Release Reset
EricLew	0:80ee8f3b695e	1470	* @brief Force or release AHB1 peripheral reset.
EricLew	0:80ee8f3b695e	1471	* @{
EricLew	0:80ee8f3b695e	1472	*/
EricLew	0:80ee8f3b695e	1473	#define __HAL_RCC_AHB1_FORCE_RESET() WRITE_REG(RCC->AHB1RSTR, 0xFFFFFFFF)
EricLew	0:80ee8f3b695e	1474
EricLew	0:80ee8f3b695e	1475	#define __HAL_RCC_DMA1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST)
EricLew	0:80ee8f3b695e	1476
EricLew	0:80ee8f3b695e	1477	#define __HAL_RCC_DMA2_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST)
EricLew	0:80ee8f3b695e	1478
EricLew	0:80ee8f3b695e	1479	#define __HAL_RCC_FLASH_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST)
EricLew	0:80ee8f3b695e	1480
EricLew	0:80ee8f3b695e	1481	#define __HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST)
EricLew	0:80ee8f3b695e	1482
EricLew	0:80ee8f3b695e	1483	#define __HAL_RCC_TSC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST)
EricLew	0:80ee8f3b695e	1484
EricLew	0:80ee8f3b695e	1485	#define __HAL_RCC_AHB1_RELEASE_RESET() WRITE_REG(RCC->AHB1RSTR, 0x00000000)
EricLew	0:80ee8f3b695e	1486
EricLew	0:80ee8f3b695e	1487	#define __HAL_RCC_DMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST)
EricLew	0:80ee8f3b695e	1488
EricLew	0:80ee8f3b695e	1489	#define __HAL_RCC_DMA2_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST)
EricLew	0:80ee8f3b695e	1490
EricLew	0:80ee8f3b695e	1491	#define __HAL_RCC_FLASH_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST)
EricLew	0:80ee8f3b695e	1492
EricLew	0:80ee8f3b695e	1493	#define __HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST)
EricLew	0:80ee8f3b695e	1494
EricLew	0:80ee8f3b695e	1495	#define __HAL_RCC_TSC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST)
EricLew	0:80ee8f3b695e	1496
EricLew	0:80ee8f3b695e	1497	/**
EricLew	0:80ee8f3b695e	1498	* @}
EricLew	0:80ee8f3b695e	1499	*/
EricLew	0:80ee8f3b695e	1500
EricLew	0:80ee8f3b695e	1501	/** @defgroup RCC_AHB2_Force_Release_Reset AHB2 Peripheral Force Release Reset
EricLew	0:80ee8f3b695e	1502	* @brief Force or release AHB2 peripheral reset.
EricLew	0:80ee8f3b695e	1503	* @{
EricLew	0:80ee8f3b695e	1504	*/
EricLew	0:80ee8f3b695e	1505	#define __HAL_RCC_AHB2_FORCE_RESET() WRITE_REG(RCC->AHB2RSTR, 0xFFFFFFFF)
EricLew	0:80ee8f3b695e	1506
EricLew	0:80ee8f3b695e	1507	#define __HAL_RCC_GPIOA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST)
EricLew	0:80ee8f3b695e	1508
EricLew	0:80ee8f3b695e	1509	#define __HAL_RCC_GPIOB_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST)
EricLew	0:80ee8f3b695e	1510
EricLew	0:80ee8f3b695e	1511	#define __HAL_RCC_GPIOC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST)
EricLew	0:80ee8f3b695e	1512
EricLew	0:80ee8f3b695e	1513	#define __HAL_RCC_GPIOD_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST)
EricLew	0:80ee8f3b695e	1514
EricLew	0:80ee8f3b695e	1515	#define __HAL_RCC_GPIOE_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST)
EricLew	0:80ee8f3b695e	1516
EricLew	0:80ee8f3b695e	1517	#define __HAL_RCC_GPIOF_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST)
EricLew	0:80ee8f3b695e	1518
EricLew	0:80ee8f3b695e	1519	#define __HAL_RCC_GPIOG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST)
EricLew	0:80ee8f3b695e	1520
EricLew	0:80ee8f3b695e	1521	#define __HAL_RCC_GPIOH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOHRST)
EricLew	0:80ee8f3b695e	1522
EricLew	0:80ee8f3b695e	1523	#if defined(STM32L475xx) \|\| defined(STM32L476xx) \|\| defined(STM32L485xx) \|\| defined(STM32L486xx)
EricLew	0:80ee8f3b695e	1524	#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OTGFSRST)
EricLew	0:80ee8f3b695e	1525	#endif /* STM32L475xx \|\| STM32L476xx \|\| STM32L485xx \|\| STM32L486xx */
EricLew	0:80ee8f3b695e	1526
EricLew	0:80ee8f3b695e	1527	#define __HAL_RCC_ADC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADCRST)
EricLew	0:80ee8f3b695e	1528
EricLew	0:80ee8f3b695e	1529	#if defined(STM32L485xx) \|\| defined(STM32L486xx)
EricLew	0:80ee8f3b695e	1530	#define __HAL_RCC_AES_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST)
EricLew	0:80ee8f3b695e	1531	#endif /* STM32L485xx \|\| STM32L486xx */
EricLew	0:80ee8f3b695e	1532
EricLew	0:80ee8f3b695e	1533	#define __HAL_RCC_RNG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST)
EricLew	0:80ee8f3b695e	1534
EricLew	0:80ee8f3b695e	1535	#define __HAL_RCC_AHB2_RELEASE_RESET() WRITE_REG(RCC->AHB2RSTR, 0x00000000)
EricLew	0:80ee8f3b695e	1536
EricLew	0:80ee8f3b695e	1537	#define __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST)
EricLew	0:80ee8f3b695e	1538
EricLew	0:80ee8f3b695e	1539	#define __HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST)
EricLew	0:80ee8f3b695e	1540
EricLew	0:80ee8f3b695e	1541	#define __HAL_RCC_GPIOC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST)
EricLew	0:80ee8f3b695e	1542
EricLew	0:80ee8f3b695e	1543	#define __HAL_RCC_GPIOD_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST)
EricLew	0:80ee8f3b695e	1544
EricLew	0:80ee8f3b695e	1545	#define __HAL_RCC_GPIOE_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST)
EricLew	0:80ee8f3b695e	1546
EricLew	0:80ee8f3b695e	1547	#define __HAL_RCC_GPIOF_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST)
EricLew	0:80ee8f3b695e	1548
EricLew	0:80ee8f3b695e	1549	#define __HAL_RCC_GPIOG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST)
EricLew	0:80ee8f3b695e	1550
EricLew	0:80ee8f3b695e	1551	#define __HAL_RCC_GPIOH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOHRST)
EricLew	0:80ee8f3b695e	1552
EricLew	0:80ee8f3b695e	1553	#if defined(STM32L475xx) \|\| defined(STM32L476xx) \|\| defined(STM32L485xx) \|\| defined(STM32L486xx)
EricLew	0:80ee8f3b695e	1554	#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OTGFSRST)
EricLew	0:80ee8f3b695e	1555	#endif /* STM32L475xx \|\| STM32L476xx \|\| STM32L485xx \|\| STM32L486xx */
EricLew	0:80ee8f3b695e	1556
EricLew	0:80ee8f3b695e	1557	#define __HAL_RCC_ADC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADCRST)
EricLew	0:80ee8f3b695e	1558
EricLew	0:80ee8f3b695e	1559	#if defined(STM32L485xx) \|\| defined(STM32L486xx)
EricLew	0:80ee8f3b695e	1560	#define __HAL_RCC_AES_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST)
EricLew	0:80ee8f3b695e	1561	#endif /* STM32L485xx \|\| STM32L486xx */
EricLew	0:80ee8f3b695e	1562
EricLew	0:80ee8f3b695e	1563	#define __HAL_RCC_RNG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST)
EricLew	0:80ee8f3b695e	1564
EricLew	0:80ee8f3b695e	1565	/**
EricLew	0:80ee8f3b695e	1566	* @}
EricLew	0:80ee8f3b695e	1567	*/
EricLew	0:80ee8f3b695e	1568
EricLew	0:80ee8f3b695e	1569	/** @defgroup RCC_AHB3_Force_Release_Reset AHB3 Peripheral Force Release Reset
EricLew	0:80ee8f3b695e	1570	* @brief Force or release AHB3 peripheral reset.
EricLew	0:80ee8f3b695e	1571	* @{
EricLew	0:80ee8f3b695e	1572	*/
EricLew	0:80ee8f3b695e	1573	#define __HAL_RCC_AHB3_FORCE_RESET() WRITE_REG(RCC->AHB3RSTR, 0xFFFFFFFF)
EricLew	0:80ee8f3b695e	1574
EricLew	0:80ee8f3b695e	1575	#define __HAL_RCC_FMC_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST)
EricLew	0:80ee8f3b695e	1576
EricLew	0:80ee8f3b695e	1577	#define __HAL_RCC_QSPI_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST)
EricLew	0:80ee8f3b695e	1578
EricLew	0:80ee8f3b695e	1579	#define __HAL_RCC_AHB3_RELEASE_RESET() WRITE_REG(RCC->AHB3RSTR, 0x00000000)
EricLew	0:80ee8f3b695e	1580
EricLew	0:80ee8f3b695e	1581	#define __HAL_RCC_FMC_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST)
EricLew	0:80ee8f3b695e	1582
EricLew	0:80ee8f3b695e	1583	#define __HAL_RCC_QSPI_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST)
EricLew	0:80ee8f3b695e	1584
EricLew	0:80ee8f3b695e	1585	/**
EricLew	0:80ee8f3b695e	1586	* @}
EricLew	0:80ee8f3b695e	1587	*/
EricLew	0:80ee8f3b695e	1588
EricLew	0:80ee8f3b695e	1589	/** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset
EricLew	0:80ee8f3b695e	1590	* @brief Force or release APB1 peripheral reset.
EricLew	0:80ee8f3b695e	1591	* @{
EricLew	0:80ee8f3b695e	1592	*/
EricLew	0:80ee8f3b695e	1593	#define __HAL_RCC_APB1_FORCE_RESET() WRITE_REG(RCC->APB1RSTR1, 0xFFFFFFFF)
EricLew	0:80ee8f3b695e	1594
EricLew	0:80ee8f3b695e	1595	#define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST)
EricLew	0:80ee8f3b695e	1596
EricLew	0:80ee8f3b695e	1597	#define __HAL_RCC_TIM3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST)
EricLew	0:80ee8f3b695e	1598
EricLew	0:80ee8f3b695e	1599	#define __HAL_RCC_TIM4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST)
EricLew	0:80ee8f3b695e	1600
EricLew	0:80ee8f3b695e	1601	#define __HAL_RCC_TIM5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST)
EricLew	0:80ee8f3b695e	1602
EricLew	0:80ee8f3b695e	1603	#define __HAL_RCC_TIM6_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST)
EricLew	0:80ee8f3b695e	1604
EricLew	0:80ee8f3b695e	1605	#define __HAL_RCC_TIM7_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST)
EricLew	0:80ee8f3b695e	1606
EricLew	0:80ee8f3b695e	1607	#if defined(STM32L476xx) \|\| defined(STM32L486xx)
EricLew	0:80ee8f3b695e	1608	#define __HAL_RCC_LCD_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LCDRST)
EricLew	0:80ee8f3b695e	1609	#endif /* STM32L476xx \|\| STM32L486xx */
EricLew	0:80ee8f3b695e	1610
EricLew	0:80ee8f3b695e	1611	#define __HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST)
EricLew	0:80ee8f3b695e	1612
EricLew	0:80ee8f3b695e	1613	#define __HAL_RCC_SPI3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST)
EricLew	0:80ee8f3b695e	1614
EricLew	0:80ee8f3b695e	1615	#define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST)
EricLew	0:80ee8f3b695e	1616
EricLew	0:80ee8f3b695e	1617	#define __HAL_RCC_USART3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST)
EricLew	0:80ee8f3b695e	1618
EricLew	0:80ee8f3b695e	1619	#define __HAL_RCC_UART4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST)
EricLew	0:80ee8f3b695e	1620
EricLew	0:80ee8f3b695e	1621	#define __HAL_RCC_UART5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST)
EricLew	0:80ee8f3b695e	1622
EricLew	0:80ee8f3b695e	1623	#define __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST)
EricLew	0:80ee8f3b695e	1624
EricLew	0:80ee8f3b695e	1625	#define __HAL_RCC_I2C2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST)
EricLew	0:80ee8f3b695e	1626
EricLew	0:80ee8f3b695e	1627	#define __HAL_RCC_I2C3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST)
EricLew	0:80ee8f3b695e	1628
EricLew	0:80ee8f3b695e	1629	#define __HAL_RCC_CAN1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN1RST)
EricLew	0:80ee8f3b695e	1630
EricLew	0:80ee8f3b695e	1631	#define __HAL_RCC_PWR_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST)
EricLew	0:80ee8f3b695e	1632
EricLew	0:80ee8f3b695e	1633	#define __HAL_RCC_DAC1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_DAC1RST)
EricLew	0:80ee8f3b695e	1634
EricLew	0:80ee8f3b695e	1635	#define __HAL_RCC_OPAMP_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_OPAMPRST)
EricLew	0:80ee8f3b695e	1636
EricLew	0:80ee8f3b695e	1637	#define __HAL_RCC_LPTIM1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST)
EricLew	0:80ee8f3b695e	1638
EricLew	0:80ee8f3b695e	1639	#define __HAL_RCC_LPUART1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST)
EricLew	0:80ee8f3b695e	1640
EricLew	0:80ee8f3b695e	1641	#define __HAL_RCC_SWPMI1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_SWPMI1RST)
EricLew	0:80ee8f3b695e	1642
EricLew	0:80ee8f3b695e	1643	#define __HAL_RCC_LPTIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST)
EricLew	0:80ee8f3b695e	1644
EricLew	0:80ee8f3b695e	1645	#define __HAL_RCC_APB1_RELEASE_RESET() WRITE_REG(RCC->APB1RSTR1, 0x00000000)
EricLew	0:80ee8f3b695e	1646
EricLew	0:80ee8f3b695e	1647	#define __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST)
EricLew	0:80ee8f3b695e	1648
EricLew	0:80ee8f3b695e	1649	#define __HAL_RCC_TIM3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST)
EricLew	0:80ee8f3b695e	1650
EricLew	0:80ee8f3b695e	1651	#define __HAL_RCC_TIM4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST)
EricLew	0:80ee8f3b695e	1652
EricLew	0:80ee8f3b695e	1653	#define __HAL_RCC_TIM5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST)
EricLew	0:80ee8f3b695e	1654
EricLew	0:80ee8f3b695e	1655	#define __HAL_RCC_TIM6_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST)
EricLew	0:80ee8f3b695e	1656
EricLew	0:80ee8f3b695e	1657	#define __HAL_RCC_TIM7_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST)
EricLew	0:80ee8f3b695e	1658
EricLew	0:80ee8f3b695e	1659	#if defined(STM32L476xx) \|\| defined(STM32L486xx)
EricLew	0:80ee8f3b695e	1660	#define __HAL_RCC_LCD_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LCDRST)
EricLew	0:80ee8f3b695e	1661	#endif /* STM32L476xx \|\| STM32L486xx */
EricLew	0:80ee8f3b695e	1662
EricLew	0:80ee8f3b695e	1663	#define __HAL_RCC_SPI2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST)
EricLew	0:80ee8f3b695e	1664
EricLew	0:80ee8f3b695e	1665	#define __HAL_RCC_SPI3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST)
EricLew	0:80ee8f3b695e	1666
EricLew	0:80ee8f3b695e	1667	#define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST)
EricLew	0:80ee8f3b695e	1668
EricLew	0:80ee8f3b695e	1669	#define __HAL_RCC_USART3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST)
EricLew	0:80ee8f3b695e	1670
EricLew	0:80ee8f3b695e	1671	#define __HAL_RCC_UART4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST)
EricLew	0:80ee8f3b695e	1672
EricLew	0:80ee8f3b695e	1673	#define __HAL_RCC_UART5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST)
EricLew	0:80ee8f3b695e	1674
EricLew	0:80ee8f3b695e	1675	#define __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST)
EricLew	0:80ee8f3b695e	1676
EricLew	0:80ee8f3b695e	1677	#define __HAL_RCC_I2C2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST)
EricLew	0:80ee8f3b695e	1678
EricLew	0:80ee8f3b695e	1679	#define __HAL_RCC_I2C3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST)
EricLew	0:80ee8f3b695e	1680
EricLew	0:80ee8f3b695e	1681	#define __HAL_RCC_CAN1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN1RST)
EricLew	0:80ee8f3b695e	1682
EricLew	0:80ee8f3b695e	1683	#define __HAL_RCC_PWR_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST)
EricLew	0:80ee8f3b695e	1684
EricLew	0:80ee8f3b695e	1685	#define __HAL_RCC_DAC1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_DAC1RST)
EricLew	0:80ee8f3b695e	1686
EricLew	0:80ee8f3b695e	1687	#define __HAL_RCC_OPAMP_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_OPAMPRST)
EricLew	0:80ee8f3b695e	1688
EricLew	0:80ee8f3b695e	1689	#define __HAL_RCC_LPTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST)
EricLew	0:80ee8f3b695e	1690
EricLew	0:80ee8f3b695e	1691	#define __HAL_RCC_LPUART1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST)
EricLew	0:80ee8f3b695e	1692
EricLew	0:80ee8f3b695e	1693	#define __HAL_RCC_SWPMI1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_SWPMI1RST)
EricLew	0:80ee8f3b695e	1694
EricLew	0:80ee8f3b695e	1695	#define __HAL_RCC_LPTIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST)
EricLew	0:80ee8f3b695e	1696
EricLew	0:80ee8f3b695e	1697	/**
EricLew	0:80ee8f3b695e	1698	* @}
EricLew	0:80ee8f3b695e	1699	*/
EricLew	0:80ee8f3b695e	1700
EricLew	0:80ee8f3b695e	1701	/** @defgroup RCC_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset
EricLew	0:80ee8f3b695e	1702	* @brief Force or release APB2 peripheral reset.
EricLew	0:80ee8f3b695e	1703	* @{
EricLew	0:80ee8f3b695e	1704	*/
EricLew	0:80ee8f3b695e	1705	#define __HAL_RCC_APB2_FORCE_RESET() WRITE_REG(RCC->APB2RSTR, 0xFFFFFFFF)
EricLew	0:80ee8f3b695e	1706
EricLew	0:80ee8f3b695e	1707	#define __HAL_RCC_SYSCFG_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST)
EricLew	0:80ee8f3b695e	1708
EricLew	0:80ee8f3b695e	1709	#define __HAL_RCC_SDMMC1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SDMMC1RST)
EricLew	0:80ee8f3b695e	1710
EricLew	0:80ee8f3b695e	1711	#define __HAL_RCC_TIM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST)
EricLew	0:80ee8f3b695e	1712
EricLew	0:80ee8f3b695e	1713	#define __HAL_RCC_SPI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST)
EricLew	0:80ee8f3b695e	1714
EricLew	0:80ee8f3b695e	1715	#define __HAL_RCC_TIM8_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST)
EricLew	0:80ee8f3b695e	1716
EricLew	0:80ee8f3b695e	1717	#define __HAL_RCC_USART1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST)
EricLew	0:80ee8f3b695e	1718
EricLew	0:80ee8f3b695e	1719	#define __HAL_RCC_TIM15_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST)
EricLew	0:80ee8f3b695e	1720
EricLew	0:80ee8f3b695e	1721	#define __HAL_RCC_TIM16_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST)
EricLew	0:80ee8f3b695e	1722
EricLew	0:80ee8f3b695e	1723	#define __HAL_RCC_TIM17_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST)
EricLew	0:80ee8f3b695e	1724
EricLew	0:80ee8f3b695e	1725	#define __HAL_RCC_SAI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST)
EricLew	0:80ee8f3b695e	1726
EricLew	0:80ee8f3b695e	1727	#define __HAL_RCC_SAI2_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST)
EricLew	0:80ee8f3b695e	1728
EricLew	0:80ee8f3b695e	1729	#define __HAL_RCC_DFSDM_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DFSDMRST)
EricLew	0:80ee8f3b695e	1730
EricLew	0:80ee8f3b695e	1731	#define __HAL_RCC_APB2_RELEASE_RESET() WRITE_REG(RCC->APB2RSTR, 0x00000000)
EricLew	0:80ee8f3b695e	1732
EricLew	0:80ee8f3b695e	1733	#define __HAL_RCC_SYSCFG_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST)
EricLew	0:80ee8f3b695e	1734
EricLew	0:80ee8f3b695e	1735	#define __HAL_RCC_SDMMC1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SDMMC1RST)
EricLew	0:80ee8f3b695e	1736
EricLew	0:80ee8f3b695e	1737	#define __HAL_RCC_TIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST)
EricLew	0:80ee8f3b695e	1738
EricLew	0:80ee8f3b695e	1739	#define __HAL_RCC_SPI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST)
EricLew	0:80ee8f3b695e	1740
EricLew	0:80ee8f3b695e	1741	#define __HAL_RCC_TIM8_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST)
EricLew	0:80ee8f3b695e	1742
EricLew	0:80ee8f3b695e	1743	#define __HAL_RCC_USART1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST)
EricLew	0:80ee8f3b695e	1744
EricLew	0:80ee8f3b695e	1745	#define __HAL_RCC_TIM15_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST)
EricLew	0:80ee8f3b695e	1746
EricLew	0:80ee8f3b695e	1747	#define __HAL_RCC_TIM16_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST)
EricLew	0:80ee8f3b695e	1748
EricLew	0:80ee8f3b695e	1749	#define __HAL_RCC_TIM17_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST)
EricLew	0:80ee8f3b695e	1750
EricLew	0:80ee8f3b695e	1751	#define __HAL_RCC_SAI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST)
EricLew	0:80ee8f3b695e	1752
EricLew	0:80ee8f3b695e	1753	#define __HAL_RCC_SAI2_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST)
EricLew	0:80ee8f3b695e	1754
EricLew	0:80ee8f3b695e	1755	#define __HAL_RCC_DFSDM_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DFSDMRST)
EricLew	0:80ee8f3b695e	1756
EricLew	0:80ee8f3b695e	1757	/**
EricLew	0:80ee8f3b695e	1758	* @}
EricLew	0:80ee8f3b695e	1759	*/
EricLew	0:80ee8f3b695e	1760
EricLew	0:80ee8f3b695e	1761	/** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable AHB1 Peripheral Clock Sleep Enable Disable
EricLew	0:80ee8f3b695e	1762	* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
EricLew	0:80ee8f3b695e	1763	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
EricLew	0:80ee8f3b695e	1764	* power consumption.
EricLew	0:80ee8f3b695e	1765	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
EricLew	0:80ee8f3b695e	1766	* @note By default, all peripheral clocks are enabled during SLEEP mode.
EricLew	0:80ee8f3b695e	1767	* @{
EricLew	0:80ee8f3b695e	1768	*/
EricLew	0:80ee8f3b695e	1769
EricLew	0:80ee8f3b695e	1770	#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN)
EricLew	0:80ee8f3b695e	1771
EricLew	0:80ee8f3b695e	1772	#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN)
EricLew	0:80ee8f3b695e	1773
EricLew	0:80ee8f3b695e	1774	#define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN)
EricLew	0:80ee8f3b695e	1775
EricLew	0:80ee8f3b695e	1776	#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN)
EricLew	0:80ee8f3b695e	1777
EricLew	0:80ee8f3b695e	1778	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN)
EricLew	0:80ee8f3b695e	1779
EricLew	0:80ee8f3b695e	1780	#define __HAL_RCC_TSC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN)
EricLew	0:80ee8f3b695e	1781
EricLew	0:80ee8f3b695e	1782	#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN)
EricLew	0:80ee8f3b695e	1783
EricLew	0:80ee8f3b695e	1784	#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN)
EricLew	0:80ee8f3b695e	1785
EricLew	0:80ee8f3b695e	1786	#define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN)
EricLew	0:80ee8f3b695e	1787
EricLew	0:80ee8f3b695e	1788	#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN)
EricLew	0:80ee8f3b695e	1789
EricLew	0:80ee8f3b695e	1790	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN)
EricLew	0:80ee8f3b695e	1791
EricLew	0:80ee8f3b695e	1792	#define __HAL_RCC_TSC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN)
EricLew	0:80ee8f3b695e	1793
EricLew	0:80ee8f3b695e	1794	/**
EricLew	0:80ee8f3b695e	1795	* @}
EricLew	0:80ee8f3b695e	1796	*/
EricLew	0:80ee8f3b695e	1797
EricLew	0:80ee8f3b695e	1798	/** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable AHB2 Peripheral Clock Sleep Enable Disable
EricLew	0:80ee8f3b695e	1799	* @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
EricLew	0:80ee8f3b695e	1800	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
EricLew	0:80ee8f3b695e	1801	* power consumption.
EricLew	0:80ee8f3b695e	1802	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
EricLew	0:80ee8f3b695e	1803	* @note By default, all peripheral clocks are enabled during SLEEP mode.
EricLew	0:80ee8f3b695e	1804	* @{
EricLew	0:80ee8f3b695e	1805	*/
EricLew	0:80ee8f3b695e	1806
EricLew	0:80ee8f3b695e	1807	#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN)
EricLew	0:80ee8f3b695e	1808
EricLew	0:80ee8f3b695e	1809	#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN)
EricLew	0:80ee8f3b695e	1810
EricLew	0:80ee8f3b695e	1811	#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN)
EricLew	0:80ee8f3b695e	1812
EricLew	0:80ee8f3b695e	1813	#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN)
EricLew	0:80ee8f3b695e	1814
EricLew	0:80ee8f3b695e	1815	#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN)
EricLew	0:80ee8f3b695e	1816
EricLew	0:80ee8f3b695e	1817	#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN)
EricLew	0:80ee8f3b695e	1818
EricLew	0:80ee8f3b695e	1819	#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN)
EricLew	0:80ee8f3b695e	1820
EricLew	0:80ee8f3b695e	1821	#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN)
EricLew	0:80ee8f3b695e	1822
EricLew	0:80ee8f3b695e	1823	#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN)
EricLew	0:80ee8f3b695e	1824
EricLew	0:80ee8f3b695e	1825	#if defined(STM32L475xx) \|\| defined(STM32L476xx) \|\| defined(STM32L485xx) \|\| defined(STM32L486xx)
EricLew	0:80ee8f3b695e	1826	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN)
EricLew	0:80ee8f3b695e	1827	#endif /* STM32L475xx \|\| STM32L476xx \|\| STM32L485xx \|\| STM32L486xx */
EricLew	0:80ee8f3b695e	1828
EricLew	0:80ee8f3b695e	1829	#define __HAL_RCC_ADC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN)
EricLew	0:80ee8f3b695e	1830
EricLew	0:80ee8f3b695e	1831	#if defined(STM32L485xx) \|\| defined(STM32L486xx)
EricLew	0:80ee8f3b695e	1832	#define __HAL_RCC_AES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN)
EricLew	0:80ee8f3b695e	1833	#endif /* STM32L485xx \|\| STM32L486xx */
EricLew	0:80ee8f3b695e	1834
EricLew	0:80ee8f3b695e	1835	#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN)
EricLew	0:80ee8f3b695e	1836
EricLew	0:80ee8f3b695e	1837	#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN)
EricLew	0:80ee8f3b695e	1838
EricLew	0:80ee8f3b695e	1839	#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN)
EricLew	0:80ee8f3b695e	1840
EricLew	0:80ee8f3b695e	1841	#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN)
EricLew	0:80ee8f3b695e	1842
EricLew	0:80ee8f3b695e	1843	#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN)
EricLew	0:80ee8f3b695e	1844
EricLew	0:80ee8f3b695e	1845	#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN)
EricLew	0:80ee8f3b695e	1846
EricLew	0:80ee8f3b695e	1847	#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN)
EricLew	0:80ee8f3b695e	1848
EricLew	0:80ee8f3b695e	1849	#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN)
EricLew	0:80ee8f3b695e	1850
EricLew	0:80ee8f3b695e	1851	#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN)
EricLew	0:80ee8f3b695e	1852
EricLew	0:80ee8f3b695e	1853	#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN)
EricLew	0:80ee8f3b695e	1854
EricLew	0:80ee8f3b695e	1855	#if defined(STM32L475xx) \|\| defined(STM32L476xx) \|\| defined(STM32L485xx) \|\| defined(STM32L486xx)
EricLew	0:80ee8f3b695e	1856	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN)
EricLew	0:80ee8f3b695e	1857	#endif /* STM32L475xx \|\| STM32L476xx \|\| STM32L485xx \|\| STM32L486xx */
EricLew	0:80ee8f3b695e	1858
EricLew	0:80ee8f3b695e	1859	#define __HAL_RCC_ADC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN)
EricLew	0:80ee8f3b695e	1860
EricLew	0:80ee8f3b695e	1861	#if defined(STM32L485xx) \|\| defined(STM32L486xx)
EricLew	0:80ee8f3b695e	1862	#define __HAL_RCC_AES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN)
EricLew	0:80ee8f3b695e	1863	#endif /* STM32L485xx \|\| STM32L486xx */
EricLew	0:80ee8f3b695e	1864
EricLew	0:80ee8f3b695e	1865	#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN)
EricLew	0:80ee8f3b695e	1866
EricLew	0:80ee8f3b695e	1867	/**
EricLew	0:80ee8f3b695e	1868	* @}
EricLew	0:80ee8f3b695e	1869	*/
EricLew	0:80ee8f3b695e	1870
EricLew	0:80ee8f3b695e	1871	/** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable AHB3 Peripheral Clock Sleep Enable Disable
EricLew	0:80ee8f3b695e	1872	* @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
EricLew	0:80ee8f3b695e	1873	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
EricLew	0:80ee8f3b695e	1874	* power consumption.
EricLew	0:80ee8f3b695e	1875	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
EricLew	0:80ee8f3b695e	1876	* @note By default, all peripheral clocks are enabled during SLEEP mode.
EricLew	0:80ee8f3b695e	1877	* @{
EricLew	0:80ee8f3b695e	1878	*/
EricLew	0:80ee8f3b695e	1879
EricLew	0:80ee8f3b695e	1880	#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN)
EricLew	0:80ee8f3b695e	1881
EricLew	0:80ee8f3b695e	1882	#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN)
EricLew	0:80ee8f3b695e	1883
EricLew	0:80ee8f3b695e	1884	#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN)
EricLew	0:80ee8f3b695e	1885
EricLew	0:80ee8f3b695e	1886	#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN)
EricLew	0:80ee8f3b695e	1887
EricLew	0:80ee8f3b695e	1888	/**
EricLew	0:80ee8f3b695e	1889	* @}
EricLew	0:80ee8f3b695e	1890	*/
EricLew	0:80ee8f3b695e	1891
EricLew	0:80ee8f3b695e	1892	/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable
EricLew	0:80ee8f3b695e	1893	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
EricLew	0:80ee8f3b695e	1894	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
EricLew	0:80ee8f3b695e	1895	* power consumption.
EricLew	0:80ee8f3b695e	1896	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
EricLew	0:80ee8f3b695e	1897	* @note By default, all peripheral clocks are enabled during SLEEP mode.
EricLew	0:80ee8f3b695e	1898	* @{
EricLew	0:80ee8f3b695e	1899	*/
EricLew	0:80ee8f3b695e	1900
EricLew	0:80ee8f3b695e	1901	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN)
EricLew	0:80ee8f3b695e	1902
EricLew	0:80ee8f3b695e	1903	#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN)
EricLew	0:80ee8f3b695e	1904
EricLew	0:80ee8f3b695e	1905	#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN)
EricLew	0:80ee8f3b695e	1906
EricLew	0:80ee8f3b695e	1907	#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN)
EricLew	0:80ee8f3b695e	1908
EricLew	0:80ee8f3b695e	1909	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN)
EricLew	0:80ee8f3b695e	1910
EricLew	0:80ee8f3b695e	1911	#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN)
EricLew	0:80ee8f3b695e	1912
EricLew	0:80ee8f3b695e	1913	#if defined(STM32L476xx) \|\| defined(STM32L486xx)
EricLew	0:80ee8f3b695e	1914	#define __HAL_RCC_LCD_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN)
EricLew	0:80ee8f3b695e	1915	#endif /* STM32L476xx \|\| STM32L486xx */
EricLew	0:80ee8f3b695e	1916
EricLew	0:80ee8f3b695e	1917	#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN)
EricLew	0:80ee8f3b695e	1918
EricLew	0:80ee8f3b695e	1919	#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN)
EricLew	0:80ee8f3b695e	1920
EricLew	0:80ee8f3b695e	1921	#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN)
EricLew	0:80ee8f3b695e	1922
EricLew	0:80ee8f3b695e	1923	#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN)
EricLew	0:80ee8f3b695e	1924
EricLew	0:80ee8f3b695e	1925	#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN)
EricLew	0:80ee8f3b695e	1926
EricLew	0:80ee8f3b695e	1927	#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN)
EricLew	0:80ee8f3b695e	1928
EricLew	0:80ee8f3b695e	1929	#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN)
EricLew	0:80ee8f3b695e	1930
EricLew	0:80ee8f3b695e	1931	#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN)
EricLew	0:80ee8f3b695e	1932
EricLew	0:80ee8f3b695e	1933	#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN)
EricLew	0:80ee8f3b695e	1934
EricLew	0:80ee8f3b695e	1935	#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN)
EricLew	0:80ee8f3b695e	1936
EricLew	0:80ee8f3b695e	1937	#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN)
EricLew	0:80ee8f3b695e	1938
EricLew	0:80ee8f3b695e	1939	#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN)
EricLew	0:80ee8f3b695e	1940
EricLew	0:80ee8f3b695e	1941	#define __HAL_RCC_DAC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN)
EricLew	0:80ee8f3b695e	1942
EricLew	0:80ee8f3b695e	1943	#define __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN)
EricLew	0:80ee8f3b695e	1944
EricLew	0:80ee8f3b695e	1945	#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN)
EricLew	0:80ee8f3b695e	1946
EricLew	0:80ee8f3b695e	1947	#define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN)
EricLew	0:80ee8f3b695e	1948
EricLew	0:80ee8f3b695e	1949	#define __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN)
EricLew	0:80ee8f3b695e	1950
EricLew	0:80ee8f3b695e	1951	#define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN)
EricLew	0:80ee8f3b695e	1952
EricLew	0:80ee8f3b695e	1953	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN)
EricLew	0:80ee8f3b695e	1954
EricLew	0:80ee8f3b695e	1955	#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN)
EricLew	0:80ee8f3b695e	1956
EricLew	0:80ee8f3b695e	1957	#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN)
EricLew	0:80ee8f3b695e	1958
EricLew	0:80ee8f3b695e	1959	#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN)
EricLew	0:80ee8f3b695e	1960
EricLew	0:80ee8f3b695e	1961	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN)
EricLew	0:80ee8f3b695e	1962
EricLew	0:80ee8f3b695e	1963	#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN)
EricLew	0:80ee8f3b695e	1964
EricLew	0:80ee8f3b695e	1965	#if defined(STM32L476xx) \|\| defined(STM32L486xx)
EricLew	0:80ee8f3b695e	1966	#define __HAL_RCC_LCD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN)
EricLew	0:80ee8f3b695e	1967	#endif /* STM32L476xx \|\| STM32L486xx */
EricLew	0:80ee8f3b695e	1968
EricLew	0:80ee8f3b695e	1969	#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN)
EricLew	0:80ee8f3b695e	1970
EricLew	0:80ee8f3b695e	1971	#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN)
EricLew	0:80ee8f3b695e	1972
EricLew	0:80ee8f3b695e	1973	#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN)
EricLew	0:80ee8f3b695e	1974
EricLew	0:80ee8f3b695e	1975	#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN)
EricLew	0:80ee8f3b695e	1976
EricLew	0:80ee8f3b695e	1977	#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN)
EricLew	0:80ee8f3b695e	1978
EricLew	0:80ee8f3b695e	1979	#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN)
EricLew	0:80ee8f3b695e	1980
EricLew	0:80ee8f3b695e	1981	#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN)
EricLew	0:80ee8f3b695e	1982
EricLew	0:80ee8f3b695e	1983	#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN)
EricLew	0:80ee8f3b695e	1984
EricLew	0:80ee8f3b695e	1985	#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN)
EricLew	0:80ee8f3b695e	1986
EricLew	0:80ee8f3b695e	1987	#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN)
EricLew	0:80ee8f3b695e	1988
EricLew	0:80ee8f3b695e	1989	#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN)
EricLew	0:80ee8f3b695e	1990
EricLew	0:80ee8f3b695e	1991	#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN)
EricLew	0:80ee8f3b695e	1992
EricLew	0:80ee8f3b695e	1993	#define __HAL_RCC_DAC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN)
EricLew	0:80ee8f3b695e	1994
EricLew	0:80ee8f3b695e	1995	#define __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN)
EricLew	0:80ee8f3b695e	1996
EricLew	0:80ee8f3b695e	1997	#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN)
EricLew	0:80ee8f3b695e	1998
EricLew	0:80ee8f3b695e	1999	#define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN)
EricLew	0:80ee8f3b695e	2000
EricLew	0:80ee8f3b695e	2001	#define __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN)
EricLew	0:80ee8f3b695e	2002
EricLew	0:80ee8f3b695e	2003	#define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN)
EricLew	0:80ee8f3b695e	2004
EricLew	0:80ee8f3b695e	2005	/**
EricLew	0:80ee8f3b695e	2006	* @}
EricLew	0:80ee8f3b695e	2007	*/
EricLew	0:80ee8f3b695e	2008
EricLew	0:80ee8f3b695e	2009	/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable
EricLew	0:80ee8f3b695e	2010	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
EricLew	0:80ee8f3b695e	2011	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
EricLew	0:80ee8f3b695e	2012	* power consumption.
EricLew	0:80ee8f3b695e	2013	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
EricLew	0:80ee8f3b695e	2014	* @note By default, all peripheral clocks are enabled during SLEEP mode.
EricLew	0:80ee8f3b695e	2015	* @{
EricLew	0:80ee8f3b695e	2016	*/
EricLew	0:80ee8f3b695e	2017
EricLew	0:80ee8f3b695e	2018	#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN)
EricLew	0:80ee8f3b695e	2019
EricLew	0:80ee8f3b695e	2020	#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN)
EricLew	0:80ee8f3b695e	2021
EricLew	0:80ee8f3b695e	2022	#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN)
EricLew	0:80ee8f3b695e	2023
EricLew	0:80ee8f3b695e	2024	#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN)
EricLew	0:80ee8f3b695e	2025
EricLew	0:80ee8f3b695e	2026	#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN)
EricLew	0:80ee8f3b695e	2027
EricLew	0:80ee8f3b695e	2028	#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN)
EricLew	0:80ee8f3b695e	2029
EricLew	0:80ee8f3b695e	2030	#define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN)
EricLew	0:80ee8f3b695e	2031
EricLew	0:80ee8f3b695e	2032	#define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN)
EricLew	0:80ee8f3b695e	2033
EricLew	0:80ee8f3b695e	2034	#define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN)
EricLew	0:80ee8f3b695e	2035
EricLew	0:80ee8f3b695e	2036	#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN)
EricLew	0:80ee8f3b695e	2037
EricLew	0:80ee8f3b695e	2038	#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN)
EricLew	0:80ee8f3b695e	2039
EricLew	0:80ee8f3b695e	2040	#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDMSMEN)
EricLew	0:80ee8f3b695e	2041
EricLew	0:80ee8f3b695e	2042	#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN)
EricLew	0:80ee8f3b695e	2043
EricLew	0:80ee8f3b695e	2044	#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN)
EricLew	0:80ee8f3b695e	2045
EricLew	0:80ee8f3b695e	2046	#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN)
EricLew	0:80ee8f3b695e	2047
EricLew	0:80ee8f3b695e	2048	#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN)
EricLew	0:80ee8f3b695e	2049
EricLew	0:80ee8f3b695e	2050	#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN)
EricLew	0:80ee8f3b695e	2051
EricLew	0:80ee8f3b695e	2052	#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN)
EricLew	0:80ee8f3b695e	2053
EricLew	0:80ee8f3b695e	2054	#define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN)
EricLew	0:80ee8f3b695e	2055
EricLew	0:80ee8f3b695e	2056	#define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN)
EricLew	0:80ee8f3b695e	2057
EricLew	0:80ee8f3b695e	2058	#define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN)
EricLew	0:80ee8f3b695e	2059
EricLew	0:80ee8f3b695e	2060	#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN)
EricLew	0:80ee8f3b695e	2061
EricLew	0:80ee8f3b695e	2062	#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN)
EricLew	0:80ee8f3b695e	2063
EricLew	0:80ee8f3b695e	2064	#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDMSMEN)
EricLew	0:80ee8f3b695e	2065
EricLew	0:80ee8f3b695e	2066	/**
EricLew	0:80ee8f3b695e	2067	* @}
EricLew	0:80ee8f3b695e	2068	*/
EricLew	0:80ee8f3b695e	2069
EricLew	0:80ee8f3b695e	2070	/** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable_Status AHB1 Peripheral Clock Sleep Enabled or Disabled Status
EricLew	0:80ee8f3b695e	2071	* @brief Check whether the AHB1 peripheral clock during Low Power (Sleep) mode is enabled or not.
EricLew	0:80ee8f3b695e	2072	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
EricLew	0:80ee8f3b695e	2073	* power consumption.
EricLew	0:80ee8f3b695e	2074	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
EricLew	0:80ee8f3b695e	2075	* @note By default, all peripheral clocks are enabled during SLEEP mode.
EricLew	0:80ee8f3b695e	2076	* @{
EricLew	0:80ee8f3b695e	2077	*/
EricLew	0:80ee8f3b695e	2078
EricLew	0:80ee8f3b695e	2079	#define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) != RESET)
EricLew	0:80ee8f3b695e	2080
EricLew	0:80ee8f3b695e	2081	#define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) != RESET)
EricLew	0:80ee8f3b695e	2082
EricLew	0:80ee8f3b695e	2083	#define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) != RESET)
EricLew	0:80ee8f3b695e	2084
EricLew	0:80ee8f3b695e	2085	#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) != RESET)
EricLew	0:80ee8f3b695e	2086
EricLew	0:80ee8f3b695e	2087	#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) != RESET)
EricLew	0:80ee8f3b695e	2088
EricLew	0:80ee8f3b695e	2089	#define __HAL_RCC_TSC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) != RESET)
EricLew	0:80ee8f3b695e	2090
EricLew	0:80ee8f3b695e	2091	#define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) == RESET)
EricLew	0:80ee8f3b695e	2092
EricLew	0:80ee8f3b695e	2093	#define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) == RESET)
EricLew	0:80ee8f3b695e	2094
EricLew	0:80ee8f3b695e	2095	#define __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) == RESET)
EricLew	0:80ee8f3b695e	2096
EricLew	0:80ee8f3b695e	2097	#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) == RESET)
EricLew	0:80ee8f3b695e	2098
EricLew	0:80ee8f3b695e	2099	#define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) == RESET)
EricLew	0:80ee8f3b695e	2100
EricLew	0:80ee8f3b695e	2101	#define __HAL_RCC_TSC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) == RESET)
EricLew	0:80ee8f3b695e	2102
EricLew	0:80ee8f3b695e	2103	/**
EricLew	0:80ee8f3b695e	2104	* @}
EricLew	0:80ee8f3b695e	2105	*/
EricLew	0:80ee8f3b695e	2106
EricLew	0:80ee8f3b695e	2107	/** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable_Status AHB2 Peripheral Clock Sleep Enabled or Disabled Status
EricLew	0:80ee8f3b695e	2108	* @brief Check whether the AHB2 peripheral clock during Low Power (Sleep) mode is enabled or not.
EricLew	0:80ee8f3b695e	2109	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
EricLew	0:80ee8f3b695e	2110	* power consumption.
EricLew	0:80ee8f3b695e	2111	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
EricLew	0:80ee8f3b695e	2112	* @note By default, all peripheral clocks are enabled during SLEEP mode.
EricLew	0:80ee8f3b695e	2113	* @{
EricLew	0:80ee8f3b695e	2114	*/
EricLew	0:80ee8f3b695e	2115
EricLew	0:80ee8f3b695e	2116	#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) != RESET)
EricLew	0:80ee8f3b695e	2117
EricLew	0:80ee8f3b695e	2118	#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) != RESET)
EricLew	0:80ee8f3b695e	2119
EricLew	0:80ee8f3b695e	2120	#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) != RESET)
EricLew	0:80ee8f3b695e	2121
EricLew	0:80ee8f3b695e	2122	#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) != RESET)
EricLew	0:80ee8f3b695e	2123
EricLew	0:80ee8f3b695e	2124	#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) != RESET)
EricLew	0:80ee8f3b695e	2125
EricLew	0:80ee8f3b695e	2126	#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) != RESET)
EricLew	0:80ee8f3b695e	2127
EricLew	0:80ee8f3b695e	2128	#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) != RESET)
EricLew	0:80ee8f3b695e	2129
EricLew	0:80ee8f3b695e	2130	#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) != RESET)
EricLew	0:80ee8f3b695e	2131
EricLew	0:80ee8f3b695e	2132	#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) != RESET)
EricLew	0:80ee8f3b695e	2133
EricLew	0:80ee8f3b695e	2134	#if defined(STM32L475xx) \|\| defined(STM32L476xx) \|\| defined(STM32L485xx) \|\| defined(STM32L486xx)
EricLew	0:80ee8f3b695e	2135	#define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) != RESET)
EricLew	0:80ee8f3b695e	2136	#endif /* STM32L475xx \|\| STM32L476xx \|\| STM32L485xx \|\| STM32L486xx */
EricLew	0:80ee8f3b695e	2137
EricLew	0:80ee8f3b695e	2138	#define __HAL_RCC_ADC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) != RESET)
EricLew	0:80ee8f3b695e	2139
EricLew	0:80ee8f3b695e	2140	#if defined(STM32L485xx) \|\| defined(STM32L486xx)
EricLew	0:80ee8f3b695e	2141	#define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) != RESET)
EricLew	0:80ee8f3b695e	2142	#endif /* STM32L485xx \|\| STM32L486xx */
EricLew	0:80ee8f3b695e	2143
EricLew	0:80ee8f3b695e	2144	#define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) != RESET)
EricLew	0:80ee8f3b695e	2145
EricLew	0:80ee8f3b695e	2146	#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) == RESET)
EricLew	0:80ee8f3b695e	2147
EricLew	0:80ee8f3b695e	2148	#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) == RESET)
EricLew	0:80ee8f3b695e	2149
EricLew	0:80ee8f3b695e	2150	#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) == RESET)
EricLew	0:80ee8f3b695e	2151
EricLew	0:80ee8f3b695e	2152	#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) == RESET)
EricLew	0:80ee8f3b695e	2153
EricLew	0:80ee8f3b695e	2154	#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) == RESET)
EricLew	0:80ee8f3b695e	2155
EricLew	0:80ee8f3b695e	2156	#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) == RESET)
EricLew	0:80ee8f3b695e	2157
EricLew	0:80ee8f3b695e	2158	#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) == RESET)
EricLew	0:80ee8f3b695e	2159
EricLew	0:80ee8f3b695e	2160	#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) == RESET)
EricLew	0:80ee8f3b695e	2161
EricLew	0:80ee8f3b695e	2162	#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) == RESET)
EricLew	0:80ee8f3b695e	2163
EricLew	0:80ee8f3b695e	2164	#if defined(STM32L475xx) \|\| defined(STM32L476xx) \|\| defined(STM32L485xx) \|\| defined(STM32L486xx)
EricLew	0:80ee8f3b695e	2165	#define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) == RESET)
EricLew	0:80ee8f3b695e	2166	#endif /* STM32L475xx \|\| STM32L476xx \|\| STM32L485xx \|\| STM32L486xx */
EricLew	0:80ee8f3b695e	2167
EricLew	0:80ee8f3b695e	2168	#define __HAL_RCC_ADC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) == RESET)
EricLew	0:80ee8f3b695e	2169
EricLew	0:80ee8f3b695e	2170	#if defined(STM32L485xx) \|\| defined(STM32L486xx)
EricLew	0:80ee8f3b695e	2171	#define __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) == RESET)
EricLew	0:80ee8f3b695e	2172	#endif /* STM32L485xx \|\| STM32L486xx */
EricLew	0:80ee8f3b695e	2173
EricLew	0:80ee8f3b695e	2174	#define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) == RESET)
EricLew	0:80ee8f3b695e	2175
EricLew	0:80ee8f3b695e	2176	/**
EricLew	0:80ee8f3b695e	2177	* @}
EricLew	0:80ee8f3b695e	2178	*/
EricLew	0:80ee8f3b695e	2179
EricLew	0:80ee8f3b695e	2180	/** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable_Status AHB3 Peripheral Clock Sleep Enabled or Disabled Status
EricLew	0:80ee8f3b695e	2181	* @brief Check whether the AHB3 peripheral clock during Low Power (Sleep) mode is enabled or not.
EricLew	0:80ee8f3b695e	2182	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
EricLew	0:80ee8f3b695e	2183	* power consumption.
EricLew	0:80ee8f3b695e	2184	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
EricLew	0:80ee8f3b695e	2185	* @note By default, all peripheral clocks are enabled during SLEEP mode.
EricLew	0:80ee8f3b695e	2186	* @{
EricLew	0:80ee8f3b695e	2187	*/
EricLew	0:80ee8f3b695e	2188
EricLew	0:80ee8f3b695e	2189	#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) != RESET)
EricLew	0:80ee8f3b695e	2190
EricLew	0:80ee8f3b695e	2191	#define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) != RESET)
EricLew	0:80ee8f3b695e	2192
EricLew	0:80ee8f3b695e	2193	#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) == RESET)
EricLew	0:80ee8f3b695e	2194
EricLew	0:80ee8f3b695e	2195	#define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) == RESET)
EricLew	0:80ee8f3b695e	2196
EricLew	0:80ee8f3b695e	2197	/**
EricLew	0:80ee8f3b695e	2198	* @}
EricLew	0:80ee8f3b695e	2199	*/
EricLew	0:80ee8f3b695e	2200
EricLew	0:80ee8f3b695e	2201	/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enabled or Disabled Status
EricLew	0:80ee8f3b695e	2202	* @brief Check whether the APB1 peripheral clock during Low Power (Sleep) mode is enabled or not.
EricLew	0:80ee8f3b695e	2203	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
EricLew	0:80ee8f3b695e	2204	* power consumption.
EricLew	0:80ee8f3b695e	2205	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
EricLew	0:80ee8f3b695e	2206	* @note By default, all peripheral clocks are enabled during SLEEP mode.
EricLew	0:80ee8f3b695e	2207	* @{
EricLew	0:80ee8f3b695e	2208	*/
EricLew	0:80ee8f3b695e	2209
EricLew	0:80ee8f3b695e	2210	#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) != RESET)
EricLew	0:80ee8f3b695e	2211
EricLew	0:80ee8f3b695e	2212	#define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) != RESET)
EricLew	0:80ee8f3b695e	2213
EricLew	0:80ee8f3b695e	2214	#define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) != RESET)
EricLew	0:80ee8f3b695e	2215
EricLew	0:80ee8f3b695e	2216	#define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) != RESET)
EricLew	0:80ee8f3b695e	2217
EricLew	0:80ee8f3b695e	2218	#define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) != RESET)
EricLew	0:80ee8f3b695e	2219
EricLew	0:80ee8f3b695e	2220	#define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) != RESET)
EricLew	0:80ee8f3b695e	2221
EricLew	0:80ee8f3b695e	2222	#if defined(STM32L476xx) \|\| defined(STM32L486xx)
EricLew	0:80ee8f3b695e	2223	#define __HAL_RCC_LCD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) != RESET)
EricLew	0:80ee8f3b695e	2224	#endif /* STM32L476xx \|\| STM32L486xx */
EricLew	0:80ee8f3b695e	2225
EricLew	0:80ee8f3b695e	2226	#define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) != RESET)
EricLew	0:80ee8f3b695e	2227
EricLew	0:80ee8f3b695e	2228	#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) != RESET)
EricLew	0:80ee8f3b695e	2229
EricLew	0:80ee8f3b695e	2230	#define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) != RESET)
EricLew	0:80ee8f3b695e	2231
EricLew	0:80ee8f3b695e	2232	#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) != RESET)
EricLew	0:80ee8f3b695e	2233
EricLew	0:80ee8f3b695e	2234	#define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) != RESET)
EricLew	0:80ee8f3b695e	2235
EricLew	0:80ee8f3b695e	2236	#define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) != RESET)
EricLew	0:80ee8f3b695e	2237
EricLew	0:80ee8f3b695e	2238	#define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) != RESET)
EricLew	0:80ee8f3b695e	2239
EricLew	0:80ee8f3b695e	2240	#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) != RESET)
EricLew	0:80ee8f3b695e	2241
EricLew	0:80ee8f3b695e	2242	#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) != RESET)
EricLew	0:80ee8f3b695e	2243
EricLew	0:80ee8f3b695e	2244	#define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) != RESET)
EricLew	0:80ee8f3b695e	2245
EricLew	0:80ee8f3b695e	2246	#define __HAL_RCC_CAN1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) != RESET)
EricLew	0:80ee8f3b695e	2247
EricLew	0:80ee8f3b695e	2248	#define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) != RESET)
EricLew	0:80ee8f3b695e	2249
EricLew	0:80ee8f3b695e	2250	#define __HAL_RCC_DAC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) != RESET)
EricLew	0:80ee8f3b695e	2251
EricLew	0:80ee8f3b695e	2252	#define __HAL_RCC_OPAMP_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) != RESET)
EricLew	0:80ee8f3b695e	2253
EricLew	0:80ee8f3b695e	2254	#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) != RESET)
EricLew	0:80ee8f3b695e	2255
EricLew	0:80ee8f3b695e	2256	#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) != RESET)
EricLew	0:80ee8f3b695e	2257
EricLew	0:80ee8f3b695e	2258	#define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) != RESET)
EricLew	0:80ee8f3b695e	2259
EricLew	0:80ee8f3b695e	2260	#define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) != RESET)
EricLew	0:80ee8f3b695e	2261
EricLew	0:80ee8f3b695e	2262	#define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) == RESET)
EricLew	0:80ee8f3b695e	2263
EricLew	0:80ee8f3b695e	2264	#define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) == RESET)
EricLew	0:80ee8f3b695e	2265
EricLew	0:80ee8f3b695e	2266	#define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) == RESET)
EricLew	0:80ee8f3b695e	2267
EricLew	0:80ee8f3b695e	2268	#define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) == RESET)
EricLew	0:80ee8f3b695e	2269
EricLew	0:80ee8f3b695e	2270	#define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) == RESET)
EricLew	0:80ee8f3b695e	2271
EricLew	0:80ee8f3b695e	2272	#define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) == RESET)
EricLew	0:80ee8f3b695e	2273
EricLew	0:80ee8f3b695e	2274	#if defined(STM32L476xx) \|\| defined(STM32L486xx)
EricLew	0:80ee8f3b695e	2275	#define __HAL_RCC_LCD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) == RESET)
EricLew	0:80ee8f3b695e	2276	#endif /* STM32L476xx \|\| STM32L486xx */
EricLew	0:80ee8f3b695e	2277
EricLew	0:80ee8f3b695e	2278	#define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) == RESET)
EricLew	0:80ee8f3b695e	2279
EricLew	0:80ee8f3b695e	2280	#define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) == RESET)
EricLew	0:80ee8f3b695e	2281
EricLew	0:80ee8f3b695e	2282	#define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) == RESET)
EricLew	0:80ee8f3b695e	2283
EricLew	0:80ee8f3b695e	2284	#define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) == RESET)
EricLew	0:80ee8f3b695e	2285
EricLew	0:80ee8f3b695e	2286	#define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) == RESET)
EricLew	0:80ee8f3b695e	2287
EricLew	0:80ee8f3b695e	2288	#define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) == RESET)
EricLew	0:80ee8f3b695e	2289
EricLew	0:80ee8f3b695e	2290	#define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) == RESET)
EricLew	0:80ee8f3b695e	2291
EricLew	0:80ee8f3b695e	2292	#define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) == RESET)
EricLew	0:80ee8f3b695e	2293
EricLew	0:80ee8f3b695e	2294	#define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) == RESET)
EricLew	0:80ee8f3b695e	2295
EricLew	0:80ee8f3b695e	2296	#define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) == RESET)
EricLew	0:80ee8f3b695e	2297
EricLew	0:80ee8f3b695e	2298	#define __HAL_RCC_CAN1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) == RESET)
EricLew	0:80ee8f3b695e	2299
EricLew	0:80ee8f3b695e	2300	#define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) == RESET)
EricLew	0:80ee8f3b695e	2301
EricLew	0:80ee8f3b695e	2302	#define __HAL_RCC_DAC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) == RESET)
EricLew	0:80ee8f3b695e	2303
EricLew	0:80ee8f3b695e	2304	#define __HAL_RCC_OPAMP_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) == RESET)
EricLew	0:80ee8f3b695e	2305
EricLew	0:80ee8f3b695e	2306	#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) == RESET)
EricLew	0:80ee8f3b695e	2307
EricLew	0:80ee8f3b695e	2308	#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) == RESET)
EricLew	0:80ee8f3b695e	2309
EricLew	0:80ee8f3b695e	2310	#define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) == RESET)
EricLew	0:80ee8f3b695e	2311
EricLew	0:80ee8f3b695e	2312	#define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) == RESET)
EricLew	0:80ee8f3b695e	2313
EricLew	0:80ee8f3b695e	2314	/**
EricLew	0:80ee8f3b695e	2315	* @}
EricLew	0:80ee8f3b695e	2316	*/
EricLew	0:80ee8f3b695e	2317
EricLew	0:80ee8f3b695e	2318	/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enabled or Disabled Status
EricLew	0:80ee8f3b695e	2319	* @brief Check whether the APB2 peripheral clock during Low Power (Sleep) mode is enabled or not.
EricLew	0:80ee8f3b695e	2320	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
EricLew	0:80ee8f3b695e	2321	* power consumption.
EricLew	0:80ee8f3b695e	2322	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
EricLew	0:80ee8f3b695e	2323	* @note By default, all peripheral clocks are enabled during SLEEP mode.
EricLew	0:80ee8f3b695e	2324	* @{
EricLew	0:80ee8f3b695e	2325	*/
EricLew	0:80ee8f3b695e	2326
EricLew	0:80ee8f3b695e	2327	#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) != RESET)
EricLew	0:80ee8f3b695e	2328
EricLew	0:80ee8f3b695e	2329	#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) != RESET)
EricLew	0:80ee8f3b695e	2330
EricLew	0:80ee8f3b695e	2331	#define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) != RESET)
EricLew	0:80ee8f3b695e	2332
EricLew	0:80ee8f3b695e	2333	#define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) != RESET)
EricLew	0:80ee8f3b695e	2334
EricLew	0:80ee8f3b695e	2335	#define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) != RESET)
EricLew	0:80ee8f3b695e	2336
EricLew	0:80ee8f3b695e	2337	#define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) != RESET)
EricLew	0:80ee8f3b695e	2338
EricLew	0:80ee8f3b695e	2339	#define __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) != RESET)
EricLew	0:80ee8f3b695e	2340
EricLew	0:80ee8f3b695e	2341	#define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) != RESET)
EricLew	0:80ee8f3b695e	2342
EricLew	0:80ee8f3b695e	2343	#define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) != RESET)
EricLew	0:80ee8f3b695e	2344
EricLew	0:80ee8f3b695e	2345	#define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) != RESET)
EricLew	0:80ee8f3b695e	2346
EricLew	0:80ee8f3b695e	2347	#define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) != RESET)
EricLew	0:80ee8f3b695e	2348
EricLew	0:80ee8f3b695e	2349	#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDMSMEN) != RESET)
EricLew	0:80ee8f3b695e	2350
EricLew	0:80ee8f3b695e	2351	#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) == RESET)
EricLew	0:80ee8f3b695e	2352
EricLew	0:80ee8f3b695e	2353	#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) == RESET)
EricLew	0:80ee8f3b695e	2354
EricLew	0:80ee8f3b695e	2355	#define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) == RESET)
EricLew	0:80ee8f3b695e	2356
EricLew	0:80ee8f3b695e	2357	#define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) == RESET)
EricLew	0:80ee8f3b695e	2358
EricLew	0:80ee8f3b695e	2359	#define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) == RESET)
EricLew	0:80ee8f3b695e	2360
EricLew	0:80ee8f3b695e	2361	#define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) == RESET)
EricLew	0:80ee8f3b695e	2362
EricLew	0:80ee8f3b695e	2363	#define __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) == RESET)
EricLew	0:80ee8f3b695e	2364
EricLew	0:80ee8f3b695e	2365	#define __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) == RESET)
EricLew	0:80ee8f3b695e	2366
EricLew	0:80ee8f3b695e	2367	#define __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) == RESET)
EricLew	0:80ee8f3b695e	2368
EricLew	0:80ee8f3b695e	2369	#define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) == RESET)
EricLew	0:80ee8f3b695e	2370
EricLew	0:80ee8f3b695e	2371	#define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) == RESET)
EricLew	0:80ee8f3b695e	2372
EricLew	0:80ee8f3b695e	2373	#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDMSMEN) == RESET)
EricLew	0:80ee8f3b695e	2374
EricLew	0:80ee8f3b695e	2375	/**
EricLew	0:80ee8f3b695e	2376	* @}
EricLew	0:80ee8f3b695e	2377	*/
EricLew	0:80ee8f3b695e	2378
EricLew	0:80ee8f3b695e	2379	/** @defgroup RCC_Backup_Domain_Reset RCC Backup Domain Reset
EricLew	0:80ee8f3b695e	2380	* @{
EricLew	0:80ee8f3b695e	2381	*/
EricLew	0:80ee8f3b695e	2382
EricLew	0:80ee8f3b695e	2383	/** @brief Macros to force or release the Backup domain reset.
EricLew	0:80ee8f3b695e	2384	* @note This function resets the RTC peripheral (including the backup registers)
EricLew	0:80ee8f3b695e	2385	* and the RTC clock source selection in RCC_CSR register.
EricLew	0:80ee8f3b695e	2386	* @note The BKPSRAM is not affected by this reset.
EricLew	0:80ee8f3b695e	2387	* @retval None
EricLew	0:80ee8f3b695e	2388	*/
EricLew	0:80ee8f3b695e	2389	#define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST)
EricLew	0:80ee8f3b695e	2390
EricLew	0:80ee8f3b695e	2391	#define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST)
EricLew	0:80ee8f3b695e	2392
EricLew	0:80ee8f3b695e	2393	/**
EricLew	0:80ee8f3b695e	2394	* @}
EricLew	0:80ee8f3b695e	2395	*/
EricLew	0:80ee8f3b695e	2396
EricLew	0:80ee8f3b695e	2397	/** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
EricLew	0:80ee8f3b695e	2398	* @{
EricLew	0:80ee8f3b695e	2399	*/
EricLew	0:80ee8f3b695e	2400
EricLew	0:80ee8f3b695e	2401	/** @brief Macros to enable or disable the RTC clock.
EricLew	0:80ee8f3b695e	2402	* @note As the RTC is in the Backup domain and write access is denied to
EricLew	0:80ee8f3b695e	2403	* this domain after reset, you have to enable write access using
EricLew	0:80ee8f3b695e	2404	* HAL_PWR_EnableBkUpAccess() function before to configure the RTC
EricLew	0:80ee8f3b695e	2405	* (to be done once after reset).
EricLew	0:80ee8f3b695e	2406	* @note These macros must be used after the RTC clock source was selected.
EricLew	0:80ee8f3b695e	2407	* @retval None
EricLew	0:80ee8f3b695e	2408	*/
EricLew	0:80ee8f3b695e	2409	#define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
EricLew	0:80ee8f3b695e	2410
EricLew	0:80ee8f3b695e	2411	#define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
EricLew	0:80ee8f3b695e	2412
EricLew	0:80ee8f3b695e	2413	/**
EricLew	0:80ee8f3b695e	2414	* @}
EricLew	0:80ee8f3b695e	2415	*/
EricLew	0:80ee8f3b695e	2416
EricLew	0:80ee8f3b695e	2417	/** @brief Macros to enable or disable the Internal High Speed 16MHz oscillator (HSI).
EricLew	0:80ee8f3b695e	2418	* @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
EricLew	0:80ee8f3b695e	2419	* It is used (enabled by hardware) as system clock source after startup
EricLew	0:80ee8f3b695e	2420	* from Reset, wakeup from STOP and STANDBY mode, or in case of failure
EricLew	0:80ee8f3b695e	2421	* of the HSE used directly or indirectly as system clock (if the Clock
EricLew	0:80ee8f3b695e	2422	* Security System CSS is enabled).
EricLew	0:80ee8f3b695e	2423	* @note HSI can not be stopped if it is used as system clock source. In this case,
EricLew	0:80ee8f3b695e	2424	* you have to select another source of the system clock then stop the HSI.
EricLew	0:80ee8f3b695e	2425	* @note After enabling the HSI, the application software should wait on HSIRDY
EricLew	0:80ee8f3b695e	2426	* flag to be set indicating that HSI clock is stable and can be used as
EricLew	0:80ee8f3b695e	2427	* system clock source.
EricLew	0:80ee8f3b695e	2428	* This parameter can be: ENABLE or DISABLE.
EricLew	0:80ee8f3b695e	2429	* @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
EricLew	0:80ee8f3b695e	2430	* clock cycles.
EricLew	0:80ee8f3b695e	2431	* @retval None
EricLew	0:80ee8f3b695e	2432	*/
EricLew	0:80ee8f3b695e	2433	#define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION)
EricLew	0:80ee8f3b695e	2434
EricLew	0:80ee8f3b695e	2435	#define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
EricLew	0:80ee8f3b695e	2436
EricLew	0:80ee8f3b695e	2437	/** @brief Macro to adjust the Internal High Speed 16MHz oscillator (HSI) calibration value.
EricLew	0:80ee8f3b695e	2438	* @note The calibration is used to compensate for the variations in voltage
EricLew	0:80ee8f3b695e	2439	* and temperature that influence the frequency of the internal HSI RC.
EricLew	0:80ee8f3b695e	2440	* @param __HSICALIBRATIONVALUE__: specifies the calibration trimming value
EricLew	0:80ee8f3b695e	2441	* (default is RCC_HSICALIBRATION_DEFAULT).
EricLew	0:80ee8f3b695e	2442	* This parameter must be a number between 0 and 31.
EricLew	0:80ee8f3b695e	2443	* @retval None
EricLew	0:80ee8f3b695e	2444	*/
EricLew	0:80ee8f3b695e	2445	#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) \
EricLew	0:80ee8f3b695e	2446	MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << POSITION_VAL(RCC_ICSCR_HSITRIM))
EricLew	0:80ee8f3b695e	2447
EricLew	0:80ee8f3b695e	2448	/**
EricLew	0:80ee8f3b695e	2449	* @brief Macros to enable or disable the wakeup the Internal High Speed oscillator (HSI)
EricLew	0:80ee8f3b695e	2450	* in parallel to the Internal Multi Speed oscillator (MSI) used at system wakeup.
EricLew	0:80ee8f3b695e	2451	* @note The enable of this function has not effect on the HSION bit.
EricLew	0:80ee8f3b695e	2452	* This parameter can be: ENABLE or DISABLE.
EricLew	0:80ee8f3b695e	2453	* @retval None
EricLew	0:80ee8f3b695e	2454	*/
EricLew	0:80ee8f3b695e	2455	#define __HAL_RCC_HSIAUTOMATIC_START_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIASFS)
EricLew	0:80ee8f3b695e	2456
EricLew	0:80ee8f3b695e	2457	#define __HAL_RCC_HSIAUTOMATIC_START_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIASFS)
EricLew	0:80ee8f3b695e	2458
EricLew	0:80ee8f3b695e	2459	/**
EricLew	0:80ee8f3b695e	2460	* @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI)
EricLew	0:80ee8f3b695e	2461	* in STOP mode to be quickly available as kernel clock for USARTs and I2Cs.
EricLew	0:80ee8f3b695e	2462	* @note Keeping the HSI ON in STOP mode allows to avoid slowing down the communication
EricLew	0:80ee8f3b695e	2463	* speed because of the HSI startup time.
EricLew	0:80ee8f3b695e	2464	* @note The enable of this function has not effect on the HSION bit.
EricLew	0:80ee8f3b695e	2465	* This parameter can be: ENABLE or DISABLE.
EricLew	0:80ee8f3b695e	2466	* @retval None
EricLew	0:80ee8f3b695e	2467	*/
EricLew	0:80ee8f3b695e	2468	#define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON)
EricLew	0:80ee8f3b695e	2469
EricLew	0:80ee8f3b695e	2470	#define __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON)
EricLew	0:80ee8f3b695e	2471
EricLew	0:80ee8f3b695e	2472	/**
EricLew	0:80ee8f3b695e	2473	* @brief Macros to enable or disable the Internal Multi Speed oscillator (MSI).
EricLew	0:80ee8f3b695e	2474	* @note The MSI is stopped by hardware when entering STOP and STANDBY modes.
EricLew	0:80ee8f3b695e	2475	* It is used (enabled by hardware) as system clock source after
EricLew	0:80ee8f3b695e	2476	* startup from Reset, wakeup from STOP and STANDBY mode, or in case
EricLew	0:80ee8f3b695e	2477	* of failure of the HSE used directly or indirectly as system clock
EricLew	0:80ee8f3b695e	2478	* (if the Clock Security System CSS is enabled).
EricLew	0:80ee8f3b695e	2479	* @note MSI can not be stopped if it is used as system clock source.
EricLew	0:80ee8f3b695e	2480	* In this case, you have to select another source of the system
EricLew	0:80ee8f3b695e	2481	* clock then stop the MSI.
EricLew	0:80ee8f3b695e	2482	* @note After enabling the MSI, the application software should wait on
EricLew	0:80ee8f3b695e	2483	* MSIRDY flag to be set indicating that MSI clock is stable and can
EricLew	0:80ee8f3b695e	2484	* be used as system clock source.
EricLew	0:80ee8f3b695e	2485	* @note When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator
EricLew	0:80ee8f3b695e	2486	* clock cycles.
EricLew	0:80ee8f3b695e	2487	* @retval None
EricLew	0:80ee8f3b695e	2488	*/
EricLew	0:80ee8f3b695e	2489	#define __HAL_RCC_MSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_MSION)
EricLew	0:80ee8f3b695e	2490
EricLew	0:80ee8f3b695e	2491	#define __HAL_RCC_MSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_MSION)
EricLew	0:80ee8f3b695e	2492
EricLew	0:80ee8f3b695e	2493	/** @brief Macro Adjusts the Internal Multi Speed oscillator (MSI) calibration value.
EricLew	0:80ee8f3b695e	2494	* @note The calibration is used to compensate for the variations in voltage
EricLew	0:80ee8f3b695e	2495	* and temperature that influence the frequency of the internal MSI RC.
EricLew	0:80ee8f3b695e	2496	* Refer to the Application Note AN3300 for more details on how to
EricLew	0:80ee8f3b695e	2497	* calibrate the MSI.
EricLew	0:80ee8f3b695e	2498	* @param __MSICALIBRATIONVALUE__: specifies the calibration trimming value
EricLew	0:80ee8f3b695e	2499	* (default is RCC_MSICALIBRATION_DEFAULT).
EricLew	0:80ee8f3b695e	2500	* This parameter must be a number between 0 and 255.
EricLew	0:80ee8f3b695e	2501	* @retval None
EricLew	0:80ee8f3b695e	2502	*/
EricLew	0:80ee8f3b695e	2503	#define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(__MSICALIBRATIONVALUE__) \
EricLew	0:80ee8f3b695e	2504	MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, (uint32_t)(__MSICALIBRATIONVALUE__) << 8)
EricLew	0:80ee8f3b695e	2505
EricLew	0:80ee8f3b695e	2506	/**
EricLew	0:80ee8f3b695e	2507	* @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range in run mode
EricLew	0:80ee8f3b695e	2508	* @note After restart from Reset , the MSI clock is around 4 MHz.
EricLew	0:80ee8f3b695e	2509	* After stop the startup clock can be MSI (at any of its possible
EricLew	0:80ee8f3b695e	2510	* frequencies, the one that was used before entering stop mode) or HSI.
EricLew	0:80ee8f3b695e	2511	* After Standby its frequency can be selected between 4 possible values
EricLew	0:80ee8f3b695e	2512	* (1, 2, 4 or 8 MHz).
EricLew	0:80ee8f3b695e	2513	* @note MSIRANGE can be modified when MSI is OFF (MSION=0) or when MSI is ready
EricLew	0:80ee8f3b695e	2514	* (MSIRDY=1).
EricLew	0:80ee8f3b695e	2515	* @note The MSI clock range after reset can be modified on the fly.
EricLew	0:80ee8f3b695e	2516	* @param __MSIRANGEVALUE__: specifies the MSI clock range.
EricLew	0:80ee8f3b695e	2517	* This parameter must be one of the following values:
EricLew	0:80ee8f3b695e	2518	* @arg RCC_MSIRANGE_0: MSI clock is around 100 KHz
EricLew	0:80ee8f3b695e	2519	* @arg RCC_MSIRANGE_1: MSI clock is around 200 KHz
EricLew	0:80ee8f3b695e	2520	* @arg RCC_MSIRANGE_2: MSI clock is around 400 KHz
EricLew	0:80ee8f3b695e	2521	* @arg RCC_MSIRANGE_3: MSI clock is around 800 KHz
EricLew	0:80ee8f3b695e	2522	* @arg RCC_MSIRANGE_4: MSI clock is around 1 MHz
EricLew	0:80ee8f3b695e	2523	* @arg RCC_MSIRANGE_5: MSI clock is around 2MHz
EricLew	0:80ee8f3b695e	2524	* @arg RCC_MSIRANGE_6: MSI clock is around 4MHz (default after Reset)
EricLew	0:80ee8f3b695e	2525	* @arg RCC_MSIRANGE_7: MSI clock is around 8 MHz
EricLew	0:80ee8f3b695e	2526	* @arg RCC_MSIRANGE_8: MSI clock is around 16 MHz
EricLew	0:80ee8f3b695e	2527	* @arg RCC_MSIRANGE_9: MSI clock is around 24 MHz
EricLew	0:80ee8f3b695e	2528	* @arg RCC_MSIRANGE_10: MSI clock is around 32 MHz
EricLew	0:80ee8f3b695e	2529	* @arg RCC_MSIRANGE_11: MSI clock is around 48 MHz
EricLew	0:80ee8f3b695e	2530	* @retval None
EricLew	0:80ee8f3b695e	2531	*/
EricLew	0:80ee8f3b695e	2532	#define __HAL_RCC_MSI_RANGE_CONFIG(__MSIRANGEVALUE__) \
EricLew	0:80ee8f3b695e	2533	do { \
EricLew	0:80ee8f3b695e	2534	SET_BIT(RCC->CR, RCC_CR_MSIRGSEL); \
EricLew	0:80ee8f3b695e	2535	MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, (__MSIRANGEVALUE__)); \
EricLew	0:80ee8f3b695e	2536	} while(0)
EricLew	0:80ee8f3b695e	2537
EricLew	0:80ee8f3b695e	2538	/**
EricLew	0:80ee8f3b695e	2539	* @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range after Standby mode
EricLew	0:80ee8f3b695e	2540	* After Standby its frequency can be selected between 4 possible values (1, 2, 4 or 8 MHz).
EricLew	0:80ee8f3b695e	2541	* @param __MSIRANGEVALUE__: specifies the MSI clock range.
EricLew	0:80ee8f3b695e	2542	* This parameter must be one of the following values:
EricLew	0:80ee8f3b695e	2543	* @arg RCC_MSIRANGE_4: MSI clock is around 1 MHz
EricLew	0:80ee8f3b695e	2544	* @arg RCC_MSIRANGE_5: MSI clock is around 2MHz
EricLew	0:80ee8f3b695e	2545	* @arg RCC_MSIRANGE_6: MSI clock is around 4MHz (default after Reset)
EricLew	0:80ee8f3b695e	2546	* @arg RCC_MSIRANGE_7: MSI clock is around 8 MHz
EricLew	0:80ee8f3b695e	2547	* @retval None
EricLew	0:80ee8f3b695e	2548	*/
EricLew	0:80ee8f3b695e	2549	#define __HAL_RCC_MSI_STANDBY_RANGE_CONFIG(__MSIRANGEVALUE__) \
EricLew	0:80ee8f3b695e	2550	MODIFY_REG(RCC->CSR, RCC_CSR_MSISRANGE, (__MSIRANGEVALUE__) << 4U)
EricLew	0:80ee8f3b695e	2551
EricLew	0:80ee8f3b695e	2552	/** @brief Macro to get the Internal Multi Speed oscillator (MSI) clock range in run mode
EricLew	0:80ee8f3b695e	2553	* @retval MSI clock range.
EricLew	0:80ee8f3b695e	2554	* This parameter must be one of the following values:
EricLew	0:80ee8f3b695e	2555	* @arg RCC_MSIRANGE_0: MSI clock is around 100 KHz
EricLew	0:80ee8f3b695e	2556	* @arg RCC_MSIRANGE_1: MSI clock is around 200 KHz
EricLew	0:80ee8f3b695e	2557	* @arg RCC_MSIRANGE_2: MSI clock is around 400 KHz
EricLew	0:80ee8f3b695e	2558	* @arg RCC_MSIRANGE_3: MSI clock is around 800 KHz
EricLew	0:80ee8f3b695e	2559	* @arg RCC_MSIRANGE_4: MSI clock is around 1 MHz
EricLew	0:80ee8f3b695e	2560	* @arg RCC_MSIRANGE_5: MSI clock is around 2MHz
EricLew	0:80ee8f3b695e	2561	* @arg RCC_MSIRANGE_6: MSI clock is around 4MHz (default after Reset)
EricLew	0:80ee8f3b695e	2562	* @arg RCC_MSIRANGE_7: MSI clock is around 8 MHz
EricLew	0:80ee8f3b695e	2563	* @arg RCC_MSIRANGE_8: MSI clock is around 16 MHz
EricLew	0:80ee8f3b695e	2564	* @arg RCC_MSIRANGE_9: MSI clock is around 24 MHz
EricLew	0:80ee8f3b695e	2565	* @arg RCC_MSIRANGE_10: MSI clock is around 32 MHz
EricLew	0:80ee8f3b695e	2566	* @arg RCC_MSIRANGE_11: MSI clock is around 48 MHz
EricLew	0:80ee8f3b695e	2567	*/
EricLew	0:80ee8f3b695e	2568	#define __HAL_RCC_GET_MSI_RANGE() \
EricLew	0:80ee8f3b695e	2569	((READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) != RESET) ? \
EricLew	0:80ee8f3b695e	2570	(uint32_t)(READ_BIT(RCC->CR, RCC_CR_MSIRANGE)) : \
EricLew	0:80ee8f3b695e	2571	(uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> 4))
EricLew	0:80ee8f3b695e	2572
EricLew	0:80ee8f3b695e	2573	/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
EricLew	0:80ee8f3b695e	2574	* @note After enabling the LSI, the application software should wait on
EricLew	0:80ee8f3b695e	2575	* LSIRDY flag to be set indicating that LSI clock is stable and can
EricLew	0:80ee8f3b695e	2576	* be used to clock the IWDG and/or the RTC.
EricLew	0:80ee8f3b695e	2577	* @note LSI can not be disabled if the IWDG is running.
EricLew	0:80ee8f3b695e	2578	* @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
EricLew	0:80ee8f3b695e	2579	* clock cycles.
EricLew	0:80ee8f3b695e	2580	* @retval None
EricLew	0:80ee8f3b695e	2581	*/
EricLew	0:80ee8f3b695e	2582	#define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION)
EricLew	0:80ee8f3b695e	2583
EricLew	0:80ee8f3b695e	2584	#define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
EricLew	0:80ee8f3b695e	2585
EricLew	0:80ee8f3b695e	2586	/**
EricLew	0:80ee8f3b695e	2587	* @brief Macro to configure the External High Speed oscillator (HSE).
EricLew	0:80ee8f3b695e	2588	* @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
EricLew	0:80ee8f3b695e	2589	* supported by this macro. User should request a transition to HSE Off
EricLew	0:80ee8f3b695e	2590	* first and then HSE On or HSE Bypass.
EricLew	0:80ee8f3b695e	2591	* @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
EricLew	0:80ee8f3b695e	2592	* software should wait on HSERDY flag to be set indicating that HSE clock
EricLew	0:80ee8f3b695e	2593	* is stable and can be used to clock the PLL and/or system clock.
EricLew	0:80ee8f3b695e	2594	* @note HSE state can not be changed if it is used directly or through the
EricLew	0:80ee8f3b695e	2595	* PLL as system clock. In this case, you have to select another source
EricLew	0:80ee8f3b695e	2596	* of the system clock then change the HSE state (ex. disable it).
EricLew	0:80ee8f3b695e	2597	* @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
EricLew	0:80ee8f3b695e	2598	* @note This function reset the CSSON bit, so if the clock security system(CSS)
EricLew	0:80ee8f3b695e	2599	* was previously enabled you have to enable it again after calling this
EricLew	0:80ee8f3b695e	2600	* function.
EricLew	0:80ee8f3b695e	2601	* @param __STATE__: specifies the new state of the HSE.
EricLew	0:80ee8f3b695e	2602	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2603	* @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
EricLew	0:80ee8f3b695e	2604	* 6 HSE oscillator clock cycles.
EricLew	0:80ee8f3b695e	2605	* @arg RCC_HSE_ON: turn ON the HSE oscillator.
EricLew	0:80ee8f3b695e	2606	* @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.
EricLew	0:80ee8f3b695e	2607	* @retval None
EricLew	0:80ee8f3b695e	2608	*/
EricLew	0:80ee8f3b695e	2609	#define __HAL_RCC_HSE_CONFIG(__STATE__) \
EricLew	0:80ee8f3b695e	2610	do { \
EricLew	0:80ee8f3b695e	2611	if((__STATE__) == RCC_HSE_ON) \
EricLew	0:80ee8f3b695e	2612	{ \
EricLew	0:80ee8f3b695e	2613	SET_BIT(RCC->CR, RCC_CR_HSEON); \
EricLew	0:80ee8f3b695e	2614	} \
EricLew	0:80ee8f3b695e	2615	else if((__STATE__) == RCC_HSE_BYPASS) \
EricLew	0:80ee8f3b695e	2616	{ \
EricLew	0:80ee8f3b695e	2617	CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
EricLew	0:80ee8f3b695e	2618	SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
EricLew	0:80ee8f3b695e	2619	SET_BIT(RCC->CR, RCC_CR_HSEON); \
EricLew	0:80ee8f3b695e	2620	} \
EricLew	0:80ee8f3b695e	2621	else \
EricLew	0:80ee8f3b695e	2622	{ \
EricLew	0:80ee8f3b695e	2623	CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
EricLew	0:80ee8f3b695e	2624	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
EricLew	0:80ee8f3b695e	2625	} \
EricLew	0:80ee8f3b695e	2626	} while(0)
EricLew	0:80ee8f3b695e	2627
EricLew	0:80ee8f3b695e	2628	/**
EricLew	0:80ee8f3b695e	2629	* @brief Macro to configure the External Low Speed oscillator (LSE).
EricLew	0:80ee8f3b695e	2630	* @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
EricLew	0:80ee8f3b695e	2631	* supported by this macro. User should request a transition to LSE Off
EricLew	0:80ee8f3b695e	2632	* first and then LSE On or LSE Bypass.
EricLew	0:80ee8f3b695e	2633	* @note As the LSE is in the Backup domain and write access is denied to
EricLew	0:80ee8f3b695e	2634	* this domain after reset, you have to enable write access using
EricLew	0:80ee8f3b695e	2635	* HAL_PWR_EnableBkUpAccess() function before to configure the LSE
EricLew	0:80ee8f3b695e	2636	* (to be done once after reset).
EricLew	0:80ee8f3b695e	2637	* @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
EricLew	0:80ee8f3b695e	2638	* software should wait on LSERDY flag to be set indicating that LSE clock
EricLew	0:80ee8f3b695e	2639	* is stable and can be used to clock the RTC.
EricLew	0:80ee8f3b695e	2640	* @param __STATE__: specifies the new state of the LSE.
EricLew	0:80ee8f3b695e	2641	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2642	* @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
EricLew	0:80ee8f3b695e	2643	* 6 LSE oscillator clock cycles.
EricLew	0:80ee8f3b695e	2644	* @arg RCC_LSE_ON: turn ON the LSE oscillator.
EricLew	0:80ee8f3b695e	2645	* @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
EricLew	0:80ee8f3b695e	2646	* @retval None
EricLew	0:80ee8f3b695e	2647	*/
EricLew	0:80ee8f3b695e	2648	#define __HAL_RCC_LSE_CONFIG(__STATE__) \
EricLew	0:80ee8f3b695e	2649	do { \
EricLew	0:80ee8f3b695e	2650	if((__STATE__) == RCC_LSE_ON) \
EricLew	0:80ee8f3b695e	2651	{ \
EricLew	0:80ee8f3b695e	2652	SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
EricLew	0:80ee8f3b695e	2653	} \
EricLew	0:80ee8f3b695e	2654	else if((__STATE__) == RCC_LSE_OFF) \
EricLew	0:80ee8f3b695e	2655	{ \
EricLew	0:80ee8f3b695e	2656	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
EricLew	0:80ee8f3b695e	2657	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
EricLew	0:80ee8f3b695e	2658	} \
EricLew	0:80ee8f3b695e	2659	else if((__STATE__) == RCC_LSE_BYPASS) \
EricLew	0:80ee8f3b695e	2660	{ \
EricLew	0:80ee8f3b695e	2661	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
EricLew	0:80ee8f3b695e	2662	SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
EricLew	0:80ee8f3b695e	2663	SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
EricLew	0:80ee8f3b695e	2664	} \
EricLew	0:80ee8f3b695e	2665	else \
EricLew	0:80ee8f3b695e	2666	{ \
EricLew	0:80ee8f3b695e	2667	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
EricLew	0:80ee8f3b695e	2668	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
EricLew	0:80ee8f3b695e	2669	} \
EricLew	0:80ee8f3b695e	2670	} while(0)
EricLew	0:80ee8f3b695e	2671
EricLew	0:80ee8f3b695e	2672	/** @brief Macros to configure the RTC clock (RTCCLK).
EricLew	0:80ee8f3b695e	2673	* @note As the RTC clock configuration bits are in the Backup domain and write
EricLew	0:80ee8f3b695e	2674	* access is denied to this domain after reset, you have to enable write
EricLew	0:80ee8f3b695e	2675	* access using the Power Backup Access macro before to configure
EricLew	0:80ee8f3b695e	2676	* the RTC clock source (to be done once after reset).
EricLew	0:80ee8f3b695e	2677	* @note Once the RTC clock is configured it cannot be changed unless the
EricLew	0:80ee8f3b695e	2678	* Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by
EricLew	0:80ee8f3b695e	2679	* a Power On Reset (POR).
EricLew	0:80ee8f3b695e	2680	*
EricLew	0:80ee8f3b695e	2681	* @param __RTC_CLKSOURCE__: specifies the RTC clock source.
EricLew	0:80ee8f3b695e	2682	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2683	* @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.
EricLew	0:80ee8f3b695e	2684	* @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.
EricLew	0:80ee8f3b695e	2685	* @arg RCC_RTCCLKSOURCE_HSE_DIV32: HSE clock divided by 32 selected
EricLew	0:80ee8f3b695e	2686	*
EricLew	0:80ee8f3b695e	2687	* @note If the LSE or LSI is used as RTC clock source, the RTC continues to
EricLew	0:80ee8f3b695e	2688	* work in STOP and STANDBY modes, and can be used as wakeup source.
EricLew	0:80ee8f3b695e	2689	* However, when the HSE clock is used as RTC clock source, the RTC
EricLew	0:80ee8f3b695e	2690	* cannot be used in STOP and STANDBY modes.
EricLew	0:80ee8f3b695e	2691	* @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
EricLew	0:80ee8f3b695e	2692	* RTC clock source).
EricLew	0:80ee8f3b695e	2693	* @retval None
EricLew	0:80ee8f3b695e	2694	*/
EricLew	0:80ee8f3b695e	2695	#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) \
EricLew	0:80ee8f3b695e	2696	MODIFY_REG( RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))
EricLew	0:80ee8f3b695e	2697
EricLew	0:80ee8f3b695e	2698
EricLew	0:80ee8f3b695e	2699	/** @brief Macro to get the RTC clock source.
EricLew	0:80ee8f3b695e	2700	* @retval The returned value can be one of the following:
EricLew	0:80ee8f3b695e	2701	* @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.
EricLew	0:80ee8f3b695e	2702	* @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.
EricLew	0:80ee8f3b695e	2703	* @arg RCC_RTCCLKSOURCE_HSE_DIV32: HSE clock divided by 32 selected
EricLew	0:80ee8f3b695e	2704	*/
EricLew	0:80ee8f3b695e	2705	#define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)))
EricLew	0:80ee8f3b695e	2706
EricLew	0:80ee8f3b695e	2707	/** @brief Macros to enable or disable the main PLL.
EricLew	0:80ee8f3b695e	2708	* @note After enabling the main PLL, the application software should wait on
EricLew	0:80ee8f3b695e	2709	* PLLRDY flag to be set indicating that PLL clock is stable and can
EricLew	0:80ee8f3b695e	2710	* be used as system clock source.
EricLew	0:80ee8f3b695e	2711	* @note The main PLL can not be disabled if it is used as system clock source
EricLew	0:80ee8f3b695e	2712	* @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
EricLew	0:80ee8f3b695e	2713	* @retval None
EricLew	0:80ee8f3b695e	2714	*/
EricLew	0:80ee8f3b695e	2715	#define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)
EricLew	0:80ee8f3b695e	2716
EricLew	0:80ee8f3b695e	2717	#define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
EricLew	0:80ee8f3b695e	2718
EricLew	0:80ee8f3b695e	2719	/** @brief Macro to configure the PLL clock source.
EricLew	0:80ee8f3b695e	2720	* @note This function must be used only when the main PLL is disabled.
EricLew	0:80ee8f3b695e	2721	* @param __PLLSOURCE__: specifies the PLL entry clock source.
EricLew	0:80ee8f3b695e	2722	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2723	* @arg RCC_PLLSOURCE_NONE: No clock selected as PLL clock entry
EricLew	0:80ee8f3b695e	2724	* @arg RCC_PLLSOURCE_MSI: MSI oscillator clock selected as PLL clock entry
EricLew	0:80ee8f3b695e	2725	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
EricLew	0:80ee8f3b695e	2726	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
EricLew	0:80ee8f3b695e	2727	* @note This clock source is common for the main PLL and audio PLL (PLLSAI1 and PLLSAI2).
EricLew	0:80ee8f3b695e	2728	* @retval None
EricLew	0:80ee8f3b695e	2729	*
EricLew	0:80ee8f3b695e	2730	*/
EricLew	0:80ee8f3b695e	2731	#define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) \
EricLew	0:80ee8f3b695e	2732	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
EricLew	0:80ee8f3b695e	2733
EricLew	0:80ee8f3b695e	2734	/** @brief Macro to configure the PLL multiplication factor.
EricLew	0:80ee8f3b695e	2735	* @note This function must be used only when the main PLL is disabled.
EricLew	0:80ee8f3b695e	2736	* @param __PLLM__: specifies the division factor for PLL VCO input clock
EricLew	0:80ee8f3b695e	2737	* This parameter must be a number between Min_Data = 1 and Max_Data = 8.
EricLew	0:80ee8f3b695e	2738	* @note You have to set the PLLM parameter correctly to ensure that the VCO input
EricLew	0:80ee8f3b695e	2739	* frequency ranges from 4 to 16 MHz. It is recommended to select a frequency
EricLew	0:80ee8f3b695e	2740	* of 16 MHz to limit PLL jitter.
EricLew	0:80ee8f3b695e	2741	* @retval None
EricLew	0:80ee8f3b695e	2742	*
EricLew	0:80ee8f3b695e	2743	*/
EricLew	0:80ee8f3b695e	2744	#define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) \
EricLew	0:80ee8f3b695e	2745	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, ((__PLLM__) - 1) << 4U)
EricLew	0:80ee8f3b695e	2746
EricLew	0:80ee8f3b695e	2747	/**
EricLew	0:80ee8f3b695e	2748	* @brief Macro to configure the main PLL clock source, multiplication and division factors.
EricLew	0:80ee8f3b695e	2749	* @note This function must be used only when the main PLL is disabled.
EricLew	0:80ee8f3b695e	2750	*
EricLew	0:80ee8f3b695e	2751	* @param __PLLSOURCE__: specifies the PLL entry clock source.
EricLew	0:80ee8f3b695e	2752	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2753	* @arg RCC_PLLSOURCE_NONE: No clock selected as PLL clock entry
EricLew	0:80ee8f3b695e	2754	* @arg RCC_PLLSOURCE_MSI: MSI oscillator clock selected as PLL clock entry
EricLew	0:80ee8f3b695e	2755	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
EricLew	0:80ee8f3b695e	2756	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
EricLew	0:80ee8f3b695e	2757	* @note This clock source is common for the main PLL and audio PLL (PLLSAI1 and PLLSAI2).
EricLew	0:80ee8f3b695e	2758	*
EricLew	0:80ee8f3b695e	2759	* @param __PLLM__: specifies the division factor for PLL VCO input clock.
EricLew	0:80ee8f3b695e	2760	* This parameter must be a number between 1 and 8.
EricLew	0:80ee8f3b695e	2761	* @note You have to set the PLLM parameter correctly to ensure that the VCO input
EricLew	0:80ee8f3b695e	2762	* frequency ranges from 4 to 16 MHz. It is recommended to select a frequency
EricLew	0:80ee8f3b695e	2763	* of 16 MHz to limit PLL jitter.
EricLew	0:80ee8f3b695e	2764	*
EricLew	0:80ee8f3b695e	2765	* @param __PLLN__: specifies the multiplication factor for PLL VCO output clock.
EricLew	0:80ee8f3b695e	2766	* This parameter must be a number between 8 and 86.
EricLew	0:80ee8f3b695e	2767	* @note You have to set the PLLN parameter correctly to ensure that the VCO
EricLew	0:80ee8f3b695e	2768	* output frequency is between 64 and 344 MHz.
EricLew	0:80ee8f3b695e	2769	*
EricLew	0:80ee8f3b695e	2770	* @param __PLLP__: specifies the division factor for SAI clock.
EricLew	0:80ee8f3b695e	2771	* This parameter must be a number in the range (7 or 17).
EricLew	0:80ee8f3b695e	2772	*
EricLew	0:80ee8f3b695e	2773	* @param __PLLQ__: specifies the division factor for OTG FS, SDMMC1 and RNG clocks.
EricLew	0:80ee8f3b695e	2774	* This parameter must be in the range (2, 4, 6 or 8).
EricLew	0:80ee8f3b695e	2775	* @note If the USB OTG FS is used in your application, you have to set the
EricLew	0:80ee8f3b695e	2776	* PLLQ parameter correctly to have 48 MHz clock for the USB. However,
EricLew	0:80ee8f3b695e	2777	* the SDMMC1 and RNG need a frequency lower than or equal to 48 MHz to work
EricLew	0:80ee8f3b695e	2778	* correctly.
EricLew	0:80ee8f3b695e	2779	* @param __PLLR__: specifies the division factor for the main system clock.
EricLew	0:80ee8f3b695e	2780	* @note You have to set the PLLR parameter correctly to not exceed 80MHZ.
EricLew	0:80ee8f3b695e	2781	* This parameter must be in the range (2, 4, 6 or 8).
EricLew	0:80ee8f3b695e	2782	* @retval None
EricLew	0:80ee8f3b695e	2783	*/
EricLew	0:80ee8f3b695e	2784	#define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \
EricLew	0:80ee8f3b695e	2785	(RCC->PLLCFGR = (uint32_t)(((__PLLM__) - 1) << 4U) \| (uint32_t)((__PLLN__) << 8U) \| (uint32_t)(((__PLLP__) >> 4U ) << 17U) \| \
EricLew	0:80ee8f3b695e	2786	(uint32_t)(__PLLSOURCE__) \| (uint32_t)((((__PLLQ__) >> 1U) - 1) << 21U) \| (uint32_t)((((__PLLR__) >> 1U) - 1) << 25U))
EricLew	0:80ee8f3b695e	2787
EricLew	0:80ee8f3b695e	2788
EricLew	0:80ee8f3b695e	2789	/** @brief Macro to get the oscillator used as PLL clock source.
EricLew	0:80ee8f3b695e	2790	* @retval The oscillator used as PLL clock source. The returned value can be one
EricLew	0:80ee8f3b695e	2791	* of the following:
EricLew	0:80ee8f3b695e	2792	* - RCC_PLLSOURCE_NONE: No oscillator is used as PLL clock source.
EricLew	0:80ee8f3b695e	2793	* - RCC_PLLSOURCE_MSI: MSI oscillator is used as PLL clock source.
EricLew	0:80ee8f3b695e	2794	* - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
EricLew	0:80ee8f3b695e	2795	* - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
EricLew	0:80ee8f3b695e	2796	*/
EricLew	0:80ee8f3b695e	2797	#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
EricLew	0:80ee8f3b695e	2798
EricLew	0:80ee8f3b695e	2799	/**
EricLew	0:80ee8f3b695e	2800	* @brief Enable or disable each clock output (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK)
EricLew	0:80ee8f3b695e	2801	* @note Enabling/disabling clock outputs RCC_PLL_SAI3CLK and RCC_PLL_48M1CLK can be done at anytime
EricLew	0:80ee8f3b695e	2802	* without the need to stop the PLL in order to save power. But RCC_PLL_SYSCLK cannot
EricLew	0:80ee8f3b695e	2803	* be stopped if used as System Clock.
EricLew	0:80ee8f3b695e	2804	* @param __PLLCLOCKOUT__: specifies the PLL clock to be output.
EricLew	0:80ee8f3b695e	2805	* This parameter can be one or a combination of the following values:
EricLew	0:80ee8f3b695e	2806	* @arg RCC_PLL_SAI3CLK: This clock is used to generate an accurate clock to achieve
EricLew	0:80ee8f3b695e	2807	* high-quality audio performance on SAI interface in case.
EricLew	0:80ee8f3b695e	2808	* @arg RCC_PLL_48M1CLK: This Clock is used to generate the clock for the USB OTG FS (48 MHz),
EricLew	0:80ee8f3b695e	2809	* the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz).
EricLew	0:80ee8f3b695e	2810	* @arg RCC_PLL_SYSCLK: This Clock is used to generate the high speed system clock (up to 80MHz)
EricLew	0:80ee8f3b695e	2811	* @retval None
EricLew	0:80ee8f3b695e	2812	*/
EricLew	0:80ee8f3b695e	2813	#define __HAL_RCC_PLLCLKOUT_ENABLE(__PLLCLOCKOUT__) SET_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
EricLew	0:80ee8f3b695e	2814
EricLew	0:80ee8f3b695e	2815	#define __HAL_RCC_PLLCLKOUT_DISABLE(__PLLCLOCKOUT__) CLEAR_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
EricLew	0:80ee8f3b695e	2816
EricLew	0:80ee8f3b695e	2817	/**
EricLew	0:80ee8f3b695e	2818	* @brief Get clock output enable status (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK)
EricLew	0:80ee8f3b695e	2819	* @param __PLLCLOCKOUT__: specifies the output PLL clock to be checked.
EricLew	0:80ee8f3b695e	2820	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2821	* @arg RCC_PLL_SAI3CLK: This clock is used to generate an accurate clock to achieve
EricLew	0:80ee8f3b695e	2822	* high-quality audio performance on SAI interface in case.
EricLew	0:80ee8f3b695e	2823	* @arg RCC_PLL_48M1CLK: This Clock is used to generate the clock for the USB OTG FS (48 MHz),
EricLew	0:80ee8f3b695e	2824	* the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz).
EricLew	0:80ee8f3b695e	2825	* @arg RCC_PLL_SYSCLK: This Clock is used to generate the high speed system clock (up to 80MHz)
EricLew	0:80ee8f3b695e	2826	* @retval SET / RESET
EricLew	0:80ee8f3b695e	2827	*/
EricLew	0:80ee8f3b695e	2828	#define __HAL_RCC_GET_PLLCLKOUT_CONFIG(__PLLCLOCKOUT__) READ_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
EricLew	0:80ee8f3b695e	2829
EricLew	0:80ee8f3b695e	2830	/**
EricLew	0:80ee8f3b695e	2831	* @brief Macro to configure the system clock source.
EricLew	0:80ee8f3b695e	2832	* @param __SYSCLKSOURCE__: specifies the system clock source.
EricLew	0:80ee8f3b695e	2833	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2834	* - RCC_SYSCLKSOURCE_MSI: MSI oscillator is used as system clock source.
EricLew	0:80ee8f3b695e	2835	* - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
EricLew	0:80ee8f3b695e	2836	* - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
EricLew	0:80ee8f3b695e	2837	* - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
EricLew	0:80ee8f3b695e	2838	* @retval None
EricLew	0:80ee8f3b695e	2839	*/
EricLew	0:80ee8f3b695e	2840	#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \
EricLew	0:80ee8f3b695e	2841	MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
EricLew	0:80ee8f3b695e	2842
EricLew	0:80ee8f3b695e	2843	/** @brief Macro to get the clock source used as system clock.
EricLew	0:80ee8f3b695e	2844	* @retval The clock source used as system clock. The returned value can be one
EricLew	0:80ee8f3b695e	2845	* of the following:
EricLew	0:80ee8f3b695e	2846	* - RCC_SYSCLKSOURCE_STATUS_MSI: MSI used as system clock.
EricLew	0:80ee8f3b695e	2847	* - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.
EricLew	0:80ee8f3b695e	2848	* - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.
EricLew	0:80ee8f3b695e	2849	* - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.
EricLew	0:80ee8f3b695e	2850	*/
EricLew	0:80ee8f3b695e	2851	#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
EricLew	0:80ee8f3b695e	2852
EricLew	0:80ee8f3b695e	2853	/**
EricLew	0:80ee8f3b695e	2854	* @brief Macro to configure the External Low Speed oscillator (LSE) drive capability.
EricLew	0:80ee8f3b695e	2855	* @note As the LSE is in the Backup domain and write access is denied to
EricLew	0:80ee8f3b695e	2856	* this domain after reset, you have to enable write access using
EricLew	0:80ee8f3b695e	2857	* HAL_PWR_EnableBkUpAccess() function before to configure the LSE
EricLew	0:80ee8f3b695e	2858	* (to be done once after reset).
EricLew	0:80ee8f3b695e	2859	* @param __LSEDRIVE__: specifies the new state of the LSE drive capability.
EricLew	0:80ee8f3b695e	2860	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2861	* @arg RCC_LSEDRIVE_LOW: LSE oscillator low drive capability.
EricLew	0:80ee8f3b695e	2862	* @arg RCC_LSEDRIVE_MEDIUMLOW: LSE oscillator medium low drive capability.
EricLew	0:80ee8f3b695e	2863	* @arg RCC_LSEDRIVE_MEDIUMHIGH: LSE oscillator medium high drive capability.
EricLew	0:80ee8f3b695e	2864	* @arg RCC_LSEDRIVE_HIGH: LSE oscillator high drive capability.
EricLew	0:80ee8f3b695e	2865	* @retval None
EricLew	0:80ee8f3b695e	2866	*/
EricLew	0:80ee8f3b695e	2867	#define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \
EricLew	0:80ee8f3b695e	2868	MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__))
EricLew	0:80ee8f3b695e	2869
EricLew	0:80ee8f3b695e	2870	/**
EricLew	0:80ee8f3b695e	2871	* @brief Macro to configure the wake up from stop clock.
EricLew	0:80ee8f3b695e	2872	* @param __STOPWUCLK__: specifies the clock source used after wake up from stop.
EricLew	0:80ee8f3b695e	2873	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2874	* @arg RCC_STOP_WAKEUPCLOCK_MSI: MSI selected as system clock source
EricLew	0:80ee8f3b695e	2875	* @arg RCC_STOP_WAKEUPCLOCK_HSI: HSI selected as system clock source
EricLew	0:80ee8f3b695e	2876	* @retval None
EricLew	0:80ee8f3b695e	2877	*/
EricLew	0:80ee8f3b695e	2878	#define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__STOPWUCLK__) \
EricLew	0:80ee8f3b695e	2879	MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, (__STOPWUCLK__))
EricLew	0:80ee8f3b695e	2880
EricLew	0:80ee8f3b695e	2881
EricLew	0:80ee8f3b695e	2882	/** @brief Macro to configure the MCO clock.
EricLew	0:80ee8f3b695e	2883	* @param __MCOCLKSOURCE__ specifies the MCO clock source.
EricLew	0:80ee8f3b695e	2884	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2885	* @arg RCC_MCO1SOURCE_NOCLOCK: MCO output disabled
EricLew	0:80ee8f3b695e	2886	* @arg RCC_MCO1SOURCE_SYSCLK: system clock selected as MCO source
EricLew	0:80ee8f3b695e	2887	* @arg RCC_MCO1SOURCE_MSI: MSI clock selected as MCO source
EricLew	0:80ee8f3b695e	2888	* @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO source
EricLew	0:80ee8f3b695e	2889	* @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO sourcee
EricLew	0:80ee8f3b695e	2890	* @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO source
EricLew	0:80ee8f3b695e	2891	* @arg RCC_MCO1SOURCE_LSI: LSI clock selected as MCO source
EricLew	0:80ee8f3b695e	2892	* @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO source
EricLew	0:80ee8f3b695e	2893	* @arg RCC_MCO1SOURCE_HSI48: HSI48 clock selected as MCO source for devices with HSI48
EricLew	0:80ee8f3b695e	2894	* @param __MCODIV__ specifies the MCO clock prescaler.
EricLew	0:80ee8f3b695e	2895	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2896	* @arg RCC_MCODIV_1 MCO clock source is divided by 1
EricLew	0:80ee8f3b695e	2897	* @arg RCC_MCODIV_2 MCO clock source is divided by 2
EricLew	0:80ee8f3b695e	2898	* @arg RCC_MCODIV_4 MCO clock source is divided by 4
EricLew	0:80ee8f3b695e	2899	* @arg RCC_MCODIV_8 MCO clock source is divided by 8
EricLew	0:80ee8f3b695e	2900	* @arg RCC_MCODIV_16 MCO clock source is divided by 16
EricLew	0:80ee8f3b695e	2901	*/
EricLew	0:80ee8f3b695e	2902	#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
EricLew	0:80ee8f3b695e	2903	MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL \| RCC_CFGR_MCO_PRE), ((__MCOCLKSOURCE__) \| (__MCODIV__)))
EricLew	0:80ee8f3b695e	2904
EricLew	0:80ee8f3b695e	2905	/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
EricLew	0:80ee8f3b695e	2906	* @brief macros to manage the specified RCC Flags and interrupts.
EricLew	0:80ee8f3b695e	2907	* @{
EricLew	0:80ee8f3b695e	2908	*/
EricLew	0:80ee8f3b695e	2909
EricLew	0:80ee8f3b695e	2910	/** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
EricLew	0:80ee8f3b695e	2911	* the selected interrupts).
EricLew	0:80ee8f3b695e	2912	* @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
EricLew	0:80ee8f3b695e	2913	* This parameter can be any combination of the following values:
EricLew	0:80ee8f3b695e	2914	* @arg RCC_IT_LSIRDY: LSI ready interrupt
EricLew	0:80ee8f3b695e	2915	* @arg RCC_IT_LSERDY: LSE ready interrupt
EricLew	0:80ee8f3b695e	2916	* @arg RCC_IT_MSIRDY: HSI ready interrupt
EricLew	0:80ee8f3b695e	2917	* @arg RCC_IT_HSIRDY: HSI ready interrupt
EricLew	0:80ee8f3b695e	2918	* @arg RCC_IT_HSERDY: HSE ready interrupt
EricLew	0:80ee8f3b695e	2919	* @arg RCC_IT_PLLRDY: main PLL ready interrupt
EricLew	0:80ee8f3b695e	2920	* @arg RCC_IT_PLLSAI1RDY: PLLSAI1 ready interrupt
EricLew	0:80ee8f3b695e	2921	* @arg RCC_IT_PLLSAI2RDY: PLLSAI2 ready interrupt
EricLew	0:80ee8f3b695e	2922	* @arg RCC_IT_LSECSS: Clock security system interrupt
EricLew	0:80ee8f3b695e	2923	* @retval None
EricLew	0:80ee8f3b695e	2924	*/
EricLew	0:80ee8f3b695e	2925	#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__))
EricLew	0:80ee8f3b695e	2926
EricLew	0:80ee8f3b695e	2927	/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable
EricLew	0:80ee8f3b695e	2928	* the selected interrupts).
EricLew	0:80ee8f3b695e	2929	* @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
EricLew	0:80ee8f3b695e	2930	* This parameter can be any combination of the following values:
EricLew	0:80ee8f3b695e	2931	* @arg RCC_IT_LSIRDY: LSI ready interrupt
EricLew	0:80ee8f3b695e	2932	* @arg RCC_IT_LSERDY: LSE ready interrupt
EricLew	0:80ee8f3b695e	2933	* @arg RCC_IT_MSIRDY: HSI ready interrupt
EricLew	0:80ee8f3b695e	2934	* @arg RCC_IT_HSIRDY: HSI ready interrupt
EricLew	0:80ee8f3b695e	2935	* @arg RCC_IT_HSERDY: HSE ready interrupt
EricLew	0:80ee8f3b695e	2936	* @arg RCC_IT_PLLRDY: main PLL ready interrupt
EricLew	0:80ee8f3b695e	2937	* @arg RCC_IT_PLLSAI1RDY: PLLSAI1 ready interrupt
EricLew	0:80ee8f3b695e	2938	* @arg RCC_IT_PLLSAI2RDY: PLLSAI2 ready interrupt
EricLew	0:80ee8f3b695e	2939	* @arg RCC_IT_LSECSS: Clock security system interrupt
EricLew	0:80ee8f3b695e	2940	* @retval None
EricLew	0:80ee8f3b695e	2941	*/
EricLew	0:80ee8f3b695e	2942	#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__))
EricLew	0:80ee8f3b695e	2943
EricLew	0:80ee8f3b695e	2944	/** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
EricLew	0:80ee8f3b695e	2945	* bits to clear the selected interrupt pending bits.
EricLew	0:80ee8f3b695e	2946	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
EricLew	0:80ee8f3b695e	2947	* This parameter can be any combination of the following values:
EricLew	0:80ee8f3b695e	2948	* @arg RCC_IT_LSIRDY: LSI ready interrupt
EricLew	0:80ee8f3b695e	2949	* @arg RCC_IT_LSERDY: LSE ready interrupt
EricLew	0:80ee8f3b695e	2950	* @arg RCC_IT_MSIRDY: MSI ready interrupt
EricLew	0:80ee8f3b695e	2951	* @arg RCC_IT_HSIRDY: HSI ready interrupt
EricLew	0:80ee8f3b695e	2952	* @arg RCC_IT_HSERDY: HSE ready interrupt
EricLew	0:80ee8f3b695e	2953	* @arg RCC_IT_PLLRDY: main PLL ready interrupt
EricLew	0:80ee8f3b695e	2954	* @arg RCC_IT_PLLSAI1RDY: PLLSAI1 ready interrupt
EricLew	0:80ee8f3b695e	2955	* @arg RCC_IT_PLLSAI2RDY: PLLSAI2 ready interrupt
EricLew	0:80ee8f3b695e	2956	* @arg RCC_IT_HSECSS: HSE Clock Security interrupt
EricLew	0:80ee8f3b695e	2957	* @arg RCC_IT_LSECSS: Clock security system interrupt
EricLew	0:80ee8f3b695e	2958	* @retval None
EricLew	0:80ee8f3b695e	2959	*/
EricLew	0:80ee8f3b695e	2960	#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__))
EricLew	0:80ee8f3b695e	2961
EricLew	0:80ee8f3b695e	2962	/** @brief Check whether the RCC interrupt has occurred or not.
EricLew	0:80ee8f3b695e	2963	* @param __INTERRUPT__: specifies the RCC interrupt source to check.
EricLew	0:80ee8f3b695e	2964	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2965	* @arg RCC_IT_LSIRDY: LSI ready interrupt
EricLew	0:80ee8f3b695e	2966	* @arg RCC_IT_LSERDY: LSE ready interrupt
EricLew	0:80ee8f3b695e	2967	* @arg RCC_IT_MSIRDY: MSI ready interrupt
EricLew	0:80ee8f3b695e	2968	* @arg RCC_IT_HSIRDY: HSI ready interrupt
EricLew	0:80ee8f3b695e	2969	* @arg RCC_IT_HSERDY: HSE ready interrupt
EricLew	0:80ee8f3b695e	2970	* @arg RCC_IT_PLLRDY: main PLL ready interrupt
EricLew	0:80ee8f3b695e	2971	* @arg RCC_IT_PLLSAI1RDY: PLLSAI1 ready interrupt
EricLew	0:80ee8f3b695e	2972	* @arg RCC_IT_PLLSAI2RDY: PLLSAI2 ready interrupt
EricLew	0:80ee8f3b695e	2973	* @arg RCC_IT_HSECSS: HSE Clock Security interrupt
EricLew	0:80ee8f3b695e	2974	* @arg RCC_IT_LSECSS: Clock security system interrupt
EricLew	0:80ee8f3b695e	2975	* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
EricLew	0:80ee8f3b695e	2976	*/
EricLew	0:80ee8f3b695e	2977	#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__))
EricLew	0:80ee8f3b695e	2978
EricLew	0:80ee8f3b695e	2979	/** @brief Set RMVF bit to clear the reset flags.
EricLew	0:80ee8f3b695e	2980	* The reset flags are: RCC_FLAG_FWRRST, RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_BORRST,
EricLew	0:80ee8f3b695e	2981	* RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
EricLew	0:80ee8f3b695e	2982	* @retval None
EricLew	0:80ee8f3b695e	2983	*/
EricLew	0:80ee8f3b695e	2984	#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR \|= RCC_CSR_RMVF)
EricLew	0:80ee8f3b695e	2985
EricLew	0:80ee8f3b695e	2986	/** @brief Check whether the selected RCC flag is set or not.
EricLew	0:80ee8f3b695e	2987	* @param __FLAG__: specifies the flag to check.
EricLew	0:80ee8f3b695e	2988	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2989	* @arg RCC_FLAG_MSIRDY: MSI oscillator clock ready
EricLew	0:80ee8f3b695e	2990	* @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
EricLew	0:80ee8f3b695e	2991	* @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
EricLew	0:80ee8f3b695e	2992	* @arg RCC_FLAG_PLLRDY: main PLL clock ready
EricLew	0:80ee8f3b695e	2993	* @arg RCC_FLAG_PLLSAI2RDY: PLLSAI2 clock ready
EricLew	0:80ee8f3b695e	2994	* @arg RCC_FLAG_PLLSAI1RDY: PLLSAI1 clock ready
EricLew	0:80ee8f3b695e	2995	* @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
EricLew	0:80ee8f3b695e	2996	* @arg RCC_FLAG_LSECSSD: Clock security system failure on LSE oscillator detection
EricLew	0:80ee8f3b695e	2997	* @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
EricLew	0:80ee8f3b695e	2998	* @arg RCC_FLAG_BORRST: BOR reset
EricLew	0:80ee8f3b695e	2999	* @arg RCC_FLAG_OBLRST: OBLRST reset
EricLew	0:80ee8f3b695e	3000	* @arg RCC_FLAG_PINRST: Pin reset
EricLew	0:80ee8f3b695e	3001	* @arg RCC_FLAG_FWRST: FIREWALL reset
EricLew	0:80ee8f3b695e	3002	* @arg RCC_FLAG_RMVF: Remove reset Flag
EricLew	0:80ee8f3b695e	3003	* @arg RCC_FLAG_SFTRST: Software reset
EricLew	0:80ee8f3b695e	3004	* @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
EricLew	0:80ee8f3b695e	3005	* @arg RCC_FLAG_WWDGRST: Window Watchdog reset
EricLew	0:80ee8f3b695e	3006	* @arg RCC_FLAG_LPWRRST: Low Power reset
EricLew	0:80ee8f3b695e	3007	* @retval The new state of __FLAG__ (TRUE or FALSE).
EricLew	0:80ee8f3b695e	3008	*/
EricLew	0:80ee8f3b695e	3009	#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U) ? RCC->CR : \
EricLew	0:80ee8f3b695e	3010	((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \
EricLew	0:80ee8f3b695e	3011	((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR))) & \
EricLew	0:80ee8f3b695e	3012	((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK))) != 0) \
EricLew	0:80ee8f3b695e	3013	? 1 : 0)
EricLew	0:80ee8f3b695e	3014
EricLew	0:80ee8f3b695e	3015	/**
EricLew	0:80ee8f3b695e	3016	* @}
EricLew	0:80ee8f3b695e	3017	*/
EricLew	0:80ee8f3b695e	3018
EricLew	0:80ee8f3b695e	3019	/**
EricLew	0:80ee8f3b695e	3020	* @}
EricLew	0:80ee8f3b695e	3021	*/
EricLew	0:80ee8f3b695e	3022
EricLew	0:80ee8f3b695e	3023	/* Private constants ---------------------------------------------------------*/
EricLew	0:80ee8f3b695e	3024	/** @defgroup RCC_Private_Constants RCC Private Constants
EricLew	0:80ee8f3b695e	3025	* @{
EricLew	0:80ee8f3b695e	3026	*/
EricLew	0:80ee8f3b695e	3027	/* Defines used for Flags */
EricLew	0:80ee8f3b695e	3028	#define CR_REG_INDEX ((uint32_t)1)
EricLew	0:80ee8f3b695e	3029	#define BDCR_REG_INDEX ((uint32_t)2)
EricLew	0:80ee8f3b695e	3030	#define CSR_REG_INDEX ((uint32_t)3)
EricLew	0:80ee8f3b695e	3031
EricLew	0:80ee8f3b695e	3032	#define RCC_FLAG_MASK ((uint32_t)0x1F)
EricLew	0:80ee8f3b695e	3033	/**
EricLew	0:80ee8f3b695e	3034	* @}
EricLew	0:80ee8f3b695e	3035	*/
EricLew	0:80ee8f3b695e	3036
EricLew	0:80ee8f3b695e	3037	/* Private macros ------------------------------------------------------------*/
EricLew	0:80ee8f3b695e	3038	/** @addtogroup RCC_Private_Macros
EricLew	0:80ee8f3b695e	3039	* @{
EricLew	0:80ee8f3b695e	3040	*/
EricLew	0:80ee8f3b695e	3041
EricLew	0:80ee8f3b695e	3042	#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) \|\| \
EricLew	0:80ee8f3b695e	3043	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) \|\| \
EricLew	0:80ee8f3b695e	3044	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) \|\| \
EricLew	0:80ee8f3b695e	3045	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) \|\| \
EricLew	0:80ee8f3b695e	3046	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) \|\| \
EricLew	0:80ee8f3b695e	3047	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
EricLew	0:80ee8f3b695e	3048
EricLew	0:80ee8f3b695e	3049	#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) \|\| ((__HSE__) == RCC_HSE_ON) \|\| \
EricLew	0:80ee8f3b695e	3050	((__HSE__) == RCC_HSE_BYPASS))
EricLew	0:80ee8f3b695e	3051
EricLew	0:80ee8f3b695e	3052	#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) \|\| ((__LSE__) == RCC_LSE_ON) \|\| \
EricLew	0:80ee8f3b695e	3053	((__LSE__) == RCC_LSE_BYPASS))
EricLew	0:80ee8f3b695e	3054
EricLew	0:80ee8f3b695e	3055	#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) \|\| ((__HSI__) == RCC_HSI_ON))
EricLew	0:80ee8f3b695e	3056
EricLew	0:80ee8f3b695e	3057	#define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)31)
EricLew	0:80ee8f3b695e	3058
EricLew	0:80ee8f3b695e	3059	#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) \|\| ((__LSI__) == RCC_LSI_ON))
EricLew	0:80ee8f3b695e	3060
EricLew	0:80ee8f3b695e	3061	#define IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) \|\| ((__MSI__) == RCC_MSI_ON))
EricLew	0:80ee8f3b695e	3062
EricLew	0:80ee8f3b695e	3063	#define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)255)
EricLew	0:80ee8f3b695e	3064
EricLew	0:80ee8f3b695e	3065	#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) \|\|((__PLL__) == RCC_PLL_OFF) \|\| \
EricLew	0:80ee8f3b695e	3066	((__PLL__) == RCC_PLL_ON))
EricLew	0:80ee8f3b695e	3067
EricLew	0:80ee8f3b695e	3068	#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_NONE) \|\| \
EricLew	0:80ee8f3b695e	3069	((__SOURCE__) == RCC_PLLSOURCE_MSI) \|\| \
EricLew	0:80ee8f3b695e	3070	((__SOURCE__) == RCC_PLLSOURCE_HSI) \|\| \
EricLew	0:80ee8f3b695e	3071	((__SOURCE__) == RCC_PLLSOURCE_HSE))
EricLew	0:80ee8f3b695e	3072
EricLew	0:80ee8f3b695e	3073	#define IS_RCC_PLLM_VALUE(__VALUE__) ((__VALUE__) <= 8)
EricLew	0:80ee8f3b695e	3074
EricLew	0:80ee8f3b695e	3075	#define IS_RCC_PLLN_VALUE(__VALUE__) ((8 <= (__VALUE__)) && ((__VALUE__) <= 86))
EricLew	0:80ee8f3b695e	3076
EricLew	0:80ee8f3b695e	3077	#define IS_RCC_PLLP_VALUE(__VALUE__) (((__VALUE__) == 7) \|\| ((__VALUE__) == 17))
EricLew	0:80ee8f3b695e	3078
EricLew	0:80ee8f3b695e	3079	#define IS_RCC_PLLQ_VALUE(__VALUE__) (((__VALUE__) == 2 ) \|\| ((__VALUE__) == 4) \|\| \
EricLew	0:80ee8f3b695e	3080	((__VALUE__) == 6) \|\| ((__VALUE__) == 8))
EricLew	0:80ee8f3b695e	3081
EricLew	0:80ee8f3b695e	3082	#define IS_RCC_PLLR_VALUE(__VALUE__) (((__VALUE__) == 2 ) \|\| ((__VALUE__) == 4) \|\| \
EricLew	0:80ee8f3b695e	3083	((__VALUE__) == 6) \|\| ((__VALUE__) == 8))
EricLew	0:80ee8f3b695e	3084
EricLew	0:80ee8f3b695e	3085	#define IS_RCC_PLLSAI1CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI1_SAI1CLK) == RCC_PLLSAI1_SAI1CLK) \|\| \
EricLew	0:80ee8f3b695e	3086	(((__VALUE__) & RCC_PLLSAI1_48M2CLK) == RCC_PLLSAI1_48M2CLK) \|\| \
EricLew	0:80ee8f3b695e	3087	(((__VALUE__) & RCC_PLLSAI1_ADC1CLK) == RCC_PLLSAI1_ADC1CLK)) && \
EricLew	0:80ee8f3b695e	3088	(((__VALUE__) & ~(RCC_PLLSAI1_SAI1CLK\|RCC_PLLSAI1_48M2CLK\|RCC_PLLSAI1_ADC1CLK)) == 0))
EricLew	0:80ee8f3b695e	3089
EricLew	0:80ee8f3b695e	3090	#define IS_RCC_PLLSAI2CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI2_SAI2CLK) == RCC_PLLSAI2_SAI2CLK ) \|\| \
EricLew	0:80ee8f3b695e	3091	(((__VALUE__) & RCC_PLLSAI2_ADC2CLK) == RCC_PLLSAI2_ADC2CLK)) && \
EricLew	0:80ee8f3b695e	3092	(((__VALUE__) & ~(RCC_PLLSAI2_SAI2CLK\|RCC_PLLSAI2_ADC2CLK)) == 0))
EricLew	0:80ee8f3b695e	3093
EricLew	0:80ee8f3b695e	3094	#define IS_RCC_MSI_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0) \|\| \
EricLew	0:80ee8f3b695e	3095	((__RANGE__) == RCC_MSIRANGE_1) \|\| \
EricLew	0:80ee8f3b695e	3096	((__RANGE__) == RCC_MSIRANGE_2) \|\| \
EricLew	0:80ee8f3b695e	3097	((__RANGE__) == RCC_MSIRANGE_3) \|\| \
EricLew	0:80ee8f3b695e	3098	((__RANGE__) == RCC_MSIRANGE_4) \|\| \
EricLew	0:80ee8f3b695e	3099	((__RANGE__) == RCC_MSIRANGE_5) \|\| \
EricLew	0:80ee8f3b695e	3100	((__RANGE__) == RCC_MSIRANGE_6) \|\| \
EricLew	0:80ee8f3b695e	3101	((__RANGE__) == RCC_MSIRANGE_7) \|\| \
EricLew	0:80ee8f3b695e	3102	((__RANGE__) == RCC_MSIRANGE_8) \|\| \
EricLew	0:80ee8f3b695e	3103	((__RANGE__) == RCC_MSIRANGE_9) \|\| \
EricLew	0:80ee8f3b695e	3104	((__RANGE__) == RCC_MSIRANGE_10) \|\| \
EricLew	0:80ee8f3b695e	3105	((__RANGE__) == RCC_MSIRANGE_11))
EricLew	0:80ee8f3b695e	3106
EricLew	0:80ee8f3b695e	3107	#define IS_RCC_MSI_STANDBY_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_4) \|\| \
EricLew	0:80ee8f3b695e	3108	((__RANGE__) == RCC_MSIRANGE_5) \|\| \
EricLew	0:80ee8f3b695e	3109	((__RANGE__) == RCC_MSIRANGE_6) \|\| \
EricLew	0:80ee8f3b695e	3110	((__RANGE__) == RCC_MSIRANGE_7))
EricLew	0:80ee8f3b695e	3111
EricLew	0:80ee8f3b695e	3112	#define IS_RCC_CLOCKTYPE(__CLK__) ((1 <= (__CLK__)) && ((__CLK__) <= 15))
EricLew	0:80ee8f3b695e	3113
EricLew	0:80ee8f3b695e	3114	#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) \|\| \
EricLew	0:80ee8f3b695e	3115	((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) \|\| \
EricLew	0:80ee8f3b695e	3116	((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) \|\| \
EricLew	0:80ee8f3b695e	3117	((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
EricLew	0:80ee8f3b695e	3118
EricLew	0:80ee8f3b695e	3119	#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) \|\| ((__HCLK__) == RCC_SYSCLK_DIV2) \|\| \
EricLew	0:80ee8f3b695e	3120	((__HCLK__) == RCC_SYSCLK_DIV4) \|\| ((__HCLK__) == RCC_SYSCLK_DIV8) \|\| \
EricLew	0:80ee8f3b695e	3121	((__HCLK__) == RCC_SYSCLK_DIV16) \|\| ((__HCLK__) == RCC_SYSCLK_DIV64) \|\| \
EricLew	0:80ee8f3b695e	3122	((__HCLK__) == RCC_SYSCLK_DIV128) \|\| ((__HCLK__) == RCC_SYSCLK_DIV256) \|\| \
EricLew	0:80ee8f3b695e	3123	((__HCLK__) == RCC_SYSCLK_DIV512))
EricLew	0:80ee8f3b695e	3124
EricLew	0:80ee8f3b695e	3125	#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) \|\| ((__PCLK__) == RCC_HCLK_DIV2) \|\| \
EricLew	0:80ee8f3b695e	3126	((__PCLK__) == RCC_HCLK_DIV4) \|\| ((__PCLK__) == RCC_HCLK_DIV8) \|\| \
EricLew	0:80ee8f3b695e	3127	((__PCLK__) == RCC_HCLK_DIV16))
EricLew	0:80ee8f3b695e	3128
EricLew	0:80ee8f3b695e	3129	#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) \|\| \
EricLew	0:80ee8f3b695e	3130	((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) \|\| \
EricLew	0:80ee8f3b695e	3131	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32))
EricLew	0:80ee8f3b695e	3132
EricLew	0:80ee8f3b695e	3133	#define IS_RCC_MCO(__MCOX__) ((__MCOX__) == RCC_MCO1)
EricLew	0:80ee8f3b695e	3134
EricLew	0:80ee8f3b695e	3135	#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) \|\| \
EricLew	0:80ee8f3b695e	3136	((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) \|\| \
EricLew	0:80ee8f3b695e	3137	((__SOURCE__) == RCC_MCO1SOURCE_MSI) \|\| \
EricLew	0:80ee8f3b695e	3138	((__SOURCE__) == RCC_MCO1SOURCE_HSI) \|\| \
EricLew	0:80ee8f3b695e	3139	((__SOURCE__) == RCC_MCO1SOURCE_HSE) \|\| \
EricLew	0:80ee8f3b695e	3140	((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \|\| \
EricLew	0:80ee8f3b695e	3141	((__SOURCE__) == RCC_MCO1SOURCE_LSI) \|\| \
EricLew	0:80ee8f3b695e	3142	((__SOURCE__) == RCC_MCO1SOURCE_LSE))
EricLew	0:80ee8f3b695e	3143
EricLew	0:80ee8f3b695e	3144	#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) \|\| ((__DIV__) == RCC_MCODIV_2) \|\| \
EricLew	0:80ee8f3b695e	3145	((__DIV__) == RCC_MCODIV_4) \|\| ((__DIV__) == RCC_MCODIV_8) \|\| \
EricLew	0:80ee8f3b695e	3146	((__DIV__) == RCC_MCODIV_16))
EricLew	0:80ee8f3b695e	3147
EricLew	0:80ee8f3b695e	3148	#define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) \|\| \
EricLew	0:80ee8f3b695e	3149	((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) \|\| \
EricLew	0:80ee8f3b695e	3150	((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) \|\| \
EricLew	0:80ee8f3b695e	3151	((__DRIVE__) == RCC_LSEDRIVE_HIGH))
EricLew	0:80ee8f3b695e	3152
EricLew	0:80ee8f3b695e	3153	#define IS_RCC_STOP_WAKEUPCLOCK(__SOURCE__) (((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_MSI) \|\| \
EricLew	0:80ee8f3b695e	3154	((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_HSI))
EricLew	0:80ee8f3b695e	3155	/**
EricLew	0:80ee8f3b695e	3156	* @}
EricLew	0:80ee8f3b695e	3157	*/
EricLew	0:80ee8f3b695e	3158
EricLew	0:80ee8f3b695e	3159	/* Include RCC HAL Extended module */
EricLew	0:80ee8f3b695e	3160	#include "stm32l4xx_hal_rcc_ex.h"
EricLew	0:80ee8f3b695e	3161
EricLew	0:80ee8f3b695e	3162	/* Exported functions --------------------------------------------------------*/
EricLew	0:80ee8f3b695e	3163	/** @addtogroup RCC_Exported_Functions
EricLew	0:80ee8f3b695e	3164	* @{
EricLew	0:80ee8f3b695e	3165	*/
EricLew	0:80ee8f3b695e	3166
EricLew	0:80ee8f3b695e	3167
EricLew	0:80ee8f3b695e	3168	/** @addtogroup RCC_Exported_Functions_Group1
EricLew	0:80ee8f3b695e	3169	* @{
EricLew	0:80ee8f3b695e	3170	*/
EricLew	0:80ee8f3b695e	3171
EricLew	0:80ee8f3b695e	3172	/* Initialization and de-initialization functions ******************************/
EricLew	0:80ee8f3b695e	3173	void HAL_RCC_DeInit(void);
EricLew	0:80ee8f3b695e	3174	HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
EricLew	0:80ee8f3b695e	3175	HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
EricLew	0:80ee8f3b695e	3176
EricLew	0:80ee8f3b695e	3177	/**
EricLew	0:80ee8f3b695e	3178	* @}
EricLew	0:80ee8f3b695e	3179	*/
EricLew	0:80ee8f3b695e	3180
EricLew	0:80ee8f3b695e	3181	/** @addtogroup RCC_Exported_Functions_Group2
EricLew	0:80ee8f3b695e	3182	* @{
EricLew	0:80ee8f3b695e	3183	*/
EricLew	0:80ee8f3b695e	3184
EricLew	0:80ee8f3b695e	3185	/* Peripheral Control functions ************************************************/
EricLew	0:80ee8f3b695e	3186	void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
EricLew	0:80ee8f3b695e	3187	void HAL_RCC_EnableCSS(void);
EricLew	0:80ee8f3b695e	3188	uint32_t HAL_RCC_GetSysClockFreq(void);
EricLew	0:80ee8f3b695e	3189	uint32_t HAL_RCC_GetHCLKFreq(void);
EricLew	0:80ee8f3b695e	3190	uint32_t HAL_RCC_GetPCLK1Freq(void);
EricLew	0:80ee8f3b695e	3191	uint32_t HAL_RCC_GetPCLK2Freq(void);
EricLew	0:80ee8f3b695e	3192	void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
EricLew	0:80ee8f3b695e	3193	void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef RCC_ClkInitStruct, uint32_t pFLatency);
EricLew	0:80ee8f3b695e	3194	/* CSS NMI IRQ handler */
EricLew	0:80ee8f3b695e	3195	void HAL_RCC_NMI_IRQHandler(void);
EricLew	0:80ee8f3b695e	3196	/* User Callbacks in non blocking mode (IT mode) */
EricLew	0:80ee8f3b695e	3197	void HAL_RCC_CSSCallback(void);
EricLew	0:80ee8f3b695e	3198
EricLew	0:80ee8f3b695e	3199	/**
EricLew	0:80ee8f3b695e	3200	* @}
EricLew	0:80ee8f3b695e	3201	*/
EricLew	0:80ee8f3b695e	3202
EricLew	0:80ee8f3b695e	3203	/**
EricLew	0:80ee8f3b695e	3204	* @}
EricLew	0:80ee8f3b695e	3205	*/
EricLew	0:80ee8f3b695e	3206
EricLew	0:80ee8f3b695e	3207	/**
EricLew	0:80ee8f3b695e	3208	* @}
EricLew	0:80ee8f3b695e	3209	*/
EricLew	0:80ee8f3b695e	3210
EricLew	0:80ee8f3b695e	3211	/**
EricLew	0:80ee8f3b695e	3212	* @}
EricLew	0:80ee8f3b695e	3213	*/
EricLew	0:80ee8f3b695e	3214
EricLew	0:80ee8f3b695e	3215	#ifdef __cplusplus
EricLew	0:80ee8f3b695e	3216	}
EricLew	0:80ee8f3b695e	3217	#endif
EricLew	0:80ee8f3b695e	3218
EricLew	0:80ee8f3b695e	3219	#endif /* __STM32L4xx_HAL_RCC_H */
EricLew	0:80ee8f3b695e	3220
EricLew	0:80ee8f3b695e	3221	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
EricLew	0:80ee8f3b695e	3222

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Type:	Library
Created:	12 Nov 2015
Imports:	198
Forks:	0
Commits:	3
Dependents:	4
Dependencies:	0
Followers:	14

Inc/stm32l4xx_hal_rcc.h@2:7aef7655b0a8, 2015-11-25 (annotated)

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