Eric Lewiston / STM32L4xx_HAL_Driver

Hal Drivers for L4

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Fork of STM32L4xx_HAL_Driver by Senior Design: Sound Monitor

Inc/stm32l4xx_hal_qspi.h@2:7aef7655b0a8, 2015-11-25 (annotated)

Committer:
EricLew
Date:
Wed Nov 25 17:30:43 2015 +0000
Revision:
2:7aef7655b0a8
Parent:
0:80ee8f3b695e 
commit;

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EricLew 0:80ee8f3b695e 1 /**
EricLew 0:80ee8f3b695e 2 ******************************************************************************
EricLew 0:80ee8f3b695e 3 * @file stm32l4xx_hal_qspi.h
EricLew 0:80ee8f3b695e 4 * @author MCD Application Team
EricLew 0:80ee8f3b695e 5 * @version V1.1.0
EricLew 0:80ee8f3b695e 6 * @date 16-September-2015
EricLew 0:80ee8f3b695e 7 * @brief Header file of QSPI HAL module.
EricLew 0:80ee8f3b695e 8 ******************************************************************************
EricLew 0:80ee8f3b695e 9 * @attention
EricLew 0:80ee8f3b695e 10 *
EricLew 0:80ee8f3b695e 11 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
EricLew 0:80ee8f3b695e 12 *
EricLew 0:80ee8f3b695e 13 * Redistribution and use in source and binary forms, with or without modification,
EricLew 0:80ee8f3b695e 14 * are permitted provided that the following conditions are met:
EricLew 0:80ee8f3b695e 15 * 1. Redistributions of source code must retain the above copyright notice,
EricLew 0:80ee8f3b695e 16 * this list of conditions and the following disclaimer.
EricLew 0:80ee8f3b695e 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
EricLew 0:80ee8f3b695e 18 * this list of conditions and the following disclaimer in the documentation
EricLew 0:80ee8f3b695e 19 * and/or other materials provided with the distribution.
EricLew 0:80ee8f3b695e 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
EricLew 0:80ee8f3b695e 21 * may be used to endorse or promote products derived from this software
EricLew 0:80ee8f3b695e 22 * without specific prior written permission.
EricLew 0:80ee8f3b695e 23 *
EricLew 0:80ee8f3b695e 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
EricLew 0:80ee8f3b695e 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
EricLew 0:80ee8f3b695e 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
EricLew 0:80ee8f3b695e 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
EricLew 0:80ee8f3b695e 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
EricLew 0:80ee8f3b695e 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
EricLew 0:80ee8f3b695e 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
EricLew 0:80ee8f3b695e 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
EricLew 0:80ee8f3b695e 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
EricLew 0:80ee8f3b695e 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
EricLew 0:80ee8f3b695e 34 *
EricLew 0:80ee8f3b695e 35 ******************************************************************************
EricLew 0:80ee8f3b695e 36 */
EricLew 0:80ee8f3b695e 37
EricLew 0:80ee8f3b695e 38 /* Define to prevent recursive inclusion -------------------------------------*/
EricLew 0:80ee8f3b695e 39 #ifndef __STM32L4xx_HAL_QSPI_H
EricLew 0:80ee8f3b695e 40 #define __STM32L4xx_HAL_QSPI_H
EricLew 0:80ee8f3b695e 41
EricLew 0:80ee8f3b695e 42 #ifdef __cplusplus
EricLew 0:80ee8f3b695e 43 extern "C" {
EricLew 0:80ee8f3b695e 44 #endif
EricLew 0:80ee8f3b695e 45
EricLew 0:80ee8f3b695e 46 /* Includes ------------------------------------------------------------------*/
EricLew 0:80ee8f3b695e 47 #include "stm32l4xx_hal_def.h"
EricLew 0:80ee8f3b695e 48
EricLew 0:80ee8f3b695e 49 /** @addtogroup STM32L4xx_HAL_Driver
EricLew 0:80ee8f3b695e 50 * @{
EricLew 0:80ee8f3b695e 51 */
EricLew 0:80ee8f3b695e 52
EricLew 0:80ee8f3b695e 53 /** @addtogroup QSPI
EricLew 0:80ee8f3b695e 54 * @{
EricLew 0:80ee8f3b695e 55 */
EricLew 0:80ee8f3b695e 56
EricLew 0:80ee8f3b695e 57 /* Exported types ------------------------------------------------------------*/
EricLew 0:80ee8f3b695e 58 /** @defgroup QSPI_Exported_Types QSPI Exported Types
EricLew 0:80ee8f3b695e 59 * @{
EricLew 0:80ee8f3b695e 60 */
EricLew 0:80ee8f3b695e 61
EricLew 0:80ee8f3b695e 62 /**
EricLew 0:80ee8f3b695e 63 * @brief QSPI Init structure definition
EricLew 0:80ee8f3b695e 64 */
EricLew 0:80ee8f3b695e 65 typedef struct
EricLew 0:80ee8f3b695e 66 {
EricLew 0:80ee8f3b695e 67 uint32_t ClockPrescaler; /* Specifies the prescaler factor for generating clock based on the AHB clock.
EricLew 0:80ee8f3b695e 68 This parameter can be a number between 0 and 255 */
EricLew 0:80ee8f3b695e 69 uint32_t FifoThreshold; /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode)
EricLew 0:80ee8f3b695e 70 This parameter can be a value between 1 and 16 */
EricLew 0:80ee8f3b695e 71 uint32_t SampleShifting; /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to
EricLew 0:80ee8f3b695e 72 take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode)
EricLew 0:80ee8f3b695e 73 This parameter can be a value of @ref QSPI_SampleShifting */
EricLew 0:80ee8f3b695e 74 uint32_t FlashSize; /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits
EricLew 0:80ee8f3b695e 75 required to address the flash memory. The flash capacity can be up to 4GB
EricLew 0:80ee8f3b695e 76 (addressed using 32 bits) in indirect mode, but the addressable space in
EricLew 0:80ee8f3b695e 77 memory-mapped mode is limited to 256MB
EricLew 0:80ee8f3b695e 78 This parameter can be a number between 0 and 31 */
EricLew 0:80ee8f3b695e 79 uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number
EricLew 0:80ee8f3b695e 80 of clock cycles which the chip select must remain high between commands.
EricLew 0:80ee8f3b695e 81 This parameter can be a value of @ref QSPI_ChipSelectHighTime */
EricLew 0:80ee8f3b695e 82 uint32_t ClockMode; /* Specifies the Clock Mode. It indicates the level that clock takes between commands.
EricLew 0:80ee8f3b695e 83 This parameter can be a value of @ref QSPI_ClockMode */
EricLew 0:80ee8f3b695e 84 }QSPI_InitTypeDef;
EricLew 0:80ee8f3b695e 85
EricLew 0:80ee8f3b695e 86 /**
EricLew 0:80ee8f3b695e 87 * @brief HAL QSPI State structures definition
EricLew 0:80ee8f3b695e 88 */
EricLew 0:80ee8f3b695e 89 typedef enum
EricLew 0:80ee8f3b695e 90 {
EricLew 0:80ee8f3b695e 91 HAL_QSPI_STATE_RESET = 0x00, /*!< Peripheral not initialized */
EricLew 0:80ee8f3b695e 92 HAL_QSPI_STATE_READY = 0x01, /*!< Peripheral initialized and ready for use */
EricLew 0:80ee8f3b695e 93 HAL_QSPI_STATE_BUSY = 0x02, /*!< Peripheral in indirect mode and busy */
EricLew 0:80ee8f3b695e 94 HAL_QSPI_STATE_BUSY_INDIRECT_TX = 0x12, /*!< Peripheral in indirect mode with transmission ongoing */
EricLew 0:80ee8f3b695e 95 HAL_QSPI_STATE_BUSY_INDIRECT_RX = 0x22, /*!< Peripheral in indirect mode with reception ongoing */
EricLew 0:80ee8f3b695e 96 HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42, /*!< Peripheral in auto polling mode ongoing */
EricLew 0:80ee8f3b695e 97 HAL_QSPI_STATE_BUSY_MEM_MAPPED = 0x82, /*!< Peripheral in memory mapped mode ongoing */
EricLew 0:80ee8f3b695e 98 HAL_QSPI_STATE_ERROR = 0x04 /*!< Peripheral in error */
EricLew 0:80ee8f3b695e 99 }HAL_QSPI_StateTypeDef;
EricLew 0:80ee8f3b695e 100
EricLew 0:80ee8f3b695e 101 /**
EricLew 0:80ee8f3b695e 102 * @brief QSPI Handle Structure definition
EricLew 0:80ee8f3b695e 103 */
EricLew 0:80ee8f3b695e 104 typedef struct
EricLew 0:80ee8f3b695e 105 {
EricLew 0:80ee8f3b695e 106 QUADSPI_TypeDef *Instance; /* QSPI registers base address */
EricLew 0:80ee8f3b695e 107 QSPI_InitTypeDef Init; /* QSPI communication parameters */
EricLew 0:80ee8f3b695e 108 uint8_t *pTxBuffPtr; /* Pointer to QSPI Tx transfer Buffer */
EricLew 0:80ee8f3b695e 109 __IO uint16_t TxXferSize; /* QSPI Tx Transfer size */
EricLew 0:80ee8f3b695e 110 __IO uint16_t TxXferCount; /* QSPI Tx Transfer Counter */
EricLew 0:80ee8f3b695e 111 uint8_t *pRxBuffPtr; /* Pointer to QSPI Rx transfer Buffer */
EricLew 0:80ee8f3b695e 112 __IO uint16_t RxXferSize; /* QSPI Rx Transfer size */
EricLew 0:80ee8f3b695e 113 __IO uint16_t RxXferCount; /* QSPI Rx Transfer Counter */
EricLew 0:80ee8f3b695e 114 DMA_HandleTypeDef *hdma; /* QSPI Rx/Tx DMA Handle parameters */
EricLew 0:80ee8f3b695e 115 __IO HAL_LockTypeDef Lock; /* Locking object */
EricLew 0:80ee8f3b695e 116 __IO HAL_QSPI_StateTypeDef State; /* QSPI communication state */
EricLew 0:80ee8f3b695e 117 __IO uint32_t ErrorCode; /* QSPI Error code */
EricLew 0:80ee8f3b695e 118 uint32_t Timeout; /* Timeout for the QSPI memory access */
EricLew 0:80ee8f3b695e 119 }QSPI_HandleTypeDef;
EricLew 0:80ee8f3b695e 120
EricLew 0:80ee8f3b695e 121 /**
EricLew 0:80ee8f3b695e 122 * @brief QSPI Command structure definition
EricLew 0:80ee8f3b695e 123 */
EricLew 0:80ee8f3b695e 124 typedef struct
EricLew 0:80ee8f3b695e 125 {
EricLew 0:80ee8f3b695e 126 uint32_t Instruction; /* Specifies the Instruction to be sent
EricLew 0:80ee8f3b695e 127 This parameter can be a value (8-bit) between 0x00 and 0xFF */
EricLew 0:80ee8f3b695e 128 uint32_t Address; /* Specifies the Address to be sent (Size from 1 to 4 bytes according AddressSize)
EricLew 0:80ee8f3b695e 129 This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */
EricLew 0:80ee8f3b695e 130 uint32_t AlternateBytes; /* Specifies the Alternate Bytes to be sent (Size from 1 to 4 bytes according AlternateBytesSize)
EricLew 0:80ee8f3b695e 131 This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */
EricLew 0:80ee8f3b695e 132 uint32_t AddressSize; /* Specifies the Address Size
EricLew 0:80ee8f3b695e 133 This parameter can be a value of @ref QSPI_AddressSize */
EricLew 0:80ee8f3b695e 134 uint32_t AlternateBytesSize; /* Specifies the Alternate Bytes Size
EricLew 0:80ee8f3b695e 135 This parameter can be a value of @ref QSPI_AlternateBytesSize */
EricLew 0:80ee8f3b695e 136 uint32_t DummyCycles; /* Specifies the Number of Dummy Cycles.
EricLew 0:80ee8f3b695e 137 This parameter can be a number between 0 and 31 */
EricLew 0:80ee8f3b695e 138 uint32_t InstructionMode; /* Specifies the Instruction Mode
EricLew 0:80ee8f3b695e 139 This parameter can be a value of @ref QSPI_InstructionMode */
EricLew 0:80ee8f3b695e 140 uint32_t AddressMode; /* Specifies the Address Mode
EricLew 0:80ee8f3b695e 141 This parameter can be a value of @ref QSPI_AddressMode */
EricLew 0:80ee8f3b695e 142 uint32_t AlternateByteMode; /* Specifies the Alternate Bytes Mode
EricLew 0:80ee8f3b695e 143 This parameter can be a value of @ref QSPI_AlternateBytesMode */
EricLew 0:80ee8f3b695e 144 uint32_t DataMode; /* Specifies the Data Mode (used for dummy cycles and data phases)
EricLew 0:80ee8f3b695e 145 This parameter can be a value of @ref QSPI_DataMode */
EricLew 0:80ee8f3b695e 146 uint32_t NbData; /* Specifies the number of data to transfer.
EricLew 0:80ee8f3b695e 147 This parameter can be any value between 0 and 0xFFFFFFFF (0 means undefined length
EricLew 0:80ee8f3b695e 148 until end of memory)*/
EricLew 0:80ee8f3b695e 149 uint32_t DdrMode; /* Specifies the double data rate mode for address, alternate byte and data phase
EricLew 0:80ee8f3b695e 150 This parameter can be a value of @ref QSPI_DdrMode */
EricLew 0:80ee8f3b695e 151 uint32_t DdrHoldHalfCycle; /* Specifies the DDR hold half cycle. It delays the data output by one half of
EricLew 0:80ee8f3b695e 152 system clock in DDR mode. Not available on STM32L4x6 devices but in future devices.
EricLew 0:80ee8f3b695e 153 This parameter can be a value of @ref QSPI_DdrHoldHalfCycle */
EricLew 0:80ee8f3b695e 154 uint32_t SIOOMode; /* Specifies the send instruction only once mode
EricLew 0:80ee8f3b695e 155 This parameter can be a value of @ref QSPI_SIOOMode */
EricLew 0:80ee8f3b695e 156 }QSPI_CommandTypeDef;
EricLew 0:80ee8f3b695e 157
EricLew 0:80ee8f3b695e 158 /**
EricLew 0:80ee8f3b695e 159 * @brief QSPI Auto Polling mode configuration structure definition
EricLew 0:80ee8f3b695e 160 */
EricLew 0:80ee8f3b695e 161 typedef struct
EricLew 0:80ee8f3b695e 162 {
EricLew 0:80ee8f3b695e 163 uint32_t Match; /* Specifies the value to be compared with the masked status register to get a match.
EricLew 0:80ee8f3b695e 164 This parameter can be any value between 0 and 0xFFFFFFFF */
EricLew 0:80ee8f3b695e 165 uint32_t Mask; /* Specifies the mask to be applied to the status bytes received.
EricLew 0:80ee8f3b695e 166 This parameter can be any value between 0 and 0xFFFFFFFF */
EricLew 0:80ee8f3b695e 167 uint32_t Interval; /* Specifies the number of clock cycles between two read during automatic polling phases.
EricLew 0:80ee8f3b695e 168 This parameter can be any value between 0 and 0xFFFF */
EricLew 0:80ee8f3b695e 169 uint32_t StatusBytesSize; /* Specifies the size of the status bytes received.
EricLew 0:80ee8f3b695e 170 This parameter can be any value between 1 and 4 */
EricLew 0:80ee8f3b695e 171 uint32_t MatchMode; /* Specifies the method used for determining a match.
EricLew 0:80ee8f3b695e 172 This parameter can be a value of @ref QSPI_MatchMode */
EricLew 0:80ee8f3b695e 173 uint32_t AutomaticStop; /* Specifies if automatic polling is stopped after a match.
EricLew 0:80ee8f3b695e 174 This parameter can be a value of @ref QSPI_AutomaticStop */
EricLew 0:80ee8f3b695e 175 }QSPI_AutoPollingTypeDef;
EricLew 0:80ee8f3b695e 176
EricLew 0:80ee8f3b695e 177 /**
EricLew 0:80ee8f3b695e 178 * @brief QSPI Memory Mapped mode configuration structure definition
EricLew 0:80ee8f3b695e 179 */
EricLew 0:80ee8f3b695e 180 typedef struct
EricLew 0:80ee8f3b695e 181 {
EricLew 0:80ee8f3b695e 182 uint32_t TimeOutPeriod; /* Specifies the number of clock to wait when the FIFO is full before to release the chip select.
EricLew 0:80ee8f3b695e 183 This parameter can be any value between 0 and 0xFFFF */
EricLew 0:80ee8f3b695e 184 uint32_t TimeOutActivation; /* Specifies if the timeout counter is enabled to release the chip select.
EricLew 0:80ee8f3b695e 185 This parameter can be a value of @ref QSPI_TimeOutActivation */
EricLew 0:80ee8f3b695e 186 }QSPI_MemoryMappedTypeDef;
EricLew 0:80ee8f3b695e 187
EricLew 0:80ee8f3b695e 188 /**
EricLew 0:80ee8f3b695e 189 * @}
EricLew 0:80ee8f3b695e 190 */
EricLew 0:80ee8f3b695e 191
EricLew 0:80ee8f3b695e 192 /* Exported constants --------------------------------------------------------*/
EricLew 0:80ee8f3b695e 193 /** @defgroup QSPI_Exported_Constants QSPI Exported Constants
EricLew 0:80ee8f3b695e 194 * @{
EricLew 0:80ee8f3b695e 195 */
EricLew 0:80ee8f3b695e 196
EricLew 0:80ee8f3b695e 197 /** @defgroup QSPI_ErrorCode QSPI Error Code
EricLew 0:80ee8f3b695e 198 * @{
EricLew 0:80ee8f3b695e 199 */
EricLew 0:80ee8f3b695e 200 #define HAL_QSPI_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
EricLew 0:80ee8f3b695e 201 #define HAL_QSPI_ERROR_TIMEOUT ((uint32_t)0x00000001) /*!< Timeout error */
EricLew 0:80ee8f3b695e 202 #define HAL_QSPI_ERROR_TRANSFER ((uint32_t)0x00000002) /*!< Transfer error */
EricLew 0:80ee8f3b695e 203 #define HAL_QSPI_ERROR_DMA ((uint32_t)0x00000004) /*!< DMA transfer error */
EricLew 0:80ee8f3b695e 204 /**
EricLew 0:80ee8f3b695e 205 * @}
EricLew 0:80ee8f3b695e 206 */
EricLew 0:80ee8f3b695e 207
EricLew 0:80ee8f3b695e 208 /** @defgroup QSPI_SampleShifting QSPI Sample Shifting
EricLew 0:80ee8f3b695e 209 * @{
EricLew 0:80ee8f3b695e 210 */
EricLew 0:80ee8f3b695e 211 #define QSPI_SAMPLE_SHIFTING_NONE ((uint32_t)0x00000000) /*!<No clock cycle shift to sample data*/
EricLew 0:80ee8f3b695e 212 #define QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT) /*!<1/2 clock cycle shift to sample data*/
EricLew 0:80ee8f3b695e 213 /**
EricLew 0:80ee8f3b695e 214 * @}
EricLew 0:80ee8f3b695e 215 */
EricLew 0:80ee8f3b695e 216
EricLew 0:80ee8f3b695e 217 /** @defgroup QSPI_ChipSelectHighTime QSPI ChipSelect High Time
EricLew 0:80ee8f3b695e 218 * @{
EricLew 0:80ee8f3b695e 219 */
EricLew 0:80ee8f3b695e 220 #define QSPI_CS_HIGH_TIME_1_CYCLE ((uint32_t)0x00000000) /*!<nCS stay high for at least 1 clock cycle between commands*/
EricLew 0:80ee8f3b695e 221 #define QSPI_CS_HIGH_TIME_2_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 2 clock cycles between commands*/
EricLew 0:80ee8f3b695e 222 #define QSPI_CS_HIGH_TIME_3_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 3 clock cycles between commands*/
EricLew 0:80ee8f3b695e 223 #define QSPI_CS_HIGH_TIME_4_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 4 clock cycles between commands*/
EricLew 0:80ee8f3b695e 224 #define QSPI_CS_HIGH_TIME_5_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2) /*!<nCS stay high for at least 5 clock cycles between commands*/
EricLew 0:80ee8f3b695e 225 #define QSPI_CS_HIGH_TIME_6_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 6 clock cycles between commands*/
EricLew 0:80ee8f3b695e 226 #define QSPI_CS_HIGH_TIME_7_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 7 clock cycles between commands*/
EricLew 0:80ee8f3b695e 227 #define QSPI_CS_HIGH_TIME_8_CYCLE ((uint32_t)QUADSPI_DCR_CSHT) /*!<nCS stay high for at least 8 clock cycles between commands*/
EricLew 0:80ee8f3b695e 228 /**
EricLew 0:80ee8f3b695e 229 * @}
EricLew 0:80ee8f3b695e 230 */
EricLew 0:80ee8f3b695e 231
EricLew 0:80ee8f3b695e 232 /** @defgroup QSPI_ClockMode QSPI Clock Mode
EricLew 0:80ee8f3b695e 233 * @{
EricLew 0:80ee8f3b695e 234 */
EricLew 0:80ee8f3b695e 235 #define QSPI_CLOCK_MODE_0 ((uint32_t)0x00000000) /*!<Clk stays low while nCS is released*/
EricLew 0:80ee8f3b695e 236 #define QSPI_CLOCK_MODE_3 ((uint32_t)QUADSPI_DCR_CKMODE) /*!<Clk goes high while nCS is released*/
EricLew 0:80ee8f3b695e 237 /**
EricLew 0:80ee8f3b695e 238 * @}
EricLew 0:80ee8f3b695e 239 */
EricLew 0:80ee8f3b695e 240
EricLew 0:80ee8f3b695e 241 /** @defgroup QSPI_AddressSize QSPI Address Size
EricLew 0:80ee8f3b695e 242 * @{
EricLew 0:80ee8f3b695e 243 */
EricLew 0:80ee8f3b695e 244 #define QSPI_ADDRESS_8_BITS ((uint32_t)0x00000000) /*!<8-bit address*/
EricLew 0:80ee8f3b695e 245 #define QSPI_ADDRESS_16_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_0) /*!<16-bit address*/
EricLew 0:80ee8f3b695e 246 #define QSPI_ADDRESS_24_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_1) /*!<24-bit address*/
EricLew 0:80ee8f3b695e 247 #define QSPI_ADDRESS_32_BITS ((uint32_t)QUADSPI_CCR_ADSIZE) /*!<32-bit address*/
EricLew 0:80ee8f3b695e 248 /**
EricLew 0:80ee8f3b695e 249 * @}
EricLew 0:80ee8f3b695e 250 */
EricLew 0:80ee8f3b695e 251
EricLew 0:80ee8f3b695e 252 /** @defgroup QSPI_AlternateBytesSize QSPI Alternate Bytes Size
EricLew 0:80ee8f3b695e 253 * @{
EricLew 0:80ee8f3b695e 254 */
EricLew 0:80ee8f3b695e 255 #define QSPI_ALTERNATE_BYTES_8_BITS ((uint32_t)0x00000000) /*!<8-bit alternate bytes*/
EricLew 0:80ee8f3b695e 256 #define QSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_0) /*!<16-bit alternate bytes*/
EricLew 0:80ee8f3b695e 257 #define QSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_1) /*!<24-bit alternate bytes*/
EricLew 0:80ee8f3b695e 258 #define QSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)QUADSPI_CCR_ABSIZE) /*!<32-bit alternate bytes*/
EricLew 0:80ee8f3b695e 259 /**
EricLew 0:80ee8f3b695e 260 * @}
EricLew 0:80ee8f3b695e 261 */
EricLew 0:80ee8f3b695e 262
EricLew 0:80ee8f3b695e 263 /** @defgroup QSPI_InstructionMode QSPI Instruction Mode
EricLew 0:80ee8f3b695e 264 * @{
EricLew 0:80ee8f3b695e 265 */
EricLew 0:80ee8f3b695e 266 #define QSPI_INSTRUCTION_NONE ((uint32_t)0x00000000) /*!<No instruction*/
EricLew 0:80ee8f3b695e 267 #define QSPI_INSTRUCTION_1_LINE ((uint32_t)QUADSPI_CCR_IMODE_0) /*!<Instruction on a single line*/
EricLew 0:80ee8f3b695e 268 #define QSPI_INSTRUCTION_2_LINES ((uint32_t)QUADSPI_CCR_IMODE_1) /*!<Instruction on two lines*/
EricLew 0:80ee8f3b695e 269 #define QSPI_INSTRUCTION_4_LINES ((uint32_t)QUADSPI_CCR_IMODE) /*!<Instruction on four lines*/
EricLew 0:80ee8f3b695e 270 /**
EricLew 0:80ee8f3b695e 271 * @}
EricLew 0:80ee8f3b695e 272 */
EricLew 0:80ee8f3b695e 273
EricLew 0:80ee8f3b695e 274 /** @defgroup QSPI_AddressMode QSPI Address Mode
EricLew 0:80ee8f3b695e 275 * @{
EricLew 0:80ee8f3b695e 276 */
EricLew 0:80ee8f3b695e 277 #define QSPI_ADDRESS_NONE ((uint32_t)0x00000000) /*!<No address*/
EricLew 0:80ee8f3b695e 278 #define QSPI_ADDRESS_1_LINE ((uint32_t)QUADSPI_CCR_ADMODE_0) /*!<Address on a single line*/
EricLew 0:80ee8f3b695e 279 #define QSPI_ADDRESS_2_LINES ((uint32_t)QUADSPI_CCR_ADMODE_1) /*!<Address on two lines*/
EricLew 0:80ee8f3b695e 280 #define QSPI_ADDRESS_4_LINES ((uint32_t)QUADSPI_CCR_ADMODE) /*!<Address on four lines*/
EricLew 0:80ee8f3b695e 281 /**
EricLew 0:80ee8f3b695e 282 * @}
EricLew 0:80ee8f3b695e 283 */
EricLew 0:80ee8f3b695e 284
EricLew 0:80ee8f3b695e 285 /** @defgroup QSPI_AlternateBytesMode QSPI Alternate Bytes Mode
EricLew 0:80ee8f3b695e 286 * @{
EricLew 0:80ee8f3b695e 287 */
EricLew 0:80ee8f3b695e 288 #define QSPI_ALTERNATE_BYTES_NONE ((uint32_t)0x00000000) /*!<No alternate bytes*/
EricLew 0:80ee8f3b695e 289 #define QSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)QUADSPI_CCR_ABMODE_0) /*!<Alternate bytes on a single line*/
EricLew 0:80ee8f3b695e 290 #define QSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)QUADSPI_CCR_ABMODE_1) /*!<Alternate bytes on two lines*/
EricLew 0:80ee8f3b695e 291 #define QSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)QUADSPI_CCR_ABMODE) /*!<Alternate bytes on four lines*/
EricLew 0:80ee8f3b695e 292 /**
EricLew 0:80ee8f3b695e 293 * @}
EricLew 0:80ee8f3b695e 294 */
EricLew 0:80ee8f3b695e 295
EricLew 0:80ee8f3b695e 296 /** @defgroup QSPI_DataMode QSPI Data Mode
EricLew 0:80ee8f3b695e 297 * @{
EricLew 0:80ee8f3b695e 298 */
EricLew 0:80ee8f3b695e 299 #define QSPI_DATA_NONE ((uint32_t)0X00000000) /*!<No data*/
EricLew 0:80ee8f3b695e 300 #define QSPI_DATA_1_LINE ((uint32_t)QUADSPI_CCR_DMODE_0) /*!<Data on a single line*/
EricLew 0:80ee8f3b695e 301 #define QSPI_DATA_2_LINES ((uint32_t)QUADSPI_CCR_DMODE_1) /*!<Data on two lines*/
EricLew 0:80ee8f3b695e 302 #define QSPI_DATA_4_LINES ((uint32_t)QUADSPI_CCR_DMODE) /*!<Data on four lines*/
EricLew 0:80ee8f3b695e 303 /**
EricLew 0:80ee8f3b695e 304 * @}
EricLew 0:80ee8f3b695e 305 */
EricLew 0:80ee8f3b695e 306
EricLew 0:80ee8f3b695e 307 /** @defgroup QSPI_DdrMode QSPI DDR Mode
EricLew 0:80ee8f3b695e 308 * @{
EricLew 0:80ee8f3b695e 309 */
EricLew 0:80ee8f3b695e 310 #define QSPI_DDR_MODE_DISABLE ((uint32_t)0x00000000) /*!<Double data rate mode disabled*/
EricLew 0:80ee8f3b695e 311 #define QSPI_DDR_MODE_ENABLE ((uint32_t)QUADSPI_CCR_DDRM) /*!<Double data rate mode enabled*/
EricLew 0:80ee8f3b695e 312 /**
EricLew 0:80ee8f3b695e 313 * @}
EricLew 0:80ee8f3b695e 314 */
EricLew 0:80ee8f3b695e 315
EricLew 0:80ee8f3b695e 316 /** @defgroup QSPI_DdrHoldHalfCycle QSPI DDR Data Output Delay
EricLew 0:80ee8f3b695e 317 * @{
EricLew 0:80ee8f3b695e 318 */
EricLew 0:80ee8f3b695e 319 #define QSPI_DDR_HHC_ANALOG_DELAY ((uint32_t)0x00000000) /*!<Delay the data output using analog delay in DDR mode*/
EricLew 0:80ee8f3b695e 320 /**
EricLew 0:80ee8f3b695e 321 * @}
EricLew 0:80ee8f3b695e 322 */
EricLew 0:80ee8f3b695e 323
EricLew 0:80ee8f3b695e 324 /** @defgroup QSPI_SIOOMode QSPI Send Instruction Mode
EricLew 0:80ee8f3b695e 325 * @{
EricLew 0:80ee8f3b695e 326 */
EricLew 0:80ee8f3b695e 327 #define QSPI_SIOO_INST_EVERY_CMD ((uint32_t)0x00000000) /*!<Send instruction on every transaction*/
EricLew 0:80ee8f3b695e 328 #define QSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)QUADSPI_CCR_SIOO) /*!<Send instruction only for the first command*/
EricLew 0:80ee8f3b695e 329 /**
EricLew 0:80ee8f3b695e 330 * @}
EricLew 0:80ee8f3b695e 331 */
EricLew 0:80ee8f3b695e 332
EricLew 0:80ee8f3b695e 333 /** @defgroup QSPI_MatchMode QSPI Match Mode
EricLew 0:80ee8f3b695e 334 * @{
EricLew 0:80ee8f3b695e 335 */
EricLew 0:80ee8f3b695e 336 #define QSPI_MATCH_MODE_AND ((uint32_t)0x00000000) /*!<AND match mode between unmasked bits*/
EricLew 0:80ee8f3b695e 337 #define QSPI_MATCH_MODE_OR ((uint32_t)QUADSPI_CR_PMM) /*!<OR match mode between unmasked bits*/
EricLew 0:80ee8f3b695e 338 /**
EricLew 0:80ee8f3b695e 339 * @}
EricLew 0:80ee8f3b695e 340 */
EricLew 0:80ee8f3b695e 341
EricLew 0:80ee8f3b695e 342 /** @defgroup QSPI_AutomaticStop QSPI Automatic Stop
EricLew 0:80ee8f3b695e 343 * @{
EricLew 0:80ee8f3b695e 344 */
EricLew 0:80ee8f3b695e 345 #define QSPI_AUTOMATIC_STOP_DISABLE ((uint32_t)0x00000000) /*!<AutoPolling stops only with abort or QSPI disabling*/
EricLew 0:80ee8f3b695e 346 #define QSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)QUADSPI_CR_APMS) /*!<AutoPolling stops as soon as there is a match*/
EricLew 0:80ee8f3b695e 347 /**
EricLew 0:80ee8f3b695e 348 * @}
EricLew 0:80ee8f3b695e 349 */
EricLew 0:80ee8f3b695e 350
EricLew 0:80ee8f3b695e 351 /** @defgroup QSPI_TimeOutActivation QSPI Timeout Activation
EricLew 0:80ee8f3b695e 352 * @{
EricLew 0:80ee8f3b695e 353 */
EricLew 0:80ee8f3b695e 354 #define QSPI_TIMEOUT_COUNTER_DISABLE ((uint32_t)0x00000000) /*!<Timeout counter disabled, nCS remains active*/
EricLew 0:80ee8f3b695e 355 #define QSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)QUADSPI_CR_TCEN) /*!<Timeout counter enabled, nCS released when timeout expires*/
EricLew 0:80ee8f3b695e 356 /**
EricLew 0:80ee8f3b695e 357 * @}
EricLew 0:80ee8f3b695e 358 */
EricLew 0:80ee8f3b695e 359
EricLew 0:80ee8f3b695e 360 /** @defgroup QSPI_Flags QSPI Flags
EricLew 0:80ee8f3b695e 361 * @{
EricLew 0:80ee8f3b695e 362 */
EricLew 0:80ee8f3b695e 363 #define QSPI_FLAG_BUSY QUADSPI_SR_BUSY /*!<Busy flag: operation is ongoing*/
EricLew 0:80ee8f3b695e 364 #define QSPI_FLAG_TO QUADSPI_SR_TOF /*!<Timeout flag: timeout occurs in memory-mapped mode*/
EricLew 0:80ee8f3b695e 365 #define QSPI_FLAG_SM QUADSPI_SR_SMF /*!<Status match flag: received data matches in autopolling mode*/
EricLew 0:80ee8f3b695e 366 #define QSPI_FLAG_FT QUADSPI_SR_FTF /*!<Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete*/
EricLew 0:80ee8f3b695e 367 #define QSPI_FLAG_TC QUADSPI_SR_TCF /*!<Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted*/
EricLew 0:80ee8f3b695e 368 #define QSPI_FLAG_TE QUADSPI_SR_TEF /*!<Transfer error flag: invalid address is being accessed*/
EricLew 0:80ee8f3b695e 369 /**
EricLew 0:80ee8f3b695e 370 * @}
EricLew 0:80ee8f3b695e 371 */
EricLew 0:80ee8f3b695e 372
EricLew 0:80ee8f3b695e 373 /** @defgroup QSPI_Interrupts QSPI Interrupts
EricLew 0:80ee8f3b695e 374 * @{
EricLew 0:80ee8f3b695e 375 */
EricLew 0:80ee8f3b695e 376 #define QSPI_IT_TO QUADSPI_CR_TOIE /*!<Interrupt on the timeout flag*/
EricLew 0:80ee8f3b695e 377 #define QSPI_IT_SM QUADSPI_CR_SMIE /*!<Interrupt on the status match flag*/
EricLew 0:80ee8f3b695e 378 #define QSPI_IT_FT QUADSPI_CR_FTIE /*!<Interrupt on the fifo threshold flag*/
EricLew 0:80ee8f3b695e 379 #define QSPI_IT_TC QUADSPI_CR_TCIE /*!<Interrupt on the transfer complete flag*/
EricLew 0:80ee8f3b695e 380 #define QSPI_IT_TE QUADSPI_CR_TEIE /*!<Interrupt on the transfer error flag*/
EricLew 0:80ee8f3b695e 381 /**
EricLew 0:80ee8f3b695e 382 * @}
EricLew 0:80ee8f3b695e 383 */
EricLew 0:80ee8f3b695e 384
EricLew 0:80ee8f3b695e 385 /** @defgroup QSPI_Timeout_definition QSPI Timeout definition
EricLew 0:80ee8f3b695e 386 * @brief QSPI Timeout definition
EricLew 0:80ee8f3b695e 387 * @{
EricLew 0:80ee8f3b695e 388 */
EricLew 0:80ee8f3b695e 389 #define HAL_QPSI_TIMEOUT_DEFAULT_VALUE ((uint32_t)5000)/* 5 s */
EricLew 0:80ee8f3b695e 390 /**
EricLew 0:80ee8f3b695e 391 * @}
EricLew 0:80ee8f3b695e 392 */
EricLew 0:80ee8f3b695e 393
EricLew 0:80ee8f3b695e 394 /**
EricLew 0:80ee8f3b695e 395 * @}
EricLew 0:80ee8f3b695e 396 */
EricLew 0:80ee8f3b695e 397
EricLew 0:80ee8f3b695e 398 /* Exported macros -----------------------------------------------------------*/
EricLew 0:80ee8f3b695e 399 /** @defgroup QSPI_Exported_Macros QSPI Exported Macros
EricLew 0:80ee8f3b695e 400 * @{
EricLew 0:80ee8f3b695e 401 */
EricLew 0:80ee8f3b695e 402 /** @brief Reset QSPI handle state.
EricLew 0:80ee8f3b695e 403 * @param __HANDLE__: QSPI handle.
EricLew 0:80ee8f3b695e 404 * @retval None
EricLew 0:80ee8f3b695e 405 */
EricLew 0:80ee8f3b695e 406 #define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_QSPI_STATE_RESET)
EricLew 0:80ee8f3b695e 407
EricLew 0:80ee8f3b695e 408 /** @brief Enable the QSPI peripheral.
EricLew 0:80ee8f3b695e 409 * @param __HANDLE__: specifies the QSPI Handle.
EricLew 0:80ee8f3b695e 410 * @retval None
EricLew 0:80ee8f3b695e 411 */
EricLew 0:80ee8f3b695e 412 #define __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
EricLew 0:80ee8f3b695e 413
EricLew 0:80ee8f3b695e 414 /** @brief Disable the QSPI peripheral.
EricLew 0:80ee8f3b695e 415 * @param __HANDLE__: specifies the QSPI Handle.
EricLew 0:80ee8f3b695e 416 * @retval None
EricLew 0:80ee8f3b695e 417 */
EricLew 0:80ee8f3b695e 418 #define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
EricLew 0:80ee8f3b695e 419
EricLew 0:80ee8f3b695e 420 /** @brief Enable the specified QSPI interrupt.
EricLew 0:80ee8f3b695e 421 * @param __HANDLE__: specifies the QSPI Handle.
EricLew 0:80ee8f3b695e 422 * @param __INTERRUPT__: specifies the QSPI interrupt source to enable.
EricLew 0:80ee8f3b695e 423 * This parameter can be one of the following values:
EricLew 0:80ee8f3b695e 424 * @arg QSPI_IT_TO: QSPI Timeout interrupt
EricLew 0:80ee8f3b695e 425 * @arg QSPI_IT_SM: QSPI Status match interrupt
EricLew 0:80ee8f3b695e 426 * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
EricLew 0:80ee8f3b695e 427 * @arg QSPI_IT_TC: QSPI Transfer complete interrupt
EricLew 0:80ee8f3b695e 428 * @arg QSPI_IT_TE: QSPI Transfer error interrupt
EricLew 0:80ee8f3b695e 429 * @retval None
EricLew 0:80ee8f3b695e 430 */
EricLew 0:80ee8f3b695e 431 #define __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
EricLew 0:80ee8f3b695e 432
EricLew 0:80ee8f3b695e 433
EricLew 0:80ee8f3b695e 434 /** @brief Disable the specified QSPI interrupt.
EricLew 0:80ee8f3b695e 435 * @param __HANDLE__: specifies the QSPI Handle.
EricLew 0:80ee8f3b695e 436 * @param __INTERRUPT__: specifies the QSPI interrupt source to disable.
EricLew 0:80ee8f3b695e 437 * This parameter can be one of the following values:
EricLew 0:80ee8f3b695e 438 * @arg QSPI_IT_TO: QSPI Timeout interrupt
EricLew 0:80ee8f3b695e 439 * @arg QSPI_IT_SM: QSPI Status match interrupt
EricLew 0:80ee8f3b695e 440 * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
EricLew 0:80ee8f3b695e 441 * @arg QSPI_IT_TC: QSPI Transfer complete interrupt
EricLew 0:80ee8f3b695e 442 * @arg QSPI_IT_TE: QSPI Transfer error interrupt
EricLew 0:80ee8f3b695e 443 * @retval None
EricLew 0:80ee8f3b695e 444 */
EricLew 0:80ee8f3b695e 445 #define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
EricLew 0:80ee8f3b695e 446
EricLew 0:80ee8f3b695e 447 /** @brief Check whether the specified QSPI interrupt source is enabled or not.
EricLew 0:80ee8f3b695e 448 * @param __HANDLE__: specifies the QSPI Handle.
EricLew 0:80ee8f3b695e 449 * @param __INTERRUPT__: specifies the QSPI interrupt source to check.
EricLew 0:80ee8f3b695e 450 * This parameter can be one of the following values:
EricLew 0:80ee8f3b695e 451 * @arg QSPI_IT_TO: QSPI Timeout interrupt
EricLew 0:80ee8f3b695e 452 * @arg QSPI_IT_SM: QSPI Status match interrupt
EricLew 0:80ee8f3b695e 453 * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
EricLew 0:80ee8f3b695e 454 * @arg QSPI_IT_TC: QSPI Transfer complete interrupt
EricLew 0:80ee8f3b695e 455 * @arg QSPI_IT_TE: QSPI Transfer error interrupt
EricLew 0:80ee8f3b695e 456 * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
EricLew 0:80ee8f3b695e 457 */
EricLew 0:80ee8f3b695e 458 #define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__))
EricLew 0:80ee8f3b695e 459
EricLew 0:80ee8f3b695e 460 /**
EricLew 0:80ee8f3b695e 461 * @brief Check whether the selected QSPI flag is set or not.
EricLew 0:80ee8f3b695e 462 * @param __HANDLE__: specifies the QSPI Handle.
EricLew 0:80ee8f3b695e 463 * @param __FLAG__: specifies the QSPI flag to check.
EricLew 0:80ee8f3b695e 464 * This parameter can be one of the following values:
EricLew 0:80ee8f3b695e 465 * @arg QSPI_FLAG_BUSY: QSPI Busy flag
EricLew 0:80ee8f3b695e 466 * @arg QSPI_FLAG_TO: QSPI Timeout flag
EricLew 0:80ee8f3b695e 467 * @arg QSPI_FLAG_SM: QSPI Status match flag
EricLew 0:80ee8f3b695e 468 * @arg QSPI_FLAG_FT: QSPI FIFO threshold flag
EricLew 0:80ee8f3b695e 469 * @arg QSPI_FLAG_TC: QSPI Transfer complete flag
EricLew 0:80ee8f3b695e 470 * @arg QSPI_FLAG_TE: QSPI Transfer error flag
EricLew 0:80ee8f3b695e 471 * @retval None
EricLew 0:80ee8f3b695e 472 */
EricLew 0:80ee8f3b695e 473 #define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) (READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0)
EricLew 0:80ee8f3b695e 474
EricLew 0:80ee8f3b695e 475 /** @brief Clears the specified QSPI's flag status.
EricLew 0:80ee8f3b695e 476 * @param __HANDLE__: specifies the QSPI Handle.
EricLew 0:80ee8f3b695e 477 * @param __FLAG__: specifies the QSPI clear register flag that needs to be set
EricLew 0:80ee8f3b695e 478 * This parameter can be one of the following values:
EricLew 0:80ee8f3b695e 479 * @arg QSPI_FLAG_TO: QSPI Timeout flag
EricLew 0:80ee8f3b695e 480 * @arg QSPI_FLAG_SM: QSPI Status match flag
EricLew 0:80ee8f3b695e 481 * @arg QSPI_FLAG_TC: QSPI Transfer complete flag
EricLew 0:80ee8f3b695e 482 * @arg QSPI_FLAG_TE: QSPI Transfer error flag
EricLew 0:80ee8f3b695e 483 * @retval None
EricLew 0:80ee8f3b695e 484 */
EricLew 0:80ee8f3b695e 485 #define __HAL_QSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__))
EricLew 0:80ee8f3b695e 486 /**
EricLew 0:80ee8f3b695e 487 * @}
EricLew 0:80ee8f3b695e 488 */
EricLew 0:80ee8f3b695e 489
EricLew 0:80ee8f3b695e 490 /* Exported functions --------------------------------------------------------*/
EricLew 0:80ee8f3b695e 491 /** @addtogroup QSPI_Exported_Functions
EricLew 0:80ee8f3b695e 492 * @{
EricLew 0:80ee8f3b695e 493 */
EricLew 0:80ee8f3b695e 494 /* Initialization/de-initialization functions ********************************/
EricLew 0:80ee8f3b695e 495 HAL_StatusTypeDef HAL_QSPI_Init (QSPI_HandleTypeDef *hqspi);
EricLew 0:80ee8f3b695e 496 HAL_StatusTypeDef HAL_QSPI_DeInit (QSPI_HandleTypeDef *hqspi);
EricLew 0:80ee8f3b695e 497 void HAL_QSPI_MspInit (QSPI_HandleTypeDef *hqspi);
EricLew 0:80ee8f3b695e 498 void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi);
EricLew 0:80ee8f3b695e 499
EricLew 0:80ee8f3b695e 500 /* IO operation functions *****************************************************/
EricLew 0:80ee8f3b695e 501 /* QSPI IRQ handler method */
EricLew 0:80ee8f3b695e 502 void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi);
EricLew 0:80ee8f3b695e 503
EricLew 0:80ee8f3b695e 504 /* QSPI indirect mode */
EricLew 0:80ee8f3b695e 505 HAL_StatusTypeDef HAL_QSPI_Command (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout);
EricLew 0:80ee8f3b695e 506 HAL_StatusTypeDef HAL_QSPI_Transmit (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);
EricLew 0:80ee8f3b695e 507 HAL_StatusTypeDef HAL_QSPI_Receive (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);
EricLew 0:80ee8f3b695e 508 HAL_StatusTypeDef HAL_QSPI_Command_IT (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd);
EricLew 0:80ee8f3b695e 509 HAL_StatusTypeDef HAL_QSPI_Transmit_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
EricLew 0:80ee8f3b695e 510 HAL_StatusTypeDef HAL_QSPI_Receive_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
EricLew 0:80ee8f3b695e 511 HAL_StatusTypeDef HAL_QSPI_Transmit_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
EricLew 0:80ee8f3b695e 512 HAL_StatusTypeDef HAL_QSPI_Receive_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
EricLew 0:80ee8f3b695e 513
EricLew 0:80ee8f3b695e 514 /* QSPI status flag polling mode */
EricLew 0:80ee8f3b695e 515 HAL_StatusTypeDef HAL_QSPI_AutoPolling (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout);
EricLew 0:80ee8f3b695e 516 HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg);
EricLew 0:80ee8f3b695e 517
EricLew 0:80ee8f3b695e 518 /* QSPI memory-mapped mode */
EricLew 0:80ee8f3b695e 519 HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg);
EricLew 0:80ee8f3b695e 520
EricLew 0:80ee8f3b695e 521 /* Callback functions in non-blocking modes ***********************************/
EricLew 0:80ee8f3b695e 522 void HAL_QSPI_ErrorCallback (QSPI_HandleTypeDef *hqspi);
EricLew 0:80ee8f3b695e 523 void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi);
EricLew 0:80ee8f3b695e 524
EricLew 0:80ee8f3b695e 525 /* QSPI indirect mode */
EricLew 0:80ee8f3b695e 526 void HAL_QSPI_CmdCpltCallback (QSPI_HandleTypeDef *hqspi);
EricLew 0:80ee8f3b695e 527 void HAL_QSPI_RxCpltCallback (QSPI_HandleTypeDef *hqspi);
EricLew 0:80ee8f3b695e 528 void HAL_QSPI_TxCpltCallback (QSPI_HandleTypeDef *hqspi);
EricLew 0:80ee8f3b695e 529 void HAL_QSPI_RxHalfCpltCallback (QSPI_HandleTypeDef *hqspi);
EricLew 0:80ee8f3b695e 530 void HAL_QSPI_TxHalfCpltCallback (QSPI_HandleTypeDef *hqspi);
EricLew 0:80ee8f3b695e 531
EricLew 0:80ee8f3b695e 532 /* QSPI status flag polling mode */
EricLew 0:80ee8f3b695e 533 void HAL_QSPI_StatusMatchCallback (QSPI_HandleTypeDef *hqspi);
EricLew 0:80ee8f3b695e 534
EricLew 0:80ee8f3b695e 535 /* QSPI memory-mapped mode */
EricLew 0:80ee8f3b695e 536 void HAL_QSPI_TimeOutCallback (QSPI_HandleTypeDef *hqspi);
EricLew 0:80ee8f3b695e 537
EricLew 0:80ee8f3b695e 538 /* Peripheral Control and State functions ************************************/
EricLew 0:80ee8f3b695e 539 HAL_QSPI_StateTypeDef HAL_QSPI_GetState (QSPI_HandleTypeDef *hqspi);
EricLew 0:80ee8f3b695e 540 uint32_t HAL_QSPI_GetError (QSPI_HandleTypeDef *hqspi);
EricLew 0:80ee8f3b695e 541 HAL_StatusTypeDef HAL_QSPI_Abort (QSPI_HandleTypeDef *hqspi);
EricLew 0:80ee8f3b695e 542 void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout);
EricLew 0:80ee8f3b695e 543 /**
EricLew 0:80ee8f3b695e 544 * @}
EricLew 0:80ee8f3b695e 545 */
EricLew 0:80ee8f3b695e 546 /* End of exported functions -------------------------------------------------*/
EricLew 0:80ee8f3b695e 547
EricLew 0:80ee8f3b695e 548 /* Private macros ------------------------------------------------------------*/
EricLew 0:80ee8f3b695e 549 /** @defgroup QSPI_Private_Macros QSPI Private Macros
EricLew 0:80ee8f3b695e 550 * @{
EricLew 0:80ee8f3b695e 551 */
EricLew 0:80ee8f3b695e 552 #define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFF)
EricLew 0:80ee8f3b695e 553
EricLew 0:80ee8f3b695e 554 #define IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0) && ((THR) <= 16))
EricLew 0:80ee8f3b695e 555
EricLew 0:80ee8f3b695e 556 #define IS_QSPI_SSHIFT(SSHIFT) (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \
EricLew 0:80ee8f3b695e 557 ((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE))
EricLew 0:80ee8f3b695e 558
EricLew 0:80ee8f3b695e 559 #define IS_QSPI_FLASH_SIZE(FSIZE) (((FSIZE) <= 31))
EricLew 0:80ee8f3b695e 560
EricLew 0:80ee8f3b695e 561 #define IS_QSPI_CS_HIGH_TIME(CSHTIME) (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \
EricLew 0:80ee8f3b695e 562 ((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \
EricLew 0:80ee8f3b695e 563 ((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) || \
EricLew 0:80ee8f3b695e 564 ((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) || \
EricLew 0:80ee8f3b695e 565 ((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) || \
EricLew 0:80ee8f3b695e 566 ((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) || \
EricLew 0:80ee8f3b695e 567 ((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) || \
EricLew 0:80ee8f3b695e 568 ((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE))
EricLew 0:80ee8f3b695e 569
EricLew 0:80ee8f3b695e 570 #define IS_QSPI_CLOCK_MODE(CLKMODE) (((CLKMODE) == QSPI_CLOCK_MODE_0) || \
EricLew 0:80ee8f3b695e 571 ((CLKMODE) == QSPI_CLOCK_MODE_3))
EricLew 0:80ee8f3b695e 572
EricLew 0:80ee8f3b695e 573 #define IS_QSPI_INSTRUCTION(INSTRUCTION) ((INSTRUCTION) <= 0xFF)
EricLew 0:80ee8f3b695e 574
EricLew 0:80ee8f3b695e 575 #define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE) (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS) || \
EricLew 0:80ee8f3b695e 576 ((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \
EricLew 0:80ee8f3b695e 577 ((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) || \
EricLew 0:80ee8f3b695e 578 ((ADDR_SIZE) == QSPI_ADDRESS_32_BITS))
EricLew 0:80ee8f3b695e 579
EricLew 0:80ee8f3b695e 580 #define IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE) (((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS) || \
EricLew 0:80ee8f3b695e 581 ((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) || \
EricLew 0:80ee8f3b695e 582 ((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \
EricLew 0:80ee8f3b695e 583 ((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS))
EricLew 0:80ee8f3b695e 584
EricLew 0:80ee8f3b695e 585 #define IS_QSPI_DUMMY_CYCLES(DCY) ((DCY) <= 31)
EricLew 0:80ee8f3b695e 586
EricLew 0:80ee8f3b695e 587 #define IS_QSPI_INSTRUCTION_MODE(MODE) (((MODE) == QSPI_INSTRUCTION_NONE) || \
EricLew 0:80ee8f3b695e 588 ((MODE) == QSPI_INSTRUCTION_1_LINE) || \
EricLew 0:80ee8f3b695e 589 ((MODE) == QSPI_INSTRUCTION_2_LINES) || \
EricLew 0:80ee8f3b695e 590 ((MODE) == QSPI_INSTRUCTION_4_LINES))
EricLew 0:80ee8f3b695e 591
EricLew 0:80ee8f3b695e 592 #define IS_QSPI_ADDRESS_MODE(MODE) (((MODE) == QSPI_ADDRESS_NONE) || \
EricLew 0:80ee8f3b695e 593 ((MODE) == QSPI_ADDRESS_1_LINE) || \
EricLew 0:80ee8f3b695e 594 ((MODE) == QSPI_ADDRESS_2_LINES) || \
EricLew 0:80ee8f3b695e 595 ((MODE) == QSPI_ADDRESS_4_LINES))
EricLew 0:80ee8f3b695e 596
EricLew 0:80ee8f3b695e 597 #define IS_QSPI_ALTERNATE_BYTES_MODE(MODE) (((MODE) == QSPI_ALTERNATE_BYTES_NONE) || \
EricLew 0:80ee8f3b695e 598 ((MODE) == QSPI_ALTERNATE_BYTES_1_LINE) || \
EricLew 0:80ee8f3b695e 599 ((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) || \
EricLew 0:80ee8f3b695e 600 ((MODE) == QSPI_ALTERNATE_BYTES_4_LINES))
EricLew 0:80ee8f3b695e 601
EricLew 0:80ee8f3b695e 602 #define IS_QSPI_DATA_MODE(MODE) (((MODE) == QSPI_DATA_NONE) || \
EricLew 0:80ee8f3b695e 603 ((MODE) == QSPI_DATA_1_LINE) || \
EricLew 0:80ee8f3b695e 604 ((MODE) == QSPI_DATA_2_LINES) || \
EricLew 0:80ee8f3b695e 605 ((MODE) == QSPI_DATA_4_LINES))
EricLew 0:80ee8f3b695e 606
EricLew 0:80ee8f3b695e 607 #define IS_QSPI_DDR_MODE(DDR_MODE) (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \
EricLew 0:80ee8f3b695e 608 ((DDR_MODE) == QSPI_DDR_MODE_ENABLE))
EricLew 0:80ee8f3b695e 609
EricLew 0:80ee8f3b695e 610 #define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY))
EricLew 0:80ee8f3b695e 611
EricLew 0:80ee8f3b695e 612 #define IS_QSPI_SIOO_MODE(SIOO_MODE) (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \
EricLew 0:80ee8f3b695e 613 ((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD))
EricLew 0:80ee8f3b695e 614
EricLew 0:80ee8f3b695e 615 #define IS_QSPI_INTERVAL(INTERVAL) ((INTERVAL) <= QUADSPI_PIR_INTERVAL)
EricLew 0:80ee8f3b695e 616
EricLew 0:80ee8f3b695e 617 #define IS_QSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1) && ((SIZE) <= 4))
EricLew 0:80ee8f3b695e 618
EricLew 0:80ee8f3b695e 619 #define IS_QSPI_MATCH_MODE(MODE) (((MODE) == QSPI_MATCH_MODE_AND) || \
EricLew 0:80ee8f3b695e 620 ((MODE) == QSPI_MATCH_MODE_OR))
EricLew 0:80ee8f3b695e 621
EricLew 0:80ee8f3b695e 622 #define IS_QSPI_AUTOMATIC_STOP(APMS) (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \
EricLew 0:80ee8f3b695e 623 ((APMS) == QSPI_AUTOMATIC_STOP_ENABLE))
EricLew 0:80ee8f3b695e 624
EricLew 0:80ee8f3b695e 625 #define IS_QSPI_TIMEOUT_ACTIVATION(TCEN) (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \
EricLew 0:80ee8f3b695e 626 ((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE))
EricLew 0:80ee8f3b695e 627
EricLew 0:80ee8f3b695e 628 #define IS_QSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFF)
EricLew 0:80ee8f3b695e 629 /**
EricLew 0:80ee8f3b695e 630 * @}
EricLew 0:80ee8f3b695e 631 */
EricLew 0:80ee8f3b695e 632 /* End of private macros -----------------------------------------------------*/
EricLew 0:80ee8f3b695e 633
EricLew 0:80ee8f3b695e 634 /**
EricLew 0:80ee8f3b695e 635 * @}
EricLew 0:80ee8f3b695e 636 */
EricLew 0:80ee8f3b695e 637
EricLew 0:80ee8f3b695e 638 /**
EricLew 0:80ee8f3b695e 639 * @}
EricLew 0:80ee8f3b695e 640 */
EricLew 0:80ee8f3b695e 641
EricLew 0:80ee8f3b695e 642 #ifdef __cplusplus
EricLew 0:80ee8f3b695e 643 }
EricLew 0:80ee8f3b695e 644 #endif
EricLew 0:80ee8f3b695e 645
EricLew 0:80ee8f3b695e 646 #endif /* __STM32L4xx_HAL_QSPI_H */
EricLew 0:80ee8f3b695e 647
EricLew 0:80ee8f3b695e 648 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
EricLew 0:80ee8f3b695e 649