Callum Ellor / PulseWidthCapture

Library to Capture the +ve and -ve Pulsewidth of a signal

Dependents:   PulseWidthCapture_Program

PulseWidthCapture.h@2:857c3c8e7a2f, 2014-12-11 (annotated)

Committer:
Ellor1
Date:
Thu Dec 11 08:59:09 2014 +0000
Revision:
2:857c3c8e7a2f
Parent:
1:6bb38ae2e503 
Pulse Width Capture;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Ellor1 0:7076676dd640 1 /* mbed Library - PulseWidthCapture
Ellor1 0:7076676dd640 2 * Copyright (c) 2014
Ellor1 0:7076676dd640 3 * released under MIT license http://mbed.org/licence/mit
Ellor1 0:7076676dd640 4 */
Ellor1 0:7076676dd640 5
Ellor1 0:7076676dd640 6 /***********************************************************************//**
Ellor1 0:7076676dd640 7 * @file PulseWidthCapture.h
Ellor1 0:7076676dd640 8 * @brief Header file for the PulseWidthCapture library.
Ellor1 0:7076676dd640 9 * @version 0.0
Ellor1 0:7076676dd640 10 * @date 03 Dec 2014
Ellor1 2:857c3c8e7a2f 11 * @author Callum Ellor
Ellor1 0:7076676dd640 12 **************************************************************************/
Ellor1 0:7076676dd640 13 /***************************************************************************
Ellor1 0:7076676dd640 14 * Revision Date Comments
Ellor1 0:7076676dd640 15 *---------- -------- -----------------------------------------------
Ellor1 0:7076676dd640 16 *
Ellor1 0:7076676dd640 17 * 0.0 03/12/14 Initial creation
Ellor1 0:7076676dd640 18 ***************************************************************************/
Ellor1 0:7076676dd640 19
Ellor1 0:7076676dd640 20 #ifndef CAPTURET0_H
Ellor1 0:7076676dd640 21 #define CAPTURET0_H
Ellor1 0:7076676dd640 22
Ellor1 0:7076676dd640 23 /* Includes ------------------------------------------------------------------- */
Ellor1 0:7076676dd640 24 #include "mbed.h"
Ellor1 0:7076676dd640 25
Ellor1 0:7076676dd640 26 /* Public Types --------------------------------------------------------------- */
Ellor1 0:7076676dd640 27
Ellor1 0:7076676dd640 28
Ellor1 0:7076676dd640 29 /* Public Functions ----------------------------------------------------------- */
Ellor1 2:857c3c8e7a2f 30 /** Capture_Public_Functions Capture Public Functions
Ellor1 0:7076676dd640 31 */
Ellor1 0:7076676dd640 32 class Capture {
Ellor1 0:7076676dd640 33 public:
Ellor1 0:7076676dd640 34
Ellor1 2:857c3c8e7a2f 35 /* Create a Capture object and configure it */
Ellor1 0:7076676dd640 36 Capture(void);
Ellor1 0:7076676dd640 37
Ellor1 2:857c3c8e7a2f 38 /* Start capturing data. */
Ellor1 0:7076676dd640 39 void Start_1(void);
Ellor1 0:7076676dd640 40 void Start_2(void);
Ellor1 0:7076676dd640 41
Ellor1 2:857c3c8e7a2f 42 /* Wait function */
Ellor1 0:7076676dd640 43 void Wait(void);
Ellor1 0:7076676dd640 44
Ellor1 2:857c3c8e7a2f 45 /* Debug function */
Ellor1 0:7076676dd640 46 unsigned int Debug(void);
Ellor1 0:7076676dd640 47
Ellor1 0:7076676dd640 48 /* Public Macros -------------------------------------------------------------- */
Ellor1 0:7076676dd640 49
Ellor1 0:7076676dd640 50 private:
Ellor1 2:857c3c8e7a2f 51 static void _Fall_ISR(void);
Ellor1 2:857c3c8e7a2f 52 static void _Rise_ISR(void);
Ellor1 2:857c3c8e7a2f 53 static void _Wait_ISR(void);
Ellor1 2:857c3c8e7a2f 54 void Fall_ISR(void);
Ellor1 2:857c3c8e7a2f 55 void Rise_ISR(void);
Ellor1 2:857c3c8e7a2f 56 void Wait_ISR(void);
Ellor1 0:7076676dd640 57 static Capture *instance;
Ellor1 2:857c3c8e7a2f 58 const char * freq_unit;
Ellor1 2:857c3c8e7a2f 59 const char * rise_sec_unit;
Ellor1 2:857c3c8e7a2f 60 const char * fall_sec_unit;
Ellor1 2:857c3c8e7a2f 61 const char * per_sec_unit;
Ellor1 2:857c3c8e7a2f 62 float rise, rise1, fall, fall1, period, period1, freq, freq1, ADCdata;
Ellor1 0:7076676dd640 63 unsigned int debug;
Ellor1 0:7076676dd640 64
Ellor1 0:7076676dd640 65 /* Private Macros ------------------------------------------------------------- */
Ellor1 0:7076676dd640 66 /* --------------------- BIT DEFINITIONS -------------------------------------- */
Ellor1 0:7076676dd640 67 /* Timer Capture Register Definitions --------------------- */
Ellor1 0:7076676dd640 68
Ellor1 0:7076676dd640 69 /*********************************************************************//**
Ellor1 0:7076676dd640 70 * Macro defines for CT32B0->IR Interrupt tegister
Ellor1 0:7076676dd640 71 **********************************************************************/
Ellor1 2:857c3c8e7a2f 72 #define CT32B0_IR_CR0INT ((uint32_t)(1<<4)) /**< Interrupt flag for capture channel 0 */
Ellor1 0:7076676dd640 73 #define CT32B0_IR_CR1INT ((uint32_t)(1<<6)) /**< Interrupt flag for capture channel 1 */
Ellor1 0:7076676dd640 74
Ellor1 0:7076676dd640 75 /*********************************************************************//**
Ellor1 0:7076676dd640 76 * Macro defines for CT32B1->IR Interrupt tegister
Ellor1 0:7076676dd640 77 **********************************************************************/
Ellor1 2:857c3c8e7a2f 78 #define CT32B1_IR_CR0INT ((uint32_t)(1<<4)) /**< Interrupt flag for capture channel 0 */
Ellor1 2:857c3c8e7a2f 79 #define CT32B1_IR_CR1INT ((uint32_t)(1<<5)) /**< Interrupt flag for capture channel 1 */
Ellor1 0:7076676dd640 80
Ellor1 0:7076676dd640 81 /*********************************************************************//**
Ellor1 2:857c3c8e7a2f 82 * Macro defines for CT16B0->IR Interrupt tegister
Ellor1 2:857c3c8e7a2f 83 **********************************************************************/
Ellor1 2:857c3c8e7a2f 84 #define CT16B0_IR_MR0INT ((uint32_t)(1<<0)) /**< Interrupt flag for Match channel 0 */
Ellor1 2:857c3c8e7a2f 85
Ellor1 2:857c3c8e7a2f 86 /*********************************************************************//**
Ellor1 2:857c3c8e7a2f 87 * Macro defines for IOCON->PIO1_29 register bits LPC11U24 page 125
Ellor1 0:7076676dd640 88 **********************************************************************/
Ellor1 0:7076676dd640 89 #define P1_29_PIN_PULL_UP 2UL
Ellor1 0:7076676dd640 90 #define P1_29_PIN_REPEATER 3UL
Ellor1 0:7076676dd640 91 #define P1_29_PIN_NORESISTOR 0UL
Ellor1 0:7076676dd640 92 #define P1_29_PIN_PULL_DOWN 1UL
Ellor1 0:7076676dd640 93
Ellor1 2:857c3c8e7a2f 94 /* FUNC bits */ // define what fucntion the pin should be set up in
Ellor1 0:7076676dd640 95 #define PORT_PIO1_29 0UL
Ellor1 0:7076676dd640 96 #define SCKO 1UL
Ellor1 0:7076676dd640 97 #define CT32B0_CAP1 2UL
Ellor1 0:7076676dd640 98
Ellor1 0:7076676dd640 99 /* MODE bits */
Ellor1 0:7076676dd640 100 #define P1_29_CAP_PULLUP ((uint32_t)(PIN_PULL_UP<<3)) // Pull up on the CT32B0_CAP1 input pin
Ellor1 0:7076676dd640 101
Ellor1 0:7076676dd640 102 /*********************************************************************//**
Ellor1 2:857c3c8e7a2f 103 * Macro defines for IOCON->PIO0_12 register bits LPC11U24 page 94
Ellor1 0:7076676dd640 104 **********************************************************************/
Ellor1 0:7076676dd640 105 #define P0_12_PIN_PULL_UP 2UL
Ellor1 0:7076676dd640 106 #define P0_12_PIN_REPEATER 3UL
Ellor1 0:7076676dd640 107 #define P0_12_PIN_NORESISTOR 0UL
Ellor1 0:7076676dd640 108 #define P0_12_PIN_PULL_DOWN 1UL
Ellor1 0:7076676dd640 109
Ellor1 0:7076676dd640 110 /* FUNC bits */
Ellor1 2:857c3c8e7a2f 111 #define PIO0_12 1UL // define what fucntion the pin should be set up in
Ellor1 0:7076676dd640 112 #define ADL 2UL
Ellor1 2:857c3c8e7a2f 113 #define CT32B1_CAP0 3UL
Ellor1 2:857c3c8e7a2f 114
Ellor1 2:857c3c8e7a2f 115 #define ADMODE ((uint32_t)(1<<7)) // Set to digital function mode to allow capture input on this pin
Ellor1 0:7076676dd640 116 #define FILTR ((uint32_t)(1<<8))
Ellor1 0:7076676dd640 117
Ellor1 0:7076676dd640 118 /* MODE bits */
Ellor1 0:7076676dd640 119 #define P0_12_CAP_PULLUP ((uint32_t)(PIN_PULL_UP<<3)) // Pull up on the CT32B0_CAP1 input pin
Ellor1 0:7076676dd640 120
Ellor1 0:7076676dd640 121 /*********************************************************************//**
Ellor1 2:857c3c8e7a2f 122 * Macro defines for SYSCON->SYSAHBCLKDIV register bits LPC11U24 page 30
Ellor1 0:7076676dd640 123 **********************************************************************/
Ellor1 0:7076676dd640 124 #define CT32B0_CLK_ENABLE ((uint32_t)(1<<9)) /**< CT32B0 clock enable */
Ellor1 0:7076676dd640 125
Ellor1 0:7076676dd640 126 #define CT32B1_CLK_ENABLE ((uint32_t)(1<<10))
Ellor1 0:7076676dd640 127
Ellor1 0:7076676dd640 128 #define CT16B0_CLK_ENABLE ((uint32_t)(1<<7))
Ellor1 0:7076676dd640 129 /*********************************************************************//**
Ellor1 2:857c3c8e7a2f 130 * Macro defines for CT32B0->TCR register bits LPC11U24 page 353
Ellor1 0:7076676dd640 131 **********************************************************************/
Ellor1 0:7076676dd640 132 #define CT32B0_TCR_CEN 1UL
Ellor1 0:7076676dd640 133
Ellor1 0:7076676dd640 134 /*********************************************************************//**
Ellor1 2:857c3c8e7a2f 135 * Macro defines for CT32B1->TCR register bits LPC11U24 page 353
Ellor1 0:7076676dd640 136 **********************************************************************/
Ellor1 0:7076676dd640 137 #define CT32B1_TCR_CEN 1UL
Ellor1 0:7076676dd640 138
Ellor1 0:7076676dd640 139 /*********************************************************************//**
Ellor1 2:857c3c8e7a2f 140 * Macro defines for CT16B0->TCR register bits LPC11U24 page 335
Ellor1 0:7076676dd640 141 **********************************************************************/
Ellor1 0:7076676dd640 142 #define CT16B0_TCR_CEN 1UL
Ellor1 0:7076676dd640 143
Ellor1 0:7076676dd640 144 /*********************************************************************//**
Ellor1 2:857c3c8e7a2f 145 * Macro defines for CT32B0->CCR register bits LPC11U24 page 357
Ellor1 0:7076676dd640 146 **********************************************************************/
Ellor1 0:7076676dd640 147 #define CCR_CAP1RE ((uint32_t)(1<<6))
Ellor1 0:7076676dd640 148 #define CCR_CAP1FE ((uint32_t)(1<<7))
Ellor1 0:7076676dd640 149 #define CCR_CAP1I ((uint32_t)(1<<8))
Ellor1 0:7076676dd640 150
Ellor1 0:7076676dd640 151 /*********************************************************************//**
Ellor1 2:857c3c8e7a2f 152 * Macro defines for CT32B1->CCR register bits LPC11U24 page 356
Ellor1 0:7076676dd640 153 **********************************************************************/
Ellor1 0:7076676dd640 154 #define CCR_CAP0RE ((uint32_t)(1<<0))
Ellor1 0:7076676dd640 155 #define CCR_CAP0FE ((uint32_t)(1<<1))
Ellor1 0:7076676dd640 156 #define CCR_CAP0I ((uint32_t)(1<<2))
Ellor1 0:7076676dd640 157
Ellor1 0:7076676dd640 158 /*********************************************************************//**
Ellor1 2:857c3c8e7a2f 159 * Macro defines for CT32B0->CTCR register bits LPC11U24 page 361
Ellor1 0:7076676dd640 160 **********************************************************************/
Ellor1 0:7076676dd640 161 #define CT32B0_CTCR_CTM_TIMER 0UL
Ellor1 0:7076676dd640 162 #define CT32B0_CTCR_ENCC ((uint32_t)(1<<4))
Ellor1 0:7076676dd640 163 #define CT32B0_CTCR_SEICC_CAP1RE ((uint32_t)(4<<5))
Ellor1 0:7076676dd640 164 #define CT32B0_CTCR_SEICC_CAP1FE ((uint32_t)(5<<5))
Ellor1 0:7076676dd640 165
Ellor1 0:7076676dd640 166
Ellor1 0:7076676dd640 167 /*********************************************************************//**
Ellor1 2:857c3c8e7a2f 168 * Macro defines for CT32B1->CTCR register bits LPC11U24 page 362
Ellor1 0:7076676dd640 169 **********************************************************************/
Ellor1 0:7076676dd640 170 #define CT32B1_CTCR_CTM_TIMER 0UL
Ellor1 0:7076676dd640 171 #define CT32B1_CTCR_ENCC ((uint32_t)(1<<4))
Ellor1 0:7076676dd640 172 #define CT32B1_CTCR_SEICC_CAP0RE ((uint32_t)(0<<5)) //CT32B1_CAP0
Ellor1 0:7076676dd640 173 #define CT32B1_CTCR_SEICC_CAP0FE ((uint32_t)(1<<5))
Ellor1 0:7076676dd640 174
Ellor1 2:857c3c8e7a2f 175 /*********************************************************************//**
Ellor1 2:857c3c8e7a2f 176 * Macro defines for CT16B0->MCR register bits LPC11U24 page 337
Ellor1 2:857c3c8e7a2f 177 **********************************************************************/
Ellor1 0:7076676dd640 178 #define CT16B0_MR0I ((uint32_t)(1<<0))
Ellor1 0:7076676dd640 179 #define CT16B0_MR0R ((uint32_t)(1<<1))
Ellor1 0:7076676dd640 180
Ellor1 0:7076676dd640 181 }; // End of Capture class information
Ellor1 0:7076676dd640 182 #endif /* CAPTURE_H */
Ellor1 0:7076676dd640 183 /* --------------------------------- End Of File ------------------------------ */