Callum Ellor / PulseWidthCapture

Library to Capture the +ve and -ve Pulsewidth of a signal

Dependents:   PulseWidthCapture_Program

PulseWidthCapture.h@1:6bb38ae2e503, 2014-12-10 (annotated)

Committer:
Ellor1
Date:
Wed Dec 10 10:33:32 2014 +0000
Revision:
1:6bb38ae2e503
Parent:
0:7076676dd640
Child:
2:857c3c8e7a2f
Working LCD;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Ellor1 0:7076676dd640 1 /* mbed Library - PulseWidthCapture
Ellor1 0:7076676dd640 2 * Copyright (c) 2014
Ellor1 0:7076676dd640 3 * released under MIT license http://mbed.org/licence/mit
Ellor1 0:7076676dd640 4 */
Ellor1 0:7076676dd640 5
Ellor1 0:7076676dd640 6 /***********************************************************************//**
Ellor1 0:7076676dd640 7 * @file PulseWidthCapture.h
Ellor1 0:7076676dd640 8 * @brief Header file for the PulseWidthCapture library.
Ellor1 0:7076676dd640 9 * @version 0.0
Ellor1 0:7076676dd640 10 * @date 03 Dec 2014
Ellor1 0:7076676dd640 11 * @author
Ellor1 0:7076676dd640 12 **************************************************************************/
Ellor1 0:7076676dd640 13 /***************************************************************************
Ellor1 0:7076676dd640 14 * Revision Date Comments
Ellor1 0:7076676dd640 15 *---------- -------- -----------------------------------------------
Ellor1 0:7076676dd640 16 *
Ellor1 0:7076676dd640 17 * 0.0 03/12/14 Initial creation
Ellor1 0:7076676dd640 18 ***************************************************************************/
Ellor1 0:7076676dd640 19
Ellor1 0:7076676dd640 20 #ifndef CAPTURET0_H
Ellor1 0:7076676dd640 21 #define CAPTURET0_H
Ellor1 0:7076676dd640 22
Ellor1 0:7076676dd640 23 /* Includes ------------------------------------------------------------------- */
Ellor1 0:7076676dd640 24 #include "mbed.h"
Ellor1 0:7076676dd640 25
Ellor1 0:7076676dd640 26 /* Public Types --------------------------------------------------------------- */
Ellor1 0:7076676dd640 27
Ellor1 0:7076676dd640 28
Ellor1 0:7076676dd640 29 /* Public Functions ----------------------------------------------------------- */
Ellor1 0:7076676dd640 30 /** @defgroup Capture_Public_Functions Capture Public Functions
Ellor1 0:7076676dd640 31 */
Ellor1 0:7076676dd640 32 class Capture {
Ellor1 0:7076676dd640 33 public:
Ellor1 0:7076676dd640 34
Ellor1 0:7076676dd640 35 /** Create a Capture object and configure it
Ellor1 0:7076676dd640 36 *
Ellor1 0:7076676dd640 37 * @param none
Ellor1 0:7076676dd640 38 */
Ellor1 0:7076676dd640 39 Capture(void);
Ellor1 0:7076676dd640 40
Ellor1 0:7076676dd640 41 /** Start capturing data. Accumulate the specified number of samples.
Ellor1 0:7076676dd640 42 * @param numsamples The number of samples to be accumulated
Ellor1 0:7076676dd640 43 * @return None
Ellor1 0:7076676dd640 44 */
Ellor1 0:7076676dd640 45 void Start_1(void);
Ellor1 0:7076676dd640 46
Ellor1 0:7076676dd640 47 void Start_2(void);
Ellor1 0:7076676dd640 48
Ellor1 0:7076676dd640 49 void Wait(void);
Ellor1 0:7076676dd640 50
Ellor1 0:7076676dd640 51
Ellor1 0:7076676dd640 52 /** Read (accumlated) sample count.
Ellor1 0:7076676dd640 53 *
Ellor1 0:7076676dd640 54 * @return (unsigned int) Accumulated capture value
Ellor1 0:7076676dd640 55 */
Ellor1 0:7076676dd640 56 //unsigned int Read_1(void);
Ellor1 0:7076676dd640 57 void Read_1(void);
Ellor1 0:7076676dd640 58
Ellor1 0:7076676dd640 59 //unsigned int Read_2(void);
Ellor1 0:7076676dd640 60 void Read_2(void);
Ellor1 0:7076676dd640 61
Ellor1 0:7076676dd640 62 unsigned int Debug(void);
Ellor1 0:7076676dd640 63
Ellor1 0:7076676dd640 64 /* Public Macros -------------------------------------------------------------- */
Ellor1 0:7076676dd640 65
Ellor1 0:7076676dd640 66 private:
Ellor1 0:7076676dd640 67 static void _Captureisr1(void);
Ellor1 0:7076676dd640 68 static void _Captureisr2(void);
Ellor1 0:7076676dd640 69 static void _Captureisr3(void);
Ellor1 0:7076676dd640 70 void Captureisr1(void);
Ellor1 0:7076676dd640 71 void Captureisr2(void);
Ellor1 0:7076676dd640 72 void Captureisr3(void);
Ellor1 0:7076676dd640 73 static Capture *instance;
Ellor1 0:7076676dd640 74 //double capturedata;
Ellor1 0:7076676dd640 75 unsigned int capturedata;
Ellor1 0:7076676dd640 76 unsigned int capturedata_2;
Ellor1 0:7076676dd640 77 unsigned int test_1, test_2;
Ellor1 1:6bb38ae2e503 78 float rise, fall, period, freq;
Ellor1 0:7076676dd640 79 double rise_2, fall_2, i_1, j_1, m_1;
Ellor1 0:7076676dd640 80 unsigned int debug;
Ellor1 0:7076676dd640 81
Ellor1 0:7076676dd640 82 /* Private Macros ------------------------------------------------------------- */
Ellor1 0:7076676dd640 83 /* --------------------- BIT DEFINITIONS -------------------------------------- */
Ellor1 0:7076676dd640 84 /* Timer Capture Register Definitions --------------------- */
Ellor1 0:7076676dd640 85
Ellor1 0:7076676dd640 86 /*********************************************************************//**
Ellor1 0:7076676dd640 87 * Macro defines for CT32B0->IR Interrupt tegister
Ellor1 0:7076676dd640 88 **********************************************************************/
Ellor1 0:7076676dd640 89 #define CT32B0_IR_CR0INT ((uint32_t)(1<<4))
Ellor1 0:7076676dd640 90 #define CT32B0_IR_CR1INT ((uint32_t)(1<<6)) /**< Interrupt flag for capture channel 1 */
Ellor1 0:7076676dd640 91
Ellor1 0:7076676dd640 92 #define CT16B0_IR_MR0INT ((uint32_t)(1<<0))
Ellor1 0:7076676dd640 93
Ellor1 0:7076676dd640 94
Ellor1 0:7076676dd640 95 /*********************************************************************//**
Ellor1 0:7076676dd640 96 * Macro defines for CT32B1->IR Interrupt tegister
Ellor1 0:7076676dd640 97 **********************************************************************/
Ellor1 0:7076676dd640 98 #define CT32B1_IR_CR0INT ((uint32_t)(1<<4)) /**< Interrupt flag for capture channel 1 */
Ellor1 0:7076676dd640 99 #define CT32B1_IR_CR1INT ((uint32_t)(1<<5))
Ellor1 0:7076676dd640 100
Ellor1 0:7076676dd640 101 /*********************************************************************//**
Ellor1 0:7076676dd640 102 * Macro defines for IOCON->PIO1_29 register bits LPC11U24
Ellor1 0:7076676dd640 103 **********************************************************************/
Ellor1 0:7076676dd640 104 #define P1_29_PIN_PULL_UP 2UL
Ellor1 0:7076676dd640 105 #define P1_29_PIN_REPEATER 3UL
Ellor1 0:7076676dd640 106 #define P1_29_PIN_NORESISTOR 0UL
Ellor1 0:7076676dd640 107 #define P1_29_PIN_PULL_DOWN 1UL
Ellor1 0:7076676dd640 108
Ellor1 0:7076676dd640 109 /* FUNC bits */
Ellor1 0:7076676dd640 110 #define PORT_PIO1_29 0UL
Ellor1 0:7076676dd640 111 #define SCKO 1UL
Ellor1 0:7076676dd640 112 #define CT32B0_CAP1 2UL
Ellor1 0:7076676dd640 113
Ellor1 0:7076676dd640 114
Ellor1 0:7076676dd640 115
Ellor1 0:7076676dd640 116 /* MODE bits */
Ellor1 0:7076676dd640 117 #define P1_29_CAP_PULLUP ((uint32_t)(PIN_PULL_UP<<3)) // Pull up on the CT32B0_CAP1 input pin
Ellor1 0:7076676dd640 118
Ellor1 0:7076676dd640 119 /*********************************************************************//**
Ellor1 0:7076676dd640 120 * Macro defines for IOCON->PIO0_12 register bits LPC11U24
Ellor1 0:7076676dd640 121 **********************************************************************/
Ellor1 0:7076676dd640 122 #define P0_12_PIN_PULL_UP 2UL
Ellor1 0:7076676dd640 123 #define P0_12_PIN_REPEATER 3UL
Ellor1 0:7076676dd640 124 #define P0_12_PIN_NORESISTOR 0UL
Ellor1 0:7076676dd640 125 #define P0_12_PIN_PULL_DOWN 1UL
Ellor1 0:7076676dd640 126
Ellor1 0:7076676dd640 127 /* FUNC bits */
Ellor1 0:7076676dd640 128 #define PIO0_12 1UL
Ellor1 0:7076676dd640 129 #define ADL 2UL
Ellor1 0:7076676dd640 130 #define CT32B1_CAP0 3UL //forPIO0_12
Ellor1 0:7076676dd640 131 #define ADMODE ((uint32_t)(1<<7))
Ellor1 0:7076676dd640 132 #define FILTR ((uint32_t)(1<<8))
Ellor1 0:7076676dd640 133
Ellor1 0:7076676dd640 134 /* MODE bits */
Ellor1 0:7076676dd640 135 #define P0_12_CAP_PULLUP ((uint32_t)(PIN_PULL_UP<<3)) // Pull up on the CT32B0_CAP1 input pin
Ellor1 0:7076676dd640 136
Ellor1 0:7076676dd640 137 /*********************************************************************//**
Ellor1 0:7076676dd640 138 * Macro defines for SYSCON->SYSAHBCLKDIV register bits LPC11U24
Ellor1 0:7076676dd640 139 **********************************************************************/
Ellor1 0:7076676dd640 140 #define CT32B0_CLK_ENABLE ((uint32_t)(1<<9)) /**< CT32B0 clock enable */
Ellor1 0:7076676dd640 141
Ellor1 0:7076676dd640 142 #define CT32B1_CLK_ENABLE ((uint32_t)(1<<10))
Ellor1 0:7076676dd640 143
Ellor1 0:7076676dd640 144 #define CT16B0_CLK_ENABLE ((uint32_t)(1<<7))
Ellor1 0:7076676dd640 145 /*********************************************************************//**
Ellor1 0:7076676dd640 146 * Macro defines for CT32B0->TCR register bits LPC11U24
Ellor1 0:7076676dd640 147 **********************************************************************/
Ellor1 0:7076676dd640 148 #define CT32B0_TCR_CEN 1UL
Ellor1 0:7076676dd640 149
Ellor1 0:7076676dd640 150 /*********************************************************************//**
Ellor1 0:7076676dd640 151 * Macro defines for CT32B1->TCR register bits LPC11U24
Ellor1 0:7076676dd640 152 **********************************************************************/
Ellor1 0:7076676dd640 153 #define CT32B1_TCR_CEN 1UL
Ellor1 0:7076676dd640 154
Ellor1 0:7076676dd640 155 /*********************************************************************//**
Ellor1 0:7076676dd640 156 * Macro defines for CT16B0->TCR register bits LPC11U24
Ellor1 0:7076676dd640 157 **********************************************************************/
Ellor1 0:7076676dd640 158 #define CT16B0_TCR_CEN 1UL
Ellor1 0:7076676dd640 159
Ellor1 0:7076676dd640 160 /*********************************************************************//**
Ellor1 0:7076676dd640 161 * Macro defines for CT32B0->CCR register bits LPC11U24
Ellor1 0:7076676dd640 162 **********************************************************************/
Ellor1 0:7076676dd640 163 #define CCR_CAP1RE ((uint32_t)(1<<6))
Ellor1 0:7076676dd640 164 #define CCR_CAP1FE ((uint32_t)(1<<7))
Ellor1 0:7076676dd640 165 #define CCR_CAP1I ((uint32_t)(1<<8))
Ellor1 0:7076676dd640 166
Ellor1 0:7076676dd640 167 /*********************************************************************//**
Ellor1 0:7076676dd640 168 * Macro defines for CT32B1->CCR register bits LPC11U24
Ellor1 0:7076676dd640 169 **********************************************************************/
Ellor1 0:7076676dd640 170 #define CCR_CAP0RE ((uint32_t)(1<<0))
Ellor1 0:7076676dd640 171 #define CCR_CAP0FE ((uint32_t)(1<<1))
Ellor1 0:7076676dd640 172 #define CCR_CAP0I ((uint32_t)(1<<2))
Ellor1 0:7076676dd640 173
Ellor1 0:7076676dd640 174 /*********************************************************************//**
Ellor1 0:7076676dd640 175 * Macro defines for CT32B0->CTCR register bits LPC11U24
Ellor1 0:7076676dd640 176 **********************************************************************/
Ellor1 0:7076676dd640 177 #define CT32B0_CTCR_CTM_TIMER 0UL
Ellor1 0:7076676dd640 178 #define CT32B0_CTCR_ENCC ((uint32_t)(1<<4))
Ellor1 0:7076676dd640 179 #define CT32B0_CTCR_SEICC_CAP1RE ((uint32_t)(4<<5))
Ellor1 0:7076676dd640 180 #define CT32B0_CTCR_SEICC_CAP1FE ((uint32_t)(5<<5))
Ellor1 0:7076676dd640 181
Ellor1 0:7076676dd640 182
Ellor1 0:7076676dd640 183 /*********************************************************************//**
Ellor1 0:7076676dd640 184 * Macro defines for CT32B1->CTCR register bits LPC11U24
Ellor1 0:7076676dd640 185 **********************************************************************/
Ellor1 0:7076676dd640 186 #define CT32B1_CTCR_CTM_TIMER 0UL
Ellor1 0:7076676dd640 187 #define CT32B1_CTCR_ENCC ((uint32_t)(1<<4))
Ellor1 0:7076676dd640 188 #define CT32B1_CTCR_SEICC_CAP0RE ((uint32_t)(0<<5)) //CT32B1_CAP0
Ellor1 0:7076676dd640 189 #define CT32B1_CTCR_SEICC_CAP0FE ((uint32_t)(1<<5))
Ellor1 0:7076676dd640 190
Ellor1 0:7076676dd640 191 #define CT16B0_MR0I ((uint32_t)(1<<0))
Ellor1 0:7076676dd640 192
Ellor1 0:7076676dd640 193 #define CT16B0_MR0R ((uint32_t)(1<<1))
Ellor1 0:7076676dd640 194
Ellor1 0:7076676dd640 195
Ellor1 0:7076676dd640 196
Ellor1 0:7076676dd640 197 }; // End of Capture class information
Ellor1 0:7076676dd640 198 #endif /* CAPTURE_H */
Ellor1 0:7076676dd640 199 /* --------------------------------- End Of File ------------------------------ */