Andrew Schaeffer / Mbed 2 deprecated OU_Davis_Old_Robot

This is the project for the Old Model Robots for OU's Dr. Davis's Configurable Robots Research. This is being published so future robots can be set up easily.

Dependencies:   FatFileSystem MCP3008 Motor PinDetect QTR_8A SRF05 SSD1308_128x64_I2C mbed

PowerControl/EthernetPowerControl.h@0:bcad524c1856, 2017-11-01 (annotated)

Committer:
DrewSchaef
Date:
Wed Nov 01 15:57:59 2017 +0000
Revision:
0:bcad524c1856
Published the project to allow access for future work on the Configurable Robots Research Project(s).

Who changed what in which revision?

UserRevisionLine numberNew contents of line
DrewSchaef 0:bcad524c1856 1 /* mbed PowerControl Library
DrewSchaef 0:bcad524c1856 2 * Copyright (c) 2010 Michael Wei
DrewSchaef 0:bcad524c1856 3 */
DrewSchaef 0:bcad524c1856 4
DrewSchaef 0:bcad524c1856 5 #ifndef MBED_POWERCONTROL_ETH_H
DrewSchaef 0:bcad524c1856 6 #define MBED_POWERCONTROL_ETH_H
DrewSchaef 0:bcad524c1856 7
DrewSchaef 0:bcad524c1856 8 #include "mbed.h"
DrewSchaef 0:bcad524c1856 9 #include "PowerControl.h"
DrewSchaef 0:bcad524c1856 10
DrewSchaef 0:bcad524c1856 11 #define PHY_REG_BMCR_POWERDOWN 0xB
DrewSchaef 0:bcad524c1856 12 #define PHY_REG_EDCR_ENABLE 0xF
DrewSchaef 0:bcad524c1856 13
DrewSchaef 0:bcad524c1856 14
DrewSchaef 0:bcad524c1856 15 void EMAC_Init();
DrewSchaef 0:bcad524c1856 16 static unsigned short read_PHY (unsigned int PhyReg);
DrewSchaef 0:bcad524c1856 17 static void write_PHY (unsigned int PhyReg, unsigned short Value);
DrewSchaef 0:bcad524c1856 18
DrewSchaef 0:bcad524c1856 19 void PHY_PowerDown(void);
DrewSchaef 0:bcad524c1856 20 void PHY_PowerUp(void);
DrewSchaef 0:bcad524c1856 21 void PHY_EnergyDetect_Enable(void);
DrewSchaef 0:bcad524c1856 22 void PHY_EnergyDetect_Disable(void);
DrewSchaef 0:bcad524c1856 23
DrewSchaef 0:bcad524c1856 24 //From NXP Sample Code .... Probably from KEIL sample code
DrewSchaef 0:bcad524c1856 25 /* EMAC Memory Buffer configuration for 16K Ethernet RAM. */
DrewSchaef 0:bcad524c1856 26 #define NUM_RX_FRAG 4 /* Num.of RX Fragments 4*1536= 6.0kB */
DrewSchaef 0:bcad524c1856 27 #define NUM_TX_FRAG 3 /* Num.of TX Fragments 3*1536= 4.6kB */
DrewSchaef 0:bcad524c1856 28 #define ETH_FRAG_SIZE 1536 /* Packet Fragment size 1536 Bytes */
DrewSchaef 0:bcad524c1856 29
DrewSchaef 0:bcad524c1856 30 #define ETH_MAX_FLEN 1536 /* Max. Ethernet Frame Size */
DrewSchaef 0:bcad524c1856 31
DrewSchaef 0:bcad524c1856 32 /* EMAC variables located in 16K Ethernet SRAM */
DrewSchaef 0:bcad524c1856 33 #define RX_DESC_BASE 0x20080000
DrewSchaef 0:bcad524c1856 34 #define RX_STAT_BASE (RX_DESC_BASE + NUM_RX_FRAG*8)
DrewSchaef 0:bcad524c1856 35 #define TX_DESC_BASE (RX_STAT_BASE + NUM_RX_FRAG*8)
DrewSchaef 0:bcad524c1856 36 #define TX_STAT_BASE (TX_DESC_BASE + NUM_TX_FRAG*8)
DrewSchaef 0:bcad524c1856 37 #define RX_BUF_BASE (TX_STAT_BASE + NUM_TX_FRAG*4)
DrewSchaef 0:bcad524c1856 38 #define TX_BUF_BASE (RX_BUF_BASE + NUM_RX_FRAG*ETH_FRAG_SIZE)
DrewSchaef 0:bcad524c1856 39
DrewSchaef 0:bcad524c1856 40 /* RX and TX descriptor and status definitions. */
DrewSchaef 0:bcad524c1856 41 #define RX_DESC_PACKET(i) (*(unsigned int *)(RX_DESC_BASE + 8*i))
DrewSchaef 0:bcad524c1856 42 #define RX_DESC_CTRL(i) (*(unsigned int *)(RX_DESC_BASE+4 + 8*i))
DrewSchaef 0:bcad524c1856 43 #define RX_STAT_INFO(i) (*(unsigned int *)(RX_STAT_BASE + 8*i))
DrewSchaef 0:bcad524c1856 44 #define RX_STAT_HASHCRC(i) (*(unsigned int *)(RX_STAT_BASE+4 + 8*i))
DrewSchaef 0:bcad524c1856 45 #define TX_DESC_PACKET(i) (*(unsigned int *)(TX_DESC_BASE + 8*i))
DrewSchaef 0:bcad524c1856 46 #define TX_DESC_CTRL(i) (*(unsigned int *)(TX_DESC_BASE+4 + 8*i))
DrewSchaef 0:bcad524c1856 47 #define TX_STAT_INFO(i) (*(unsigned int *)(TX_STAT_BASE + 4*i))
DrewSchaef 0:bcad524c1856 48 #define RX_BUF(i) (RX_BUF_BASE + ETH_FRAG_SIZE*i)
DrewSchaef 0:bcad524c1856 49 #define TX_BUF(i) (TX_BUF_BASE + ETH_FRAG_SIZE*i)
DrewSchaef 0:bcad524c1856 50
DrewSchaef 0:bcad524c1856 51 /* MAC Configuration Register 1 */
DrewSchaef 0:bcad524c1856 52 #define MAC1_REC_EN 0x00000001 /* Receive Enable */
DrewSchaef 0:bcad524c1856 53 #define MAC1_PASS_ALL 0x00000002 /* Pass All Receive Frames */
DrewSchaef 0:bcad524c1856 54 #define MAC1_RX_FLOWC 0x00000004 /* RX Flow Control */
DrewSchaef 0:bcad524c1856 55 #define MAC1_TX_FLOWC 0x00000008 /* TX Flow Control */
DrewSchaef 0:bcad524c1856 56 #define MAC1_LOOPB 0x00000010 /* Loop Back Mode */
DrewSchaef 0:bcad524c1856 57 #define MAC1_RES_TX 0x00000100 /* Reset TX Logic */
DrewSchaef 0:bcad524c1856 58 #define MAC1_RES_MCS_TX 0x00000200 /* Reset MAC TX Control Sublayer */
DrewSchaef 0:bcad524c1856 59 #define MAC1_RES_RX 0x00000400 /* Reset RX Logic */
DrewSchaef 0:bcad524c1856 60 #define MAC1_RES_MCS_RX 0x00000800 /* Reset MAC RX Control Sublayer */
DrewSchaef 0:bcad524c1856 61 #define MAC1_SIM_RES 0x00004000 /* Simulation Reset */
DrewSchaef 0:bcad524c1856 62 #define MAC1_SOFT_RES 0x00008000 /* Soft Reset MAC */
DrewSchaef 0:bcad524c1856 63
DrewSchaef 0:bcad524c1856 64 /* MAC Configuration Register 2 */
DrewSchaef 0:bcad524c1856 65 #define MAC2_FULL_DUP 0x00000001 /* Full Duplex Mode */
DrewSchaef 0:bcad524c1856 66 #define MAC2_FRM_LEN_CHK 0x00000002 /* Frame Length Checking */
DrewSchaef 0:bcad524c1856 67 #define MAC2_HUGE_FRM_EN 0x00000004 /* Huge Frame Enable */
DrewSchaef 0:bcad524c1856 68 #define MAC2_DLY_CRC 0x00000008 /* Delayed CRC Mode */
DrewSchaef 0:bcad524c1856 69 #define MAC2_CRC_EN 0x00000010 /* Append CRC to every Frame */
DrewSchaef 0:bcad524c1856 70 #define MAC2_PAD_EN 0x00000020 /* Pad all Short Frames */
DrewSchaef 0:bcad524c1856 71 #define MAC2_VLAN_PAD_EN 0x00000040 /* VLAN Pad Enable */
DrewSchaef 0:bcad524c1856 72 #define MAC2_ADET_PAD_EN 0x00000080 /* Auto Detect Pad Enable */
DrewSchaef 0:bcad524c1856 73 #define MAC2_PPREAM_ENF 0x00000100 /* Pure Preamble Enforcement */
DrewSchaef 0:bcad524c1856 74 #define MAC2_LPREAM_ENF 0x00000200 /* Long Preamble Enforcement */
DrewSchaef 0:bcad524c1856 75 #define MAC2_NO_BACKOFF 0x00001000 /* No Backoff Algorithm */
DrewSchaef 0:bcad524c1856 76 #define MAC2_BACK_PRESSURE 0x00002000 /* Backoff Presurre / No Backoff */
DrewSchaef 0:bcad524c1856 77 #define MAC2_EXCESS_DEF 0x00004000 /* Excess Defer */
DrewSchaef 0:bcad524c1856 78
DrewSchaef 0:bcad524c1856 79 /* Back-to-Back Inter-Packet-Gap Register */
DrewSchaef 0:bcad524c1856 80 #define IPGT_FULL_DUP 0x00000015 /* Recommended value for Full Duplex */
DrewSchaef 0:bcad524c1856 81 #define IPGT_HALF_DUP 0x00000012 /* Recommended value for Half Duplex */
DrewSchaef 0:bcad524c1856 82
DrewSchaef 0:bcad524c1856 83 /* Non Back-to-Back Inter-Packet-Gap Register */
DrewSchaef 0:bcad524c1856 84 #define IPGR_DEF 0x00000012 /* Recommended value */
DrewSchaef 0:bcad524c1856 85
DrewSchaef 0:bcad524c1856 86 /* Collision Window/Retry Register */
DrewSchaef 0:bcad524c1856 87 #define CLRT_DEF 0x0000370F /* Default value */
DrewSchaef 0:bcad524c1856 88
DrewSchaef 0:bcad524c1856 89 /* PHY Support Register */
DrewSchaef 0:bcad524c1856 90 #define SUPP_SPEED 0x00000100 /* Reduced MII Logic Current Speed */
DrewSchaef 0:bcad524c1856 91 #define SUPP_RES_RMII 0x00000800 /* Reset Reduced MII Logic */
DrewSchaef 0:bcad524c1856 92
DrewSchaef 0:bcad524c1856 93 /* Test Register */
DrewSchaef 0:bcad524c1856 94 #define TEST_SHCUT_PQUANTA 0x00000001 /* Shortcut Pause Quanta */
DrewSchaef 0:bcad524c1856 95 #define TEST_TST_PAUSE 0x00000002 /* Test Pause */
DrewSchaef 0:bcad524c1856 96 #define TEST_TST_BACKP 0x00000004 /* Test Back Pressure */
DrewSchaef 0:bcad524c1856 97
DrewSchaef 0:bcad524c1856 98 /* MII Management Configuration Register */
DrewSchaef 0:bcad524c1856 99 #define MCFG_SCAN_INC 0x00000001 /* Scan Increment PHY Address */
DrewSchaef 0:bcad524c1856 100 #define MCFG_SUPP_PREAM 0x00000002 /* Suppress Preamble */
DrewSchaef 0:bcad524c1856 101 #define MCFG_CLK_SEL 0x0000001C /* Clock Select Mask */
DrewSchaef 0:bcad524c1856 102 #define MCFG_RES_MII 0x00008000 /* Reset MII Management Hardware */
DrewSchaef 0:bcad524c1856 103
DrewSchaef 0:bcad524c1856 104 /* MII Management Command Register */
DrewSchaef 0:bcad524c1856 105 #define MCMD_READ 0x00000001 /* MII Read */
DrewSchaef 0:bcad524c1856 106 #define MCMD_SCAN 0x00000002 /* MII Scan continuously */
DrewSchaef 0:bcad524c1856 107
DrewSchaef 0:bcad524c1856 108 #define MII_WR_TOUT 0x00050000 /* MII Write timeout count */
DrewSchaef 0:bcad524c1856 109 #define MII_RD_TOUT 0x00050000 /* MII Read timeout count */
DrewSchaef 0:bcad524c1856 110
DrewSchaef 0:bcad524c1856 111 /* MII Management Address Register */
DrewSchaef 0:bcad524c1856 112 #define MADR_REG_ADR 0x0000001F /* MII Register Address Mask */
DrewSchaef 0:bcad524c1856 113 #define MADR_PHY_ADR 0x00001F00 /* PHY Address Mask */
DrewSchaef 0:bcad524c1856 114
DrewSchaef 0:bcad524c1856 115 /* MII Management Indicators Register */
DrewSchaef 0:bcad524c1856 116 #define MIND_BUSY 0x00000001 /* MII is Busy */
DrewSchaef 0:bcad524c1856 117 #define MIND_SCAN 0x00000002 /* MII Scanning in Progress */
DrewSchaef 0:bcad524c1856 118 #define MIND_NOT_VAL 0x00000004 /* MII Read Data not valid */
DrewSchaef 0:bcad524c1856 119 #define MIND_MII_LINK_FAIL 0x00000008 /* MII Link Failed */
DrewSchaef 0:bcad524c1856 120
DrewSchaef 0:bcad524c1856 121 /* Command Register */
DrewSchaef 0:bcad524c1856 122 #define CR_RX_EN 0x00000001 /* Enable Receive */
DrewSchaef 0:bcad524c1856 123 #define CR_TX_EN 0x00000002 /* Enable Transmit */
DrewSchaef 0:bcad524c1856 124 #define CR_REG_RES 0x00000008 /* Reset Host Registers */
DrewSchaef 0:bcad524c1856 125 #define CR_TX_RES 0x00000010 /* Reset Transmit Datapath */
DrewSchaef 0:bcad524c1856 126 #define CR_RX_RES 0x00000020 /* Reset Receive Datapath */
DrewSchaef 0:bcad524c1856 127 #define CR_PASS_RUNT_FRM 0x00000040 /* Pass Runt Frames */
DrewSchaef 0:bcad524c1856 128 #define CR_PASS_RX_FILT 0x00000080 /* Pass RX Filter */
DrewSchaef 0:bcad524c1856 129 #define CR_TX_FLOW_CTRL 0x00000100 /* TX Flow Control */
DrewSchaef 0:bcad524c1856 130 #define CR_RMII 0x00000200 /* Reduced MII Interface */
DrewSchaef 0:bcad524c1856 131 #define CR_FULL_DUP 0x00000400 /* Full Duplex */
DrewSchaef 0:bcad524c1856 132
DrewSchaef 0:bcad524c1856 133 /* Status Register */
DrewSchaef 0:bcad524c1856 134 #define SR_RX_EN 0x00000001 /* Enable Receive */
DrewSchaef 0:bcad524c1856 135 #define SR_TX_EN 0x00000002 /* Enable Transmit */
DrewSchaef 0:bcad524c1856 136
DrewSchaef 0:bcad524c1856 137 /* Transmit Status Vector 0 Register */
DrewSchaef 0:bcad524c1856 138 #define TSV0_CRC_ERR 0x00000001 /* CRC error */
DrewSchaef 0:bcad524c1856 139 #define TSV0_LEN_CHKERR 0x00000002 /* Length Check Error */
DrewSchaef 0:bcad524c1856 140 #define TSV0_LEN_OUTRNG 0x00000004 /* Length Out of Range */
DrewSchaef 0:bcad524c1856 141 #define TSV0_DONE 0x00000008 /* Tramsmission Completed */
DrewSchaef 0:bcad524c1856 142 #define TSV0_MCAST 0x00000010 /* Multicast Destination */
DrewSchaef 0:bcad524c1856 143 #define TSV0_BCAST 0x00000020 /* Broadcast Destination */
DrewSchaef 0:bcad524c1856 144 #define TSV0_PKT_DEFER 0x00000040 /* Packet Deferred */
DrewSchaef 0:bcad524c1856 145 #define TSV0_EXC_DEFER 0x00000080 /* Excessive Packet Deferral */
DrewSchaef 0:bcad524c1856 146 #define TSV0_EXC_COLL 0x00000100 /* Excessive Collision */
DrewSchaef 0:bcad524c1856 147 #define TSV0_LATE_COLL 0x00000200 /* Late Collision Occured */
DrewSchaef 0:bcad524c1856 148 #define TSV0_GIANT 0x00000400 /* Giant Frame */
DrewSchaef 0:bcad524c1856 149 #define TSV0_UNDERRUN 0x00000800 /* Buffer Underrun */
DrewSchaef 0:bcad524c1856 150 #define TSV0_BYTES 0x0FFFF000 /* Total Bytes Transferred */
DrewSchaef 0:bcad524c1856 151 #define TSV0_CTRL_FRAME 0x10000000 /* Control Frame */
DrewSchaef 0:bcad524c1856 152 #define TSV0_PAUSE 0x20000000 /* Pause Frame */
DrewSchaef 0:bcad524c1856 153 #define TSV0_BACK_PRESS 0x40000000 /* Backpressure Method Applied */
DrewSchaef 0:bcad524c1856 154 #define TSV0_VLAN 0x80000000 /* VLAN Frame */
DrewSchaef 0:bcad524c1856 155
DrewSchaef 0:bcad524c1856 156 /* Transmit Status Vector 1 Register */
DrewSchaef 0:bcad524c1856 157 #define TSV1_BYTE_CNT 0x0000FFFF /* Transmit Byte Count */
DrewSchaef 0:bcad524c1856 158 #define TSV1_COLL_CNT 0x000F0000 /* Transmit Collision Count */
DrewSchaef 0:bcad524c1856 159
DrewSchaef 0:bcad524c1856 160 /* Receive Status Vector Register */
DrewSchaef 0:bcad524c1856 161 #define RSV_BYTE_CNT 0x0000FFFF /* Receive Byte Count */
DrewSchaef 0:bcad524c1856 162 #define RSV_PKT_IGNORED 0x00010000 /* Packet Previously Ignored */
DrewSchaef 0:bcad524c1856 163 #define RSV_RXDV_SEEN 0x00020000 /* RXDV Event Previously Seen */
DrewSchaef 0:bcad524c1856 164 #define RSV_CARR_SEEN 0x00040000 /* Carrier Event Previously Seen */
DrewSchaef 0:bcad524c1856 165 #define RSV_REC_CODEV 0x00080000 /* Receive Code Violation */
DrewSchaef 0:bcad524c1856 166 #define RSV_CRC_ERR 0x00100000 /* CRC Error */
DrewSchaef 0:bcad524c1856 167 #define RSV_LEN_CHKERR 0x00200000 /* Length Check Error */
DrewSchaef 0:bcad524c1856 168 #define RSV_LEN_OUTRNG 0x00400000 /* Length Out of Range */
DrewSchaef 0:bcad524c1856 169 #define RSV_REC_OK 0x00800000 /* Frame Received OK */
DrewSchaef 0:bcad524c1856 170 #define RSV_MCAST 0x01000000 /* Multicast Frame */
DrewSchaef 0:bcad524c1856 171 #define RSV_BCAST 0x02000000 /* Broadcast Frame */
DrewSchaef 0:bcad524c1856 172 #define RSV_DRIB_NIBB 0x04000000 /* Dribble Nibble */
DrewSchaef 0:bcad524c1856 173 #define RSV_CTRL_FRAME 0x08000000 /* Control Frame */
DrewSchaef 0:bcad524c1856 174 #define RSV_PAUSE 0x10000000 /* Pause Frame */
DrewSchaef 0:bcad524c1856 175 #define RSV_UNSUPP_OPC 0x20000000 /* Unsupported Opcode */
DrewSchaef 0:bcad524c1856 176 #define RSV_VLAN 0x40000000 /* VLAN Frame */
DrewSchaef 0:bcad524c1856 177
DrewSchaef 0:bcad524c1856 178 /* Flow Control Counter Register */
DrewSchaef 0:bcad524c1856 179 #define FCC_MIRR_CNT 0x0000FFFF /* Mirror Counter */
DrewSchaef 0:bcad524c1856 180 #define FCC_PAUSE_TIM 0xFFFF0000 /* Pause Timer */
DrewSchaef 0:bcad524c1856 181
DrewSchaef 0:bcad524c1856 182 /* Flow Control Status Register */
DrewSchaef 0:bcad524c1856 183 #define FCS_MIRR_CNT 0x0000FFFF /* Mirror Counter Current */
DrewSchaef 0:bcad524c1856 184
DrewSchaef 0:bcad524c1856 185 /* Receive Filter Control Register */
DrewSchaef 0:bcad524c1856 186 #define RFC_UCAST_EN 0x00000001 /* Accept Unicast Frames Enable */
DrewSchaef 0:bcad524c1856 187 #define RFC_BCAST_EN 0x00000002 /* Accept Broadcast Frames Enable */
DrewSchaef 0:bcad524c1856 188 #define RFC_MCAST_EN 0x00000004 /* Accept Multicast Frames Enable */
DrewSchaef 0:bcad524c1856 189 #define RFC_UCAST_HASH_EN 0x00000008 /* Accept Unicast Hash Filter Frames */
DrewSchaef 0:bcad524c1856 190 #define RFC_MCAST_HASH_EN 0x00000010 /* Accept Multicast Hash Filter Fram.*/
DrewSchaef 0:bcad524c1856 191 #define RFC_PERFECT_EN 0x00000020 /* Accept Perfect Match Enable */
DrewSchaef 0:bcad524c1856 192 #define RFC_MAGP_WOL_EN 0x00001000 /* Magic Packet Filter WoL Enable */
DrewSchaef 0:bcad524c1856 193 #define RFC_PFILT_WOL_EN 0x00002000 /* Perfect Filter WoL Enable */
DrewSchaef 0:bcad524c1856 194
DrewSchaef 0:bcad524c1856 195 /* Receive Filter WoL Status/Clear Registers */
DrewSchaef 0:bcad524c1856 196 #define WOL_UCAST 0x00000001 /* Unicast Frame caused WoL */
DrewSchaef 0:bcad524c1856 197 #define WOL_BCAST 0x00000002 /* Broadcast Frame caused WoL */
DrewSchaef 0:bcad524c1856 198 #define WOL_MCAST 0x00000004 /* Multicast Frame caused WoL */
DrewSchaef 0:bcad524c1856 199 #define WOL_UCAST_HASH 0x00000008 /* Unicast Hash Filter Frame WoL */
DrewSchaef 0:bcad524c1856 200 #define WOL_MCAST_HASH 0x00000010 /* Multicast Hash Filter Frame WoL */
DrewSchaef 0:bcad524c1856 201 #define WOL_PERFECT 0x00000020 /* Perfect Filter WoL */
DrewSchaef 0:bcad524c1856 202 #define WOL_RX_FILTER 0x00000080 /* RX Filter caused WoL */
DrewSchaef 0:bcad524c1856 203 #define WOL_MAG_PACKET 0x00000100 /* Magic Packet Filter caused WoL */
DrewSchaef 0:bcad524c1856 204
DrewSchaef 0:bcad524c1856 205 /* Interrupt Status/Enable/Clear/Set Registers */
DrewSchaef 0:bcad524c1856 206 #define INT_RX_OVERRUN 0x00000001 /* Overrun Error in RX Queue */
DrewSchaef 0:bcad524c1856 207 #define INT_RX_ERR 0x00000002 /* Receive Error */
DrewSchaef 0:bcad524c1856 208 #define INT_RX_FIN 0x00000004 /* RX Finished Process Descriptors */
DrewSchaef 0:bcad524c1856 209 #define INT_RX_DONE 0x00000008 /* Receive Done */
DrewSchaef 0:bcad524c1856 210 #define INT_TX_UNDERRUN 0x00000010 /* Transmit Underrun */
DrewSchaef 0:bcad524c1856 211 #define INT_TX_ERR 0x00000020 /* Transmit Error */
DrewSchaef 0:bcad524c1856 212 #define INT_TX_FIN 0x00000040 /* TX Finished Process Descriptors */
DrewSchaef 0:bcad524c1856 213 #define INT_TX_DONE 0x00000080 /* Transmit Done */
DrewSchaef 0:bcad524c1856 214 #define INT_SOFT_INT 0x00001000 /* Software Triggered Interrupt */
DrewSchaef 0:bcad524c1856 215 #define INT_WAKEUP 0x00002000 /* Wakeup Event Interrupt */
DrewSchaef 0:bcad524c1856 216
DrewSchaef 0:bcad524c1856 217 /* Power Down Register */
DrewSchaef 0:bcad524c1856 218 #define PD_POWER_DOWN 0x80000000 /* Power Down MAC */
DrewSchaef 0:bcad524c1856 219
DrewSchaef 0:bcad524c1856 220 /* RX Descriptor Control Word */
DrewSchaef 0:bcad524c1856 221 #define RCTRL_SIZE 0x000007FF /* Buffer size mask */
DrewSchaef 0:bcad524c1856 222 #define RCTRL_INT 0x80000000 /* Generate RxDone Interrupt */
DrewSchaef 0:bcad524c1856 223
DrewSchaef 0:bcad524c1856 224 /* RX Status Hash CRC Word */
DrewSchaef 0:bcad524c1856 225 #define RHASH_SA 0x000001FF /* Hash CRC for Source Address */
DrewSchaef 0:bcad524c1856 226 #define RHASH_DA 0x001FF000 /* Hash CRC for Destination Address */
DrewSchaef 0:bcad524c1856 227
DrewSchaef 0:bcad524c1856 228 /* RX Status Information Word */
DrewSchaef 0:bcad524c1856 229 #define RINFO_SIZE 0x000007FF /* Data size in bytes */
DrewSchaef 0:bcad524c1856 230 #define RINFO_CTRL_FRAME 0x00040000 /* Control Frame */
DrewSchaef 0:bcad524c1856 231 #define RINFO_VLAN 0x00080000 /* VLAN Frame */
DrewSchaef 0:bcad524c1856 232 #define RINFO_FAIL_FILT 0x00100000 /* RX Filter Failed */
DrewSchaef 0:bcad524c1856 233 #define RINFO_MCAST 0x00200000 /* Multicast Frame */
DrewSchaef 0:bcad524c1856 234 #define RINFO_BCAST 0x00400000 /* Broadcast Frame */
DrewSchaef 0:bcad524c1856 235 #define RINFO_CRC_ERR 0x00800000 /* CRC Error in Frame */
DrewSchaef 0:bcad524c1856 236 #define RINFO_SYM_ERR 0x01000000 /* Symbol Error from PHY */
DrewSchaef 0:bcad524c1856 237 #define RINFO_LEN_ERR 0x02000000 /* Length Error */
DrewSchaef 0:bcad524c1856 238 #define RINFO_RANGE_ERR 0x04000000 /* Range Error (exceeded max. size) */
DrewSchaef 0:bcad524c1856 239 #define RINFO_ALIGN_ERR 0x08000000 /* Alignment Error */
DrewSchaef 0:bcad524c1856 240 #define RINFO_OVERRUN 0x10000000 /* Receive overrun */
DrewSchaef 0:bcad524c1856 241 #define RINFO_NO_DESCR 0x20000000 /* No new Descriptor available */
DrewSchaef 0:bcad524c1856 242 #define RINFO_LAST_FLAG 0x40000000 /* Last Fragment in Frame */
DrewSchaef 0:bcad524c1856 243 #define RINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */
DrewSchaef 0:bcad524c1856 244
DrewSchaef 0:bcad524c1856 245 #define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_CRC_ERR | RINFO_SYM_ERR | \
DrewSchaef 0:bcad524c1856 246 RINFO_LEN_ERR | RINFO_ALIGN_ERR | RINFO_OVERRUN)
DrewSchaef 0:bcad524c1856 247
DrewSchaef 0:bcad524c1856 248 /* TX Descriptor Control Word */
DrewSchaef 0:bcad524c1856 249 #define TCTRL_SIZE 0x000007FF /* Size of data buffer in bytes */
DrewSchaef 0:bcad524c1856 250 #define TCTRL_OVERRIDE 0x04000000 /* Override Default MAC Registers */
DrewSchaef 0:bcad524c1856 251 #define TCTRL_HUGE 0x08000000 /* Enable Huge Frame */
DrewSchaef 0:bcad524c1856 252 #define TCTRL_PAD 0x10000000 /* Pad short Frames to 64 bytes */
DrewSchaef 0:bcad524c1856 253 #define TCTRL_CRC 0x20000000 /* Append a hardware CRC to Frame */
DrewSchaef 0:bcad524c1856 254 #define TCTRL_LAST 0x40000000 /* Last Descriptor for TX Frame */
DrewSchaef 0:bcad524c1856 255 #define TCTRL_INT 0x80000000 /* Generate TxDone Interrupt */
DrewSchaef 0:bcad524c1856 256
DrewSchaef 0:bcad524c1856 257 /* TX Status Information Word */
DrewSchaef 0:bcad524c1856 258 #define TINFO_COL_CNT 0x01E00000 /* Collision Count */
DrewSchaef 0:bcad524c1856 259 #define TINFO_DEFER 0x02000000 /* Packet Deferred (not an error) */
DrewSchaef 0:bcad524c1856 260 #define TINFO_EXCESS_DEF 0x04000000 /* Excessive Deferral */
DrewSchaef 0:bcad524c1856 261 #define TINFO_EXCESS_COL 0x08000000 /* Excessive Collision */
DrewSchaef 0:bcad524c1856 262 #define TINFO_LATE_COL 0x10000000 /* Late Collision Occured */
DrewSchaef 0:bcad524c1856 263 #define TINFO_UNDERRUN 0x20000000 /* Transmit Underrun */
DrewSchaef 0:bcad524c1856 264 #define TINFO_NO_DESCR 0x40000000 /* No new Descriptor available */
DrewSchaef 0:bcad524c1856 265 #define TINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */
DrewSchaef 0:bcad524c1856 266
DrewSchaef 0:bcad524c1856 267 /* DP83848C PHY Registers */
DrewSchaef 0:bcad524c1856 268 #define PHY_REG_BMCR 0x00 /* Basic Mode Control Register */
DrewSchaef 0:bcad524c1856 269 #define PHY_REG_BMSR 0x01 /* Basic Mode Status Register */
DrewSchaef 0:bcad524c1856 270 #define PHY_REG_IDR1 0x02 /* PHY Identifier 1 */
DrewSchaef 0:bcad524c1856 271 #define PHY_REG_IDR2 0x03 /* PHY Identifier 2 */
DrewSchaef 0:bcad524c1856 272 #define PHY_REG_ANAR 0x04 /* Auto-Negotiation Advertisement */
DrewSchaef 0:bcad524c1856 273 #define PHY_REG_ANLPAR 0x05 /* Auto-Neg. Link Partner Abitily */
DrewSchaef 0:bcad524c1856 274 #define PHY_REG_ANER 0x06 /* Auto-Neg. Expansion Register */
DrewSchaef 0:bcad524c1856 275 #define PHY_REG_ANNPTR 0x07 /* Auto-Neg. Next Page TX */
DrewSchaef 0:bcad524c1856 276
DrewSchaef 0:bcad524c1856 277 /* PHY Extended Registers */
DrewSchaef 0:bcad524c1856 278 #define PHY_REG_STS 0x10 /* Status Register */
DrewSchaef 0:bcad524c1856 279 #define PHY_REG_MICR 0x11 /* MII Interrupt Control Register */
DrewSchaef 0:bcad524c1856 280 #define PHY_REG_MISR 0x12 /* MII Interrupt Status Register */
DrewSchaef 0:bcad524c1856 281 #define PHY_REG_FCSCR 0x14 /* False Carrier Sense Counter */
DrewSchaef 0:bcad524c1856 282 #define PHY_REG_RECR 0x15 /* Receive Error Counter */
DrewSchaef 0:bcad524c1856 283 #define PHY_REG_PCSR 0x16 /* PCS Sublayer Config. and Status */
DrewSchaef 0:bcad524c1856 284 #define PHY_REG_RBR 0x17 /* RMII and Bypass Register */
DrewSchaef 0:bcad524c1856 285 #define PHY_REG_LEDCR 0x18 /* LED Direct Control Register */
DrewSchaef 0:bcad524c1856 286 #define PHY_REG_PHYCR 0x19 /* PHY Control Register */
DrewSchaef 0:bcad524c1856 287 #define PHY_REG_10BTSCR 0x1A /* 10Base-T Status/Control Register */
DrewSchaef 0:bcad524c1856 288 #define PHY_REG_CDCTRL1 0x1B /* CD Test Control and BIST Extens. */
DrewSchaef 0:bcad524c1856 289 #define PHY_REG_EDCR 0x1D /* Energy Detect Control Register */
DrewSchaef 0:bcad524c1856 290
DrewSchaef 0:bcad524c1856 291 #define PHY_FULLD_100M 0x2100 /* Full Duplex 100Mbit */
DrewSchaef 0:bcad524c1856 292 #define PHY_HALFD_100M 0x2000 /* Half Duplex 100Mbit */
DrewSchaef 0:bcad524c1856 293 #define PHY_FULLD_10M 0x0100 /* Full Duplex 10Mbit */
DrewSchaef 0:bcad524c1856 294 #define PHY_HALFD_10M 0x0000 /* Half Duplex 10MBit */
DrewSchaef 0:bcad524c1856 295 #define PHY_AUTO_NEG 0x3000 /* Select Auto Negotiation */
DrewSchaef 0:bcad524c1856 296
DrewSchaef 0:bcad524c1856 297 #define DP83848C_DEF_ADR 0x0100 /* Default PHY device address */
DrewSchaef 0:bcad524c1856 298 #define DP83848C_ID 0x20005C90 /* PHY Identifier */
DrewSchaef 0:bcad524c1856 299 #endif