Krzysztof Sitko / mbed-dev-STM32F031K6

STM32F031K6 Fork of mbed library sources. PLL are disabled for lower clock.

Fork of mbed-dev by mbed official

targets/hal/TARGET_Maxim/TARGET_MAX32610/sleep.c@133:6b577b9a0a7d, 2016-05-31 (annotated)

Committer:
Dot
Date:
Tue May 31 22:46:42 2016 +0000
Revision:
133:6b577b9a0a7d
Parent:
0:9b334a45a8ff 
Forked for F031K6 for UART & I2C

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /*******************************************************************************
bogdanm 0:9b334a45a8ff 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
bogdanm 0:9b334a45a8ff 3 *
bogdanm 0:9b334a45a8ff 4 * Permission is hereby granted, free of charge, to any person obtaining a
bogdanm 0:9b334a45a8ff 5 * copy of this software and associated documentation files (the "Software"),
bogdanm 0:9b334a45a8ff 6 * to deal in the Software without restriction, including without limitation
bogdanm 0:9b334a45a8ff 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
bogdanm 0:9b334a45a8ff 8 * and/or sell copies of the Software, and to permit persons to whom the
bogdanm 0:9b334a45a8ff 9 * Software is furnished to do so, subject to the following conditions:
bogdanm 0:9b334a45a8ff 10 *
bogdanm 0:9b334a45a8ff 11 * The above copyright notice and this permission notice shall be included
bogdanm 0:9b334a45a8ff 12 * in all copies or substantial portions of the Software.
bogdanm 0:9b334a45a8ff 13 *
bogdanm 0:9b334a45a8ff 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
bogdanm 0:9b334a45a8ff 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
bogdanm 0:9b334a45a8ff 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
bogdanm 0:9b334a45a8ff 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
bogdanm 0:9b334a45a8ff 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
bogdanm 0:9b334a45a8ff 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
bogdanm 0:9b334a45a8ff 20 * OTHER DEALINGS IN THE SOFTWARE.
bogdanm 0:9b334a45a8ff 21 *
bogdanm 0:9b334a45a8ff 22 * Except as contained in this notice, the name of Maxim Integrated
bogdanm 0:9b334a45a8ff 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
bogdanm 0:9b334a45a8ff 24 * Products, Inc. Branding Policy.
bogdanm 0:9b334a45a8ff 25 *
bogdanm 0:9b334a45a8ff 26 * The mere transfer of this software does not imply any licenses
bogdanm 0:9b334a45a8ff 27 * of trade secrets, proprietary technology, copyrights, patents,
bogdanm 0:9b334a45a8ff 28 * trademarks, maskwork rights, or any other form of intellectual
bogdanm 0:9b334a45a8ff 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
bogdanm 0:9b334a45a8ff 30 * ownership rights.
bogdanm 0:9b334a45a8ff 31 *******************************************************************************
bogdanm 0:9b334a45a8ff 32 */
bogdanm 0:9b334a45a8ff 33
bogdanm 0:9b334a45a8ff 34 #include "sleep_api.h"
bogdanm 0:9b334a45a8ff 35 #include "cmsis.h"
bogdanm 0:9b334a45a8ff 36 #include "pwrman_regs.h"
bogdanm 0:9b334a45a8ff 37 #include "pwrseq_regs.h"
bogdanm 0:9b334a45a8ff 38 #include "ioman_regs.h"
bogdanm 0:9b334a45a8ff 39 #include "rtc_regs.h"
bogdanm 0:9b334a45a8ff 40
bogdanm 0:9b334a45a8ff 41 static mxc_uart_regs_t *stdio_uart = (mxc_uart_regs_t*)STDIO_UART;
bogdanm 0:9b334a45a8ff 42
bogdanm 0:9b334a45a8ff 43 // Normal wait mode
bogdanm 0:9b334a45a8ff 44 void sleep(void)
bogdanm 0:9b334a45a8ff 45 {
bogdanm 0:9b334a45a8ff 46 // Normal sleep mode for ARM core
bogdanm 0:9b334a45a8ff 47 SCB->SCR = 0;
bogdanm 0:9b334a45a8ff 48
bogdanm 0:9b334a45a8ff 49 __DSB();
bogdanm 0:9b334a45a8ff 50 __WFI();
bogdanm 0:9b334a45a8ff 51 }
bogdanm 0:9b334a45a8ff 52
bogdanm 0:9b334a45a8ff 53 // Work-around for issue of clearing power sequencer I/O flag
bogdanm 0:9b334a45a8ff 54 static void clearAllGPIOWUD(void)
bogdanm 0:9b334a45a8ff 55 {
bogdanm 0:9b334a45a8ff 56 uint32_t wud_req0 = MXC_IOMAN->wud_req0;
bogdanm 0:9b334a45a8ff 57 uint32_t wud_req1 = MXC_IOMAN->wud_req1;
bogdanm 0:9b334a45a8ff 58
bogdanm 0:9b334a45a8ff 59 // I/O must be a wakeup detect to clear
bogdanm 0:9b334a45a8ff 60 MXC_IOMAN->wud_req0 = 0xffffffff;
bogdanm 0:9b334a45a8ff 61 MXC_IOMAN->wud_req1 = 0xffffffff;
bogdanm 0:9b334a45a8ff 62
bogdanm 0:9b334a45a8ff 63 // Clear all WUDs
bogdanm 0:9b334a45a8ff 64 MXC_PWRMAN->wud_ctrl = (MXC_E_PWRMAN_PAD_MODE_CLEAR_SET << MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS) | MXC_F_PWRMAN_WUD_CTRL_CLEAR_ALL;
bogdanm 0:9b334a45a8ff 65 MXC_PWRMAN->wud_pulse0 = 1;
bogdanm 0:9b334a45a8ff 66
bogdanm 0:9b334a45a8ff 67 // Restore WUD requests
bogdanm 0:9b334a45a8ff 68 MXC_IOMAN->wud_req0 = wud_req0;
bogdanm 0:9b334a45a8ff 69 MXC_IOMAN->wud_req1 = wud_req1;
bogdanm 0:9b334a45a8ff 70 }
bogdanm 0:9b334a45a8ff 71
bogdanm 0:9b334a45a8ff 72 // Low-power stop mode
bogdanm 0:9b334a45a8ff 73 void deepsleep(void)
bogdanm 0:9b334a45a8ff 74 {
bogdanm 0:9b334a45a8ff 75 __disable_irq();
bogdanm 0:9b334a45a8ff 76
bogdanm 0:9b334a45a8ff 77 // Wait for all STDIO characters to be sent. The UART clock will stop.
bogdanm 0:9b334a45a8ff 78 while (stdio_uart->status & MXC_F_UART_STATUS_TX_BUSY);
bogdanm 0:9b334a45a8ff 79
bogdanm 0:9b334a45a8ff 80 // Prepare for LP1
bogdanm 0:9b334a45a8ff 81 uint32_t reg0 = MXC_PWRSEQ->reg0;
bogdanm 0:9b334a45a8ff 82 reg0 &= ~MXC_F_PWRSEQ_REG0_PWR_SVM3EN_SLP; // disable VDD3 SVM during sleep mode
bogdanm 0:9b334a45a8ff 83 reg0 &= ~MXC_F_PWRSEQ_REG0_PWR_SVM1EN_SLP; // disable VREG18 SVM during sleep mode
bogdanm 0:9b334a45a8ff 84 if (reg0 & MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN) { // if real-time clock enabled during run
bogdanm 0:9b334a45a8ff 85 reg0 |= MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP; // enable real-time clock during sleep mode
bogdanm 0:9b334a45a8ff 86 } else {
bogdanm 0:9b334a45a8ff 87 reg0 &= ~MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP; // disable real-time clock during sleep mode
bogdanm 0:9b334a45a8ff 88 }
bogdanm 0:9b334a45a8ff 89 reg0 |= MXC_F_PWRSEQ_REG0_PWR_CHZYEN_SLP; // enable CHZY regulator during sleep mode
bogdanm 0:9b334a45a8ff 90 reg0 |= MXC_F_PWRSEQ_REG0_PWR_LP1; // go into LP1
bogdanm 0:9b334a45a8ff 91 reg0 &= ~MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT; // clear first boot flag
bogdanm 0:9b334a45a8ff 92 MXC_PWRSEQ->reg0 = reg0;
bogdanm 0:9b334a45a8ff 93
bogdanm 0:9b334a45a8ff 94 MXC_PWRSEQ->reg3 = (MXC_PWRSEQ->reg3 & ~MXC_F_PWRSEQ_REG3_PWR_ROSEL_QUICK) | (3 << MXC_F_PWRSEQ_REG3_PWR_ROSEL_QUICK_POS);
bogdanm 0:9b334a45a8ff 95
bogdanm 0:9b334a45a8ff 96 // Deep sleep for ARM core
bogdanm 0:9b334a45a8ff 97 SCB->SCR = SCB_SCR_SLEEPDEEP_Msk;
bogdanm 0:9b334a45a8ff 98
bogdanm 0:9b334a45a8ff 99 // clear latches for wakeup detect
bogdanm 0:9b334a45a8ff 100 MXC_PWRSEQ->flags = MXC_PWRSEQ->flags;
bogdanm 0:9b334a45a8ff 101 if (MXC_PWRSEQ->flags & MXC_F_PWRSEQ_FLAGS_PWR_IO_WAKEUP) {
bogdanm 0:9b334a45a8ff 102 // attempt work-around for I/O flag clearing issue
bogdanm 0:9b334a45a8ff 103 clearAllGPIOWUD();
bogdanm 0:9b334a45a8ff 104 MXC_PWRSEQ->flags = MXC_F_PWRSEQ_FLAGS_PWR_IO_WAKEUP;
bogdanm 0:9b334a45a8ff 105 }
bogdanm 0:9b334a45a8ff 106
bogdanm 0:9b334a45a8ff 107 // Wait for pending RTC transaction
bogdanm 0:9b334a45a8ff 108 while (MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING);
bogdanm 0:9b334a45a8ff 109
bogdanm 0:9b334a45a8ff 110 // Ensure that the event register is clear
bogdanm 0:9b334a45a8ff 111 __SEV(); // set event
bogdanm 0:9b334a45a8ff 112 __WFE(); // clear event
bogdanm 0:9b334a45a8ff 113
bogdanm 0:9b334a45a8ff 114 // Enter LP1
bogdanm 0:9b334a45a8ff 115 __WFE();
bogdanm 0:9b334a45a8ff 116 // Woke up from LP1
bogdanm 0:9b334a45a8ff 117
bogdanm 0:9b334a45a8ff 118 // The RTC timer does not update until the next tick
bogdanm 0:9b334a45a8ff 119 uint32_t temp = MXC_RTCTMR->timer;
bogdanm 0:9b334a45a8ff 120 while (MXC_RTCTMR->timer == temp);
bogdanm 0:9b334a45a8ff 121
bogdanm 0:9b334a45a8ff 122 __enable_irq();
bogdanm 0:9b334a45a8ff 123 }