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cmsis/core_cm33.h@174:ed647f63e28d, 2017-12-19 (annotated)

Committer:: Dollyparton
Date:: Tue Dec 19 12:50:13 2017 +0000
Revision:: 174:ed647f63e28d
Parent:: 167:e84263d55307

Added RAW socket.

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	167:e84263d55307	1	/************************************************************************//
AnnaBridge	167:e84263d55307	2	* @file core_cm33.h
AnnaBridge	167:e84263d55307	3	* @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File
AnnaBridge	167:e84263d55307	4	* @version V5.0.2
AnnaBridge	167:e84263d55307	5	* @date 13. February 2017
AnnaBridge	167:e84263d55307	6	******************************************************************************/
AnnaBridge	167:e84263d55307	7	/*
AnnaBridge	167:e84263d55307	8	* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
AnnaBridge	167:e84263d55307	9	*
AnnaBridge	167:e84263d55307	10	* SPDX-License-Identifier: Apache-2.0
AnnaBridge	167:e84263d55307	11	*
AnnaBridge	167:e84263d55307	12	* Licensed under the Apache License, Version 2.0 (the License); you may
AnnaBridge	167:e84263d55307	13	* not use this file except in compliance with the License.
AnnaBridge	167:e84263d55307	14	* You may obtain a copy of the License at
AnnaBridge	167:e84263d55307	15	*
AnnaBridge	167:e84263d55307	16	* www.apache.org/licenses/LICENSE-2.0
AnnaBridge	167:e84263d55307	17	*
AnnaBridge	167:e84263d55307	18	* Unless required by applicable law or agreed to in writing, software
AnnaBridge	167:e84263d55307	19	* distributed under the License is distributed on an AS IS BASIS, WITHOUT
AnnaBridge	167:e84263d55307	20	* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge	167:e84263d55307	21	* See the License for the specific language governing permissions and
AnnaBridge	167:e84263d55307	22	* limitations under the License.
AnnaBridge	167:e84263d55307	23	*/
AnnaBridge	167:e84263d55307	24
AnnaBridge	167:e84263d55307	25	#if defined ( __ICCARM__ )
AnnaBridge	167:e84263d55307	26	#pragma system_include /* treat file as system include file for MISRA check */
AnnaBridge	167:e84263d55307	27	#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge	167:e84263d55307	28	#pragma clang system_header /* treat file as system include file */
AnnaBridge	167:e84263d55307	29	#endif
AnnaBridge	167:e84263d55307	30
AnnaBridge	167:e84263d55307	31	#ifndef __CORE_CM33_H_GENERIC
AnnaBridge	167:e84263d55307	32	#define __CORE_CM33_H_GENERIC
AnnaBridge	167:e84263d55307	33
AnnaBridge	167:e84263d55307	34	#include <stdint.h>
AnnaBridge	167:e84263d55307	35
AnnaBridge	167:e84263d55307	36	#ifdef __cplusplus
AnnaBridge	167:e84263d55307	37	extern "C" {
AnnaBridge	167:e84263d55307	38	#endif
AnnaBridge	167:e84263d55307	39
AnnaBridge	167:e84263d55307	40	/**
AnnaBridge	167:e84263d55307	41	\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
AnnaBridge	167:e84263d55307	42	CMSIS violates the following MISRA-C:2004 rules:
AnnaBridge	167:e84263d55307	43
AnnaBridge	167:e84263d55307	44	\li Required Rule 8.5, object/function definition in header file.<br>
AnnaBridge	167:e84263d55307	45	Function definitions in header files are used to allow 'inlining'.
AnnaBridge	167:e84263d55307	46
AnnaBridge	167:e84263d55307	47	\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
AnnaBridge	167:e84263d55307	48	Unions are used for effective representation of core registers.
AnnaBridge	167:e84263d55307	49
AnnaBridge	167:e84263d55307	50	\li Advisory Rule 19.7, Function-like macro defined.<br>
AnnaBridge	167:e84263d55307	51	Function-like macros are used to allow more efficient code.
AnnaBridge	167:e84263d55307	52	*/
AnnaBridge	167:e84263d55307	53
AnnaBridge	167:e84263d55307	54
AnnaBridge	167:e84263d55307	55	/*******************************************************************************
AnnaBridge	167:e84263d55307	56	* CMSIS definitions
AnnaBridge	167:e84263d55307	57	******************************************************************************/
AnnaBridge	167:e84263d55307	58	/**
AnnaBridge	167:e84263d55307	59	\ingroup Cortex_M33
AnnaBridge	167:e84263d55307	60	@{
AnnaBridge	167:e84263d55307	61	*/
AnnaBridge	167:e84263d55307	62
AnnaBridge	167:e84263d55307	63	/* CMSIS CM33 definitions */
AnnaBridge	167:e84263d55307	64	#define __CM33_CMSIS_VERSION_MAIN ( 5U) /!< [31:16] CMSIS HAL main version /
AnnaBridge	167:e84263d55307	65	#define __CM33_CMSIS_VERSION_SUB ( 0U) /!< [15:0] CMSIS HAL sub version /
AnnaBridge	167:e84263d55307	66	#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) \| \
AnnaBridge	167:e84263d55307	67	__CM33_CMSIS_VERSION_SUB ) /!< CMSIS HAL version number /
AnnaBridge	167:e84263d55307	68
AnnaBridge	167:e84263d55307	69	#define __CORTEX_M (33U) /!< Cortex-M Core /
AnnaBridge	167:e84263d55307	70
AnnaBridge	167:e84263d55307	71	/** __FPU_USED indicates whether an FPU is used or not.
AnnaBridge	167:e84263d55307	72	For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
AnnaBridge	167:e84263d55307	73	*/
AnnaBridge	167:e84263d55307	74	#if defined ( __CC_ARM )
AnnaBridge	167:e84263d55307	75	#if defined __TARGET_FPU_VFP
AnnaBridge	167:e84263d55307	76	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge	167:e84263d55307	77	#define __FPU_USED 1U
AnnaBridge	167:e84263d55307	78	#else
AnnaBridge	167:e84263d55307	79	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	167:e84263d55307	80	#define __FPU_USED 0U
AnnaBridge	167:e84263d55307	81	#endif
AnnaBridge	167:e84263d55307	82	#else
AnnaBridge	167:e84263d55307	83	#define __FPU_USED 0U
AnnaBridge	167:e84263d55307	84	#endif
AnnaBridge	167:e84263d55307	85
AnnaBridge	167:e84263d55307	86	#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge	167:e84263d55307	87	#if defined __ARM_PCS_VFP
AnnaBridge	167:e84263d55307	88	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge	167:e84263d55307	89	#define __FPU_USED 1U
AnnaBridge	167:e84263d55307	90	#else
AnnaBridge	167:e84263d55307	91	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	167:e84263d55307	92	#define __FPU_USED 0U
AnnaBridge	167:e84263d55307	93	#endif
AnnaBridge	167:e84263d55307	94	#else
AnnaBridge	167:e84263d55307	95	#define __FPU_USED 0U
AnnaBridge	167:e84263d55307	96	#endif
AnnaBridge	167:e84263d55307	97
AnnaBridge	167:e84263d55307	98	#elif defined ( __GNUC__ )
AnnaBridge	167:e84263d55307	99	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
AnnaBridge	167:e84263d55307	100	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge	167:e84263d55307	101	#define __FPU_USED 1U
AnnaBridge	167:e84263d55307	102	#else
AnnaBridge	167:e84263d55307	103	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	167:e84263d55307	104	#define __FPU_USED 0U
AnnaBridge	167:e84263d55307	105	#endif
AnnaBridge	167:e84263d55307	106	#else
AnnaBridge	167:e84263d55307	107	#define __FPU_USED 0U
AnnaBridge	167:e84263d55307	108	#endif
AnnaBridge	167:e84263d55307	109
AnnaBridge	167:e84263d55307	110	#elif defined ( __ICCARM__ )
AnnaBridge	167:e84263d55307	111	#if defined __ARMVFP__
AnnaBridge	167:e84263d55307	112	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge	167:e84263d55307	113	#define __FPU_USED 1U
AnnaBridge	167:e84263d55307	114	#else
AnnaBridge	167:e84263d55307	115	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	167:e84263d55307	116	#define __FPU_USED 0U
AnnaBridge	167:e84263d55307	117	#endif
AnnaBridge	167:e84263d55307	118	#else
AnnaBridge	167:e84263d55307	119	#define __FPU_USED 0U
AnnaBridge	167:e84263d55307	120	#endif
AnnaBridge	167:e84263d55307	121
AnnaBridge	167:e84263d55307	122	#elif defined ( __TI_ARM__ )
AnnaBridge	167:e84263d55307	123	#if defined __TI_VFP_SUPPORT__
AnnaBridge	167:e84263d55307	124	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge	167:e84263d55307	125	#define __FPU_USED 1U
AnnaBridge	167:e84263d55307	126	#else
AnnaBridge	167:e84263d55307	127	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	167:e84263d55307	128	#define __FPU_USED 0U
AnnaBridge	167:e84263d55307	129	#endif
AnnaBridge	167:e84263d55307	130	#else
AnnaBridge	167:e84263d55307	131	#define __FPU_USED 0U
AnnaBridge	167:e84263d55307	132	#endif
AnnaBridge	167:e84263d55307	133
AnnaBridge	167:e84263d55307	134	#elif defined ( __TASKING__ )
AnnaBridge	167:e84263d55307	135	#if defined __FPU_VFP__
AnnaBridge	167:e84263d55307	136	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge	167:e84263d55307	137	#define __FPU_USED 1U
AnnaBridge	167:e84263d55307	138	#else
AnnaBridge	167:e84263d55307	139	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	167:e84263d55307	140	#define __FPU_USED 0U
AnnaBridge	167:e84263d55307	141	#endif
AnnaBridge	167:e84263d55307	142	#else
AnnaBridge	167:e84263d55307	143	#define __FPU_USED 0U
AnnaBridge	167:e84263d55307	144	#endif
AnnaBridge	167:e84263d55307	145
AnnaBridge	167:e84263d55307	146	#elif defined ( __CSMC__ )
AnnaBridge	167:e84263d55307	147	#if ( __CSMC__ & 0x400U)
AnnaBridge	167:e84263d55307	148	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge	167:e84263d55307	149	#define __FPU_USED 1U
AnnaBridge	167:e84263d55307	150	#else
AnnaBridge	167:e84263d55307	151	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	167:e84263d55307	152	#define __FPU_USED 0U
AnnaBridge	167:e84263d55307	153	#endif
AnnaBridge	167:e84263d55307	154	#else
AnnaBridge	167:e84263d55307	155	#define __FPU_USED 0U
AnnaBridge	167:e84263d55307	156	#endif
AnnaBridge	167:e84263d55307	157
AnnaBridge	167:e84263d55307	158	#endif
AnnaBridge	167:e84263d55307	159
AnnaBridge	167:e84263d55307	160	#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
AnnaBridge	167:e84263d55307	161
AnnaBridge	167:e84263d55307	162
AnnaBridge	167:e84263d55307	163	#ifdef __cplusplus
AnnaBridge	167:e84263d55307	164	}
AnnaBridge	167:e84263d55307	165	#endif
AnnaBridge	167:e84263d55307	166
AnnaBridge	167:e84263d55307	167	#endif /* __CORE_CM33_H_GENERIC */
AnnaBridge	167:e84263d55307	168
AnnaBridge	167:e84263d55307	169	#ifndef __CMSIS_GENERIC
AnnaBridge	167:e84263d55307	170
AnnaBridge	167:e84263d55307	171	#ifndef __CORE_CM33_H_DEPENDANT
AnnaBridge	167:e84263d55307	172	#define __CORE_CM33_H_DEPENDANT
AnnaBridge	167:e84263d55307	173
AnnaBridge	167:e84263d55307	174	#ifdef __cplusplus
AnnaBridge	167:e84263d55307	175	extern "C" {
AnnaBridge	167:e84263d55307	176	#endif
AnnaBridge	167:e84263d55307	177
AnnaBridge	167:e84263d55307	178	/* check device defines and use defaults */
AnnaBridge	167:e84263d55307	179	#if defined __CHECK_DEVICE_DEFINES
AnnaBridge	167:e84263d55307	180	#ifndef __CM33_REV
AnnaBridge	167:e84263d55307	181	#define __CM33_REV 0x0000U
AnnaBridge	167:e84263d55307	182	#warning "__CM33_REV not defined in device header file; using default!"
AnnaBridge	167:e84263d55307	183	#endif
AnnaBridge	167:e84263d55307	184
AnnaBridge	167:e84263d55307	185	#ifndef __FPU_PRESENT
AnnaBridge	167:e84263d55307	186	#define __FPU_PRESENT 0U
AnnaBridge	167:e84263d55307	187	#warning "__FPU_PRESENT not defined in device header file; using default!"
AnnaBridge	167:e84263d55307	188	#endif
AnnaBridge	167:e84263d55307	189
AnnaBridge	167:e84263d55307	190	#ifndef __MPU_PRESENT
AnnaBridge	167:e84263d55307	191	#define __MPU_PRESENT 0U
AnnaBridge	167:e84263d55307	192	#warning "__MPU_PRESENT not defined in device header file; using default!"
AnnaBridge	167:e84263d55307	193	#endif
AnnaBridge	167:e84263d55307	194
AnnaBridge	167:e84263d55307	195	#ifndef __SAUREGION_PRESENT
AnnaBridge	167:e84263d55307	196	#define __SAUREGION_PRESENT 0U
AnnaBridge	167:e84263d55307	197	#warning "__SAUREGION_PRESENT not defined in device header file; using default!"
AnnaBridge	167:e84263d55307	198	#endif
AnnaBridge	167:e84263d55307	199
AnnaBridge	167:e84263d55307	200	#ifndef __DSP_PRESENT
AnnaBridge	167:e84263d55307	201	#define __DSP_PRESENT 0U
AnnaBridge	167:e84263d55307	202	#warning "__DSP_PRESENT not defined in device header file; using default!"
AnnaBridge	167:e84263d55307	203	#endif
AnnaBridge	167:e84263d55307	204
AnnaBridge	167:e84263d55307	205	#ifndef __NVIC_PRIO_BITS
AnnaBridge	167:e84263d55307	206	#define __NVIC_PRIO_BITS 3U
AnnaBridge	167:e84263d55307	207	#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
AnnaBridge	167:e84263d55307	208	#endif
AnnaBridge	167:e84263d55307	209
AnnaBridge	167:e84263d55307	210	#ifndef __Vendor_SysTickConfig
AnnaBridge	167:e84263d55307	211	#define __Vendor_SysTickConfig 0U
AnnaBridge	167:e84263d55307	212	#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
AnnaBridge	167:e84263d55307	213	#endif
AnnaBridge	167:e84263d55307	214	#endif
AnnaBridge	167:e84263d55307	215
AnnaBridge	167:e84263d55307	216	/* IO definitions (access restrictions to peripheral registers) */
AnnaBridge	167:e84263d55307	217	/**
AnnaBridge	167:e84263d55307	218	\defgroup CMSIS_glob_defs CMSIS Global Defines
AnnaBridge	167:e84263d55307	219
AnnaBridge	167:e84263d55307	220	<strong>IO Type Qualifiers</strong> are used
AnnaBridge	167:e84263d55307	221	\li to specify the access to peripheral variables.
AnnaBridge	167:e84263d55307	222	\li for automatic generation of peripheral register debug information.
AnnaBridge	167:e84263d55307	223	*/
AnnaBridge	167:e84263d55307	224	#ifdef __cplusplus
AnnaBridge	167:e84263d55307	225	#define __I volatile /!< Defines 'read only' permissions /
AnnaBridge	167:e84263d55307	226	#else
AnnaBridge	167:e84263d55307	227	#define __I volatile const /!< Defines 'read only' permissions /
AnnaBridge	167:e84263d55307	228	#endif
AnnaBridge	167:e84263d55307	229	#define __O volatile /!< Defines 'write only' permissions /
AnnaBridge	167:e84263d55307	230	#define __IO volatile /!< Defines 'read / write' permissions /
AnnaBridge	167:e84263d55307	231
AnnaBridge	167:e84263d55307	232	/* following defines should be used for structure members */
AnnaBridge	167:e84263d55307	233	#define __IM volatile const /! Defines 'read only' structure member permissions /
AnnaBridge	167:e84263d55307	234	#define __OM volatile /! Defines 'write only' structure member permissions /
AnnaBridge	167:e84263d55307	235	#define __IOM volatile /! Defines 'read / write' structure member permissions /
AnnaBridge	167:e84263d55307	236
AnnaBridge	167:e84263d55307	237	/@} end of group Cortex_M33 /
AnnaBridge	167:e84263d55307	238
AnnaBridge	167:e84263d55307	239
AnnaBridge	167:e84263d55307	240
AnnaBridge	167:e84263d55307	241	/*******************************************************************************
AnnaBridge	167:e84263d55307	242	* Register Abstraction
AnnaBridge	167:e84263d55307	243	Core Register contain:
AnnaBridge	167:e84263d55307	244	- Core Register
AnnaBridge	167:e84263d55307	245	- Core NVIC Register
AnnaBridge	167:e84263d55307	246	- Core SCB Register
AnnaBridge	167:e84263d55307	247	- Core SysTick Register
AnnaBridge	167:e84263d55307	248	- Core Debug Register
AnnaBridge	167:e84263d55307	249	- Core MPU Register
AnnaBridge	167:e84263d55307	250	- Core SAU Register
AnnaBridge	167:e84263d55307	251	- Core FPU Register
AnnaBridge	167:e84263d55307	252	******************************************************************************/
AnnaBridge	167:e84263d55307	253	/**
AnnaBridge	167:e84263d55307	254	\defgroup CMSIS_core_register Defines and Type Definitions
AnnaBridge	167:e84263d55307	255	\brief Type definitions and defines for Cortex-M processor based devices.
AnnaBridge	167:e84263d55307	256	*/
AnnaBridge	167:e84263d55307	257
AnnaBridge	167:e84263d55307	258	/**
AnnaBridge	167:e84263d55307	259	\ingroup CMSIS_core_register
AnnaBridge	167:e84263d55307	260	\defgroup CMSIS_CORE Status and Control Registers
AnnaBridge	167:e84263d55307	261	\brief Core Register type definitions.
AnnaBridge	167:e84263d55307	262	@{
AnnaBridge	167:e84263d55307	263	*/
AnnaBridge	167:e84263d55307	264
AnnaBridge	167:e84263d55307	265	/**
AnnaBridge	167:e84263d55307	266	\brief Union type to access the Application Program Status Register (APSR).
AnnaBridge	167:e84263d55307	267	*/
AnnaBridge	167:e84263d55307	268	typedef union
AnnaBridge	167:e84263d55307	269	{
AnnaBridge	167:e84263d55307	270	struct
AnnaBridge	167:e84263d55307	271	{
AnnaBridge	167:e84263d55307	272	uint32_t _reserved0:16; /!< bit: 0..15 Reserved /
AnnaBridge	167:e84263d55307	273	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
AnnaBridge	167:e84263d55307	274	uint32_t _reserved1:7; /!< bit: 20..26 Reserved /
AnnaBridge	167:e84263d55307	275	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
AnnaBridge	167:e84263d55307	276	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
AnnaBridge	167:e84263d55307	277	uint32_t C:1; /!< bit: 29 Carry condition code flag /
AnnaBridge	167:e84263d55307	278	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
AnnaBridge	167:e84263d55307	279	uint32_t N:1; /!< bit: 31 Negative condition code flag /
AnnaBridge	167:e84263d55307	280	} b; /!< Structure used for bit access /
AnnaBridge	167:e84263d55307	281	uint32_t w; /!< Type used for word access /
AnnaBridge	167:e84263d55307	282	} APSR_Type;
AnnaBridge	167:e84263d55307	283
AnnaBridge	167:e84263d55307	284	/* APSR Register Definitions */
AnnaBridge	167:e84263d55307	285	#define APSR_N_Pos 31U /!< APSR: N Position /
AnnaBridge	167:e84263d55307	286	#define APSR_N_Msk (1UL << APSR_N_Pos) /!< APSR: N Mask /
AnnaBridge	167:e84263d55307	287
AnnaBridge	167:e84263d55307	288	#define APSR_Z_Pos 30U /!< APSR: Z Position /
AnnaBridge	167:e84263d55307	289	#define APSR_Z_Msk (1UL << APSR_Z_Pos) /!< APSR: Z Mask /
AnnaBridge	167:e84263d55307	290
AnnaBridge	167:e84263d55307	291	#define APSR_C_Pos 29U /!< APSR: C Position /
AnnaBridge	167:e84263d55307	292	#define APSR_C_Msk (1UL << APSR_C_Pos) /!< APSR: C Mask /
AnnaBridge	167:e84263d55307	293
AnnaBridge	167:e84263d55307	294	#define APSR_V_Pos 28U /!< APSR: V Position /
AnnaBridge	167:e84263d55307	295	#define APSR_V_Msk (1UL << APSR_V_Pos) /!< APSR: V Mask /
AnnaBridge	167:e84263d55307	296
AnnaBridge	167:e84263d55307	297	#define APSR_Q_Pos 27U /!< APSR: Q Position /
AnnaBridge	167:e84263d55307	298	#define APSR_Q_Msk (1UL << APSR_Q_Pos) /!< APSR: Q Mask /
AnnaBridge	167:e84263d55307	299
AnnaBridge	167:e84263d55307	300	#define APSR_GE_Pos 16U /!< APSR: GE Position /
AnnaBridge	167:e84263d55307	301	#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /!< APSR: GE Mask /
AnnaBridge	167:e84263d55307	302
AnnaBridge	167:e84263d55307	303
AnnaBridge	167:e84263d55307	304	/**
AnnaBridge	167:e84263d55307	305	\brief Union type to access the Interrupt Program Status Register (IPSR).
AnnaBridge	167:e84263d55307	306	*/
AnnaBridge	167:e84263d55307	307	typedef union
AnnaBridge	167:e84263d55307	308	{
AnnaBridge	167:e84263d55307	309	struct
AnnaBridge	167:e84263d55307	310	{
AnnaBridge	167:e84263d55307	311	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
AnnaBridge	167:e84263d55307	312	uint32_t _reserved0:23; /!< bit: 9..31 Reserved /
AnnaBridge	167:e84263d55307	313	} b; /!< Structure used for bit access /
AnnaBridge	167:e84263d55307	314	uint32_t w; /!< Type used for word access /
AnnaBridge	167:e84263d55307	315	} IPSR_Type;
AnnaBridge	167:e84263d55307	316
AnnaBridge	167:e84263d55307	317	/* IPSR Register Definitions */
AnnaBridge	167:e84263d55307	318	#define IPSR_ISR_Pos 0U /!< IPSR: ISR Position /
AnnaBridge	167:e84263d55307	319	#define IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/) /!< IPSR: ISR Mask /
AnnaBridge	167:e84263d55307	320
AnnaBridge	167:e84263d55307	321
AnnaBridge	167:e84263d55307	322	/**
AnnaBridge	167:e84263d55307	323	\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
AnnaBridge	167:e84263d55307	324	*/
AnnaBridge	167:e84263d55307	325	typedef union
AnnaBridge	167:e84263d55307	326	{
AnnaBridge	167:e84263d55307	327	struct
AnnaBridge	167:e84263d55307	328	{
AnnaBridge	167:e84263d55307	329	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
AnnaBridge	167:e84263d55307	330	uint32_t _reserved0:7; /!< bit: 9..15 Reserved /
AnnaBridge	167:e84263d55307	331	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
AnnaBridge	167:e84263d55307	332	uint32_t _reserved1:4; /!< bit: 20..23 Reserved /
AnnaBridge	167:e84263d55307	333	uint32_t T:1; /!< bit: 24 Thumb bit (read 0) /
AnnaBridge	167:e84263d55307	334	uint32_t IT:2; /!< bit: 25..26 saved IT state (read 0) /
AnnaBridge	167:e84263d55307	335	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
AnnaBridge	167:e84263d55307	336	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
AnnaBridge	167:e84263d55307	337	uint32_t C:1; /!< bit: 29 Carry condition code flag /
AnnaBridge	167:e84263d55307	338	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
AnnaBridge	167:e84263d55307	339	uint32_t N:1; /!< bit: 31 Negative condition code flag /
AnnaBridge	167:e84263d55307	340	} b; /!< Structure used for bit access /
AnnaBridge	167:e84263d55307	341	uint32_t w; /!< Type used for word access /
AnnaBridge	167:e84263d55307	342	} xPSR_Type;
AnnaBridge	167:e84263d55307	343
AnnaBridge	167:e84263d55307	344	/* xPSR Register Definitions */
AnnaBridge	167:e84263d55307	345	#define xPSR_N_Pos 31U /!< xPSR: N Position /
AnnaBridge	167:e84263d55307	346	#define xPSR_N_Msk (1UL << xPSR_N_Pos) /!< xPSR: N Mask /
AnnaBridge	167:e84263d55307	347
AnnaBridge	167:e84263d55307	348	#define xPSR_Z_Pos 30U /!< xPSR: Z Position /
AnnaBridge	167:e84263d55307	349	#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /!< xPSR: Z Mask /
AnnaBridge	167:e84263d55307	350
AnnaBridge	167:e84263d55307	351	#define xPSR_C_Pos 29U /!< xPSR: C Position /
AnnaBridge	167:e84263d55307	352	#define xPSR_C_Msk (1UL << xPSR_C_Pos) /!< xPSR: C Mask /
AnnaBridge	167:e84263d55307	353
AnnaBridge	167:e84263d55307	354	#define xPSR_V_Pos 28U /!< xPSR: V Position /
AnnaBridge	167:e84263d55307	355	#define xPSR_V_Msk (1UL << xPSR_V_Pos) /!< xPSR: V Mask /
AnnaBridge	167:e84263d55307	356
AnnaBridge	167:e84263d55307	357	#define xPSR_Q_Pos 27U /!< xPSR: Q Position /
AnnaBridge	167:e84263d55307	358	#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /!< xPSR: Q Mask /
AnnaBridge	167:e84263d55307	359
AnnaBridge	167:e84263d55307	360	#define xPSR_IT_Pos 25U /!< xPSR: IT Position /
AnnaBridge	167:e84263d55307	361	#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /!< xPSR: IT Mask /
AnnaBridge	167:e84263d55307	362
AnnaBridge	167:e84263d55307	363	#define xPSR_T_Pos 24U /!< xPSR: T Position /
AnnaBridge	167:e84263d55307	364	#define xPSR_T_Msk (1UL << xPSR_T_Pos) /!< xPSR: T Mask /
AnnaBridge	167:e84263d55307	365
AnnaBridge	167:e84263d55307	366	#define xPSR_GE_Pos 16U /!< xPSR: GE Position /
AnnaBridge	167:e84263d55307	367	#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /!< xPSR: GE Mask /
AnnaBridge	167:e84263d55307	368
AnnaBridge	167:e84263d55307	369	#define xPSR_ISR_Pos 0U /!< xPSR: ISR Position /
AnnaBridge	167:e84263d55307	370	#define xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/) /!< xPSR: ISR Mask /
AnnaBridge	167:e84263d55307	371
AnnaBridge	167:e84263d55307	372
AnnaBridge	167:e84263d55307	373	/**
AnnaBridge	167:e84263d55307	374	\brief Union type to access the Control Registers (CONTROL).
AnnaBridge	167:e84263d55307	375	*/
AnnaBridge	167:e84263d55307	376	typedef union
AnnaBridge	167:e84263d55307	377	{
AnnaBridge	167:e84263d55307	378	struct
AnnaBridge	167:e84263d55307	379	{
AnnaBridge	167:e84263d55307	380	uint32_t nPRIV:1; /!< bit: 0 Execution privilege in Thread mode /
AnnaBridge	167:e84263d55307	381	uint32_t SPSEL:1; /!< bit: 1 Stack-pointer select /
AnnaBridge	167:e84263d55307	382	uint32_t FPCA:1; /!< bit: 2 Floating-point context active /
AnnaBridge	167:e84263d55307	383	uint32_t SFPA:1; /!< bit: 3 Secure floating-point active /
AnnaBridge	167:e84263d55307	384	uint32_t _reserved1:28; /!< bit: 4..31 Reserved /
AnnaBridge	167:e84263d55307	385	} b; /!< Structure used for bit access /
AnnaBridge	167:e84263d55307	386	uint32_t w; /!< Type used for word access /
AnnaBridge	167:e84263d55307	387	} CONTROL_Type;
AnnaBridge	167:e84263d55307	388
AnnaBridge	167:e84263d55307	389	/* CONTROL Register Definitions */
AnnaBridge	167:e84263d55307	390	#define CONTROL_SFPA_Pos 3U /!< CONTROL: SFPA Position /
AnnaBridge	167:e84263d55307	391	#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /!< CONTROL: SFPA Mask /
AnnaBridge	167:e84263d55307	392
AnnaBridge	167:e84263d55307	393	#define CONTROL_FPCA_Pos 2U /!< CONTROL: FPCA Position /
AnnaBridge	167:e84263d55307	394	#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /!< CONTROL: FPCA Mask /
AnnaBridge	167:e84263d55307	395
AnnaBridge	167:e84263d55307	396	#define CONTROL_SPSEL_Pos 1U /!< CONTROL: SPSEL Position /
AnnaBridge	167:e84263d55307	397	#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /!< CONTROL: SPSEL Mask /
AnnaBridge	167:e84263d55307	398
AnnaBridge	167:e84263d55307	399	#define CONTROL_nPRIV_Pos 0U /!< CONTROL: nPRIV Position /
AnnaBridge	167:e84263d55307	400	#define CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/) /!< CONTROL: nPRIV Mask /
AnnaBridge	167:e84263d55307	401
AnnaBridge	167:e84263d55307	402	/@} end of group CMSIS_CORE /
AnnaBridge	167:e84263d55307	403
AnnaBridge	167:e84263d55307	404
AnnaBridge	167:e84263d55307	405	/**
AnnaBridge	167:e84263d55307	406	\ingroup CMSIS_core_register
AnnaBridge	167:e84263d55307	407	\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
AnnaBridge	167:e84263d55307	408	\brief Type definitions for the NVIC Registers
AnnaBridge	167:e84263d55307	409	@{
AnnaBridge	167:e84263d55307	410	*/
AnnaBridge	167:e84263d55307	411
AnnaBridge	167:e84263d55307	412	/**
AnnaBridge	167:e84263d55307	413	\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
AnnaBridge	167:e84263d55307	414	*/
AnnaBridge	167:e84263d55307	415	typedef struct
AnnaBridge	167:e84263d55307	416	{
AnnaBridge	167:e84263d55307	417	__IOM uint32_t ISER[16U]; /!< Offset: 0x000 (R/W) Interrupt Set Enable Register /
AnnaBridge	167:e84263d55307	418	uint32_t RESERVED0[16U];
AnnaBridge	167:e84263d55307	419	__IOM uint32_t ICER[16U]; /!< Offset: 0x080 (R/W) Interrupt Clear Enable Register /
AnnaBridge	167:e84263d55307	420	uint32_t RSERVED1[16U];
AnnaBridge	167:e84263d55307	421	__IOM uint32_t ISPR[16U]; /!< Offset: 0x100 (R/W) Interrupt Set Pending Register /
AnnaBridge	167:e84263d55307	422	uint32_t RESERVED2[16U];
AnnaBridge	167:e84263d55307	423	__IOM uint32_t ICPR[16U]; /!< Offset: 0x180 (R/W) Interrupt Clear Pending Register /
AnnaBridge	167:e84263d55307	424	uint32_t RESERVED3[16U];
AnnaBridge	167:e84263d55307	425	__IOM uint32_t IABR[16U]; /!< Offset: 0x200 (R/W) Interrupt Active bit Register /
AnnaBridge	167:e84263d55307	426	uint32_t RESERVED4[16U];
AnnaBridge	167:e84263d55307	427	__IOM uint32_t ITNS[16U]; /!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register /
AnnaBridge	167:e84263d55307	428	uint32_t RESERVED5[16U];
AnnaBridge	167:e84263d55307	429	__IOM uint8_t IPR[496U]; /!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) /
AnnaBridge	167:e84263d55307	430	uint32_t RESERVED6[580U];
AnnaBridge	167:e84263d55307	431	__OM uint32_t STIR; /!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register /
AnnaBridge	167:e84263d55307	432	} NVIC_Type;
AnnaBridge	167:e84263d55307	433
AnnaBridge	167:e84263d55307	434	/* Software Triggered Interrupt Register Definitions */
AnnaBridge	167:e84263d55307	435	#define NVIC_STIR_INTID_Pos 0U /!< STIR: INTLINESNUM Position /
AnnaBridge	167:e84263d55307	436	#define NVIC_STIR_INTID_Msk (0x1FFUL /<< NVIC_STIR_INTID_Pos/) /!< STIR: INTLINESNUM Mask /
AnnaBridge	167:e84263d55307	437
AnnaBridge	167:e84263d55307	438	/@} end of group CMSIS_NVIC /
AnnaBridge	167:e84263d55307	439
AnnaBridge	167:e84263d55307	440
AnnaBridge	167:e84263d55307	441	/**
AnnaBridge	167:e84263d55307	442	\ingroup CMSIS_core_register
AnnaBridge	167:e84263d55307	443	\defgroup CMSIS_SCB System Control Block (SCB)
AnnaBridge	167:e84263d55307	444	\brief Type definitions for the System Control Block Registers
AnnaBridge	167:e84263d55307	445	@{
AnnaBridge	167:e84263d55307	446	*/
AnnaBridge	167:e84263d55307	447
AnnaBridge	167:e84263d55307	448	/**
AnnaBridge	167:e84263d55307	449	\brief Structure type to access the System Control Block (SCB).
AnnaBridge	167:e84263d55307	450	*/
AnnaBridge	167:e84263d55307	451	typedef struct
AnnaBridge	167:e84263d55307	452	{
AnnaBridge	167:e84263d55307	453	__IM uint32_t CPUID; /!< Offset: 0x000 (R/ ) CPUID Base Register /
AnnaBridge	167:e84263d55307	454	__IOM uint32_t ICSR; /!< Offset: 0x004 (R/W) Interrupt Control and State Register /
AnnaBridge	167:e84263d55307	455	__IOM uint32_t VTOR; /!< Offset: 0x008 (R/W) Vector Table Offset Register /
AnnaBridge	167:e84263d55307	456	__IOM uint32_t AIRCR; /!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register /
AnnaBridge	167:e84263d55307	457	__IOM uint32_t SCR; /!< Offset: 0x010 (R/W) System Control Register /
AnnaBridge	167:e84263d55307	458	__IOM uint32_t CCR; /!< Offset: 0x014 (R/W) Configuration Control Register /
AnnaBridge	167:e84263d55307	459	__IOM uint8_t SHPR[12U]; /!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) /
AnnaBridge	167:e84263d55307	460	__IOM uint32_t SHCSR; /!< Offset: 0x024 (R/W) System Handler Control and State Register /
AnnaBridge	167:e84263d55307	461	__IOM uint32_t CFSR; /!< Offset: 0x028 (R/W) Configurable Fault Status Register /
AnnaBridge	167:e84263d55307	462	__IOM uint32_t HFSR; /!< Offset: 0x02C (R/W) HardFault Status Register /
AnnaBridge	167:e84263d55307	463	__IOM uint32_t DFSR; /!< Offset: 0x030 (R/W) Debug Fault Status Register /
AnnaBridge	167:e84263d55307	464	__IOM uint32_t MMFAR; /!< Offset: 0x034 (R/W) MemManage Fault Address Register /
AnnaBridge	167:e84263d55307	465	__IOM uint32_t BFAR; /!< Offset: 0x038 (R/W) BusFault Address Register /
AnnaBridge	167:e84263d55307	466	__IOM uint32_t AFSR; /!< Offset: 0x03C (R/W) Auxiliary Fault Status Register /
AnnaBridge	167:e84263d55307	467	__IM uint32_t ID_PFR[2U]; /!< Offset: 0x040 (R/ ) Processor Feature Register /
AnnaBridge	167:e84263d55307	468	__IM uint32_t ID_DFR; /!< Offset: 0x048 (R/ ) Debug Feature Register /
AnnaBridge	167:e84263d55307	469	__IM uint32_t ID_ADR; /!< Offset: 0x04C (R/ ) Auxiliary Feature Register /
AnnaBridge	167:e84263d55307	470	__IM uint32_t ID_MMFR[4U]; /!< Offset: 0x050 (R/ ) Memory Model Feature Register /
AnnaBridge	167:e84263d55307	471	__IM uint32_t ID_ISAR[6U]; /!< Offset: 0x060 (R/ ) Instruction Set Attributes Register /
AnnaBridge	167:e84263d55307	472	__IM uint32_t CLIDR; /!< Offset: 0x078 (R/ ) Cache Level ID register /
AnnaBridge	167:e84263d55307	473	__IM uint32_t CTR; /!< Offset: 0x07C (R/ ) Cache Type register /
AnnaBridge	167:e84263d55307	474	__IM uint32_t CCSIDR; /!< Offset: 0x080 (R/ ) Cache Size ID Register /
AnnaBridge	167:e84263d55307	475	__IOM uint32_t CSSELR; /!< Offset: 0x084 (R/W) Cache Size Selection Register /
AnnaBridge	167:e84263d55307	476	__IOM uint32_t CPACR; /!< Offset: 0x088 (R/W) Coprocessor Access Control Register /
AnnaBridge	167:e84263d55307	477	__IOM uint32_t NSACR; /!< Offset: 0x08C (R/W) Non-Secure Access Control Register /
AnnaBridge	167:e84263d55307	478	uint32_t RESERVED3[92U];
AnnaBridge	167:e84263d55307	479	__OM uint32_t STIR; /!< Offset: 0x200 ( /W) Software Triggered Interrupt Register /
AnnaBridge	167:e84263d55307	480	uint32_t RESERVED4[15U];
AnnaBridge	167:e84263d55307	481	__IM uint32_t MVFR0; /!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 /
AnnaBridge	167:e84263d55307	482	__IM uint32_t MVFR1; /!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 /
AnnaBridge	167:e84263d55307	483	__IM uint32_t MVFR2; /!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 /
AnnaBridge	167:e84263d55307	484	uint32_t RESERVED5[1U];
AnnaBridge	167:e84263d55307	485	__OM uint32_t ICIALLU; /!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU /
AnnaBridge	167:e84263d55307	486	uint32_t RESERVED6[1U];
AnnaBridge	167:e84263d55307	487	__OM uint32_t ICIMVAU; /!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU /
AnnaBridge	167:e84263d55307	488	__OM uint32_t DCIMVAC; /!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC /
AnnaBridge	167:e84263d55307	489	__OM uint32_t DCISW; /!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way /
AnnaBridge	167:e84263d55307	490	__OM uint32_t DCCMVAU; /!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU /
AnnaBridge	167:e84263d55307	491	__OM uint32_t DCCMVAC; /!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC /
AnnaBridge	167:e84263d55307	492	__OM uint32_t DCCSW; /!< Offset: 0x26C ( /W) D-Cache Clean by Set-way /
AnnaBridge	167:e84263d55307	493	__OM uint32_t DCCIMVAC; /!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC /
AnnaBridge	167:e84263d55307	494	__OM uint32_t DCCISW; /!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way /
AnnaBridge	167:e84263d55307	495	uint32_t RESERVED7[6U];
AnnaBridge	167:e84263d55307	496	__IOM uint32_t ITCMCR; /!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register /
AnnaBridge	167:e84263d55307	497	__IOM uint32_t DTCMCR; /!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers /
AnnaBridge	167:e84263d55307	498	__IOM uint32_t AHBPCR; /!< Offset: 0x298 (R/W) AHBP Control Register /
AnnaBridge	167:e84263d55307	499	__IOM uint32_t CACR; /!< Offset: 0x29C (R/W) L1 Cache Control Register /
AnnaBridge	167:e84263d55307	500	__IOM uint32_t AHBSCR; /!< Offset: 0x2A0 (R/W) AHB Slave Control Register /
AnnaBridge	167:e84263d55307	501	uint32_t RESERVED8[1U];
AnnaBridge	167:e84263d55307	502	__IOM uint32_t ABFSR; /!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register /
AnnaBridge	167:e84263d55307	503	} SCB_Type;
AnnaBridge	167:e84263d55307	504
AnnaBridge	167:e84263d55307	505	/* SCB CPUID Register Definitions */
AnnaBridge	167:e84263d55307	506	#define SCB_CPUID_IMPLEMENTER_Pos 24U /!< SCB CPUID: IMPLEMENTER Position /
AnnaBridge	167:e84263d55307	507	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
AnnaBridge	167:e84263d55307	508
AnnaBridge	167:e84263d55307	509	#define SCB_CPUID_VARIANT_Pos 20U /!< SCB CPUID: VARIANT Position /
AnnaBridge	167:e84263d55307	510	#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
AnnaBridge	167:e84263d55307	511
AnnaBridge	167:e84263d55307	512	#define SCB_CPUID_ARCHITECTURE_Pos 16U /!< SCB CPUID: ARCHITECTURE Position /
AnnaBridge	167:e84263d55307	513	#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /!< SCB CPUID: ARCHITECTURE Mask /
AnnaBridge	167:e84263d55307	514
AnnaBridge	167:e84263d55307	515	#define SCB_CPUID_PARTNO_Pos 4U /!< SCB CPUID: PARTNO Position /
AnnaBridge	167:e84263d55307	516	#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
AnnaBridge	167:e84263d55307	517
AnnaBridge	167:e84263d55307	518	#define SCB_CPUID_REVISION_Pos 0U /!< SCB CPUID: REVISION Position /
AnnaBridge	167:e84263d55307	519	#define SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/) /!< SCB CPUID: REVISION Mask /
AnnaBridge	167:e84263d55307	520
AnnaBridge	167:e84263d55307	521	/* SCB Interrupt Control State Register Definitions */
AnnaBridge	167:e84263d55307	522	#define SCB_ICSR_PENDNMISET_Pos 31U /!< SCB ICSR: PENDNMISET Position /
AnnaBridge	167:e84263d55307	523	#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /!< SCB ICSR: PENDNMISET Mask /
AnnaBridge	167:e84263d55307	524
AnnaBridge	167:e84263d55307	525	#define SCB_ICSR_PENDNMICLR_Pos 30U /!< SCB ICSR: PENDNMICLR Position /
AnnaBridge	167:e84263d55307	526	#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /!< SCB ICSR: PENDNMICLR Mask /
AnnaBridge	167:e84263d55307	527
AnnaBridge	167:e84263d55307	528	#define SCB_ICSR_PENDSVSET_Pos 28U /!< SCB ICSR: PENDSVSET Position /
AnnaBridge	167:e84263d55307	529	#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
AnnaBridge	167:e84263d55307	530
AnnaBridge	167:e84263d55307	531	#define SCB_ICSR_PENDSVCLR_Pos 27U /!< SCB ICSR: PENDSVCLR Position /
AnnaBridge	167:e84263d55307	532	#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
AnnaBridge	167:e84263d55307	533
AnnaBridge	167:e84263d55307	534	#define SCB_ICSR_PENDSTSET_Pos 26U /!< SCB ICSR: PENDSTSET Position /
AnnaBridge	167:e84263d55307	535	#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
AnnaBridge	167:e84263d55307	536
AnnaBridge	167:e84263d55307	537	#define SCB_ICSR_PENDSTCLR_Pos 25U /!< SCB ICSR: PENDSTCLR Position /
AnnaBridge	167:e84263d55307	538	#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
AnnaBridge	167:e84263d55307	539
AnnaBridge	167:e84263d55307	540	#define SCB_ICSR_STTNS_Pos 24U /!< SCB ICSR: STTNS Position (Security Extension) /
AnnaBridge	167:e84263d55307	541	#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /!< SCB ICSR: STTNS Mask (Security Extension) /
AnnaBridge	167:e84263d55307	542
AnnaBridge	167:e84263d55307	543	#define SCB_ICSR_ISRPREEMPT_Pos 23U /!< SCB ICSR: ISRPREEMPT Position /
AnnaBridge	167:e84263d55307	544	#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
AnnaBridge	167:e84263d55307	545
AnnaBridge	167:e84263d55307	546	#define SCB_ICSR_ISRPENDING_Pos 22U /!< SCB ICSR: ISRPENDING Position /
AnnaBridge	167:e84263d55307	547	#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
AnnaBridge	167:e84263d55307	548
AnnaBridge	167:e84263d55307	549	#define SCB_ICSR_VECTPENDING_Pos 12U /!< SCB ICSR: VECTPENDING Position /
AnnaBridge	167:e84263d55307	550	#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
AnnaBridge	167:e84263d55307	551
AnnaBridge	167:e84263d55307	552	#define SCB_ICSR_RETTOBASE_Pos 11U /!< SCB ICSR: RETTOBASE Position /
AnnaBridge	167:e84263d55307	553	#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
AnnaBridge	167:e84263d55307	554
AnnaBridge	167:e84263d55307	555	#define SCB_ICSR_VECTACTIVE_Pos 0U /!< SCB ICSR: VECTACTIVE Position /
AnnaBridge	167:e84263d55307	556	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/) /!< SCB ICSR: VECTACTIVE Mask /
AnnaBridge	167:e84263d55307	557
AnnaBridge	167:e84263d55307	558	/* SCB Vector Table Offset Register Definitions */
AnnaBridge	167:e84263d55307	559	#define SCB_VTOR_TBLOFF_Pos 7U /!< SCB VTOR: TBLOFF Position /
AnnaBridge	167:e84263d55307	560	#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
AnnaBridge	167:e84263d55307	561
AnnaBridge	167:e84263d55307	562	/* SCB Application Interrupt and Reset Control Register Definitions */
AnnaBridge	167:e84263d55307	563	#define SCB_AIRCR_VECTKEY_Pos 16U /!< SCB AIRCR: VECTKEY Position /
AnnaBridge	167:e84263d55307	564	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
AnnaBridge	167:e84263d55307	565
AnnaBridge	167:e84263d55307	566	#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /!< SCB AIRCR: VECTKEYSTAT Position /
AnnaBridge	167:e84263d55307	567	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
AnnaBridge	167:e84263d55307	568
AnnaBridge	167:e84263d55307	569	#define SCB_AIRCR_ENDIANESS_Pos 15U /!< SCB AIRCR: ENDIANESS Position /
AnnaBridge	167:e84263d55307	570	#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
AnnaBridge	167:e84263d55307	571
AnnaBridge	167:e84263d55307	572	#define SCB_AIRCR_PRIS_Pos 14U /!< SCB AIRCR: PRIS Position /
AnnaBridge	167:e84263d55307	573	#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /!< SCB AIRCR: PRIS Mask /
AnnaBridge	167:e84263d55307	574
AnnaBridge	167:e84263d55307	575	#define SCB_AIRCR_BFHFNMINS_Pos 13U /!< SCB AIRCR: BFHFNMINS Position /
AnnaBridge	167:e84263d55307	576	#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /!< SCB AIRCR: BFHFNMINS Mask /
AnnaBridge	167:e84263d55307	577
AnnaBridge	167:e84263d55307	578	#define SCB_AIRCR_PRIGROUP_Pos 8U /!< SCB AIRCR: PRIGROUP Position /
AnnaBridge	167:e84263d55307	579	#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /!< SCB AIRCR: PRIGROUP Mask /
AnnaBridge	167:e84263d55307	580
AnnaBridge	167:e84263d55307	581	#define SCB_AIRCR_SYSRESETREQS_Pos 3U /!< SCB AIRCR: SYSRESETREQS Position /
AnnaBridge	167:e84263d55307	582	#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /!< SCB AIRCR: SYSRESETREQS Mask /
AnnaBridge	167:e84263d55307	583
AnnaBridge	167:e84263d55307	584	#define SCB_AIRCR_SYSRESETREQ_Pos 2U /!< SCB AIRCR: SYSRESETREQ Position /
AnnaBridge	167:e84263d55307	585	#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
AnnaBridge	167:e84263d55307	586
AnnaBridge	167:e84263d55307	587	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /!< SCB AIRCR: VECTCLRACTIVE Position /
AnnaBridge	167:e84263d55307	588	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
AnnaBridge	167:e84263d55307	589
AnnaBridge	167:e84263d55307	590	/* SCB System Control Register Definitions */
AnnaBridge	167:e84263d55307	591	#define SCB_SCR_SEVONPEND_Pos 4U /!< SCB SCR: SEVONPEND Position /
AnnaBridge	167:e84263d55307	592	#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
AnnaBridge	167:e84263d55307	593
AnnaBridge	167:e84263d55307	594	#define SCB_SCR_SLEEPDEEPS_Pos 3U /!< SCB SCR: SLEEPDEEPS Position /
AnnaBridge	167:e84263d55307	595	#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /!< SCB SCR: SLEEPDEEPS Mask /
AnnaBridge	167:e84263d55307	596
AnnaBridge	167:e84263d55307	597	#define SCB_SCR_SLEEPDEEP_Pos 2U /!< SCB SCR: SLEEPDEEP Position /
AnnaBridge	167:e84263d55307	598	#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
AnnaBridge	167:e84263d55307	599
AnnaBridge	167:e84263d55307	600	#define SCB_SCR_SLEEPONEXIT_Pos 1U /!< SCB SCR: SLEEPONEXIT Position /
AnnaBridge	167:e84263d55307	601	#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
AnnaBridge	167:e84263d55307	602
AnnaBridge	167:e84263d55307	603	/* SCB Configuration Control Register Definitions */
AnnaBridge	167:e84263d55307	604	#define SCB_CCR_BP_Pos 18U /!< SCB CCR: BP Position /
AnnaBridge	167:e84263d55307	605	#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /!< SCB CCR: BP Mask /
AnnaBridge	167:e84263d55307	606
AnnaBridge	167:e84263d55307	607	#define SCB_CCR_IC_Pos 17U /!< SCB CCR: IC Position /
AnnaBridge	167:e84263d55307	608	#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /!< SCB CCR: IC Mask /
AnnaBridge	167:e84263d55307	609
AnnaBridge	167:e84263d55307	610	#define SCB_CCR_DC_Pos 16U /!< SCB CCR: DC Position /
AnnaBridge	167:e84263d55307	611	#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /!< SCB CCR: DC Mask /
AnnaBridge	167:e84263d55307	612
AnnaBridge	167:e84263d55307	613	#define SCB_CCR_STKOFHFNMIGN_Pos 10U /!< SCB CCR: STKOFHFNMIGN Position /
AnnaBridge	167:e84263d55307	614	#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /!< SCB CCR: STKOFHFNMIGN Mask /
AnnaBridge	167:e84263d55307	615
AnnaBridge	167:e84263d55307	616	#define SCB_CCR_BFHFNMIGN_Pos 8U /!< SCB CCR: BFHFNMIGN Position /
AnnaBridge	167:e84263d55307	617	#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
AnnaBridge	167:e84263d55307	618
AnnaBridge	167:e84263d55307	619	#define SCB_CCR_DIV_0_TRP_Pos 4U /!< SCB CCR: DIV_0_TRP Position /
AnnaBridge	167:e84263d55307	620	#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
AnnaBridge	167:e84263d55307	621
AnnaBridge	167:e84263d55307	622	#define SCB_CCR_UNALIGN_TRP_Pos 3U /!< SCB CCR: UNALIGN_TRP Position /
AnnaBridge	167:e84263d55307	623	#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
AnnaBridge	167:e84263d55307	624
AnnaBridge	167:e84263d55307	625	#define SCB_CCR_USERSETMPEND_Pos 1U /!< SCB CCR: USERSETMPEND Position /
AnnaBridge	167:e84263d55307	626	#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
AnnaBridge	167:e84263d55307	627
AnnaBridge	167:e84263d55307	628	/* SCB System Handler Control and State Register Definitions */
AnnaBridge	167:e84263d55307	629	#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /!< SCB SHCSR: HARDFAULTPENDED Position /
AnnaBridge	167:e84263d55307	630	#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /!< SCB SHCSR: HARDFAULTPENDED Mask /
AnnaBridge	167:e84263d55307	631
AnnaBridge	167:e84263d55307	632	#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /!< SCB SHCSR: SECUREFAULTPENDED Position /
AnnaBridge	167:e84263d55307	633	#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /!< SCB SHCSR: SECUREFAULTPENDED Mask /
AnnaBridge	167:e84263d55307	634
AnnaBridge	167:e84263d55307	635	#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /!< SCB SHCSR: SECUREFAULTENA Position /
AnnaBridge	167:e84263d55307	636	#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /!< SCB SHCSR: SECUREFAULTENA Mask /
AnnaBridge	167:e84263d55307	637
AnnaBridge	167:e84263d55307	638	#define SCB_SHCSR_USGFAULTENA_Pos 18U /!< SCB SHCSR: USGFAULTENA Position /
AnnaBridge	167:e84263d55307	639	#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /!< SCB SHCSR: USGFAULTENA Mask /
AnnaBridge	167:e84263d55307	640
AnnaBridge	167:e84263d55307	641	#define SCB_SHCSR_BUSFAULTENA_Pos 17U /!< SCB SHCSR: BUSFAULTENA Position /
AnnaBridge	167:e84263d55307	642	#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /!< SCB SHCSR: BUSFAULTENA Mask /
AnnaBridge	167:e84263d55307	643
AnnaBridge	167:e84263d55307	644	#define SCB_SHCSR_MEMFAULTENA_Pos 16U /!< SCB SHCSR: MEMFAULTENA Position /
AnnaBridge	167:e84263d55307	645	#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /!< SCB SHCSR: MEMFAULTENA Mask /
AnnaBridge	167:e84263d55307	646
AnnaBridge	167:e84263d55307	647	#define SCB_SHCSR_SVCALLPENDED_Pos 15U /!< SCB SHCSR: SVCALLPENDED Position /
AnnaBridge	167:e84263d55307	648	#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
AnnaBridge	167:e84263d55307	649
AnnaBridge	167:e84263d55307	650	#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /!< SCB SHCSR: BUSFAULTPENDED Position /
AnnaBridge	167:e84263d55307	651	#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /!< SCB SHCSR: BUSFAULTPENDED Mask /
AnnaBridge	167:e84263d55307	652
AnnaBridge	167:e84263d55307	653	#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /!< SCB SHCSR: MEMFAULTPENDED Position /
AnnaBridge	167:e84263d55307	654	#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /!< SCB SHCSR: MEMFAULTPENDED Mask /
AnnaBridge	167:e84263d55307	655
AnnaBridge	167:e84263d55307	656	#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /!< SCB SHCSR: USGFAULTPENDED Position /
AnnaBridge	167:e84263d55307	657	#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /!< SCB SHCSR: USGFAULTPENDED Mask /
AnnaBridge	167:e84263d55307	658
AnnaBridge	167:e84263d55307	659	#define SCB_SHCSR_SYSTICKACT_Pos 11U /!< SCB SHCSR: SYSTICKACT Position /
AnnaBridge	167:e84263d55307	660	#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
AnnaBridge	167:e84263d55307	661
AnnaBridge	167:e84263d55307	662	#define SCB_SHCSR_PENDSVACT_Pos 10U /!< SCB SHCSR: PENDSVACT Position /
AnnaBridge	167:e84263d55307	663	#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
AnnaBridge	167:e84263d55307	664
AnnaBridge	167:e84263d55307	665	#define SCB_SHCSR_MONITORACT_Pos 8U /!< SCB SHCSR: MONITORACT Position /
AnnaBridge	167:e84263d55307	666	#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /!< SCB SHCSR: MONITORACT Mask /
AnnaBridge	167:e84263d55307	667
AnnaBridge	167:e84263d55307	668	#define SCB_SHCSR_SVCALLACT_Pos 7U /!< SCB SHCSR: SVCALLACT Position /
AnnaBridge	167:e84263d55307	669	#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
AnnaBridge	167:e84263d55307	670
AnnaBridge	167:e84263d55307	671	#define SCB_SHCSR_NMIACT_Pos 5U /!< SCB SHCSR: NMIACT Position /
AnnaBridge	167:e84263d55307	672	#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /!< SCB SHCSR: NMIACT Mask /
AnnaBridge	167:e84263d55307	673
AnnaBridge	167:e84263d55307	674	#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /!< SCB SHCSR: SECUREFAULTACT Position /
AnnaBridge	167:e84263d55307	675	#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /!< SCB SHCSR: SECUREFAULTACT Mask /
AnnaBridge	167:e84263d55307	676
AnnaBridge	167:e84263d55307	677	#define SCB_SHCSR_USGFAULTACT_Pos 3U /!< SCB SHCSR: USGFAULTACT Position /
AnnaBridge	167:e84263d55307	678	#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /!< SCB SHCSR: USGFAULTACT Mask /
AnnaBridge	167:e84263d55307	679
AnnaBridge	167:e84263d55307	680	#define SCB_SHCSR_HARDFAULTACT_Pos 2U /!< SCB SHCSR: HARDFAULTACT Position /
AnnaBridge	167:e84263d55307	681	#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /!< SCB SHCSR: HARDFAULTACT Mask /
AnnaBridge	167:e84263d55307	682
AnnaBridge	167:e84263d55307	683	#define SCB_SHCSR_BUSFAULTACT_Pos 1U /!< SCB SHCSR: BUSFAULTACT Position /
AnnaBridge	167:e84263d55307	684	#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /!< SCB SHCSR: BUSFAULTACT Mask /
AnnaBridge	167:e84263d55307	685
AnnaBridge	167:e84263d55307	686	#define SCB_SHCSR_MEMFAULTACT_Pos 0U /!< SCB SHCSR: MEMFAULTACT Position /
AnnaBridge	167:e84263d55307	687	#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /<< SCB_SHCSR_MEMFAULTACT_Pos/) /!< SCB SHCSR: MEMFAULTACT Mask /
AnnaBridge	167:e84263d55307	688
AnnaBridge	167:e84263d55307	689	/* SCB Configurable Fault Status Register Definitions */
AnnaBridge	167:e84263d55307	690	#define SCB_CFSR_USGFAULTSR_Pos 16U /!< SCB CFSR: Usage Fault Status Register Position /
AnnaBridge	167:e84263d55307	691	#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /!< SCB CFSR: Usage Fault Status Register Mask /
AnnaBridge	167:e84263d55307	692
AnnaBridge	167:e84263d55307	693	#define SCB_CFSR_BUSFAULTSR_Pos 8U /!< SCB CFSR: Bus Fault Status Register Position /
AnnaBridge	167:e84263d55307	694	#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /!< SCB CFSR: Bus Fault Status Register Mask /
AnnaBridge	167:e84263d55307	695
AnnaBridge	167:e84263d55307	696	#define SCB_CFSR_MEMFAULTSR_Pos 0U /!< SCB CFSR: Memory Manage Fault Status Register Position /
AnnaBridge	167:e84263d55307	697	#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /<< SCB_CFSR_MEMFAULTSR_Pos/) /!< SCB CFSR: Memory Manage Fault Status Register Mask /
AnnaBridge	167:e84263d55307	698
AnnaBridge	167:e84263d55307	699	/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
AnnaBridge	167:e84263d55307	700	#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /!< SCB CFSR (MMFSR): MMARVALID Position /
AnnaBridge	167:e84263d55307	701	#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /!< SCB CFSR (MMFSR): MMARVALID Mask /
AnnaBridge	167:e84263d55307	702
AnnaBridge	167:e84263d55307	703	#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /!< SCB CFSR (MMFSR): MLSPERR Position /
AnnaBridge	167:e84263d55307	704	#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /!< SCB CFSR (MMFSR): MLSPERR Mask /
AnnaBridge	167:e84263d55307	705
AnnaBridge	167:e84263d55307	706	#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /!< SCB CFSR (MMFSR): MSTKERR Position /
AnnaBridge	167:e84263d55307	707	#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /!< SCB CFSR (MMFSR): MSTKERR Mask /
AnnaBridge	167:e84263d55307	708
AnnaBridge	167:e84263d55307	709	#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /!< SCB CFSR (MMFSR): MUNSTKERR Position /
AnnaBridge	167:e84263d55307	710	#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /!< SCB CFSR (MMFSR): MUNSTKERR Mask /
AnnaBridge	167:e84263d55307	711
AnnaBridge	167:e84263d55307	712	#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /!< SCB CFSR (MMFSR): DACCVIOL Position /
AnnaBridge	167:e84263d55307	713	#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /!< SCB CFSR (MMFSR): DACCVIOL Mask /
AnnaBridge	167:e84263d55307	714
AnnaBridge	167:e84263d55307	715	#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /!< SCB CFSR (MMFSR): IACCVIOL Position /
AnnaBridge	167:e84263d55307	716	#define SCB_CFSR_IACCVIOL_Msk (1UL /<< SCB_CFSR_IACCVIOL_Pos/) /!< SCB CFSR (MMFSR): IACCVIOL Mask /
AnnaBridge	167:e84263d55307	717
AnnaBridge	167:e84263d55307	718	/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
AnnaBridge	167:e84263d55307	719	#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /!< SCB CFSR (BFSR): BFARVALID Position /
AnnaBridge	167:e84263d55307	720	#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /!< SCB CFSR (BFSR): BFARVALID Mask /
AnnaBridge	167:e84263d55307	721
AnnaBridge	167:e84263d55307	722	#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /!< SCB CFSR (BFSR): LSPERR Position /
AnnaBridge	167:e84263d55307	723	#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /!< SCB CFSR (BFSR): LSPERR Mask /
AnnaBridge	167:e84263d55307	724
AnnaBridge	167:e84263d55307	725	#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /!< SCB CFSR (BFSR): STKERR Position /
AnnaBridge	167:e84263d55307	726	#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /!< SCB CFSR (BFSR): STKERR Mask /
AnnaBridge	167:e84263d55307	727
AnnaBridge	167:e84263d55307	728	#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /!< SCB CFSR (BFSR): UNSTKERR Position /
AnnaBridge	167:e84263d55307	729	#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /!< SCB CFSR (BFSR): UNSTKERR Mask /
AnnaBridge	167:e84263d55307	730
AnnaBridge	167:e84263d55307	731	#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /!< SCB CFSR (BFSR): IMPRECISERR Position /
AnnaBridge	167:e84263d55307	732	#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /!< SCB CFSR (BFSR): IMPRECISERR Mask /
AnnaBridge	167:e84263d55307	733
AnnaBridge	167:e84263d55307	734	#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /!< SCB CFSR (BFSR): PRECISERR Position /
AnnaBridge	167:e84263d55307	735	#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /!< SCB CFSR (BFSR): PRECISERR Mask /
AnnaBridge	167:e84263d55307	736
AnnaBridge	167:e84263d55307	737	#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /!< SCB CFSR (BFSR): IBUSERR Position /
AnnaBridge	167:e84263d55307	738	#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /!< SCB CFSR (BFSR): IBUSERR Mask /
AnnaBridge	167:e84263d55307	739
AnnaBridge	167:e84263d55307	740	/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
AnnaBridge	167:e84263d55307	741	#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /!< SCB CFSR (UFSR): DIVBYZERO Position /
AnnaBridge	167:e84263d55307	742	#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /!< SCB CFSR (UFSR): DIVBYZERO Mask /
AnnaBridge	167:e84263d55307	743
AnnaBridge	167:e84263d55307	744	#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /!< SCB CFSR (UFSR): UNALIGNED Position /
AnnaBridge	167:e84263d55307	745	#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /!< SCB CFSR (UFSR): UNALIGNED Mask /
AnnaBridge	167:e84263d55307	746
AnnaBridge	167:e84263d55307	747	#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /!< SCB CFSR (UFSR): STKOF Position /
AnnaBridge	167:e84263d55307	748	#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /!< SCB CFSR (UFSR): STKOF Mask /
AnnaBridge	167:e84263d55307	749
AnnaBridge	167:e84263d55307	750	#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /!< SCB CFSR (UFSR): NOCP Position /
AnnaBridge	167:e84263d55307	751	#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /!< SCB CFSR (UFSR): NOCP Mask /
AnnaBridge	167:e84263d55307	752
AnnaBridge	167:e84263d55307	753	#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /!< SCB CFSR (UFSR): INVPC Position /
AnnaBridge	167:e84263d55307	754	#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /!< SCB CFSR (UFSR): INVPC Mask /
AnnaBridge	167:e84263d55307	755
AnnaBridge	167:e84263d55307	756	#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /!< SCB CFSR (UFSR): INVSTATE Position /
AnnaBridge	167:e84263d55307	757	#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /!< SCB CFSR (UFSR): INVSTATE Mask /
AnnaBridge	167:e84263d55307	758
AnnaBridge	167:e84263d55307	759	#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /!< SCB CFSR (UFSR): UNDEFINSTR Position /
AnnaBridge	167:e84263d55307	760	#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /!< SCB CFSR (UFSR): UNDEFINSTR Mask /
AnnaBridge	167:e84263d55307	761
AnnaBridge	167:e84263d55307	762	/* SCB Hard Fault Status Register Definitions */
AnnaBridge	167:e84263d55307	763	#define SCB_HFSR_DEBUGEVT_Pos 31U /!< SCB HFSR: DEBUGEVT Position /
AnnaBridge	167:e84263d55307	764	#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /!< SCB HFSR: DEBUGEVT Mask /
AnnaBridge	167:e84263d55307	765
AnnaBridge	167:e84263d55307	766	#define SCB_HFSR_FORCED_Pos 30U /!< SCB HFSR: FORCED Position /
AnnaBridge	167:e84263d55307	767	#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /!< SCB HFSR: FORCED Mask /
AnnaBridge	167:e84263d55307	768
AnnaBridge	167:e84263d55307	769	#define SCB_HFSR_VECTTBL_Pos 1U /!< SCB HFSR: VECTTBL Position /
AnnaBridge	167:e84263d55307	770	#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /!< SCB HFSR: VECTTBL Mask /
AnnaBridge	167:e84263d55307	771
AnnaBridge	167:e84263d55307	772	/* SCB Debug Fault Status Register Definitions */
AnnaBridge	167:e84263d55307	773	#define SCB_DFSR_EXTERNAL_Pos 4U /!< SCB DFSR: EXTERNAL Position /
AnnaBridge	167:e84263d55307	774	#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /!< SCB DFSR: EXTERNAL Mask /
AnnaBridge	167:e84263d55307	775
AnnaBridge	167:e84263d55307	776	#define SCB_DFSR_VCATCH_Pos 3U /!< SCB DFSR: VCATCH Position /
AnnaBridge	167:e84263d55307	777	#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /!< SCB DFSR: VCATCH Mask /
AnnaBridge	167:e84263d55307	778
AnnaBridge	167:e84263d55307	779	#define SCB_DFSR_DWTTRAP_Pos 2U /!< SCB DFSR: DWTTRAP Position /
AnnaBridge	167:e84263d55307	780	#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /!< SCB DFSR: DWTTRAP Mask /
AnnaBridge	167:e84263d55307	781
AnnaBridge	167:e84263d55307	782	#define SCB_DFSR_BKPT_Pos 1U /!< SCB DFSR: BKPT Position /
AnnaBridge	167:e84263d55307	783	#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /!< SCB DFSR: BKPT Mask /
AnnaBridge	167:e84263d55307	784
AnnaBridge	167:e84263d55307	785	#define SCB_DFSR_HALTED_Pos 0U /!< SCB DFSR: HALTED Position /
AnnaBridge	167:e84263d55307	786	#define SCB_DFSR_HALTED_Msk (1UL /<< SCB_DFSR_HALTED_Pos/) /!< SCB DFSR: HALTED Mask /
AnnaBridge	167:e84263d55307	787
AnnaBridge	167:e84263d55307	788	/* SCB Non-Secure Access Control Register Definitions */
AnnaBridge	167:e84263d55307	789	#define SCB_NSACR_CP11_Pos 11U /!< SCB NSACR: CP11 Position /
AnnaBridge	167:e84263d55307	790	#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /!< SCB NSACR: CP11 Mask /
AnnaBridge	167:e84263d55307	791
AnnaBridge	167:e84263d55307	792	#define SCB_NSACR_CP10_Pos 10U /!< SCB NSACR: CP10 Position /
AnnaBridge	167:e84263d55307	793	#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /!< SCB NSACR: CP10 Mask /
AnnaBridge	167:e84263d55307	794
AnnaBridge	167:e84263d55307	795	#define SCB_NSACR_CPn_Pos 0U /!< SCB NSACR: CPn Position /
AnnaBridge	167:e84263d55307	796	#define SCB_NSACR_CPn_Msk (1UL /<< SCB_NSACR_CPn_Pos/) /!< SCB NSACR: CPn Mask /
AnnaBridge	167:e84263d55307	797
AnnaBridge	167:e84263d55307	798	/* SCB Cache Level ID Register Definitions */
AnnaBridge	167:e84263d55307	799	#define SCB_CLIDR_LOUU_Pos 27U /!< SCB CLIDR: LoUU Position /
AnnaBridge	167:e84263d55307	800	#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /!< SCB CLIDR: LoUU Mask /
AnnaBridge	167:e84263d55307	801
AnnaBridge	167:e84263d55307	802	#define SCB_CLIDR_LOC_Pos 24U /!< SCB CLIDR: LoC Position /
AnnaBridge	167:e84263d55307	803	#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /!< SCB CLIDR: LoC Mask /
AnnaBridge	167:e84263d55307	804
AnnaBridge	167:e84263d55307	805	/* SCB Cache Type Register Definitions */
AnnaBridge	167:e84263d55307	806	#define SCB_CTR_FORMAT_Pos 29U /!< SCB CTR: Format Position /
AnnaBridge	167:e84263d55307	807	#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /!< SCB CTR: Format Mask /
AnnaBridge	167:e84263d55307	808
AnnaBridge	167:e84263d55307	809	#define SCB_CTR_CWG_Pos 24U /!< SCB CTR: CWG Position /
AnnaBridge	167:e84263d55307	810	#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /!< SCB CTR: CWG Mask /
AnnaBridge	167:e84263d55307	811
AnnaBridge	167:e84263d55307	812	#define SCB_CTR_ERG_Pos 20U /!< SCB CTR: ERG Position /
AnnaBridge	167:e84263d55307	813	#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /!< SCB CTR: ERG Mask /
AnnaBridge	167:e84263d55307	814
AnnaBridge	167:e84263d55307	815	#define SCB_CTR_DMINLINE_Pos 16U /!< SCB CTR: DminLine Position /
AnnaBridge	167:e84263d55307	816	#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /!< SCB CTR: DminLine Mask /
AnnaBridge	167:e84263d55307	817
AnnaBridge	167:e84263d55307	818	#define SCB_CTR_IMINLINE_Pos 0U /!< SCB CTR: ImInLine Position /
AnnaBridge	167:e84263d55307	819	#define SCB_CTR_IMINLINE_Msk (0xFUL /<< SCB_CTR_IMINLINE_Pos/) /!< SCB CTR: ImInLine Mask /
AnnaBridge	167:e84263d55307	820
AnnaBridge	167:e84263d55307	821	/* SCB Cache Size ID Register Definitions */
AnnaBridge	167:e84263d55307	822	#define SCB_CCSIDR_WT_Pos 31U /!< SCB CCSIDR: WT Position /
AnnaBridge	167:e84263d55307	823	#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /!< SCB CCSIDR: WT Mask /
AnnaBridge	167:e84263d55307	824
AnnaBridge	167:e84263d55307	825	#define SCB_CCSIDR_WB_Pos 30U /!< SCB CCSIDR: WB Position /
AnnaBridge	167:e84263d55307	826	#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /!< SCB CCSIDR: WB Mask /
AnnaBridge	167:e84263d55307	827
AnnaBridge	167:e84263d55307	828	#define SCB_CCSIDR_RA_Pos 29U /!< SCB CCSIDR: RA Position /
AnnaBridge	167:e84263d55307	829	#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /!< SCB CCSIDR: RA Mask /
AnnaBridge	167:e84263d55307	830
AnnaBridge	167:e84263d55307	831	#define SCB_CCSIDR_WA_Pos 28U /!< SCB CCSIDR: WA Position /
AnnaBridge	167:e84263d55307	832	#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /!< SCB CCSIDR: WA Mask /
AnnaBridge	167:e84263d55307	833
AnnaBridge	167:e84263d55307	834	#define SCB_CCSIDR_NUMSETS_Pos 13U /!< SCB CCSIDR: NumSets Position /
AnnaBridge	167:e84263d55307	835	#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /!< SCB CCSIDR: NumSets Mask /
AnnaBridge	167:e84263d55307	836
AnnaBridge	167:e84263d55307	837	#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /!< SCB CCSIDR: Associativity Position /
AnnaBridge	167:e84263d55307	838	#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /!< SCB CCSIDR: Associativity Mask /
AnnaBridge	167:e84263d55307	839
AnnaBridge	167:e84263d55307	840	#define SCB_CCSIDR_LINESIZE_Pos 0U /!< SCB CCSIDR: LineSize Position /
AnnaBridge	167:e84263d55307	841	#define SCB_CCSIDR_LINESIZE_Msk (7UL /<< SCB_CCSIDR_LINESIZE_Pos/) /!< SCB CCSIDR: LineSize Mask /
AnnaBridge	167:e84263d55307	842
AnnaBridge	167:e84263d55307	843	/* SCB Cache Size Selection Register Definitions */
AnnaBridge	167:e84263d55307	844	#define SCB_CSSELR_LEVEL_Pos 1U /!< SCB CSSELR: Level Position /
AnnaBridge	167:e84263d55307	845	#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /!< SCB CSSELR: Level Mask /
AnnaBridge	167:e84263d55307	846
AnnaBridge	167:e84263d55307	847	#define SCB_CSSELR_IND_Pos 0U /!< SCB CSSELR: InD Position /
AnnaBridge	167:e84263d55307	848	#define SCB_CSSELR_IND_Msk (1UL /<< SCB_CSSELR_IND_Pos/) /!< SCB CSSELR: InD Mask /
AnnaBridge	167:e84263d55307	849
AnnaBridge	167:e84263d55307	850	/* SCB Software Triggered Interrupt Register Definitions */
AnnaBridge	167:e84263d55307	851	#define SCB_STIR_INTID_Pos 0U /!< SCB STIR: INTID Position /
AnnaBridge	167:e84263d55307	852	#define SCB_STIR_INTID_Msk (0x1FFUL /<< SCB_STIR_INTID_Pos/) /!< SCB STIR: INTID Mask /
AnnaBridge	167:e84263d55307	853
AnnaBridge	167:e84263d55307	854	/* SCB D-Cache Invalidate by Set-way Register Definitions */
AnnaBridge	167:e84263d55307	855	#define SCB_DCISW_WAY_Pos 30U /!< SCB DCISW: Way Position /
AnnaBridge	167:e84263d55307	856	#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /!< SCB DCISW: Way Mask /
AnnaBridge	167:e84263d55307	857
AnnaBridge	167:e84263d55307	858	#define SCB_DCISW_SET_Pos 5U /!< SCB DCISW: Set Position /
AnnaBridge	167:e84263d55307	859	#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /!< SCB DCISW: Set Mask /
AnnaBridge	167:e84263d55307	860
AnnaBridge	167:e84263d55307	861	/* SCB D-Cache Clean by Set-way Register Definitions */
AnnaBridge	167:e84263d55307	862	#define SCB_DCCSW_WAY_Pos 30U /!< SCB DCCSW: Way Position /
AnnaBridge	167:e84263d55307	863	#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /!< SCB DCCSW: Way Mask /
AnnaBridge	167:e84263d55307	864
AnnaBridge	167:e84263d55307	865	#define SCB_DCCSW_SET_Pos 5U /!< SCB DCCSW: Set Position /
AnnaBridge	167:e84263d55307	866	#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /!< SCB DCCSW: Set Mask /
AnnaBridge	167:e84263d55307	867
AnnaBridge	167:e84263d55307	868	/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
AnnaBridge	167:e84263d55307	869	#define SCB_DCCISW_WAY_Pos 30U /!< SCB DCCISW: Way Position /
AnnaBridge	167:e84263d55307	870	#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /!< SCB DCCISW: Way Mask /
AnnaBridge	167:e84263d55307	871
AnnaBridge	167:e84263d55307	872	#define SCB_DCCISW_SET_Pos 5U /!< SCB DCCISW: Set Position /
AnnaBridge	167:e84263d55307	873	#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /!< SCB DCCISW: Set Mask /
AnnaBridge	167:e84263d55307	874
AnnaBridge	167:e84263d55307	875	/* Instruction Tightly-Coupled Memory Control Register Definitions */
AnnaBridge	167:e84263d55307	876	#define SCB_ITCMCR_SZ_Pos 3U /!< SCB ITCMCR: SZ Position /
AnnaBridge	167:e84263d55307	877	#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /!< SCB ITCMCR: SZ Mask /
AnnaBridge	167:e84263d55307	878
AnnaBridge	167:e84263d55307	879	#define SCB_ITCMCR_RETEN_Pos 2U /!< SCB ITCMCR: RETEN Position /
AnnaBridge	167:e84263d55307	880	#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /!< SCB ITCMCR: RETEN Mask /
AnnaBridge	167:e84263d55307	881
AnnaBridge	167:e84263d55307	882	#define SCB_ITCMCR_RMW_Pos 1U /!< SCB ITCMCR: RMW Position /
AnnaBridge	167:e84263d55307	883	#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /!< SCB ITCMCR: RMW Mask /
AnnaBridge	167:e84263d55307	884
AnnaBridge	167:e84263d55307	885	#define SCB_ITCMCR_EN_Pos 0U /!< SCB ITCMCR: EN Position /
AnnaBridge	167:e84263d55307	886	#define SCB_ITCMCR_EN_Msk (1UL /<< SCB_ITCMCR_EN_Pos/) /!< SCB ITCMCR: EN Mask /
AnnaBridge	167:e84263d55307	887
AnnaBridge	167:e84263d55307	888	/* Data Tightly-Coupled Memory Control Register Definitions */
AnnaBridge	167:e84263d55307	889	#define SCB_DTCMCR_SZ_Pos 3U /!< SCB DTCMCR: SZ Position /
AnnaBridge	167:e84263d55307	890	#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /!< SCB DTCMCR: SZ Mask /
AnnaBridge	167:e84263d55307	891
AnnaBridge	167:e84263d55307	892	#define SCB_DTCMCR_RETEN_Pos 2U /!< SCB DTCMCR: RETEN Position /
AnnaBridge	167:e84263d55307	893	#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /!< SCB DTCMCR: RETEN Mask /
AnnaBridge	167:e84263d55307	894
AnnaBridge	167:e84263d55307	895	#define SCB_DTCMCR_RMW_Pos 1U /!< SCB DTCMCR: RMW Position /
AnnaBridge	167:e84263d55307	896	#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /!< SCB DTCMCR: RMW Mask /
AnnaBridge	167:e84263d55307	897
AnnaBridge	167:e84263d55307	898	#define SCB_DTCMCR_EN_Pos 0U /!< SCB DTCMCR: EN Position /
AnnaBridge	167:e84263d55307	899	#define SCB_DTCMCR_EN_Msk (1UL /<< SCB_DTCMCR_EN_Pos/) /!< SCB DTCMCR: EN Mask /
AnnaBridge	167:e84263d55307	900
AnnaBridge	167:e84263d55307	901	/* AHBP Control Register Definitions */
AnnaBridge	167:e84263d55307	902	#define SCB_AHBPCR_SZ_Pos 1U /!< SCB AHBPCR: SZ Position /
AnnaBridge	167:e84263d55307	903	#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /!< SCB AHBPCR: SZ Mask /
AnnaBridge	167:e84263d55307	904
AnnaBridge	167:e84263d55307	905	#define SCB_AHBPCR_EN_Pos 0U /!< SCB AHBPCR: EN Position /
AnnaBridge	167:e84263d55307	906	#define SCB_AHBPCR_EN_Msk (1UL /<< SCB_AHBPCR_EN_Pos/) /!< SCB AHBPCR: EN Mask /
AnnaBridge	167:e84263d55307	907
AnnaBridge	167:e84263d55307	908	/* L1 Cache Control Register Definitions */
AnnaBridge	167:e84263d55307	909	#define SCB_CACR_FORCEWT_Pos 2U /!< SCB CACR: FORCEWT Position /
AnnaBridge	167:e84263d55307	910	#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /!< SCB CACR: FORCEWT Mask /
AnnaBridge	167:e84263d55307	911
AnnaBridge	167:e84263d55307	912	#define SCB_CACR_ECCEN_Pos 1U /!< SCB CACR: ECCEN Position /
AnnaBridge	167:e84263d55307	913	#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /!< SCB CACR: ECCEN Mask /
AnnaBridge	167:e84263d55307	914
AnnaBridge	167:e84263d55307	915	#define SCB_CACR_SIWT_Pos 0U /!< SCB CACR: SIWT Position /
AnnaBridge	167:e84263d55307	916	#define SCB_CACR_SIWT_Msk (1UL /<< SCB_CACR_SIWT_Pos/) /!< SCB CACR: SIWT Mask /
AnnaBridge	167:e84263d55307	917
AnnaBridge	167:e84263d55307	918	/* AHBS Control Register Definitions */
AnnaBridge	167:e84263d55307	919	#define SCB_AHBSCR_INITCOUNT_Pos 11U /!< SCB AHBSCR: INITCOUNT Position /
AnnaBridge	167:e84263d55307	920	#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /!< SCB AHBSCR: INITCOUNT Mask /
AnnaBridge	167:e84263d55307	921
AnnaBridge	167:e84263d55307	922	#define SCB_AHBSCR_TPRI_Pos 2U /!< SCB AHBSCR: TPRI Position /
AnnaBridge	167:e84263d55307	923	#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /!< SCB AHBSCR: TPRI Mask /
AnnaBridge	167:e84263d55307	924
AnnaBridge	167:e84263d55307	925	#define SCB_AHBSCR_CTL_Pos 0U /!< SCB AHBSCR: CTL Position/
AnnaBridge	167:e84263d55307	926	#define SCB_AHBSCR_CTL_Msk (3UL /<< SCB_AHBPCR_CTL_Pos/) /!< SCB AHBSCR: CTL Mask /
AnnaBridge	167:e84263d55307	927
AnnaBridge	167:e84263d55307	928	/* Auxiliary Bus Fault Status Register Definitions */
AnnaBridge	167:e84263d55307	929	#define SCB_ABFSR_AXIMTYPE_Pos 8U /!< SCB ABFSR: AXIMTYPE Position/
AnnaBridge	167:e84263d55307	930	#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /!< SCB ABFSR: AXIMTYPE Mask /
AnnaBridge	167:e84263d55307	931
AnnaBridge	167:e84263d55307	932	#define SCB_ABFSR_EPPB_Pos 4U /!< SCB ABFSR: EPPB Position/
AnnaBridge	167:e84263d55307	933	#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /!< SCB ABFSR: EPPB Mask /
AnnaBridge	167:e84263d55307	934
AnnaBridge	167:e84263d55307	935	#define SCB_ABFSR_AXIM_Pos 3U /!< SCB ABFSR: AXIM Position/
AnnaBridge	167:e84263d55307	936	#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /!< SCB ABFSR: AXIM Mask /
AnnaBridge	167:e84263d55307	937
AnnaBridge	167:e84263d55307	938	#define SCB_ABFSR_AHBP_Pos 2U /!< SCB ABFSR: AHBP Position/
AnnaBridge	167:e84263d55307	939	#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /!< SCB ABFSR: AHBP Mask /
AnnaBridge	167:e84263d55307	940
AnnaBridge	167:e84263d55307	941	#define SCB_ABFSR_DTCM_Pos 1U /!< SCB ABFSR: DTCM Position/
AnnaBridge	167:e84263d55307	942	#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /!< SCB ABFSR: DTCM Mask /
AnnaBridge	167:e84263d55307	943
AnnaBridge	167:e84263d55307	944	#define SCB_ABFSR_ITCM_Pos 0U /!< SCB ABFSR: ITCM Position/
AnnaBridge	167:e84263d55307	945	#define SCB_ABFSR_ITCM_Msk (1UL /<< SCB_ABFSR_ITCM_Pos/) /!< SCB ABFSR: ITCM Mask /
AnnaBridge	167:e84263d55307	946
AnnaBridge	167:e84263d55307	947	/@} end of group CMSIS_SCB /
AnnaBridge	167:e84263d55307	948
AnnaBridge	167:e84263d55307	949
AnnaBridge	167:e84263d55307	950	/**
AnnaBridge	167:e84263d55307	951	\ingroup CMSIS_core_register
AnnaBridge	167:e84263d55307	952	\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
AnnaBridge	167:e84263d55307	953	\brief Type definitions for the System Control and ID Register not in the SCB
AnnaBridge	167:e84263d55307	954	@{
AnnaBridge	167:e84263d55307	955	*/
AnnaBridge	167:e84263d55307	956
AnnaBridge	167:e84263d55307	957	/**
AnnaBridge	167:e84263d55307	958	\brief Structure type to access the System Control and ID Register not in the SCB.
AnnaBridge	167:e84263d55307	959	*/
AnnaBridge	167:e84263d55307	960	typedef struct
AnnaBridge	167:e84263d55307	961	{
AnnaBridge	167:e84263d55307	962	uint32_t RESERVED0[1U];
AnnaBridge	167:e84263d55307	963	__IM uint32_t ICTR; /!< Offset: 0x004 (R/ ) Interrupt Controller Type Register /
AnnaBridge	167:e84263d55307	964	__IOM uint32_t ACTLR; /!< Offset: 0x008 (R/W) Auxiliary Control Register /
AnnaBridge	167:e84263d55307	965	__IOM uint32_t CPPWR; /!< Offset: 0x00C (R/W) Coprocessor Power Control Register /
AnnaBridge	167:e84263d55307	966	} SCnSCB_Type;
AnnaBridge	167:e84263d55307	967
AnnaBridge	167:e84263d55307	968	/* Interrupt Controller Type Register Definitions */
AnnaBridge	167:e84263d55307	969	#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /!< ICTR: INTLINESNUM Position /
AnnaBridge	167:e84263d55307	970	#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /<< SCnSCB_ICTR_INTLINESNUM_Pos/) /!< ICTR: INTLINESNUM Mask /
AnnaBridge	167:e84263d55307	971
AnnaBridge	167:e84263d55307	972	/@} end of group CMSIS_SCnotSCB /
AnnaBridge	167:e84263d55307	973
AnnaBridge	167:e84263d55307	974
AnnaBridge	167:e84263d55307	975	/**
AnnaBridge	167:e84263d55307	976	\ingroup CMSIS_core_register
AnnaBridge	167:e84263d55307	977	\defgroup CMSIS_SysTick System Tick Timer (SysTick)
AnnaBridge	167:e84263d55307	978	\brief Type definitions for the System Timer Registers.
AnnaBridge	167:e84263d55307	979	@{
AnnaBridge	167:e84263d55307	980	*/
AnnaBridge	167:e84263d55307	981
AnnaBridge	167:e84263d55307	982	/**
AnnaBridge	167:e84263d55307	983	\brief Structure type to access the System Timer (SysTick).
AnnaBridge	167:e84263d55307	984	*/
AnnaBridge	167:e84263d55307	985	typedef struct
AnnaBridge	167:e84263d55307	986	{
AnnaBridge	167:e84263d55307	987	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) SysTick Control and Status Register /
AnnaBridge	167:e84263d55307	988	__IOM uint32_t LOAD; /!< Offset: 0x004 (R/W) SysTick Reload Value Register /
AnnaBridge	167:e84263d55307	989	__IOM uint32_t VAL; /!< Offset: 0x008 (R/W) SysTick Current Value Register /
AnnaBridge	167:e84263d55307	990	__IM uint32_t CALIB; /!< Offset: 0x00C (R/ ) SysTick Calibration Register /
AnnaBridge	167:e84263d55307	991	} SysTick_Type;
AnnaBridge	167:e84263d55307	992
AnnaBridge	167:e84263d55307	993	/* SysTick Control / Status Register Definitions */
AnnaBridge	167:e84263d55307	994	#define SysTick_CTRL_COUNTFLAG_Pos 16U /!< SysTick CTRL: COUNTFLAG Position /
AnnaBridge	167:e84263d55307	995	#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
AnnaBridge	167:e84263d55307	996
AnnaBridge	167:e84263d55307	997	#define SysTick_CTRL_CLKSOURCE_Pos 2U /!< SysTick CTRL: CLKSOURCE Position /
AnnaBridge	167:e84263d55307	998	#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
AnnaBridge	167:e84263d55307	999
AnnaBridge	167:e84263d55307	1000	#define SysTick_CTRL_TICKINT_Pos 1U /!< SysTick CTRL: TICKINT Position /
AnnaBridge	167:e84263d55307	1001	#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
AnnaBridge	167:e84263d55307	1002
AnnaBridge	167:e84263d55307	1003	#define SysTick_CTRL_ENABLE_Pos 0U /!< SysTick CTRL: ENABLE Position /
AnnaBridge	167:e84263d55307	1004	#define SysTick_CTRL_ENABLE_Msk (1UL /<< SysTick_CTRL_ENABLE_Pos/) /!< SysTick CTRL: ENABLE Mask /
AnnaBridge	167:e84263d55307	1005
AnnaBridge	167:e84263d55307	1006	/* SysTick Reload Register Definitions */
AnnaBridge	167:e84263d55307	1007	#define SysTick_LOAD_RELOAD_Pos 0U /!< SysTick LOAD: RELOAD Position /
AnnaBridge	167:e84263d55307	1008	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /<< SysTick_LOAD_RELOAD_Pos/) /!< SysTick LOAD: RELOAD Mask /
AnnaBridge	167:e84263d55307	1009
AnnaBridge	167:e84263d55307	1010	/* SysTick Current Register Definitions */
AnnaBridge	167:e84263d55307	1011	#define SysTick_VAL_CURRENT_Pos 0U /!< SysTick VAL: CURRENT Position /
AnnaBridge	167:e84263d55307	1012	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /<< SysTick_VAL_CURRENT_Pos/) /!< SysTick VAL: CURRENT Mask /
AnnaBridge	167:e84263d55307	1013
AnnaBridge	167:e84263d55307	1014	/* SysTick Calibration Register Definitions */
AnnaBridge	167:e84263d55307	1015	#define SysTick_CALIB_NOREF_Pos 31U /!< SysTick CALIB: NOREF Position /
AnnaBridge	167:e84263d55307	1016	#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
AnnaBridge	167:e84263d55307	1017
AnnaBridge	167:e84263d55307	1018	#define SysTick_CALIB_SKEW_Pos 30U /!< SysTick CALIB: SKEW Position /
AnnaBridge	167:e84263d55307	1019	#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
AnnaBridge	167:e84263d55307	1020
AnnaBridge	167:e84263d55307	1021	#define SysTick_CALIB_TENMS_Pos 0U /!< SysTick CALIB: TENMS Position /
AnnaBridge	167:e84263d55307	1022	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /<< SysTick_CALIB_TENMS_Pos/) /!< SysTick CALIB: TENMS Mask /
AnnaBridge	167:e84263d55307	1023
AnnaBridge	167:e84263d55307	1024	/@} end of group CMSIS_SysTick /
AnnaBridge	167:e84263d55307	1025
AnnaBridge	167:e84263d55307	1026
AnnaBridge	167:e84263d55307	1027	/**
AnnaBridge	167:e84263d55307	1028	\ingroup CMSIS_core_register
AnnaBridge	167:e84263d55307	1029	\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
AnnaBridge	167:e84263d55307	1030	\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
AnnaBridge	167:e84263d55307	1031	@{
AnnaBridge	167:e84263d55307	1032	*/
AnnaBridge	167:e84263d55307	1033
AnnaBridge	167:e84263d55307	1034	/**
AnnaBridge	167:e84263d55307	1035	\brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
AnnaBridge	167:e84263d55307	1036	*/
AnnaBridge	167:e84263d55307	1037	typedef struct
AnnaBridge	167:e84263d55307	1038	{
AnnaBridge	167:e84263d55307	1039	__OM union
AnnaBridge	167:e84263d55307	1040	{
AnnaBridge	167:e84263d55307	1041	__OM uint8_t u8; /!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit /
AnnaBridge	167:e84263d55307	1042	__OM uint16_t u16; /!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit /
AnnaBridge	167:e84263d55307	1043	__OM uint32_t u32; /!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit /
AnnaBridge	167:e84263d55307	1044	} PORT [32U]; /!< Offset: 0x000 ( /W) ITM Stimulus Port Registers /
AnnaBridge	167:e84263d55307	1045	uint32_t RESERVED0[864U];
AnnaBridge	167:e84263d55307	1046	__IOM uint32_t TER; /!< Offset: 0xE00 (R/W) ITM Trace Enable Register /
AnnaBridge	167:e84263d55307	1047	uint32_t RESERVED1[15U];
AnnaBridge	167:e84263d55307	1048	__IOM uint32_t TPR; /!< Offset: 0xE40 (R/W) ITM Trace Privilege Register /
AnnaBridge	167:e84263d55307	1049	uint32_t RESERVED2[15U];
AnnaBridge	167:e84263d55307	1050	__IOM uint32_t TCR; /!< Offset: 0xE80 (R/W) ITM Trace Control Register /
AnnaBridge	167:e84263d55307	1051	uint32_t RESERVED3[29U];
AnnaBridge	167:e84263d55307	1052	__OM uint32_t IWR; /!< Offset: 0xEF8 ( /W) ITM Integration Write Register /
AnnaBridge	167:e84263d55307	1053	__IM uint32_t IRR; /!< Offset: 0xEFC (R/ ) ITM Integration Read Register /
AnnaBridge	167:e84263d55307	1054	__IOM uint32_t IMCR; /!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register /
AnnaBridge	167:e84263d55307	1055	uint32_t RESERVED4[43U];
AnnaBridge	167:e84263d55307	1056	__OM uint32_t LAR; /!< Offset: 0xFB0 ( /W) ITM Lock Access Register /
AnnaBridge	167:e84263d55307	1057	__IM uint32_t LSR; /!< Offset: 0xFB4 (R/ ) ITM Lock Status Register /
AnnaBridge	167:e84263d55307	1058	uint32_t RESERVED5[1U];
AnnaBridge	167:e84263d55307	1059	__IM uint32_t DEVARCH; /!< Offset: 0xFBC (R/ ) ITM Device Architecture Register /
AnnaBridge	167:e84263d55307	1060	uint32_t RESERVED6[4U];
AnnaBridge	167:e84263d55307	1061	__IM uint32_t PID4; /!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 /
AnnaBridge	167:e84263d55307	1062	__IM uint32_t PID5; /!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 /
AnnaBridge	167:e84263d55307	1063	__IM uint32_t PID6; /!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 /
AnnaBridge	167:e84263d55307	1064	__IM uint32_t PID7; /!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 /
AnnaBridge	167:e84263d55307	1065	__IM uint32_t PID0; /!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 /
AnnaBridge	167:e84263d55307	1066	__IM uint32_t PID1; /!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 /
AnnaBridge	167:e84263d55307	1067	__IM uint32_t PID2; /!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 /
AnnaBridge	167:e84263d55307	1068	__IM uint32_t PID3; /!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 /
AnnaBridge	167:e84263d55307	1069	__IM uint32_t CID0; /!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 /
AnnaBridge	167:e84263d55307	1070	__IM uint32_t CID1; /!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 /
AnnaBridge	167:e84263d55307	1071	__IM uint32_t CID2; /!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 /
AnnaBridge	167:e84263d55307	1072	__IM uint32_t CID3; /!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 /
AnnaBridge	167:e84263d55307	1073	} ITM_Type;
AnnaBridge	167:e84263d55307	1074
AnnaBridge	167:e84263d55307	1075	/* ITM Stimulus Port Register Definitions */
AnnaBridge	167:e84263d55307	1076	#define ITM_STIM_DISABLED_Pos 1U /!< ITM STIM: DISABLED Position /
AnnaBridge	167:e84263d55307	1077	#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /!< ITM STIM: DISABLED Mask /
AnnaBridge	167:e84263d55307	1078
AnnaBridge	167:e84263d55307	1079	#define ITM_STIM_FIFOREADY_Pos 0U /!< ITM STIM: FIFOREADY Position /
AnnaBridge	167:e84263d55307	1080	#define ITM_STIM_FIFOREADY_Msk (0x1UL /<< ITM_STIM_FIFOREADY_Pos/) /!< ITM STIM: FIFOREADY Mask /
AnnaBridge	167:e84263d55307	1081
AnnaBridge	167:e84263d55307	1082	/* ITM Trace Privilege Register Definitions */
AnnaBridge	167:e84263d55307	1083	#define ITM_TPR_PRIVMASK_Pos 0U /!< ITM TPR: PRIVMASK Position /
AnnaBridge	167:e84263d55307	1084	#define ITM_TPR_PRIVMASK_Msk (0xFUL /<< ITM_TPR_PRIVMASK_Pos/) /!< ITM TPR: PRIVMASK Mask /
AnnaBridge	167:e84263d55307	1085
AnnaBridge	167:e84263d55307	1086	/* ITM Trace Control Register Definitions */
AnnaBridge	167:e84263d55307	1087	#define ITM_TCR_BUSY_Pos 23U /!< ITM TCR: BUSY Position /
AnnaBridge	167:e84263d55307	1088	#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /!< ITM TCR: BUSY Mask /
AnnaBridge	167:e84263d55307	1089
AnnaBridge	167:e84263d55307	1090	#define ITM_TCR_TRACEBUSID_Pos 16U /!< ITM TCR: ATBID Position /
AnnaBridge	167:e84263d55307	1091	#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /!< ITM TCR: ATBID Mask /
AnnaBridge	167:e84263d55307	1092
AnnaBridge	167:e84263d55307	1093	#define ITM_TCR_GTSFREQ_Pos 10U /!< ITM TCR: Global timestamp frequency Position /
AnnaBridge	167:e84263d55307	1094	#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /!< ITM TCR: Global timestamp frequency Mask /
AnnaBridge	167:e84263d55307	1095
AnnaBridge	167:e84263d55307	1096	#define ITM_TCR_TSPRESCALE_Pos 8U /!< ITM TCR: TSPRESCALE Position /
AnnaBridge	167:e84263d55307	1097	#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /!< ITM TCR: TSPRESCALE Mask /
AnnaBridge	167:e84263d55307	1098
AnnaBridge	167:e84263d55307	1099	#define ITM_TCR_STALLENA_Pos 5U /!< ITM TCR: STALLENA Position /
AnnaBridge	167:e84263d55307	1100	#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /!< ITM TCR: STALLENA Mask /
AnnaBridge	167:e84263d55307	1101
AnnaBridge	167:e84263d55307	1102	#define ITM_TCR_SWOENA_Pos 4U /!< ITM TCR: SWOENA Position /
AnnaBridge	167:e84263d55307	1103	#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /!< ITM TCR: SWOENA Mask /
AnnaBridge	167:e84263d55307	1104
AnnaBridge	167:e84263d55307	1105	#define ITM_TCR_DWTENA_Pos 3U /!< ITM TCR: DWTENA Position /
AnnaBridge	167:e84263d55307	1106	#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /!< ITM TCR: DWTENA Mask /
AnnaBridge	167:e84263d55307	1107
AnnaBridge	167:e84263d55307	1108	#define ITM_TCR_SYNCENA_Pos 2U /!< ITM TCR: SYNCENA Position /
AnnaBridge	167:e84263d55307	1109	#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /!< ITM TCR: SYNCENA Mask /
AnnaBridge	167:e84263d55307	1110
AnnaBridge	167:e84263d55307	1111	#define ITM_TCR_TSENA_Pos 1U /!< ITM TCR: TSENA Position /
AnnaBridge	167:e84263d55307	1112	#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /!< ITM TCR: TSENA Mask /
AnnaBridge	167:e84263d55307	1113
AnnaBridge	167:e84263d55307	1114	#define ITM_TCR_ITMENA_Pos 0U /!< ITM TCR: ITM Enable bit Position /
AnnaBridge	167:e84263d55307	1115	#define ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/) /!< ITM TCR: ITM Enable bit Mask /
AnnaBridge	167:e84263d55307	1116
AnnaBridge	167:e84263d55307	1117	/* ITM Integration Write Register Definitions */
AnnaBridge	167:e84263d55307	1118	#define ITM_IWR_ATVALIDM_Pos 0U /!< ITM IWR: ATVALIDM Position /
AnnaBridge	167:e84263d55307	1119	#define ITM_IWR_ATVALIDM_Msk (1UL /<< ITM_IWR_ATVALIDM_Pos/) /!< ITM IWR: ATVALIDM Mask /
AnnaBridge	167:e84263d55307	1120
AnnaBridge	167:e84263d55307	1121	/* ITM Integration Read Register Definitions */
AnnaBridge	167:e84263d55307	1122	#define ITM_IRR_ATREADYM_Pos 0U /!< ITM IRR: ATREADYM Position /
AnnaBridge	167:e84263d55307	1123	#define ITM_IRR_ATREADYM_Msk (1UL /<< ITM_IRR_ATREADYM_Pos/) /!< ITM IRR: ATREADYM Mask /
AnnaBridge	167:e84263d55307	1124
AnnaBridge	167:e84263d55307	1125	/* ITM Integration Mode Control Register Definitions */
AnnaBridge	167:e84263d55307	1126	#define ITM_IMCR_INTEGRATION_Pos 0U /!< ITM IMCR: INTEGRATION Position /
AnnaBridge	167:e84263d55307	1127	#define ITM_IMCR_INTEGRATION_Msk (1UL /<< ITM_IMCR_INTEGRATION_Pos/) /!< ITM IMCR: INTEGRATION Mask /
AnnaBridge	167:e84263d55307	1128
AnnaBridge	167:e84263d55307	1129	/* ITM Lock Status Register Definitions */
AnnaBridge	167:e84263d55307	1130	#define ITM_LSR_ByteAcc_Pos 2U /!< ITM LSR: ByteAcc Position /
AnnaBridge	167:e84263d55307	1131	#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /!< ITM LSR: ByteAcc Mask /
AnnaBridge	167:e84263d55307	1132
AnnaBridge	167:e84263d55307	1133	#define ITM_LSR_Access_Pos 1U /!< ITM LSR: Access Position /
AnnaBridge	167:e84263d55307	1134	#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /!< ITM LSR: Access Mask /
AnnaBridge	167:e84263d55307	1135
AnnaBridge	167:e84263d55307	1136	#define ITM_LSR_Present_Pos 0U /!< ITM LSR: Present Position /
AnnaBridge	167:e84263d55307	1137	#define ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/) /!< ITM LSR: Present Mask /
AnnaBridge	167:e84263d55307	1138
AnnaBridge	167:e84263d55307	1139	/@}/ /* end of group CMSIS_ITM */
AnnaBridge	167:e84263d55307	1140
AnnaBridge	167:e84263d55307	1141
AnnaBridge	167:e84263d55307	1142	/**
AnnaBridge	167:e84263d55307	1143	\ingroup CMSIS_core_register
AnnaBridge	167:e84263d55307	1144	\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
AnnaBridge	167:e84263d55307	1145	\brief Type definitions for the Data Watchpoint and Trace (DWT)
AnnaBridge	167:e84263d55307	1146	@{
AnnaBridge	167:e84263d55307	1147	*/
AnnaBridge	167:e84263d55307	1148
AnnaBridge	167:e84263d55307	1149	/**
AnnaBridge	167:e84263d55307	1150	\brief Structure type to access the Data Watchpoint and Trace Register (DWT).
AnnaBridge	167:e84263d55307	1151	*/
AnnaBridge	167:e84263d55307	1152	typedef struct
AnnaBridge	167:e84263d55307	1153	{
AnnaBridge	167:e84263d55307	1154	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) Control Register /
AnnaBridge	167:e84263d55307	1155	__IOM uint32_t CYCCNT; /!< Offset: 0x004 (R/W) Cycle Count Register /
AnnaBridge	167:e84263d55307	1156	__IOM uint32_t CPICNT; /!< Offset: 0x008 (R/W) CPI Count Register /
AnnaBridge	167:e84263d55307	1157	__IOM uint32_t EXCCNT; /!< Offset: 0x00C (R/W) Exception Overhead Count Register /
AnnaBridge	167:e84263d55307	1158	__IOM uint32_t SLEEPCNT; /!< Offset: 0x010 (R/W) Sleep Count Register /
AnnaBridge	167:e84263d55307	1159	__IOM uint32_t LSUCNT; /!< Offset: 0x014 (R/W) LSU Count Register /
AnnaBridge	167:e84263d55307	1160	__IOM uint32_t FOLDCNT; /!< Offset: 0x018 (R/W) Folded-instruction Count Register /
AnnaBridge	167:e84263d55307	1161	__IM uint32_t PCSR; /!< Offset: 0x01C (R/ ) Program Counter Sample Register /
AnnaBridge	167:e84263d55307	1162	__IOM uint32_t COMP0; /!< Offset: 0x020 (R/W) Comparator Register 0 /
AnnaBridge	167:e84263d55307	1163	uint32_t RESERVED1[1U];
AnnaBridge	167:e84263d55307	1164	__IOM uint32_t FUNCTION0; /!< Offset: 0x028 (R/W) Function Register 0 /
AnnaBridge	167:e84263d55307	1165	uint32_t RESERVED2[1U];
AnnaBridge	167:e84263d55307	1166	__IOM uint32_t COMP1; /!< Offset: 0x030 (R/W) Comparator Register 1 /
AnnaBridge	167:e84263d55307	1167	uint32_t RESERVED3[1U];
AnnaBridge	167:e84263d55307	1168	__IOM uint32_t FUNCTION1; /!< Offset: 0x038 (R/W) Function Register 1 /
AnnaBridge	167:e84263d55307	1169	uint32_t RESERVED4[1U];
AnnaBridge	167:e84263d55307	1170	__IOM uint32_t COMP2; /!< Offset: 0x040 (R/W) Comparator Register 2 /
AnnaBridge	167:e84263d55307	1171	uint32_t RESERVED5[1U];
AnnaBridge	167:e84263d55307	1172	__IOM uint32_t FUNCTION2; /!< Offset: 0x048 (R/W) Function Register 2 /
AnnaBridge	167:e84263d55307	1173	uint32_t RESERVED6[1U];
AnnaBridge	167:e84263d55307	1174	__IOM uint32_t COMP3; /!< Offset: 0x050 (R/W) Comparator Register 3 /
AnnaBridge	167:e84263d55307	1175	uint32_t RESERVED7[1U];
AnnaBridge	167:e84263d55307	1176	__IOM uint32_t FUNCTION3; /!< Offset: 0x058 (R/W) Function Register 3 /
AnnaBridge	167:e84263d55307	1177	uint32_t RESERVED8[1U];
AnnaBridge	167:e84263d55307	1178	__IOM uint32_t COMP4; /!< Offset: 0x060 (R/W) Comparator Register 4 /
AnnaBridge	167:e84263d55307	1179	uint32_t RESERVED9[1U];
AnnaBridge	167:e84263d55307	1180	__IOM uint32_t FUNCTION4; /!< Offset: 0x068 (R/W) Function Register 4 /
AnnaBridge	167:e84263d55307	1181	uint32_t RESERVED10[1U];
AnnaBridge	167:e84263d55307	1182	__IOM uint32_t COMP5; /!< Offset: 0x070 (R/W) Comparator Register 5 /
AnnaBridge	167:e84263d55307	1183	uint32_t RESERVED11[1U];
AnnaBridge	167:e84263d55307	1184	__IOM uint32_t FUNCTION5; /!< Offset: 0x078 (R/W) Function Register 5 /
AnnaBridge	167:e84263d55307	1185	uint32_t RESERVED12[1U];
AnnaBridge	167:e84263d55307	1186	__IOM uint32_t COMP6; /!< Offset: 0x080 (R/W) Comparator Register 6 /
AnnaBridge	167:e84263d55307	1187	uint32_t RESERVED13[1U];
AnnaBridge	167:e84263d55307	1188	__IOM uint32_t FUNCTION6; /!< Offset: 0x088 (R/W) Function Register 6 /
AnnaBridge	167:e84263d55307	1189	uint32_t RESERVED14[1U];
AnnaBridge	167:e84263d55307	1190	__IOM uint32_t COMP7; /!< Offset: 0x090 (R/W) Comparator Register 7 /
AnnaBridge	167:e84263d55307	1191	uint32_t RESERVED15[1U];
AnnaBridge	167:e84263d55307	1192	__IOM uint32_t FUNCTION7; /!< Offset: 0x098 (R/W) Function Register 7 /
AnnaBridge	167:e84263d55307	1193	uint32_t RESERVED16[1U];
AnnaBridge	167:e84263d55307	1194	__IOM uint32_t COMP8; /!< Offset: 0x0A0 (R/W) Comparator Register 8 /
AnnaBridge	167:e84263d55307	1195	uint32_t RESERVED17[1U];
AnnaBridge	167:e84263d55307	1196	__IOM uint32_t FUNCTION8; /!< Offset: 0x0A8 (R/W) Function Register 8 /
AnnaBridge	167:e84263d55307	1197	uint32_t RESERVED18[1U];
AnnaBridge	167:e84263d55307	1198	__IOM uint32_t COMP9; /!< Offset: 0x0B0 (R/W) Comparator Register 9 /
AnnaBridge	167:e84263d55307	1199	uint32_t RESERVED19[1U];
AnnaBridge	167:e84263d55307	1200	__IOM uint32_t FUNCTION9; /!< Offset: 0x0B8 (R/W) Function Register 9 /
AnnaBridge	167:e84263d55307	1201	uint32_t RESERVED20[1U];
AnnaBridge	167:e84263d55307	1202	__IOM uint32_t COMP10; /!< Offset: 0x0C0 (R/W) Comparator Register 10 /
AnnaBridge	167:e84263d55307	1203	uint32_t RESERVED21[1U];
AnnaBridge	167:e84263d55307	1204	__IOM uint32_t FUNCTION10; /!< Offset: 0x0C8 (R/W) Function Register 10 /
AnnaBridge	167:e84263d55307	1205	uint32_t RESERVED22[1U];
AnnaBridge	167:e84263d55307	1206	__IOM uint32_t COMP11; /!< Offset: 0x0D0 (R/W) Comparator Register 11 /
AnnaBridge	167:e84263d55307	1207	uint32_t RESERVED23[1U];
AnnaBridge	167:e84263d55307	1208	__IOM uint32_t FUNCTION11; /!< Offset: 0x0D8 (R/W) Function Register 11 /
AnnaBridge	167:e84263d55307	1209	uint32_t RESERVED24[1U];
AnnaBridge	167:e84263d55307	1210	__IOM uint32_t COMP12; /!< Offset: 0x0E0 (R/W) Comparator Register 12 /
AnnaBridge	167:e84263d55307	1211	uint32_t RESERVED25[1U];
AnnaBridge	167:e84263d55307	1212	__IOM uint32_t FUNCTION12; /!< Offset: 0x0E8 (R/W) Function Register 12 /
AnnaBridge	167:e84263d55307	1213	uint32_t RESERVED26[1U];
AnnaBridge	167:e84263d55307	1214	__IOM uint32_t COMP13; /!< Offset: 0x0F0 (R/W) Comparator Register 13 /
AnnaBridge	167:e84263d55307	1215	uint32_t RESERVED27[1U];
AnnaBridge	167:e84263d55307	1216	__IOM uint32_t FUNCTION13; /!< Offset: 0x0F8 (R/W) Function Register 13 /
AnnaBridge	167:e84263d55307	1217	uint32_t RESERVED28[1U];
AnnaBridge	167:e84263d55307	1218	__IOM uint32_t COMP14; /!< Offset: 0x100 (R/W) Comparator Register 14 /
AnnaBridge	167:e84263d55307	1219	uint32_t RESERVED29[1U];
AnnaBridge	167:e84263d55307	1220	__IOM uint32_t FUNCTION14; /!< Offset: 0x108 (R/W) Function Register 14 /
AnnaBridge	167:e84263d55307	1221	uint32_t RESERVED30[1U];
AnnaBridge	167:e84263d55307	1222	__IOM uint32_t COMP15; /!< Offset: 0x110 (R/W) Comparator Register 15 /
AnnaBridge	167:e84263d55307	1223	uint32_t RESERVED31[1U];
AnnaBridge	167:e84263d55307	1224	__IOM uint32_t FUNCTION15; /!< Offset: 0x118 (R/W) Function Register 15 /
AnnaBridge	167:e84263d55307	1225	uint32_t RESERVED32[934U];
AnnaBridge	167:e84263d55307	1226	__IM uint32_t LSR; /!< Offset: 0xFB4 (R ) Lock Status Register /
AnnaBridge	167:e84263d55307	1227	uint32_t RESERVED33[1U];
AnnaBridge	167:e84263d55307	1228	__IM uint32_t DEVARCH; /!< Offset: 0xFBC (R/ ) Device Architecture Register /
AnnaBridge	167:e84263d55307	1229	} DWT_Type;
AnnaBridge	167:e84263d55307	1230
AnnaBridge	167:e84263d55307	1231	/* DWT Control Register Definitions */
AnnaBridge	167:e84263d55307	1232	#define DWT_CTRL_NUMCOMP_Pos 28U /!< DWT CTRL: NUMCOMP Position /
AnnaBridge	167:e84263d55307	1233	#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /!< DWT CTRL: NUMCOMP Mask /
AnnaBridge	167:e84263d55307	1234
AnnaBridge	167:e84263d55307	1235	#define DWT_CTRL_NOTRCPKT_Pos 27U /!< DWT CTRL: NOTRCPKT Position /
AnnaBridge	167:e84263d55307	1236	#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /!< DWT CTRL: NOTRCPKT Mask /
AnnaBridge	167:e84263d55307	1237
AnnaBridge	167:e84263d55307	1238	#define DWT_CTRL_NOEXTTRIG_Pos 26U /!< DWT CTRL: NOEXTTRIG Position /
AnnaBridge	167:e84263d55307	1239	#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /!< DWT CTRL: NOEXTTRIG Mask /
AnnaBridge	167:e84263d55307	1240
AnnaBridge	167:e84263d55307	1241	#define DWT_CTRL_NOCYCCNT_Pos 25U /!< DWT CTRL: NOCYCCNT Position /
AnnaBridge	167:e84263d55307	1242	#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /!< DWT CTRL: NOCYCCNT Mask /
AnnaBridge	167:e84263d55307	1243
AnnaBridge	167:e84263d55307	1244	#define DWT_CTRL_NOPRFCNT_Pos 24U /!< DWT CTRL: NOPRFCNT Position /
AnnaBridge	167:e84263d55307	1245	#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /!< DWT CTRL: NOPRFCNT Mask /
AnnaBridge	167:e84263d55307	1246
AnnaBridge	167:e84263d55307	1247	#define DWT_CTRL_CYCDISS_Pos 23U /!< DWT CTRL: CYCDISS Position /
AnnaBridge	167:e84263d55307	1248	#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /!< DWT CTRL: CYCDISS Mask /
AnnaBridge	167:e84263d55307	1249
AnnaBridge	167:e84263d55307	1250	#define DWT_CTRL_CYCEVTENA_Pos 22U /!< DWT CTRL: CYCEVTENA Position /
AnnaBridge	167:e84263d55307	1251	#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /!< DWT CTRL: CYCEVTENA Mask /
AnnaBridge	167:e84263d55307	1252
AnnaBridge	167:e84263d55307	1253	#define DWT_CTRL_FOLDEVTENA_Pos 21U /!< DWT CTRL: FOLDEVTENA Position /
AnnaBridge	167:e84263d55307	1254	#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /!< DWT CTRL: FOLDEVTENA Mask /
AnnaBridge	167:e84263d55307	1255
AnnaBridge	167:e84263d55307	1256	#define DWT_CTRL_LSUEVTENA_Pos 20U /!< DWT CTRL: LSUEVTENA Position /
AnnaBridge	167:e84263d55307	1257	#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /!< DWT CTRL: LSUEVTENA Mask /
AnnaBridge	167:e84263d55307	1258
AnnaBridge	167:e84263d55307	1259	#define DWT_CTRL_SLEEPEVTENA_Pos 19U /!< DWT CTRL: SLEEPEVTENA Position /
AnnaBridge	167:e84263d55307	1260	#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /!< DWT CTRL: SLEEPEVTENA Mask /
AnnaBridge	167:e84263d55307	1261
AnnaBridge	167:e84263d55307	1262	#define DWT_CTRL_EXCEVTENA_Pos 18U /!< DWT CTRL: EXCEVTENA Position /
AnnaBridge	167:e84263d55307	1263	#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /!< DWT CTRL: EXCEVTENA Mask /
AnnaBridge	167:e84263d55307	1264
AnnaBridge	167:e84263d55307	1265	#define DWT_CTRL_CPIEVTENA_Pos 17U /!< DWT CTRL: CPIEVTENA Position /
AnnaBridge	167:e84263d55307	1266	#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /!< DWT CTRL: CPIEVTENA Mask /
AnnaBridge	167:e84263d55307	1267
AnnaBridge	167:e84263d55307	1268	#define DWT_CTRL_EXCTRCENA_Pos 16U /!< DWT CTRL: EXCTRCENA Position /
AnnaBridge	167:e84263d55307	1269	#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /!< DWT CTRL: EXCTRCENA Mask /
AnnaBridge	167:e84263d55307	1270
AnnaBridge	167:e84263d55307	1271	#define DWT_CTRL_PCSAMPLENA_Pos 12U /!< DWT CTRL: PCSAMPLENA Position /
AnnaBridge	167:e84263d55307	1272	#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /!< DWT CTRL: PCSAMPLENA Mask /
AnnaBridge	167:e84263d55307	1273
AnnaBridge	167:e84263d55307	1274	#define DWT_CTRL_SYNCTAP_Pos 10U /!< DWT CTRL: SYNCTAP Position /
AnnaBridge	167:e84263d55307	1275	#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /!< DWT CTRL: SYNCTAP Mask /
AnnaBridge	167:e84263d55307	1276
AnnaBridge	167:e84263d55307	1277	#define DWT_CTRL_CYCTAP_Pos 9U /!< DWT CTRL: CYCTAP Position /
AnnaBridge	167:e84263d55307	1278	#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /!< DWT CTRL: CYCTAP Mask /
AnnaBridge	167:e84263d55307	1279
AnnaBridge	167:e84263d55307	1280	#define DWT_CTRL_POSTINIT_Pos 5U /!< DWT CTRL: POSTINIT Position /
AnnaBridge	167:e84263d55307	1281	#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /!< DWT CTRL: POSTINIT Mask /
AnnaBridge	167:e84263d55307	1282
AnnaBridge	167:e84263d55307	1283	#define DWT_CTRL_POSTPRESET_Pos 1U /!< DWT CTRL: POSTPRESET Position /
AnnaBridge	167:e84263d55307	1284	#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /!< DWT CTRL: POSTPRESET Mask /
AnnaBridge	167:e84263d55307	1285
AnnaBridge	167:e84263d55307	1286	#define DWT_CTRL_CYCCNTENA_Pos 0U /!< DWT CTRL: CYCCNTENA Position /
AnnaBridge	167:e84263d55307	1287	#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /<< DWT_CTRL_CYCCNTENA_Pos/) /!< DWT CTRL: CYCCNTENA Mask /
AnnaBridge	167:e84263d55307	1288
AnnaBridge	167:e84263d55307	1289	/* DWT CPI Count Register Definitions */
AnnaBridge	167:e84263d55307	1290	#define DWT_CPICNT_CPICNT_Pos 0U /!< DWT CPICNT: CPICNT Position /
AnnaBridge	167:e84263d55307	1291	#define DWT_CPICNT_CPICNT_Msk (0xFFUL /<< DWT_CPICNT_CPICNT_Pos/) /!< DWT CPICNT: CPICNT Mask /
AnnaBridge	167:e84263d55307	1292
AnnaBridge	167:e84263d55307	1293	/* DWT Exception Overhead Count Register Definitions */
AnnaBridge	167:e84263d55307	1294	#define DWT_EXCCNT_EXCCNT_Pos 0U /!< DWT EXCCNT: EXCCNT Position /
AnnaBridge	167:e84263d55307	1295	#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /<< DWT_EXCCNT_EXCCNT_Pos/) /!< DWT EXCCNT: EXCCNT Mask /
AnnaBridge	167:e84263d55307	1296
AnnaBridge	167:e84263d55307	1297	/* DWT Sleep Count Register Definitions */
AnnaBridge	167:e84263d55307	1298	#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /!< DWT SLEEPCNT: SLEEPCNT Position /
AnnaBridge	167:e84263d55307	1299	#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /<< DWT_SLEEPCNT_SLEEPCNT_Pos/) /!< DWT SLEEPCNT: SLEEPCNT Mask /
AnnaBridge	167:e84263d55307	1300
AnnaBridge	167:e84263d55307	1301	/* DWT LSU Count Register Definitions */
AnnaBridge	167:e84263d55307	1302	#define DWT_LSUCNT_LSUCNT_Pos 0U /!< DWT LSUCNT: LSUCNT Position /
AnnaBridge	167:e84263d55307	1303	#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /<< DWT_LSUCNT_LSUCNT_Pos/) /!< DWT LSUCNT: LSUCNT Mask /
AnnaBridge	167:e84263d55307	1304
AnnaBridge	167:e84263d55307	1305	/* DWT Folded-instruction Count Register Definitions */
AnnaBridge	167:e84263d55307	1306	#define DWT_FOLDCNT_FOLDCNT_Pos 0U /!< DWT FOLDCNT: FOLDCNT Position /
AnnaBridge	167:e84263d55307	1307	#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /<< DWT_FOLDCNT_FOLDCNT_Pos/) /!< DWT FOLDCNT: FOLDCNT Mask /
AnnaBridge	167:e84263d55307	1308
AnnaBridge	167:e84263d55307	1309	/* DWT Comparator Function Register Definitions */
AnnaBridge	167:e84263d55307	1310	#define DWT_FUNCTION_ID_Pos 27U /!< DWT FUNCTION: ID Position /
AnnaBridge	167:e84263d55307	1311	#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /!< DWT FUNCTION: ID Mask /
AnnaBridge	167:e84263d55307	1312
AnnaBridge	167:e84263d55307	1313	#define DWT_FUNCTION_MATCHED_Pos 24U /!< DWT FUNCTION: MATCHED Position /
AnnaBridge	167:e84263d55307	1314	#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /!< DWT FUNCTION: MATCHED Mask /
AnnaBridge	167:e84263d55307	1315
AnnaBridge	167:e84263d55307	1316	#define DWT_FUNCTION_DATAVSIZE_Pos 10U /!< DWT FUNCTION: DATAVSIZE Position /
AnnaBridge	167:e84263d55307	1317	#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /!< DWT FUNCTION: DATAVSIZE Mask /
AnnaBridge	167:e84263d55307	1318
AnnaBridge	167:e84263d55307	1319	#define DWT_FUNCTION_ACTION_Pos 4U /!< DWT FUNCTION: ACTION Position /
AnnaBridge	167:e84263d55307	1320	#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /!< DWT FUNCTION: ACTION Mask /
AnnaBridge	167:e84263d55307	1321
AnnaBridge	167:e84263d55307	1322	#define DWT_FUNCTION_MATCH_Pos 0U /!< DWT FUNCTION: MATCH Position /
AnnaBridge	167:e84263d55307	1323	#define DWT_FUNCTION_MATCH_Msk (0xFUL /<< DWT_FUNCTION_MATCH_Pos/) /!< DWT FUNCTION: MATCH Mask /
AnnaBridge	167:e84263d55307	1324
AnnaBridge	167:e84263d55307	1325	/@}/ /* end of group CMSIS_DWT */
AnnaBridge	167:e84263d55307	1326
AnnaBridge	167:e84263d55307	1327
AnnaBridge	167:e84263d55307	1328	/**
AnnaBridge	167:e84263d55307	1329	\ingroup CMSIS_core_register
AnnaBridge	167:e84263d55307	1330	\defgroup CMSIS_TPI Trace Port Interface (TPI)
AnnaBridge	167:e84263d55307	1331	\brief Type definitions for the Trace Port Interface (TPI)
AnnaBridge	167:e84263d55307	1332	@{
AnnaBridge	167:e84263d55307	1333	*/
AnnaBridge	167:e84263d55307	1334
AnnaBridge	167:e84263d55307	1335	/**
AnnaBridge	167:e84263d55307	1336	\brief Structure type to access the Trace Port Interface Register (TPI).
AnnaBridge	167:e84263d55307	1337	*/
AnnaBridge	167:e84263d55307	1338	typedef struct
AnnaBridge	167:e84263d55307	1339	{
AnnaBridge	167:e84263d55307	1340	__IOM uint32_t SSPSR; /!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register /
AnnaBridge	167:e84263d55307	1341	__IOM uint32_t CSPSR; /!< Offset: 0x004 (R/W) Current Parallel Port Size Register /
AnnaBridge	167:e84263d55307	1342	uint32_t RESERVED0[2U];
AnnaBridge	167:e84263d55307	1343	__IOM uint32_t ACPR; /!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register /
AnnaBridge	167:e84263d55307	1344	uint32_t RESERVED1[55U];
AnnaBridge	167:e84263d55307	1345	__IOM uint32_t SPPR; /!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register /
AnnaBridge	167:e84263d55307	1346	uint32_t RESERVED2[131U];
AnnaBridge	167:e84263d55307	1347	__IM uint32_t FFSR; /!< Offset: 0x300 (R/ ) Formatter and Flush Status Register /
AnnaBridge	167:e84263d55307	1348	__IOM uint32_t FFCR; /!< Offset: 0x304 (R/W) Formatter and Flush Control Register /
AnnaBridge	167:e84263d55307	1349	__IM uint32_t FSCR; /!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register /
AnnaBridge	167:e84263d55307	1350	uint32_t RESERVED3[759U];
AnnaBridge	167:e84263d55307	1351	__IM uint32_t TRIGGER; /!< Offset: 0xEE8 (R/ ) TRIGGER /
AnnaBridge	167:e84263d55307	1352	__IM uint32_t FIFO0; /!< Offset: 0xEEC (R/ ) Integration ETM Data /
AnnaBridge	167:e84263d55307	1353	__IM uint32_t ITATBCTR2; /!< Offset: 0xEF0 (R/ ) ITATBCTR2 /
AnnaBridge	167:e84263d55307	1354	uint32_t RESERVED4[1U];
AnnaBridge	167:e84263d55307	1355	__IM uint32_t ITATBCTR0; /!< Offset: 0xEF8 (R/ ) ITATBCTR0 /
AnnaBridge	167:e84263d55307	1356	__IM uint32_t FIFO1; /!< Offset: 0xEFC (R/ ) Integration ITM Data /
AnnaBridge	167:e84263d55307	1357	__IOM uint32_t ITCTRL; /!< Offset: 0xF00 (R/W) Integration Mode Control /
AnnaBridge	167:e84263d55307	1358	uint32_t RESERVED5[39U];
AnnaBridge	167:e84263d55307	1359	__IOM uint32_t CLAIMSET; /!< Offset: 0xFA0 (R/W) Claim tag set /
AnnaBridge	167:e84263d55307	1360	__IOM uint32_t CLAIMCLR; /!< Offset: 0xFA4 (R/W) Claim tag clear /
AnnaBridge	167:e84263d55307	1361	uint32_t RESERVED7[8U];
AnnaBridge	167:e84263d55307	1362	__IM uint32_t DEVID; /!< Offset: 0xFC8 (R/ ) TPIU_DEVID /
AnnaBridge	167:e84263d55307	1363	__IM uint32_t DEVTYPE; /!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE /
AnnaBridge	167:e84263d55307	1364	} TPI_Type;
AnnaBridge	167:e84263d55307	1365
AnnaBridge	167:e84263d55307	1366	/* TPI Asynchronous Clock Prescaler Register Definitions */
AnnaBridge	167:e84263d55307	1367	#define TPI_ACPR_PRESCALER_Pos 0U /!< TPI ACPR: PRESCALER Position /
AnnaBridge	167:e84263d55307	1368	#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/) /!< TPI ACPR: PRESCALER Mask /
AnnaBridge	167:e84263d55307	1369
AnnaBridge	167:e84263d55307	1370	/* TPI Selected Pin Protocol Register Definitions */
AnnaBridge	167:e84263d55307	1371	#define TPI_SPPR_TXMODE_Pos 0U /!< TPI SPPR: TXMODE Position /
AnnaBridge	167:e84263d55307	1372	#define TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/) /!< TPI SPPR: TXMODE Mask /
AnnaBridge	167:e84263d55307	1373
AnnaBridge	167:e84263d55307	1374	/* TPI Formatter and Flush Status Register Definitions */
AnnaBridge	167:e84263d55307	1375	#define TPI_FFSR_FtNonStop_Pos 3U /!< TPI FFSR: FtNonStop Position /
AnnaBridge	167:e84263d55307	1376	#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /!< TPI FFSR: FtNonStop Mask /
AnnaBridge	167:e84263d55307	1377
AnnaBridge	167:e84263d55307	1378	#define TPI_FFSR_TCPresent_Pos 2U /!< TPI FFSR: TCPresent Position /
AnnaBridge	167:e84263d55307	1379	#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /!< TPI FFSR: TCPresent Mask /
AnnaBridge	167:e84263d55307	1380
AnnaBridge	167:e84263d55307	1381	#define TPI_FFSR_FtStopped_Pos 1U /!< TPI FFSR: FtStopped Position /
AnnaBridge	167:e84263d55307	1382	#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /!< TPI FFSR: FtStopped Mask /
AnnaBridge	167:e84263d55307	1383
AnnaBridge	167:e84263d55307	1384	#define TPI_FFSR_FlInProg_Pos 0U /!< TPI FFSR: FlInProg Position /
AnnaBridge	167:e84263d55307	1385	#define TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/) /!< TPI FFSR: FlInProg Mask /
AnnaBridge	167:e84263d55307	1386
AnnaBridge	167:e84263d55307	1387	/* TPI Formatter and Flush Control Register Definitions */
AnnaBridge	167:e84263d55307	1388	#define TPI_FFCR_TrigIn_Pos 8U /!< TPI FFCR: TrigIn Position /
AnnaBridge	167:e84263d55307	1389	#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /!< TPI FFCR: TrigIn Mask /
AnnaBridge	167:e84263d55307	1390
AnnaBridge	167:e84263d55307	1391	#define TPI_FFCR_EnFCont_Pos 1U /!< TPI FFCR: EnFCont Position /
AnnaBridge	167:e84263d55307	1392	#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /!< TPI FFCR: EnFCont Mask /
AnnaBridge	167:e84263d55307	1393
AnnaBridge	167:e84263d55307	1394	/* TPI TRIGGER Register Definitions */
AnnaBridge	167:e84263d55307	1395	#define TPI_TRIGGER_TRIGGER_Pos 0U /!< TPI TRIGGER: TRIGGER Position /
AnnaBridge	167:e84263d55307	1396	#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/) /!< TPI TRIGGER: TRIGGER Mask /
AnnaBridge	167:e84263d55307	1397
AnnaBridge	167:e84263d55307	1398	/* TPI Integration ETM Data Register Definitions (FIFO0) */
AnnaBridge	167:e84263d55307	1399	#define TPI_FIFO0_ITM_ATVALID_Pos 29U /!< TPI FIFO0: ITM_ATVALID Position /
AnnaBridge	167:e84263d55307	1400	#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /!< TPI FIFO0: ITM_ATVALID Mask /
AnnaBridge	167:e84263d55307	1401
AnnaBridge	167:e84263d55307	1402	#define TPI_FIFO0_ITM_bytecount_Pos 27U /!< TPI FIFO0: ITM_bytecount Position /
AnnaBridge	167:e84263d55307	1403	#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /!< TPI FIFO0: ITM_bytecount Mask /
AnnaBridge	167:e84263d55307	1404
AnnaBridge	167:e84263d55307	1405	#define TPI_FIFO0_ETM_ATVALID_Pos 26U /!< TPI FIFO0: ETM_ATVALID Position /
AnnaBridge	167:e84263d55307	1406	#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /!< TPI FIFO0: ETM_ATVALID Mask /
AnnaBridge	167:e84263d55307	1407
AnnaBridge	167:e84263d55307	1408	#define TPI_FIFO0_ETM_bytecount_Pos 24U /!< TPI FIFO0: ETM_bytecount Position /
AnnaBridge	167:e84263d55307	1409	#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /!< TPI FIFO0: ETM_bytecount Mask /
AnnaBridge	167:e84263d55307	1410
AnnaBridge	167:e84263d55307	1411	#define TPI_FIFO0_ETM2_Pos 16U /!< TPI FIFO0: ETM2 Position /
AnnaBridge	167:e84263d55307	1412	#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /!< TPI FIFO0: ETM2 Mask /
AnnaBridge	167:e84263d55307	1413
AnnaBridge	167:e84263d55307	1414	#define TPI_FIFO0_ETM1_Pos 8U /!< TPI FIFO0: ETM1 Position /
AnnaBridge	167:e84263d55307	1415	#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /!< TPI FIFO0: ETM1 Mask /
AnnaBridge	167:e84263d55307	1416
AnnaBridge	167:e84263d55307	1417	#define TPI_FIFO0_ETM0_Pos 0U /!< TPI FIFO0: ETM0 Position /
AnnaBridge	167:e84263d55307	1418	#define TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/) /!< TPI FIFO0: ETM0 Mask /
AnnaBridge	167:e84263d55307	1419
AnnaBridge	167:e84263d55307	1420	/* TPI ITATBCTR2 Register Definitions */
AnnaBridge	167:e84263d55307	1421	#define TPI_ITATBCTR2_ATREADY_Pos 0U /!< TPI ITATBCTR2: ATREADY Position /
AnnaBridge	167:e84263d55307	1422	#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY_Pos/) /!< TPI ITATBCTR2: ATREADY Mask /
AnnaBridge	167:e84263d55307	1423
AnnaBridge	167:e84263d55307	1424	/* TPI Integration ITM Data Register Definitions (FIFO1) */
AnnaBridge	167:e84263d55307	1425	#define TPI_FIFO1_ITM_ATVALID_Pos 29U /!< TPI FIFO1: ITM_ATVALID Position /
AnnaBridge	167:e84263d55307	1426	#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /!< TPI FIFO1: ITM_ATVALID Mask /
AnnaBridge	167:e84263d55307	1427
AnnaBridge	167:e84263d55307	1428	#define TPI_FIFO1_ITM_bytecount_Pos 27U /!< TPI FIFO1: ITM_bytecount Position /
AnnaBridge	167:e84263d55307	1429	#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /!< TPI FIFO1: ITM_bytecount Mask /
AnnaBridge	167:e84263d55307	1430
AnnaBridge	167:e84263d55307	1431	#define TPI_FIFO1_ETM_ATVALID_Pos 26U /!< TPI FIFO1: ETM_ATVALID Position /
AnnaBridge	167:e84263d55307	1432	#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /!< TPI FIFO1: ETM_ATVALID Mask /
AnnaBridge	167:e84263d55307	1433
AnnaBridge	167:e84263d55307	1434	#define TPI_FIFO1_ETM_bytecount_Pos 24U /!< TPI FIFO1: ETM_bytecount Position /
AnnaBridge	167:e84263d55307	1435	#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /!< TPI FIFO1: ETM_bytecount Mask /
AnnaBridge	167:e84263d55307	1436
AnnaBridge	167:e84263d55307	1437	#define TPI_FIFO1_ITM2_Pos 16U /!< TPI FIFO1: ITM2 Position /
AnnaBridge	167:e84263d55307	1438	#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /!< TPI FIFO1: ITM2 Mask /
AnnaBridge	167:e84263d55307	1439
AnnaBridge	167:e84263d55307	1440	#define TPI_FIFO1_ITM1_Pos 8U /!< TPI FIFO1: ITM1 Position /
AnnaBridge	167:e84263d55307	1441	#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /!< TPI FIFO1: ITM1 Mask /
AnnaBridge	167:e84263d55307	1442
AnnaBridge	167:e84263d55307	1443	#define TPI_FIFO1_ITM0_Pos 0U /!< TPI FIFO1: ITM0 Position /
AnnaBridge	167:e84263d55307	1444	#define TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/) /!< TPI FIFO1: ITM0 Mask /
AnnaBridge	167:e84263d55307	1445
AnnaBridge	167:e84263d55307	1446	/* TPI ITATBCTR0 Register Definitions */
AnnaBridge	167:e84263d55307	1447	#define TPI_ITATBCTR0_ATREADY_Pos 0U /!< TPI ITATBCTR0: ATREADY Position /
AnnaBridge	167:e84263d55307	1448	#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY_Pos/) /!< TPI ITATBCTR0: ATREADY Mask /
AnnaBridge	167:e84263d55307	1449
AnnaBridge	167:e84263d55307	1450	/* TPI Integration Mode Control Register Definitions */
AnnaBridge	167:e84263d55307	1451	#define TPI_ITCTRL_Mode_Pos 0U /!< TPI ITCTRL: Mode Position /
AnnaBridge	167:e84263d55307	1452	#define TPI_ITCTRL_Mode_Msk (0x1UL /<< TPI_ITCTRL_Mode_Pos/) /!< TPI ITCTRL: Mode Mask /
AnnaBridge	167:e84263d55307	1453
AnnaBridge	167:e84263d55307	1454	/* TPI DEVID Register Definitions */
AnnaBridge	167:e84263d55307	1455	#define TPI_DEVID_NRZVALID_Pos 11U /!< TPI DEVID: NRZVALID Position /
AnnaBridge	167:e84263d55307	1456	#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /!< TPI DEVID: NRZVALID Mask /
AnnaBridge	167:e84263d55307	1457
AnnaBridge	167:e84263d55307	1458	#define TPI_DEVID_MANCVALID_Pos 10U /!< TPI DEVID: MANCVALID Position /
AnnaBridge	167:e84263d55307	1459	#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /!< TPI DEVID: MANCVALID Mask /
AnnaBridge	167:e84263d55307	1460
AnnaBridge	167:e84263d55307	1461	#define TPI_DEVID_PTINVALID_Pos 9U /!< TPI DEVID: PTINVALID Position /
AnnaBridge	167:e84263d55307	1462	#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /!< TPI DEVID: PTINVALID Mask /
AnnaBridge	167:e84263d55307	1463
AnnaBridge	167:e84263d55307	1464	#define TPI_DEVID_MinBufSz_Pos 6U /!< TPI DEVID: MinBufSz Position /
AnnaBridge	167:e84263d55307	1465	#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /!< TPI DEVID: MinBufSz Mask /
AnnaBridge	167:e84263d55307	1466
AnnaBridge	167:e84263d55307	1467	#define TPI_DEVID_AsynClkIn_Pos 5U /!< TPI DEVID: AsynClkIn Position /
AnnaBridge	167:e84263d55307	1468	#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /!< TPI DEVID: AsynClkIn Mask /
AnnaBridge	167:e84263d55307	1469
AnnaBridge	167:e84263d55307	1470	#define TPI_DEVID_NrTraceInput_Pos 0U /!< TPI DEVID: NrTraceInput Position /
AnnaBridge	167:e84263d55307	1471	#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/) /!< TPI DEVID: NrTraceInput Mask /
AnnaBridge	167:e84263d55307	1472
AnnaBridge	167:e84263d55307	1473	/* TPI DEVTYPE Register Definitions */
AnnaBridge	167:e84263d55307	1474	#define TPI_DEVTYPE_MajorType_Pos 4U /!< TPI DEVTYPE: MajorType Position /
AnnaBridge	167:e84263d55307	1475	#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /!< TPI DEVTYPE: MajorType Mask /
AnnaBridge	167:e84263d55307	1476
AnnaBridge	167:e84263d55307	1477	#define TPI_DEVTYPE_SubType_Pos 0U /!< TPI DEVTYPE: SubType Position /
AnnaBridge	167:e84263d55307	1478	#define TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/) /!< TPI DEVTYPE: SubType Mask /
AnnaBridge	167:e84263d55307	1479
AnnaBridge	167:e84263d55307	1480	/@}/ /* end of group CMSIS_TPI */
AnnaBridge	167:e84263d55307	1481
AnnaBridge	167:e84263d55307	1482
AnnaBridge	167:e84263d55307	1483	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge	167:e84263d55307	1484	/**
AnnaBridge	167:e84263d55307	1485	\ingroup CMSIS_core_register
AnnaBridge	167:e84263d55307	1486	\defgroup CMSIS_MPU Memory Protection Unit (MPU)
AnnaBridge	167:e84263d55307	1487	\brief Type definitions for the Memory Protection Unit (MPU)
AnnaBridge	167:e84263d55307	1488	@{
AnnaBridge	167:e84263d55307	1489	*/
AnnaBridge	167:e84263d55307	1490
AnnaBridge	167:e84263d55307	1491	/**
AnnaBridge	167:e84263d55307	1492	\brief Structure type to access the Memory Protection Unit (MPU).
AnnaBridge	167:e84263d55307	1493	*/
AnnaBridge	167:e84263d55307	1494	typedef struct
AnnaBridge	167:e84263d55307	1495	{
AnnaBridge	167:e84263d55307	1496	__IM uint32_t TYPE; /!< Offset: 0x000 (R/ ) MPU Type Register /
AnnaBridge	167:e84263d55307	1497	__IOM uint32_t CTRL; /!< Offset: 0x004 (R/W) MPU Control Register /
AnnaBridge	167:e84263d55307	1498	__IOM uint32_t RNR; /!< Offset: 0x008 (R/W) MPU Region Number Register /
AnnaBridge	167:e84263d55307	1499	__IOM uint32_t RBAR; /!< Offset: 0x00C (R/W) MPU Region Base Address Register /
AnnaBridge	167:e84263d55307	1500	__IOM uint32_t RLAR; /!< Offset: 0x010 (R/W) MPU Region Limit Address Register /
AnnaBridge	167:e84263d55307	1501	__IOM uint32_t RBAR_A1; /!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 /
AnnaBridge	167:e84263d55307	1502	__IOM uint32_t RLAR_A1; /!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 /
AnnaBridge	167:e84263d55307	1503	__IOM uint32_t RBAR_A2; /!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 /
AnnaBridge	167:e84263d55307	1504	__IOM uint32_t RLAR_A2; /!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 /
AnnaBridge	167:e84263d55307	1505	__IOM uint32_t RBAR_A3; /!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 /
AnnaBridge	167:e84263d55307	1506	__IOM uint32_t RLAR_A3; /!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 /
AnnaBridge	167:e84263d55307	1507	uint32_t RESERVED0[1];
AnnaBridge	167:e84263d55307	1508	__IOM uint32_t MAIR0; /!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 /
AnnaBridge	167:e84263d55307	1509	__IOM uint32_t MAIR1; /!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 /
AnnaBridge	167:e84263d55307	1510	} MPU_Type;
AnnaBridge	167:e84263d55307	1511
AnnaBridge	167:e84263d55307	1512	/* MPU Type Register Definitions */
AnnaBridge	167:e84263d55307	1513	#define MPU_TYPE_IREGION_Pos 16U /!< MPU TYPE: IREGION Position /
AnnaBridge	167:e84263d55307	1514	#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
AnnaBridge	167:e84263d55307	1515
AnnaBridge	167:e84263d55307	1516	#define MPU_TYPE_DREGION_Pos 8U /!< MPU TYPE: DREGION Position /
AnnaBridge	167:e84263d55307	1517	#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
AnnaBridge	167:e84263d55307	1518
AnnaBridge	167:e84263d55307	1519	#define MPU_TYPE_SEPARATE_Pos 0U /!< MPU TYPE: SEPARATE Position /
AnnaBridge	167:e84263d55307	1520	#define MPU_TYPE_SEPARATE_Msk (1UL /<< MPU_TYPE_SEPARATE_Pos/) /!< MPU TYPE: SEPARATE Mask /
AnnaBridge	167:e84263d55307	1521
AnnaBridge	167:e84263d55307	1522	/* MPU Control Register Definitions */
AnnaBridge	167:e84263d55307	1523	#define MPU_CTRL_PRIVDEFENA_Pos 2U /!< MPU CTRL: PRIVDEFENA Position /
AnnaBridge	167:e84263d55307	1524	#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
AnnaBridge	167:e84263d55307	1525
AnnaBridge	167:e84263d55307	1526	#define MPU_CTRL_HFNMIENA_Pos 1U /!< MPU CTRL: HFNMIENA Position /
AnnaBridge	167:e84263d55307	1527	#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
AnnaBridge	167:e84263d55307	1528
AnnaBridge	167:e84263d55307	1529	#define MPU_CTRL_ENABLE_Pos 0U /!< MPU CTRL: ENABLE Position /
AnnaBridge	167:e84263d55307	1530	#define MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/) /!< MPU CTRL: ENABLE Mask /
AnnaBridge	167:e84263d55307	1531
AnnaBridge	167:e84263d55307	1532	/* MPU Region Number Register Definitions */
AnnaBridge	167:e84263d55307	1533	#define MPU_RNR_REGION_Pos 0U /!< MPU RNR: REGION Position /
AnnaBridge	167:e84263d55307	1534	#define MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/) /!< MPU RNR: REGION Mask /
AnnaBridge	167:e84263d55307	1535
AnnaBridge	167:e84263d55307	1536	/* MPU Region Base Address Register Definitions */
AnnaBridge	167:e84263d55307	1537	#define MPU_RBAR_ADDR_Pos 5U /!< MPU RBAR: ADDR Position /
AnnaBridge	167:e84263d55307	1538	#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /!< MPU RBAR: ADDR Mask /
AnnaBridge	167:e84263d55307	1539
AnnaBridge	167:e84263d55307	1540	#define MPU_RBAR_SH_Pos 3U /!< MPU RBAR: SH Position /
AnnaBridge	167:e84263d55307	1541	#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /!< MPU RBAR: SH Mask /
AnnaBridge	167:e84263d55307	1542
AnnaBridge	167:e84263d55307	1543	#define MPU_RBAR_AP_Pos 1U /!< MPU RBAR: AP Position /
AnnaBridge	167:e84263d55307	1544	#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /!< MPU RBAR: AP Mask /
AnnaBridge	167:e84263d55307	1545
AnnaBridge	167:e84263d55307	1546	#define MPU_RBAR_XN_Pos 0U /!< MPU RBAR: XN Position /
AnnaBridge	167:e84263d55307	1547	#define MPU_RBAR_XN_Msk (01UL /<< MPU_RBAR_XN_Pos/) /!< MPU RBAR: XN Mask /
AnnaBridge	167:e84263d55307	1548
AnnaBridge	167:e84263d55307	1549	/* MPU Region Limit Address Register Definitions */
AnnaBridge	167:e84263d55307	1550	#define MPU_RLAR_LIMIT_Pos 5U /!< MPU RLAR: LIMIT Position /
AnnaBridge	167:e84263d55307	1551	#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /!< MPU RLAR: LIMIT Mask /
AnnaBridge	167:e84263d55307	1552
AnnaBridge	167:e84263d55307	1553	#define MPU_RLAR_AttrIndx_Pos 1U /!< MPU RLAR: AttrIndx Position /
AnnaBridge	167:e84263d55307	1554	#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /!< MPU RLAR: AttrIndx Mask /
AnnaBridge	167:e84263d55307	1555
AnnaBridge	167:e84263d55307	1556	#define MPU_RLAR_EN_Pos 0U /!< MPU RLAR: Region enable bit Position /
AnnaBridge	167:e84263d55307	1557	#define MPU_RLAR_EN_Msk (1UL /<< MPU_RLAR_EN_Pos/) /!< MPU RLAR: Region enable bit Disable Mask /
AnnaBridge	167:e84263d55307	1558
AnnaBridge	167:e84263d55307	1559	/* MPU Memory Attribute Indirection Register 0 Definitions */
AnnaBridge	167:e84263d55307	1560	#define MPU_MAIR0_Attr3_Pos 24U /!< MPU MAIR0: Attr3 Position /
AnnaBridge	167:e84263d55307	1561	#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /!< MPU MAIR0: Attr3 Mask /
AnnaBridge	167:e84263d55307	1562
AnnaBridge	167:e84263d55307	1563	#define MPU_MAIR0_Attr2_Pos 16U /!< MPU MAIR0: Attr2 Position /
AnnaBridge	167:e84263d55307	1564	#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /!< MPU MAIR0: Attr2 Mask /
AnnaBridge	167:e84263d55307	1565
AnnaBridge	167:e84263d55307	1566	#define MPU_MAIR0_Attr1_Pos 8U /!< MPU MAIR0: Attr1 Position /
AnnaBridge	167:e84263d55307	1567	#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /!< MPU MAIR0: Attr1 Mask /
AnnaBridge	167:e84263d55307	1568
AnnaBridge	167:e84263d55307	1569	#define MPU_MAIR0_Attr0_Pos 0U /!< MPU MAIR0: Attr0 Position /
AnnaBridge	167:e84263d55307	1570	#define MPU_MAIR0_Attr0_Msk (0xFFUL /<< MPU_MAIR0_Attr0_Pos/) /!< MPU MAIR0: Attr0 Mask /
AnnaBridge	167:e84263d55307	1571
AnnaBridge	167:e84263d55307	1572	/* MPU Memory Attribute Indirection Register 1 Definitions */
AnnaBridge	167:e84263d55307	1573	#define MPU_MAIR1_Attr7_Pos 24U /!< MPU MAIR1: Attr7 Position /
AnnaBridge	167:e84263d55307	1574	#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /!< MPU MAIR1: Attr7 Mask /
AnnaBridge	167:e84263d55307	1575
AnnaBridge	167:e84263d55307	1576	#define MPU_MAIR1_Attr6_Pos 16U /!< MPU MAIR1: Attr6 Position /
AnnaBridge	167:e84263d55307	1577	#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /!< MPU MAIR1: Attr6 Mask /
AnnaBridge	167:e84263d55307	1578
AnnaBridge	167:e84263d55307	1579	#define MPU_MAIR1_Attr5_Pos 8U /!< MPU MAIR1: Attr5 Position /
AnnaBridge	167:e84263d55307	1580	#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /!< MPU MAIR1: Attr5 Mask /
AnnaBridge	167:e84263d55307	1581
AnnaBridge	167:e84263d55307	1582	#define MPU_MAIR1_Attr4_Pos 0U /!< MPU MAIR1: Attr4 Position /
AnnaBridge	167:e84263d55307	1583	#define MPU_MAIR1_Attr4_Msk (0xFFUL /<< MPU_MAIR1_Attr4_Pos/) /!< MPU MAIR1: Attr4 Mask /
AnnaBridge	167:e84263d55307	1584
AnnaBridge	167:e84263d55307	1585	/@} end of group CMSIS_MPU /
AnnaBridge	167:e84263d55307	1586	#endif
AnnaBridge	167:e84263d55307	1587
AnnaBridge	167:e84263d55307	1588
AnnaBridge	167:e84263d55307	1589	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge	167:e84263d55307	1590	/**
AnnaBridge	167:e84263d55307	1591	\ingroup CMSIS_core_register
AnnaBridge	167:e84263d55307	1592	\defgroup CMSIS_SAU Security Attribution Unit (SAU)
AnnaBridge	167:e84263d55307	1593	\brief Type definitions for the Security Attribution Unit (SAU)
AnnaBridge	167:e84263d55307	1594	@{
AnnaBridge	167:e84263d55307	1595	*/
AnnaBridge	167:e84263d55307	1596
AnnaBridge	167:e84263d55307	1597	/**
AnnaBridge	167:e84263d55307	1598	\brief Structure type to access the Security Attribution Unit (SAU).
AnnaBridge	167:e84263d55307	1599	*/
AnnaBridge	167:e84263d55307	1600	typedef struct
AnnaBridge	167:e84263d55307	1601	{
AnnaBridge	167:e84263d55307	1602	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) SAU Control Register /
AnnaBridge	167:e84263d55307	1603	__IM uint32_t TYPE; /!< Offset: 0x004 (R/ ) SAU Type Register /
AnnaBridge	167:e84263d55307	1604	#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
AnnaBridge	167:e84263d55307	1605	__IOM uint32_t RNR; /!< Offset: 0x008 (R/W) SAU Region Number Register /
AnnaBridge	167:e84263d55307	1606	__IOM uint32_t RBAR; /!< Offset: 0x00C (R/W) SAU Region Base Address Register /
AnnaBridge	167:e84263d55307	1607	__IOM uint32_t RLAR; /!< Offset: 0x010 (R/W) SAU Region Limit Address Register /
AnnaBridge	167:e84263d55307	1608	#else
AnnaBridge	167:e84263d55307	1609	uint32_t RESERVED0[3];
AnnaBridge	167:e84263d55307	1610	#endif
AnnaBridge	167:e84263d55307	1611	__IOM uint32_t SFSR; /!< Offset: 0x014 (R/W) Secure Fault Status Register /
AnnaBridge	167:e84263d55307	1612	__IOM uint32_t SFAR; /!< Offset: 0x018 (R/W) Secure Fault Address Register /
AnnaBridge	167:e84263d55307	1613	} SAU_Type;
AnnaBridge	167:e84263d55307	1614
AnnaBridge	167:e84263d55307	1615	/* SAU Control Register Definitions */
AnnaBridge	167:e84263d55307	1616	#define SAU_CTRL_ALLNS_Pos 1U /!< SAU CTRL: ALLNS Position /
AnnaBridge	167:e84263d55307	1617	#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /!< SAU CTRL: ALLNS Mask /
AnnaBridge	167:e84263d55307	1618
AnnaBridge	167:e84263d55307	1619	#define SAU_CTRL_ENABLE_Pos 0U /!< SAU CTRL: ENABLE Position /
AnnaBridge	167:e84263d55307	1620	#define SAU_CTRL_ENABLE_Msk (1UL /<< SAU_CTRL_ENABLE_Pos/) /!< SAU CTRL: ENABLE Mask /
AnnaBridge	167:e84263d55307	1621
AnnaBridge	167:e84263d55307	1622	/* SAU Type Register Definitions */
AnnaBridge	167:e84263d55307	1623	#define SAU_TYPE_SREGION_Pos 0U /!< SAU TYPE: SREGION Position /
AnnaBridge	167:e84263d55307	1624	#define SAU_TYPE_SREGION_Msk (0xFFUL /<< SAU_TYPE_SREGION_Pos/) /!< SAU TYPE: SREGION Mask /
AnnaBridge	167:e84263d55307	1625
AnnaBridge	167:e84263d55307	1626	#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
AnnaBridge	167:e84263d55307	1627	/* SAU Region Number Register Definitions */
AnnaBridge	167:e84263d55307	1628	#define SAU_RNR_REGION_Pos 0U /!< SAU RNR: REGION Position /
AnnaBridge	167:e84263d55307	1629	#define SAU_RNR_REGION_Msk (0xFFUL /<< SAU_RNR_REGION_Pos/) /!< SAU RNR: REGION Mask /
AnnaBridge	167:e84263d55307	1630
AnnaBridge	167:e84263d55307	1631	/* SAU Region Base Address Register Definitions */
AnnaBridge	167:e84263d55307	1632	#define SAU_RBAR_BADDR_Pos 5U /!< SAU RBAR: BADDR Position /
AnnaBridge	167:e84263d55307	1633	#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /!< SAU RBAR: BADDR Mask /
AnnaBridge	167:e84263d55307	1634
AnnaBridge	167:e84263d55307	1635	/* SAU Region Limit Address Register Definitions */
AnnaBridge	167:e84263d55307	1636	#define SAU_RLAR_LADDR_Pos 5U /!< SAU RLAR: LADDR Position /
AnnaBridge	167:e84263d55307	1637	#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /!< SAU RLAR: LADDR Mask /
AnnaBridge	167:e84263d55307	1638
AnnaBridge	167:e84263d55307	1639	#define SAU_RLAR_NSC_Pos 1U /!< SAU RLAR: NSC Position /
AnnaBridge	167:e84263d55307	1640	#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /!< SAU RLAR: NSC Mask /
AnnaBridge	167:e84263d55307	1641
AnnaBridge	167:e84263d55307	1642	#define SAU_RLAR_ENABLE_Pos 0U /!< SAU RLAR: ENABLE Position /
AnnaBridge	167:e84263d55307	1643	#define SAU_RLAR_ENABLE_Msk (1UL /<< SAU_RLAR_ENABLE_Pos/) /!< SAU RLAR: ENABLE Mask /
AnnaBridge	167:e84263d55307	1644
AnnaBridge	167:e84263d55307	1645	#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
AnnaBridge	167:e84263d55307	1646
AnnaBridge	167:e84263d55307	1647	/* Secure Fault Status Register Definitions */
AnnaBridge	167:e84263d55307	1648	#define SAU_SFSR_LSERR_Pos 7U /!< SAU SFSR: LSERR Position /
AnnaBridge	167:e84263d55307	1649	#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /!< SAU SFSR: LSERR Mask /
AnnaBridge	167:e84263d55307	1650
AnnaBridge	167:e84263d55307	1651	#define SAU_SFSR_SFARVALID_Pos 6U /!< SAU SFSR: SFARVALID Position /
AnnaBridge	167:e84263d55307	1652	#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /!< SAU SFSR: SFARVALID Mask /
AnnaBridge	167:e84263d55307	1653
AnnaBridge	167:e84263d55307	1654	#define SAU_SFSR_LSPERR_Pos 5U /!< SAU SFSR: LSPERR Position /
AnnaBridge	167:e84263d55307	1655	#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /!< SAU SFSR: LSPERR Mask /
AnnaBridge	167:e84263d55307	1656
AnnaBridge	167:e84263d55307	1657	#define SAU_SFSR_INVTRAN_Pos 4U /!< SAU SFSR: INVTRAN Position /
AnnaBridge	167:e84263d55307	1658	#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /!< SAU SFSR: INVTRAN Mask /
AnnaBridge	167:e84263d55307	1659
AnnaBridge	167:e84263d55307	1660	#define SAU_SFSR_AUVIOL_Pos 3U /!< SAU SFSR: AUVIOL Position /
AnnaBridge	167:e84263d55307	1661	#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /!< SAU SFSR: AUVIOL Mask /
AnnaBridge	167:e84263d55307	1662
AnnaBridge	167:e84263d55307	1663	#define SAU_SFSR_INVER_Pos 2U /!< SAU SFSR: INVER Position /
AnnaBridge	167:e84263d55307	1664	#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /!< SAU SFSR: INVER Mask /
AnnaBridge	167:e84263d55307	1665
AnnaBridge	167:e84263d55307	1666	#define SAU_SFSR_INVIS_Pos 1U /!< SAU SFSR: INVIS Position /
AnnaBridge	167:e84263d55307	1667	#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /!< SAU SFSR: INVIS Mask /
AnnaBridge	167:e84263d55307	1668
AnnaBridge	167:e84263d55307	1669	#define SAU_SFSR_INVEP_Pos 0U /!< SAU SFSR: INVEP Position /
AnnaBridge	167:e84263d55307	1670	#define SAU_SFSR_INVEP_Msk (1UL /<< SAU_SFSR_INVEP_Pos/) /!< SAU SFSR: INVEP Mask /
AnnaBridge	167:e84263d55307	1671
AnnaBridge	167:e84263d55307	1672	/@} end of group CMSIS_SAU /
AnnaBridge	167:e84263d55307	1673	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
AnnaBridge	167:e84263d55307	1674
AnnaBridge	167:e84263d55307	1675
AnnaBridge	167:e84263d55307	1676	/**
AnnaBridge	167:e84263d55307	1677	\ingroup CMSIS_core_register
AnnaBridge	167:e84263d55307	1678	\defgroup CMSIS_FPU Floating Point Unit (FPU)
AnnaBridge	167:e84263d55307	1679	\brief Type definitions for the Floating Point Unit (FPU)
AnnaBridge	167:e84263d55307	1680	@{
AnnaBridge	167:e84263d55307	1681	*/
AnnaBridge	167:e84263d55307	1682
AnnaBridge	167:e84263d55307	1683	/**
AnnaBridge	167:e84263d55307	1684	\brief Structure type to access the Floating Point Unit (FPU).
AnnaBridge	167:e84263d55307	1685	*/
AnnaBridge	167:e84263d55307	1686	typedef struct
AnnaBridge	167:e84263d55307	1687	{
AnnaBridge	167:e84263d55307	1688	uint32_t RESERVED0[1U];
AnnaBridge	167:e84263d55307	1689	__IOM uint32_t FPCCR; /!< Offset: 0x004 (R/W) Floating-Point Context Control Register /
AnnaBridge	167:e84263d55307	1690	__IOM uint32_t FPCAR; /!< Offset: 0x008 (R/W) Floating-Point Context Address Register /
AnnaBridge	167:e84263d55307	1691	__IOM uint32_t FPDSCR; /!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register /
AnnaBridge	167:e84263d55307	1692	__IM uint32_t MVFR0; /!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 /
AnnaBridge	167:e84263d55307	1693	__IM uint32_t MVFR1; /!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 /
AnnaBridge	167:e84263d55307	1694	} FPU_Type;
AnnaBridge	167:e84263d55307	1695
AnnaBridge	167:e84263d55307	1696	/* Floating-Point Context Control Register Definitions */
AnnaBridge	167:e84263d55307	1697	#define FPU_FPCCR_ASPEN_Pos 31U /!< FPCCR: ASPEN bit Position /
AnnaBridge	167:e84263d55307	1698	#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /!< FPCCR: ASPEN bit Mask /
AnnaBridge	167:e84263d55307	1699
AnnaBridge	167:e84263d55307	1700	#define FPU_FPCCR_LSPEN_Pos 30U /!< FPCCR: LSPEN Position /
AnnaBridge	167:e84263d55307	1701	#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /!< FPCCR: LSPEN bit Mask /
AnnaBridge	167:e84263d55307	1702
AnnaBridge	167:e84263d55307	1703	#define FPU_FPCCR_LSPENS_Pos 29U /!< FPCCR: LSPENS Position /
AnnaBridge	167:e84263d55307	1704	#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /!< FPCCR: LSPENS bit Mask /
AnnaBridge	167:e84263d55307	1705
AnnaBridge	167:e84263d55307	1706	#define FPU_FPCCR_CLRONRET_Pos 28U /!< FPCCR: CLRONRET Position /
AnnaBridge	167:e84263d55307	1707	#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /!< FPCCR: CLRONRET bit Mask /
AnnaBridge	167:e84263d55307	1708
AnnaBridge	167:e84263d55307	1709	#define FPU_FPCCR_CLRONRETS_Pos 27U /!< FPCCR: CLRONRETS Position /
AnnaBridge	167:e84263d55307	1710	#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /!< FPCCR: CLRONRETS bit Mask /
AnnaBridge	167:e84263d55307	1711
AnnaBridge	167:e84263d55307	1712	#define FPU_FPCCR_TS_Pos 26U /!< FPCCR: TS Position /
AnnaBridge	167:e84263d55307	1713	#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /!< FPCCR: TS bit Mask /
AnnaBridge	167:e84263d55307	1714
AnnaBridge	167:e84263d55307	1715	#define FPU_FPCCR_UFRDY_Pos 10U /!< FPCCR: UFRDY Position /
AnnaBridge	167:e84263d55307	1716	#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /!< FPCCR: UFRDY bit Mask /
AnnaBridge	167:e84263d55307	1717
AnnaBridge	167:e84263d55307	1718	#define FPU_FPCCR_SPLIMVIOL_Pos 9U /!< FPCCR: SPLIMVIOL Position /
AnnaBridge	167:e84263d55307	1719	#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /!< FPCCR: SPLIMVIOL bit Mask /
AnnaBridge	167:e84263d55307	1720
AnnaBridge	167:e84263d55307	1721	#define FPU_FPCCR_MONRDY_Pos 8U /!< FPCCR: MONRDY Position /
AnnaBridge	167:e84263d55307	1722	#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /!< FPCCR: MONRDY bit Mask /
AnnaBridge	167:e84263d55307	1723
AnnaBridge	167:e84263d55307	1724	#define FPU_FPCCR_SFRDY_Pos 7U /!< FPCCR: SFRDY Position /
AnnaBridge	167:e84263d55307	1725	#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /!< FPCCR: SFRDY bit Mask /
AnnaBridge	167:e84263d55307	1726
AnnaBridge	167:e84263d55307	1727	#define FPU_FPCCR_BFRDY_Pos 6U /!< FPCCR: BFRDY Position /
AnnaBridge	167:e84263d55307	1728	#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /!< FPCCR: BFRDY bit Mask /
AnnaBridge	167:e84263d55307	1729
AnnaBridge	167:e84263d55307	1730	#define FPU_FPCCR_MMRDY_Pos 5U /!< FPCCR: MMRDY Position /
AnnaBridge	167:e84263d55307	1731	#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /!< FPCCR: MMRDY bit Mask /
AnnaBridge	167:e84263d55307	1732
AnnaBridge	167:e84263d55307	1733	#define FPU_FPCCR_HFRDY_Pos 4U /!< FPCCR: HFRDY Position /
AnnaBridge	167:e84263d55307	1734	#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /!< FPCCR: HFRDY bit Mask /
AnnaBridge	167:e84263d55307	1735
AnnaBridge	167:e84263d55307	1736	#define FPU_FPCCR_THREAD_Pos 3U /!< FPCCR: processor mode bit Position /
AnnaBridge	167:e84263d55307	1737	#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /!< FPCCR: processor mode active bit Mask /
AnnaBridge	167:e84263d55307	1738
AnnaBridge	167:e84263d55307	1739	#define FPU_FPCCR_S_Pos 2U /!< FPCCR: Security status of the FP context bit Position /
AnnaBridge	167:e84263d55307	1740	#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /!< FPCCR: Security status of the FP context bit Mask /
AnnaBridge	167:e84263d55307	1741
AnnaBridge	167:e84263d55307	1742	#define FPU_FPCCR_USER_Pos 1U /!< FPCCR: privilege level bit Position /
AnnaBridge	167:e84263d55307	1743	#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /!< FPCCR: privilege level bit Mask /
AnnaBridge	167:e84263d55307	1744
AnnaBridge	167:e84263d55307	1745	#define FPU_FPCCR_LSPACT_Pos 0U /!< FPCCR: Lazy state preservation active bit Position /
AnnaBridge	167:e84263d55307	1746	#define FPU_FPCCR_LSPACT_Msk (1UL /<< FPU_FPCCR_LSPACT_Pos/) /!< FPCCR: Lazy state preservation active bit Mask /
AnnaBridge	167:e84263d55307	1747
AnnaBridge	167:e84263d55307	1748	/* Floating-Point Context Address Register Definitions */
AnnaBridge	167:e84263d55307	1749	#define FPU_FPCAR_ADDRESS_Pos 3U /!< FPCAR: ADDRESS bit Position /
AnnaBridge	167:e84263d55307	1750	#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /!< FPCAR: ADDRESS bit Mask /
AnnaBridge	167:e84263d55307	1751
AnnaBridge	167:e84263d55307	1752	/* Floating-Point Default Status Control Register Definitions */
AnnaBridge	167:e84263d55307	1753	#define FPU_FPDSCR_AHP_Pos 26U /!< FPDSCR: AHP bit Position /
AnnaBridge	167:e84263d55307	1754	#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /!< FPDSCR: AHP bit Mask /
AnnaBridge	167:e84263d55307	1755
AnnaBridge	167:e84263d55307	1756	#define FPU_FPDSCR_DN_Pos 25U /!< FPDSCR: DN bit Position /
AnnaBridge	167:e84263d55307	1757	#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /!< FPDSCR: DN bit Mask /
AnnaBridge	167:e84263d55307	1758
AnnaBridge	167:e84263d55307	1759	#define FPU_FPDSCR_FZ_Pos 24U /!< FPDSCR: FZ bit Position /
AnnaBridge	167:e84263d55307	1760	#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /!< FPDSCR: FZ bit Mask /
AnnaBridge	167:e84263d55307	1761
AnnaBridge	167:e84263d55307	1762	#define FPU_FPDSCR_RMode_Pos 22U /!< FPDSCR: RMode bit Position /
AnnaBridge	167:e84263d55307	1763	#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /!< FPDSCR: RMode bit Mask /
AnnaBridge	167:e84263d55307	1764
AnnaBridge	167:e84263d55307	1765	/* Media and FP Feature Register 0 Definitions */
AnnaBridge	167:e84263d55307	1766	#define FPU_MVFR0_FP_rounding_modes_Pos 28U /!< MVFR0: FP rounding modes bits Position /
AnnaBridge	167:e84263d55307	1767	#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /!< MVFR0: FP rounding modes bits Mask /
AnnaBridge	167:e84263d55307	1768
AnnaBridge	167:e84263d55307	1769	#define FPU_MVFR0_Short_vectors_Pos 24U /!< MVFR0: Short vectors bits Position /
AnnaBridge	167:e84263d55307	1770	#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /!< MVFR0: Short vectors bits Mask /
AnnaBridge	167:e84263d55307	1771
AnnaBridge	167:e84263d55307	1772	#define FPU_MVFR0_Square_root_Pos 20U /!< MVFR0: Square root bits Position /
AnnaBridge	167:e84263d55307	1773	#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /!< MVFR0: Square root bits Mask /
AnnaBridge	167:e84263d55307	1774
AnnaBridge	167:e84263d55307	1775	#define FPU_MVFR0_Divide_Pos 16U /!< MVFR0: Divide bits Position /
AnnaBridge	167:e84263d55307	1776	#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /!< MVFR0: Divide bits Mask /
AnnaBridge	167:e84263d55307	1777
AnnaBridge	167:e84263d55307	1778	#define FPU_MVFR0_FP_excep_trapping_Pos 12U /!< MVFR0: FP exception trapping bits Position /
AnnaBridge	167:e84263d55307	1779	#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /!< MVFR0: FP exception trapping bits Mask /
AnnaBridge	167:e84263d55307	1780
AnnaBridge	167:e84263d55307	1781	#define FPU_MVFR0_Double_precision_Pos 8U /!< MVFR0: Double-precision bits Position /
AnnaBridge	167:e84263d55307	1782	#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /!< MVFR0: Double-precision bits Mask /
AnnaBridge	167:e84263d55307	1783
AnnaBridge	167:e84263d55307	1784	#define FPU_MVFR0_Single_precision_Pos 4U /!< MVFR0: Single-precision bits Position /
AnnaBridge	167:e84263d55307	1785	#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /!< MVFR0: Single-precision bits Mask /
AnnaBridge	167:e84263d55307	1786
AnnaBridge	167:e84263d55307	1787	#define FPU_MVFR0_A_SIMD_registers_Pos 0U /!< MVFR0: A_SIMD registers bits Position /
AnnaBridge	167:e84263d55307	1788	#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /<< FPU_MVFR0_A_SIMD_registers_Pos/) /!< MVFR0: A_SIMD registers bits Mask /
AnnaBridge	167:e84263d55307	1789
AnnaBridge	167:e84263d55307	1790	/* Media and FP Feature Register 1 Definitions */
AnnaBridge	167:e84263d55307	1791	#define FPU_MVFR1_FP_fused_MAC_Pos 28U /!< MVFR1: FP fused MAC bits Position /
AnnaBridge	167:e84263d55307	1792	#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /!< MVFR1: FP fused MAC bits Mask /
AnnaBridge	167:e84263d55307	1793
AnnaBridge	167:e84263d55307	1794	#define FPU_MVFR1_FP_HPFP_Pos 24U /!< MVFR1: FP HPFP bits Position /
AnnaBridge	167:e84263d55307	1795	#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /!< MVFR1: FP HPFP bits Mask /
AnnaBridge	167:e84263d55307	1796
AnnaBridge	167:e84263d55307	1797	#define FPU_MVFR1_D_NaN_mode_Pos 4U /!< MVFR1: D_NaN mode bits Position /
AnnaBridge	167:e84263d55307	1798	#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /!< MVFR1: D_NaN mode bits Mask /
AnnaBridge	167:e84263d55307	1799
AnnaBridge	167:e84263d55307	1800	#define FPU_MVFR1_FtZ_mode_Pos 0U /!< MVFR1: FtZ mode bits Position /
AnnaBridge	167:e84263d55307	1801	#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /<< FPU_MVFR1_FtZ_mode_Pos/) /!< MVFR1: FtZ mode bits Mask /
AnnaBridge	167:e84263d55307	1802
AnnaBridge	167:e84263d55307	1803	/@} end of group CMSIS_FPU /
AnnaBridge	167:e84263d55307	1804
AnnaBridge	167:e84263d55307	1805
AnnaBridge	167:e84263d55307	1806	/**
AnnaBridge	167:e84263d55307	1807	\ingroup CMSIS_core_register
AnnaBridge	167:e84263d55307	1808	\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
AnnaBridge	167:e84263d55307	1809	\brief Type definitions for the Core Debug Registers
AnnaBridge	167:e84263d55307	1810	@{
AnnaBridge	167:e84263d55307	1811	*/
AnnaBridge	167:e84263d55307	1812
AnnaBridge	167:e84263d55307	1813	/**
AnnaBridge	167:e84263d55307	1814	\brief Structure type to access the Core Debug Register (CoreDebug).
AnnaBridge	167:e84263d55307	1815	*/
AnnaBridge	167:e84263d55307	1816	typedef struct
AnnaBridge	167:e84263d55307	1817	{
AnnaBridge	167:e84263d55307	1818	__IOM uint32_t DHCSR; /!< Offset: 0x000 (R/W) Debug Halting Control and Status Register /
AnnaBridge	167:e84263d55307	1819	__OM uint32_t DCRSR; /!< Offset: 0x004 ( /W) Debug Core Register Selector Register /
AnnaBridge	167:e84263d55307	1820	__IOM uint32_t DCRDR; /!< Offset: 0x008 (R/W) Debug Core Register Data Register /
AnnaBridge	167:e84263d55307	1821	__IOM uint32_t DEMCR; /!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register /
AnnaBridge	167:e84263d55307	1822	uint32_t RESERVED4[1U];
AnnaBridge	167:e84263d55307	1823	__IOM uint32_t DAUTHCTRL; /!< Offset: 0x014 (R/W) Debug Authentication Control Register /
AnnaBridge	167:e84263d55307	1824	__IOM uint32_t DSCSR; /!< Offset: 0x018 (R/W) Debug Security Control and Status Register /
AnnaBridge	167:e84263d55307	1825	} CoreDebug_Type;
AnnaBridge	167:e84263d55307	1826
AnnaBridge	167:e84263d55307	1827	/* Debug Halting Control and Status Register Definitions */
AnnaBridge	167:e84263d55307	1828	#define CoreDebug_DHCSR_DBGKEY_Pos 16U /!< CoreDebug DHCSR: DBGKEY Position /
AnnaBridge	167:e84263d55307	1829	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
AnnaBridge	167:e84263d55307	1830
AnnaBridge	167:e84263d55307	1831	#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /!< CoreDebug DHCSR: S_RESTART_ST Position /
AnnaBridge	167:e84263d55307	1832	#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /!< CoreDebug DHCSR: S_RESTART_ST Mask /
AnnaBridge	167:e84263d55307	1833
AnnaBridge	167:e84263d55307	1834	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /!< CoreDebug DHCSR: S_RESET_ST Position /
AnnaBridge	167:e84263d55307	1835	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
AnnaBridge	167:e84263d55307	1836
AnnaBridge	167:e84263d55307	1837	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /!< CoreDebug DHCSR: S_RETIRE_ST Position /
AnnaBridge	167:e84263d55307	1838	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
AnnaBridge	167:e84263d55307	1839
AnnaBridge	167:e84263d55307	1840	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /!< CoreDebug DHCSR: S_LOCKUP Position /
AnnaBridge	167:e84263d55307	1841	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
AnnaBridge	167:e84263d55307	1842
AnnaBridge	167:e84263d55307	1843	#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /!< CoreDebug DHCSR: S_SLEEP Position /
AnnaBridge	167:e84263d55307	1844	#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
AnnaBridge	167:e84263d55307	1845
AnnaBridge	167:e84263d55307	1846	#define CoreDebug_DHCSR_S_HALT_Pos 17U /!< CoreDebug DHCSR: S_HALT Position /
AnnaBridge	167:e84263d55307	1847	#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
AnnaBridge	167:e84263d55307	1848
AnnaBridge	167:e84263d55307	1849	#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /!< CoreDebug DHCSR: S_REGRDY Position /
AnnaBridge	167:e84263d55307	1850	#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
AnnaBridge	167:e84263d55307	1851
AnnaBridge	167:e84263d55307	1852	#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /!< CoreDebug DHCSR: C_SNAPSTALL Position /
AnnaBridge	167:e84263d55307	1853	#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /!< CoreDebug DHCSR: C_SNAPSTALL Mask /
AnnaBridge	167:e84263d55307	1854
AnnaBridge	167:e84263d55307	1855	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /!< CoreDebug DHCSR: C_MASKINTS Position /
AnnaBridge	167:e84263d55307	1856	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
AnnaBridge	167:e84263d55307	1857
AnnaBridge	167:e84263d55307	1858	#define CoreDebug_DHCSR_C_STEP_Pos 2U /!< CoreDebug DHCSR: C_STEP Position /
AnnaBridge	167:e84263d55307	1859	#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
AnnaBridge	167:e84263d55307	1860
AnnaBridge	167:e84263d55307	1861	#define CoreDebug_DHCSR_C_HALT_Pos 1U /!< CoreDebug DHCSR: C_HALT Position /
AnnaBridge	167:e84263d55307	1862	#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
AnnaBridge	167:e84263d55307	1863
AnnaBridge	167:e84263d55307	1864	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /!< CoreDebug DHCSR: C_DEBUGEN Position /
AnnaBridge	167:e84263d55307	1865	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
AnnaBridge	167:e84263d55307	1866
AnnaBridge	167:e84263d55307	1867	/* Debug Core Register Selector Register Definitions */
AnnaBridge	167:e84263d55307	1868	#define CoreDebug_DCRSR_REGWnR_Pos 16U /!< CoreDebug DCRSR: REGWnR Position /
AnnaBridge	167:e84263d55307	1869	#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
AnnaBridge	167:e84263d55307	1870
AnnaBridge	167:e84263d55307	1871	#define CoreDebug_DCRSR_REGSEL_Pos 0U /!< CoreDebug DCRSR: REGSEL Position /
AnnaBridge	167:e84263d55307	1872	#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/) /!< CoreDebug DCRSR: REGSEL Mask /
AnnaBridge	167:e84263d55307	1873
AnnaBridge	167:e84263d55307	1874	/* Debug Exception and Monitor Control Register Definitions */
AnnaBridge	167:e84263d55307	1875	#define CoreDebug_DEMCR_TRCENA_Pos 24U /!< CoreDebug DEMCR: TRCENA Position /
AnnaBridge	167:e84263d55307	1876	#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /!< CoreDebug DEMCR: TRCENA Mask /
AnnaBridge	167:e84263d55307	1877
AnnaBridge	167:e84263d55307	1878	#define CoreDebug_DEMCR_MON_REQ_Pos 19U /!< CoreDebug DEMCR: MON_REQ Position /
AnnaBridge	167:e84263d55307	1879	#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /!< CoreDebug DEMCR: MON_REQ Mask /
AnnaBridge	167:e84263d55307	1880
AnnaBridge	167:e84263d55307	1881	#define CoreDebug_DEMCR_MON_STEP_Pos 18U /!< CoreDebug DEMCR: MON_STEP Position /
AnnaBridge	167:e84263d55307	1882	#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /!< CoreDebug DEMCR: MON_STEP Mask /
AnnaBridge	167:e84263d55307	1883
AnnaBridge	167:e84263d55307	1884	#define CoreDebug_DEMCR_MON_PEND_Pos 17U /!< CoreDebug DEMCR: MON_PEND Position /
AnnaBridge	167:e84263d55307	1885	#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /!< CoreDebug DEMCR: MON_PEND Mask /
AnnaBridge	167:e84263d55307	1886
AnnaBridge	167:e84263d55307	1887	#define CoreDebug_DEMCR_MON_EN_Pos 16U /!< CoreDebug DEMCR: MON_EN Position /
AnnaBridge	167:e84263d55307	1888	#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /!< CoreDebug DEMCR: MON_EN Mask /
AnnaBridge	167:e84263d55307	1889
AnnaBridge	167:e84263d55307	1890	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /!< CoreDebug DEMCR: VC_HARDERR Position /
AnnaBridge	167:e84263d55307	1891	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
AnnaBridge	167:e84263d55307	1892
AnnaBridge	167:e84263d55307	1893	#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /!< CoreDebug DEMCR: VC_INTERR Position /
AnnaBridge	167:e84263d55307	1894	#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /!< CoreDebug DEMCR: VC_INTERR Mask /
AnnaBridge	167:e84263d55307	1895
AnnaBridge	167:e84263d55307	1896	#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /!< CoreDebug DEMCR: VC_BUSERR Position /
AnnaBridge	167:e84263d55307	1897	#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /!< CoreDebug DEMCR: VC_BUSERR Mask /
AnnaBridge	167:e84263d55307	1898
AnnaBridge	167:e84263d55307	1899	#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /!< CoreDebug DEMCR: VC_STATERR Position /
AnnaBridge	167:e84263d55307	1900	#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /!< CoreDebug DEMCR: VC_STATERR Mask /
AnnaBridge	167:e84263d55307	1901
AnnaBridge	167:e84263d55307	1902	#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /!< CoreDebug DEMCR: VC_CHKERR Position /
AnnaBridge	167:e84263d55307	1903	#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /!< CoreDebug DEMCR: VC_CHKERR Mask /
AnnaBridge	167:e84263d55307	1904
AnnaBridge	167:e84263d55307	1905	#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /!< CoreDebug DEMCR: VC_NOCPERR Position /
AnnaBridge	167:e84263d55307	1906	#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /!< CoreDebug DEMCR: VC_NOCPERR Mask /
AnnaBridge	167:e84263d55307	1907
AnnaBridge	167:e84263d55307	1908	#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /!< CoreDebug DEMCR: VC_MMERR Position /
AnnaBridge	167:e84263d55307	1909	#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /!< CoreDebug DEMCR: VC_MMERR Mask /
AnnaBridge	167:e84263d55307	1910
AnnaBridge	167:e84263d55307	1911	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /!< CoreDebug DEMCR: VC_CORERESET Position /
AnnaBridge	167:e84263d55307	1912	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/) /!< CoreDebug DEMCR: VC_CORERESET Mask /
AnnaBridge	167:e84263d55307	1913
AnnaBridge	167:e84263d55307	1914	/* Debug Authentication Control Register Definitions */
AnnaBridge	167:e84263d55307	1915	#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position /
AnnaBridge	167:e84263d55307	1916	#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask /
AnnaBridge	167:e84263d55307	1917
AnnaBridge	167:e84263d55307	1918	#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /!< CoreDebug DAUTHCTRL: SPNIDENSEL Position /
AnnaBridge	167:e84263d55307	1919	#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask /
AnnaBridge	167:e84263d55307	1920
AnnaBridge	167:e84263d55307	1921	#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /!< CoreDebug DAUTHCTRL: INTSPIDEN Position /
AnnaBridge	167:e84263d55307	1922	#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /!< CoreDebug DAUTHCTRL: INTSPIDEN Mask /
AnnaBridge	167:e84263d55307	1923
AnnaBridge	167:e84263d55307	1924	#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /!< CoreDebug DAUTHCTRL: SPIDENSEL Position /
AnnaBridge	167:e84263d55307	1925	#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos/) /!< CoreDebug DAUTHCTRL: SPIDENSEL Mask /
AnnaBridge	167:e84263d55307	1926
AnnaBridge	167:e84263d55307	1927	/* Debug Security Control and Status Register Definitions */
AnnaBridge	167:e84263d55307	1928	#define CoreDebug_DSCSR_CDS_Pos 16U /!< CoreDebug DSCSR: CDS Position /
AnnaBridge	167:e84263d55307	1929	#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /!< CoreDebug DSCSR: CDS Mask /
AnnaBridge	167:e84263d55307	1930
AnnaBridge	167:e84263d55307	1931	#define CoreDebug_DSCSR_SBRSEL_Pos 1U /!< CoreDebug DSCSR: SBRSEL Position /
AnnaBridge	167:e84263d55307	1932	#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /!< CoreDebug DSCSR: SBRSEL Mask /
AnnaBridge	167:e84263d55307	1933
AnnaBridge	167:e84263d55307	1934	#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /!< CoreDebug DSCSR: SBRSELEN Position /
AnnaBridge	167:e84263d55307	1935	#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /<< CoreDebug_DSCSR_SBRSELEN_Pos/) /!< CoreDebug DSCSR: SBRSELEN Mask /
AnnaBridge	167:e84263d55307	1936
AnnaBridge	167:e84263d55307	1937	/@} end of group CMSIS_CoreDebug /
AnnaBridge	167:e84263d55307	1938
AnnaBridge	167:e84263d55307	1939
AnnaBridge	167:e84263d55307	1940	/**
AnnaBridge	167:e84263d55307	1941	\ingroup CMSIS_core_register
AnnaBridge	167:e84263d55307	1942	\defgroup CMSIS_core_bitfield Core register bit field macros
AnnaBridge	167:e84263d55307	1943	\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
AnnaBridge	167:e84263d55307	1944	@{
AnnaBridge	167:e84263d55307	1945	*/
AnnaBridge	167:e84263d55307	1946
AnnaBridge	167:e84263d55307	1947	/**
AnnaBridge	167:e84263d55307	1948	\brief Mask and shift a bit field value for use in a register bit range.
AnnaBridge	167:e84263d55307	1949	\param[in] field Name of the register bit field.
AnnaBridge	167:e84263d55307	1950	\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
AnnaBridge	167:e84263d55307	1951	\return Masked and shifted value.
AnnaBridge	167:e84263d55307	1952	*/
AnnaBridge	167:e84263d55307	1953	#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
AnnaBridge	167:e84263d55307	1954
AnnaBridge	167:e84263d55307	1955	/**
AnnaBridge	167:e84263d55307	1956	\brief Mask and shift a register value to extract a bit filed value.
AnnaBridge	167:e84263d55307	1957	\param[in] field Name of the register bit field.
AnnaBridge	167:e84263d55307	1958	\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
AnnaBridge	167:e84263d55307	1959	\return Masked and shifted bit field value.
AnnaBridge	167:e84263d55307	1960	*/
AnnaBridge	167:e84263d55307	1961	#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
AnnaBridge	167:e84263d55307	1962
AnnaBridge	167:e84263d55307	1963	/@} end of group CMSIS_core_bitfield /
AnnaBridge	167:e84263d55307	1964
AnnaBridge	167:e84263d55307	1965
AnnaBridge	167:e84263d55307	1966	/**
AnnaBridge	167:e84263d55307	1967	\ingroup CMSIS_core_register
AnnaBridge	167:e84263d55307	1968	\defgroup CMSIS_core_base Core Definitions
AnnaBridge	167:e84263d55307	1969	\brief Definitions for base addresses, unions, and structures.
AnnaBridge	167:e84263d55307	1970	@{
AnnaBridge	167:e84263d55307	1971	*/
AnnaBridge	167:e84263d55307	1972
AnnaBridge	167:e84263d55307	1973	/* Memory mapping of Core Hardware */
AnnaBridge	167:e84263d55307	1974	#define SCS_BASE (0xE000E000UL) /!< System Control Space Base Address /
AnnaBridge	167:e84263d55307	1975	#define ITM_BASE (0xE0000000UL) /!< ITM Base Address /
AnnaBridge	167:e84263d55307	1976	#define DWT_BASE (0xE0001000UL) /!< DWT Base Address /
AnnaBridge	167:e84263d55307	1977	#define TPI_BASE (0xE0040000UL) /!< TPI Base Address /
AnnaBridge	167:e84263d55307	1978	#define CoreDebug_BASE (0xE000EDF0UL) /!< Core Debug Base Address /
AnnaBridge	167:e84263d55307	1979	#define SysTick_BASE (SCS_BASE + 0x0010UL) /!< SysTick Base Address /
AnnaBridge	167:e84263d55307	1980	#define NVIC_BASE (SCS_BASE + 0x0100UL) /!< NVIC Base Address /
AnnaBridge	167:e84263d55307	1981	#define SCB_BASE (SCS_BASE + 0x0D00UL) /!< System Control Block Base Address /
AnnaBridge	167:e84263d55307	1982
AnnaBridge	167:e84263d55307	1983	#define SCnSCB ((SCnSCB_Type ) SCS_BASE ) /!< System control Register not in SCB */
AnnaBridge	167:e84263d55307	1984	#define SCB ((SCB_Type ) SCB_BASE ) /!< SCB configuration struct */
AnnaBridge	167:e84263d55307	1985	#define SysTick ((SysTick_Type ) SysTick_BASE ) /!< SysTick configuration struct */
AnnaBridge	167:e84263d55307	1986	#define NVIC ((NVIC_Type ) NVIC_BASE ) /!< NVIC configuration struct */
AnnaBridge	167:e84263d55307	1987	#define ITM ((ITM_Type ) ITM_BASE ) /!< ITM configuration struct */
AnnaBridge	167:e84263d55307	1988	#define DWT ((DWT_Type ) DWT_BASE ) /!< DWT configuration struct */
AnnaBridge	167:e84263d55307	1989	#define TPI ((TPI_Type ) TPI_BASE ) /!< TPI configuration struct */
AnnaBridge	167:e84263d55307	1990	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE ) /!< Core Debug configuration struct */
AnnaBridge	167:e84263d55307	1991
AnnaBridge	167:e84263d55307	1992	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge	167:e84263d55307	1993	#define MPU_BASE (SCS_BASE + 0x0D90UL) /!< Memory Protection Unit /
AnnaBridge	167:e84263d55307	1994	#define MPU ((MPU_Type ) MPU_BASE ) /!< Memory Protection Unit */
AnnaBridge	167:e84263d55307	1995	#endif
AnnaBridge	167:e84263d55307	1996
AnnaBridge	167:e84263d55307	1997	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge	167:e84263d55307	1998	#define SAU_BASE (SCS_BASE + 0x0DD0UL) /!< Security Attribution Unit /
AnnaBridge	167:e84263d55307	1999	#define SAU ((SAU_Type ) SAU_BASE ) /!< Security Attribution Unit */
AnnaBridge	167:e84263d55307	2000	#endif
AnnaBridge	167:e84263d55307	2001
AnnaBridge	167:e84263d55307	2002	#define FPU_BASE (SCS_BASE + 0x0F30UL) /!< Floating Point Unit /
AnnaBridge	167:e84263d55307	2003	#define FPU ((FPU_Type ) FPU_BASE ) /!< Floating Point Unit */
AnnaBridge	167:e84263d55307	2004
AnnaBridge	167:e84263d55307	2005	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge	167:e84263d55307	2006	#define SCS_BASE_NS (0xE002E000UL) /!< System Control Space Base Address (non-secure address space) /
AnnaBridge	167:e84263d55307	2007	#define CoreDebug_BASE_NS (0xE002EDF0UL) /!< Core Debug Base Address (non-secure address space) /
AnnaBridge	167:e84263d55307	2008	#define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /!< SysTick Base Address (non-secure address space) /
AnnaBridge	167:e84263d55307	2009	#define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /!< NVIC Base Address (non-secure address space) /
AnnaBridge	167:e84263d55307	2010	#define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /!< System Control Block Base Address (non-secure address space) /
AnnaBridge	167:e84263d55307	2011
AnnaBridge	167:e84263d55307	2012	#define SCnSCB_NS ((SCnSCB_Type ) SCS_BASE_NS ) /!< System control Register not in SCB(non-secure address space) */
AnnaBridge	167:e84263d55307	2013	#define SCB_NS ((SCB_Type ) SCB_BASE_NS ) /!< SCB configuration struct (non-secure address space) */
AnnaBridge	167:e84263d55307	2014	#define SysTick_NS ((SysTick_Type ) SysTick_BASE_NS ) /!< SysTick configuration struct (non-secure address space) */
AnnaBridge	167:e84263d55307	2015	#define NVIC_NS ((NVIC_Type ) NVIC_BASE_NS ) /!< NVIC configuration struct (non-secure address space) */
AnnaBridge	167:e84263d55307	2016	#define CoreDebug_NS ((CoreDebug_Type ) CoreDebug_BASE_NS) /!< Core Debug configuration struct (non-secure address space) */
AnnaBridge	167:e84263d55307	2017
AnnaBridge	167:e84263d55307	2018	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge	167:e84263d55307	2019	#define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /!< Memory Protection Unit (non-secure address space) /
AnnaBridge	167:e84263d55307	2020	#define MPU_NS ((MPU_Type ) MPU_BASE_NS ) /!< Memory Protection Unit (non-secure address space) */
AnnaBridge	167:e84263d55307	2021	#endif
AnnaBridge	167:e84263d55307	2022
AnnaBridge	167:e84263d55307	2023	#define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /!< Floating Point Unit (non-secure address space) /
AnnaBridge	167:e84263d55307	2024	#define FPU_NS ((FPU_Type ) FPU_BASE_NS ) /!< Floating Point Unit (non-secure address space) */
AnnaBridge	167:e84263d55307	2025
AnnaBridge	167:e84263d55307	2026	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
AnnaBridge	167:e84263d55307	2027	/@} /
AnnaBridge	167:e84263d55307	2028
AnnaBridge	167:e84263d55307	2029
AnnaBridge	167:e84263d55307	2030
AnnaBridge	167:e84263d55307	2031	/*******************************************************************************
AnnaBridge	167:e84263d55307	2032	* Hardware Abstraction Layer
AnnaBridge	167:e84263d55307	2033	Core Function Interface contains:
AnnaBridge	167:e84263d55307	2034	- Core NVIC Functions
AnnaBridge	167:e84263d55307	2035	- Core SysTick Functions
AnnaBridge	167:e84263d55307	2036	- Core Debug Functions
AnnaBridge	167:e84263d55307	2037	- Core Register Access Functions
AnnaBridge	167:e84263d55307	2038	******************************************************************************/
AnnaBridge	167:e84263d55307	2039	/**
AnnaBridge	167:e84263d55307	2040	\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
AnnaBridge	167:e84263d55307	2041	*/
AnnaBridge	167:e84263d55307	2042
AnnaBridge	167:e84263d55307	2043
AnnaBridge	167:e84263d55307	2044
AnnaBridge	167:e84263d55307	2045	/* ########################## NVIC functions #################################### */
AnnaBridge	167:e84263d55307	2046	/**
AnnaBridge	167:e84263d55307	2047	\ingroup CMSIS_Core_FunctionInterface
AnnaBridge	167:e84263d55307	2048	\defgroup CMSIS_Core_NVICFunctions NVIC Functions
AnnaBridge	167:e84263d55307	2049	\brief Functions that manage interrupts and exceptions via the NVIC.
AnnaBridge	167:e84263d55307	2050	@{
AnnaBridge	167:e84263d55307	2051	*/
AnnaBridge	167:e84263d55307	2052
AnnaBridge	167:e84263d55307	2053	#ifdef CMSIS_NVIC_VIRTUAL
AnnaBridge	167:e84263d55307	2054	#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge	167:e84263d55307	2055	#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
AnnaBridge	167:e84263d55307	2056	#endif
AnnaBridge	167:e84263d55307	2057	#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge	167:e84263d55307	2058	#else
AnnaBridge	167:e84263d55307	2059	#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
AnnaBridge	167:e84263d55307	2060	#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
AnnaBridge	167:e84263d55307	2061	#define NVIC_EnableIRQ __NVIC_EnableIRQ
AnnaBridge	167:e84263d55307	2062	#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
AnnaBridge	167:e84263d55307	2063	#define NVIC_DisableIRQ __NVIC_DisableIRQ
AnnaBridge	167:e84263d55307	2064	#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
AnnaBridge	167:e84263d55307	2065	#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
AnnaBridge	167:e84263d55307	2066	#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
AnnaBridge	167:e84263d55307	2067	#define NVIC_GetActive __NVIC_GetActive
AnnaBridge	167:e84263d55307	2068	#define NVIC_SetPriority __NVIC_SetPriority
AnnaBridge	167:e84263d55307	2069	#define NVIC_GetPriority __NVIC_GetPriority
AnnaBridge	167:e84263d55307	2070	#define NVIC_SystemReset __NVIC_SystemReset
AnnaBridge	167:e84263d55307	2071	#endif /* CMSIS_NVIC_VIRTUAL */
AnnaBridge	167:e84263d55307	2072
AnnaBridge	167:e84263d55307	2073	#ifdef CMSIS_VECTAB_VIRTUAL
AnnaBridge	167:e84263d55307	2074	#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge	167:e84263d55307	2075	#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
AnnaBridge	167:e84263d55307	2076	#endif
AnnaBridge	167:e84263d55307	2077	#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge	167:e84263d55307	2078	#else
AnnaBridge	167:e84263d55307	2079	#define NVIC_SetVector __NVIC_SetVector
AnnaBridge	167:e84263d55307	2080	#define NVIC_GetVector __NVIC_GetVector
AnnaBridge	167:e84263d55307	2081	#endif /* (CMSIS_VECTAB_VIRTUAL) */
AnnaBridge	167:e84263d55307	2082
AnnaBridge	167:e84263d55307	2083	#define NVIC_USER_IRQ_OFFSET 16
AnnaBridge	167:e84263d55307	2084
AnnaBridge	167:e84263d55307	2085
AnnaBridge	167:e84263d55307	2086
AnnaBridge	167:e84263d55307	2087	/**
AnnaBridge	167:e84263d55307	2088	\brief Set Priority Grouping
AnnaBridge	167:e84263d55307	2089	\details Sets the priority grouping field using the required unlock sequence.
AnnaBridge	167:e84263d55307	2090	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
AnnaBridge	167:e84263d55307	2091	Only values from 0..7 are used.
AnnaBridge	167:e84263d55307	2092	In case of a conflict between priority grouping and available
AnnaBridge	167:e84263d55307	2093	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
AnnaBridge	167:e84263d55307	2094	\param [in] PriorityGroup Priority grouping field.
AnnaBridge	167:e84263d55307	2095	*/
AnnaBridge	167:e84263d55307	2096	__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
AnnaBridge	167:e84263d55307	2097	{
AnnaBridge	167:e84263d55307	2098	uint32_t reg_value;
AnnaBridge	167:e84263d55307	2099	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
AnnaBridge	167:e84263d55307	2100
AnnaBridge	167:e84263d55307	2101	reg_value = SCB->AIRCR; /* read old register configuration */
AnnaBridge	167:e84263d55307	2102	reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
AnnaBridge	167:e84263d55307	2103	reg_value = (reg_value \|
AnnaBridge	167:e84263d55307	2104	((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
AnnaBridge	167:e84263d55307	2105	(PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
AnnaBridge	167:e84263d55307	2106	SCB->AIRCR = reg_value;
AnnaBridge	167:e84263d55307	2107	}
AnnaBridge	167:e84263d55307	2108
AnnaBridge	167:e84263d55307	2109
AnnaBridge	167:e84263d55307	2110	/**
AnnaBridge	167:e84263d55307	2111	\brief Get Priority Grouping
AnnaBridge	167:e84263d55307	2112	\details Reads the priority grouping field from the NVIC Interrupt Controller.
AnnaBridge	167:e84263d55307	2113	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
AnnaBridge	167:e84263d55307	2114	*/
AnnaBridge	167:e84263d55307	2115	__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
AnnaBridge	167:e84263d55307	2116	{
AnnaBridge	167:e84263d55307	2117	return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
AnnaBridge	167:e84263d55307	2118	}
AnnaBridge	167:e84263d55307	2119
AnnaBridge	167:e84263d55307	2120
AnnaBridge	167:e84263d55307	2121	/**
AnnaBridge	167:e84263d55307	2122	\brief Enable Interrupt
AnnaBridge	167:e84263d55307	2123	\details Enables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge	167:e84263d55307	2124	\param [in] IRQn Device specific interrupt number.
AnnaBridge	167:e84263d55307	2125	\note IRQn must not be negative.
AnnaBridge	167:e84263d55307	2126	*/
AnnaBridge	167:e84263d55307	2127	__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
AnnaBridge	167:e84263d55307	2128	{
AnnaBridge	167:e84263d55307	2129	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:e84263d55307	2130	{
AnnaBridge	167:e84263d55307	2131	NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge	167:e84263d55307	2132	}
AnnaBridge	167:e84263d55307	2133	}
AnnaBridge	167:e84263d55307	2134
AnnaBridge	167:e84263d55307	2135
AnnaBridge	167:e84263d55307	2136	/**
AnnaBridge	167:e84263d55307	2137	\brief Get Interrupt Enable status
AnnaBridge	167:e84263d55307	2138	\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
AnnaBridge	167:e84263d55307	2139	\param [in] IRQn Device specific interrupt number.
AnnaBridge	167:e84263d55307	2140	\return 0 Interrupt is not enabled.
AnnaBridge	167:e84263d55307	2141	\return 1 Interrupt is enabled.
AnnaBridge	167:e84263d55307	2142	\note IRQn must not be negative.
AnnaBridge	167:e84263d55307	2143	*/
AnnaBridge	167:e84263d55307	2144	__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
AnnaBridge	167:e84263d55307	2145	{
AnnaBridge	167:e84263d55307	2146	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:e84263d55307	2147	{
AnnaBridge	167:e84263d55307	2148	return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	167:e84263d55307	2149	}
AnnaBridge	167:e84263d55307	2150	else
AnnaBridge	167:e84263d55307	2151	{
AnnaBridge	167:e84263d55307	2152	return(0U);
AnnaBridge	167:e84263d55307	2153	}
AnnaBridge	167:e84263d55307	2154	}
AnnaBridge	167:e84263d55307	2155
AnnaBridge	167:e84263d55307	2156
AnnaBridge	167:e84263d55307	2157	/**
AnnaBridge	167:e84263d55307	2158	\brief Disable Interrupt
AnnaBridge	167:e84263d55307	2159	\details Disables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge	167:e84263d55307	2160	\param [in] IRQn Device specific interrupt number.
AnnaBridge	167:e84263d55307	2161	\note IRQn must not be negative.
AnnaBridge	167:e84263d55307	2162	*/
AnnaBridge	167:e84263d55307	2163	__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
AnnaBridge	167:e84263d55307	2164	{
AnnaBridge	167:e84263d55307	2165	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:e84263d55307	2166	{
AnnaBridge	167:e84263d55307	2167	NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge	167:e84263d55307	2168	__DSB();
AnnaBridge	167:e84263d55307	2169	__ISB();
AnnaBridge	167:e84263d55307	2170	}
AnnaBridge	167:e84263d55307	2171	}
AnnaBridge	167:e84263d55307	2172
AnnaBridge	167:e84263d55307	2173
AnnaBridge	167:e84263d55307	2174	/**
AnnaBridge	167:e84263d55307	2175	\brief Get Pending Interrupt
AnnaBridge	167:e84263d55307	2176	\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
AnnaBridge	167:e84263d55307	2177	\param [in] IRQn Device specific interrupt number.
AnnaBridge	167:e84263d55307	2178	\return 0 Interrupt status is not pending.
AnnaBridge	167:e84263d55307	2179	\return 1 Interrupt status is pending.
AnnaBridge	167:e84263d55307	2180	\note IRQn must not be negative.
AnnaBridge	167:e84263d55307	2181	*/
AnnaBridge	167:e84263d55307	2182	__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
AnnaBridge	167:e84263d55307	2183	{
AnnaBridge	167:e84263d55307	2184	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:e84263d55307	2185	{
AnnaBridge	167:e84263d55307	2186	return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	167:e84263d55307	2187	}
AnnaBridge	167:e84263d55307	2188	else
AnnaBridge	167:e84263d55307	2189	{
AnnaBridge	167:e84263d55307	2190	return(0U);
AnnaBridge	167:e84263d55307	2191	}
AnnaBridge	167:e84263d55307	2192	}
AnnaBridge	167:e84263d55307	2193
AnnaBridge	167:e84263d55307	2194
AnnaBridge	167:e84263d55307	2195	/**
AnnaBridge	167:e84263d55307	2196	\brief Set Pending Interrupt
AnnaBridge	167:e84263d55307	2197	\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge	167:e84263d55307	2198	\param [in] IRQn Device specific interrupt number.
AnnaBridge	167:e84263d55307	2199	\note IRQn must not be negative.
AnnaBridge	167:e84263d55307	2200	*/
AnnaBridge	167:e84263d55307	2201	__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
AnnaBridge	167:e84263d55307	2202	{
AnnaBridge	167:e84263d55307	2203	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:e84263d55307	2204	{
AnnaBridge	167:e84263d55307	2205	NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge	167:e84263d55307	2206	}
AnnaBridge	167:e84263d55307	2207	}
AnnaBridge	167:e84263d55307	2208
AnnaBridge	167:e84263d55307	2209
AnnaBridge	167:e84263d55307	2210	/**
AnnaBridge	167:e84263d55307	2211	\brief Clear Pending Interrupt
AnnaBridge	167:e84263d55307	2212	\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge	167:e84263d55307	2213	\param [in] IRQn Device specific interrupt number.
AnnaBridge	167:e84263d55307	2214	\note IRQn must not be negative.
AnnaBridge	167:e84263d55307	2215	*/
AnnaBridge	167:e84263d55307	2216	__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
AnnaBridge	167:e84263d55307	2217	{
AnnaBridge	167:e84263d55307	2218	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:e84263d55307	2219	{
AnnaBridge	167:e84263d55307	2220	NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge	167:e84263d55307	2221	}
AnnaBridge	167:e84263d55307	2222	}
AnnaBridge	167:e84263d55307	2223
AnnaBridge	167:e84263d55307	2224
AnnaBridge	167:e84263d55307	2225	/**
AnnaBridge	167:e84263d55307	2226	\brief Get Active Interrupt
AnnaBridge	167:e84263d55307	2227	\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
AnnaBridge	167:e84263d55307	2228	\param [in] IRQn Device specific interrupt number.
AnnaBridge	167:e84263d55307	2229	\return 0 Interrupt status is not active.
AnnaBridge	167:e84263d55307	2230	\return 1 Interrupt status is active.
AnnaBridge	167:e84263d55307	2231	\note IRQn must not be negative.
AnnaBridge	167:e84263d55307	2232	*/
AnnaBridge	167:e84263d55307	2233	__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
AnnaBridge	167:e84263d55307	2234	{
AnnaBridge	167:e84263d55307	2235	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:e84263d55307	2236	{
AnnaBridge	167:e84263d55307	2237	return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	167:e84263d55307	2238	}
AnnaBridge	167:e84263d55307	2239	else
AnnaBridge	167:e84263d55307	2240	{
AnnaBridge	167:e84263d55307	2241	return(0U);
AnnaBridge	167:e84263d55307	2242	}
AnnaBridge	167:e84263d55307	2243	}
AnnaBridge	167:e84263d55307	2244
AnnaBridge	167:e84263d55307	2245
AnnaBridge	167:e84263d55307	2246	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge	167:e84263d55307	2247	/**
AnnaBridge	167:e84263d55307	2248	\brief Get Interrupt Target State
AnnaBridge	167:e84263d55307	2249	\details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
AnnaBridge	167:e84263d55307	2250	\param [in] IRQn Device specific interrupt number.
AnnaBridge	167:e84263d55307	2251	\return 0 if interrupt is assigned to Secure
AnnaBridge	167:e84263d55307	2252	\return 1 if interrupt is assigned to Non Secure
AnnaBridge	167:e84263d55307	2253	\note IRQn must not be negative.
AnnaBridge	167:e84263d55307	2254	*/
AnnaBridge	167:e84263d55307	2255	__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
AnnaBridge	167:e84263d55307	2256	{
AnnaBridge	167:e84263d55307	2257	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:e84263d55307	2258	{
AnnaBridge	167:e84263d55307	2259	return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	167:e84263d55307	2260	}
AnnaBridge	167:e84263d55307	2261	else
AnnaBridge	167:e84263d55307	2262	{
AnnaBridge	167:e84263d55307	2263	return(0U);
AnnaBridge	167:e84263d55307	2264	}
AnnaBridge	167:e84263d55307	2265	}
AnnaBridge	167:e84263d55307	2266
AnnaBridge	167:e84263d55307	2267
AnnaBridge	167:e84263d55307	2268	/**
AnnaBridge	167:e84263d55307	2269	\brief Set Interrupt Target State
AnnaBridge	167:e84263d55307	2270	\details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
AnnaBridge	167:e84263d55307	2271	\param [in] IRQn Device specific interrupt number.
AnnaBridge	167:e84263d55307	2272	\return 0 if interrupt is assigned to Secure
AnnaBridge	167:e84263d55307	2273	1 if interrupt is assigned to Non Secure
AnnaBridge	167:e84263d55307	2274	\note IRQn must not be negative.
AnnaBridge	167:e84263d55307	2275	*/
AnnaBridge	167:e84263d55307	2276	__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
AnnaBridge	167:e84263d55307	2277	{
AnnaBridge	167:e84263d55307	2278	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:e84263d55307	2279	{
AnnaBridge	167:e84263d55307	2280	NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] \|= ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
AnnaBridge	167:e84263d55307	2281	return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	167:e84263d55307	2282	}
AnnaBridge	167:e84263d55307	2283	else
AnnaBridge	167:e84263d55307	2284	{
AnnaBridge	167:e84263d55307	2285	return(0U);
AnnaBridge	167:e84263d55307	2286	}
AnnaBridge	167:e84263d55307	2287	}
AnnaBridge	167:e84263d55307	2288
AnnaBridge	167:e84263d55307	2289
AnnaBridge	167:e84263d55307	2290	/**
AnnaBridge	167:e84263d55307	2291	\brief Clear Interrupt Target State
AnnaBridge	167:e84263d55307	2292	\details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
AnnaBridge	167:e84263d55307	2293	\param [in] IRQn Device specific interrupt number.
AnnaBridge	167:e84263d55307	2294	\return 0 if interrupt is assigned to Secure
AnnaBridge	167:e84263d55307	2295	1 if interrupt is assigned to Non Secure
AnnaBridge	167:e84263d55307	2296	\note IRQn must not be negative.
AnnaBridge	167:e84263d55307	2297	*/
AnnaBridge	167:e84263d55307	2298	__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
AnnaBridge	167:e84263d55307	2299	{
AnnaBridge	167:e84263d55307	2300	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:e84263d55307	2301	{
AnnaBridge	167:e84263d55307	2302	NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
AnnaBridge	167:e84263d55307	2303	return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	167:e84263d55307	2304	}
AnnaBridge	167:e84263d55307	2305	else
AnnaBridge	167:e84263d55307	2306	{
AnnaBridge	167:e84263d55307	2307	return(0U);
AnnaBridge	167:e84263d55307	2308	}
AnnaBridge	167:e84263d55307	2309	}
AnnaBridge	167:e84263d55307	2310	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
AnnaBridge	167:e84263d55307	2311
AnnaBridge	167:e84263d55307	2312
AnnaBridge	167:e84263d55307	2313	/**
AnnaBridge	167:e84263d55307	2314	\brief Set Interrupt Priority
AnnaBridge	167:e84263d55307	2315	\details Sets the priority of a device specific interrupt or a processor exception.
AnnaBridge	167:e84263d55307	2316	The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge	167:e84263d55307	2317	or negative to specify a processor exception.
AnnaBridge	167:e84263d55307	2318	\param [in] IRQn Interrupt number.
AnnaBridge	167:e84263d55307	2319	\param [in] priority Priority to set.
AnnaBridge	167:e84263d55307	2320	\note The priority cannot be set for every processor exception.
AnnaBridge	167:e84263d55307	2321	*/
AnnaBridge	167:e84263d55307	2322	__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
AnnaBridge	167:e84263d55307	2323	{
AnnaBridge	167:e84263d55307	2324	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:e84263d55307	2325	{
AnnaBridge	167:e84263d55307	2326	NVIC->IPR[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
AnnaBridge	167:e84263d55307	2327	}
AnnaBridge	167:e84263d55307	2328	else
AnnaBridge	167:e84263d55307	2329	{
AnnaBridge	167:e84263d55307	2330	SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
AnnaBridge	167:e84263d55307	2331	}
AnnaBridge	167:e84263d55307	2332	}
AnnaBridge	167:e84263d55307	2333
AnnaBridge	167:e84263d55307	2334
AnnaBridge	167:e84263d55307	2335	/**
AnnaBridge	167:e84263d55307	2336	\brief Get Interrupt Priority
AnnaBridge	167:e84263d55307	2337	\details Reads the priority of a device specific interrupt or a processor exception.
AnnaBridge	167:e84263d55307	2338	The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge	167:e84263d55307	2339	or negative to specify a processor exception.
AnnaBridge	167:e84263d55307	2340	\param [in] IRQn Interrupt number.
AnnaBridge	167:e84263d55307	2341	\return Interrupt Priority.
AnnaBridge	167:e84263d55307	2342	Value is aligned automatically to the implemented priority bits of the microcontroller.
AnnaBridge	167:e84263d55307	2343	*/
AnnaBridge	167:e84263d55307	2344	__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
AnnaBridge	167:e84263d55307	2345	{
AnnaBridge	167:e84263d55307	2346
AnnaBridge	167:e84263d55307	2347	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:e84263d55307	2348	{
AnnaBridge	167:e84263d55307	2349	return(((uint32_t)NVIC->IPR[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge	167:e84263d55307	2350	}
AnnaBridge	167:e84263d55307	2351	else
AnnaBridge	167:e84263d55307	2352	{
AnnaBridge	167:e84263d55307	2353	return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge	167:e84263d55307	2354	}
AnnaBridge	167:e84263d55307	2355	}
AnnaBridge	167:e84263d55307	2356
AnnaBridge	167:e84263d55307	2357
AnnaBridge	167:e84263d55307	2358	/**
AnnaBridge	167:e84263d55307	2359	\brief Encode Priority
AnnaBridge	167:e84263d55307	2360	\details Encodes the priority for an interrupt with the given priority group,
AnnaBridge	167:e84263d55307	2361	preemptive priority value, and subpriority value.
AnnaBridge	167:e84263d55307	2362	In case of a conflict between priority grouping and available
AnnaBridge	167:e84263d55307	2363	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
AnnaBridge	167:e84263d55307	2364	\param [in] PriorityGroup Used priority group.
AnnaBridge	167:e84263d55307	2365	\param [in] PreemptPriority Preemptive priority value (starting from 0).
AnnaBridge	167:e84263d55307	2366	\param [in] SubPriority Subpriority value (starting from 0).
AnnaBridge	167:e84263d55307	2367	\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
AnnaBridge	167:e84263d55307	2368	*/
AnnaBridge	167:e84263d55307	2369	__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
AnnaBridge	167:e84263d55307	2370	{
AnnaBridge	167:e84263d55307	2371	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
AnnaBridge	167:e84263d55307	2372	uint32_t PreemptPriorityBits;
AnnaBridge	167:e84263d55307	2373	uint32_t SubPriorityBits;
AnnaBridge	167:e84263d55307	2374
AnnaBridge	167:e84263d55307	2375	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
AnnaBridge	167:e84263d55307	2376	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
AnnaBridge	167:e84263d55307	2377
AnnaBridge	167:e84263d55307	2378	return (
AnnaBridge	167:e84263d55307	2379	((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) \|
AnnaBridge	167:e84263d55307	2380	((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
AnnaBridge	167:e84263d55307	2381	);
AnnaBridge	167:e84263d55307	2382	}
AnnaBridge	167:e84263d55307	2383
AnnaBridge	167:e84263d55307	2384
AnnaBridge	167:e84263d55307	2385	/**
AnnaBridge	167:e84263d55307	2386	\brief Decode Priority
AnnaBridge	167:e84263d55307	2387	\details Decodes an interrupt priority value with a given priority group to
AnnaBridge	167:e84263d55307	2388	preemptive priority value and subpriority value.
AnnaBridge	167:e84263d55307	2389	In case of a conflict between priority grouping and available
AnnaBridge	167:e84263d55307	2390	priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
AnnaBridge	167:e84263d55307	2391	\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
AnnaBridge	167:e84263d55307	2392	\param [in] PriorityGroup Used priority group.
AnnaBridge	167:e84263d55307	2393	\param [out] pPreemptPriority Preemptive priority value (starting from 0).
AnnaBridge	167:e84263d55307	2394	\param [out] pSubPriority Subpriority value (starting from 0).
AnnaBridge	167:e84263d55307	2395	*/
AnnaBridge	167:e84263d55307	2396	__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
AnnaBridge	167:e84263d55307	2397	{
AnnaBridge	167:e84263d55307	2398	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
AnnaBridge	167:e84263d55307	2399	uint32_t PreemptPriorityBits;
AnnaBridge	167:e84263d55307	2400	uint32_t SubPriorityBits;
AnnaBridge	167:e84263d55307	2401
AnnaBridge	167:e84263d55307	2402	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
AnnaBridge	167:e84263d55307	2403	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
AnnaBridge	167:e84263d55307	2404
AnnaBridge	167:e84263d55307	2405	*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
AnnaBridge	167:e84263d55307	2406	*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
AnnaBridge	167:e84263d55307	2407	}
AnnaBridge	167:e84263d55307	2408
AnnaBridge	167:e84263d55307	2409
AnnaBridge	167:e84263d55307	2410	/**
AnnaBridge	167:e84263d55307	2411	\brief Set Interrupt Vector
AnnaBridge	167:e84263d55307	2412	\details Sets an interrupt vector in SRAM based interrupt vector table.
AnnaBridge	167:e84263d55307	2413	The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge	167:e84263d55307	2414	or negative to specify a processor exception.
AnnaBridge	167:e84263d55307	2415	VTOR must been relocated to SRAM before.
AnnaBridge	167:e84263d55307	2416	\param [in] IRQn Interrupt number
AnnaBridge	167:e84263d55307	2417	\param [in] vector Address of interrupt handler function
AnnaBridge	167:e84263d55307	2418	*/
AnnaBridge	167:e84263d55307	2419	__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
AnnaBridge	167:e84263d55307	2420	{
AnnaBridge	167:e84263d55307	2421	uint32_t vectors = (uint32_t )SCB->VTOR;
AnnaBridge	167:e84263d55307	2422	vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
AnnaBridge	167:e84263d55307	2423	}
AnnaBridge	167:e84263d55307	2424
AnnaBridge	167:e84263d55307	2425
AnnaBridge	167:e84263d55307	2426	/**
AnnaBridge	167:e84263d55307	2427	\brief Get Interrupt Vector
AnnaBridge	167:e84263d55307	2428	\details Reads an interrupt vector from interrupt vector table.
AnnaBridge	167:e84263d55307	2429	The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge	167:e84263d55307	2430	or negative to specify a processor exception.
AnnaBridge	167:e84263d55307	2431	\param [in] IRQn Interrupt number.
AnnaBridge	167:e84263d55307	2432	\return Address of interrupt handler function
AnnaBridge	167:e84263d55307	2433	*/
AnnaBridge	167:e84263d55307	2434	__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
AnnaBridge	167:e84263d55307	2435	{
AnnaBridge	167:e84263d55307	2436	uint32_t vectors = (uint32_t )SCB->VTOR;
AnnaBridge	167:e84263d55307	2437	return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
AnnaBridge	167:e84263d55307	2438	}
AnnaBridge	167:e84263d55307	2439
AnnaBridge	167:e84263d55307	2440
AnnaBridge	167:e84263d55307	2441	/**
AnnaBridge	167:e84263d55307	2442	\brief System Reset
AnnaBridge	167:e84263d55307	2443	\details Initiates a system reset request to reset the MCU.
AnnaBridge	167:e84263d55307	2444	*/
AnnaBridge	167:e84263d55307	2445	__STATIC_INLINE void __NVIC_SystemReset(void)
AnnaBridge	167:e84263d55307	2446	{
AnnaBridge	167:e84263d55307	2447	__DSB(); /* Ensure all outstanding memory accesses included
AnnaBridge	167:e84263d55307	2448	buffered write are completed before reset */
AnnaBridge	167:e84263d55307	2449	SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
AnnaBridge	167:e84263d55307	2450	(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) \|
AnnaBridge	167:e84263d55307	2451	SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
AnnaBridge	167:e84263d55307	2452	__DSB(); /* Ensure completion of memory access */
AnnaBridge	167:e84263d55307	2453
AnnaBridge	167:e84263d55307	2454	for(;;) /* wait until reset */
AnnaBridge	167:e84263d55307	2455	{
AnnaBridge	167:e84263d55307	2456	__NOP();
AnnaBridge	167:e84263d55307	2457	}
AnnaBridge	167:e84263d55307	2458	}
AnnaBridge	167:e84263d55307	2459
AnnaBridge	167:e84263d55307	2460	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge	167:e84263d55307	2461	/**
AnnaBridge	167:e84263d55307	2462	\brief Set Priority Grouping (non-secure)
AnnaBridge	167:e84263d55307	2463	\details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
AnnaBridge	167:e84263d55307	2464	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
AnnaBridge	167:e84263d55307	2465	Only values from 0..7 are used.
AnnaBridge	167:e84263d55307	2466	In case of a conflict between priority grouping and available
AnnaBridge	167:e84263d55307	2467	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
AnnaBridge	167:e84263d55307	2468	\param [in] PriorityGroup Priority grouping field.
AnnaBridge	167:e84263d55307	2469	*/
AnnaBridge	167:e84263d55307	2470	__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
AnnaBridge	167:e84263d55307	2471	{
AnnaBridge	167:e84263d55307	2472	uint32_t reg_value;
AnnaBridge	167:e84263d55307	2473	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
AnnaBridge	167:e84263d55307	2474
AnnaBridge	167:e84263d55307	2475	reg_value = SCB_NS->AIRCR; /* read old register configuration */
AnnaBridge	167:e84263d55307	2476	reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
AnnaBridge	167:e84263d55307	2477	reg_value = (reg_value \|
AnnaBridge	167:e84263d55307	2478	((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
AnnaBridge	167:e84263d55307	2479	(PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
AnnaBridge	167:e84263d55307	2480	SCB_NS->AIRCR = reg_value;
AnnaBridge	167:e84263d55307	2481	}
AnnaBridge	167:e84263d55307	2482
AnnaBridge	167:e84263d55307	2483
AnnaBridge	167:e84263d55307	2484	/**
AnnaBridge	167:e84263d55307	2485	\brief Get Priority Grouping (non-secure)
AnnaBridge	167:e84263d55307	2486	\details Reads the priority grouping field from the non-secure NVIC when in secure state.
AnnaBridge	167:e84263d55307	2487	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
AnnaBridge	167:e84263d55307	2488	*/
AnnaBridge	167:e84263d55307	2489	__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
AnnaBridge	167:e84263d55307	2490	{
AnnaBridge	167:e84263d55307	2491	return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
AnnaBridge	167:e84263d55307	2492	}
AnnaBridge	167:e84263d55307	2493
AnnaBridge	167:e84263d55307	2494
AnnaBridge	167:e84263d55307	2495	/**
AnnaBridge	167:e84263d55307	2496	\brief Enable Interrupt (non-secure)
AnnaBridge	167:e84263d55307	2497	\details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
AnnaBridge	167:e84263d55307	2498	\param [in] IRQn Device specific interrupt number.
AnnaBridge	167:e84263d55307	2499	\note IRQn must not be negative.
AnnaBridge	167:e84263d55307	2500	*/
AnnaBridge	167:e84263d55307	2501	__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
AnnaBridge	167:e84263d55307	2502	{
AnnaBridge	167:e84263d55307	2503	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:e84263d55307	2504	{
AnnaBridge	167:e84263d55307	2505	NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge	167:e84263d55307	2506	}
AnnaBridge	167:e84263d55307	2507	}
AnnaBridge	167:e84263d55307	2508
AnnaBridge	167:e84263d55307	2509
AnnaBridge	167:e84263d55307	2510	/**
AnnaBridge	167:e84263d55307	2511	\brief Get Interrupt Enable status (non-secure)
AnnaBridge	167:e84263d55307	2512	\details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
AnnaBridge	167:e84263d55307	2513	\param [in] IRQn Device specific interrupt number.
AnnaBridge	167:e84263d55307	2514	\return 0 Interrupt is not enabled.
AnnaBridge	167:e84263d55307	2515	\return 1 Interrupt is enabled.
AnnaBridge	167:e84263d55307	2516	\note IRQn must not be negative.
AnnaBridge	167:e84263d55307	2517	*/
AnnaBridge	167:e84263d55307	2518	__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
AnnaBridge	167:e84263d55307	2519	{
AnnaBridge	167:e84263d55307	2520	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:e84263d55307	2521	{
AnnaBridge	167:e84263d55307	2522	return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	167:e84263d55307	2523	}
AnnaBridge	167:e84263d55307	2524	else
AnnaBridge	167:e84263d55307	2525	{
AnnaBridge	167:e84263d55307	2526	return(0U);
AnnaBridge	167:e84263d55307	2527	}
AnnaBridge	167:e84263d55307	2528	}
AnnaBridge	167:e84263d55307	2529
AnnaBridge	167:e84263d55307	2530
AnnaBridge	167:e84263d55307	2531	/**
AnnaBridge	167:e84263d55307	2532	\brief Disable Interrupt (non-secure)
AnnaBridge	167:e84263d55307	2533	\details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
AnnaBridge	167:e84263d55307	2534	\param [in] IRQn Device specific interrupt number.
AnnaBridge	167:e84263d55307	2535	\note IRQn must not be negative.
AnnaBridge	167:e84263d55307	2536	*/
AnnaBridge	167:e84263d55307	2537	__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
AnnaBridge	167:e84263d55307	2538	{
AnnaBridge	167:e84263d55307	2539	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:e84263d55307	2540	{
AnnaBridge	167:e84263d55307	2541	NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge	167:e84263d55307	2542	}
AnnaBridge	167:e84263d55307	2543	}
AnnaBridge	167:e84263d55307	2544
AnnaBridge	167:e84263d55307	2545
AnnaBridge	167:e84263d55307	2546	/**
AnnaBridge	167:e84263d55307	2547	\brief Get Pending Interrupt (non-secure)
AnnaBridge	167:e84263d55307	2548	\details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
AnnaBridge	167:e84263d55307	2549	\param [in] IRQn Device specific interrupt number.
AnnaBridge	167:e84263d55307	2550	\return 0 Interrupt status is not pending.
AnnaBridge	167:e84263d55307	2551	\return 1 Interrupt status is pending.
AnnaBridge	167:e84263d55307	2552	\note IRQn must not be negative.
AnnaBridge	167:e84263d55307	2553	*/
AnnaBridge	167:e84263d55307	2554	__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
AnnaBridge	167:e84263d55307	2555	{
AnnaBridge	167:e84263d55307	2556	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:e84263d55307	2557	{
AnnaBridge	167:e84263d55307	2558	return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	167:e84263d55307	2559	}
AnnaBridge	167:e84263d55307	2560	}
AnnaBridge	167:e84263d55307	2561
AnnaBridge	167:e84263d55307	2562
AnnaBridge	167:e84263d55307	2563	/**
AnnaBridge	167:e84263d55307	2564	\brief Set Pending Interrupt (non-secure)
AnnaBridge	167:e84263d55307	2565	\details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
AnnaBridge	167:e84263d55307	2566	\param [in] IRQn Device specific interrupt number.
AnnaBridge	167:e84263d55307	2567	\note IRQn must not be negative.
AnnaBridge	167:e84263d55307	2568	*/
AnnaBridge	167:e84263d55307	2569	__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
AnnaBridge	167:e84263d55307	2570	{
AnnaBridge	167:e84263d55307	2571	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:e84263d55307	2572	{
AnnaBridge	167:e84263d55307	2573	NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge	167:e84263d55307	2574	}
AnnaBridge	167:e84263d55307	2575	}
AnnaBridge	167:e84263d55307	2576
AnnaBridge	167:e84263d55307	2577
AnnaBridge	167:e84263d55307	2578	/**
AnnaBridge	167:e84263d55307	2579	\brief Clear Pending Interrupt (non-secure)
AnnaBridge	167:e84263d55307	2580	\details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
AnnaBridge	167:e84263d55307	2581	\param [in] IRQn Device specific interrupt number.
AnnaBridge	167:e84263d55307	2582	\note IRQn must not be negative.
AnnaBridge	167:e84263d55307	2583	*/
AnnaBridge	167:e84263d55307	2584	__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
AnnaBridge	167:e84263d55307	2585	{
AnnaBridge	167:e84263d55307	2586	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:e84263d55307	2587	{
AnnaBridge	167:e84263d55307	2588	NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge	167:e84263d55307	2589	}
AnnaBridge	167:e84263d55307	2590	}
AnnaBridge	167:e84263d55307	2591
AnnaBridge	167:e84263d55307	2592
AnnaBridge	167:e84263d55307	2593	/**
AnnaBridge	167:e84263d55307	2594	\brief Get Active Interrupt (non-secure)
AnnaBridge	167:e84263d55307	2595	\details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
AnnaBridge	167:e84263d55307	2596	\param [in] IRQn Device specific interrupt number.
AnnaBridge	167:e84263d55307	2597	\return 0 Interrupt status is not active.
AnnaBridge	167:e84263d55307	2598	\return 1 Interrupt status is active.
AnnaBridge	167:e84263d55307	2599	\note IRQn must not be negative.
AnnaBridge	167:e84263d55307	2600	*/
AnnaBridge	167:e84263d55307	2601	__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
AnnaBridge	167:e84263d55307	2602	{
AnnaBridge	167:e84263d55307	2603	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:e84263d55307	2604	{
AnnaBridge	167:e84263d55307	2605	return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	167:e84263d55307	2606	}
AnnaBridge	167:e84263d55307	2607	else
AnnaBridge	167:e84263d55307	2608	{
AnnaBridge	167:e84263d55307	2609	return(0U);
AnnaBridge	167:e84263d55307	2610	}
AnnaBridge	167:e84263d55307	2611	}
AnnaBridge	167:e84263d55307	2612
AnnaBridge	167:e84263d55307	2613
AnnaBridge	167:e84263d55307	2614	/**
AnnaBridge	167:e84263d55307	2615	\brief Set Interrupt Priority (non-secure)
AnnaBridge	167:e84263d55307	2616	\details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
AnnaBridge	167:e84263d55307	2617	The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge	167:e84263d55307	2618	or negative to specify a processor exception.
AnnaBridge	167:e84263d55307	2619	\param [in] IRQn Interrupt number.
AnnaBridge	167:e84263d55307	2620	\param [in] priority Priority to set.
AnnaBridge	167:e84263d55307	2621	\note The priority cannot be set for every non-secure processor exception.
AnnaBridge	167:e84263d55307	2622	*/
AnnaBridge	167:e84263d55307	2623	__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
AnnaBridge	167:e84263d55307	2624	{
AnnaBridge	167:e84263d55307	2625	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:e84263d55307	2626	{
AnnaBridge	167:e84263d55307	2627	NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
AnnaBridge	167:e84263d55307	2628	}
AnnaBridge	167:e84263d55307	2629	else
AnnaBridge	167:e84263d55307	2630	{
AnnaBridge	167:e84263d55307	2631	SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
AnnaBridge	167:e84263d55307	2632	}
AnnaBridge	167:e84263d55307	2633	}
AnnaBridge	167:e84263d55307	2634
AnnaBridge	167:e84263d55307	2635
AnnaBridge	167:e84263d55307	2636	/**
AnnaBridge	167:e84263d55307	2637	\brief Get Interrupt Priority (non-secure)
AnnaBridge	167:e84263d55307	2638	\details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
AnnaBridge	167:e84263d55307	2639	The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge	167:e84263d55307	2640	or negative to specify a processor exception.
AnnaBridge	167:e84263d55307	2641	\param [in] IRQn Interrupt number.
AnnaBridge	167:e84263d55307	2642	\return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
AnnaBridge	167:e84263d55307	2643	*/
AnnaBridge	167:e84263d55307	2644	__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
AnnaBridge	167:e84263d55307	2645	{
AnnaBridge	167:e84263d55307	2646
AnnaBridge	167:e84263d55307	2647	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:e84263d55307	2648	{
AnnaBridge	167:e84263d55307	2649	return(((uint32_t)NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge	167:e84263d55307	2650	}
AnnaBridge	167:e84263d55307	2651	else
AnnaBridge	167:e84263d55307	2652	{
AnnaBridge	167:e84263d55307	2653	return(((uint32_t)SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge	167:e84263d55307	2654	}
AnnaBridge	167:e84263d55307	2655	}
AnnaBridge	167:e84263d55307	2656	#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
AnnaBridge	167:e84263d55307	2657
AnnaBridge	167:e84263d55307	2658	/@} end of CMSIS_Core_NVICFunctions /
AnnaBridge	167:e84263d55307	2659
AnnaBridge	167:e84263d55307	2660
AnnaBridge	167:e84263d55307	2661	/* ########################## FPU functions #################################### */
AnnaBridge	167:e84263d55307	2662	/**
AnnaBridge	167:e84263d55307	2663	\ingroup CMSIS_Core_FunctionInterface
AnnaBridge	167:e84263d55307	2664	\defgroup CMSIS_Core_FpuFunctions FPU Functions
AnnaBridge	167:e84263d55307	2665	\brief Function that provides FPU type.
AnnaBridge	167:e84263d55307	2666	@{
AnnaBridge	167:e84263d55307	2667	*/
AnnaBridge	167:e84263d55307	2668
AnnaBridge	167:e84263d55307	2669	/**
AnnaBridge	167:e84263d55307	2670	\brief get FPU type
AnnaBridge	167:e84263d55307	2671	\details returns the FPU type
AnnaBridge	167:e84263d55307	2672	\returns
AnnaBridge	167:e84263d55307	2673	- \b 0: No FPU
AnnaBridge	167:e84263d55307	2674	- \b 1: Single precision FPU
AnnaBridge	167:e84263d55307	2675	- \b 2: Double + Single precision FPU
AnnaBridge	167:e84263d55307	2676	*/
AnnaBridge	167:e84263d55307	2677	__STATIC_INLINE uint32_t SCB_GetFPUType(void)
AnnaBridge	167:e84263d55307	2678	{
AnnaBridge	167:e84263d55307	2679	uint32_t mvfr0;
AnnaBridge	167:e84263d55307	2680
AnnaBridge	167:e84263d55307	2681	mvfr0 = FPU->MVFR0;
AnnaBridge	167:e84263d55307	2682	if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk \| FPU_MVFR0_Double_precision_Msk)) == 0x220U)
AnnaBridge	167:e84263d55307	2683	{
AnnaBridge	167:e84263d55307	2684	return 2U; /* Double + Single precision FPU */
AnnaBridge	167:e84263d55307	2685	}
AnnaBridge	167:e84263d55307	2686	else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk \| FPU_MVFR0_Double_precision_Msk)) == 0x020U)
AnnaBridge	167:e84263d55307	2687	{
AnnaBridge	167:e84263d55307	2688	return 1U; /* Single precision FPU */
AnnaBridge	167:e84263d55307	2689	}
AnnaBridge	167:e84263d55307	2690	else
AnnaBridge	167:e84263d55307	2691	{
AnnaBridge	167:e84263d55307	2692	return 0U; /* No FPU */
AnnaBridge	167:e84263d55307	2693	}
AnnaBridge	167:e84263d55307	2694	}
AnnaBridge	167:e84263d55307	2695
AnnaBridge	167:e84263d55307	2696
AnnaBridge	167:e84263d55307	2697	/@} end of CMSIS_Core_FpuFunctions /
AnnaBridge	167:e84263d55307	2698
AnnaBridge	167:e84263d55307	2699
AnnaBridge	167:e84263d55307	2700
AnnaBridge	167:e84263d55307	2701	/* ########################## SAU functions #################################### */
AnnaBridge	167:e84263d55307	2702	/**
AnnaBridge	167:e84263d55307	2703	\ingroup CMSIS_Core_FunctionInterface
AnnaBridge	167:e84263d55307	2704	\defgroup CMSIS_Core_SAUFunctions SAU Functions
AnnaBridge	167:e84263d55307	2705	\brief Functions that configure the SAU.
AnnaBridge	167:e84263d55307	2706	@{
AnnaBridge	167:e84263d55307	2707	*/
AnnaBridge	167:e84263d55307	2708
AnnaBridge	167:e84263d55307	2709	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge	167:e84263d55307	2710
AnnaBridge	167:e84263d55307	2711	/**
AnnaBridge	167:e84263d55307	2712	\brief Enable SAU
AnnaBridge	167:e84263d55307	2713	\details Enables the Security Attribution Unit (SAU).
AnnaBridge	167:e84263d55307	2714	*/
AnnaBridge	167:e84263d55307	2715	__STATIC_INLINE void TZ_SAU_Enable(void)
AnnaBridge	167:e84263d55307	2716	{
AnnaBridge	167:e84263d55307	2717	SAU->CTRL \|= (SAU_CTRL_ENABLE_Msk);
AnnaBridge	167:e84263d55307	2718	}
AnnaBridge	167:e84263d55307	2719
AnnaBridge	167:e84263d55307	2720
AnnaBridge	167:e84263d55307	2721
AnnaBridge	167:e84263d55307	2722	/**
AnnaBridge	167:e84263d55307	2723	\brief Disable SAU
AnnaBridge	167:e84263d55307	2724	\details Disables the Security Attribution Unit (SAU).
AnnaBridge	167:e84263d55307	2725	*/
AnnaBridge	167:e84263d55307	2726	__STATIC_INLINE void TZ_SAU_Disable(void)
AnnaBridge	167:e84263d55307	2727	{
AnnaBridge	167:e84263d55307	2728	SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
AnnaBridge	167:e84263d55307	2729	}
AnnaBridge	167:e84263d55307	2730
AnnaBridge	167:e84263d55307	2731	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
AnnaBridge	167:e84263d55307	2732
AnnaBridge	167:e84263d55307	2733	/@} end of CMSIS_Core_SAUFunctions /
AnnaBridge	167:e84263d55307	2734
AnnaBridge	167:e84263d55307	2735
AnnaBridge	167:e84263d55307	2736
AnnaBridge	167:e84263d55307	2737
AnnaBridge	167:e84263d55307	2738	/* ################################## SysTick function ############################################ */
AnnaBridge	167:e84263d55307	2739	/**
AnnaBridge	167:e84263d55307	2740	\ingroup CMSIS_Core_FunctionInterface
AnnaBridge	167:e84263d55307	2741	\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
AnnaBridge	167:e84263d55307	2742	\brief Functions that configure the System.
AnnaBridge	167:e84263d55307	2743	@{
AnnaBridge	167:e84263d55307	2744	*/
AnnaBridge	167:e84263d55307	2745
AnnaBridge	167:e84263d55307	2746	#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
AnnaBridge	167:e84263d55307	2747
AnnaBridge	167:e84263d55307	2748	/**
AnnaBridge	167:e84263d55307	2749	\brief System Tick Configuration
AnnaBridge	167:e84263d55307	2750	\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
AnnaBridge	167:e84263d55307	2751	Counter is in free running mode to generate periodic interrupts.
AnnaBridge	167:e84263d55307	2752	\param [in] ticks Number of ticks between two interrupts.
AnnaBridge	167:e84263d55307	2753	\return 0 Function succeeded.
AnnaBridge	167:e84263d55307	2754	\return 1 Function failed.
AnnaBridge	167:e84263d55307	2755	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
AnnaBridge	167:e84263d55307	2756	function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
AnnaBridge	167:e84263d55307	2757	must contain a vendor-specific implementation of this function.
AnnaBridge	167:e84263d55307	2758	*/
AnnaBridge	167:e84263d55307	2759	__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
AnnaBridge	167:e84263d55307	2760	{
AnnaBridge	167:e84263d55307	2761	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
AnnaBridge	167:e84263d55307	2762	{
AnnaBridge	167:e84263d55307	2763	return (1UL); /* Reload value impossible */
AnnaBridge	167:e84263d55307	2764	}
AnnaBridge	167:e84263d55307	2765
AnnaBridge	167:e84263d55307	2766	SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
AnnaBridge	167:e84263d55307	2767	NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
AnnaBridge	167:e84263d55307	2768	SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
AnnaBridge	167:e84263d55307	2769	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
AnnaBridge	167:e84263d55307	2770	SysTick_CTRL_TICKINT_Msk \|
AnnaBridge	167:e84263d55307	2771	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
AnnaBridge	167:e84263d55307	2772	return (0UL); /* Function successful */
AnnaBridge	167:e84263d55307	2773	}
AnnaBridge	167:e84263d55307	2774
AnnaBridge	167:e84263d55307	2775	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge	167:e84263d55307	2776	/**
AnnaBridge	167:e84263d55307	2777	\brief System Tick Configuration (non-secure)
AnnaBridge	167:e84263d55307	2778	\details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
AnnaBridge	167:e84263d55307	2779	Counter is in free running mode to generate periodic interrupts.
AnnaBridge	167:e84263d55307	2780	\param [in] ticks Number of ticks between two interrupts.
AnnaBridge	167:e84263d55307	2781	\return 0 Function succeeded.
AnnaBridge	167:e84263d55307	2782	\return 1 Function failed.
AnnaBridge	167:e84263d55307	2783	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
AnnaBridge	167:e84263d55307	2784	function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
AnnaBridge	167:e84263d55307	2785	must contain a vendor-specific implementation of this function.
AnnaBridge	167:e84263d55307	2786
AnnaBridge	167:e84263d55307	2787	*/
AnnaBridge	167:e84263d55307	2788	__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
AnnaBridge	167:e84263d55307	2789	{
AnnaBridge	167:e84263d55307	2790	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
AnnaBridge	167:e84263d55307	2791	{
AnnaBridge	167:e84263d55307	2792	return (1UL); /* Reload value impossible */
AnnaBridge	167:e84263d55307	2793	}
AnnaBridge	167:e84263d55307	2794
AnnaBridge	167:e84263d55307	2795	SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
AnnaBridge	167:e84263d55307	2796	TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
AnnaBridge	167:e84263d55307	2797	SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
AnnaBridge	167:e84263d55307	2798	SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
AnnaBridge	167:e84263d55307	2799	SysTick_CTRL_TICKINT_Msk \|
AnnaBridge	167:e84263d55307	2800	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
AnnaBridge	167:e84263d55307	2801	return (0UL); /* Function successful */
AnnaBridge	167:e84263d55307	2802	}
AnnaBridge	167:e84263d55307	2803	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
AnnaBridge	167:e84263d55307	2804
AnnaBridge	167:e84263d55307	2805	#endif
AnnaBridge	167:e84263d55307	2806
AnnaBridge	167:e84263d55307	2807	/@} end of CMSIS_Core_SysTickFunctions /
AnnaBridge	167:e84263d55307	2808
AnnaBridge	167:e84263d55307	2809
AnnaBridge	167:e84263d55307	2810
AnnaBridge	167:e84263d55307	2811	/* ##################################### Debug In/Output function ########################################### */
AnnaBridge	167:e84263d55307	2812	/**
AnnaBridge	167:e84263d55307	2813	\ingroup CMSIS_Core_FunctionInterface
AnnaBridge	167:e84263d55307	2814	\defgroup CMSIS_core_DebugFunctions ITM Functions
AnnaBridge	167:e84263d55307	2815	\brief Functions that access the ITM debug interface.
AnnaBridge	167:e84263d55307	2816	@{
AnnaBridge	167:e84263d55307	2817	*/
AnnaBridge	167:e84263d55307	2818
AnnaBridge	167:e84263d55307	2819	extern volatile int32_t ITM_RxBuffer; /!< External variable to receive characters. /
AnnaBridge	167:e84263d55307	2820	#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /!< Value identifying \ref ITM_RxBuffer is ready for next character. /
AnnaBridge	167:e84263d55307	2821
AnnaBridge	167:e84263d55307	2822
AnnaBridge	167:e84263d55307	2823	/**
AnnaBridge	167:e84263d55307	2824	\brief ITM Send Character
AnnaBridge	167:e84263d55307	2825	\details Transmits a character via the ITM channel 0, and
AnnaBridge	167:e84263d55307	2826	\li Just returns when no debugger is connected that has booked the output.
AnnaBridge	167:e84263d55307	2827	\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
AnnaBridge	167:e84263d55307	2828	\param [in] ch Character to transmit.
AnnaBridge	167:e84263d55307	2829	\returns Character to transmit.
AnnaBridge	167:e84263d55307	2830	*/
AnnaBridge	167:e84263d55307	2831	__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
AnnaBridge	167:e84263d55307	2832	{
AnnaBridge	167:e84263d55307	2833	if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
AnnaBridge	167:e84263d55307	2834	((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
AnnaBridge	167:e84263d55307	2835	{
AnnaBridge	167:e84263d55307	2836	while (ITM->PORT[0U].u32 == 0UL)
AnnaBridge	167:e84263d55307	2837	{
AnnaBridge	167:e84263d55307	2838	__NOP();
AnnaBridge	167:e84263d55307	2839	}
AnnaBridge	167:e84263d55307	2840	ITM->PORT[0U].u8 = (uint8_t)ch;
AnnaBridge	167:e84263d55307	2841	}
AnnaBridge	167:e84263d55307	2842	return (ch);
AnnaBridge	167:e84263d55307	2843	}
AnnaBridge	167:e84263d55307	2844
AnnaBridge	167:e84263d55307	2845
AnnaBridge	167:e84263d55307	2846	/**
AnnaBridge	167:e84263d55307	2847	\brief ITM Receive Character
AnnaBridge	167:e84263d55307	2848	\details Inputs a character via the external variable \ref ITM_RxBuffer.
AnnaBridge	167:e84263d55307	2849	\return Received character.
AnnaBridge	167:e84263d55307	2850	\return -1 No character pending.
AnnaBridge	167:e84263d55307	2851	*/
AnnaBridge	167:e84263d55307	2852	__STATIC_INLINE int32_t ITM_ReceiveChar (void)
AnnaBridge	167:e84263d55307	2853	{
AnnaBridge	167:e84263d55307	2854	int32_t ch = -1; /* no character available */
AnnaBridge	167:e84263d55307	2855
AnnaBridge	167:e84263d55307	2856	if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
AnnaBridge	167:e84263d55307	2857	{
AnnaBridge	167:e84263d55307	2858	ch = ITM_RxBuffer;
AnnaBridge	167:e84263d55307	2859	ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
AnnaBridge	167:e84263d55307	2860	}
AnnaBridge	167:e84263d55307	2861
AnnaBridge	167:e84263d55307	2862	return (ch);
AnnaBridge	167:e84263d55307	2863	}
AnnaBridge	167:e84263d55307	2864
AnnaBridge	167:e84263d55307	2865
AnnaBridge	167:e84263d55307	2866	/**
AnnaBridge	167:e84263d55307	2867	\brief ITM Check Character
AnnaBridge	167:e84263d55307	2868	\details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
AnnaBridge	167:e84263d55307	2869	\return 0 No character available.
AnnaBridge	167:e84263d55307	2870	\return 1 Character available.
AnnaBridge	167:e84263d55307	2871	*/
AnnaBridge	167:e84263d55307	2872	__STATIC_INLINE int32_t ITM_CheckChar (void)
AnnaBridge	167:e84263d55307	2873	{
AnnaBridge	167:e84263d55307	2874
AnnaBridge	167:e84263d55307	2875	if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
AnnaBridge	167:e84263d55307	2876	{
AnnaBridge	167:e84263d55307	2877	return (0); /* no character available */
AnnaBridge	167:e84263d55307	2878	}
AnnaBridge	167:e84263d55307	2879	else
AnnaBridge	167:e84263d55307	2880	{
AnnaBridge	167:e84263d55307	2881	return (1); /* character available */
AnnaBridge	167:e84263d55307	2882	}
AnnaBridge	167:e84263d55307	2883	}
AnnaBridge	167:e84263d55307	2884
AnnaBridge	167:e84263d55307	2885	/@} end of CMSIS_core_DebugFunctions /
AnnaBridge	167:e84263d55307	2886
AnnaBridge	167:e84263d55307	2887
AnnaBridge	167:e84263d55307	2888
AnnaBridge	167:e84263d55307	2889
AnnaBridge	167:e84263d55307	2890	#ifdef __cplusplus
AnnaBridge	167:e84263d55307	2891	}
AnnaBridge	167:e84263d55307	2892	#endif
AnnaBridge	167:e84263d55307	2893
AnnaBridge	167:e84263d55307	2894	#endif /* __CORE_CM33_H_DEPENDANT */
AnnaBridge	167:e84263d55307	2895
AnnaBridge	167:e84263d55307	2896	#endif /* __CMSIS_GENERIC */

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Type:	Library
Created:	19 Dec 2017
Imports:	0
Forks:	0
Commits:	175
Dependents:	0
Dependencies:	0
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cmsis/core_cm33.h@174:ed647f63e28d, 2017-12-19 (annotated)

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