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cmsis/core_cm3.h@174:ed647f63e28d, 2017-12-19 (annotated)

Committer:
Dollyparton
Date:
Tue Dec 19 12:50:13 2017 +0000
Revision:
174:ed647f63e28d
Parent:
167:e84263d55307 
Added RAW socket.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 149:156823d33999 1 /**************************************************************************//**
<> 149:156823d33999 2 * @file core_cm3.h
<> 149:156823d33999 3 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
AnnaBridge 167:e84263d55307 4 * @version V5.0.2
AnnaBridge 167:e84263d55307 5 * @date 13. February 2017
AnnaBridge 167:e84263d55307 6 ******************************************************************************/
AnnaBridge 167:e84263d55307 7 /*
AnnaBridge 167:e84263d55307 8 * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
AnnaBridge 167:e84263d55307 9 *
AnnaBridge 167:e84263d55307 10 * SPDX-License-Identifier: Apache-2.0
<> 149:156823d33999 11 *
AnnaBridge 167:e84263d55307 12 * Licensed under the Apache License, Version 2.0 (the License); you may
AnnaBridge 167:e84263d55307 13 * not use this file except in compliance with the License.
AnnaBridge 167:e84263d55307 14 * You may obtain a copy of the License at
AnnaBridge 167:e84263d55307 15 *
AnnaBridge 167:e84263d55307 16 * www.apache.org/licenses/LICENSE-2.0
<> 149:156823d33999 17 *
AnnaBridge 167:e84263d55307 18 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 167:e84263d55307 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
AnnaBridge 167:e84263d55307 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 167:e84263d55307 21 * See the License for the specific language governing permissions and
AnnaBridge 167:e84263d55307 22 * limitations under the License.
AnnaBridge 167:e84263d55307 23 */
<> 149:156823d33999 24
AnnaBridge 167:e84263d55307 25 #if defined ( __ICCARM__ )
AnnaBridge 167:e84263d55307 26 #pragma system_include /* treat file as system include file for MISRA check */
AnnaBridge 167:e84263d55307 27 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge 167:e84263d55307 28 #pragma clang system_header /* treat file as system include file */
<> 149:156823d33999 29 #endif
<> 149:156823d33999 30
<> 149:156823d33999 31 #ifndef __CORE_CM3_H_GENERIC
<> 149:156823d33999 32 #define __CORE_CM3_H_GENERIC
<> 149:156823d33999 33
AnnaBridge 167:e84263d55307 34 #include <stdint.h>
AnnaBridge 167:e84263d55307 35
<> 149:156823d33999 36 #ifdef __cplusplus
<> 149:156823d33999 37 extern "C" {
<> 149:156823d33999 38 #endif
<> 149:156823d33999 39
AnnaBridge 167:e84263d55307 40 /**
AnnaBridge 167:e84263d55307 41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
<> 149:156823d33999 42 CMSIS violates the following MISRA-C:2004 rules:
<> 149:156823d33999 43
<> 149:156823d33999 44 \li Required Rule 8.5, object/function definition in header file.<br>
<> 149:156823d33999 45 Function definitions in header files are used to allow 'inlining'.
<> 149:156823d33999 46
<> 149:156823d33999 47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
<> 149:156823d33999 48 Unions are used for effective representation of core registers.
<> 149:156823d33999 49
<> 149:156823d33999 50 \li Advisory Rule 19.7, Function-like macro defined.<br>
<> 149:156823d33999 51 Function-like macros are used to allow more efficient code.
<> 149:156823d33999 52 */
<> 149:156823d33999 53
<> 149:156823d33999 54
<> 149:156823d33999 55 /*******************************************************************************
<> 149:156823d33999 56 * CMSIS definitions
<> 149:156823d33999 57 ******************************************************************************/
AnnaBridge 167:e84263d55307 58 /**
AnnaBridge 167:e84263d55307 59 \ingroup Cortex_M3
<> 149:156823d33999 60 @{
<> 149:156823d33999 61 */
<> 149:156823d33999 62
<> 149:156823d33999 63 /* CMSIS CM3 definitions */
AnnaBridge 167:e84263d55307 64 #define __CM3_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */
AnnaBridge 167:e84263d55307 65 #define __CM3_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */
AnnaBridge 167:e84263d55307 66 #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \
AnnaBridge 167:e84263d55307 67 __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
<> 149:156823d33999 68
AnnaBridge 167:e84263d55307 69 #define __CORTEX_M (3U) /*!< Cortex-M Core */
<> 149:156823d33999 70
<> 149:156823d33999 71 /** __FPU_USED indicates whether an FPU is used or not.
<> 149:156823d33999 72 This core does not support an FPU at all
<> 149:156823d33999 73 */
AnnaBridge 167:e84263d55307 74 #define __FPU_USED 0U
<> 149:156823d33999 75
<> 149:156823d33999 76 #if defined ( __CC_ARM )
<> 149:156823d33999 77 #if defined __TARGET_FPU_VFP
AnnaBridge 167:e84263d55307 78 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 167:e84263d55307 79 #endif
AnnaBridge 167:e84263d55307 80
AnnaBridge 167:e84263d55307 81 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge 167:e84263d55307 82 #if defined __ARM_PCS_VFP
AnnaBridge 167:e84263d55307 83 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 149:156823d33999 84 #endif
<> 149:156823d33999 85
<> 149:156823d33999 86 #elif defined ( __GNUC__ )
<> 149:156823d33999 87 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
AnnaBridge 167:e84263d55307 88 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 149:156823d33999 89 #endif
<> 149:156823d33999 90
<> 149:156823d33999 91 #elif defined ( __ICCARM__ )
<> 149:156823d33999 92 #if defined __ARMVFP__
AnnaBridge 167:e84263d55307 93 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 149:156823d33999 94 #endif
<> 149:156823d33999 95
AnnaBridge 167:e84263d55307 96 #elif defined ( __TI_ARM__ )
AnnaBridge 167:e84263d55307 97 #if defined __TI_VFP_SUPPORT__
AnnaBridge 167:e84263d55307 98 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 149:156823d33999 99 #endif
<> 149:156823d33999 100
<> 149:156823d33999 101 #elif defined ( __TASKING__ )
<> 149:156823d33999 102 #if defined __FPU_VFP__
<> 149:156823d33999 103 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 149:156823d33999 104 #endif
<> 149:156823d33999 105
AnnaBridge 167:e84263d55307 106 #elif defined ( __CSMC__ )
AnnaBridge 167:e84263d55307 107 #if ( __CSMC__ & 0x400U)
<> 149:156823d33999 108 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 149:156823d33999 109 #endif
AnnaBridge 167:e84263d55307 110
<> 149:156823d33999 111 #endif
<> 149:156823d33999 112
AnnaBridge 167:e84263d55307 113 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
AnnaBridge 167:e84263d55307 114
<> 149:156823d33999 115
<> 149:156823d33999 116 #ifdef __cplusplus
<> 149:156823d33999 117 }
<> 149:156823d33999 118 #endif
<> 149:156823d33999 119
<> 149:156823d33999 120 #endif /* __CORE_CM3_H_GENERIC */
<> 149:156823d33999 121
<> 149:156823d33999 122 #ifndef __CMSIS_GENERIC
<> 149:156823d33999 123
<> 149:156823d33999 124 #ifndef __CORE_CM3_H_DEPENDANT
<> 149:156823d33999 125 #define __CORE_CM3_H_DEPENDANT
<> 149:156823d33999 126
<> 149:156823d33999 127 #ifdef __cplusplus
<> 149:156823d33999 128 extern "C" {
<> 149:156823d33999 129 #endif
<> 149:156823d33999 130
<> 149:156823d33999 131 /* check device defines and use defaults */
<> 149:156823d33999 132 #if defined __CHECK_DEVICE_DEFINES
<> 149:156823d33999 133 #ifndef __CM3_REV
AnnaBridge 167:e84263d55307 134 #define __CM3_REV 0x0200U
<> 149:156823d33999 135 #warning "__CM3_REV not defined in device header file; using default!"
<> 149:156823d33999 136 #endif
<> 149:156823d33999 137
<> 149:156823d33999 138 #ifndef __MPU_PRESENT
AnnaBridge 167:e84263d55307 139 #define __MPU_PRESENT 0U
<> 149:156823d33999 140 #warning "__MPU_PRESENT not defined in device header file; using default!"
<> 149:156823d33999 141 #endif
<> 149:156823d33999 142
<> 149:156823d33999 143 #ifndef __NVIC_PRIO_BITS
AnnaBridge 167:e84263d55307 144 #define __NVIC_PRIO_BITS 3U
<> 149:156823d33999 145 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
<> 149:156823d33999 146 #endif
<> 149:156823d33999 147
<> 149:156823d33999 148 #ifndef __Vendor_SysTickConfig
AnnaBridge 167:e84263d55307 149 #define __Vendor_SysTickConfig 0U
<> 149:156823d33999 150 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
<> 149:156823d33999 151 #endif
<> 149:156823d33999 152 #endif
<> 149:156823d33999 153
<> 149:156823d33999 154 /* IO definitions (access restrictions to peripheral registers) */
<> 149:156823d33999 155 /**
<> 149:156823d33999 156 \defgroup CMSIS_glob_defs CMSIS Global Defines
<> 149:156823d33999 157
<> 149:156823d33999 158 <strong>IO Type Qualifiers</strong> are used
<> 149:156823d33999 159 \li to specify the access to peripheral variables.
<> 149:156823d33999 160 \li for automatic generation of peripheral register debug information.
<> 149:156823d33999 161 */
<> 149:156823d33999 162 #ifdef __cplusplus
AnnaBridge 167:e84263d55307 163 #define __I volatile /*!< Defines 'read only' permissions */
<> 149:156823d33999 164 #else
AnnaBridge 167:e84263d55307 165 #define __I volatile const /*!< Defines 'read only' permissions */
<> 149:156823d33999 166 #endif
AnnaBridge 167:e84263d55307 167 #define __O volatile /*!< Defines 'write only' permissions */
AnnaBridge 167:e84263d55307 168 #define __IO volatile /*!< Defines 'read / write' permissions */
<> 149:156823d33999 169
AnnaBridge 167:e84263d55307 170 /* following defines should be used for structure members */
AnnaBridge 167:e84263d55307 171 #define __IM volatile const /*! Defines 'read only' structure member permissions */
AnnaBridge 167:e84263d55307 172 #define __OM volatile /*! Defines 'write only' structure member permissions */
AnnaBridge 167:e84263d55307 173 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
<> 150:02e0a0aed4ec 174
<> 149:156823d33999 175 /*@} end of group Cortex_M3 */
<> 149:156823d33999 176
<> 149:156823d33999 177
<> 149:156823d33999 178
<> 149:156823d33999 179 /*******************************************************************************
<> 149:156823d33999 180 * Register Abstraction
<> 149:156823d33999 181 Core Register contain:
<> 149:156823d33999 182 - Core Register
<> 149:156823d33999 183 - Core NVIC Register
<> 149:156823d33999 184 - Core SCB Register
<> 149:156823d33999 185 - Core SysTick Register
<> 149:156823d33999 186 - Core Debug Register
<> 149:156823d33999 187 - Core MPU Register
<> 149:156823d33999 188 ******************************************************************************/
AnnaBridge 167:e84263d55307 189 /**
AnnaBridge 167:e84263d55307 190 \defgroup CMSIS_core_register Defines and Type Definitions
AnnaBridge 167:e84263d55307 191 \brief Type definitions and defines for Cortex-M processor based devices.
<> 149:156823d33999 192 */
<> 149:156823d33999 193
AnnaBridge 167:e84263d55307 194 /**
AnnaBridge 167:e84263d55307 195 \ingroup CMSIS_core_register
AnnaBridge 167:e84263d55307 196 \defgroup CMSIS_CORE Status and Control Registers
AnnaBridge 167:e84263d55307 197 \brief Core Register type definitions.
<> 149:156823d33999 198 @{
<> 149:156823d33999 199 */
<> 149:156823d33999 200
AnnaBridge 167:e84263d55307 201 /**
AnnaBridge 167:e84263d55307 202 \brief Union type to access the Application Program Status Register (APSR).
<> 149:156823d33999 203 */
<> 149:156823d33999 204 typedef union
<> 149:156823d33999 205 {
<> 149:156823d33999 206 struct
<> 149:156823d33999 207 {
AnnaBridge 167:e84263d55307 208 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
AnnaBridge 167:e84263d55307 209 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
AnnaBridge 167:e84263d55307 210 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
AnnaBridge 167:e84263d55307 211 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
AnnaBridge 167:e84263d55307 212 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
AnnaBridge 167:e84263d55307 213 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
AnnaBridge 167:e84263d55307 214 } b; /*!< Structure used for bit access */
AnnaBridge 167:e84263d55307 215 uint32_t w; /*!< Type used for word access */
<> 149:156823d33999 216 } APSR_Type;
<> 149:156823d33999 217
<> 149:156823d33999 218 /* APSR Register Definitions */
AnnaBridge 167:e84263d55307 219 #define APSR_N_Pos 31U /*!< APSR: N Position */
<> 149:156823d33999 220 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
<> 149:156823d33999 221
AnnaBridge 167:e84263d55307 222 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
<> 149:156823d33999 223 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
<> 149:156823d33999 224
AnnaBridge 167:e84263d55307 225 #define APSR_C_Pos 29U /*!< APSR: C Position */
<> 149:156823d33999 226 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
<> 149:156823d33999 227
AnnaBridge 167:e84263d55307 228 #define APSR_V_Pos 28U /*!< APSR: V Position */
<> 149:156823d33999 229 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
<> 149:156823d33999 230
AnnaBridge 167:e84263d55307 231 #define APSR_Q_Pos 27U /*!< APSR: Q Position */
<> 149:156823d33999 232 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
<> 149:156823d33999 233
<> 149:156823d33999 234
AnnaBridge 167:e84263d55307 235 /**
AnnaBridge 167:e84263d55307 236 \brief Union type to access the Interrupt Program Status Register (IPSR).
<> 149:156823d33999 237 */
<> 149:156823d33999 238 typedef union
<> 149:156823d33999 239 {
<> 149:156823d33999 240 struct
<> 149:156823d33999 241 {
AnnaBridge 167:e84263d55307 242 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
AnnaBridge 167:e84263d55307 243 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
AnnaBridge 167:e84263d55307 244 } b; /*!< Structure used for bit access */
AnnaBridge 167:e84263d55307 245 uint32_t w; /*!< Type used for word access */
<> 149:156823d33999 246 } IPSR_Type;
<> 149:156823d33999 247
<> 149:156823d33999 248 /* IPSR Register Definitions */
AnnaBridge 167:e84263d55307 249 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
<> 149:156823d33999 250 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
<> 149:156823d33999 251
<> 149:156823d33999 252
AnnaBridge 167:e84263d55307 253 /**
AnnaBridge 167:e84263d55307 254 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
<> 149:156823d33999 255 */
<> 149:156823d33999 256 typedef union
<> 149:156823d33999 257 {
<> 149:156823d33999 258 struct
<> 149:156823d33999 259 {
AnnaBridge 167:e84263d55307 260 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
AnnaBridge 167:e84263d55307 261 uint32_t _reserved0:1; /*!< bit: 9 Reserved */
AnnaBridge 167:e84263d55307 262 uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
AnnaBridge 167:e84263d55307 263 uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */
AnnaBridge 167:e84263d55307 264 uint32_t T:1; /*!< bit: 24 Thumb bit */
AnnaBridge 167:e84263d55307 265 uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
AnnaBridge 167:e84263d55307 266 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
AnnaBridge 167:e84263d55307 267 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
AnnaBridge 167:e84263d55307 268 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
AnnaBridge 167:e84263d55307 269 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
AnnaBridge 167:e84263d55307 270 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
AnnaBridge 167:e84263d55307 271 } b; /*!< Structure used for bit access */
AnnaBridge 167:e84263d55307 272 uint32_t w; /*!< Type used for word access */
<> 149:156823d33999 273 } xPSR_Type;
<> 149:156823d33999 274
<> 149:156823d33999 275 /* xPSR Register Definitions */
AnnaBridge 167:e84263d55307 276 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
<> 149:156823d33999 277 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
<> 149:156823d33999 278
AnnaBridge 167:e84263d55307 279 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
<> 149:156823d33999 280 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
<> 149:156823d33999 281
AnnaBridge 167:e84263d55307 282 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
<> 149:156823d33999 283 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
<> 149:156823d33999 284
AnnaBridge 167:e84263d55307 285 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
<> 149:156823d33999 286 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
<> 149:156823d33999 287
AnnaBridge 167:e84263d55307 288 #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
<> 149:156823d33999 289 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
<> 149:156823d33999 290
AnnaBridge 167:e84263d55307 291 #define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
AnnaBridge 167:e84263d55307 292 #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
<> 149:156823d33999 293
AnnaBridge 167:e84263d55307 294 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
<> 149:156823d33999 295 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
<> 149:156823d33999 296
AnnaBridge 167:e84263d55307 297 #define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
AnnaBridge 167:e84263d55307 298 #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
AnnaBridge 167:e84263d55307 299
AnnaBridge 167:e84263d55307 300 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
<> 149:156823d33999 301 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
<> 149:156823d33999 302
<> 149:156823d33999 303
AnnaBridge 167:e84263d55307 304 /**
AnnaBridge 167:e84263d55307 305 \brief Union type to access the Control Registers (CONTROL).
<> 149:156823d33999 306 */
<> 149:156823d33999 307 typedef union
<> 149:156823d33999 308 {
<> 149:156823d33999 309 struct
<> 149:156823d33999 310 {
<> 149:156823d33999 311 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
AnnaBridge 167:e84263d55307 312 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
AnnaBridge 167:e84263d55307 313 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
AnnaBridge 167:e84263d55307 314 } b; /*!< Structure used for bit access */
AnnaBridge 167:e84263d55307 315 uint32_t w; /*!< Type used for word access */
<> 149:156823d33999 316 } CONTROL_Type;
<> 149:156823d33999 317
<> 149:156823d33999 318 /* CONTROL Register Definitions */
AnnaBridge 167:e84263d55307 319 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
<> 149:156823d33999 320 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
<> 149:156823d33999 321
AnnaBridge 167:e84263d55307 322 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
<> 149:156823d33999 323 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
<> 149:156823d33999 324
<> 149:156823d33999 325 /*@} end of group CMSIS_CORE */
<> 149:156823d33999 326
<> 149:156823d33999 327
AnnaBridge 167:e84263d55307 328 /**
AnnaBridge 167:e84263d55307 329 \ingroup CMSIS_core_register
AnnaBridge 167:e84263d55307 330 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
AnnaBridge 167:e84263d55307 331 \brief Type definitions for the NVIC Registers
<> 149:156823d33999 332 @{
<> 149:156823d33999 333 */
<> 149:156823d33999 334
AnnaBridge 167:e84263d55307 335 /**
AnnaBridge 167:e84263d55307 336 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
<> 149:156823d33999 337 */
<> 149:156823d33999 338 typedef struct
<> 149:156823d33999 339 {
AnnaBridge 167:e84263d55307 340 __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
AnnaBridge 167:e84263d55307 341 uint32_t RESERVED0[24U];
AnnaBridge 167:e84263d55307 342 __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
AnnaBridge 167:e84263d55307 343 uint32_t RSERVED1[24U];
AnnaBridge 167:e84263d55307 344 __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
AnnaBridge 167:e84263d55307 345 uint32_t RESERVED2[24U];
AnnaBridge 167:e84263d55307 346 __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
AnnaBridge 167:e84263d55307 347 uint32_t RESERVED3[24U];
AnnaBridge 167:e84263d55307 348 __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
AnnaBridge 167:e84263d55307 349 uint32_t RESERVED4[56U];
AnnaBridge 167:e84263d55307 350 __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
AnnaBridge 167:e84263d55307 351 uint32_t RESERVED5[644U];
AnnaBridge 167:e84263d55307 352 __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
<> 149:156823d33999 353 } NVIC_Type;
<> 149:156823d33999 354
<> 149:156823d33999 355 /* Software Triggered Interrupt Register Definitions */
AnnaBridge 167:e84263d55307 356 #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
<> 149:156823d33999 357 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
<> 149:156823d33999 358
<> 149:156823d33999 359 /*@} end of group CMSIS_NVIC */
<> 149:156823d33999 360
<> 149:156823d33999 361
AnnaBridge 167:e84263d55307 362 /**
AnnaBridge 167:e84263d55307 363 \ingroup CMSIS_core_register
AnnaBridge 167:e84263d55307 364 \defgroup CMSIS_SCB System Control Block (SCB)
AnnaBridge 167:e84263d55307 365 \brief Type definitions for the System Control Block Registers
<> 149:156823d33999 366 @{
<> 149:156823d33999 367 */
<> 149:156823d33999 368
AnnaBridge 167:e84263d55307 369 /**
AnnaBridge 167:e84263d55307 370 \brief Structure type to access the System Control Block (SCB).
<> 149:156823d33999 371 */
<> 149:156823d33999 372 typedef struct
<> 149:156823d33999 373 {
AnnaBridge 167:e84263d55307 374 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
AnnaBridge 167:e84263d55307 375 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
AnnaBridge 167:e84263d55307 376 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
AnnaBridge 167:e84263d55307 377 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
AnnaBridge 167:e84263d55307 378 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
AnnaBridge 167:e84263d55307 379 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
AnnaBridge 167:e84263d55307 380 __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
AnnaBridge 167:e84263d55307 381 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
AnnaBridge 167:e84263d55307 382 __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
AnnaBridge 167:e84263d55307 383 __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
AnnaBridge 167:e84263d55307 384 __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
AnnaBridge 167:e84263d55307 385 __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
AnnaBridge 167:e84263d55307 386 __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
AnnaBridge 167:e84263d55307 387 __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
AnnaBridge 167:e84263d55307 388 __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
AnnaBridge 167:e84263d55307 389 __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
AnnaBridge 167:e84263d55307 390 __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
AnnaBridge 167:e84263d55307 391 __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
AnnaBridge 167:e84263d55307 392 __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
AnnaBridge 167:e84263d55307 393 uint32_t RESERVED0[5U];
AnnaBridge 167:e84263d55307 394 __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
<> 149:156823d33999 395 } SCB_Type;
<> 149:156823d33999 396
<> 149:156823d33999 397 /* SCB CPUID Register Definitions */
AnnaBridge 167:e84263d55307 398 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
<> 149:156823d33999 399 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
<> 149:156823d33999 400
AnnaBridge 167:e84263d55307 401 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
<> 149:156823d33999 402 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
<> 149:156823d33999 403
AnnaBridge 167:e84263d55307 404 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
<> 149:156823d33999 405 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
<> 149:156823d33999 406
AnnaBridge 167:e84263d55307 407 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
<> 149:156823d33999 408 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
<> 149:156823d33999 409
AnnaBridge 167:e84263d55307 410 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
<> 149:156823d33999 411 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
<> 149:156823d33999 412
<> 149:156823d33999 413 /* SCB Interrupt Control State Register Definitions */
AnnaBridge 167:e84263d55307 414 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
<> 149:156823d33999 415 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
<> 149:156823d33999 416
AnnaBridge 167:e84263d55307 417 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
<> 149:156823d33999 418 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
<> 149:156823d33999 419
AnnaBridge 167:e84263d55307 420 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
<> 149:156823d33999 421 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
<> 149:156823d33999 422
AnnaBridge 167:e84263d55307 423 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
<> 149:156823d33999 424 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
<> 149:156823d33999 425
AnnaBridge 167:e84263d55307 426 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
<> 149:156823d33999 427 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
<> 149:156823d33999 428
AnnaBridge 167:e84263d55307 429 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
<> 149:156823d33999 430 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
<> 149:156823d33999 431
AnnaBridge 167:e84263d55307 432 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
<> 149:156823d33999 433 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
<> 149:156823d33999 434
AnnaBridge 167:e84263d55307 435 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
<> 149:156823d33999 436 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
<> 149:156823d33999 437
AnnaBridge 167:e84263d55307 438 #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
<> 149:156823d33999 439 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
<> 149:156823d33999 440
AnnaBridge 167:e84263d55307 441 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
<> 149:156823d33999 442 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
<> 149:156823d33999 443
<> 149:156823d33999 444 /* SCB Vector Table Offset Register Definitions */
AnnaBridge 167:e84263d55307 445 #if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */
AnnaBridge 167:e84263d55307 446 #define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */
<> 149:156823d33999 447 #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
<> 149:156823d33999 448
AnnaBridge 167:e84263d55307 449 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
<> 149:156823d33999 450 #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
<> 149:156823d33999 451 #else
AnnaBridge 167:e84263d55307 452 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
<> 149:156823d33999 453 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
<> 149:156823d33999 454 #endif
<> 149:156823d33999 455
<> 149:156823d33999 456 /* SCB Application Interrupt and Reset Control Register Definitions */
AnnaBridge 167:e84263d55307 457 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
<> 149:156823d33999 458 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
<> 149:156823d33999 459
AnnaBridge 167:e84263d55307 460 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
<> 149:156823d33999 461 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
<> 149:156823d33999 462
AnnaBridge 167:e84263d55307 463 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
<> 149:156823d33999 464 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
<> 149:156823d33999 465
AnnaBridge 167:e84263d55307 466 #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
<> 149:156823d33999 467 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
<> 149:156823d33999 468
AnnaBridge 167:e84263d55307 469 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
<> 149:156823d33999 470 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
<> 149:156823d33999 471
AnnaBridge 167:e84263d55307 472 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
<> 149:156823d33999 473 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
<> 149:156823d33999 474
AnnaBridge 167:e84263d55307 475 #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
<> 149:156823d33999 476 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
<> 149:156823d33999 477
<> 149:156823d33999 478 /* SCB System Control Register Definitions */
AnnaBridge 167:e84263d55307 479 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
<> 149:156823d33999 480 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
<> 149:156823d33999 481
AnnaBridge 167:e84263d55307 482 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
<> 149:156823d33999 483 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
<> 149:156823d33999 484
AnnaBridge 167:e84263d55307 485 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
<> 149:156823d33999 486 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
<> 149:156823d33999 487
<> 149:156823d33999 488 /* SCB Configuration Control Register Definitions */
AnnaBridge 167:e84263d55307 489 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
<> 149:156823d33999 490 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
<> 149:156823d33999 491
AnnaBridge 167:e84263d55307 492 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
<> 149:156823d33999 493 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
<> 149:156823d33999 494
AnnaBridge 167:e84263d55307 495 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
<> 149:156823d33999 496 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
<> 149:156823d33999 497
AnnaBridge 167:e84263d55307 498 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
<> 149:156823d33999 499 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
<> 149:156823d33999 500
AnnaBridge 167:e84263d55307 501 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
<> 149:156823d33999 502 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
<> 149:156823d33999 503
AnnaBridge 167:e84263d55307 504 #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
<> 149:156823d33999 505 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
<> 149:156823d33999 506
<> 149:156823d33999 507 /* SCB System Handler Control and State Register Definitions */
AnnaBridge 167:e84263d55307 508 #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
<> 149:156823d33999 509 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
<> 149:156823d33999 510
AnnaBridge 167:e84263d55307 511 #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
<> 149:156823d33999 512 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
<> 149:156823d33999 513
AnnaBridge 167:e84263d55307 514 #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
<> 149:156823d33999 515 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
<> 149:156823d33999 516
AnnaBridge 167:e84263d55307 517 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
<> 149:156823d33999 518 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
<> 149:156823d33999 519
AnnaBridge 167:e84263d55307 520 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
<> 149:156823d33999 521 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
<> 149:156823d33999 522
AnnaBridge 167:e84263d55307 523 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
<> 149:156823d33999 524 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
<> 149:156823d33999 525
AnnaBridge 167:e84263d55307 526 #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
<> 149:156823d33999 527 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
<> 149:156823d33999 528
AnnaBridge 167:e84263d55307 529 #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
<> 149:156823d33999 530 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
<> 149:156823d33999 531
AnnaBridge 167:e84263d55307 532 #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
<> 149:156823d33999 533 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
<> 149:156823d33999 534
AnnaBridge 167:e84263d55307 535 #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
<> 149:156823d33999 536 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
<> 149:156823d33999 537
AnnaBridge 167:e84263d55307 538 #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
<> 149:156823d33999 539 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
<> 149:156823d33999 540
AnnaBridge 167:e84263d55307 541 #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
<> 149:156823d33999 542 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
<> 149:156823d33999 543
AnnaBridge 167:e84263d55307 544 #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
<> 149:156823d33999 545 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
<> 149:156823d33999 546
AnnaBridge 167:e84263d55307 547 #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
<> 149:156823d33999 548 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
<> 149:156823d33999 549
AnnaBridge 167:e84263d55307 550 /* SCB Configurable Fault Status Register Definitions */
AnnaBridge 167:e84263d55307 551 #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
<> 149:156823d33999 552 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
<> 149:156823d33999 553
AnnaBridge 167:e84263d55307 554 #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
<> 149:156823d33999 555 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
<> 149:156823d33999 556
AnnaBridge 167:e84263d55307 557 #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
<> 149:156823d33999 558 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
<> 149:156823d33999 559
AnnaBridge 167:e84263d55307 560 /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
AnnaBridge 167:e84263d55307 561 #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
AnnaBridge 167:e84263d55307 562 #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
AnnaBridge 167:e84263d55307 563
AnnaBridge 167:e84263d55307 564 #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
AnnaBridge 167:e84263d55307 565 #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
AnnaBridge 167:e84263d55307 566
AnnaBridge 167:e84263d55307 567 #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
AnnaBridge 167:e84263d55307 568 #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
AnnaBridge 167:e84263d55307 569
AnnaBridge 167:e84263d55307 570 #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
AnnaBridge 167:e84263d55307 571 #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
AnnaBridge 167:e84263d55307 572
AnnaBridge 167:e84263d55307 573 #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
AnnaBridge 167:e84263d55307 574 #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
AnnaBridge 167:e84263d55307 575
AnnaBridge 167:e84263d55307 576 /* BusFault Status Register (part of SCB Configurable Fault Status Register) */
AnnaBridge 167:e84263d55307 577 #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
AnnaBridge 167:e84263d55307 578 #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
AnnaBridge 167:e84263d55307 579
AnnaBridge 167:e84263d55307 580 #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
AnnaBridge 167:e84263d55307 581 #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
AnnaBridge 167:e84263d55307 582
AnnaBridge 167:e84263d55307 583 #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
AnnaBridge 167:e84263d55307 584 #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
AnnaBridge 167:e84263d55307 585
AnnaBridge 167:e84263d55307 586 #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
AnnaBridge 167:e84263d55307 587 #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
AnnaBridge 167:e84263d55307 588
AnnaBridge 167:e84263d55307 589 #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
AnnaBridge 167:e84263d55307 590 #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
AnnaBridge 167:e84263d55307 591
AnnaBridge 167:e84263d55307 592 #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
AnnaBridge 167:e84263d55307 593 #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
AnnaBridge 167:e84263d55307 594
AnnaBridge 167:e84263d55307 595 /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
AnnaBridge 167:e84263d55307 596 #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
AnnaBridge 167:e84263d55307 597 #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
AnnaBridge 167:e84263d55307 598
AnnaBridge 167:e84263d55307 599 #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
AnnaBridge 167:e84263d55307 600 #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
AnnaBridge 167:e84263d55307 601
AnnaBridge 167:e84263d55307 602 #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
AnnaBridge 167:e84263d55307 603 #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
AnnaBridge 167:e84263d55307 604
AnnaBridge 167:e84263d55307 605 #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
AnnaBridge 167:e84263d55307 606 #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
AnnaBridge 167:e84263d55307 607
AnnaBridge 167:e84263d55307 608 #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
AnnaBridge 167:e84263d55307 609 #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
AnnaBridge 167:e84263d55307 610
AnnaBridge 167:e84263d55307 611 #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
AnnaBridge 167:e84263d55307 612 #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
AnnaBridge 167:e84263d55307 613
AnnaBridge 167:e84263d55307 614 /* SCB Hard Fault Status Register Definitions */
AnnaBridge 167:e84263d55307 615 #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
<> 149:156823d33999 616 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
<> 149:156823d33999 617
AnnaBridge 167:e84263d55307 618 #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
<> 149:156823d33999 619 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
<> 149:156823d33999 620
AnnaBridge 167:e84263d55307 621 #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
<> 149:156823d33999 622 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
<> 149:156823d33999 623
<> 149:156823d33999 624 /* SCB Debug Fault Status Register Definitions */
AnnaBridge 167:e84263d55307 625 #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
<> 149:156823d33999 626 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
<> 149:156823d33999 627
AnnaBridge 167:e84263d55307 628 #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
<> 149:156823d33999 629 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
<> 149:156823d33999 630
AnnaBridge 167:e84263d55307 631 #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
<> 149:156823d33999 632 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
<> 149:156823d33999 633
AnnaBridge 167:e84263d55307 634 #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
<> 149:156823d33999 635 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
<> 149:156823d33999 636
AnnaBridge 167:e84263d55307 637 #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
<> 149:156823d33999 638 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
<> 149:156823d33999 639
<> 149:156823d33999 640 /*@} end of group CMSIS_SCB */
<> 149:156823d33999 641
<> 149:156823d33999 642
AnnaBridge 167:e84263d55307 643 /**
AnnaBridge 167:e84263d55307 644 \ingroup CMSIS_core_register
AnnaBridge 167:e84263d55307 645 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
AnnaBridge 167:e84263d55307 646 \brief Type definitions for the System Control and ID Register not in the SCB
<> 149:156823d33999 647 @{
<> 149:156823d33999 648 */
<> 149:156823d33999 649
AnnaBridge 167:e84263d55307 650 /**
AnnaBridge 167:e84263d55307 651 \brief Structure type to access the System Control and ID Register not in the SCB.
<> 149:156823d33999 652 */
<> 149:156823d33999 653 typedef struct
<> 149:156823d33999 654 {
AnnaBridge 167:e84263d55307 655 uint32_t RESERVED0[1U];
AnnaBridge 167:e84263d55307 656 __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
AnnaBridge 167:e84263d55307 657 #if defined (__CM3_REV) && (__CM3_REV >= 0x200U)
AnnaBridge 167:e84263d55307 658 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
<> 149:156823d33999 659 #else
AnnaBridge 167:e84263d55307 660 uint32_t RESERVED1[1U];
<> 149:156823d33999 661 #endif
<> 149:156823d33999 662 } SCnSCB_Type;
<> 149:156823d33999 663
<> 149:156823d33999 664 /* Interrupt Controller Type Register Definitions */
AnnaBridge 167:e84263d55307 665 #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
<> 149:156823d33999 666 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
<> 149:156823d33999 667
<> 149:156823d33999 668 /* Auxiliary Control Register Definitions */
<> 149:156823d33999 669
AnnaBridge 167:e84263d55307 670 #define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
<> 149:156823d33999 671 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
<> 149:156823d33999 672
AnnaBridge 167:e84263d55307 673 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */
<> 149:156823d33999 674 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
<> 149:156823d33999 675
AnnaBridge 167:e84263d55307 676 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
<> 149:156823d33999 677 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
<> 149:156823d33999 678
<> 149:156823d33999 679 /*@} end of group CMSIS_SCnotSCB */
<> 149:156823d33999 680
<> 149:156823d33999 681
AnnaBridge 167:e84263d55307 682 /**
AnnaBridge 167:e84263d55307 683 \ingroup CMSIS_core_register
AnnaBridge 167:e84263d55307 684 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
AnnaBridge 167:e84263d55307 685 \brief Type definitions for the System Timer Registers.
<> 149:156823d33999 686 @{
<> 149:156823d33999 687 */
<> 149:156823d33999 688
AnnaBridge 167:e84263d55307 689 /**
AnnaBridge 167:e84263d55307 690 \brief Structure type to access the System Timer (SysTick).
<> 149:156823d33999 691 */
<> 149:156823d33999 692 typedef struct
<> 149:156823d33999 693 {
AnnaBridge 167:e84263d55307 694 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
AnnaBridge 167:e84263d55307 695 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
AnnaBridge 167:e84263d55307 696 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
AnnaBridge 167:e84263d55307 697 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
<> 149:156823d33999 698 } SysTick_Type;
<> 149:156823d33999 699
<> 149:156823d33999 700 /* SysTick Control / Status Register Definitions */
AnnaBridge 167:e84263d55307 701 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
<> 149:156823d33999 702 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
<> 149:156823d33999 703
AnnaBridge 167:e84263d55307 704 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
<> 149:156823d33999 705 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
<> 149:156823d33999 706
AnnaBridge 167:e84263d55307 707 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
<> 149:156823d33999 708 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
<> 149:156823d33999 709
AnnaBridge 167:e84263d55307 710 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
<> 149:156823d33999 711 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
<> 149:156823d33999 712
<> 149:156823d33999 713 /* SysTick Reload Register Definitions */
AnnaBridge 167:e84263d55307 714 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
<> 149:156823d33999 715 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
<> 149:156823d33999 716
<> 149:156823d33999 717 /* SysTick Current Register Definitions */
AnnaBridge 167:e84263d55307 718 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
<> 149:156823d33999 719 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
<> 149:156823d33999 720
<> 149:156823d33999 721 /* SysTick Calibration Register Definitions */
AnnaBridge 167:e84263d55307 722 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
<> 149:156823d33999 723 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
<> 149:156823d33999 724
AnnaBridge 167:e84263d55307 725 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
<> 149:156823d33999 726 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
<> 149:156823d33999 727
AnnaBridge 167:e84263d55307 728 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
<> 149:156823d33999 729 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
<> 149:156823d33999 730
<> 149:156823d33999 731 /*@} end of group CMSIS_SysTick */
<> 149:156823d33999 732
<> 149:156823d33999 733
AnnaBridge 167:e84263d55307 734 /**
AnnaBridge 167:e84263d55307 735 \ingroup CMSIS_core_register
AnnaBridge 167:e84263d55307 736 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
AnnaBridge 167:e84263d55307 737 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
<> 149:156823d33999 738 @{
<> 149:156823d33999 739 */
<> 149:156823d33999 740
AnnaBridge 167:e84263d55307 741 /**
AnnaBridge 167:e84263d55307 742 \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
<> 149:156823d33999 743 */
<> 149:156823d33999 744 typedef struct
<> 149:156823d33999 745 {
AnnaBridge 167:e84263d55307 746 __OM union
<> 149:156823d33999 747 {
AnnaBridge 167:e84263d55307 748 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
AnnaBridge 167:e84263d55307 749 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
AnnaBridge 167:e84263d55307 750 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
AnnaBridge 167:e84263d55307 751 } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
AnnaBridge 167:e84263d55307 752 uint32_t RESERVED0[864U];
AnnaBridge 167:e84263d55307 753 __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
AnnaBridge 167:e84263d55307 754 uint32_t RESERVED1[15U];
AnnaBridge 167:e84263d55307 755 __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
AnnaBridge 167:e84263d55307 756 uint32_t RESERVED2[15U];
AnnaBridge 167:e84263d55307 757 __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
AnnaBridge 167:e84263d55307 758 uint32_t RESERVED3[29U];
AnnaBridge 167:e84263d55307 759 __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
AnnaBridge 167:e84263d55307 760 __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
AnnaBridge 167:e84263d55307 761 __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
AnnaBridge 167:e84263d55307 762 uint32_t RESERVED4[43U];
AnnaBridge 167:e84263d55307 763 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
AnnaBridge 167:e84263d55307 764 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
AnnaBridge 167:e84263d55307 765 uint32_t RESERVED5[6U];
AnnaBridge 167:e84263d55307 766 __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
AnnaBridge 167:e84263d55307 767 __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
AnnaBridge 167:e84263d55307 768 __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
AnnaBridge 167:e84263d55307 769 __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
AnnaBridge 167:e84263d55307 770 __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
AnnaBridge 167:e84263d55307 771 __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
AnnaBridge 167:e84263d55307 772 __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
AnnaBridge 167:e84263d55307 773 __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
AnnaBridge 167:e84263d55307 774 __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
AnnaBridge 167:e84263d55307 775 __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
AnnaBridge 167:e84263d55307 776 __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
AnnaBridge 167:e84263d55307 777 __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
<> 149:156823d33999 778 } ITM_Type;
<> 149:156823d33999 779
<> 149:156823d33999 780 /* ITM Trace Privilege Register Definitions */
AnnaBridge 167:e84263d55307 781 #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
<> 149:156823d33999 782 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
<> 149:156823d33999 783
<> 149:156823d33999 784 /* ITM Trace Control Register Definitions */
AnnaBridge 167:e84263d55307 785 #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
<> 149:156823d33999 786 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
<> 149:156823d33999 787
AnnaBridge 167:e84263d55307 788 #define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
<> 149:156823d33999 789 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
<> 149:156823d33999 790
AnnaBridge 167:e84263d55307 791 #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
<> 149:156823d33999 792 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
<> 149:156823d33999 793
AnnaBridge 167:e84263d55307 794 #define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
<> 149:156823d33999 795 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
<> 149:156823d33999 796
AnnaBridge 167:e84263d55307 797 #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
<> 149:156823d33999 798 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
<> 149:156823d33999 799
AnnaBridge 167:e84263d55307 800 #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
<> 149:156823d33999 801 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
<> 149:156823d33999 802
AnnaBridge 167:e84263d55307 803 #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
<> 149:156823d33999 804 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
<> 149:156823d33999 805
AnnaBridge 167:e84263d55307 806 #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
<> 149:156823d33999 807 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
<> 149:156823d33999 808
AnnaBridge 167:e84263d55307 809 #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
<> 149:156823d33999 810 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
<> 149:156823d33999 811
<> 149:156823d33999 812 /* ITM Integration Write Register Definitions */
AnnaBridge 167:e84263d55307 813 #define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
<> 149:156823d33999 814 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
<> 149:156823d33999 815
<> 149:156823d33999 816 /* ITM Integration Read Register Definitions */
AnnaBridge 167:e84263d55307 817 #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
<> 149:156823d33999 818 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
<> 149:156823d33999 819
<> 149:156823d33999 820 /* ITM Integration Mode Control Register Definitions */
AnnaBridge 167:e84263d55307 821 #define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
<> 149:156823d33999 822 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
<> 149:156823d33999 823
<> 149:156823d33999 824 /* ITM Lock Status Register Definitions */
AnnaBridge 167:e84263d55307 825 #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
<> 149:156823d33999 826 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
<> 149:156823d33999 827
AnnaBridge 167:e84263d55307 828 #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
<> 149:156823d33999 829 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
<> 149:156823d33999 830
AnnaBridge 167:e84263d55307 831 #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
<> 149:156823d33999 832 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
<> 149:156823d33999 833
<> 149:156823d33999 834 /*@}*/ /* end of group CMSIS_ITM */
<> 149:156823d33999 835
<> 149:156823d33999 836
AnnaBridge 167:e84263d55307 837 /**
AnnaBridge 167:e84263d55307 838 \ingroup CMSIS_core_register
AnnaBridge 167:e84263d55307 839 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
AnnaBridge 167:e84263d55307 840 \brief Type definitions for the Data Watchpoint and Trace (DWT)
<> 149:156823d33999 841 @{
<> 149:156823d33999 842 */
<> 149:156823d33999 843
AnnaBridge 167:e84263d55307 844 /**
AnnaBridge 167:e84263d55307 845 \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
<> 149:156823d33999 846 */
<> 149:156823d33999 847 typedef struct
<> 149:156823d33999 848 {
AnnaBridge 167:e84263d55307 849 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
AnnaBridge 167:e84263d55307 850 __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
AnnaBridge 167:e84263d55307 851 __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
AnnaBridge 167:e84263d55307 852 __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
AnnaBridge 167:e84263d55307 853 __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
AnnaBridge 167:e84263d55307 854 __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
AnnaBridge 167:e84263d55307 855 __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
AnnaBridge 167:e84263d55307 856 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
AnnaBridge 167:e84263d55307 857 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
AnnaBridge 167:e84263d55307 858 __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
AnnaBridge 167:e84263d55307 859 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
AnnaBridge 167:e84263d55307 860 uint32_t RESERVED0[1U];
AnnaBridge 167:e84263d55307 861 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
AnnaBridge 167:e84263d55307 862 __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
AnnaBridge 167:e84263d55307 863 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
AnnaBridge 167:e84263d55307 864 uint32_t RESERVED1[1U];
AnnaBridge 167:e84263d55307 865 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
AnnaBridge 167:e84263d55307 866 __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
AnnaBridge 167:e84263d55307 867 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
AnnaBridge 167:e84263d55307 868 uint32_t RESERVED2[1U];
AnnaBridge 167:e84263d55307 869 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
AnnaBridge 167:e84263d55307 870 __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
AnnaBridge 167:e84263d55307 871 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
<> 149:156823d33999 872 } DWT_Type;
<> 149:156823d33999 873
<> 149:156823d33999 874 /* DWT Control Register Definitions */
AnnaBridge 167:e84263d55307 875 #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
<> 149:156823d33999 876 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
<> 149:156823d33999 877
AnnaBridge 167:e84263d55307 878 #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
<> 149:156823d33999 879 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
<> 149:156823d33999 880
AnnaBridge 167:e84263d55307 881 #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
<> 149:156823d33999 882 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
<> 149:156823d33999 883
AnnaBridge 167:e84263d55307 884 #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
<> 149:156823d33999 885 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
<> 149:156823d33999 886
AnnaBridge 167:e84263d55307 887 #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
<> 149:156823d33999 888 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
<> 149:156823d33999 889
AnnaBridge 167:e84263d55307 890 #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
<> 149:156823d33999 891 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
<> 149:156823d33999 892
AnnaBridge 167:e84263d55307 893 #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
<> 149:156823d33999 894 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
<> 149:156823d33999 895
AnnaBridge 167:e84263d55307 896 #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
<> 149:156823d33999 897 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
<> 149:156823d33999 898
AnnaBridge 167:e84263d55307 899 #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
<> 149:156823d33999 900 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
<> 149:156823d33999 901
AnnaBridge 167:e84263d55307 902 #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
<> 149:156823d33999 903 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
<> 149:156823d33999 904
AnnaBridge 167:e84263d55307 905 #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
<> 149:156823d33999 906 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
<> 149:156823d33999 907
AnnaBridge 167:e84263d55307 908 #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
<> 149:156823d33999 909 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
<> 149:156823d33999 910
AnnaBridge 167:e84263d55307 911 #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
<> 149:156823d33999 912 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
<> 149:156823d33999 913
AnnaBridge 167:e84263d55307 914 #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
<> 149:156823d33999 915 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
<> 149:156823d33999 916
AnnaBridge 167:e84263d55307 917 #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
<> 149:156823d33999 918 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
<> 149:156823d33999 919
AnnaBridge 167:e84263d55307 920 #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
<> 149:156823d33999 921 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
<> 149:156823d33999 922
AnnaBridge 167:e84263d55307 923 #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
<> 149:156823d33999 924 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
<> 149:156823d33999 925
AnnaBridge 167:e84263d55307 926 #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
<> 149:156823d33999 927 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
<> 149:156823d33999 928
<> 149:156823d33999 929 /* DWT CPI Count Register Definitions */
AnnaBridge 167:e84263d55307 930 #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
<> 149:156823d33999 931 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
<> 149:156823d33999 932
<> 149:156823d33999 933 /* DWT Exception Overhead Count Register Definitions */
AnnaBridge 167:e84263d55307 934 #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
<> 149:156823d33999 935 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
<> 149:156823d33999 936
<> 149:156823d33999 937 /* DWT Sleep Count Register Definitions */
AnnaBridge 167:e84263d55307 938 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
<> 149:156823d33999 939 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
<> 149:156823d33999 940
<> 149:156823d33999 941 /* DWT LSU Count Register Definitions */
AnnaBridge 167:e84263d55307 942 #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
<> 149:156823d33999 943 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
<> 149:156823d33999 944
<> 149:156823d33999 945 /* DWT Folded-instruction Count Register Definitions */
AnnaBridge 167:e84263d55307 946 #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
<> 149:156823d33999 947 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
<> 149:156823d33999 948
<> 149:156823d33999 949 /* DWT Comparator Mask Register Definitions */
AnnaBridge 167:e84263d55307 950 #define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
<> 149:156823d33999 951 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
<> 149:156823d33999 952
<> 149:156823d33999 953 /* DWT Comparator Function Register Definitions */
AnnaBridge 167:e84263d55307 954 #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
<> 149:156823d33999 955 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
<> 149:156823d33999 956
AnnaBridge 167:e84263d55307 957 #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
<> 149:156823d33999 958 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
<> 149:156823d33999 959
AnnaBridge 167:e84263d55307 960 #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
<> 149:156823d33999 961 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
<> 149:156823d33999 962
AnnaBridge 167:e84263d55307 963 #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
<> 149:156823d33999 964 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
<> 149:156823d33999 965
AnnaBridge 167:e84263d55307 966 #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
<> 149:156823d33999 967 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
<> 149:156823d33999 968
AnnaBridge 167:e84263d55307 969 #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
<> 149:156823d33999 970 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
<> 149:156823d33999 971
AnnaBridge 167:e84263d55307 972 #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
<> 149:156823d33999 973 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
<> 149:156823d33999 974
AnnaBridge 167:e84263d55307 975 #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
<> 149:156823d33999 976 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
<> 149:156823d33999 977
AnnaBridge 167:e84263d55307 978 #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
<> 149:156823d33999 979 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
<> 149:156823d33999 980
<> 149:156823d33999 981 /*@}*/ /* end of group CMSIS_DWT */
<> 149:156823d33999 982
<> 149:156823d33999 983
AnnaBridge 167:e84263d55307 984 /**
AnnaBridge 167:e84263d55307 985 \ingroup CMSIS_core_register
AnnaBridge 167:e84263d55307 986 \defgroup CMSIS_TPI Trace Port Interface (TPI)
AnnaBridge 167:e84263d55307 987 \brief Type definitions for the Trace Port Interface (TPI)
<> 149:156823d33999 988 @{
<> 149:156823d33999 989 */
<> 149:156823d33999 990
AnnaBridge 167:e84263d55307 991 /**
AnnaBridge 167:e84263d55307 992 \brief Structure type to access the Trace Port Interface Register (TPI).
<> 149:156823d33999 993 */
<> 149:156823d33999 994 typedef struct
<> 149:156823d33999 995 {
AnnaBridge 167:e84263d55307 996 __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
AnnaBridge 167:e84263d55307 997 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
AnnaBridge 167:e84263d55307 998 uint32_t RESERVED0[2U];
AnnaBridge 167:e84263d55307 999 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
AnnaBridge 167:e84263d55307 1000 uint32_t RESERVED1[55U];
AnnaBridge 167:e84263d55307 1001 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
AnnaBridge 167:e84263d55307 1002 uint32_t RESERVED2[131U];
AnnaBridge 167:e84263d55307 1003 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
AnnaBridge 167:e84263d55307 1004 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
AnnaBridge 167:e84263d55307 1005 __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
AnnaBridge 167:e84263d55307 1006 uint32_t RESERVED3[759U];
AnnaBridge 167:e84263d55307 1007 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
AnnaBridge 167:e84263d55307 1008 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
AnnaBridge 167:e84263d55307 1009 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
AnnaBridge 167:e84263d55307 1010 uint32_t RESERVED4[1U];
AnnaBridge 167:e84263d55307 1011 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
AnnaBridge 167:e84263d55307 1012 __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
AnnaBridge 167:e84263d55307 1013 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
AnnaBridge 167:e84263d55307 1014 uint32_t RESERVED5[39U];
AnnaBridge 167:e84263d55307 1015 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
AnnaBridge 167:e84263d55307 1016 __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
AnnaBridge 167:e84263d55307 1017 uint32_t RESERVED7[8U];
AnnaBridge 167:e84263d55307 1018 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
AnnaBridge 167:e84263d55307 1019 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
<> 149:156823d33999 1020 } TPI_Type;
<> 149:156823d33999 1021
<> 149:156823d33999 1022 /* TPI Asynchronous Clock Prescaler Register Definitions */
AnnaBridge 167:e84263d55307 1023 #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
<> 149:156823d33999 1024 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
<> 149:156823d33999 1025
<> 149:156823d33999 1026 /* TPI Selected Pin Protocol Register Definitions */
AnnaBridge 167:e84263d55307 1027 #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
<> 149:156823d33999 1028 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
<> 149:156823d33999 1029
<> 149:156823d33999 1030 /* TPI Formatter and Flush Status Register Definitions */
AnnaBridge 167:e84263d55307 1031 #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
<> 149:156823d33999 1032 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
<> 149:156823d33999 1033
AnnaBridge 167:e84263d55307 1034 #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
<> 149:156823d33999 1035 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
<> 149:156823d33999 1036
AnnaBridge 167:e84263d55307 1037 #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
<> 149:156823d33999 1038 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
<> 149:156823d33999 1039
AnnaBridge 167:e84263d55307 1040 #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
<> 149:156823d33999 1041 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
<> 149:156823d33999 1042
<> 149:156823d33999 1043 /* TPI Formatter and Flush Control Register Definitions */
AnnaBridge 167:e84263d55307 1044 #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
<> 149:156823d33999 1045 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
<> 149:156823d33999 1046
AnnaBridge 167:e84263d55307 1047 #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
<> 149:156823d33999 1048 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
<> 149:156823d33999 1049
<> 149:156823d33999 1050 /* TPI TRIGGER Register Definitions */
AnnaBridge 167:e84263d55307 1051 #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
<> 149:156823d33999 1052 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
<> 149:156823d33999 1053
<> 149:156823d33999 1054 /* TPI Integration ETM Data Register Definitions (FIFO0) */
AnnaBridge 167:e84263d55307 1055 #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
<> 149:156823d33999 1056 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
<> 149:156823d33999 1057
AnnaBridge 167:e84263d55307 1058 #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
<> 149:156823d33999 1059 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
<> 149:156823d33999 1060
AnnaBridge 167:e84263d55307 1061 #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
<> 149:156823d33999 1062 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
<> 149:156823d33999 1063
AnnaBridge 167:e84263d55307 1064 #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
<> 149:156823d33999 1065 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
<> 149:156823d33999 1066
AnnaBridge 167:e84263d55307 1067 #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
<> 149:156823d33999 1068 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
<> 149:156823d33999 1069
AnnaBridge 167:e84263d55307 1070 #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
<> 149:156823d33999 1071 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
<> 149:156823d33999 1072
AnnaBridge 167:e84263d55307 1073 #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
<> 149:156823d33999 1074 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
<> 149:156823d33999 1075
<> 149:156823d33999 1076 /* TPI ITATBCTR2 Register Definitions */
AnnaBridge 167:e84263d55307 1077 #define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
<> 149:156823d33999 1078 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
<> 149:156823d33999 1079
<> 149:156823d33999 1080 /* TPI Integration ITM Data Register Definitions (FIFO1) */
AnnaBridge 167:e84263d55307 1081 #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
<> 149:156823d33999 1082 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
<> 149:156823d33999 1083
AnnaBridge 167:e84263d55307 1084 #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
<> 149:156823d33999 1085 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
<> 149:156823d33999 1086
AnnaBridge 167:e84263d55307 1087 #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
<> 149:156823d33999 1088 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
<> 149:156823d33999 1089
AnnaBridge 167:e84263d55307 1090 #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
<> 149:156823d33999 1091 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
<> 149:156823d33999 1092
AnnaBridge 167:e84263d55307 1093 #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
<> 149:156823d33999 1094 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
<> 149:156823d33999 1095
AnnaBridge 167:e84263d55307 1096 #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
<> 149:156823d33999 1097 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
<> 149:156823d33999 1098
AnnaBridge 167:e84263d55307 1099 #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
<> 149:156823d33999 1100 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
<> 149:156823d33999 1101
<> 149:156823d33999 1102 /* TPI ITATBCTR0 Register Definitions */
AnnaBridge 167:e84263d55307 1103 #define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
<> 149:156823d33999 1104 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
<> 149:156823d33999 1105
<> 149:156823d33999 1106 /* TPI Integration Mode Control Register Definitions */
AnnaBridge 167:e84263d55307 1107 #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
<> 149:156823d33999 1108 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
<> 149:156823d33999 1109
<> 149:156823d33999 1110 /* TPI DEVID Register Definitions */
AnnaBridge 167:e84263d55307 1111 #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
<> 149:156823d33999 1112 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
<> 149:156823d33999 1113
AnnaBridge 167:e84263d55307 1114 #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
<> 149:156823d33999 1115 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
<> 149:156823d33999 1116
AnnaBridge 167:e84263d55307 1117 #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
<> 149:156823d33999 1118 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
<> 149:156823d33999 1119
AnnaBridge 167:e84263d55307 1120 #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
<> 149:156823d33999 1121 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
<> 149:156823d33999 1122
AnnaBridge 167:e84263d55307 1123 #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
<> 149:156823d33999 1124 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
<> 149:156823d33999 1125
AnnaBridge 167:e84263d55307 1126 #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
<> 149:156823d33999 1127 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
<> 149:156823d33999 1128
<> 149:156823d33999 1129 /* TPI DEVTYPE Register Definitions */
AnnaBridge 167:e84263d55307 1130 #define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
<> 149:156823d33999 1131 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
<> 149:156823d33999 1132
AnnaBridge 167:e84263d55307 1133 #define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
<> 149:156823d33999 1134 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
<> 149:156823d33999 1135
<> 149:156823d33999 1136 /*@}*/ /* end of group CMSIS_TPI */
<> 149:156823d33999 1137
<> 149:156823d33999 1138
AnnaBridge 167:e84263d55307 1139 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge 167:e84263d55307 1140 /**
AnnaBridge 167:e84263d55307 1141 \ingroup CMSIS_core_register
AnnaBridge 167:e84263d55307 1142 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
AnnaBridge 167:e84263d55307 1143 \brief Type definitions for the Memory Protection Unit (MPU)
<> 149:156823d33999 1144 @{
<> 149:156823d33999 1145 */
<> 149:156823d33999 1146
AnnaBridge 167:e84263d55307 1147 /**
AnnaBridge 167:e84263d55307 1148 \brief Structure type to access the Memory Protection Unit (MPU).
<> 149:156823d33999 1149 */
<> 149:156823d33999 1150 typedef struct
<> 149:156823d33999 1151 {
AnnaBridge 167:e84263d55307 1152 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
AnnaBridge 167:e84263d55307 1153 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
AnnaBridge 167:e84263d55307 1154 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
AnnaBridge 167:e84263d55307 1155 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
AnnaBridge 167:e84263d55307 1156 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
AnnaBridge 167:e84263d55307 1157 __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
AnnaBridge 167:e84263d55307 1158 __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
AnnaBridge 167:e84263d55307 1159 __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
AnnaBridge 167:e84263d55307 1160 __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
AnnaBridge 167:e84263d55307 1161 __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
AnnaBridge 167:e84263d55307 1162 __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
<> 149:156823d33999 1163 } MPU_Type;
<> 149:156823d33999 1164
AnnaBridge 167:e84263d55307 1165 /* MPU Type Register Definitions */
AnnaBridge 167:e84263d55307 1166 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
<> 149:156823d33999 1167 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
<> 149:156823d33999 1168
AnnaBridge 167:e84263d55307 1169 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
<> 149:156823d33999 1170 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
<> 149:156823d33999 1171
AnnaBridge 167:e84263d55307 1172 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
<> 149:156823d33999 1173 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
<> 149:156823d33999 1174
AnnaBridge 167:e84263d55307 1175 /* MPU Control Register Definitions */
AnnaBridge 167:e84263d55307 1176 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
<> 149:156823d33999 1177 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
<> 149:156823d33999 1178
AnnaBridge 167:e84263d55307 1179 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
<> 149:156823d33999 1180 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
<> 149:156823d33999 1181
AnnaBridge 167:e84263d55307 1182 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
<> 149:156823d33999 1183 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
<> 149:156823d33999 1184
AnnaBridge 167:e84263d55307 1185 /* MPU Region Number Register Definitions */
AnnaBridge 167:e84263d55307 1186 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
<> 149:156823d33999 1187 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
<> 149:156823d33999 1188
AnnaBridge 167:e84263d55307 1189 /* MPU Region Base Address Register Definitions */
AnnaBridge 167:e84263d55307 1190 #define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
<> 149:156823d33999 1191 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
<> 149:156823d33999 1192
AnnaBridge 167:e84263d55307 1193 #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
<> 149:156823d33999 1194 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
<> 149:156823d33999 1195
AnnaBridge 167:e84263d55307 1196 #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
<> 149:156823d33999 1197 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
<> 149:156823d33999 1198
AnnaBridge 167:e84263d55307 1199 /* MPU Region Attribute and Size Register Definitions */
AnnaBridge 167:e84263d55307 1200 #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
<> 149:156823d33999 1201 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
<> 149:156823d33999 1202
AnnaBridge 167:e84263d55307 1203 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
<> 149:156823d33999 1204 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
<> 149:156823d33999 1205
AnnaBridge 167:e84263d55307 1206 #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
<> 149:156823d33999 1207 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
<> 149:156823d33999 1208
AnnaBridge 167:e84263d55307 1209 #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
<> 149:156823d33999 1210 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
<> 149:156823d33999 1211
AnnaBridge 167:e84263d55307 1212 #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
<> 149:156823d33999 1213 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
<> 149:156823d33999 1214
AnnaBridge 167:e84263d55307 1215 #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
<> 149:156823d33999 1216 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
<> 149:156823d33999 1217
AnnaBridge 167:e84263d55307 1218 #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
<> 149:156823d33999 1219 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
<> 149:156823d33999 1220
AnnaBridge 167:e84263d55307 1221 #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
<> 149:156823d33999 1222 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
<> 149:156823d33999 1223
AnnaBridge 167:e84263d55307 1224 #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
<> 149:156823d33999 1225 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
<> 149:156823d33999 1226
AnnaBridge 167:e84263d55307 1227 #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
<> 149:156823d33999 1228 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
<> 149:156823d33999 1229
<> 149:156823d33999 1230 /*@} end of group CMSIS_MPU */
<> 149:156823d33999 1231 #endif
<> 149:156823d33999 1232
<> 149:156823d33999 1233
AnnaBridge 167:e84263d55307 1234 /**
AnnaBridge 167:e84263d55307 1235 \ingroup CMSIS_core_register
AnnaBridge 167:e84263d55307 1236 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
AnnaBridge 167:e84263d55307 1237 \brief Type definitions for the Core Debug Registers
<> 149:156823d33999 1238 @{
<> 149:156823d33999 1239 */
<> 149:156823d33999 1240
AnnaBridge 167:e84263d55307 1241 /**
AnnaBridge 167:e84263d55307 1242 \brief Structure type to access the Core Debug Register (CoreDebug).
<> 149:156823d33999 1243 */
<> 149:156823d33999 1244 typedef struct
<> 149:156823d33999 1245 {
AnnaBridge 167:e84263d55307 1246 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
AnnaBridge 167:e84263d55307 1247 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
AnnaBridge 167:e84263d55307 1248 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
AnnaBridge 167:e84263d55307 1249 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
<> 149:156823d33999 1250 } CoreDebug_Type;
<> 149:156823d33999 1251
AnnaBridge 167:e84263d55307 1252 /* Debug Halting Control and Status Register Definitions */
AnnaBridge 167:e84263d55307 1253 #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
<> 149:156823d33999 1254 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
<> 149:156823d33999 1255
AnnaBridge 167:e84263d55307 1256 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
<> 149:156823d33999 1257 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
<> 149:156823d33999 1258
AnnaBridge 167:e84263d55307 1259 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
<> 149:156823d33999 1260 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
<> 149:156823d33999 1261
AnnaBridge 167:e84263d55307 1262 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
<> 149:156823d33999 1263 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
<> 149:156823d33999 1264
AnnaBridge 167:e84263d55307 1265 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
<> 149:156823d33999 1266 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
<> 149:156823d33999 1267
AnnaBridge 167:e84263d55307 1268 #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
<> 149:156823d33999 1269 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
<> 149:156823d33999 1270
AnnaBridge 167:e84263d55307 1271 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
<> 149:156823d33999 1272 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
<> 149:156823d33999 1273
AnnaBridge 167:e84263d55307 1274 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
<> 149:156823d33999 1275 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
<> 149:156823d33999 1276
AnnaBridge 167:e84263d55307 1277 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
<> 149:156823d33999 1278 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
<> 149:156823d33999 1279
AnnaBridge 167:e84263d55307 1280 #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
<> 149:156823d33999 1281 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
<> 149:156823d33999 1282
AnnaBridge 167:e84263d55307 1283 #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
<> 149:156823d33999 1284 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
<> 149:156823d33999 1285
AnnaBridge 167:e84263d55307 1286 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
<> 149:156823d33999 1287 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
<> 149:156823d33999 1288
AnnaBridge 167:e84263d55307 1289 /* Debug Core Register Selector Register Definitions */
AnnaBridge 167:e84263d55307 1290 #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
<> 149:156823d33999 1291 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
<> 149:156823d33999 1292
AnnaBridge 167:e84263d55307 1293 #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
<> 149:156823d33999 1294 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
<> 149:156823d33999 1295
AnnaBridge 167:e84263d55307 1296 /* Debug Exception and Monitor Control Register Definitions */
AnnaBridge 167:e84263d55307 1297 #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
<> 149:156823d33999 1298 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
<> 149:156823d33999 1299
AnnaBridge 167:e84263d55307 1300 #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
<> 149:156823d33999 1301 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
<> 149:156823d33999 1302
AnnaBridge 167:e84263d55307 1303 #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
<> 149:156823d33999 1304 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
<> 149:156823d33999 1305
AnnaBridge 167:e84263d55307 1306 #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
<> 149:156823d33999 1307 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
<> 149:156823d33999 1308
AnnaBridge 167:e84263d55307 1309 #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
<> 149:156823d33999 1310 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
<> 149:156823d33999 1311
AnnaBridge 167:e84263d55307 1312 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
<> 149:156823d33999 1313 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
<> 149:156823d33999 1314
AnnaBridge 167:e84263d55307 1315 #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
<> 149:156823d33999 1316 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
<> 149:156823d33999 1317
AnnaBridge 167:e84263d55307 1318 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
<> 149:156823d33999 1319 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
<> 149:156823d33999 1320
AnnaBridge 167:e84263d55307 1321 #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
<> 149:156823d33999 1322 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
<> 149:156823d33999 1323
AnnaBridge 167:e84263d55307 1324 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
<> 149:156823d33999 1325 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
<> 149:156823d33999 1326
AnnaBridge 167:e84263d55307 1327 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
<> 149:156823d33999 1328 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
<> 149:156823d33999 1329
AnnaBridge 167:e84263d55307 1330 #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
<> 149:156823d33999 1331 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
<> 149:156823d33999 1332
AnnaBridge 167:e84263d55307 1333 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
<> 149:156823d33999 1334 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
<> 149:156823d33999 1335
<> 149:156823d33999 1336 /*@} end of group CMSIS_CoreDebug */
<> 149:156823d33999 1337
<> 149:156823d33999 1338
AnnaBridge 167:e84263d55307 1339 /**
AnnaBridge 167:e84263d55307 1340 \ingroup CMSIS_core_register
AnnaBridge 167:e84263d55307 1341 \defgroup CMSIS_core_bitfield Core register bit field macros
AnnaBridge 167:e84263d55307 1342 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
<> 149:156823d33999 1343 @{
<> 149:156823d33999 1344 */
<> 149:156823d33999 1345
AnnaBridge 167:e84263d55307 1346 /**
AnnaBridge 167:e84263d55307 1347 \brief Mask and shift a bit field value for use in a register bit range.
AnnaBridge 167:e84263d55307 1348 \param[in] field Name of the register bit field.
AnnaBridge 167:e84263d55307 1349 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
AnnaBridge 167:e84263d55307 1350 \return Masked and shifted value.
AnnaBridge 167:e84263d55307 1351 */
AnnaBridge 167:e84263d55307 1352 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
AnnaBridge 167:e84263d55307 1353
AnnaBridge 167:e84263d55307 1354 /**
AnnaBridge 167:e84263d55307 1355 \brief Mask and shift a register value to extract a bit filed value.
AnnaBridge 167:e84263d55307 1356 \param[in] field Name of the register bit field.
AnnaBridge 167:e84263d55307 1357 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
AnnaBridge 167:e84263d55307 1358 \return Masked and shifted bit field value.
AnnaBridge 167:e84263d55307 1359 */
AnnaBridge 167:e84263d55307 1360 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
AnnaBridge 167:e84263d55307 1361
AnnaBridge 167:e84263d55307 1362 /*@} end of group CMSIS_core_bitfield */
AnnaBridge 167:e84263d55307 1363
AnnaBridge 167:e84263d55307 1364
AnnaBridge 167:e84263d55307 1365 /**
AnnaBridge 167:e84263d55307 1366 \ingroup CMSIS_core_register
AnnaBridge 167:e84263d55307 1367 \defgroup CMSIS_core_base Core Definitions
AnnaBridge 167:e84263d55307 1368 \brief Definitions for base addresses, unions, and structures.
AnnaBridge 167:e84263d55307 1369 @{
AnnaBridge 167:e84263d55307 1370 */
AnnaBridge 167:e84263d55307 1371
AnnaBridge 167:e84263d55307 1372 /* Memory mapping of Core Hardware */
AnnaBridge 167:e84263d55307 1373 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
AnnaBridge 167:e84263d55307 1374 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
AnnaBridge 167:e84263d55307 1375 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
AnnaBridge 167:e84263d55307 1376 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
AnnaBridge 167:e84263d55307 1377 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
AnnaBridge 167:e84263d55307 1378 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
AnnaBridge 167:e84263d55307 1379 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
AnnaBridge 167:e84263d55307 1380 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
<> 149:156823d33999 1381
<> 149:156823d33999 1382 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
AnnaBridge 167:e84263d55307 1383 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
AnnaBridge 167:e84263d55307 1384 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
AnnaBridge 167:e84263d55307 1385 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
AnnaBridge 167:e84263d55307 1386 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
AnnaBridge 167:e84263d55307 1387 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
AnnaBridge 167:e84263d55307 1388 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
AnnaBridge 167:e84263d55307 1389 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
<> 149:156823d33999 1390
AnnaBridge 167:e84263d55307 1391 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge 167:e84263d55307 1392 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
AnnaBridge 167:e84263d55307 1393 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
<> 149:156823d33999 1394 #endif
<> 149:156823d33999 1395
<> 149:156823d33999 1396 /*@} */
<> 149:156823d33999 1397
<> 149:156823d33999 1398
<> 149:156823d33999 1399
<> 149:156823d33999 1400 /*******************************************************************************
<> 149:156823d33999 1401 * Hardware Abstraction Layer
<> 149:156823d33999 1402 Core Function Interface contains:
<> 149:156823d33999 1403 - Core NVIC Functions
<> 149:156823d33999 1404 - Core SysTick Functions
<> 149:156823d33999 1405 - Core Debug Functions
<> 149:156823d33999 1406 - Core Register Access Functions
<> 149:156823d33999 1407 ******************************************************************************/
AnnaBridge 167:e84263d55307 1408 /**
AnnaBridge 167:e84263d55307 1409 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
<> 149:156823d33999 1410 */
<> 149:156823d33999 1411
<> 149:156823d33999 1412
<> 149:156823d33999 1413
<> 149:156823d33999 1414 /* ########################## NVIC functions #################################### */
AnnaBridge 167:e84263d55307 1415 /**
AnnaBridge 167:e84263d55307 1416 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 167:e84263d55307 1417 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
AnnaBridge 167:e84263d55307 1418 \brief Functions that manage interrupts and exceptions via the NVIC.
AnnaBridge 167:e84263d55307 1419 @{
<> 149:156823d33999 1420 */
<> 149:156823d33999 1421
<> 149:156823d33999 1422 #ifdef CMSIS_NVIC_VIRTUAL
<> 149:156823d33999 1423 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
<> 149:156823d33999 1424 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
<> 149:156823d33999 1425 #endif
<> 149:156823d33999 1426 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
<> 149:156823d33999 1427 #else
<> 149:156823d33999 1428 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
<> 149:156823d33999 1429 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
<> 149:156823d33999 1430 #define NVIC_EnableIRQ __NVIC_EnableIRQ
AnnaBridge 167:e84263d55307 1431 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
<> 149:156823d33999 1432 #define NVIC_DisableIRQ __NVIC_DisableIRQ
<> 149:156823d33999 1433 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
<> 149:156823d33999 1434 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
<> 149:156823d33999 1435 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
<> 149:156823d33999 1436 #define NVIC_GetActive __NVIC_GetActive
<> 149:156823d33999 1437 #define NVIC_SetPriority __NVIC_SetPriority
<> 149:156823d33999 1438 #define NVIC_GetPriority __NVIC_GetPriority
<> 149:156823d33999 1439 #define NVIC_SystemReset __NVIC_SystemReset
<> 149:156823d33999 1440 #endif /* CMSIS_NVIC_VIRTUAL */
<> 149:156823d33999 1441
<> 149:156823d33999 1442 #ifdef CMSIS_VECTAB_VIRTUAL
<> 149:156823d33999 1443 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
<> 149:156823d33999 1444 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
<> 149:156823d33999 1445 #endif
<> 149:156823d33999 1446 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
<> 149:156823d33999 1447 #else
<> 149:156823d33999 1448 #define NVIC_SetVector __NVIC_SetVector
<> 149:156823d33999 1449 #define NVIC_GetVector __NVIC_GetVector
AnnaBridge 167:e84263d55307 1450 #endif /* (CMSIS_VECTAB_VIRTUAL) */
<> 149:156823d33999 1451
AnnaBridge 167:e84263d55307 1452 #define NVIC_USER_IRQ_OFFSET 16
AnnaBridge 167:e84263d55307 1453
AnnaBridge 167:e84263d55307 1454
<> 149:156823d33999 1455
AnnaBridge 167:e84263d55307 1456 /**
AnnaBridge 167:e84263d55307 1457 \brief Set Priority Grouping
AnnaBridge 167:e84263d55307 1458 \details Sets the priority grouping field using the required unlock sequence.
AnnaBridge 167:e84263d55307 1459 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
AnnaBridge 167:e84263d55307 1460 Only values from 0..7 are used.
AnnaBridge 167:e84263d55307 1461 In case of a conflict between priority grouping and available
AnnaBridge 167:e84263d55307 1462 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
AnnaBridge 167:e84263d55307 1463 \param [in] PriorityGroup Priority grouping field.
<> 149:156823d33999 1464 */
<> 149:156823d33999 1465 __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
<> 149:156823d33999 1466 {
<> 149:156823d33999 1467 uint32_t reg_value;
<> 149:156823d33999 1468 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
<> 149:156823d33999 1469
<> 149:156823d33999 1470 reg_value = SCB->AIRCR; /* read old register configuration */
AnnaBridge 167:e84263d55307 1471 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
<> 149:156823d33999 1472 reg_value = (reg_value |
<> 149:156823d33999 1473 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
AnnaBridge 167:e84263d55307 1474 (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
<> 149:156823d33999 1475 SCB->AIRCR = reg_value;
<> 149:156823d33999 1476 }
<> 149:156823d33999 1477
<> 149:156823d33999 1478
AnnaBridge 167:e84263d55307 1479 /**
AnnaBridge 167:e84263d55307 1480 \brief Get Priority Grouping
AnnaBridge 167:e84263d55307 1481 \details Reads the priority grouping field from the NVIC Interrupt Controller.
AnnaBridge 167:e84263d55307 1482 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
<> 149:156823d33999 1483 */
<> 149:156823d33999 1484 __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
<> 149:156823d33999 1485 {
<> 149:156823d33999 1486 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
<> 149:156823d33999 1487 }
<> 149:156823d33999 1488
<> 149:156823d33999 1489
AnnaBridge 167:e84263d55307 1490 /**
AnnaBridge 167:e84263d55307 1491 \brief Enable Interrupt
AnnaBridge 167:e84263d55307 1492 \details Enables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge 167:e84263d55307 1493 \param [in] IRQn Device specific interrupt number.
AnnaBridge 167:e84263d55307 1494 \note IRQn must not be negative.
<> 149:156823d33999 1495 */
<> 149:156823d33999 1496 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
<> 149:156823d33999 1497 {
AnnaBridge 167:e84263d55307 1498 if ((int32_t)(IRQn) >= 0)
AnnaBridge 167:e84263d55307 1499 {
AnnaBridge 167:e84263d55307 1500 NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 167:e84263d55307 1501 }
<> 149:156823d33999 1502 }
<> 149:156823d33999 1503
<> 149:156823d33999 1504
AnnaBridge 167:e84263d55307 1505 /**
AnnaBridge 167:e84263d55307 1506 \brief Get Interrupt Enable status
AnnaBridge 167:e84263d55307 1507 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
AnnaBridge 167:e84263d55307 1508 \param [in] IRQn Device specific interrupt number.
AnnaBridge 167:e84263d55307 1509 \return 0 Interrupt is not enabled.
AnnaBridge 167:e84263d55307 1510 \return 1 Interrupt is enabled.
AnnaBridge 167:e84263d55307 1511 \note IRQn must not be negative.
<> 149:156823d33999 1512 */
AnnaBridge 167:e84263d55307 1513 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
<> 149:156823d33999 1514 {
AnnaBridge 167:e84263d55307 1515 if ((int32_t)(IRQn) >= 0)
AnnaBridge 167:e84263d55307 1516 {
AnnaBridge 167:e84263d55307 1517 return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 167:e84263d55307 1518 }
AnnaBridge 167:e84263d55307 1519 else
AnnaBridge 167:e84263d55307 1520 {
AnnaBridge 167:e84263d55307 1521 return(0U);
AnnaBridge 167:e84263d55307 1522 }
<> 149:156823d33999 1523 }
<> 149:156823d33999 1524
<> 149:156823d33999 1525
AnnaBridge 167:e84263d55307 1526 /**
AnnaBridge 167:e84263d55307 1527 \brief Disable Interrupt
AnnaBridge 167:e84263d55307 1528 \details Disables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge 167:e84263d55307 1529 \param [in] IRQn Device specific interrupt number.
AnnaBridge 167:e84263d55307 1530 \note IRQn must not be negative.
<> 149:156823d33999 1531 */
AnnaBridge 167:e84263d55307 1532 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
<> 149:156823d33999 1533 {
AnnaBridge 167:e84263d55307 1534 if ((int32_t)(IRQn) >= 0)
AnnaBridge 167:e84263d55307 1535 {
AnnaBridge 167:e84263d55307 1536 NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 167:e84263d55307 1537 __DSB();
AnnaBridge 167:e84263d55307 1538 __ISB();
AnnaBridge 167:e84263d55307 1539 }
<> 149:156823d33999 1540 }
<> 149:156823d33999 1541
<> 149:156823d33999 1542
AnnaBridge 167:e84263d55307 1543 /**
AnnaBridge 167:e84263d55307 1544 \brief Get Pending Interrupt
AnnaBridge 167:e84263d55307 1545 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
AnnaBridge 167:e84263d55307 1546 \param [in] IRQn Device specific interrupt number.
AnnaBridge 167:e84263d55307 1547 \return 0 Interrupt status is not pending.
AnnaBridge 167:e84263d55307 1548 \return 1 Interrupt status is pending.
AnnaBridge 167:e84263d55307 1549 \note IRQn must not be negative.
<> 149:156823d33999 1550 */
AnnaBridge 167:e84263d55307 1551 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
<> 149:156823d33999 1552 {
AnnaBridge 167:e84263d55307 1553 if ((int32_t)(IRQn) >= 0)
AnnaBridge 167:e84263d55307 1554 {
AnnaBridge 167:e84263d55307 1555 return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 167:e84263d55307 1556 }
AnnaBridge 167:e84263d55307 1557 else
AnnaBridge 167:e84263d55307 1558 {
AnnaBridge 167:e84263d55307 1559 return(0U);
AnnaBridge 167:e84263d55307 1560 }
<> 149:156823d33999 1561 }
<> 149:156823d33999 1562
<> 149:156823d33999 1563
AnnaBridge 167:e84263d55307 1564 /**
AnnaBridge 167:e84263d55307 1565 \brief Set Pending Interrupt
AnnaBridge 167:e84263d55307 1566 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge 167:e84263d55307 1567 \param [in] IRQn Device specific interrupt number.
AnnaBridge 167:e84263d55307 1568 \note IRQn must not be negative.
<> 149:156823d33999 1569 */
AnnaBridge 167:e84263d55307 1570 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
<> 149:156823d33999 1571 {
AnnaBridge 167:e84263d55307 1572 if ((int32_t)(IRQn) >= 0)
AnnaBridge 167:e84263d55307 1573 {
AnnaBridge 167:e84263d55307 1574 NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 149:156823d33999 1575 }
<> 149:156823d33999 1576 }
<> 149:156823d33999 1577
<> 149:156823d33999 1578
AnnaBridge 167:e84263d55307 1579 /**
AnnaBridge 167:e84263d55307 1580 \brief Clear Pending Interrupt
AnnaBridge 167:e84263d55307 1581 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge 167:e84263d55307 1582 \param [in] IRQn Device specific interrupt number.
AnnaBridge 167:e84263d55307 1583 \note IRQn must not be negative.
AnnaBridge 167:e84263d55307 1584 */
AnnaBridge 167:e84263d55307 1585 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
AnnaBridge 167:e84263d55307 1586 {
AnnaBridge 167:e84263d55307 1587 if ((int32_t)(IRQn) >= 0)
AnnaBridge 167:e84263d55307 1588 {
AnnaBridge 167:e84263d55307 1589 NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 167:e84263d55307 1590 }
AnnaBridge 167:e84263d55307 1591 }
<> 149:156823d33999 1592
<> 149:156823d33999 1593
AnnaBridge 167:e84263d55307 1594 /**
AnnaBridge 167:e84263d55307 1595 \brief Get Active Interrupt
AnnaBridge 167:e84263d55307 1596 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
AnnaBridge 167:e84263d55307 1597 \param [in] IRQn Device specific interrupt number.
AnnaBridge 167:e84263d55307 1598 \return 0 Interrupt status is not active.
AnnaBridge 167:e84263d55307 1599 \return 1 Interrupt status is active.
AnnaBridge 167:e84263d55307 1600 \note IRQn must not be negative.
AnnaBridge 167:e84263d55307 1601 */
AnnaBridge 167:e84263d55307 1602 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
AnnaBridge 167:e84263d55307 1603 {
AnnaBridge 167:e84263d55307 1604 if ((int32_t)(IRQn) >= 0)
AnnaBridge 167:e84263d55307 1605 {
AnnaBridge 167:e84263d55307 1606 return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 167:e84263d55307 1607 }
AnnaBridge 167:e84263d55307 1608 else
AnnaBridge 167:e84263d55307 1609 {
AnnaBridge 167:e84263d55307 1610 return(0U);
AnnaBridge 167:e84263d55307 1611 }
AnnaBridge 167:e84263d55307 1612 }
AnnaBridge 167:e84263d55307 1613
AnnaBridge 167:e84263d55307 1614
AnnaBridge 167:e84263d55307 1615 /**
AnnaBridge 167:e84263d55307 1616 \brief Set Interrupt Priority
AnnaBridge 167:e84263d55307 1617 \details Sets the priority of a device specific interrupt or a processor exception.
AnnaBridge 167:e84263d55307 1618 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 167:e84263d55307 1619 or negative to specify a processor exception.
AnnaBridge 167:e84263d55307 1620 \param [in] IRQn Interrupt number.
AnnaBridge 167:e84263d55307 1621 \param [in] priority Priority to set.
AnnaBridge 167:e84263d55307 1622 \note The priority cannot be set for every processor exception.
AnnaBridge 167:e84263d55307 1623 */
AnnaBridge 167:e84263d55307 1624 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
AnnaBridge 167:e84263d55307 1625 {
AnnaBridge 167:e84263d55307 1626 if ((int32_t)(IRQn) >= 0)
AnnaBridge 167:e84263d55307 1627 {
AnnaBridge 167:e84263d55307 1628 NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
AnnaBridge 167:e84263d55307 1629 }
AnnaBridge 167:e84263d55307 1630 else
AnnaBridge 167:e84263d55307 1631 {
AnnaBridge 167:e84263d55307 1632 SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
AnnaBridge 167:e84263d55307 1633 }
AnnaBridge 167:e84263d55307 1634 }
AnnaBridge 167:e84263d55307 1635
AnnaBridge 167:e84263d55307 1636
AnnaBridge 167:e84263d55307 1637 /**
AnnaBridge 167:e84263d55307 1638 \brief Get Interrupt Priority
AnnaBridge 167:e84263d55307 1639 \details Reads the priority of a device specific interrupt or a processor exception.
AnnaBridge 167:e84263d55307 1640 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 167:e84263d55307 1641 or negative to specify a processor exception.
AnnaBridge 167:e84263d55307 1642 \param [in] IRQn Interrupt number.
AnnaBridge 167:e84263d55307 1643 \return Interrupt Priority.
AnnaBridge 167:e84263d55307 1644 Value is aligned automatically to the implemented priority bits of the microcontroller.
<> 149:156823d33999 1645 */
<> 149:156823d33999 1646 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
<> 149:156823d33999 1647 {
<> 149:156823d33999 1648
AnnaBridge 167:e84263d55307 1649 if ((int32_t)(IRQn) >= 0)
AnnaBridge 167:e84263d55307 1650 {
AnnaBridge 167:e84263d55307 1651 return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
<> 149:156823d33999 1652 }
AnnaBridge 167:e84263d55307 1653 else
AnnaBridge 167:e84263d55307 1654 {
AnnaBridge 167:e84263d55307 1655 return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
<> 149:156823d33999 1656 }
<> 149:156823d33999 1657 }
<> 149:156823d33999 1658
<> 149:156823d33999 1659
AnnaBridge 167:e84263d55307 1660 /**
AnnaBridge 167:e84263d55307 1661 \brief Encode Priority
AnnaBridge 167:e84263d55307 1662 \details Encodes the priority for an interrupt with the given priority group,
AnnaBridge 167:e84263d55307 1663 preemptive priority value, and subpriority value.
AnnaBridge 167:e84263d55307 1664 In case of a conflict between priority grouping and available
AnnaBridge 167:e84263d55307 1665 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
AnnaBridge 167:e84263d55307 1666 \param [in] PriorityGroup Used priority group.
AnnaBridge 167:e84263d55307 1667 \param [in] PreemptPriority Preemptive priority value (starting from 0).
AnnaBridge 167:e84263d55307 1668 \param [in] SubPriority Subpriority value (starting from 0).
AnnaBridge 167:e84263d55307 1669 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
<> 149:156823d33999 1670 */
<> 149:156823d33999 1671 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
<> 149:156823d33999 1672 {
<> 149:156823d33999 1673 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
<> 149:156823d33999 1674 uint32_t PreemptPriorityBits;
<> 149:156823d33999 1675 uint32_t SubPriorityBits;
<> 149:156823d33999 1676
<> 149:156823d33999 1677 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
<> 149:156823d33999 1678 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
<> 149:156823d33999 1679
<> 149:156823d33999 1680 return (
<> 149:156823d33999 1681 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
<> 149:156823d33999 1682 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
<> 149:156823d33999 1683 );
<> 149:156823d33999 1684 }
<> 149:156823d33999 1685
<> 149:156823d33999 1686
AnnaBridge 167:e84263d55307 1687 /**
AnnaBridge 167:e84263d55307 1688 \brief Decode Priority
AnnaBridge 167:e84263d55307 1689 \details Decodes an interrupt priority value with a given priority group to
AnnaBridge 167:e84263d55307 1690 preemptive priority value and subpriority value.
AnnaBridge 167:e84263d55307 1691 In case of a conflict between priority grouping and available
AnnaBridge 167:e84263d55307 1692 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
AnnaBridge 167:e84263d55307 1693 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
AnnaBridge 167:e84263d55307 1694 \param [in] PriorityGroup Used priority group.
AnnaBridge 167:e84263d55307 1695 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
AnnaBridge 167:e84263d55307 1696 \param [out] pSubPriority Subpriority value (starting from 0).
<> 149:156823d33999 1697 */
AnnaBridge 167:e84263d55307 1698 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
<> 149:156823d33999 1699 {
<> 149:156823d33999 1700 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
<> 149:156823d33999 1701 uint32_t PreemptPriorityBits;
<> 149:156823d33999 1702 uint32_t SubPriorityBits;
<> 149:156823d33999 1703
<> 149:156823d33999 1704 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
<> 149:156823d33999 1705 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
<> 149:156823d33999 1706
<> 149:156823d33999 1707 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
<> 149:156823d33999 1708 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
<> 149:156823d33999 1709 }
<> 149:156823d33999 1710
<> 149:156823d33999 1711
AnnaBridge 167:e84263d55307 1712 /**
AnnaBridge 167:e84263d55307 1713 \brief Set Interrupt Vector
AnnaBridge 167:e84263d55307 1714 \details Sets an interrupt vector in SRAM based interrupt vector table.
AnnaBridge 167:e84263d55307 1715 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 167:e84263d55307 1716 or negative to specify a processor exception.
AnnaBridge 167:e84263d55307 1717 VTOR must been relocated to SRAM before.
AnnaBridge 167:e84263d55307 1718 \param [in] IRQn Interrupt number
AnnaBridge 167:e84263d55307 1719 \param [in] vector Address of interrupt handler function
AnnaBridge 167:e84263d55307 1720 */
AnnaBridge 167:e84263d55307 1721 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
AnnaBridge 167:e84263d55307 1722 {
AnnaBridge 167:e84263d55307 1723 uint32_t *vectors = (uint32_t *)SCB->VTOR;
AnnaBridge 167:e84263d55307 1724 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
AnnaBridge 167:e84263d55307 1725 }
AnnaBridge 167:e84263d55307 1726
<> 149:156823d33999 1727
AnnaBridge 167:e84263d55307 1728 /**
AnnaBridge 167:e84263d55307 1729 \brief Get Interrupt Vector
AnnaBridge 167:e84263d55307 1730 \details Reads an interrupt vector from interrupt vector table.
AnnaBridge 167:e84263d55307 1731 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 167:e84263d55307 1732 or negative to specify a processor exception.
AnnaBridge 167:e84263d55307 1733 \param [in] IRQn Interrupt number.
AnnaBridge 167:e84263d55307 1734 \return Address of interrupt handler function
AnnaBridge 167:e84263d55307 1735 */
AnnaBridge 167:e84263d55307 1736 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
AnnaBridge 167:e84263d55307 1737 {
AnnaBridge 167:e84263d55307 1738 uint32_t *vectors = (uint32_t *)SCB->VTOR;
AnnaBridge 167:e84263d55307 1739 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
AnnaBridge 167:e84263d55307 1740 }
AnnaBridge 167:e84263d55307 1741
AnnaBridge 167:e84263d55307 1742
AnnaBridge 167:e84263d55307 1743 /**
AnnaBridge 167:e84263d55307 1744 \brief System Reset
AnnaBridge 167:e84263d55307 1745 \details Initiates a system reset request to reset the MCU.
<> 149:156823d33999 1746 */
<> 149:156823d33999 1747 __STATIC_INLINE void __NVIC_SystemReset(void)
<> 149:156823d33999 1748 {
<> 149:156823d33999 1749 __DSB(); /* Ensure all outstanding memory accesses included
<> 149:156823d33999 1750 buffered write are completed before reset */
<> 149:156823d33999 1751 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
<> 149:156823d33999 1752 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
<> 149:156823d33999 1753 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
<> 149:156823d33999 1754 __DSB(); /* Ensure completion of memory access */
AnnaBridge 167:e84263d55307 1755
AnnaBridge 167:e84263d55307 1756 for(;;) /* wait until reset */
AnnaBridge 167:e84263d55307 1757 {
AnnaBridge 167:e84263d55307 1758 __NOP();
AnnaBridge 167:e84263d55307 1759 }
<> 149:156823d33999 1760 }
<> 149:156823d33999 1761
<> 149:156823d33999 1762 /*@} end of CMSIS_Core_NVICFunctions */
<> 149:156823d33999 1763
<> 149:156823d33999 1764
AnnaBridge 167:e84263d55307 1765 /* ########################## FPU functions #################################### */
AnnaBridge 167:e84263d55307 1766 /**
AnnaBridge 167:e84263d55307 1767 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 167:e84263d55307 1768 \defgroup CMSIS_Core_FpuFunctions FPU Functions
AnnaBridge 167:e84263d55307 1769 \brief Function that provides FPU type.
<> 149:156823d33999 1770 @{
<> 149:156823d33999 1771 */
<> 149:156823d33999 1772
AnnaBridge 167:e84263d55307 1773 /**
AnnaBridge 167:e84263d55307 1774 \brief get FPU type
AnnaBridge 167:e84263d55307 1775 \details returns the FPU type
AnnaBridge 167:e84263d55307 1776 \returns
AnnaBridge 167:e84263d55307 1777 - \b 0: No FPU
AnnaBridge 167:e84263d55307 1778 - \b 1: Single precision FPU
AnnaBridge 167:e84263d55307 1779 - \b 2: Double + Single precision FPU
AnnaBridge 167:e84263d55307 1780 */
AnnaBridge 167:e84263d55307 1781 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
AnnaBridge 167:e84263d55307 1782 {
AnnaBridge 167:e84263d55307 1783 return 0U; /* No FPU */
AnnaBridge 167:e84263d55307 1784 }
<> 149:156823d33999 1785
<> 149:156823d33999 1786
AnnaBridge 167:e84263d55307 1787 /*@} end of CMSIS_Core_FpuFunctions */
AnnaBridge 167:e84263d55307 1788
AnnaBridge 167:e84263d55307 1789
<> 149:156823d33999 1790
AnnaBridge 167:e84263d55307 1791 /* ################################## SysTick function ############################################ */
AnnaBridge 167:e84263d55307 1792 /**
AnnaBridge 167:e84263d55307 1793 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 167:e84263d55307 1794 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
AnnaBridge 167:e84263d55307 1795 \brief Functions that configure the System.
AnnaBridge 167:e84263d55307 1796 @{
AnnaBridge 167:e84263d55307 1797 */
<> 149:156823d33999 1798
AnnaBridge 167:e84263d55307 1799 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
<> 149:156823d33999 1800
AnnaBridge 167:e84263d55307 1801 /**
AnnaBridge 167:e84263d55307 1802 \brief System Tick Configuration
AnnaBridge 167:e84263d55307 1803 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
AnnaBridge 167:e84263d55307 1804 Counter is in free running mode to generate periodic interrupts.
AnnaBridge 167:e84263d55307 1805 \param [in] ticks Number of ticks between two interrupts.
AnnaBridge 167:e84263d55307 1806 \return 0 Function succeeded.
AnnaBridge 167:e84263d55307 1807 \return 1 Function failed.
AnnaBridge 167:e84263d55307 1808 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
AnnaBridge 167:e84263d55307 1809 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
AnnaBridge 167:e84263d55307 1810 must contain a vendor-specific implementation of this function.
<> 149:156823d33999 1811 */
<> 149:156823d33999 1812 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
<> 149:156823d33999 1813 {
AnnaBridge 167:e84263d55307 1814 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
AnnaBridge 167:e84263d55307 1815 {
AnnaBridge 167:e84263d55307 1816 return (1UL); /* Reload value impossible */
AnnaBridge 167:e84263d55307 1817 }
<> 149:156823d33999 1818
<> 149:156823d33999 1819 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
<> 149:156823d33999 1820 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
<> 149:156823d33999 1821 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
<> 149:156823d33999 1822 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
<> 149:156823d33999 1823 SysTick_CTRL_TICKINT_Msk |
<> 149:156823d33999 1824 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
<> 149:156823d33999 1825 return (0UL); /* Function successful */
<> 149:156823d33999 1826 }
<> 149:156823d33999 1827
<> 149:156823d33999 1828 #endif
<> 149:156823d33999 1829
<> 149:156823d33999 1830 /*@} end of CMSIS_Core_SysTickFunctions */
<> 149:156823d33999 1831
<> 149:156823d33999 1832
<> 149:156823d33999 1833
<> 149:156823d33999 1834 /* ##################################### Debug In/Output function ########################################### */
AnnaBridge 167:e84263d55307 1835 /**
AnnaBridge 167:e84263d55307 1836 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 167:e84263d55307 1837 \defgroup CMSIS_core_DebugFunctions ITM Functions
AnnaBridge 167:e84263d55307 1838 \brief Functions that access the ITM debug interface.
<> 149:156823d33999 1839 @{
<> 149:156823d33999 1840 */
<> 149:156823d33999 1841
AnnaBridge 167:e84263d55307 1842 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
AnnaBridge 167:e84263d55307 1843 #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
<> 149:156823d33999 1844
<> 149:156823d33999 1845
AnnaBridge 167:e84263d55307 1846 /**
AnnaBridge 167:e84263d55307 1847 \brief ITM Send Character
AnnaBridge 167:e84263d55307 1848 \details Transmits a character via the ITM channel 0, and
AnnaBridge 167:e84263d55307 1849 \li Just returns when no debugger is connected that has booked the output.
AnnaBridge 167:e84263d55307 1850 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
AnnaBridge 167:e84263d55307 1851 \param [in] ch Character to transmit.
AnnaBridge 167:e84263d55307 1852 \returns Character to transmit.
<> 149:156823d33999 1853 */
<> 149:156823d33999 1854 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
<> 149:156823d33999 1855 {
<> 149:156823d33999 1856 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
<> 149:156823d33999 1857 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
<> 149:156823d33999 1858 {
AnnaBridge 167:e84263d55307 1859 while (ITM->PORT[0U].u32 == 0UL)
AnnaBridge 167:e84263d55307 1860 {
AnnaBridge 167:e84263d55307 1861 __NOP();
AnnaBridge 167:e84263d55307 1862 }
AnnaBridge 167:e84263d55307 1863 ITM->PORT[0U].u8 = (uint8_t)ch;
<> 149:156823d33999 1864 }
<> 149:156823d33999 1865 return (ch);
<> 149:156823d33999 1866 }
<> 149:156823d33999 1867
<> 149:156823d33999 1868
AnnaBridge 167:e84263d55307 1869 /**
AnnaBridge 167:e84263d55307 1870 \brief ITM Receive Character
AnnaBridge 167:e84263d55307 1871 \details Inputs a character via the external variable \ref ITM_RxBuffer.
AnnaBridge 167:e84263d55307 1872 \return Received character.
AnnaBridge 167:e84263d55307 1873 \return -1 No character pending.
<> 149:156823d33999 1874 */
AnnaBridge 167:e84263d55307 1875 __STATIC_INLINE int32_t ITM_ReceiveChar (void)
AnnaBridge 167:e84263d55307 1876 {
<> 149:156823d33999 1877 int32_t ch = -1; /* no character available */
<> 149:156823d33999 1878
AnnaBridge 167:e84263d55307 1879 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
AnnaBridge 167:e84263d55307 1880 {
<> 149:156823d33999 1881 ch = ITM_RxBuffer;
<> 149:156823d33999 1882 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
<> 149:156823d33999 1883 }
<> 149:156823d33999 1884
<> 149:156823d33999 1885 return (ch);
<> 149:156823d33999 1886 }
<> 149:156823d33999 1887
<> 149:156823d33999 1888
AnnaBridge 167:e84263d55307 1889 /**
AnnaBridge 167:e84263d55307 1890 \brief ITM Check Character
AnnaBridge 167:e84263d55307 1891 \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
AnnaBridge 167:e84263d55307 1892 \return 0 No character available.
AnnaBridge 167:e84263d55307 1893 \return 1 Character available.
<> 149:156823d33999 1894 */
AnnaBridge 167:e84263d55307 1895 __STATIC_INLINE int32_t ITM_CheckChar (void)
AnnaBridge 167:e84263d55307 1896 {
<> 149:156823d33999 1897
AnnaBridge 167:e84263d55307 1898 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
AnnaBridge 167:e84263d55307 1899 {
AnnaBridge 167:e84263d55307 1900 return (0); /* no character available */
AnnaBridge 167:e84263d55307 1901 }
AnnaBridge 167:e84263d55307 1902 else
AnnaBridge 167:e84263d55307 1903 {
AnnaBridge 167:e84263d55307 1904 return (1); /* character available */
<> 149:156823d33999 1905 }
<> 149:156823d33999 1906 }
<> 149:156823d33999 1907
<> 149:156823d33999 1908 /*@} end of CMSIS_core_DebugFunctions */
<> 149:156823d33999 1909
<> 149:156823d33999 1910
<> 149:156823d33999 1911
<> 149:156823d33999 1912
<> 149:156823d33999 1913 #ifdef __cplusplus
<> 149:156823d33999 1914 }
<> 149:156823d33999 1915 #endif
<> 149:156823d33999 1916
<> 149:156823d33999 1917 #endif /* __CORE_CM3_H_DEPENDANT */
<> 149:156823d33999 1918
<> 149:156823d33999 1919 #endif /* __CMSIS_GENERIC */