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targets/TARGET_NXP/TARGET_LPC11U6X/spi_api.c@174:ed647f63e28d, 2017-12-19 (annotated)

Committer:
Dollyparton
Date:
Tue Dec 19 12:50:13 2017 +0000
Revision:
174:ed647f63e28d
Parent:
172:7d866c31b3c5 
Added RAW socket.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /* mbed Microcontroller Library
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2006-2013 ARM Limited
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Licensed under the Apache License, Version 2.0 (the "License");
<> 144:ef7eb2e8f9f7 5 * you may not use this file except in compliance with the License.
<> 144:ef7eb2e8f9f7 6 * You may obtain a copy of the License at
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * http://www.apache.org/licenses/LICENSE-2.0
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * Unless required by applicable law or agreed to in writing, software
<> 144:ef7eb2e8f9f7 11 * distributed under the License is distributed on an "AS IS" BASIS,
<> 144:ef7eb2e8f9f7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<> 144:ef7eb2e8f9f7 13 * See the License for the specific language governing permissions and
<> 144:ef7eb2e8f9f7 14 * limitations under the License.
<> 144:ef7eb2e8f9f7 15 */
<> 144:ef7eb2e8f9f7 16 #include "mbed_assert.h"
<> 144:ef7eb2e8f9f7 17 #include <math.h>
<> 144:ef7eb2e8f9f7 18
<> 144:ef7eb2e8f9f7 19 #include "spi_api.h"
<> 144:ef7eb2e8f9f7 20 #include "cmsis.h"
<> 144:ef7eb2e8f9f7 21 #include "pinmap.h"
<> 144:ef7eb2e8f9f7 22 #include "mbed_error.h"
<> 144:ef7eb2e8f9f7 23
<> 144:ef7eb2e8f9f7 24 #if DEVICE_SPI
<> 144:ef7eb2e8f9f7 25
<> 144:ef7eb2e8f9f7 26 static const PinMap PinMap_SPI_SCLK[] = {
<> 144:ef7eb2e8f9f7 27 {P0_6 , SPI_0, 0x02},
<> 144:ef7eb2e8f9f7 28 {P1_29, SPI_0, 0x01},
<> 144:ef7eb2e8f9f7 29 {P2_7 , SPI_0, 0x01},
<> 144:ef7eb2e8f9f7 30 {P1_20, SPI_1, 0x02},
<> 144:ef7eb2e8f9f7 31 {P1_27, SPI_1, 0x04},
<> 144:ef7eb2e8f9f7 32 {NC , NC , 0}
<> 144:ef7eb2e8f9f7 33 };
<> 144:ef7eb2e8f9f7 34
<> 144:ef7eb2e8f9f7 35 static const PinMap PinMap_SPI_MOSI[] = {
<> 144:ef7eb2e8f9f7 36 {P0_9 , SPI_0, 0x01},
<> 144:ef7eb2e8f9f7 37 {P1_12, SPI_0, 0x01},
<> 144:ef7eb2e8f9f7 38 {P0_21, SPI_1, 0x02},
<> 144:ef7eb2e8f9f7 39 {P1_22, SPI_1, 0x01},
<> 144:ef7eb2e8f9f7 40 {NC , NC , 0}
<> 144:ef7eb2e8f9f7 41 };
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 static const PinMap PinMap_SPI_MISO[] = {
<> 144:ef7eb2e8f9f7 44 {P0_8 , SPI_0, 0x01},
<> 144:ef7eb2e8f9f7 45 {P1_16, SPI_0, 0x01},
<> 144:ef7eb2e8f9f7 46 {P0_22, SPI_1, 0x03},
<> 144:ef7eb2e8f9f7 47 {P1_21, SPI_1, 0x02},
<> 144:ef7eb2e8f9f7 48 {NC , NC , 0}
<> 144:ef7eb2e8f9f7 49 };
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 static const PinMap PinMap_SPI_SSEL[] = {
<> 144:ef7eb2e8f9f7 52 {P0_2 , SPI_0, 0x01},
<> 144:ef7eb2e8f9f7 53 {P1_15, SPI_0, 0x01},
<> 144:ef7eb2e8f9f7 54 {P0_23, SPI_1, 0x04},
<> 144:ef7eb2e8f9f7 55 {P1_23, SPI_1, 0x02},
<> 144:ef7eb2e8f9f7 56 {NC , NC , 0}
<> 144:ef7eb2e8f9f7 57 };
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 static inline int ssp_disable(spi_t *obj);
<> 144:ef7eb2e8f9f7 60 static inline int ssp_enable(spi_t *obj);
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
<> 144:ef7eb2e8f9f7 63 // determine the SPI to use
<> 144:ef7eb2e8f9f7 64 SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
<> 144:ef7eb2e8f9f7 65 SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
<> 144:ef7eb2e8f9f7 66 SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
<> 144:ef7eb2e8f9f7 67 SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
<> 144:ef7eb2e8f9f7 68 SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
<> 144:ef7eb2e8f9f7 69 SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
<> 144:ef7eb2e8f9f7 70
<> 144:ef7eb2e8f9f7 71 obj->spi = (LPC_SSP0_Type*)pinmap_merge(spi_data, spi_cntl);
<> 144:ef7eb2e8f9f7 72 MBED_ASSERT((int)obj->spi != NC);
<> 144:ef7eb2e8f9f7 73
<> 144:ef7eb2e8f9f7 74 // enable power and clocking
<> 144:ef7eb2e8f9f7 75 switch ((int)obj->spi) {
<> 144:ef7eb2e8f9f7 76 case SPI_0:
<> 144:ef7eb2e8f9f7 77 LPC_SYSCON->SYSAHBCLKCTRL |= 1 << 11;
<> 144:ef7eb2e8f9f7 78 LPC_SYSCON->SSP0CLKDIV = 0x01;
<> 144:ef7eb2e8f9f7 79 LPC_SYSCON->PRESETCTRL |= 1 << 0;
<> 144:ef7eb2e8f9f7 80 break;
<> 144:ef7eb2e8f9f7 81 case SPI_1:
<> 144:ef7eb2e8f9f7 82 LPC_SYSCON->SYSAHBCLKCTRL |= 1 << 18;
<> 144:ef7eb2e8f9f7 83 LPC_SYSCON->SSP1CLKDIV = 0x01;
<> 144:ef7eb2e8f9f7 84 LPC_SYSCON->PRESETCTRL |= 1 << 2;
<> 144:ef7eb2e8f9f7 85 break;
<> 144:ef7eb2e8f9f7 86 }
<> 144:ef7eb2e8f9f7 87
<> 144:ef7eb2e8f9f7 88 // pin out the spi pins
<> 144:ef7eb2e8f9f7 89 pinmap_pinout(mosi, PinMap_SPI_MOSI);
<> 144:ef7eb2e8f9f7 90 pinmap_pinout(miso, PinMap_SPI_MISO);
<> 144:ef7eb2e8f9f7 91 pinmap_pinout(sclk, PinMap_SPI_SCLK);
<> 144:ef7eb2e8f9f7 92 if (ssel != NC) {
<> 144:ef7eb2e8f9f7 93 pinmap_pinout(ssel, PinMap_SPI_SSEL);
<> 144:ef7eb2e8f9f7 94 }
<> 144:ef7eb2e8f9f7 95 }
<> 144:ef7eb2e8f9f7 96
<> 144:ef7eb2e8f9f7 97 void spi_free(spi_t *obj) {}
<> 144:ef7eb2e8f9f7 98
<> 144:ef7eb2e8f9f7 99 void spi_format(spi_t *obj, int bits, int mode, int slave) {
<> 144:ef7eb2e8f9f7 100 ssp_disable(obj);
<> 144:ef7eb2e8f9f7 101 MBED_ASSERT(((bits >= 4) && (bits <= 16)) || ((mode >= 0) && (mode <= 3)));
<> 144:ef7eb2e8f9f7 102
<> 144:ef7eb2e8f9f7 103 int polarity = (mode & 0x2) ? 1 : 0;
<> 144:ef7eb2e8f9f7 104 int phase = (mode & 0x1) ? 1 : 0;
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 // set it up
<> 144:ef7eb2e8f9f7 107 int DSS = bits - 1; // DSS (data select size)
<> 144:ef7eb2e8f9f7 108 int SPO = (polarity) ? 1 : 0; // SPO - clock out polarity
<> 144:ef7eb2e8f9f7 109 int SPH = (phase) ? 1 : 0; // SPH - clock out phase
<> 144:ef7eb2e8f9f7 110
<> 144:ef7eb2e8f9f7 111 int FRF = 0; // FRF (frame format) = SPI
<> 144:ef7eb2e8f9f7 112 uint32_t tmp = obj->spi->CR0;
AnnaBridge 172:7d866c31b3c5 113 tmp &= ~(0x00FF); // Clear DSS, FRF, CPOL and CPHA [7:0]
<> 144:ef7eb2e8f9f7 114 tmp |= DSS << 0
<> 144:ef7eb2e8f9f7 115 | FRF << 4
<> 144:ef7eb2e8f9f7 116 | SPO << 6
<> 144:ef7eb2e8f9f7 117 | SPH << 7;
<> 144:ef7eb2e8f9f7 118 obj->spi->CR0 = tmp;
<> 144:ef7eb2e8f9f7 119
<> 144:ef7eb2e8f9f7 120 tmp = obj->spi->CR1;
<> 144:ef7eb2e8f9f7 121 tmp &= ~(0xD);
<> 144:ef7eb2e8f9f7 122 tmp |= 0 << 0 // LBM - loop back mode - off
<> 144:ef7eb2e8f9f7 123 | ((slave) ? 1 : 0) << 2 // MS - master slave mode, 1 = slave
<> 144:ef7eb2e8f9f7 124 | 0 << 3; // SOD - slave output disable - na
<> 144:ef7eb2e8f9f7 125 obj->spi->CR1 = tmp;
<> 144:ef7eb2e8f9f7 126
<> 144:ef7eb2e8f9f7 127 ssp_enable(obj);
<> 144:ef7eb2e8f9f7 128 }
<> 144:ef7eb2e8f9f7 129
<> 144:ef7eb2e8f9f7 130 void spi_frequency(spi_t *obj, int hz) {
<> 144:ef7eb2e8f9f7 131 ssp_disable(obj);
<> 144:ef7eb2e8f9f7 132
<> 144:ef7eb2e8f9f7 133 uint32_t PCLK = SystemCoreClock;
<> 144:ef7eb2e8f9f7 134
<> 144:ef7eb2e8f9f7 135 int prescaler;
<> 144:ef7eb2e8f9f7 136
<> 144:ef7eb2e8f9f7 137 for (prescaler = 2; prescaler <= 254; prescaler += 2) {
<> 144:ef7eb2e8f9f7 138 int prescale_hz = PCLK / prescaler;
<> 144:ef7eb2e8f9f7 139
<> 144:ef7eb2e8f9f7 140 // calculate the divider
<> 144:ef7eb2e8f9f7 141 int divider = floor(((float)prescale_hz / (float)hz) + 0.5f);
<> 144:ef7eb2e8f9f7 142
<> 144:ef7eb2e8f9f7 143 // check we can support the divider
<> 144:ef7eb2e8f9f7 144 if (divider < 256) {
<> 144:ef7eb2e8f9f7 145 // prescaler
<> 144:ef7eb2e8f9f7 146 obj->spi->CPSR = prescaler;
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148 // divider
AnnaBridge 172:7d866c31b3c5 149 obj->spi->CR0 &= ~(0xFF00); // Clear SCR: Serial clock rate [15:8]
<> 144:ef7eb2e8f9f7 150 obj->spi->CR0 |= (divider - 1) << 8;
<> 144:ef7eb2e8f9f7 151 ssp_enable(obj);
<> 144:ef7eb2e8f9f7 152 return;
<> 144:ef7eb2e8f9f7 153 }
<> 144:ef7eb2e8f9f7 154 }
<> 144:ef7eb2e8f9f7 155 error("Couldn't setup requested SPI frequency");
<> 144:ef7eb2e8f9f7 156 }
<> 144:ef7eb2e8f9f7 157
<> 144:ef7eb2e8f9f7 158 static inline int ssp_disable(spi_t *obj) {
<> 144:ef7eb2e8f9f7 159 return obj->spi->CR1 &= ~(1 << 1);
<> 144:ef7eb2e8f9f7 160 }
<> 144:ef7eb2e8f9f7 161
<> 144:ef7eb2e8f9f7 162 static inline int ssp_enable(spi_t *obj) {
<> 144:ef7eb2e8f9f7 163 return obj->spi->CR1 |= (1 << 1);
<> 144:ef7eb2e8f9f7 164 }
<> 144:ef7eb2e8f9f7 165
<> 144:ef7eb2e8f9f7 166 static inline int ssp_readable(spi_t *obj) {
<> 144:ef7eb2e8f9f7 167 return obj->spi->SR & (1 << 2);
<> 144:ef7eb2e8f9f7 168 }
<> 144:ef7eb2e8f9f7 169
<> 144:ef7eb2e8f9f7 170 static inline int ssp_writeable(spi_t *obj) {
<> 144:ef7eb2e8f9f7 171 return obj->spi->SR & (1 << 1);
<> 144:ef7eb2e8f9f7 172 }
<> 144:ef7eb2e8f9f7 173
<> 144:ef7eb2e8f9f7 174 static inline void ssp_write(spi_t *obj, int value) {
<> 144:ef7eb2e8f9f7 175 while (!ssp_writeable(obj));
<> 144:ef7eb2e8f9f7 176 obj->spi->DR = value;
<> 144:ef7eb2e8f9f7 177 }
<> 144:ef7eb2e8f9f7 178
<> 144:ef7eb2e8f9f7 179 static inline int ssp_read(spi_t *obj) {
<> 144:ef7eb2e8f9f7 180 while (!ssp_readable(obj));
<> 144:ef7eb2e8f9f7 181 return obj->spi->DR;
<> 144:ef7eb2e8f9f7 182 }
<> 144:ef7eb2e8f9f7 183
<> 144:ef7eb2e8f9f7 184 static inline int ssp_busy(spi_t *obj) {
<> 144:ef7eb2e8f9f7 185 return (obj->spi->SR & (1 << 4)) ? (1) : (0);
<> 144:ef7eb2e8f9f7 186 }
<> 144:ef7eb2e8f9f7 187
<> 144:ef7eb2e8f9f7 188 int spi_master_write(spi_t *obj, int value) {
<> 144:ef7eb2e8f9f7 189 ssp_write(obj, value);
<> 144:ef7eb2e8f9f7 190 return ssp_read(obj);
<> 144:ef7eb2e8f9f7 191 }
<> 144:ef7eb2e8f9f7 192
Kojto 170:19eb464bc2be 193 int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
Kojto 170:19eb464bc2be 194 char *rx_buffer, int rx_length, char write_fill) {
AnnaBridge 167:e84263d55307 195 int total = (tx_length > rx_length) ? tx_length : rx_length;
AnnaBridge 167:e84263d55307 196
AnnaBridge 167:e84263d55307 197 for (int i = 0; i < total; i++) {
Kojto 170:19eb464bc2be 198 char out = (i < tx_length) ? tx_buffer[i] : write_fill;
AnnaBridge 167:e84263d55307 199 char in = spi_master_write(obj, out);
AnnaBridge 167:e84263d55307 200 if (i < rx_length) {
AnnaBridge 167:e84263d55307 201 rx_buffer[i] = in;
AnnaBridge 167:e84263d55307 202 }
AnnaBridge 167:e84263d55307 203 }
AnnaBridge 167:e84263d55307 204
AnnaBridge 167:e84263d55307 205 return total;
AnnaBridge 167:e84263d55307 206 }
AnnaBridge 167:e84263d55307 207
<> 144:ef7eb2e8f9f7 208 int spi_slave_receive(spi_t *obj) {
<> 144:ef7eb2e8f9f7 209 return (ssp_readable(obj) && !ssp_busy(obj)) ? (1) : (0);
<> 144:ef7eb2e8f9f7 210 }
<> 144:ef7eb2e8f9f7 211
<> 144:ef7eb2e8f9f7 212 int spi_slave_read(spi_t *obj) {
<> 144:ef7eb2e8f9f7 213 return obj->spi->DR;
<> 144:ef7eb2e8f9f7 214 }
<> 144:ef7eb2e8f9f7 215
<> 144:ef7eb2e8f9f7 216 void spi_slave_write(spi_t *obj, int value) {
<> 144:ef7eb2e8f9f7 217 while (ssp_writeable(obj) == 0) ;
<> 144:ef7eb2e8f9f7 218 obj->spi->DR = value;
<> 144:ef7eb2e8f9f7 219 }
<> 144:ef7eb2e8f9f7 220
<> 144:ef7eb2e8f9f7 221 int spi_busy(spi_t *obj) {
<> 144:ef7eb2e8f9f7 222 return ssp_busy(obj);
<> 144:ef7eb2e8f9f7 223 }
<> 144:ef7eb2e8f9f7 224
<> 144:ef7eb2e8f9f7 225 #endif