mbed-dev - Forked.

Users » Dollyparton » Code » mbed-dev

Forked.

cmsis/core_cm23.h@174:ed647f63e28d, 2017-12-19 (annotated)

Committer:: Dollyparton
Date:: Tue Dec 19 12:50:13 2017 +0000
Revision:: 174:ed647f63e28d
Parent:: 167:e84263d55307

Added RAW socket.

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	167:e84263d55307	1	/************************************************************************//
AnnaBridge	167:e84263d55307	2	* @file core_cm23.h
AnnaBridge	167:e84263d55307	3	* @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File
AnnaBridge	167:e84263d55307	4	* @version V5.0.2
AnnaBridge	167:e84263d55307	5	* @date 13. February 2017
AnnaBridge	167:e84263d55307	6	******************************************************************************/
AnnaBridge	167:e84263d55307	7	/*
AnnaBridge	167:e84263d55307	8	* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
AnnaBridge	167:e84263d55307	9	*
AnnaBridge	167:e84263d55307	10	* SPDX-License-Identifier: Apache-2.0
AnnaBridge	167:e84263d55307	11	*
AnnaBridge	167:e84263d55307	12	* Licensed under the Apache License, Version 2.0 (the License); you may
AnnaBridge	167:e84263d55307	13	* not use this file except in compliance with the License.
AnnaBridge	167:e84263d55307	14	* You may obtain a copy of the License at
AnnaBridge	167:e84263d55307	15	*
AnnaBridge	167:e84263d55307	16	* www.apache.org/licenses/LICENSE-2.0
AnnaBridge	167:e84263d55307	17	*
AnnaBridge	167:e84263d55307	18	* Unless required by applicable law or agreed to in writing, software
AnnaBridge	167:e84263d55307	19	* distributed under the License is distributed on an AS IS BASIS, WITHOUT
AnnaBridge	167:e84263d55307	20	* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge	167:e84263d55307	21	* See the License for the specific language governing permissions and
AnnaBridge	167:e84263d55307	22	* limitations under the License.
AnnaBridge	167:e84263d55307	23	*/
AnnaBridge	167:e84263d55307	24
AnnaBridge	167:e84263d55307	25	#if defined ( __ICCARM__ )
AnnaBridge	167:e84263d55307	26	#pragma system_include /* treat file as system include file for MISRA check */
AnnaBridge	167:e84263d55307	27	#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge	167:e84263d55307	28	#pragma clang system_header /* treat file as system include file */
AnnaBridge	167:e84263d55307	29	#endif
AnnaBridge	167:e84263d55307	30
AnnaBridge	167:e84263d55307	31	#ifndef __CORE_CM23_H_GENERIC
AnnaBridge	167:e84263d55307	32	#define __CORE_CM23_H_GENERIC
AnnaBridge	167:e84263d55307	33
AnnaBridge	167:e84263d55307	34	#include <stdint.h>
AnnaBridge	167:e84263d55307	35
AnnaBridge	167:e84263d55307	36	#ifdef __cplusplus
AnnaBridge	167:e84263d55307	37	extern "C" {
AnnaBridge	167:e84263d55307	38	#endif
AnnaBridge	167:e84263d55307	39
AnnaBridge	167:e84263d55307	40	/**
AnnaBridge	167:e84263d55307	41	\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
AnnaBridge	167:e84263d55307	42	CMSIS violates the following MISRA-C:2004 rules:
AnnaBridge	167:e84263d55307	43
AnnaBridge	167:e84263d55307	44	\li Required Rule 8.5, object/function definition in header file.<br>
AnnaBridge	167:e84263d55307	45	Function definitions in header files are used to allow 'inlining'.
AnnaBridge	167:e84263d55307	46
AnnaBridge	167:e84263d55307	47	\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
AnnaBridge	167:e84263d55307	48	Unions are used for effective representation of core registers.
AnnaBridge	167:e84263d55307	49
AnnaBridge	167:e84263d55307	50	\li Advisory Rule 19.7, Function-like macro defined.<br>
AnnaBridge	167:e84263d55307	51	Function-like macros are used to allow more efficient code.
AnnaBridge	167:e84263d55307	52	*/
AnnaBridge	167:e84263d55307	53
AnnaBridge	167:e84263d55307	54
AnnaBridge	167:e84263d55307	55	/*******************************************************************************
AnnaBridge	167:e84263d55307	56	* CMSIS definitions
AnnaBridge	167:e84263d55307	57	******************************************************************************/
AnnaBridge	167:e84263d55307	58	/**
AnnaBridge	167:e84263d55307	59	\ingroup Cortex_M23
AnnaBridge	167:e84263d55307	60	@{
AnnaBridge	167:e84263d55307	61	*/
AnnaBridge	167:e84263d55307	62
AnnaBridge	167:e84263d55307	63	/* CMSIS cmGrebe definitions */
AnnaBridge	167:e84263d55307	64	#define __CM23_CMSIS_VERSION_MAIN ( 5U) /!< [31:16] CMSIS HAL main version /
AnnaBridge	167:e84263d55307	65	#define __CM23_CMSIS_VERSION_SUB ( 0U) /!< [15:0] CMSIS HAL sub version /
AnnaBridge	167:e84263d55307	66	#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) \| \
AnnaBridge	167:e84263d55307	67	__CM23_CMSIS_VERSION_SUB ) /!< CMSIS HAL version number /
AnnaBridge	167:e84263d55307	68
AnnaBridge	167:e84263d55307	69	#define __CORTEX_M (23U) /!< Cortex-M Core /
AnnaBridge	167:e84263d55307	70
AnnaBridge	167:e84263d55307	71	/** __FPU_USED indicates whether an FPU is used or not.
AnnaBridge	167:e84263d55307	72	This core does not support an FPU at all
AnnaBridge	167:e84263d55307	73	*/
AnnaBridge	167:e84263d55307	74	#define __FPU_USED 0U
AnnaBridge	167:e84263d55307	75
AnnaBridge	167:e84263d55307	76	#if defined ( __CC_ARM )
AnnaBridge	167:e84263d55307	77	#if defined __TARGET_FPU_VFP
AnnaBridge	167:e84263d55307	78	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	167:e84263d55307	79	#endif
AnnaBridge	167:e84263d55307	80
AnnaBridge	167:e84263d55307	81	#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge	167:e84263d55307	82	#if defined __ARM_PCS_VFP
AnnaBridge	167:e84263d55307	83	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	167:e84263d55307	84	#endif
AnnaBridge	167:e84263d55307	85
AnnaBridge	167:e84263d55307	86	#elif defined ( __GNUC__ )
AnnaBridge	167:e84263d55307	87	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
AnnaBridge	167:e84263d55307	88	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	167:e84263d55307	89	#endif
AnnaBridge	167:e84263d55307	90
AnnaBridge	167:e84263d55307	91	#elif defined ( __ICCARM__ )
AnnaBridge	167:e84263d55307	92	#if defined __ARMVFP__
AnnaBridge	167:e84263d55307	93	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	167:e84263d55307	94	#endif
AnnaBridge	167:e84263d55307	95
AnnaBridge	167:e84263d55307	96	#elif defined ( __TI_ARM__ )
AnnaBridge	167:e84263d55307	97	#if defined __TI_VFP_SUPPORT__
AnnaBridge	167:e84263d55307	98	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	167:e84263d55307	99	#endif
AnnaBridge	167:e84263d55307	100
AnnaBridge	167:e84263d55307	101	#elif defined ( __TASKING__ )
AnnaBridge	167:e84263d55307	102	#if defined __FPU_VFP__
AnnaBridge	167:e84263d55307	103	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	167:e84263d55307	104	#endif
AnnaBridge	167:e84263d55307	105
AnnaBridge	167:e84263d55307	106	#elif defined ( __CSMC__ )
AnnaBridge	167:e84263d55307	107	#if ( __CSMC__ & 0x400U)
AnnaBridge	167:e84263d55307	108	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	167:e84263d55307	109	#endif
AnnaBridge	167:e84263d55307	110
AnnaBridge	167:e84263d55307	111	#endif
AnnaBridge	167:e84263d55307	112
AnnaBridge	167:e84263d55307	113	#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
AnnaBridge	167:e84263d55307	114
AnnaBridge	167:e84263d55307	115
AnnaBridge	167:e84263d55307	116	#ifdef __cplusplus
AnnaBridge	167:e84263d55307	117	}
AnnaBridge	167:e84263d55307	118	#endif
AnnaBridge	167:e84263d55307	119
AnnaBridge	167:e84263d55307	120	#endif /* __CORE_CM23_H_GENERIC */
AnnaBridge	167:e84263d55307	121
AnnaBridge	167:e84263d55307	122	#ifndef __CMSIS_GENERIC
AnnaBridge	167:e84263d55307	123
AnnaBridge	167:e84263d55307	124	#ifndef __CORE_CM23_H_DEPENDANT
AnnaBridge	167:e84263d55307	125	#define __CORE_CM23_H_DEPENDANT
AnnaBridge	167:e84263d55307	126
AnnaBridge	167:e84263d55307	127	#ifdef __cplusplus
AnnaBridge	167:e84263d55307	128	extern "C" {
AnnaBridge	167:e84263d55307	129	#endif
AnnaBridge	167:e84263d55307	130
AnnaBridge	167:e84263d55307	131	/* check device defines and use defaults */
AnnaBridge	167:e84263d55307	132	#if defined __CHECK_DEVICE_DEFINES
AnnaBridge	167:e84263d55307	133	#ifndef __CM23_REV
AnnaBridge	167:e84263d55307	134	#define __CM23_REV 0x0000U
AnnaBridge	167:e84263d55307	135	#warning "__CM23_REV not defined in device header file; using default!"
AnnaBridge	167:e84263d55307	136	#endif
AnnaBridge	167:e84263d55307	137
AnnaBridge	167:e84263d55307	138	#ifndef __FPU_PRESENT
AnnaBridge	167:e84263d55307	139	#define __FPU_PRESENT 0U
AnnaBridge	167:e84263d55307	140	#warning "__FPU_PRESENT not defined in device header file; using default!"
AnnaBridge	167:e84263d55307	141	#endif
AnnaBridge	167:e84263d55307	142
AnnaBridge	167:e84263d55307	143	#ifndef __MPU_PRESENT
AnnaBridge	167:e84263d55307	144	#define __MPU_PRESENT 0U
AnnaBridge	167:e84263d55307	145	#warning "__MPU_PRESENT not defined in device header file; using default!"
AnnaBridge	167:e84263d55307	146	#endif
AnnaBridge	167:e84263d55307	147
AnnaBridge	167:e84263d55307	148	#ifndef __SAUREGION_PRESENT
AnnaBridge	167:e84263d55307	149	#define __SAUREGION_PRESENT 0U
AnnaBridge	167:e84263d55307	150	#warning "__SAUREGION_PRESENT not defined in device header file; using default!"
AnnaBridge	167:e84263d55307	151	#endif
AnnaBridge	167:e84263d55307	152
AnnaBridge	167:e84263d55307	153	#ifndef __VTOR_PRESENT
AnnaBridge	167:e84263d55307	154	#define __VTOR_PRESENT 0U
AnnaBridge	167:e84263d55307	155	#warning "__VTOR_PRESENT not defined in device header file; using default!"
AnnaBridge	167:e84263d55307	156	#endif
AnnaBridge	167:e84263d55307	157
AnnaBridge	167:e84263d55307	158	#ifndef __NVIC_PRIO_BITS
AnnaBridge	167:e84263d55307	159	#define __NVIC_PRIO_BITS 2U
AnnaBridge	167:e84263d55307	160	#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
AnnaBridge	167:e84263d55307	161	#endif
AnnaBridge	167:e84263d55307	162
AnnaBridge	167:e84263d55307	163	#ifndef __Vendor_SysTickConfig
AnnaBridge	167:e84263d55307	164	#define __Vendor_SysTickConfig 0U
AnnaBridge	167:e84263d55307	165	#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
AnnaBridge	167:e84263d55307	166	#endif
AnnaBridge	167:e84263d55307	167
AnnaBridge	167:e84263d55307	168	#ifndef __ETM_PRESENT
AnnaBridge	167:e84263d55307	169	#define __ETM_PRESENT 0U
AnnaBridge	167:e84263d55307	170	#warning "__ETM_PRESENT not defined in device header file; using default!"
AnnaBridge	167:e84263d55307	171	#endif
AnnaBridge	167:e84263d55307	172
AnnaBridge	167:e84263d55307	173	#ifndef __MTB_PRESENT
AnnaBridge	167:e84263d55307	174	#define __MTB_PRESENT 0U
AnnaBridge	167:e84263d55307	175	#warning "__MTB_PRESENT not defined in device header file; using default!"
AnnaBridge	167:e84263d55307	176	#endif
AnnaBridge	167:e84263d55307	177
AnnaBridge	167:e84263d55307	178	#endif
AnnaBridge	167:e84263d55307	179
AnnaBridge	167:e84263d55307	180	/* IO definitions (access restrictions to peripheral registers) */
AnnaBridge	167:e84263d55307	181	/**
AnnaBridge	167:e84263d55307	182	\defgroup CMSIS_glob_defs CMSIS Global Defines
AnnaBridge	167:e84263d55307	183
AnnaBridge	167:e84263d55307	184	<strong>IO Type Qualifiers</strong> are used
AnnaBridge	167:e84263d55307	185	\li to specify the access to peripheral variables.
AnnaBridge	167:e84263d55307	186	\li for automatic generation of peripheral register debug information.
AnnaBridge	167:e84263d55307	187	*/
AnnaBridge	167:e84263d55307	188	#ifdef __cplusplus
AnnaBridge	167:e84263d55307	189	#define __I volatile /!< Defines 'read only' permissions /
AnnaBridge	167:e84263d55307	190	#else
AnnaBridge	167:e84263d55307	191	#define __I volatile const /!< Defines 'read only' permissions /
AnnaBridge	167:e84263d55307	192	#endif
AnnaBridge	167:e84263d55307	193	#define __O volatile /!< Defines 'write only' permissions /
AnnaBridge	167:e84263d55307	194	#define __IO volatile /!< Defines 'read / write' permissions /
AnnaBridge	167:e84263d55307	195
AnnaBridge	167:e84263d55307	196	/* following defines should be used for structure members */
AnnaBridge	167:e84263d55307	197	#define __IM volatile const /! Defines 'read only' structure member permissions /
AnnaBridge	167:e84263d55307	198	#define __OM volatile /! Defines 'write only' structure member permissions /
AnnaBridge	167:e84263d55307	199	#define __IOM volatile /! Defines 'read / write' structure member permissions /
AnnaBridge	167:e84263d55307	200
AnnaBridge	167:e84263d55307	201	/@} end of group Cortex_M23 /
AnnaBridge	167:e84263d55307	202
AnnaBridge	167:e84263d55307	203
AnnaBridge	167:e84263d55307	204
AnnaBridge	167:e84263d55307	205	/*******************************************************************************
AnnaBridge	167:e84263d55307	206	* Register Abstraction
AnnaBridge	167:e84263d55307	207	Core Register contain:
AnnaBridge	167:e84263d55307	208	- Core Register
AnnaBridge	167:e84263d55307	209	- Core NVIC Register
AnnaBridge	167:e84263d55307	210	- Core SCB Register
AnnaBridge	167:e84263d55307	211	- Core SysTick Register
AnnaBridge	167:e84263d55307	212	- Core Debug Register
AnnaBridge	167:e84263d55307	213	- Core MPU Register
AnnaBridge	167:e84263d55307	214	- Core SAU Register
AnnaBridge	167:e84263d55307	215	******************************************************************************/
AnnaBridge	167:e84263d55307	216	/**
AnnaBridge	167:e84263d55307	217	\defgroup CMSIS_core_register Defines and Type Definitions
AnnaBridge	167:e84263d55307	218	\brief Type definitions and defines for Cortex-M processor based devices.
AnnaBridge	167:e84263d55307	219	*/
AnnaBridge	167:e84263d55307	220
AnnaBridge	167:e84263d55307	221	/**
AnnaBridge	167:e84263d55307	222	\ingroup CMSIS_core_register
AnnaBridge	167:e84263d55307	223	\defgroup CMSIS_CORE Status and Control Registers
AnnaBridge	167:e84263d55307	224	\brief Core Register type definitions.
AnnaBridge	167:e84263d55307	225	@{
AnnaBridge	167:e84263d55307	226	*/
AnnaBridge	167:e84263d55307	227
AnnaBridge	167:e84263d55307	228	/**
AnnaBridge	167:e84263d55307	229	\brief Union type to access the Application Program Status Register (APSR).
AnnaBridge	167:e84263d55307	230	*/
AnnaBridge	167:e84263d55307	231	typedef union
AnnaBridge	167:e84263d55307	232	{
AnnaBridge	167:e84263d55307	233	struct
AnnaBridge	167:e84263d55307	234	{
AnnaBridge	167:e84263d55307	235	uint32_t _reserved0:28; /!< bit: 0..27 Reserved /
AnnaBridge	167:e84263d55307	236	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
AnnaBridge	167:e84263d55307	237	uint32_t C:1; /!< bit: 29 Carry condition code flag /
AnnaBridge	167:e84263d55307	238	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
AnnaBridge	167:e84263d55307	239	uint32_t N:1; /!< bit: 31 Negative condition code flag /
AnnaBridge	167:e84263d55307	240	} b; /!< Structure used for bit access /
AnnaBridge	167:e84263d55307	241	uint32_t w; /!< Type used for word access /
AnnaBridge	167:e84263d55307	242	} APSR_Type;
AnnaBridge	167:e84263d55307	243
AnnaBridge	167:e84263d55307	244	/* APSR Register Definitions */
AnnaBridge	167:e84263d55307	245	#define APSR_N_Pos 31U /!< APSR: N Position /
AnnaBridge	167:e84263d55307	246	#define APSR_N_Msk (1UL << APSR_N_Pos) /!< APSR: N Mask /
AnnaBridge	167:e84263d55307	247
AnnaBridge	167:e84263d55307	248	#define APSR_Z_Pos 30U /!< APSR: Z Position /
AnnaBridge	167:e84263d55307	249	#define APSR_Z_Msk (1UL << APSR_Z_Pos) /!< APSR: Z Mask /
AnnaBridge	167:e84263d55307	250
AnnaBridge	167:e84263d55307	251	#define APSR_C_Pos 29U /!< APSR: C Position /
AnnaBridge	167:e84263d55307	252	#define APSR_C_Msk (1UL << APSR_C_Pos) /!< APSR: C Mask /
AnnaBridge	167:e84263d55307	253
AnnaBridge	167:e84263d55307	254	#define APSR_V_Pos 28U /!< APSR: V Position /
AnnaBridge	167:e84263d55307	255	#define APSR_V_Msk (1UL << APSR_V_Pos) /!< APSR: V Mask /
AnnaBridge	167:e84263d55307	256
AnnaBridge	167:e84263d55307	257
AnnaBridge	167:e84263d55307	258	/**
AnnaBridge	167:e84263d55307	259	\brief Union type to access the Interrupt Program Status Register (IPSR).
AnnaBridge	167:e84263d55307	260	*/
AnnaBridge	167:e84263d55307	261	typedef union
AnnaBridge	167:e84263d55307	262	{
AnnaBridge	167:e84263d55307	263	struct
AnnaBridge	167:e84263d55307	264	{
AnnaBridge	167:e84263d55307	265	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
AnnaBridge	167:e84263d55307	266	uint32_t _reserved0:23; /!< bit: 9..31 Reserved /
AnnaBridge	167:e84263d55307	267	} b; /!< Structure used for bit access /
AnnaBridge	167:e84263d55307	268	uint32_t w; /!< Type used for word access /
AnnaBridge	167:e84263d55307	269	} IPSR_Type;
AnnaBridge	167:e84263d55307	270
AnnaBridge	167:e84263d55307	271	/* IPSR Register Definitions */
AnnaBridge	167:e84263d55307	272	#define IPSR_ISR_Pos 0U /!< IPSR: ISR Position /
AnnaBridge	167:e84263d55307	273	#define IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/) /!< IPSR: ISR Mask /
AnnaBridge	167:e84263d55307	274
AnnaBridge	167:e84263d55307	275
AnnaBridge	167:e84263d55307	276	/**
AnnaBridge	167:e84263d55307	277	\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
AnnaBridge	167:e84263d55307	278	*/
AnnaBridge	167:e84263d55307	279	typedef union
AnnaBridge	167:e84263d55307	280	{
AnnaBridge	167:e84263d55307	281	struct
AnnaBridge	167:e84263d55307	282	{
AnnaBridge	167:e84263d55307	283	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
AnnaBridge	167:e84263d55307	284	uint32_t _reserved0:15; /!< bit: 9..23 Reserved /
AnnaBridge	167:e84263d55307	285	uint32_t T:1; /!< bit: 24 Thumb bit (read 0) /
AnnaBridge	167:e84263d55307	286	uint32_t _reserved1:3; /!< bit: 25..27 Reserved /
AnnaBridge	167:e84263d55307	287	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
AnnaBridge	167:e84263d55307	288	uint32_t C:1; /!< bit: 29 Carry condition code flag /
AnnaBridge	167:e84263d55307	289	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
AnnaBridge	167:e84263d55307	290	uint32_t N:1; /!< bit: 31 Negative condition code flag /
AnnaBridge	167:e84263d55307	291	} b; /!< Structure used for bit access /
AnnaBridge	167:e84263d55307	292	uint32_t w; /!< Type used for word access /
AnnaBridge	167:e84263d55307	293	} xPSR_Type;
AnnaBridge	167:e84263d55307	294
AnnaBridge	167:e84263d55307	295	/* xPSR Register Definitions */
AnnaBridge	167:e84263d55307	296	#define xPSR_N_Pos 31U /!< xPSR: N Position /
AnnaBridge	167:e84263d55307	297	#define xPSR_N_Msk (1UL << xPSR_N_Pos) /!< xPSR: N Mask /
AnnaBridge	167:e84263d55307	298
AnnaBridge	167:e84263d55307	299	#define xPSR_Z_Pos 30U /!< xPSR: Z Position /
AnnaBridge	167:e84263d55307	300	#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /!< xPSR: Z Mask /
AnnaBridge	167:e84263d55307	301
AnnaBridge	167:e84263d55307	302	#define xPSR_C_Pos 29U /!< xPSR: C Position /
AnnaBridge	167:e84263d55307	303	#define xPSR_C_Msk (1UL << xPSR_C_Pos) /!< xPSR: C Mask /
AnnaBridge	167:e84263d55307	304
AnnaBridge	167:e84263d55307	305	#define xPSR_V_Pos 28U /!< xPSR: V Position /
AnnaBridge	167:e84263d55307	306	#define xPSR_V_Msk (1UL << xPSR_V_Pos) /!< xPSR: V Mask /
AnnaBridge	167:e84263d55307	307
AnnaBridge	167:e84263d55307	308	#define xPSR_T_Pos 24U /!< xPSR: T Position /
AnnaBridge	167:e84263d55307	309	#define xPSR_T_Msk (1UL << xPSR_T_Pos) /!< xPSR: T Mask /
AnnaBridge	167:e84263d55307	310
AnnaBridge	167:e84263d55307	311	#define xPSR_ISR_Pos 0U /!< xPSR: ISR Position /
AnnaBridge	167:e84263d55307	312	#define xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/) /!< xPSR: ISR Mask /
AnnaBridge	167:e84263d55307	313
AnnaBridge	167:e84263d55307	314
AnnaBridge	167:e84263d55307	315	/**
AnnaBridge	167:e84263d55307	316	\brief Union type to access the Control Registers (CONTROL).
AnnaBridge	167:e84263d55307	317	*/
AnnaBridge	167:e84263d55307	318	typedef union
AnnaBridge	167:e84263d55307	319	{
AnnaBridge	167:e84263d55307	320	struct
AnnaBridge	167:e84263d55307	321	{
AnnaBridge	167:e84263d55307	322	uint32_t nPRIV:1; /!< bit: 0 Execution privilege in Thread mode /
AnnaBridge	167:e84263d55307	323	uint32_t SPSEL:1; /!< bit: 1 Stack-pointer select /
AnnaBridge	167:e84263d55307	324	uint32_t _reserved1:30; /!< bit: 2..31 Reserved /
AnnaBridge	167:e84263d55307	325	} b; /!< Structure used for bit access /
AnnaBridge	167:e84263d55307	326	uint32_t w; /!< Type used for word access /
AnnaBridge	167:e84263d55307	327	} CONTROL_Type;
AnnaBridge	167:e84263d55307	328
AnnaBridge	167:e84263d55307	329	/* CONTROL Register Definitions */
AnnaBridge	167:e84263d55307	330	#define CONTROL_SPSEL_Pos 1U /!< CONTROL: SPSEL Position /
AnnaBridge	167:e84263d55307	331	#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /!< CONTROL: SPSEL Mask /
AnnaBridge	167:e84263d55307	332
AnnaBridge	167:e84263d55307	333	#define CONTROL_nPRIV_Pos 0U /!< CONTROL: nPRIV Position /
AnnaBridge	167:e84263d55307	334	#define CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/) /!< CONTROL: nPRIV Mask /
AnnaBridge	167:e84263d55307	335
AnnaBridge	167:e84263d55307	336	/@} end of group CMSIS_CORE /
AnnaBridge	167:e84263d55307	337
AnnaBridge	167:e84263d55307	338
AnnaBridge	167:e84263d55307	339	/**
AnnaBridge	167:e84263d55307	340	\ingroup CMSIS_core_register
AnnaBridge	167:e84263d55307	341	\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
AnnaBridge	167:e84263d55307	342	\brief Type definitions for the NVIC Registers
AnnaBridge	167:e84263d55307	343	@{
AnnaBridge	167:e84263d55307	344	*/
AnnaBridge	167:e84263d55307	345
AnnaBridge	167:e84263d55307	346	/**
AnnaBridge	167:e84263d55307	347	\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
AnnaBridge	167:e84263d55307	348	*/
AnnaBridge	167:e84263d55307	349	typedef struct
AnnaBridge	167:e84263d55307	350	{
AnnaBridge	167:e84263d55307	351	__IOM uint32_t ISER[16U]; /!< Offset: 0x000 (R/W) Interrupt Set Enable Register /
AnnaBridge	167:e84263d55307	352	uint32_t RESERVED0[16U];
AnnaBridge	167:e84263d55307	353	__IOM uint32_t ICER[16U]; /!< Offset: 0x080 (R/W) Interrupt Clear Enable Register /
AnnaBridge	167:e84263d55307	354	uint32_t RSERVED1[16U];
AnnaBridge	167:e84263d55307	355	__IOM uint32_t ISPR[16U]; /!< Offset: 0x100 (R/W) Interrupt Set Pending Register /
AnnaBridge	167:e84263d55307	356	uint32_t RESERVED2[16U];
AnnaBridge	167:e84263d55307	357	__IOM uint32_t ICPR[16U]; /!< Offset: 0x180 (R/W) Interrupt Clear Pending Register /
AnnaBridge	167:e84263d55307	358	uint32_t RESERVED3[16U];
AnnaBridge	167:e84263d55307	359	__IOM uint32_t IABR[16U]; /!< Offset: 0x200 (R/W) Interrupt Active bit Register /
AnnaBridge	167:e84263d55307	360	uint32_t RESERVED4[16U];
AnnaBridge	167:e84263d55307	361	__IOM uint32_t ITNS[16U]; /!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register /
AnnaBridge	167:e84263d55307	362	uint32_t RESERVED5[16U];
AnnaBridge	167:e84263d55307	363	__IOM uint32_t IPR[124U]; /!< Offset: 0x300 (R/W) Interrupt Priority Register /
AnnaBridge	167:e84263d55307	364	} NVIC_Type;
AnnaBridge	167:e84263d55307	365
AnnaBridge	167:e84263d55307	366	/@} end of group CMSIS_NVIC /
AnnaBridge	167:e84263d55307	367
AnnaBridge	167:e84263d55307	368
AnnaBridge	167:e84263d55307	369	/**
AnnaBridge	167:e84263d55307	370	\ingroup CMSIS_core_register
AnnaBridge	167:e84263d55307	371	\defgroup CMSIS_SCB System Control Block (SCB)
AnnaBridge	167:e84263d55307	372	\brief Type definitions for the System Control Block Registers
AnnaBridge	167:e84263d55307	373	@{
AnnaBridge	167:e84263d55307	374	*/
AnnaBridge	167:e84263d55307	375
AnnaBridge	167:e84263d55307	376	/**
AnnaBridge	167:e84263d55307	377	\brief Structure type to access the System Control Block (SCB).
AnnaBridge	167:e84263d55307	378	*/
AnnaBridge	167:e84263d55307	379	typedef struct
AnnaBridge	167:e84263d55307	380	{
AnnaBridge	167:e84263d55307	381	__IM uint32_t CPUID; /!< Offset: 0x000 (R/ ) CPUID Base Register /
AnnaBridge	167:e84263d55307	382	__IOM uint32_t ICSR; /!< Offset: 0x004 (R/W) Interrupt Control and State Register /
AnnaBridge	167:e84263d55307	383	#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
AnnaBridge	167:e84263d55307	384	__IOM uint32_t VTOR; /!< Offset: 0x008 (R/W) Vector Table Offset Register /
AnnaBridge	167:e84263d55307	385	#else
AnnaBridge	167:e84263d55307	386	uint32_t RESERVED0;
AnnaBridge	167:e84263d55307	387	#endif
AnnaBridge	167:e84263d55307	388	__IOM uint32_t AIRCR; /!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register /
AnnaBridge	167:e84263d55307	389	__IOM uint32_t SCR; /!< Offset: 0x010 (R/W) System Control Register /
AnnaBridge	167:e84263d55307	390	__IOM uint32_t CCR; /!< Offset: 0x014 (R/W) Configuration Control Register /
AnnaBridge	167:e84263d55307	391	uint32_t RESERVED1;
AnnaBridge	167:e84263d55307	392	__IOM uint32_t SHPR[2U]; /!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED /
AnnaBridge	167:e84263d55307	393	__IOM uint32_t SHCSR; /!< Offset: 0x024 (R/W) System Handler Control and State Register /
AnnaBridge	167:e84263d55307	394	} SCB_Type;
AnnaBridge	167:e84263d55307	395
AnnaBridge	167:e84263d55307	396	/* SCB CPUID Register Definitions */
AnnaBridge	167:e84263d55307	397	#define SCB_CPUID_IMPLEMENTER_Pos 24U /!< SCB CPUID: IMPLEMENTER Position /
AnnaBridge	167:e84263d55307	398	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
AnnaBridge	167:e84263d55307	399
AnnaBridge	167:e84263d55307	400	#define SCB_CPUID_VARIANT_Pos 20U /!< SCB CPUID: VARIANT Position /
AnnaBridge	167:e84263d55307	401	#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
AnnaBridge	167:e84263d55307	402
AnnaBridge	167:e84263d55307	403	#define SCB_CPUID_ARCHITECTURE_Pos 16U /!< SCB CPUID: ARCHITECTURE Position /
AnnaBridge	167:e84263d55307	404	#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /!< SCB CPUID: ARCHITECTURE Mask /
AnnaBridge	167:e84263d55307	405
AnnaBridge	167:e84263d55307	406	#define SCB_CPUID_PARTNO_Pos 4U /!< SCB CPUID: PARTNO Position /
AnnaBridge	167:e84263d55307	407	#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
AnnaBridge	167:e84263d55307	408
AnnaBridge	167:e84263d55307	409	#define SCB_CPUID_REVISION_Pos 0U /!< SCB CPUID: REVISION Position /
AnnaBridge	167:e84263d55307	410	#define SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/) /!< SCB CPUID: REVISION Mask /
AnnaBridge	167:e84263d55307	411
AnnaBridge	167:e84263d55307	412	/* SCB Interrupt Control State Register Definitions */
AnnaBridge	167:e84263d55307	413	#define SCB_ICSR_PENDNMISET_Pos 31U /!< SCB ICSR: PENDNMISET Position /
AnnaBridge	167:e84263d55307	414	#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /!< SCB ICSR: PENDNMISET Mask /
AnnaBridge	167:e84263d55307	415
AnnaBridge	167:e84263d55307	416	#define SCB_ICSR_PENDNMICLR_Pos 30U /!< SCB ICSR: PENDNMICLR Position /
AnnaBridge	167:e84263d55307	417	#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /!< SCB ICSR: PENDNMICLR Mask /
AnnaBridge	167:e84263d55307	418
AnnaBridge	167:e84263d55307	419	#define SCB_ICSR_PENDSVSET_Pos 28U /!< SCB ICSR: PENDSVSET Position /
AnnaBridge	167:e84263d55307	420	#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
AnnaBridge	167:e84263d55307	421
AnnaBridge	167:e84263d55307	422	#define SCB_ICSR_PENDSVCLR_Pos 27U /!< SCB ICSR: PENDSVCLR Position /
AnnaBridge	167:e84263d55307	423	#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
AnnaBridge	167:e84263d55307	424
AnnaBridge	167:e84263d55307	425	#define SCB_ICSR_PENDSTSET_Pos 26U /!< SCB ICSR: PENDSTSET Position /
AnnaBridge	167:e84263d55307	426	#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
AnnaBridge	167:e84263d55307	427
AnnaBridge	167:e84263d55307	428	#define SCB_ICSR_PENDSTCLR_Pos 25U /!< SCB ICSR: PENDSTCLR Position /
AnnaBridge	167:e84263d55307	429	#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
AnnaBridge	167:e84263d55307	430
AnnaBridge	167:e84263d55307	431	#define SCB_ICSR_STTNS_Pos 24U /!< SCB ICSR: STTNS Position (Security Extension) /
AnnaBridge	167:e84263d55307	432	#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /!< SCB ICSR: STTNS Mask (Security Extension) /
AnnaBridge	167:e84263d55307	433
AnnaBridge	167:e84263d55307	434	#define SCB_ICSR_ISRPREEMPT_Pos 23U /!< SCB ICSR: ISRPREEMPT Position /
AnnaBridge	167:e84263d55307	435	#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
AnnaBridge	167:e84263d55307	436
AnnaBridge	167:e84263d55307	437	#define SCB_ICSR_ISRPENDING_Pos 22U /!< SCB ICSR: ISRPENDING Position /
AnnaBridge	167:e84263d55307	438	#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
AnnaBridge	167:e84263d55307	439
AnnaBridge	167:e84263d55307	440	#define SCB_ICSR_VECTPENDING_Pos 12U /!< SCB ICSR: VECTPENDING Position /
AnnaBridge	167:e84263d55307	441	#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
AnnaBridge	167:e84263d55307	442
AnnaBridge	167:e84263d55307	443	#define SCB_ICSR_RETTOBASE_Pos 11U /!< SCB ICSR: RETTOBASE Position /
AnnaBridge	167:e84263d55307	444	#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
AnnaBridge	167:e84263d55307	445
AnnaBridge	167:e84263d55307	446	#define SCB_ICSR_VECTACTIVE_Pos 0U /!< SCB ICSR: VECTACTIVE Position /
AnnaBridge	167:e84263d55307	447	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/) /!< SCB ICSR: VECTACTIVE Mask /
AnnaBridge	167:e84263d55307	448
AnnaBridge	167:e84263d55307	449	#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
AnnaBridge	167:e84263d55307	450	/* SCB Vector Table Offset Register Definitions */
AnnaBridge	167:e84263d55307	451	#define SCB_VTOR_TBLOFF_Pos 7U /!< SCB VTOR: TBLOFF Position /
AnnaBridge	167:e84263d55307	452	#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
AnnaBridge	167:e84263d55307	453	#endif
AnnaBridge	167:e84263d55307	454
AnnaBridge	167:e84263d55307	455	/* SCB Application Interrupt and Reset Control Register Definitions */
AnnaBridge	167:e84263d55307	456	#define SCB_AIRCR_VECTKEY_Pos 16U /!< SCB AIRCR: VECTKEY Position /
AnnaBridge	167:e84263d55307	457	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
AnnaBridge	167:e84263d55307	458
AnnaBridge	167:e84263d55307	459	#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /!< SCB AIRCR: VECTKEYSTAT Position /
AnnaBridge	167:e84263d55307	460	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
AnnaBridge	167:e84263d55307	461
AnnaBridge	167:e84263d55307	462	#define SCB_AIRCR_ENDIANESS_Pos 15U /!< SCB AIRCR: ENDIANESS Position /
AnnaBridge	167:e84263d55307	463	#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
AnnaBridge	167:e84263d55307	464
AnnaBridge	167:e84263d55307	465	#define SCB_AIRCR_PRIS_Pos 14U /!< SCB AIRCR: PRIS Position /
AnnaBridge	167:e84263d55307	466	#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /!< SCB AIRCR: PRIS Mask /
AnnaBridge	167:e84263d55307	467
AnnaBridge	167:e84263d55307	468	#define SCB_AIRCR_BFHFNMINS_Pos 13U /!< SCB AIRCR: BFHFNMINS Position /
AnnaBridge	167:e84263d55307	469	#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /!< SCB AIRCR: BFHFNMINS Mask /
AnnaBridge	167:e84263d55307	470
AnnaBridge	167:e84263d55307	471	#define SCB_AIRCR_SYSRESETREQS_Pos 3U /!< SCB AIRCR: SYSRESETREQS Position /
AnnaBridge	167:e84263d55307	472	#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /!< SCB AIRCR: SYSRESETREQS Mask /
AnnaBridge	167:e84263d55307	473
AnnaBridge	167:e84263d55307	474	#define SCB_AIRCR_SYSRESETREQ_Pos 2U /!< SCB AIRCR: SYSRESETREQ Position /
AnnaBridge	167:e84263d55307	475	#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
AnnaBridge	167:e84263d55307	476
AnnaBridge	167:e84263d55307	477	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /!< SCB AIRCR: VECTCLRACTIVE Position /
AnnaBridge	167:e84263d55307	478	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
AnnaBridge	167:e84263d55307	479
AnnaBridge	167:e84263d55307	480	/* SCB System Control Register Definitions */
AnnaBridge	167:e84263d55307	481	#define SCB_SCR_SEVONPEND_Pos 4U /!< SCB SCR: SEVONPEND Position /
AnnaBridge	167:e84263d55307	482	#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
AnnaBridge	167:e84263d55307	483
AnnaBridge	167:e84263d55307	484	#define SCB_SCR_SLEEPDEEPS_Pos 3U /!< SCB SCR: SLEEPDEEPS Position /
AnnaBridge	167:e84263d55307	485	#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /!< SCB SCR: SLEEPDEEPS Mask /
AnnaBridge	167:e84263d55307	486
AnnaBridge	167:e84263d55307	487	#define SCB_SCR_SLEEPDEEP_Pos 2U /!< SCB SCR: SLEEPDEEP Position /
AnnaBridge	167:e84263d55307	488	#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
AnnaBridge	167:e84263d55307	489
AnnaBridge	167:e84263d55307	490	#define SCB_SCR_SLEEPONEXIT_Pos 1U /!< SCB SCR: SLEEPONEXIT Position /
AnnaBridge	167:e84263d55307	491	#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
AnnaBridge	167:e84263d55307	492
AnnaBridge	167:e84263d55307	493	/* SCB Configuration Control Register Definitions */
AnnaBridge	167:e84263d55307	494	#define SCB_CCR_BP_Pos 18U /!< SCB CCR: BP Position /
AnnaBridge	167:e84263d55307	495	#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /!< SCB CCR: BP Mask /
AnnaBridge	167:e84263d55307	496
AnnaBridge	167:e84263d55307	497	#define SCB_CCR_IC_Pos 17U /!< SCB CCR: IC Position /
AnnaBridge	167:e84263d55307	498	#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /!< SCB CCR: IC Mask /
AnnaBridge	167:e84263d55307	499
AnnaBridge	167:e84263d55307	500	#define SCB_CCR_DC_Pos 16U /!< SCB CCR: DC Position /
AnnaBridge	167:e84263d55307	501	#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /!< SCB CCR: DC Mask /
AnnaBridge	167:e84263d55307	502
AnnaBridge	167:e84263d55307	503	#define SCB_CCR_STKOFHFNMIGN_Pos 10U /!< SCB CCR: STKOFHFNMIGN Position /
AnnaBridge	167:e84263d55307	504	#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /!< SCB CCR: STKOFHFNMIGN Mask /
AnnaBridge	167:e84263d55307	505
AnnaBridge	167:e84263d55307	506	#define SCB_CCR_BFHFNMIGN_Pos 8U /!< SCB CCR: BFHFNMIGN Position /
AnnaBridge	167:e84263d55307	507	#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
AnnaBridge	167:e84263d55307	508
AnnaBridge	167:e84263d55307	509	#define SCB_CCR_DIV_0_TRP_Pos 4U /!< SCB CCR: DIV_0_TRP Position /
AnnaBridge	167:e84263d55307	510	#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
AnnaBridge	167:e84263d55307	511
AnnaBridge	167:e84263d55307	512	#define SCB_CCR_UNALIGN_TRP_Pos 3U /!< SCB CCR: UNALIGN_TRP Position /
AnnaBridge	167:e84263d55307	513	#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
AnnaBridge	167:e84263d55307	514
AnnaBridge	167:e84263d55307	515	#define SCB_CCR_USERSETMPEND_Pos 1U /!< SCB CCR: USERSETMPEND Position /
AnnaBridge	167:e84263d55307	516	#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
AnnaBridge	167:e84263d55307	517
AnnaBridge	167:e84263d55307	518	/* SCB System Handler Control and State Register Definitions */
AnnaBridge	167:e84263d55307	519	#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /!< SCB SHCSR: HARDFAULTPENDED Position /
AnnaBridge	167:e84263d55307	520	#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /!< SCB SHCSR: HARDFAULTPENDED Mask /
AnnaBridge	167:e84263d55307	521
AnnaBridge	167:e84263d55307	522	#define SCB_SHCSR_SVCALLPENDED_Pos 15U /!< SCB SHCSR: SVCALLPENDED Position /
AnnaBridge	167:e84263d55307	523	#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
AnnaBridge	167:e84263d55307	524
AnnaBridge	167:e84263d55307	525	#define SCB_SHCSR_SYSTICKACT_Pos 11U /!< SCB SHCSR: SYSTICKACT Position /
AnnaBridge	167:e84263d55307	526	#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
AnnaBridge	167:e84263d55307	527
AnnaBridge	167:e84263d55307	528	#define SCB_SHCSR_PENDSVACT_Pos 10U /!< SCB SHCSR: PENDSVACT Position /
AnnaBridge	167:e84263d55307	529	#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
AnnaBridge	167:e84263d55307	530
AnnaBridge	167:e84263d55307	531	#define SCB_SHCSR_SVCALLACT_Pos 7U /!< SCB SHCSR: SVCALLACT Position /
AnnaBridge	167:e84263d55307	532	#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
AnnaBridge	167:e84263d55307	533
AnnaBridge	167:e84263d55307	534	#define SCB_SHCSR_NMIACT_Pos 5U /!< SCB SHCSR: NMIACT Position /
AnnaBridge	167:e84263d55307	535	#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /!< SCB SHCSR: NMIACT Mask /
AnnaBridge	167:e84263d55307	536
AnnaBridge	167:e84263d55307	537	#define SCB_SHCSR_HARDFAULTACT_Pos 2U /!< SCB SHCSR: HARDFAULTACT Position /
AnnaBridge	167:e84263d55307	538	#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /!< SCB SHCSR: HARDFAULTACT Mask /
AnnaBridge	167:e84263d55307	539
AnnaBridge	167:e84263d55307	540	/@} end of group CMSIS_SCB /
AnnaBridge	167:e84263d55307	541
AnnaBridge	167:e84263d55307	542
AnnaBridge	167:e84263d55307	543	/**
AnnaBridge	167:e84263d55307	544	\ingroup CMSIS_core_register
AnnaBridge	167:e84263d55307	545	\defgroup CMSIS_SysTick System Tick Timer (SysTick)
AnnaBridge	167:e84263d55307	546	\brief Type definitions for the System Timer Registers.
AnnaBridge	167:e84263d55307	547	@{
AnnaBridge	167:e84263d55307	548	*/
AnnaBridge	167:e84263d55307	549
AnnaBridge	167:e84263d55307	550	/**
AnnaBridge	167:e84263d55307	551	\brief Structure type to access the System Timer (SysTick).
AnnaBridge	167:e84263d55307	552	*/
AnnaBridge	167:e84263d55307	553	typedef struct
AnnaBridge	167:e84263d55307	554	{
AnnaBridge	167:e84263d55307	555	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) SysTick Control and Status Register /
AnnaBridge	167:e84263d55307	556	__IOM uint32_t LOAD; /!< Offset: 0x004 (R/W) SysTick Reload Value Register /
AnnaBridge	167:e84263d55307	557	__IOM uint32_t VAL; /!< Offset: 0x008 (R/W) SysTick Current Value Register /
AnnaBridge	167:e84263d55307	558	__IM uint32_t CALIB; /!< Offset: 0x00C (R/ ) SysTick Calibration Register /
AnnaBridge	167:e84263d55307	559	} SysTick_Type;
AnnaBridge	167:e84263d55307	560
AnnaBridge	167:e84263d55307	561	/* SysTick Control / Status Register Definitions */
AnnaBridge	167:e84263d55307	562	#define SysTick_CTRL_COUNTFLAG_Pos 16U /!< SysTick CTRL: COUNTFLAG Position /
AnnaBridge	167:e84263d55307	563	#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
AnnaBridge	167:e84263d55307	564
AnnaBridge	167:e84263d55307	565	#define SysTick_CTRL_CLKSOURCE_Pos 2U /!< SysTick CTRL: CLKSOURCE Position /
AnnaBridge	167:e84263d55307	566	#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
AnnaBridge	167:e84263d55307	567
AnnaBridge	167:e84263d55307	568	#define SysTick_CTRL_TICKINT_Pos 1U /!< SysTick CTRL: TICKINT Position /
AnnaBridge	167:e84263d55307	569	#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
AnnaBridge	167:e84263d55307	570
AnnaBridge	167:e84263d55307	571	#define SysTick_CTRL_ENABLE_Pos 0U /!< SysTick CTRL: ENABLE Position /
AnnaBridge	167:e84263d55307	572	#define SysTick_CTRL_ENABLE_Msk (1UL /<< SysTick_CTRL_ENABLE_Pos/) /!< SysTick CTRL: ENABLE Mask /
AnnaBridge	167:e84263d55307	573
AnnaBridge	167:e84263d55307	574	/* SysTick Reload Register Definitions */
AnnaBridge	167:e84263d55307	575	#define SysTick_LOAD_RELOAD_Pos 0U /!< SysTick LOAD: RELOAD Position /
AnnaBridge	167:e84263d55307	576	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /<< SysTick_LOAD_RELOAD_Pos/) /!< SysTick LOAD: RELOAD Mask /
AnnaBridge	167:e84263d55307	577
AnnaBridge	167:e84263d55307	578	/* SysTick Current Register Definitions */
AnnaBridge	167:e84263d55307	579	#define SysTick_VAL_CURRENT_Pos 0U /!< SysTick VAL: CURRENT Position /
AnnaBridge	167:e84263d55307	580	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /<< SysTick_VAL_CURRENT_Pos/) /!< SysTick VAL: CURRENT Mask /
AnnaBridge	167:e84263d55307	581
AnnaBridge	167:e84263d55307	582	/* SysTick Calibration Register Definitions */
AnnaBridge	167:e84263d55307	583	#define SysTick_CALIB_NOREF_Pos 31U /!< SysTick CALIB: NOREF Position /
AnnaBridge	167:e84263d55307	584	#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
AnnaBridge	167:e84263d55307	585
AnnaBridge	167:e84263d55307	586	#define SysTick_CALIB_SKEW_Pos 30U /!< SysTick CALIB: SKEW Position /
AnnaBridge	167:e84263d55307	587	#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
AnnaBridge	167:e84263d55307	588
AnnaBridge	167:e84263d55307	589	#define SysTick_CALIB_TENMS_Pos 0U /!< SysTick CALIB: TENMS Position /
AnnaBridge	167:e84263d55307	590	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /<< SysTick_CALIB_TENMS_Pos/) /!< SysTick CALIB: TENMS Mask /
AnnaBridge	167:e84263d55307	591
AnnaBridge	167:e84263d55307	592	/@} end of group CMSIS_SysTick /
AnnaBridge	167:e84263d55307	593
AnnaBridge	167:e84263d55307	594
AnnaBridge	167:e84263d55307	595	/**
AnnaBridge	167:e84263d55307	596	\ingroup CMSIS_core_register
AnnaBridge	167:e84263d55307	597	\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
AnnaBridge	167:e84263d55307	598	\brief Type definitions for the Data Watchpoint and Trace (DWT)
AnnaBridge	167:e84263d55307	599	@{
AnnaBridge	167:e84263d55307	600	*/
AnnaBridge	167:e84263d55307	601
AnnaBridge	167:e84263d55307	602	/**
AnnaBridge	167:e84263d55307	603	\brief Structure type to access the Data Watchpoint and Trace Register (DWT).
AnnaBridge	167:e84263d55307	604	*/
AnnaBridge	167:e84263d55307	605	typedef struct
AnnaBridge	167:e84263d55307	606	{
AnnaBridge	167:e84263d55307	607	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) Control Register /
AnnaBridge	167:e84263d55307	608	uint32_t RESERVED0[6U];
AnnaBridge	167:e84263d55307	609	__IM uint32_t PCSR; /!< Offset: 0x01C (R/ ) Program Counter Sample Register /
AnnaBridge	167:e84263d55307	610	__IOM uint32_t COMP0; /!< Offset: 0x020 (R/W) Comparator Register 0 /
AnnaBridge	167:e84263d55307	611	uint32_t RESERVED1[1U];
AnnaBridge	167:e84263d55307	612	__IOM uint32_t FUNCTION0; /!< Offset: 0x028 (R/W) Function Register 0 /
AnnaBridge	167:e84263d55307	613	uint32_t RESERVED2[1U];
AnnaBridge	167:e84263d55307	614	__IOM uint32_t COMP1; /!< Offset: 0x030 (R/W) Comparator Register 1 /
AnnaBridge	167:e84263d55307	615	uint32_t RESERVED3[1U];
AnnaBridge	167:e84263d55307	616	__IOM uint32_t FUNCTION1; /!< Offset: 0x038 (R/W) Function Register 1 /
AnnaBridge	167:e84263d55307	617	uint32_t RESERVED4[1U];
AnnaBridge	167:e84263d55307	618	__IOM uint32_t COMP2; /!< Offset: 0x040 (R/W) Comparator Register 2 /
AnnaBridge	167:e84263d55307	619	uint32_t RESERVED5[1U];
AnnaBridge	167:e84263d55307	620	__IOM uint32_t FUNCTION2; /!< Offset: 0x048 (R/W) Function Register 2 /
AnnaBridge	167:e84263d55307	621	uint32_t RESERVED6[1U];
AnnaBridge	167:e84263d55307	622	__IOM uint32_t COMP3; /!< Offset: 0x050 (R/W) Comparator Register 3 /
AnnaBridge	167:e84263d55307	623	uint32_t RESERVED7[1U];
AnnaBridge	167:e84263d55307	624	__IOM uint32_t FUNCTION3; /!< Offset: 0x058 (R/W) Function Register 3 /
AnnaBridge	167:e84263d55307	625	uint32_t RESERVED8[1U];
AnnaBridge	167:e84263d55307	626	__IOM uint32_t COMP4; /!< Offset: 0x060 (R/W) Comparator Register 4 /
AnnaBridge	167:e84263d55307	627	uint32_t RESERVED9[1U];
AnnaBridge	167:e84263d55307	628	__IOM uint32_t FUNCTION4; /!< Offset: 0x068 (R/W) Function Register 4 /
AnnaBridge	167:e84263d55307	629	uint32_t RESERVED10[1U];
AnnaBridge	167:e84263d55307	630	__IOM uint32_t COMP5; /!< Offset: 0x070 (R/W) Comparator Register 5 /
AnnaBridge	167:e84263d55307	631	uint32_t RESERVED11[1U];
AnnaBridge	167:e84263d55307	632	__IOM uint32_t FUNCTION5; /!< Offset: 0x078 (R/W) Function Register 5 /
AnnaBridge	167:e84263d55307	633	uint32_t RESERVED12[1U];
AnnaBridge	167:e84263d55307	634	__IOM uint32_t COMP6; /!< Offset: 0x080 (R/W) Comparator Register 6 /
AnnaBridge	167:e84263d55307	635	uint32_t RESERVED13[1U];
AnnaBridge	167:e84263d55307	636	__IOM uint32_t FUNCTION6; /!< Offset: 0x088 (R/W) Function Register 6 /
AnnaBridge	167:e84263d55307	637	uint32_t RESERVED14[1U];
AnnaBridge	167:e84263d55307	638	__IOM uint32_t COMP7; /!< Offset: 0x090 (R/W) Comparator Register 7 /
AnnaBridge	167:e84263d55307	639	uint32_t RESERVED15[1U];
AnnaBridge	167:e84263d55307	640	__IOM uint32_t FUNCTION7; /!< Offset: 0x098 (R/W) Function Register 7 /
AnnaBridge	167:e84263d55307	641	uint32_t RESERVED16[1U];
AnnaBridge	167:e84263d55307	642	__IOM uint32_t COMP8; /!< Offset: 0x0A0 (R/W) Comparator Register 8 /
AnnaBridge	167:e84263d55307	643	uint32_t RESERVED17[1U];
AnnaBridge	167:e84263d55307	644	__IOM uint32_t FUNCTION8; /!< Offset: 0x0A8 (R/W) Function Register 8 /
AnnaBridge	167:e84263d55307	645	uint32_t RESERVED18[1U];
AnnaBridge	167:e84263d55307	646	__IOM uint32_t COMP9; /!< Offset: 0x0B0 (R/W) Comparator Register 9 /
AnnaBridge	167:e84263d55307	647	uint32_t RESERVED19[1U];
AnnaBridge	167:e84263d55307	648	__IOM uint32_t FUNCTION9; /!< Offset: 0x0B8 (R/W) Function Register 9 /
AnnaBridge	167:e84263d55307	649	uint32_t RESERVED20[1U];
AnnaBridge	167:e84263d55307	650	__IOM uint32_t COMP10; /!< Offset: 0x0C0 (R/W) Comparator Register 10 /
AnnaBridge	167:e84263d55307	651	uint32_t RESERVED21[1U];
AnnaBridge	167:e84263d55307	652	__IOM uint32_t FUNCTION10; /!< Offset: 0x0C8 (R/W) Function Register 10 /
AnnaBridge	167:e84263d55307	653	uint32_t RESERVED22[1U];
AnnaBridge	167:e84263d55307	654	__IOM uint32_t COMP11; /!< Offset: 0x0D0 (R/W) Comparator Register 11 /
AnnaBridge	167:e84263d55307	655	uint32_t RESERVED23[1U];
AnnaBridge	167:e84263d55307	656	__IOM uint32_t FUNCTION11; /!< Offset: 0x0D8 (R/W) Function Register 11 /
AnnaBridge	167:e84263d55307	657	uint32_t RESERVED24[1U];
AnnaBridge	167:e84263d55307	658	__IOM uint32_t COMP12; /!< Offset: 0x0E0 (R/W) Comparator Register 12 /
AnnaBridge	167:e84263d55307	659	uint32_t RESERVED25[1U];
AnnaBridge	167:e84263d55307	660	__IOM uint32_t FUNCTION12; /!< Offset: 0x0E8 (R/W) Function Register 12 /
AnnaBridge	167:e84263d55307	661	uint32_t RESERVED26[1U];
AnnaBridge	167:e84263d55307	662	__IOM uint32_t COMP13; /!< Offset: 0x0F0 (R/W) Comparator Register 13 /
AnnaBridge	167:e84263d55307	663	uint32_t RESERVED27[1U];
AnnaBridge	167:e84263d55307	664	__IOM uint32_t FUNCTION13; /!< Offset: 0x0F8 (R/W) Function Register 13 /
AnnaBridge	167:e84263d55307	665	uint32_t RESERVED28[1U];
AnnaBridge	167:e84263d55307	666	__IOM uint32_t COMP14; /!< Offset: 0x100 (R/W) Comparator Register 14 /
AnnaBridge	167:e84263d55307	667	uint32_t RESERVED29[1U];
AnnaBridge	167:e84263d55307	668	__IOM uint32_t FUNCTION14; /!< Offset: 0x108 (R/W) Function Register 14 /
AnnaBridge	167:e84263d55307	669	uint32_t RESERVED30[1U];
AnnaBridge	167:e84263d55307	670	__IOM uint32_t COMP15; /!< Offset: 0x110 (R/W) Comparator Register 15 /
AnnaBridge	167:e84263d55307	671	uint32_t RESERVED31[1U];
AnnaBridge	167:e84263d55307	672	__IOM uint32_t FUNCTION15; /!< Offset: 0x118 (R/W) Function Register 15 /
AnnaBridge	167:e84263d55307	673	} DWT_Type;
AnnaBridge	167:e84263d55307	674
AnnaBridge	167:e84263d55307	675	/* DWT Control Register Definitions */
AnnaBridge	167:e84263d55307	676	#define DWT_CTRL_NUMCOMP_Pos 28U /!< DWT CTRL: NUMCOMP Position /
AnnaBridge	167:e84263d55307	677	#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /!< DWT CTRL: NUMCOMP Mask /
AnnaBridge	167:e84263d55307	678
AnnaBridge	167:e84263d55307	679	#define DWT_CTRL_NOTRCPKT_Pos 27U /!< DWT CTRL: NOTRCPKT Position /
AnnaBridge	167:e84263d55307	680	#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /!< DWT CTRL: NOTRCPKT Mask /
AnnaBridge	167:e84263d55307	681
AnnaBridge	167:e84263d55307	682	#define DWT_CTRL_NOEXTTRIG_Pos 26U /!< DWT CTRL: NOEXTTRIG Position /
AnnaBridge	167:e84263d55307	683	#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /!< DWT CTRL: NOEXTTRIG Mask /
AnnaBridge	167:e84263d55307	684
AnnaBridge	167:e84263d55307	685	#define DWT_CTRL_NOCYCCNT_Pos 25U /!< DWT CTRL: NOCYCCNT Position /
AnnaBridge	167:e84263d55307	686	#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /!< DWT CTRL: NOCYCCNT Mask /
AnnaBridge	167:e84263d55307	687
AnnaBridge	167:e84263d55307	688	#define DWT_CTRL_NOPRFCNT_Pos 24U /!< DWT CTRL: NOPRFCNT Position /
AnnaBridge	167:e84263d55307	689	#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /!< DWT CTRL: NOPRFCNT Mask /
AnnaBridge	167:e84263d55307	690
AnnaBridge	167:e84263d55307	691	/* DWT Comparator Function Register Definitions */
AnnaBridge	167:e84263d55307	692	#define DWT_FUNCTION_ID_Pos 27U /!< DWT FUNCTION: ID Position /
AnnaBridge	167:e84263d55307	693	#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /!< DWT FUNCTION: ID Mask /
AnnaBridge	167:e84263d55307	694
AnnaBridge	167:e84263d55307	695	#define DWT_FUNCTION_MATCHED_Pos 24U /!< DWT FUNCTION: MATCHED Position /
AnnaBridge	167:e84263d55307	696	#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /!< DWT FUNCTION: MATCHED Mask /
AnnaBridge	167:e84263d55307	697
AnnaBridge	167:e84263d55307	698	#define DWT_FUNCTION_DATAVSIZE_Pos 10U /!< DWT FUNCTION: DATAVSIZE Position /
AnnaBridge	167:e84263d55307	699	#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /!< DWT FUNCTION: DATAVSIZE Mask /
AnnaBridge	167:e84263d55307	700
AnnaBridge	167:e84263d55307	701	#define DWT_FUNCTION_ACTION_Pos 4U /!< DWT FUNCTION: ACTION Position /
AnnaBridge	167:e84263d55307	702	#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /!< DWT FUNCTION: ACTION Mask /
AnnaBridge	167:e84263d55307	703
AnnaBridge	167:e84263d55307	704	#define DWT_FUNCTION_MATCH_Pos 0U /!< DWT FUNCTION: MATCH Position /
AnnaBridge	167:e84263d55307	705	#define DWT_FUNCTION_MATCH_Msk (0xFUL /<< DWT_FUNCTION_MATCH_Pos/) /!< DWT FUNCTION: MATCH Mask /
AnnaBridge	167:e84263d55307	706
AnnaBridge	167:e84263d55307	707	/@}/ /* end of group CMSIS_DWT */
AnnaBridge	167:e84263d55307	708
AnnaBridge	167:e84263d55307	709
AnnaBridge	167:e84263d55307	710	/**
AnnaBridge	167:e84263d55307	711	\ingroup CMSIS_core_register
AnnaBridge	167:e84263d55307	712	\defgroup CMSIS_TPI Trace Port Interface (TPI)
AnnaBridge	167:e84263d55307	713	\brief Type definitions for the Trace Port Interface (TPI)
AnnaBridge	167:e84263d55307	714	@{
AnnaBridge	167:e84263d55307	715	*/
AnnaBridge	167:e84263d55307	716
AnnaBridge	167:e84263d55307	717	/**
AnnaBridge	167:e84263d55307	718	\brief Structure type to access the Trace Port Interface Register (TPI).
AnnaBridge	167:e84263d55307	719	*/
AnnaBridge	167:e84263d55307	720	typedef struct
AnnaBridge	167:e84263d55307	721	{
AnnaBridge	167:e84263d55307	722	__IOM uint32_t SSPSR; /!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register /
AnnaBridge	167:e84263d55307	723	__IOM uint32_t CSPSR; /!< Offset: 0x004 (R/W) Current Parallel Port Size Register /
AnnaBridge	167:e84263d55307	724	uint32_t RESERVED0[2U];
AnnaBridge	167:e84263d55307	725	__IOM uint32_t ACPR; /!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register /
AnnaBridge	167:e84263d55307	726	uint32_t RESERVED1[55U];
AnnaBridge	167:e84263d55307	727	__IOM uint32_t SPPR; /!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register /
AnnaBridge	167:e84263d55307	728	uint32_t RESERVED2[131U];
AnnaBridge	167:e84263d55307	729	__IM uint32_t FFSR; /!< Offset: 0x300 (R/ ) Formatter and Flush Status Register /
AnnaBridge	167:e84263d55307	730	__IOM uint32_t FFCR; /!< Offset: 0x304 (R/W) Formatter and Flush Control Register /
AnnaBridge	167:e84263d55307	731	__IM uint32_t FSCR; /!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register /
AnnaBridge	167:e84263d55307	732	uint32_t RESERVED3[759U];
AnnaBridge	167:e84263d55307	733	__IM uint32_t TRIGGER; /!< Offset: 0xEE8 (R/ ) TRIGGER /
AnnaBridge	167:e84263d55307	734	__IM uint32_t FIFO0; /!< Offset: 0xEEC (R/ ) Integration ETM Data /
AnnaBridge	167:e84263d55307	735	__IM uint32_t ITATBCTR2; /!< Offset: 0xEF0 (R/ ) ITATBCTR2 /
AnnaBridge	167:e84263d55307	736	uint32_t RESERVED4[1U];
AnnaBridge	167:e84263d55307	737	__IM uint32_t ITATBCTR0; /!< Offset: 0xEF8 (R/ ) ITATBCTR0 /
AnnaBridge	167:e84263d55307	738	__IM uint32_t FIFO1; /!< Offset: 0xEFC (R/ ) Integration ITM Data /
AnnaBridge	167:e84263d55307	739	__IOM uint32_t ITCTRL; /!< Offset: 0xF00 (R/W) Integration Mode Control /
AnnaBridge	167:e84263d55307	740	uint32_t RESERVED5[39U];
AnnaBridge	167:e84263d55307	741	__IOM uint32_t CLAIMSET; /!< Offset: 0xFA0 (R/W) Claim tag set /
AnnaBridge	167:e84263d55307	742	__IOM uint32_t CLAIMCLR; /!< Offset: 0xFA4 (R/W) Claim tag clear /
AnnaBridge	167:e84263d55307	743	uint32_t RESERVED7[8U];
AnnaBridge	167:e84263d55307	744	__IM uint32_t DEVID; /!< Offset: 0xFC8 (R/ ) TPIU_DEVID /
AnnaBridge	167:e84263d55307	745	__IM uint32_t DEVTYPE; /!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE /
AnnaBridge	167:e84263d55307	746	} TPI_Type;
AnnaBridge	167:e84263d55307	747
AnnaBridge	167:e84263d55307	748	/* TPI Asynchronous Clock Prescaler Register Definitions */
AnnaBridge	167:e84263d55307	749	#define TPI_ACPR_PRESCALER_Pos 0U /!< TPI ACPR: PRESCALER Position /
AnnaBridge	167:e84263d55307	750	#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/) /!< TPI ACPR: PRESCALER Mask /
AnnaBridge	167:e84263d55307	751
AnnaBridge	167:e84263d55307	752	/* TPI Selected Pin Protocol Register Definitions */
AnnaBridge	167:e84263d55307	753	#define TPI_SPPR_TXMODE_Pos 0U /!< TPI SPPR: TXMODE Position /
AnnaBridge	167:e84263d55307	754	#define TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/) /!< TPI SPPR: TXMODE Mask /
AnnaBridge	167:e84263d55307	755
AnnaBridge	167:e84263d55307	756	/* TPI Formatter and Flush Status Register Definitions */
AnnaBridge	167:e84263d55307	757	#define TPI_FFSR_FtNonStop_Pos 3U /!< TPI FFSR: FtNonStop Position /
AnnaBridge	167:e84263d55307	758	#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /!< TPI FFSR: FtNonStop Mask /
AnnaBridge	167:e84263d55307	759
AnnaBridge	167:e84263d55307	760	#define TPI_FFSR_TCPresent_Pos 2U /!< TPI FFSR: TCPresent Position /
AnnaBridge	167:e84263d55307	761	#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /!< TPI FFSR: TCPresent Mask /
AnnaBridge	167:e84263d55307	762
AnnaBridge	167:e84263d55307	763	#define TPI_FFSR_FtStopped_Pos 1U /!< TPI FFSR: FtStopped Position /
AnnaBridge	167:e84263d55307	764	#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /!< TPI FFSR: FtStopped Mask /
AnnaBridge	167:e84263d55307	765
AnnaBridge	167:e84263d55307	766	#define TPI_FFSR_FlInProg_Pos 0U /!< TPI FFSR: FlInProg Position /
AnnaBridge	167:e84263d55307	767	#define TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/) /!< TPI FFSR: FlInProg Mask /
AnnaBridge	167:e84263d55307	768
AnnaBridge	167:e84263d55307	769	/* TPI Formatter and Flush Control Register Definitions */
AnnaBridge	167:e84263d55307	770	#define TPI_FFCR_TrigIn_Pos 8U /!< TPI FFCR: TrigIn Position /
AnnaBridge	167:e84263d55307	771	#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /!< TPI FFCR: TrigIn Mask /
AnnaBridge	167:e84263d55307	772
AnnaBridge	167:e84263d55307	773	#define TPI_FFCR_EnFCont_Pos 1U /!< TPI FFCR: EnFCont Position /
AnnaBridge	167:e84263d55307	774	#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /!< TPI FFCR: EnFCont Mask /
AnnaBridge	167:e84263d55307	775
AnnaBridge	167:e84263d55307	776	/* TPI TRIGGER Register Definitions */
AnnaBridge	167:e84263d55307	777	#define TPI_TRIGGER_TRIGGER_Pos 0U /!< TPI TRIGGER: TRIGGER Position /
AnnaBridge	167:e84263d55307	778	#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/) /!< TPI TRIGGER: TRIGGER Mask /
AnnaBridge	167:e84263d55307	779
AnnaBridge	167:e84263d55307	780	/* TPI Integration ETM Data Register Definitions (FIFO0) */
AnnaBridge	167:e84263d55307	781	#define TPI_FIFO0_ITM_ATVALID_Pos 29U /!< TPI FIFO0: ITM_ATVALID Position /
AnnaBridge	167:e84263d55307	782	#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /!< TPI FIFO0: ITM_ATVALID Mask /
AnnaBridge	167:e84263d55307	783
AnnaBridge	167:e84263d55307	784	#define TPI_FIFO0_ITM_bytecount_Pos 27U /!< TPI FIFO0: ITM_bytecount Position /
AnnaBridge	167:e84263d55307	785	#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /!< TPI FIFO0: ITM_bytecount Mask /
AnnaBridge	167:e84263d55307	786
AnnaBridge	167:e84263d55307	787	#define TPI_FIFO0_ETM_ATVALID_Pos 26U /!< TPI FIFO0: ETM_ATVALID Position /
AnnaBridge	167:e84263d55307	788	#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /!< TPI FIFO0: ETM_ATVALID Mask /
AnnaBridge	167:e84263d55307	789
AnnaBridge	167:e84263d55307	790	#define TPI_FIFO0_ETM_bytecount_Pos 24U /!< TPI FIFO0: ETM_bytecount Position /
AnnaBridge	167:e84263d55307	791	#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /!< TPI FIFO0: ETM_bytecount Mask /
AnnaBridge	167:e84263d55307	792
AnnaBridge	167:e84263d55307	793	#define TPI_FIFO0_ETM2_Pos 16U /!< TPI FIFO0: ETM2 Position /
AnnaBridge	167:e84263d55307	794	#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /!< TPI FIFO0: ETM2 Mask /
AnnaBridge	167:e84263d55307	795
AnnaBridge	167:e84263d55307	796	#define TPI_FIFO0_ETM1_Pos 8U /!< TPI FIFO0: ETM1 Position /
AnnaBridge	167:e84263d55307	797	#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /!< TPI FIFO0: ETM1 Mask /
AnnaBridge	167:e84263d55307	798
AnnaBridge	167:e84263d55307	799	#define TPI_FIFO0_ETM0_Pos 0U /!< TPI FIFO0: ETM0 Position /
AnnaBridge	167:e84263d55307	800	#define TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/) /!< TPI FIFO0: ETM0 Mask /
AnnaBridge	167:e84263d55307	801
AnnaBridge	167:e84263d55307	802	/* TPI ITATBCTR2 Register Definitions */
AnnaBridge	167:e84263d55307	803	#define TPI_ITATBCTR2_ATREADY_Pos 0U /!< TPI ITATBCTR2: ATREADY Position /
AnnaBridge	167:e84263d55307	804	#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY_Pos/) /!< TPI ITATBCTR2: ATREADY Mask /
AnnaBridge	167:e84263d55307	805
AnnaBridge	167:e84263d55307	806	/* TPI Integration ITM Data Register Definitions (FIFO1) */
AnnaBridge	167:e84263d55307	807	#define TPI_FIFO1_ITM_ATVALID_Pos 29U /!< TPI FIFO1: ITM_ATVALID Position /
AnnaBridge	167:e84263d55307	808	#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /!< TPI FIFO1: ITM_ATVALID Mask /
AnnaBridge	167:e84263d55307	809
AnnaBridge	167:e84263d55307	810	#define TPI_FIFO1_ITM_bytecount_Pos 27U /!< TPI FIFO1: ITM_bytecount Position /
AnnaBridge	167:e84263d55307	811	#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /!< TPI FIFO1: ITM_bytecount Mask /
AnnaBridge	167:e84263d55307	812
AnnaBridge	167:e84263d55307	813	#define TPI_FIFO1_ETM_ATVALID_Pos 26U /!< TPI FIFO1: ETM_ATVALID Position /
AnnaBridge	167:e84263d55307	814	#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /!< TPI FIFO1: ETM_ATVALID Mask /
AnnaBridge	167:e84263d55307	815
AnnaBridge	167:e84263d55307	816	#define TPI_FIFO1_ETM_bytecount_Pos 24U /!< TPI FIFO1: ETM_bytecount Position /
AnnaBridge	167:e84263d55307	817	#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /!< TPI FIFO1: ETM_bytecount Mask /
AnnaBridge	167:e84263d55307	818
AnnaBridge	167:e84263d55307	819	#define TPI_FIFO1_ITM2_Pos 16U /!< TPI FIFO1: ITM2 Position /
AnnaBridge	167:e84263d55307	820	#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /!< TPI FIFO1: ITM2 Mask /
AnnaBridge	167:e84263d55307	821
AnnaBridge	167:e84263d55307	822	#define TPI_FIFO1_ITM1_Pos 8U /!< TPI FIFO1: ITM1 Position /
AnnaBridge	167:e84263d55307	823	#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /!< TPI FIFO1: ITM1 Mask /
AnnaBridge	167:e84263d55307	824
AnnaBridge	167:e84263d55307	825	#define TPI_FIFO1_ITM0_Pos 0U /!< TPI FIFO1: ITM0 Position /
AnnaBridge	167:e84263d55307	826	#define TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/) /!< TPI FIFO1: ITM0 Mask /
AnnaBridge	167:e84263d55307	827
AnnaBridge	167:e84263d55307	828	/* TPI ITATBCTR0 Register Definitions */
AnnaBridge	167:e84263d55307	829	#define TPI_ITATBCTR0_ATREADY_Pos 0U /!< TPI ITATBCTR0: ATREADY Position /
AnnaBridge	167:e84263d55307	830	#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY_Pos/) /!< TPI ITATBCTR0: ATREADY Mask /
AnnaBridge	167:e84263d55307	831
AnnaBridge	167:e84263d55307	832	/* TPI Integration Mode Control Register Definitions */
AnnaBridge	167:e84263d55307	833	#define TPI_ITCTRL_Mode_Pos 0U /!< TPI ITCTRL: Mode Position /
AnnaBridge	167:e84263d55307	834	#define TPI_ITCTRL_Mode_Msk (0x1UL /<< TPI_ITCTRL_Mode_Pos/) /!< TPI ITCTRL: Mode Mask /
AnnaBridge	167:e84263d55307	835
AnnaBridge	167:e84263d55307	836	/* TPI DEVID Register Definitions */
AnnaBridge	167:e84263d55307	837	#define TPI_DEVID_NRZVALID_Pos 11U /!< TPI DEVID: NRZVALID Position /
AnnaBridge	167:e84263d55307	838	#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /!< TPI DEVID: NRZVALID Mask /
AnnaBridge	167:e84263d55307	839
AnnaBridge	167:e84263d55307	840	#define TPI_DEVID_MANCVALID_Pos 10U /!< TPI DEVID: MANCVALID Position /
AnnaBridge	167:e84263d55307	841	#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /!< TPI DEVID: MANCVALID Mask /
AnnaBridge	167:e84263d55307	842
AnnaBridge	167:e84263d55307	843	#define TPI_DEVID_PTINVALID_Pos 9U /!< TPI DEVID: PTINVALID Position /
AnnaBridge	167:e84263d55307	844	#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /!< TPI DEVID: PTINVALID Mask /
AnnaBridge	167:e84263d55307	845
AnnaBridge	167:e84263d55307	846	#define TPI_DEVID_MinBufSz_Pos 6U /!< TPI DEVID: MinBufSz Position /
AnnaBridge	167:e84263d55307	847	#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /!< TPI DEVID: MinBufSz Mask /
AnnaBridge	167:e84263d55307	848
AnnaBridge	167:e84263d55307	849	#define TPI_DEVID_AsynClkIn_Pos 5U /!< TPI DEVID: AsynClkIn Position /
AnnaBridge	167:e84263d55307	850	#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /!< TPI DEVID: AsynClkIn Mask /
AnnaBridge	167:e84263d55307	851
AnnaBridge	167:e84263d55307	852	#define TPI_DEVID_NrTraceInput_Pos 0U /!< TPI DEVID: NrTraceInput Position /
AnnaBridge	167:e84263d55307	853	#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/) /!< TPI DEVID: NrTraceInput Mask /
AnnaBridge	167:e84263d55307	854
AnnaBridge	167:e84263d55307	855	/* TPI DEVTYPE Register Definitions */
AnnaBridge	167:e84263d55307	856	#define TPI_DEVTYPE_MajorType_Pos 4U /!< TPI DEVTYPE: MajorType Position /
AnnaBridge	167:e84263d55307	857	#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /!< TPI DEVTYPE: MajorType Mask /
AnnaBridge	167:e84263d55307	858
AnnaBridge	167:e84263d55307	859	#define TPI_DEVTYPE_SubType_Pos 0U /!< TPI DEVTYPE: SubType Position /
AnnaBridge	167:e84263d55307	860	#define TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/) /!< TPI DEVTYPE: SubType Mask /
AnnaBridge	167:e84263d55307	861
AnnaBridge	167:e84263d55307	862	/@}/ /* end of group CMSIS_TPI */
AnnaBridge	167:e84263d55307	863
AnnaBridge	167:e84263d55307	864
AnnaBridge	167:e84263d55307	865	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge	167:e84263d55307	866	/**
AnnaBridge	167:e84263d55307	867	\ingroup CMSIS_core_register
AnnaBridge	167:e84263d55307	868	\defgroup CMSIS_MPU Memory Protection Unit (MPU)
AnnaBridge	167:e84263d55307	869	\brief Type definitions for the Memory Protection Unit (MPU)
AnnaBridge	167:e84263d55307	870	@{
AnnaBridge	167:e84263d55307	871	*/
AnnaBridge	167:e84263d55307	872
AnnaBridge	167:e84263d55307	873	/**
AnnaBridge	167:e84263d55307	874	\brief Structure type to access the Memory Protection Unit (MPU).
AnnaBridge	167:e84263d55307	875	*/
AnnaBridge	167:e84263d55307	876	typedef struct
AnnaBridge	167:e84263d55307	877	{
AnnaBridge	167:e84263d55307	878	__IM uint32_t TYPE; /!< Offset: 0x000 (R/ ) MPU Type Register /
AnnaBridge	167:e84263d55307	879	__IOM uint32_t CTRL; /!< Offset: 0x004 (R/W) MPU Control Register /
AnnaBridge	167:e84263d55307	880	__IOM uint32_t RNR; /!< Offset: 0x008 (R/W) MPU Region Number Register /
AnnaBridge	167:e84263d55307	881	__IOM uint32_t RBAR; /!< Offset: 0x00C (R/W) MPU Region Base Address Register /
AnnaBridge	167:e84263d55307	882	__IOM uint32_t RLAR; /!< Offset: 0x010 (R/W) MPU Region Limit Address Register /
AnnaBridge	167:e84263d55307	883	uint32_t RESERVED0[7U];
AnnaBridge	167:e84263d55307	884	__IOM uint32_t MAIR0; /!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 /
AnnaBridge	167:e84263d55307	885	__IOM uint32_t MAIR1; /!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 /
AnnaBridge	167:e84263d55307	886	} MPU_Type;
AnnaBridge	167:e84263d55307	887
AnnaBridge	167:e84263d55307	888	/* MPU Type Register Definitions */
AnnaBridge	167:e84263d55307	889	#define MPU_TYPE_IREGION_Pos 16U /!< MPU TYPE: IREGION Position /
AnnaBridge	167:e84263d55307	890	#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
AnnaBridge	167:e84263d55307	891
AnnaBridge	167:e84263d55307	892	#define MPU_TYPE_DREGION_Pos 8U /!< MPU TYPE: DREGION Position /
AnnaBridge	167:e84263d55307	893	#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
AnnaBridge	167:e84263d55307	894
AnnaBridge	167:e84263d55307	895	#define MPU_TYPE_SEPARATE_Pos 0U /!< MPU TYPE: SEPARATE Position /
AnnaBridge	167:e84263d55307	896	#define MPU_TYPE_SEPARATE_Msk (1UL /<< MPU_TYPE_SEPARATE_Pos/) /!< MPU TYPE: SEPARATE Mask /
AnnaBridge	167:e84263d55307	897
AnnaBridge	167:e84263d55307	898	/* MPU Control Register Definitions */
AnnaBridge	167:e84263d55307	899	#define MPU_CTRL_PRIVDEFENA_Pos 2U /!< MPU CTRL: PRIVDEFENA Position /
AnnaBridge	167:e84263d55307	900	#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
AnnaBridge	167:e84263d55307	901
AnnaBridge	167:e84263d55307	902	#define MPU_CTRL_HFNMIENA_Pos 1U /!< MPU CTRL: HFNMIENA Position /
AnnaBridge	167:e84263d55307	903	#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
AnnaBridge	167:e84263d55307	904
AnnaBridge	167:e84263d55307	905	#define MPU_CTRL_ENABLE_Pos 0U /!< MPU CTRL: ENABLE Position /
AnnaBridge	167:e84263d55307	906	#define MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/) /!< MPU CTRL: ENABLE Mask /
AnnaBridge	167:e84263d55307	907
AnnaBridge	167:e84263d55307	908	/* MPU Region Number Register Definitions */
AnnaBridge	167:e84263d55307	909	#define MPU_RNR_REGION_Pos 0U /!< MPU RNR: REGION Position /
AnnaBridge	167:e84263d55307	910	#define MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/) /!< MPU RNR: REGION Mask /
AnnaBridge	167:e84263d55307	911
AnnaBridge	167:e84263d55307	912	/* MPU Region Base Address Register Definitions */
AnnaBridge	167:e84263d55307	913	#define MPU_RBAR_BASE_Pos 5U /!< MPU RBAR: BASE Position /
AnnaBridge	167:e84263d55307	914	#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /!< MPU RBAR: BASE Mask /
AnnaBridge	167:e84263d55307	915
AnnaBridge	167:e84263d55307	916	#define MPU_RBAR_SH_Pos 3U /!< MPU RBAR: SH Position /
AnnaBridge	167:e84263d55307	917	#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /!< MPU RBAR: SH Mask /
AnnaBridge	167:e84263d55307	918
AnnaBridge	167:e84263d55307	919	#define MPU_RBAR_AP_Pos 1U /!< MPU RBAR: AP Position /
AnnaBridge	167:e84263d55307	920	#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /!< MPU RBAR: AP Mask /
AnnaBridge	167:e84263d55307	921
AnnaBridge	167:e84263d55307	922	#define MPU_RBAR_XN_Pos 0U /!< MPU RBAR: XN Position /
AnnaBridge	167:e84263d55307	923	#define MPU_RBAR_XN_Msk (01UL /<< MPU_RBAR_XN_Pos/) /!< MPU RBAR: XN Mask /
AnnaBridge	167:e84263d55307	924
AnnaBridge	167:e84263d55307	925	/* MPU Region Limit Address Register Definitions */
AnnaBridge	167:e84263d55307	926	#define MPU_RLAR_LIMIT_Pos 5U /!< MPU RLAR: LIMIT Position /
AnnaBridge	167:e84263d55307	927	#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /!< MPU RLAR: LIMIT Mask /
AnnaBridge	167:e84263d55307	928
AnnaBridge	167:e84263d55307	929	#define MPU_RLAR_AttrIndx_Pos 1U /!< MPU RLAR: AttrIndx Position /
AnnaBridge	167:e84263d55307	930	#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /!< MPU RLAR: AttrIndx Mask /
AnnaBridge	167:e84263d55307	931
AnnaBridge	167:e84263d55307	932	#define MPU_RLAR_EN_Pos 0U /!< MPU RLAR: EN Position /
AnnaBridge	167:e84263d55307	933	#define MPU_RLAR_EN_Msk (1UL /<< MPU_RLAR_EN_Pos/) /!< MPU RLAR: EN Mask /
AnnaBridge	167:e84263d55307	934
AnnaBridge	167:e84263d55307	935	/* MPU Memory Attribute Indirection Register 0 Definitions */
AnnaBridge	167:e84263d55307	936	#define MPU_MAIR0_Attr3_Pos 24U /!< MPU MAIR0: Attr3 Position /
AnnaBridge	167:e84263d55307	937	#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /!< MPU MAIR0: Attr3 Mask /
AnnaBridge	167:e84263d55307	938
AnnaBridge	167:e84263d55307	939	#define MPU_MAIR0_Attr2_Pos 16U /!< MPU MAIR0: Attr2 Position /
AnnaBridge	167:e84263d55307	940	#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /!< MPU MAIR0: Attr2 Mask /
AnnaBridge	167:e84263d55307	941
AnnaBridge	167:e84263d55307	942	#define MPU_MAIR0_Attr1_Pos 8U /!< MPU MAIR0: Attr1 Position /
AnnaBridge	167:e84263d55307	943	#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /!< MPU MAIR0: Attr1 Mask /
AnnaBridge	167:e84263d55307	944
AnnaBridge	167:e84263d55307	945	#define MPU_MAIR0_Attr0_Pos 0U /!< MPU MAIR0: Attr0 Position /
AnnaBridge	167:e84263d55307	946	#define MPU_MAIR0_Attr0_Msk (0xFFUL /<< MPU_MAIR0_Attr0_Pos/) /!< MPU MAIR0: Attr0 Mask /
AnnaBridge	167:e84263d55307	947
AnnaBridge	167:e84263d55307	948	/* MPU Memory Attribute Indirection Register 1 Definitions */
AnnaBridge	167:e84263d55307	949	#define MPU_MAIR1_Attr7_Pos 24U /!< MPU MAIR1: Attr7 Position /
AnnaBridge	167:e84263d55307	950	#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /!< MPU MAIR1: Attr7 Mask /
AnnaBridge	167:e84263d55307	951
AnnaBridge	167:e84263d55307	952	#define MPU_MAIR1_Attr6_Pos 16U /!< MPU MAIR1: Attr6 Position /
AnnaBridge	167:e84263d55307	953	#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /!< MPU MAIR1: Attr6 Mask /
AnnaBridge	167:e84263d55307	954
AnnaBridge	167:e84263d55307	955	#define MPU_MAIR1_Attr5_Pos 8U /!< MPU MAIR1: Attr5 Position /
AnnaBridge	167:e84263d55307	956	#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /!< MPU MAIR1: Attr5 Mask /
AnnaBridge	167:e84263d55307	957
AnnaBridge	167:e84263d55307	958	#define MPU_MAIR1_Attr4_Pos 0U /!< MPU MAIR1: Attr4 Position /
AnnaBridge	167:e84263d55307	959	#define MPU_MAIR1_Attr4_Msk (0xFFUL /<< MPU_MAIR1_Attr4_Pos/) /!< MPU MAIR1: Attr4 Mask /
AnnaBridge	167:e84263d55307	960
AnnaBridge	167:e84263d55307	961	/@} end of group CMSIS_MPU /
AnnaBridge	167:e84263d55307	962	#endif
AnnaBridge	167:e84263d55307	963
AnnaBridge	167:e84263d55307	964
AnnaBridge	167:e84263d55307	965	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge	167:e84263d55307	966	/**
AnnaBridge	167:e84263d55307	967	\ingroup CMSIS_core_register
AnnaBridge	167:e84263d55307	968	\defgroup CMSIS_SAU Security Attribution Unit (SAU)
AnnaBridge	167:e84263d55307	969	\brief Type definitions for the Security Attribution Unit (SAU)
AnnaBridge	167:e84263d55307	970	@{
AnnaBridge	167:e84263d55307	971	*/
AnnaBridge	167:e84263d55307	972
AnnaBridge	167:e84263d55307	973	/**
AnnaBridge	167:e84263d55307	974	\brief Structure type to access the Security Attribution Unit (SAU).
AnnaBridge	167:e84263d55307	975	*/
AnnaBridge	167:e84263d55307	976	typedef struct
AnnaBridge	167:e84263d55307	977	{
AnnaBridge	167:e84263d55307	978	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) SAU Control Register /
AnnaBridge	167:e84263d55307	979	__IM uint32_t TYPE; /!< Offset: 0x004 (R/ ) SAU Type Register /
AnnaBridge	167:e84263d55307	980	#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
AnnaBridge	167:e84263d55307	981	__IOM uint32_t RNR; /!< Offset: 0x008 (R/W) SAU Region Number Register /
AnnaBridge	167:e84263d55307	982	__IOM uint32_t RBAR; /!< Offset: 0x00C (R/W) SAU Region Base Address Register /
AnnaBridge	167:e84263d55307	983	__IOM uint32_t RLAR; /!< Offset: 0x010 (R/W) SAU Region Limit Address Register /
AnnaBridge	167:e84263d55307	984	#endif
AnnaBridge	167:e84263d55307	985	} SAU_Type;
AnnaBridge	167:e84263d55307	986
AnnaBridge	167:e84263d55307	987	/* SAU Control Register Definitions */
AnnaBridge	167:e84263d55307	988	#define SAU_CTRL_ALLNS_Pos 1U /!< SAU CTRL: ALLNS Position /
AnnaBridge	167:e84263d55307	989	#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /!< SAU CTRL: ALLNS Mask /
AnnaBridge	167:e84263d55307	990
AnnaBridge	167:e84263d55307	991	#define SAU_CTRL_ENABLE_Pos 0U /!< SAU CTRL: ENABLE Position /
AnnaBridge	167:e84263d55307	992	#define SAU_CTRL_ENABLE_Msk (1UL /<< SAU_CTRL_ENABLE_Pos/) /!< SAU CTRL: ENABLE Mask /
AnnaBridge	167:e84263d55307	993
AnnaBridge	167:e84263d55307	994	/* SAU Type Register Definitions */
AnnaBridge	167:e84263d55307	995	#define SAU_TYPE_SREGION_Pos 0U /!< SAU TYPE: SREGION Position /
AnnaBridge	167:e84263d55307	996	#define SAU_TYPE_SREGION_Msk (0xFFUL /<< SAU_TYPE_SREGION_Pos/) /!< SAU TYPE: SREGION Mask /
AnnaBridge	167:e84263d55307	997
AnnaBridge	167:e84263d55307	998	#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
AnnaBridge	167:e84263d55307	999	/* SAU Region Number Register Definitions */
AnnaBridge	167:e84263d55307	1000	#define SAU_RNR_REGION_Pos 0U /!< SAU RNR: REGION Position /
AnnaBridge	167:e84263d55307	1001	#define SAU_RNR_REGION_Msk (0xFFUL /<< SAU_RNR_REGION_Pos/) /!< SAU RNR: REGION Mask /
AnnaBridge	167:e84263d55307	1002
AnnaBridge	167:e84263d55307	1003	/* SAU Region Base Address Register Definitions */
AnnaBridge	167:e84263d55307	1004	#define SAU_RBAR_BADDR_Pos 5U /!< SAU RBAR: BADDR Position /
AnnaBridge	167:e84263d55307	1005	#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /!< SAU RBAR: BADDR Mask /
AnnaBridge	167:e84263d55307	1006
AnnaBridge	167:e84263d55307	1007	/* SAU Region Limit Address Register Definitions */
AnnaBridge	167:e84263d55307	1008	#define SAU_RLAR_LADDR_Pos 5U /!< SAU RLAR: LADDR Position /
AnnaBridge	167:e84263d55307	1009	#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /!< SAU RLAR: LADDR Mask /
AnnaBridge	167:e84263d55307	1010
AnnaBridge	167:e84263d55307	1011	#define SAU_RLAR_NSC_Pos 1U /!< SAU RLAR: NSC Position /
AnnaBridge	167:e84263d55307	1012	#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /!< SAU RLAR: NSC Mask /
AnnaBridge	167:e84263d55307	1013
AnnaBridge	167:e84263d55307	1014	#define SAU_RLAR_ENABLE_Pos 0U /!< SAU RLAR: ENABLE Position /
AnnaBridge	167:e84263d55307	1015	#define SAU_RLAR_ENABLE_Msk (1UL /<< SAU_RLAR_ENABLE_Pos/) /!< SAU RLAR: ENABLE Mask /
AnnaBridge	167:e84263d55307	1016
AnnaBridge	167:e84263d55307	1017	#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
AnnaBridge	167:e84263d55307	1018
AnnaBridge	167:e84263d55307	1019	/@} end of group CMSIS_SAU /
AnnaBridge	167:e84263d55307	1020	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
AnnaBridge	167:e84263d55307	1021
AnnaBridge	167:e84263d55307	1022
AnnaBridge	167:e84263d55307	1023	/**
AnnaBridge	167:e84263d55307	1024	\ingroup CMSIS_core_register
AnnaBridge	167:e84263d55307	1025	\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
AnnaBridge	167:e84263d55307	1026	\brief Type definitions for the Core Debug Registers
AnnaBridge	167:e84263d55307	1027	@{
AnnaBridge	167:e84263d55307	1028	*/
AnnaBridge	167:e84263d55307	1029
AnnaBridge	167:e84263d55307	1030	/**
AnnaBridge	167:e84263d55307	1031	\brief Structure type to access the Core Debug Register (CoreDebug).
AnnaBridge	167:e84263d55307	1032	*/
AnnaBridge	167:e84263d55307	1033	typedef struct
AnnaBridge	167:e84263d55307	1034	{
AnnaBridge	167:e84263d55307	1035	__IOM uint32_t DHCSR; /!< Offset: 0x000 (R/W) Debug Halting Control and Status Register /
AnnaBridge	167:e84263d55307	1036	__OM uint32_t DCRSR; /!< Offset: 0x004 ( /W) Debug Core Register Selector Register /
AnnaBridge	167:e84263d55307	1037	__IOM uint32_t DCRDR; /!< Offset: 0x008 (R/W) Debug Core Register Data Register /
AnnaBridge	167:e84263d55307	1038	__IOM uint32_t DEMCR; /!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register /
AnnaBridge	167:e84263d55307	1039	uint32_t RESERVED4[1U];
AnnaBridge	167:e84263d55307	1040	__IOM uint32_t DAUTHCTRL; /!< Offset: 0x014 (R/W) Debug Authentication Control Register /
AnnaBridge	167:e84263d55307	1041	__IOM uint32_t DSCSR; /!< Offset: 0x018 (R/W) Debug Security Control and Status Register /
AnnaBridge	167:e84263d55307	1042	} CoreDebug_Type;
AnnaBridge	167:e84263d55307	1043
AnnaBridge	167:e84263d55307	1044	/* Debug Halting Control and Status Register Definitions */
AnnaBridge	167:e84263d55307	1045	#define CoreDebug_DHCSR_DBGKEY_Pos 16U /!< CoreDebug DHCSR: DBGKEY Position /
AnnaBridge	167:e84263d55307	1046	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
AnnaBridge	167:e84263d55307	1047
AnnaBridge	167:e84263d55307	1048	#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /!< CoreDebug DHCSR: S_RESTART_ST Position /
AnnaBridge	167:e84263d55307	1049	#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /!< CoreDebug DHCSR: S_RESTART_ST Mask /
AnnaBridge	167:e84263d55307	1050
AnnaBridge	167:e84263d55307	1051	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /!< CoreDebug DHCSR: S_RESET_ST Position /
AnnaBridge	167:e84263d55307	1052	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
AnnaBridge	167:e84263d55307	1053
AnnaBridge	167:e84263d55307	1054	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /!< CoreDebug DHCSR: S_RETIRE_ST Position /
AnnaBridge	167:e84263d55307	1055	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
AnnaBridge	167:e84263d55307	1056
AnnaBridge	167:e84263d55307	1057	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /!< CoreDebug DHCSR: S_LOCKUP Position /
AnnaBridge	167:e84263d55307	1058	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
AnnaBridge	167:e84263d55307	1059
AnnaBridge	167:e84263d55307	1060	#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /!< CoreDebug DHCSR: S_SLEEP Position /
AnnaBridge	167:e84263d55307	1061	#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
AnnaBridge	167:e84263d55307	1062
AnnaBridge	167:e84263d55307	1063	#define CoreDebug_DHCSR_S_HALT_Pos 17U /!< CoreDebug DHCSR: S_HALT Position /
AnnaBridge	167:e84263d55307	1064	#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
AnnaBridge	167:e84263d55307	1065
AnnaBridge	167:e84263d55307	1066	#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /!< CoreDebug DHCSR: S_REGRDY Position /
AnnaBridge	167:e84263d55307	1067	#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
AnnaBridge	167:e84263d55307	1068
AnnaBridge	167:e84263d55307	1069	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /!< CoreDebug DHCSR: C_MASKINTS Position /
AnnaBridge	167:e84263d55307	1070	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
AnnaBridge	167:e84263d55307	1071
AnnaBridge	167:e84263d55307	1072	#define CoreDebug_DHCSR_C_STEP_Pos 2U /!< CoreDebug DHCSR: C_STEP Position /
AnnaBridge	167:e84263d55307	1073	#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
AnnaBridge	167:e84263d55307	1074
AnnaBridge	167:e84263d55307	1075	#define CoreDebug_DHCSR_C_HALT_Pos 1U /!< CoreDebug DHCSR: C_HALT Position /
AnnaBridge	167:e84263d55307	1076	#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
AnnaBridge	167:e84263d55307	1077
AnnaBridge	167:e84263d55307	1078	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /!< CoreDebug DHCSR: C_DEBUGEN Position /
AnnaBridge	167:e84263d55307	1079	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
AnnaBridge	167:e84263d55307	1080
AnnaBridge	167:e84263d55307	1081	/* Debug Core Register Selector Register Definitions */
AnnaBridge	167:e84263d55307	1082	#define CoreDebug_DCRSR_REGWnR_Pos 16U /!< CoreDebug DCRSR: REGWnR Position /
AnnaBridge	167:e84263d55307	1083	#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
AnnaBridge	167:e84263d55307	1084
AnnaBridge	167:e84263d55307	1085	#define CoreDebug_DCRSR_REGSEL_Pos 0U /!< CoreDebug DCRSR: REGSEL Position /
AnnaBridge	167:e84263d55307	1086	#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/) /!< CoreDebug DCRSR: REGSEL Mask /
AnnaBridge	167:e84263d55307	1087
AnnaBridge	167:e84263d55307	1088	/* Debug Exception and Monitor Control Register */
AnnaBridge	167:e84263d55307	1089	#define CoreDebug_DEMCR_DWTENA_Pos 24U /!< CoreDebug DEMCR: DWTENA Position /
AnnaBridge	167:e84263d55307	1090	#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /!< CoreDebug DEMCR: DWTENA Mask /
AnnaBridge	167:e84263d55307	1091
AnnaBridge	167:e84263d55307	1092	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /!< CoreDebug DEMCR: VC_HARDERR Position /
AnnaBridge	167:e84263d55307	1093	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
AnnaBridge	167:e84263d55307	1094
AnnaBridge	167:e84263d55307	1095	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /!< CoreDebug DEMCR: VC_CORERESET Position /
AnnaBridge	167:e84263d55307	1096	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/) /!< CoreDebug DEMCR: VC_CORERESET Mask /
AnnaBridge	167:e84263d55307	1097
AnnaBridge	167:e84263d55307	1098	/* Debug Authentication Control Register Definitions */
AnnaBridge	167:e84263d55307	1099	#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position /
AnnaBridge	167:e84263d55307	1100	#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask /
AnnaBridge	167:e84263d55307	1101
AnnaBridge	167:e84263d55307	1102	#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /!< CoreDebug DAUTHCTRL: SPNIDENSEL Position /
AnnaBridge	167:e84263d55307	1103	#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask /
AnnaBridge	167:e84263d55307	1104
AnnaBridge	167:e84263d55307	1105	#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /!< CoreDebug DAUTHCTRL: INTSPIDEN Position /
AnnaBridge	167:e84263d55307	1106	#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /!< CoreDebug DAUTHCTRL: INTSPIDEN Mask /
AnnaBridge	167:e84263d55307	1107
AnnaBridge	167:e84263d55307	1108	#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /!< CoreDebug DAUTHCTRL: SPIDENSEL Position /
AnnaBridge	167:e84263d55307	1109	#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos/) /!< CoreDebug DAUTHCTRL: SPIDENSEL Mask /
AnnaBridge	167:e84263d55307	1110
AnnaBridge	167:e84263d55307	1111	/* Debug Security Control and Status Register Definitions */
AnnaBridge	167:e84263d55307	1112	#define CoreDebug_DSCSR_CDS_Pos 16U /!< CoreDebug DSCSR: CDS Position /
AnnaBridge	167:e84263d55307	1113	#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /!< CoreDebug DSCSR: CDS Mask /
AnnaBridge	167:e84263d55307	1114
AnnaBridge	167:e84263d55307	1115	#define CoreDebug_DSCSR_SBRSEL_Pos 1U /!< CoreDebug DSCSR: SBRSEL Position /
AnnaBridge	167:e84263d55307	1116	#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /!< CoreDebug DSCSR: SBRSEL Mask /
AnnaBridge	167:e84263d55307	1117
AnnaBridge	167:e84263d55307	1118	#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /!< CoreDebug DSCSR: SBRSELEN Position /
AnnaBridge	167:e84263d55307	1119	#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /<< CoreDebug_DSCSR_SBRSELEN_Pos/) /!< CoreDebug DSCSR: SBRSELEN Mask /
AnnaBridge	167:e84263d55307	1120
AnnaBridge	167:e84263d55307	1121	/@} end of group CMSIS_CoreDebug /
AnnaBridge	167:e84263d55307	1122
AnnaBridge	167:e84263d55307	1123
AnnaBridge	167:e84263d55307	1124	/**
AnnaBridge	167:e84263d55307	1125	\ingroup CMSIS_core_register
AnnaBridge	167:e84263d55307	1126	\defgroup CMSIS_core_bitfield Core register bit field macros
AnnaBridge	167:e84263d55307	1127	\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
AnnaBridge	167:e84263d55307	1128	@{
AnnaBridge	167:e84263d55307	1129	*/
AnnaBridge	167:e84263d55307	1130
AnnaBridge	167:e84263d55307	1131	/**
AnnaBridge	167:e84263d55307	1132	\brief Mask and shift a bit field value for use in a register bit range.
AnnaBridge	167:e84263d55307	1133	\param[in] field Name of the register bit field.
AnnaBridge	167:e84263d55307	1134	\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
AnnaBridge	167:e84263d55307	1135	\return Masked and shifted value.
AnnaBridge	167:e84263d55307	1136	*/
AnnaBridge	167:e84263d55307	1137	#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
AnnaBridge	167:e84263d55307	1138
AnnaBridge	167:e84263d55307	1139	/**
AnnaBridge	167:e84263d55307	1140	\brief Mask and shift a register value to extract a bit filed value.
AnnaBridge	167:e84263d55307	1141	\param[in] field Name of the register bit field.
AnnaBridge	167:e84263d55307	1142	\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
AnnaBridge	167:e84263d55307	1143	\return Masked and shifted bit field value.
AnnaBridge	167:e84263d55307	1144	*/
AnnaBridge	167:e84263d55307	1145	#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
AnnaBridge	167:e84263d55307	1146
AnnaBridge	167:e84263d55307	1147	/@} end of group CMSIS_core_bitfield /
AnnaBridge	167:e84263d55307	1148
AnnaBridge	167:e84263d55307	1149
AnnaBridge	167:e84263d55307	1150	/**
AnnaBridge	167:e84263d55307	1151	\ingroup CMSIS_core_register
AnnaBridge	167:e84263d55307	1152	\defgroup CMSIS_core_base Core Definitions
AnnaBridge	167:e84263d55307	1153	\brief Definitions for base addresses, unions, and structures.
AnnaBridge	167:e84263d55307	1154	@{
AnnaBridge	167:e84263d55307	1155	*/
AnnaBridge	167:e84263d55307	1156
AnnaBridge	167:e84263d55307	1157	/* Memory mapping of Core Hardware */
AnnaBridge	167:e84263d55307	1158	#define SCS_BASE (0xE000E000UL) /!< System Control Space Base Address /
AnnaBridge	167:e84263d55307	1159	#define DWT_BASE (0xE0001000UL) /!< DWT Base Address /
AnnaBridge	167:e84263d55307	1160	#define TPI_BASE (0xE0040000UL) /!< TPI Base Address /
AnnaBridge	167:e84263d55307	1161	#define CoreDebug_BASE (0xE000EDF0UL) /!< Core Debug Base Address /
AnnaBridge	167:e84263d55307	1162	#define SysTick_BASE (SCS_BASE + 0x0010UL) /!< SysTick Base Address /
AnnaBridge	167:e84263d55307	1163	#define NVIC_BASE (SCS_BASE + 0x0100UL) /!< NVIC Base Address /
AnnaBridge	167:e84263d55307	1164	#define SCB_BASE (SCS_BASE + 0x0D00UL) /!< System Control Block Base Address /
AnnaBridge	167:e84263d55307	1165
AnnaBridge	167:e84263d55307	1166
AnnaBridge	167:e84263d55307	1167	#define SCB ((SCB_Type ) SCB_BASE ) /!< SCB configuration struct */
AnnaBridge	167:e84263d55307	1168	#define SysTick ((SysTick_Type ) SysTick_BASE ) /!< SysTick configuration struct */
AnnaBridge	167:e84263d55307	1169	#define NVIC ((NVIC_Type ) NVIC_BASE ) /!< NVIC configuration struct */
AnnaBridge	167:e84263d55307	1170	#define DWT ((DWT_Type ) DWT_BASE ) /!< DWT configuration struct */
AnnaBridge	167:e84263d55307	1171	#define TPI ((TPI_Type ) TPI_BASE ) /!< TPI configuration struct */
AnnaBridge	167:e84263d55307	1172	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE ) /!< Core Debug configuration struct */
AnnaBridge	167:e84263d55307	1173
AnnaBridge	167:e84263d55307	1174	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge	167:e84263d55307	1175	#define MPU_BASE (SCS_BASE + 0x0D90UL) /!< Memory Protection Unit /
AnnaBridge	167:e84263d55307	1176	#define MPU ((MPU_Type ) MPU_BASE ) /!< Memory Protection Unit */
AnnaBridge	167:e84263d55307	1177	#endif
AnnaBridge	167:e84263d55307	1178
AnnaBridge	167:e84263d55307	1179	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge	167:e84263d55307	1180	#define SAU_BASE (SCS_BASE + 0x0DD0UL) /!< Security Attribution Unit /
AnnaBridge	167:e84263d55307	1181	#define SAU ((SAU_Type ) SAU_BASE ) /!< Security Attribution Unit */
AnnaBridge	167:e84263d55307	1182	#endif
AnnaBridge	167:e84263d55307	1183
AnnaBridge	167:e84263d55307	1184	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge	167:e84263d55307	1185	#define SCS_BASE_NS (0xE002E000UL) /!< System Control Space Base Address (non-secure address space) /
AnnaBridge	167:e84263d55307	1186	#define CoreDebug_BASE_NS (0xE002EDF0UL) /!< Core Debug Base Address (non-secure address space) /
AnnaBridge	167:e84263d55307	1187	#define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /!< SysTick Base Address (non-secure address space) /
AnnaBridge	167:e84263d55307	1188	#define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /!< NVIC Base Address (non-secure address space) /
AnnaBridge	167:e84263d55307	1189	#define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /!< System Control Block Base Address (non-secure address space) /
AnnaBridge	167:e84263d55307	1190
AnnaBridge	167:e84263d55307	1191	#define SCB_NS ((SCB_Type ) SCB_BASE_NS ) /!< SCB configuration struct (non-secure address space) */
AnnaBridge	167:e84263d55307	1192	#define SysTick_NS ((SysTick_Type ) SysTick_BASE_NS ) /!< SysTick configuration struct (non-secure address space) */
AnnaBridge	167:e84263d55307	1193	#define NVIC_NS ((NVIC_Type ) NVIC_BASE_NS ) /!< NVIC configuration struct (non-secure address space) */
AnnaBridge	167:e84263d55307	1194	#define CoreDebug_NS ((CoreDebug_Type ) CoreDebug_BASE_NS) /!< Core Debug configuration struct (non-secure address space) */
AnnaBridge	167:e84263d55307	1195
AnnaBridge	167:e84263d55307	1196	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge	167:e84263d55307	1197	#define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /!< Memory Protection Unit (non-secure address space) /
AnnaBridge	167:e84263d55307	1198	#define MPU_NS ((MPU_Type ) MPU_BASE_NS ) /!< Memory Protection Unit (non-secure address space) */
AnnaBridge	167:e84263d55307	1199	#endif
AnnaBridge	167:e84263d55307	1200
AnnaBridge	167:e84263d55307	1201	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
AnnaBridge	167:e84263d55307	1202	/@} /
AnnaBridge	167:e84263d55307	1203
AnnaBridge	167:e84263d55307	1204
AnnaBridge	167:e84263d55307	1205
AnnaBridge	167:e84263d55307	1206	/*******************************************************************************
AnnaBridge	167:e84263d55307	1207	* Hardware Abstraction Layer
AnnaBridge	167:e84263d55307	1208	Core Function Interface contains:
AnnaBridge	167:e84263d55307	1209	- Core NVIC Functions
AnnaBridge	167:e84263d55307	1210	- Core SysTick Functions
AnnaBridge	167:e84263d55307	1211	- Core Register Access Functions
AnnaBridge	167:e84263d55307	1212	******************************************************************************/
AnnaBridge	167:e84263d55307	1213	/**
AnnaBridge	167:e84263d55307	1214	\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
AnnaBridge	167:e84263d55307	1215	*/
AnnaBridge	167:e84263d55307	1216
AnnaBridge	167:e84263d55307	1217
AnnaBridge	167:e84263d55307	1218
AnnaBridge	167:e84263d55307	1219	/* ########################## NVIC functions #################################### */
AnnaBridge	167:e84263d55307	1220	/**
AnnaBridge	167:e84263d55307	1221	\ingroup CMSIS_Core_FunctionInterface
AnnaBridge	167:e84263d55307	1222	\defgroup CMSIS_Core_NVICFunctions NVIC Functions
AnnaBridge	167:e84263d55307	1223	\brief Functions that manage interrupts and exceptions via the NVIC.
AnnaBridge	167:e84263d55307	1224	@{
AnnaBridge	167:e84263d55307	1225	*/
AnnaBridge	167:e84263d55307	1226
AnnaBridge	167:e84263d55307	1227	#ifdef CMSIS_NVIC_VIRTUAL
AnnaBridge	167:e84263d55307	1228	#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge	167:e84263d55307	1229	#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
AnnaBridge	167:e84263d55307	1230	#endif
AnnaBridge	167:e84263d55307	1231	#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge	167:e84263d55307	1232	#else
AnnaBridge	167:e84263d55307	1233	/#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 /
AnnaBridge	167:e84263d55307	1234	/#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 /
AnnaBridge	167:e84263d55307	1235	#define NVIC_EnableIRQ __NVIC_EnableIRQ
AnnaBridge	167:e84263d55307	1236	#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
AnnaBridge	167:e84263d55307	1237	#define NVIC_DisableIRQ __NVIC_DisableIRQ
AnnaBridge	167:e84263d55307	1238	#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
AnnaBridge	167:e84263d55307	1239	#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
AnnaBridge	167:e84263d55307	1240	#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
AnnaBridge	167:e84263d55307	1241	#define NVIC_GetActive __NVIC_GetActive
AnnaBridge	167:e84263d55307	1242	#define NVIC_SetPriority __NVIC_SetPriority
AnnaBridge	167:e84263d55307	1243	#define NVIC_GetPriority __NVIC_GetPriority
AnnaBridge	167:e84263d55307	1244	#define NVIC_SystemReset __NVIC_SystemReset
AnnaBridge	167:e84263d55307	1245	#endif /* CMSIS_NVIC_VIRTUAL */
AnnaBridge	167:e84263d55307	1246
AnnaBridge	167:e84263d55307	1247	#ifdef CMSIS_VECTAB_VIRTUAL
AnnaBridge	167:e84263d55307	1248	#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge	167:e84263d55307	1249	#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
AnnaBridge	167:e84263d55307	1250	#endif
AnnaBridge	167:e84263d55307	1251	#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge	167:e84263d55307	1252	#else
AnnaBridge	167:e84263d55307	1253	#define NVIC_SetVector __NVIC_SetVector
AnnaBridge	167:e84263d55307	1254	#define NVIC_GetVector __NVIC_GetVector
AnnaBridge	167:e84263d55307	1255	#endif /* (CMSIS_VECTAB_VIRTUAL) */
AnnaBridge	167:e84263d55307	1256
AnnaBridge	167:e84263d55307	1257	#define NVIC_USER_IRQ_OFFSET 16
AnnaBridge	167:e84263d55307	1258
AnnaBridge	167:e84263d55307	1259
AnnaBridge	167:e84263d55307	1260	/* Interrupt Priorities are WORD accessible only under ARMv6M */
AnnaBridge	167:e84263d55307	1261	/* The following MACROS handle generation of the register offset and byte masks */
AnnaBridge	167:e84263d55307	1262	#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
AnnaBridge	167:e84263d55307	1263	#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
AnnaBridge	167:e84263d55307	1264	#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
AnnaBridge	167:e84263d55307	1265
AnnaBridge	167:e84263d55307	1266
AnnaBridge	167:e84263d55307	1267	/**
AnnaBridge	167:e84263d55307	1268	\brief Enable Interrupt
AnnaBridge	167:e84263d55307	1269	\details Enables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge	167:e84263d55307	1270	\param [in] IRQn Device specific interrupt number.
AnnaBridge	167:e84263d55307	1271	\note IRQn must not be negative.
AnnaBridge	167:e84263d55307	1272	*/
AnnaBridge	167:e84263d55307	1273	__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
AnnaBridge	167:e84263d55307	1274	{
AnnaBridge	167:e84263d55307	1275	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:e84263d55307	1276	{
AnnaBridge	167:e84263d55307	1277	NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge	167:e84263d55307	1278	}
AnnaBridge	167:e84263d55307	1279	}
AnnaBridge	167:e84263d55307	1280
AnnaBridge	167:e84263d55307	1281
AnnaBridge	167:e84263d55307	1282	/**
AnnaBridge	167:e84263d55307	1283	\brief Get Interrupt Enable status
AnnaBridge	167:e84263d55307	1284	\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
AnnaBridge	167:e84263d55307	1285	\param [in] IRQn Device specific interrupt number.
AnnaBridge	167:e84263d55307	1286	\return 0 Interrupt is not enabled.
AnnaBridge	167:e84263d55307	1287	\return 1 Interrupt is enabled.
AnnaBridge	167:e84263d55307	1288	\note IRQn must not be negative.
AnnaBridge	167:e84263d55307	1289	*/
AnnaBridge	167:e84263d55307	1290	__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
AnnaBridge	167:e84263d55307	1291	{
AnnaBridge	167:e84263d55307	1292	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:e84263d55307	1293	{
AnnaBridge	167:e84263d55307	1294	return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	167:e84263d55307	1295	}
AnnaBridge	167:e84263d55307	1296	else
AnnaBridge	167:e84263d55307	1297	{
AnnaBridge	167:e84263d55307	1298	return(0U);
AnnaBridge	167:e84263d55307	1299	}
AnnaBridge	167:e84263d55307	1300	}
AnnaBridge	167:e84263d55307	1301
AnnaBridge	167:e84263d55307	1302
AnnaBridge	167:e84263d55307	1303	/**
AnnaBridge	167:e84263d55307	1304	\brief Disable Interrupt
AnnaBridge	167:e84263d55307	1305	\details Disables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge	167:e84263d55307	1306	\param [in] IRQn Device specific interrupt number.
AnnaBridge	167:e84263d55307	1307	\note IRQn must not be negative.
AnnaBridge	167:e84263d55307	1308	*/
AnnaBridge	167:e84263d55307	1309	__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
AnnaBridge	167:e84263d55307	1310	{
AnnaBridge	167:e84263d55307	1311	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:e84263d55307	1312	{
AnnaBridge	167:e84263d55307	1313	NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge	167:e84263d55307	1314	__DSB();
AnnaBridge	167:e84263d55307	1315	__ISB();
AnnaBridge	167:e84263d55307	1316	}
AnnaBridge	167:e84263d55307	1317	}
AnnaBridge	167:e84263d55307	1318
AnnaBridge	167:e84263d55307	1319
AnnaBridge	167:e84263d55307	1320	/**
AnnaBridge	167:e84263d55307	1321	\brief Get Pending Interrupt
AnnaBridge	167:e84263d55307	1322	\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
AnnaBridge	167:e84263d55307	1323	\param [in] IRQn Device specific interrupt number.
AnnaBridge	167:e84263d55307	1324	\return 0 Interrupt status is not pending.
AnnaBridge	167:e84263d55307	1325	\return 1 Interrupt status is pending.
AnnaBridge	167:e84263d55307	1326	\note IRQn must not be negative.
AnnaBridge	167:e84263d55307	1327	*/
AnnaBridge	167:e84263d55307	1328	__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
AnnaBridge	167:e84263d55307	1329	{
AnnaBridge	167:e84263d55307	1330	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:e84263d55307	1331	{
AnnaBridge	167:e84263d55307	1332	return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	167:e84263d55307	1333	}
AnnaBridge	167:e84263d55307	1334	else
AnnaBridge	167:e84263d55307	1335	{
AnnaBridge	167:e84263d55307	1336	return(0U);
AnnaBridge	167:e84263d55307	1337	}
AnnaBridge	167:e84263d55307	1338	}
AnnaBridge	167:e84263d55307	1339
AnnaBridge	167:e84263d55307	1340
AnnaBridge	167:e84263d55307	1341	/**
AnnaBridge	167:e84263d55307	1342	\brief Set Pending Interrupt
AnnaBridge	167:e84263d55307	1343	\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge	167:e84263d55307	1344	\param [in] IRQn Device specific interrupt number.
AnnaBridge	167:e84263d55307	1345	\note IRQn must not be negative.
AnnaBridge	167:e84263d55307	1346	*/
AnnaBridge	167:e84263d55307	1347	__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
AnnaBridge	167:e84263d55307	1348	{
AnnaBridge	167:e84263d55307	1349	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:e84263d55307	1350	{
AnnaBridge	167:e84263d55307	1351	NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge	167:e84263d55307	1352	}
AnnaBridge	167:e84263d55307	1353	}
AnnaBridge	167:e84263d55307	1354
AnnaBridge	167:e84263d55307	1355
AnnaBridge	167:e84263d55307	1356	/**
AnnaBridge	167:e84263d55307	1357	\brief Clear Pending Interrupt
AnnaBridge	167:e84263d55307	1358	\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge	167:e84263d55307	1359	\param [in] IRQn Device specific interrupt number.
AnnaBridge	167:e84263d55307	1360	\note IRQn must not be negative.
AnnaBridge	167:e84263d55307	1361	*/
AnnaBridge	167:e84263d55307	1362	__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
AnnaBridge	167:e84263d55307	1363	{
AnnaBridge	167:e84263d55307	1364	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:e84263d55307	1365	{
AnnaBridge	167:e84263d55307	1366	NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge	167:e84263d55307	1367	}
AnnaBridge	167:e84263d55307	1368	}
AnnaBridge	167:e84263d55307	1369
AnnaBridge	167:e84263d55307	1370
AnnaBridge	167:e84263d55307	1371	/**
AnnaBridge	167:e84263d55307	1372	\brief Get Active Interrupt
AnnaBridge	167:e84263d55307	1373	\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
AnnaBridge	167:e84263d55307	1374	\param [in] IRQn Device specific interrupt number.
AnnaBridge	167:e84263d55307	1375	\return 0 Interrupt status is not active.
AnnaBridge	167:e84263d55307	1376	\return 1 Interrupt status is active.
AnnaBridge	167:e84263d55307	1377	\note IRQn must not be negative.
AnnaBridge	167:e84263d55307	1378	*/
AnnaBridge	167:e84263d55307	1379	__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
AnnaBridge	167:e84263d55307	1380	{
AnnaBridge	167:e84263d55307	1381	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:e84263d55307	1382	{
AnnaBridge	167:e84263d55307	1383	return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	167:e84263d55307	1384	}
AnnaBridge	167:e84263d55307	1385	else
AnnaBridge	167:e84263d55307	1386	{
AnnaBridge	167:e84263d55307	1387	return(0U);
AnnaBridge	167:e84263d55307	1388	}
AnnaBridge	167:e84263d55307	1389	}
AnnaBridge	167:e84263d55307	1390
AnnaBridge	167:e84263d55307	1391
AnnaBridge	167:e84263d55307	1392	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge	167:e84263d55307	1393	/**
AnnaBridge	167:e84263d55307	1394	\brief Get Interrupt Target State
AnnaBridge	167:e84263d55307	1395	\details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
AnnaBridge	167:e84263d55307	1396	\param [in] IRQn Device specific interrupt number.
AnnaBridge	167:e84263d55307	1397	\return 0 if interrupt is assigned to Secure
AnnaBridge	167:e84263d55307	1398	\return 1 if interrupt is assigned to Non Secure
AnnaBridge	167:e84263d55307	1399	\note IRQn must not be negative.
AnnaBridge	167:e84263d55307	1400	*/
AnnaBridge	167:e84263d55307	1401	__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
AnnaBridge	167:e84263d55307	1402	{
AnnaBridge	167:e84263d55307	1403	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:e84263d55307	1404	{
AnnaBridge	167:e84263d55307	1405	return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	167:e84263d55307	1406	}
AnnaBridge	167:e84263d55307	1407	else
AnnaBridge	167:e84263d55307	1408	{
AnnaBridge	167:e84263d55307	1409	return(0U);
AnnaBridge	167:e84263d55307	1410	}
AnnaBridge	167:e84263d55307	1411	}
AnnaBridge	167:e84263d55307	1412
AnnaBridge	167:e84263d55307	1413
AnnaBridge	167:e84263d55307	1414	/**
AnnaBridge	167:e84263d55307	1415	\brief Set Interrupt Target State
AnnaBridge	167:e84263d55307	1416	\details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
AnnaBridge	167:e84263d55307	1417	\param [in] IRQn Device specific interrupt number.
AnnaBridge	167:e84263d55307	1418	\return 0 if interrupt is assigned to Secure
AnnaBridge	167:e84263d55307	1419	1 if interrupt is assigned to Non Secure
AnnaBridge	167:e84263d55307	1420	\note IRQn must not be negative.
AnnaBridge	167:e84263d55307	1421	*/
AnnaBridge	167:e84263d55307	1422	__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
AnnaBridge	167:e84263d55307	1423	{
AnnaBridge	167:e84263d55307	1424	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:e84263d55307	1425	{
AnnaBridge	167:e84263d55307	1426	NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] \|= ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
AnnaBridge	167:e84263d55307	1427	return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	167:e84263d55307	1428	}
AnnaBridge	167:e84263d55307	1429	else
AnnaBridge	167:e84263d55307	1430	{
AnnaBridge	167:e84263d55307	1431	return(0U);
AnnaBridge	167:e84263d55307	1432	}
AnnaBridge	167:e84263d55307	1433	}
AnnaBridge	167:e84263d55307	1434
AnnaBridge	167:e84263d55307	1435
AnnaBridge	167:e84263d55307	1436	/**
AnnaBridge	167:e84263d55307	1437	\brief Clear Interrupt Target State
AnnaBridge	167:e84263d55307	1438	\details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
AnnaBridge	167:e84263d55307	1439	\param [in] IRQn Device specific interrupt number.
AnnaBridge	167:e84263d55307	1440	\return 0 if interrupt is assigned to Secure
AnnaBridge	167:e84263d55307	1441	1 if interrupt is assigned to Non Secure
AnnaBridge	167:e84263d55307	1442	\note IRQn must not be negative.
AnnaBridge	167:e84263d55307	1443	*/
AnnaBridge	167:e84263d55307	1444	__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
AnnaBridge	167:e84263d55307	1445	{
AnnaBridge	167:e84263d55307	1446	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:e84263d55307	1447	{
AnnaBridge	167:e84263d55307	1448	NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
AnnaBridge	167:e84263d55307	1449	return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	167:e84263d55307	1450	}
AnnaBridge	167:e84263d55307	1451	else
AnnaBridge	167:e84263d55307	1452	{
AnnaBridge	167:e84263d55307	1453	return(0U);
AnnaBridge	167:e84263d55307	1454	}
AnnaBridge	167:e84263d55307	1455	}
AnnaBridge	167:e84263d55307	1456	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
AnnaBridge	167:e84263d55307	1457
AnnaBridge	167:e84263d55307	1458
AnnaBridge	167:e84263d55307	1459	/**
AnnaBridge	167:e84263d55307	1460	\brief Set Interrupt Priority
AnnaBridge	167:e84263d55307	1461	\details Sets the priority of a device specific interrupt or a processor exception.
AnnaBridge	167:e84263d55307	1462	The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge	167:e84263d55307	1463	or negative to specify a processor exception.
AnnaBridge	167:e84263d55307	1464	\param [in] IRQn Interrupt number.
AnnaBridge	167:e84263d55307	1465	\param [in] priority Priority to set.
AnnaBridge	167:e84263d55307	1466	\note The priority cannot be set for every processor exception.
AnnaBridge	167:e84263d55307	1467	*/
AnnaBridge	167:e84263d55307	1468	__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
AnnaBridge	167:e84263d55307	1469	{
AnnaBridge	167:e84263d55307	1470	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:e84263d55307	1471	{
AnnaBridge	167:e84263d55307	1472	NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) \|
AnnaBridge	167:e84263d55307	1473	(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
AnnaBridge	167:e84263d55307	1474	}
AnnaBridge	167:e84263d55307	1475	else
AnnaBridge	167:e84263d55307	1476	{
AnnaBridge	167:e84263d55307	1477	SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) \|
AnnaBridge	167:e84263d55307	1478	(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
AnnaBridge	167:e84263d55307	1479	}
AnnaBridge	167:e84263d55307	1480	}
AnnaBridge	167:e84263d55307	1481
AnnaBridge	167:e84263d55307	1482
AnnaBridge	167:e84263d55307	1483	/**
AnnaBridge	167:e84263d55307	1484	\brief Get Interrupt Priority
AnnaBridge	167:e84263d55307	1485	\details Reads the priority of a device specific interrupt or a processor exception.
AnnaBridge	167:e84263d55307	1486	The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge	167:e84263d55307	1487	or negative to specify a processor exception.
AnnaBridge	167:e84263d55307	1488	\param [in] IRQn Interrupt number.
AnnaBridge	167:e84263d55307	1489	\return Interrupt Priority.
AnnaBridge	167:e84263d55307	1490	Value is aligned automatically to the implemented priority bits of the microcontroller.
AnnaBridge	167:e84263d55307	1491	*/
AnnaBridge	167:e84263d55307	1492	__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
AnnaBridge	167:e84263d55307	1493	{
AnnaBridge	167:e84263d55307	1494
AnnaBridge	167:e84263d55307	1495	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:e84263d55307	1496	{
AnnaBridge	167:e84263d55307	1497	return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge	167:e84263d55307	1498	}
AnnaBridge	167:e84263d55307	1499	else
AnnaBridge	167:e84263d55307	1500	{
AnnaBridge	167:e84263d55307	1501	return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge	167:e84263d55307	1502	}
AnnaBridge	167:e84263d55307	1503	}
AnnaBridge	167:e84263d55307	1504
AnnaBridge	167:e84263d55307	1505
AnnaBridge	167:e84263d55307	1506	/**
AnnaBridge	167:e84263d55307	1507	\brief Set Interrupt Vector
AnnaBridge	167:e84263d55307	1508	\details Sets an interrupt vector in SRAM based interrupt vector table.
AnnaBridge	167:e84263d55307	1509	The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge	167:e84263d55307	1510	or negative to specify a processor exception.
AnnaBridge	167:e84263d55307	1511	VTOR must been relocated to SRAM before.
AnnaBridge	167:e84263d55307	1512	If VTOR is not present address 0 must be mapped to SRAM.
AnnaBridge	167:e84263d55307	1513	\param [in] IRQn Interrupt number
AnnaBridge	167:e84263d55307	1514	\param [in] vector Address of interrupt handler function
AnnaBridge	167:e84263d55307	1515	*/
AnnaBridge	167:e84263d55307	1516	__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
AnnaBridge	167:e84263d55307	1517	{
AnnaBridge	167:e84263d55307	1518	#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
AnnaBridge	167:e84263d55307	1519	uint32_t vectors = (uint32_t )SCB->VTOR;
AnnaBridge	167:e84263d55307	1520	#else
AnnaBridge	167:e84263d55307	1521	uint32_t vectors = (uint32_t )0x0U;
AnnaBridge	167:e84263d55307	1522	#endif
AnnaBridge	167:e84263d55307	1523	vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
AnnaBridge	167:e84263d55307	1524	}
AnnaBridge	167:e84263d55307	1525
AnnaBridge	167:e84263d55307	1526
AnnaBridge	167:e84263d55307	1527	/**
AnnaBridge	167:e84263d55307	1528	\brief Get Interrupt Vector
AnnaBridge	167:e84263d55307	1529	\details Reads an interrupt vector from interrupt vector table.
AnnaBridge	167:e84263d55307	1530	The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge	167:e84263d55307	1531	or negative to specify a processor exception.
AnnaBridge	167:e84263d55307	1532	\param [in] IRQn Interrupt number.
AnnaBridge	167:e84263d55307	1533	\return Address of interrupt handler function
AnnaBridge	167:e84263d55307	1534	*/
AnnaBridge	167:e84263d55307	1535	__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
AnnaBridge	167:e84263d55307	1536	{
AnnaBridge	167:e84263d55307	1537	#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
AnnaBridge	167:e84263d55307	1538	uint32_t vectors = (uint32_t )SCB->VTOR;
AnnaBridge	167:e84263d55307	1539	#else
AnnaBridge	167:e84263d55307	1540	uint32_t vectors = (uint32_t )0x0U;
AnnaBridge	167:e84263d55307	1541	#endif
AnnaBridge	167:e84263d55307	1542	return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
AnnaBridge	167:e84263d55307	1543	}
AnnaBridge	167:e84263d55307	1544
AnnaBridge	167:e84263d55307	1545
AnnaBridge	167:e84263d55307	1546	/**
AnnaBridge	167:e84263d55307	1547	\brief System Reset
AnnaBridge	167:e84263d55307	1548	\details Initiates a system reset request to reset the MCU.
AnnaBridge	167:e84263d55307	1549	*/
AnnaBridge	167:e84263d55307	1550	__STATIC_INLINE void __NVIC_SystemReset(void)
AnnaBridge	167:e84263d55307	1551	{
AnnaBridge	167:e84263d55307	1552	__DSB(); /* Ensure all outstanding memory accesses included
AnnaBridge	167:e84263d55307	1553	buffered write are completed before reset */
AnnaBridge	167:e84263d55307	1554	SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
AnnaBridge	167:e84263d55307	1555	SCB_AIRCR_SYSRESETREQ_Msk);
AnnaBridge	167:e84263d55307	1556	__DSB(); /* Ensure completion of memory access */
AnnaBridge	167:e84263d55307	1557
AnnaBridge	167:e84263d55307	1558	for(;;) /* wait until reset */
AnnaBridge	167:e84263d55307	1559	{
AnnaBridge	167:e84263d55307	1560	__NOP();
AnnaBridge	167:e84263d55307	1561	}
AnnaBridge	167:e84263d55307	1562	}
AnnaBridge	167:e84263d55307	1563
AnnaBridge	167:e84263d55307	1564	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge	167:e84263d55307	1565	/**
AnnaBridge	167:e84263d55307	1566	\brief Enable Interrupt (non-secure)
AnnaBridge	167:e84263d55307	1567	\details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
AnnaBridge	167:e84263d55307	1568	\param [in] IRQn Device specific interrupt number.
AnnaBridge	167:e84263d55307	1569	\note IRQn must not be negative.
AnnaBridge	167:e84263d55307	1570	*/
AnnaBridge	167:e84263d55307	1571	__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
AnnaBridge	167:e84263d55307	1572	{
AnnaBridge	167:e84263d55307	1573	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:e84263d55307	1574	{
AnnaBridge	167:e84263d55307	1575	NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge	167:e84263d55307	1576	}
AnnaBridge	167:e84263d55307	1577	}
AnnaBridge	167:e84263d55307	1578
AnnaBridge	167:e84263d55307	1579
AnnaBridge	167:e84263d55307	1580	/**
AnnaBridge	167:e84263d55307	1581	\brief Get Interrupt Enable status (non-secure)
AnnaBridge	167:e84263d55307	1582	\details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
AnnaBridge	167:e84263d55307	1583	\param [in] IRQn Device specific interrupt number.
AnnaBridge	167:e84263d55307	1584	\return 0 Interrupt is not enabled.
AnnaBridge	167:e84263d55307	1585	\return 1 Interrupt is enabled.
AnnaBridge	167:e84263d55307	1586	\note IRQn must not be negative.
AnnaBridge	167:e84263d55307	1587	*/
AnnaBridge	167:e84263d55307	1588	__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
AnnaBridge	167:e84263d55307	1589	{
AnnaBridge	167:e84263d55307	1590	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:e84263d55307	1591	{
AnnaBridge	167:e84263d55307	1592	return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	167:e84263d55307	1593	}
AnnaBridge	167:e84263d55307	1594	else
AnnaBridge	167:e84263d55307	1595	{
AnnaBridge	167:e84263d55307	1596	return(0U);
AnnaBridge	167:e84263d55307	1597	}
AnnaBridge	167:e84263d55307	1598	}
AnnaBridge	167:e84263d55307	1599
AnnaBridge	167:e84263d55307	1600
AnnaBridge	167:e84263d55307	1601	/**
AnnaBridge	167:e84263d55307	1602	\brief Disable Interrupt (non-secure)
AnnaBridge	167:e84263d55307	1603	\details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
AnnaBridge	167:e84263d55307	1604	\param [in] IRQn Device specific interrupt number.
AnnaBridge	167:e84263d55307	1605	\note IRQn must not be negative.
AnnaBridge	167:e84263d55307	1606	*/
AnnaBridge	167:e84263d55307	1607	__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
AnnaBridge	167:e84263d55307	1608	{
AnnaBridge	167:e84263d55307	1609	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:e84263d55307	1610	{
AnnaBridge	167:e84263d55307	1611	NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge	167:e84263d55307	1612	}
AnnaBridge	167:e84263d55307	1613	}
AnnaBridge	167:e84263d55307	1614
AnnaBridge	167:e84263d55307	1615
AnnaBridge	167:e84263d55307	1616	/**
AnnaBridge	167:e84263d55307	1617	\brief Get Pending Interrupt (non-secure)
AnnaBridge	167:e84263d55307	1618	\details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
AnnaBridge	167:e84263d55307	1619	\param [in] IRQn Device specific interrupt number.
AnnaBridge	167:e84263d55307	1620	\return 0 Interrupt status is not pending.
AnnaBridge	167:e84263d55307	1621	\return 1 Interrupt status is pending.
AnnaBridge	167:e84263d55307	1622	\note IRQn must not be negative.
AnnaBridge	167:e84263d55307	1623	*/
AnnaBridge	167:e84263d55307	1624	__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
AnnaBridge	167:e84263d55307	1625	{
AnnaBridge	167:e84263d55307	1626	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:e84263d55307	1627	{
AnnaBridge	167:e84263d55307	1628	return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	167:e84263d55307	1629	}
AnnaBridge	167:e84263d55307	1630	}
AnnaBridge	167:e84263d55307	1631
AnnaBridge	167:e84263d55307	1632
AnnaBridge	167:e84263d55307	1633	/**
AnnaBridge	167:e84263d55307	1634	\brief Set Pending Interrupt (non-secure)
AnnaBridge	167:e84263d55307	1635	\details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
AnnaBridge	167:e84263d55307	1636	\param [in] IRQn Device specific interrupt number.
AnnaBridge	167:e84263d55307	1637	\note IRQn must not be negative.
AnnaBridge	167:e84263d55307	1638	*/
AnnaBridge	167:e84263d55307	1639	__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
AnnaBridge	167:e84263d55307	1640	{
AnnaBridge	167:e84263d55307	1641	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:e84263d55307	1642	{
AnnaBridge	167:e84263d55307	1643	NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge	167:e84263d55307	1644	}
AnnaBridge	167:e84263d55307	1645	}
AnnaBridge	167:e84263d55307	1646
AnnaBridge	167:e84263d55307	1647
AnnaBridge	167:e84263d55307	1648	/**
AnnaBridge	167:e84263d55307	1649	\brief Clear Pending Interrupt (non-secure)
AnnaBridge	167:e84263d55307	1650	\details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
AnnaBridge	167:e84263d55307	1651	\param [in] IRQn Device specific interrupt number.
AnnaBridge	167:e84263d55307	1652	\note IRQn must not be negative.
AnnaBridge	167:e84263d55307	1653	*/
AnnaBridge	167:e84263d55307	1654	__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
AnnaBridge	167:e84263d55307	1655	{
AnnaBridge	167:e84263d55307	1656	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:e84263d55307	1657	{
AnnaBridge	167:e84263d55307	1658	NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge	167:e84263d55307	1659	}
AnnaBridge	167:e84263d55307	1660	}
AnnaBridge	167:e84263d55307	1661
AnnaBridge	167:e84263d55307	1662
AnnaBridge	167:e84263d55307	1663	/**
AnnaBridge	167:e84263d55307	1664	\brief Get Active Interrupt (non-secure)
AnnaBridge	167:e84263d55307	1665	\details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
AnnaBridge	167:e84263d55307	1666	\param [in] IRQn Device specific interrupt number.
AnnaBridge	167:e84263d55307	1667	\return 0 Interrupt status is not active.
AnnaBridge	167:e84263d55307	1668	\return 1 Interrupt status is active.
AnnaBridge	167:e84263d55307	1669	\note IRQn must not be negative.
AnnaBridge	167:e84263d55307	1670	*/
AnnaBridge	167:e84263d55307	1671	__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
AnnaBridge	167:e84263d55307	1672	{
AnnaBridge	167:e84263d55307	1673	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:e84263d55307	1674	{
AnnaBridge	167:e84263d55307	1675	return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	167:e84263d55307	1676	}
AnnaBridge	167:e84263d55307	1677	else
AnnaBridge	167:e84263d55307	1678	{
AnnaBridge	167:e84263d55307	1679	return(0U);
AnnaBridge	167:e84263d55307	1680	}
AnnaBridge	167:e84263d55307	1681	}
AnnaBridge	167:e84263d55307	1682
AnnaBridge	167:e84263d55307	1683
AnnaBridge	167:e84263d55307	1684	/**
AnnaBridge	167:e84263d55307	1685	\brief Set Interrupt Priority (non-secure)
AnnaBridge	167:e84263d55307	1686	\details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
AnnaBridge	167:e84263d55307	1687	The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge	167:e84263d55307	1688	or negative to specify a processor exception.
AnnaBridge	167:e84263d55307	1689	\param [in] IRQn Interrupt number.
AnnaBridge	167:e84263d55307	1690	\param [in] priority Priority to set.
AnnaBridge	167:e84263d55307	1691	\note The priority cannot be set for every non-secure processor exception.
AnnaBridge	167:e84263d55307	1692	*/
AnnaBridge	167:e84263d55307	1693	__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
AnnaBridge	167:e84263d55307	1694	{
AnnaBridge	167:e84263d55307	1695	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:e84263d55307	1696	{
AnnaBridge	167:e84263d55307	1697	NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) \|
AnnaBridge	167:e84263d55307	1698	(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
AnnaBridge	167:e84263d55307	1699	}
AnnaBridge	167:e84263d55307	1700	else
AnnaBridge	167:e84263d55307	1701	{
AnnaBridge	167:e84263d55307	1702	SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) \|
AnnaBridge	167:e84263d55307	1703	(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
AnnaBridge	167:e84263d55307	1704	}
AnnaBridge	167:e84263d55307	1705	}
AnnaBridge	167:e84263d55307	1706
AnnaBridge	167:e84263d55307	1707
AnnaBridge	167:e84263d55307	1708	/**
AnnaBridge	167:e84263d55307	1709	\brief Get Interrupt Priority (non-secure)
AnnaBridge	167:e84263d55307	1710	\details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
AnnaBridge	167:e84263d55307	1711	The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge	167:e84263d55307	1712	or negative to specify a processor exception.
AnnaBridge	167:e84263d55307	1713	\param [in] IRQn Interrupt number.
AnnaBridge	167:e84263d55307	1714	\return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
AnnaBridge	167:e84263d55307	1715	*/
AnnaBridge	167:e84263d55307	1716	__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
AnnaBridge	167:e84263d55307	1717	{
AnnaBridge	167:e84263d55307	1718
AnnaBridge	167:e84263d55307	1719	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:e84263d55307	1720	{
AnnaBridge	167:e84263d55307	1721	return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge	167:e84263d55307	1722	}
AnnaBridge	167:e84263d55307	1723	else
AnnaBridge	167:e84263d55307	1724	{
AnnaBridge	167:e84263d55307	1725	return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge	167:e84263d55307	1726	}
AnnaBridge	167:e84263d55307	1727	}
AnnaBridge	167:e84263d55307	1728	#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
AnnaBridge	167:e84263d55307	1729
AnnaBridge	167:e84263d55307	1730	/@} end of CMSIS_Core_NVICFunctions /
AnnaBridge	167:e84263d55307	1731
AnnaBridge	167:e84263d55307	1732
AnnaBridge	167:e84263d55307	1733	/* ########################## FPU functions #################################### */
AnnaBridge	167:e84263d55307	1734	/**
AnnaBridge	167:e84263d55307	1735	\ingroup CMSIS_Core_FunctionInterface
AnnaBridge	167:e84263d55307	1736	\defgroup CMSIS_Core_FpuFunctions FPU Functions
AnnaBridge	167:e84263d55307	1737	\brief Function that provides FPU type.
AnnaBridge	167:e84263d55307	1738	@{
AnnaBridge	167:e84263d55307	1739	*/
AnnaBridge	167:e84263d55307	1740
AnnaBridge	167:e84263d55307	1741	/**
AnnaBridge	167:e84263d55307	1742	\brief get FPU type
AnnaBridge	167:e84263d55307	1743	\details returns the FPU type
AnnaBridge	167:e84263d55307	1744	\returns
AnnaBridge	167:e84263d55307	1745	- \b 0: No FPU
AnnaBridge	167:e84263d55307	1746	- \b 1: Single precision FPU
AnnaBridge	167:e84263d55307	1747	- \b 2: Double + Single precision FPU
AnnaBridge	167:e84263d55307	1748	*/
AnnaBridge	167:e84263d55307	1749	__STATIC_INLINE uint32_t SCB_GetFPUType(void)
AnnaBridge	167:e84263d55307	1750	{
AnnaBridge	167:e84263d55307	1751	return 0U; /* No FPU */
AnnaBridge	167:e84263d55307	1752	}
AnnaBridge	167:e84263d55307	1753
AnnaBridge	167:e84263d55307	1754
AnnaBridge	167:e84263d55307	1755	/@} end of CMSIS_Core_FpuFunctions /
AnnaBridge	167:e84263d55307	1756
AnnaBridge	167:e84263d55307	1757
AnnaBridge	167:e84263d55307	1758
AnnaBridge	167:e84263d55307	1759	/* ########################## SAU functions #################################### */
AnnaBridge	167:e84263d55307	1760	/**
AnnaBridge	167:e84263d55307	1761	\ingroup CMSIS_Core_FunctionInterface
AnnaBridge	167:e84263d55307	1762	\defgroup CMSIS_Core_SAUFunctions SAU Functions
AnnaBridge	167:e84263d55307	1763	\brief Functions that configure the SAU.
AnnaBridge	167:e84263d55307	1764	@{
AnnaBridge	167:e84263d55307	1765	*/
AnnaBridge	167:e84263d55307	1766
AnnaBridge	167:e84263d55307	1767	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge	167:e84263d55307	1768
AnnaBridge	167:e84263d55307	1769	/**
AnnaBridge	167:e84263d55307	1770	\brief Enable SAU
AnnaBridge	167:e84263d55307	1771	\details Enables the Security Attribution Unit (SAU).
AnnaBridge	167:e84263d55307	1772	*/
AnnaBridge	167:e84263d55307	1773	__STATIC_INLINE void TZ_SAU_Enable(void)
AnnaBridge	167:e84263d55307	1774	{
AnnaBridge	167:e84263d55307	1775	SAU->CTRL \|= (SAU_CTRL_ENABLE_Msk);
AnnaBridge	167:e84263d55307	1776	}
AnnaBridge	167:e84263d55307	1777
AnnaBridge	167:e84263d55307	1778
AnnaBridge	167:e84263d55307	1779
AnnaBridge	167:e84263d55307	1780	/**
AnnaBridge	167:e84263d55307	1781	\brief Disable SAU
AnnaBridge	167:e84263d55307	1782	\details Disables the Security Attribution Unit (SAU).
AnnaBridge	167:e84263d55307	1783	*/
AnnaBridge	167:e84263d55307	1784	__STATIC_INLINE void TZ_SAU_Disable(void)
AnnaBridge	167:e84263d55307	1785	{
AnnaBridge	167:e84263d55307	1786	SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
AnnaBridge	167:e84263d55307	1787	}
AnnaBridge	167:e84263d55307	1788
AnnaBridge	167:e84263d55307	1789	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
AnnaBridge	167:e84263d55307	1790
AnnaBridge	167:e84263d55307	1791	/@} end of CMSIS_Core_SAUFunctions /
AnnaBridge	167:e84263d55307	1792
AnnaBridge	167:e84263d55307	1793
AnnaBridge	167:e84263d55307	1794
AnnaBridge	167:e84263d55307	1795
AnnaBridge	167:e84263d55307	1796	/* ################################## SysTick function ############################################ */
AnnaBridge	167:e84263d55307	1797	/**
AnnaBridge	167:e84263d55307	1798	\ingroup CMSIS_Core_FunctionInterface
AnnaBridge	167:e84263d55307	1799	\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
AnnaBridge	167:e84263d55307	1800	\brief Functions that configure the System.
AnnaBridge	167:e84263d55307	1801	@{
AnnaBridge	167:e84263d55307	1802	*/
AnnaBridge	167:e84263d55307	1803
AnnaBridge	167:e84263d55307	1804	#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
AnnaBridge	167:e84263d55307	1805
AnnaBridge	167:e84263d55307	1806	/**
AnnaBridge	167:e84263d55307	1807	\brief System Tick Configuration
AnnaBridge	167:e84263d55307	1808	\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
AnnaBridge	167:e84263d55307	1809	Counter is in free running mode to generate periodic interrupts.
AnnaBridge	167:e84263d55307	1810	\param [in] ticks Number of ticks between two interrupts.
AnnaBridge	167:e84263d55307	1811	\return 0 Function succeeded.
AnnaBridge	167:e84263d55307	1812	\return 1 Function failed.
AnnaBridge	167:e84263d55307	1813	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
AnnaBridge	167:e84263d55307	1814	function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
AnnaBridge	167:e84263d55307	1815	must contain a vendor-specific implementation of this function.
AnnaBridge	167:e84263d55307	1816	*/
AnnaBridge	167:e84263d55307	1817	__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
AnnaBridge	167:e84263d55307	1818	{
AnnaBridge	167:e84263d55307	1819	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
AnnaBridge	167:e84263d55307	1820	{
AnnaBridge	167:e84263d55307	1821	return (1UL); /* Reload value impossible */
AnnaBridge	167:e84263d55307	1822	}
AnnaBridge	167:e84263d55307	1823
AnnaBridge	167:e84263d55307	1824	SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
AnnaBridge	167:e84263d55307	1825	NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
AnnaBridge	167:e84263d55307	1826	SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
AnnaBridge	167:e84263d55307	1827	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
AnnaBridge	167:e84263d55307	1828	SysTick_CTRL_TICKINT_Msk \|
AnnaBridge	167:e84263d55307	1829	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
AnnaBridge	167:e84263d55307	1830	return (0UL); /* Function successful */
AnnaBridge	167:e84263d55307	1831	}
AnnaBridge	167:e84263d55307	1832
AnnaBridge	167:e84263d55307	1833	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge	167:e84263d55307	1834	/**
AnnaBridge	167:e84263d55307	1835	\brief System Tick Configuration (non-secure)
AnnaBridge	167:e84263d55307	1836	\details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
AnnaBridge	167:e84263d55307	1837	Counter is in free running mode to generate periodic interrupts.
AnnaBridge	167:e84263d55307	1838	\param [in] ticks Number of ticks between two interrupts.
AnnaBridge	167:e84263d55307	1839	\return 0 Function succeeded.
AnnaBridge	167:e84263d55307	1840	\return 1 Function failed.
AnnaBridge	167:e84263d55307	1841	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
AnnaBridge	167:e84263d55307	1842	function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
AnnaBridge	167:e84263d55307	1843	must contain a vendor-specific implementation of this function.
AnnaBridge	167:e84263d55307	1844
AnnaBridge	167:e84263d55307	1845	*/
AnnaBridge	167:e84263d55307	1846	__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
AnnaBridge	167:e84263d55307	1847	{
AnnaBridge	167:e84263d55307	1848	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
AnnaBridge	167:e84263d55307	1849	{
AnnaBridge	167:e84263d55307	1850	return (1UL); /* Reload value impossible */
AnnaBridge	167:e84263d55307	1851	}
AnnaBridge	167:e84263d55307	1852
AnnaBridge	167:e84263d55307	1853	SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
AnnaBridge	167:e84263d55307	1854	TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
AnnaBridge	167:e84263d55307	1855	SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
AnnaBridge	167:e84263d55307	1856	SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
AnnaBridge	167:e84263d55307	1857	SysTick_CTRL_TICKINT_Msk \|
AnnaBridge	167:e84263d55307	1858	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
AnnaBridge	167:e84263d55307	1859	return (0UL); /* Function successful */
AnnaBridge	167:e84263d55307	1860	}
AnnaBridge	167:e84263d55307	1861	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
AnnaBridge	167:e84263d55307	1862
AnnaBridge	167:e84263d55307	1863	#endif
AnnaBridge	167:e84263d55307	1864
AnnaBridge	167:e84263d55307	1865	/@} end of CMSIS_Core_SysTickFunctions /
AnnaBridge	167:e84263d55307	1866
AnnaBridge	167:e84263d55307	1867
AnnaBridge	167:e84263d55307	1868
AnnaBridge	167:e84263d55307	1869
AnnaBridge	167:e84263d55307	1870	#ifdef __cplusplus
AnnaBridge	167:e84263d55307	1871	}
AnnaBridge	167:e84263d55307	1872	#endif
AnnaBridge	167:e84263d55307	1873
AnnaBridge	167:e84263d55307	1874	#endif /* __CORE_CM23_H_DEPENDANT */
AnnaBridge	167:e84263d55307	1875
AnnaBridge	167:e84263d55307	1876	#endif /* __CMSIS_GENERIC */

Repository toolbox

Export to desktop IDE

Repository details

Type:	Library
Created:	19 Dec 2017
Imports:	0
Forks:	0
Commits:	175
Dependents:	0
Dependencies:	0
Followers:	1

cmsis/core_cm23.h@174:ed647f63e28d, 2017-12-19 (annotated)

Who changed what in which revision?

Repository toolbox

Repository details

Important Information for this Arm website

Access Warning