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cmsis/core_cm0.h@174:ed647f63e28d, 2017-12-19 (annotated)

Committer:
Dollyparton
Date:
Tue Dec 19 12:50:13 2017 +0000
Revision:
174:ed647f63e28d
Parent:
167:e84263d55307 
Added RAW socket.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**************************************************************************//**
<> 144:ef7eb2e8f9f7 2 * @file core_cm0.h
<> 144:ef7eb2e8f9f7 3 * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
AnnaBridge 167:e84263d55307 4 * @version V5.0.2
AnnaBridge 167:e84263d55307 5 * @date 13. February 2017
AnnaBridge 167:e84263d55307 6 ******************************************************************************/
AnnaBridge 167:e84263d55307 7 /*
AnnaBridge 167:e84263d55307 8 * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
AnnaBridge 167:e84263d55307 9 *
AnnaBridge 167:e84263d55307 10 * SPDX-License-Identifier: Apache-2.0
<> 144:ef7eb2e8f9f7 11 *
AnnaBridge 167:e84263d55307 12 * Licensed under the Apache License, Version 2.0 (the License); you may
AnnaBridge 167:e84263d55307 13 * not use this file except in compliance with the License.
AnnaBridge 167:e84263d55307 14 * You may obtain a copy of the License at
AnnaBridge 167:e84263d55307 15 *
AnnaBridge 167:e84263d55307 16 * www.apache.org/licenses/LICENSE-2.0
<> 144:ef7eb2e8f9f7 17 *
AnnaBridge 167:e84263d55307 18 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 167:e84263d55307 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
AnnaBridge 167:e84263d55307 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 167:e84263d55307 21 * See the License for the specific language governing permissions and
AnnaBridge 167:e84263d55307 22 * limitations under the License.
AnnaBridge 167:e84263d55307 23 */
<> 144:ef7eb2e8f9f7 24
AnnaBridge 167:e84263d55307 25 #if defined ( __ICCARM__ )
AnnaBridge 167:e84263d55307 26 #pragma system_include /* treat file as system include file for MISRA check */
AnnaBridge 167:e84263d55307 27 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge 167:e84263d55307 28 #pragma clang system_header /* treat file as system include file */
<> 144:ef7eb2e8f9f7 29 #endif
<> 144:ef7eb2e8f9f7 30
<> 144:ef7eb2e8f9f7 31 #ifndef __CORE_CM0_H_GENERIC
<> 144:ef7eb2e8f9f7 32 #define __CORE_CM0_H_GENERIC
<> 144:ef7eb2e8f9f7 33
AnnaBridge 167:e84263d55307 34 #include <stdint.h>
AnnaBridge 167:e84263d55307 35
<> 144:ef7eb2e8f9f7 36 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 37 extern "C" {
<> 144:ef7eb2e8f9f7 38 #endif
<> 144:ef7eb2e8f9f7 39
AnnaBridge 167:e84263d55307 40 /**
AnnaBridge 167:e84263d55307 41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
<> 144:ef7eb2e8f9f7 42 CMSIS violates the following MISRA-C:2004 rules:
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 \li Required Rule 8.5, object/function definition in header file.<br>
<> 144:ef7eb2e8f9f7 45 Function definitions in header files are used to allow 'inlining'.
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
<> 144:ef7eb2e8f9f7 48 Unions are used for effective representation of core registers.
<> 144:ef7eb2e8f9f7 49
<> 144:ef7eb2e8f9f7 50 \li Advisory Rule 19.7, Function-like macro defined.<br>
<> 144:ef7eb2e8f9f7 51 Function-like macros are used to allow more efficient code.
<> 144:ef7eb2e8f9f7 52 */
<> 144:ef7eb2e8f9f7 53
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 /*******************************************************************************
<> 144:ef7eb2e8f9f7 56 * CMSIS definitions
<> 144:ef7eb2e8f9f7 57 ******************************************************************************/
AnnaBridge 167:e84263d55307 58 /**
AnnaBridge 167:e84263d55307 59 \ingroup Cortex_M0
<> 144:ef7eb2e8f9f7 60 @{
<> 144:ef7eb2e8f9f7 61 */
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63 /* CMSIS CM0 definitions */
AnnaBridge 167:e84263d55307 64 #define __CM0_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */
AnnaBridge 167:e84263d55307 65 #define __CM0_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */
AnnaBridge 167:e84263d55307 66 #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
AnnaBridge 167:e84263d55307 67 __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
<> 144:ef7eb2e8f9f7 68
AnnaBridge 167:e84263d55307 69 #define __CORTEX_M (0U) /*!< Cortex-M Core */
<> 144:ef7eb2e8f9f7 70
<> 144:ef7eb2e8f9f7 71 /** __FPU_USED indicates whether an FPU is used or not.
<> 144:ef7eb2e8f9f7 72 This core does not support an FPU at all
<> 144:ef7eb2e8f9f7 73 */
AnnaBridge 167:e84263d55307 74 #define __FPU_USED 0U
<> 144:ef7eb2e8f9f7 75
<> 144:ef7eb2e8f9f7 76 #if defined ( __CC_ARM )
<> 144:ef7eb2e8f9f7 77 #if defined __TARGET_FPU_VFP
AnnaBridge 167:e84263d55307 78 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 167:e84263d55307 79 #endif
AnnaBridge 167:e84263d55307 80
AnnaBridge 167:e84263d55307 81 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge 167:e84263d55307 82 #if defined __ARM_PCS_VFP
AnnaBridge 167:e84263d55307 83 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 144:ef7eb2e8f9f7 84 #endif
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 #elif defined ( __GNUC__ )
<> 144:ef7eb2e8f9f7 87 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
AnnaBridge 167:e84263d55307 88 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 144:ef7eb2e8f9f7 89 #endif
<> 144:ef7eb2e8f9f7 90
<> 144:ef7eb2e8f9f7 91 #elif defined ( __ICCARM__ )
<> 144:ef7eb2e8f9f7 92 #if defined __ARMVFP__
AnnaBridge 167:e84263d55307 93 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 144:ef7eb2e8f9f7 94 #endif
<> 144:ef7eb2e8f9f7 95
AnnaBridge 167:e84263d55307 96 #elif defined ( __TI_ARM__ )
AnnaBridge 167:e84263d55307 97 #if defined __TI_VFP_SUPPORT__
AnnaBridge 167:e84263d55307 98 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 144:ef7eb2e8f9f7 99 #endif
<> 144:ef7eb2e8f9f7 100
<> 144:ef7eb2e8f9f7 101 #elif defined ( __TASKING__ )
<> 144:ef7eb2e8f9f7 102 #if defined __FPU_VFP__
<> 144:ef7eb2e8f9f7 103 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 144:ef7eb2e8f9f7 104 #endif
<> 144:ef7eb2e8f9f7 105
AnnaBridge 167:e84263d55307 106 #elif defined ( __CSMC__ )
AnnaBridge 167:e84263d55307 107 #if ( __CSMC__ & 0x400U)
<> 144:ef7eb2e8f9f7 108 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 144:ef7eb2e8f9f7 109 #endif
AnnaBridge 167:e84263d55307 110
<> 144:ef7eb2e8f9f7 111 #endif
<> 144:ef7eb2e8f9f7 112
AnnaBridge 167:e84263d55307 113 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
AnnaBridge 167:e84263d55307 114
<> 144:ef7eb2e8f9f7 115
<> 144:ef7eb2e8f9f7 116 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 117 }
<> 144:ef7eb2e8f9f7 118 #endif
<> 144:ef7eb2e8f9f7 119
<> 144:ef7eb2e8f9f7 120 #endif /* __CORE_CM0_H_GENERIC */
<> 144:ef7eb2e8f9f7 121
<> 144:ef7eb2e8f9f7 122 #ifndef __CMSIS_GENERIC
<> 144:ef7eb2e8f9f7 123
<> 144:ef7eb2e8f9f7 124 #ifndef __CORE_CM0_H_DEPENDANT
<> 144:ef7eb2e8f9f7 125 #define __CORE_CM0_H_DEPENDANT
<> 144:ef7eb2e8f9f7 126
<> 144:ef7eb2e8f9f7 127 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 128 extern "C" {
<> 144:ef7eb2e8f9f7 129 #endif
<> 144:ef7eb2e8f9f7 130
<> 144:ef7eb2e8f9f7 131 /* check device defines and use defaults */
<> 144:ef7eb2e8f9f7 132 #if defined __CHECK_DEVICE_DEFINES
<> 144:ef7eb2e8f9f7 133 #ifndef __CM0_REV
AnnaBridge 167:e84263d55307 134 #define __CM0_REV 0x0000U
<> 144:ef7eb2e8f9f7 135 #warning "__CM0_REV not defined in device header file; using default!"
<> 144:ef7eb2e8f9f7 136 #endif
<> 144:ef7eb2e8f9f7 137
<> 144:ef7eb2e8f9f7 138 #ifndef __NVIC_PRIO_BITS
AnnaBridge 167:e84263d55307 139 #define __NVIC_PRIO_BITS 2U
<> 144:ef7eb2e8f9f7 140 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
<> 144:ef7eb2e8f9f7 141 #endif
<> 144:ef7eb2e8f9f7 142
<> 144:ef7eb2e8f9f7 143 #ifndef __Vendor_SysTickConfig
AnnaBridge 167:e84263d55307 144 #define __Vendor_SysTickConfig 0U
<> 144:ef7eb2e8f9f7 145 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
<> 144:ef7eb2e8f9f7 146 #endif
<> 144:ef7eb2e8f9f7 147 #endif
<> 144:ef7eb2e8f9f7 148
<> 144:ef7eb2e8f9f7 149 /* IO definitions (access restrictions to peripheral registers) */
<> 144:ef7eb2e8f9f7 150 /**
<> 144:ef7eb2e8f9f7 151 \defgroup CMSIS_glob_defs CMSIS Global Defines
<> 144:ef7eb2e8f9f7 152
<> 144:ef7eb2e8f9f7 153 <strong>IO Type Qualifiers</strong> are used
<> 144:ef7eb2e8f9f7 154 \li to specify the access to peripheral variables.
<> 144:ef7eb2e8f9f7 155 \li for automatic generation of peripheral register debug information.
<> 144:ef7eb2e8f9f7 156 */
<> 144:ef7eb2e8f9f7 157 #ifdef __cplusplus
AnnaBridge 167:e84263d55307 158 #define __I volatile /*!< Defines 'read only' permissions */
<> 144:ef7eb2e8f9f7 159 #else
AnnaBridge 167:e84263d55307 160 #define __I volatile const /*!< Defines 'read only' permissions */
<> 144:ef7eb2e8f9f7 161 #endif
AnnaBridge 167:e84263d55307 162 #define __O volatile /*!< Defines 'write only' permissions */
AnnaBridge 167:e84263d55307 163 #define __IO volatile /*!< Defines 'read / write' permissions */
<> 144:ef7eb2e8f9f7 164
AnnaBridge 167:e84263d55307 165 /* following defines should be used for structure members */
AnnaBridge 167:e84263d55307 166 #define __IM volatile const /*! Defines 'read only' structure member permissions */
AnnaBridge 167:e84263d55307 167 #define __OM volatile /*! Defines 'write only' structure member permissions */
AnnaBridge 167:e84263d55307 168 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
<> 150:02e0a0aed4ec 169
<> 144:ef7eb2e8f9f7 170 /*@} end of group Cortex_M0 */
<> 144:ef7eb2e8f9f7 171
<> 144:ef7eb2e8f9f7 172
<> 144:ef7eb2e8f9f7 173
<> 144:ef7eb2e8f9f7 174 /*******************************************************************************
<> 144:ef7eb2e8f9f7 175 * Register Abstraction
<> 144:ef7eb2e8f9f7 176 Core Register contain:
<> 144:ef7eb2e8f9f7 177 - Core Register
<> 144:ef7eb2e8f9f7 178 - Core NVIC Register
<> 144:ef7eb2e8f9f7 179 - Core SCB Register
<> 144:ef7eb2e8f9f7 180 - Core SysTick Register
<> 144:ef7eb2e8f9f7 181 ******************************************************************************/
AnnaBridge 167:e84263d55307 182 /**
AnnaBridge 167:e84263d55307 183 \defgroup CMSIS_core_register Defines and Type Definitions
AnnaBridge 167:e84263d55307 184 \brief Type definitions and defines for Cortex-M processor based devices.
<> 144:ef7eb2e8f9f7 185 */
<> 144:ef7eb2e8f9f7 186
AnnaBridge 167:e84263d55307 187 /**
AnnaBridge 167:e84263d55307 188 \ingroup CMSIS_core_register
AnnaBridge 167:e84263d55307 189 \defgroup CMSIS_CORE Status and Control Registers
AnnaBridge 167:e84263d55307 190 \brief Core Register type definitions.
<> 144:ef7eb2e8f9f7 191 @{
<> 144:ef7eb2e8f9f7 192 */
<> 144:ef7eb2e8f9f7 193
AnnaBridge 167:e84263d55307 194 /**
AnnaBridge 167:e84263d55307 195 \brief Union type to access the Application Program Status Register (APSR).
<> 144:ef7eb2e8f9f7 196 */
<> 144:ef7eb2e8f9f7 197 typedef union
<> 144:ef7eb2e8f9f7 198 {
<> 144:ef7eb2e8f9f7 199 struct
<> 144:ef7eb2e8f9f7 200 {
AnnaBridge 167:e84263d55307 201 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
AnnaBridge 167:e84263d55307 202 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
AnnaBridge 167:e84263d55307 203 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
AnnaBridge 167:e84263d55307 204 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
AnnaBridge 167:e84263d55307 205 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
AnnaBridge 167:e84263d55307 206 } b; /*!< Structure used for bit access */
AnnaBridge 167:e84263d55307 207 uint32_t w; /*!< Type used for word access */
<> 144:ef7eb2e8f9f7 208 } APSR_Type;
<> 144:ef7eb2e8f9f7 209
<> 144:ef7eb2e8f9f7 210 /* APSR Register Definitions */
AnnaBridge 167:e84263d55307 211 #define APSR_N_Pos 31U /*!< APSR: N Position */
<> 144:ef7eb2e8f9f7 212 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
<> 144:ef7eb2e8f9f7 213
AnnaBridge 167:e84263d55307 214 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
<> 144:ef7eb2e8f9f7 215 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
<> 144:ef7eb2e8f9f7 216
AnnaBridge 167:e84263d55307 217 #define APSR_C_Pos 29U /*!< APSR: C Position */
<> 144:ef7eb2e8f9f7 218 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
<> 144:ef7eb2e8f9f7 219
AnnaBridge 167:e84263d55307 220 #define APSR_V_Pos 28U /*!< APSR: V Position */
<> 144:ef7eb2e8f9f7 221 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
<> 144:ef7eb2e8f9f7 222
<> 144:ef7eb2e8f9f7 223
AnnaBridge 167:e84263d55307 224 /**
AnnaBridge 167:e84263d55307 225 \brief Union type to access the Interrupt Program Status Register (IPSR).
<> 144:ef7eb2e8f9f7 226 */
<> 144:ef7eb2e8f9f7 227 typedef union
<> 144:ef7eb2e8f9f7 228 {
<> 144:ef7eb2e8f9f7 229 struct
<> 144:ef7eb2e8f9f7 230 {
AnnaBridge 167:e84263d55307 231 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
AnnaBridge 167:e84263d55307 232 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
AnnaBridge 167:e84263d55307 233 } b; /*!< Structure used for bit access */
AnnaBridge 167:e84263d55307 234 uint32_t w; /*!< Type used for word access */
<> 144:ef7eb2e8f9f7 235 } IPSR_Type;
<> 144:ef7eb2e8f9f7 236
<> 144:ef7eb2e8f9f7 237 /* IPSR Register Definitions */
AnnaBridge 167:e84263d55307 238 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
<> 144:ef7eb2e8f9f7 239 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
<> 144:ef7eb2e8f9f7 240
<> 144:ef7eb2e8f9f7 241
AnnaBridge 167:e84263d55307 242 /**
AnnaBridge 167:e84263d55307 243 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
<> 144:ef7eb2e8f9f7 244 */
<> 144:ef7eb2e8f9f7 245 typedef union
<> 144:ef7eb2e8f9f7 246 {
<> 144:ef7eb2e8f9f7 247 struct
<> 144:ef7eb2e8f9f7 248 {
AnnaBridge 167:e84263d55307 249 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
AnnaBridge 167:e84263d55307 250 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
AnnaBridge 167:e84263d55307 251 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
AnnaBridge 167:e84263d55307 252 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
AnnaBridge 167:e84263d55307 253 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
AnnaBridge 167:e84263d55307 254 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
AnnaBridge 167:e84263d55307 255 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
AnnaBridge 167:e84263d55307 256 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
AnnaBridge 167:e84263d55307 257 } b; /*!< Structure used for bit access */
AnnaBridge 167:e84263d55307 258 uint32_t w; /*!< Type used for word access */
<> 144:ef7eb2e8f9f7 259 } xPSR_Type;
<> 144:ef7eb2e8f9f7 260
<> 144:ef7eb2e8f9f7 261 /* xPSR Register Definitions */
AnnaBridge 167:e84263d55307 262 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
<> 144:ef7eb2e8f9f7 263 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
<> 144:ef7eb2e8f9f7 264
AnnaBridge 167:e84263d55307 265 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
<> 144:ef7eb2e8f9f7 266 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
<> 144:ef7eb2e8f9f7 267
AnnaBridge 167:e84263d55307 268 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
<> 144:ef7eb2e8f9f7 269 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
<> 144:ef7eb2e8f9f7 270
AnnaBridge 167:e84263d55307 271 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
<> 144:ef7eb2e8f9f7 272 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
<> 144:ef7eb2e8f9f7 273
AnnaBridge 167:e84263d55307 274 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
<> 144:ef7eb2e8f9f7 275 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
<> 144:ef7eb2e8f9f7 276
AnnaBridge 167:e84263d55307 277 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
<> 144:ef7eb2e8f9f7 278 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
<> 144:ef7eb2e8f9f7 279
<> 144:ef7eb2e8f9f7 280
AnnaBridge 167:e84263d55307 281 /**
AnnaBridge 167:e84263d55307 282 \brief Union type to access the Control Registers (CONTROL).
<> 144:ef7eb2e8f9f7 283 */
<> 144:ef7eb2e8f9f7 284 typedef union
<> 144:ef7eb2e8f9f7 285 {
<> 144:ef7eb2e8f9f7 286 struct
<> 144:ef7eb2e8f9f7 287 {
AnnaBridge 167:e84263d55307 288 uint32_t _reserved0:1; /*!< bit: 0 Reserved */
AnnaBridge 167:e84263d55307 289 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
AnnaBridge 167:e84263d55307 290 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
AnnaBridge 167:e84263d55307 291 } b; /*!< Structure used for bit access */
AnnaBridge 167:e84263d55307 292 uint32_t w; /*!< Type used for word access */
<> 144:ef7eb2e8f9f7 293 } CONTROL_Type;
<> 144:ef7eb2e8f9f7 294
<> 144:ef7eb2e8f9f7 295 /* CONTROL Register Definitions */
AnnaBridge 167:e84263d55307 296 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
<> 144:ef7eb2e8f9f7 297 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
<> 144:ef7eb2e8f9f7 298
<> 144:ef7eb2e8f9f7 299 /*@} end of group CMSIS_CORE */
<> 144:ef7eb2e8f9f7 300
<> 144:ef7eb2e8f9f7 301
AnnaBridge 167:e84263d55307 302 /**
AnnaBridge 167:e84263d55307 303 \ingroup CMSIS_core_register
AnnaBridge 167:e84263d55307 304 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
AnnaBridge 167:e84263d55307 305 \brief Type definitions for the NVIC Registers
<> 144:ef7eb2e8f9f7 306 @{
<> 144:ef7eb2e8f9f7 307 */
<> 144:ef7eb2e8f9f7 308
AnnaBridge 167:e84263d55307 309 /**
AnnaBridge 167:e84263d55307 310 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
<> 144:ef7eb2e8f9f7 311 */
<> 144:ef7eb2e8f9f7 312 typedef struct
<> 144:ef7eb2e8f9f7 313 {
AnnaBridge 167:e84263d55307 314 __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
AnnaBridge 167:e84263d55307 315 uint32_t RESERVED0[31U];
AnnaBridge 167:e84263d55307 316 __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
AnnaBridge 167:e84263d55307 317 uint32_t RSERVED1[31U];
AnnaBridge 167:e84263d55307 318 __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
AnnaBridge 167:e84263d55307 319 uint32_t RESERVED2[31U];
AnnaBridge 167:e84263d55307 320 __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
AnnaBridge 167:e84263d55307 321 uint32_t RESERVED3[31U];
AnnaBridge 167:e84263d55307 322 uint32_t RESERVED4[64U];
AnnaBridge 167:e84263d55307 323 __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
<> 144:ef7eb2e8f9f7 324 } NVIC_Type;
<> 144:ef7eb2e8f9f7 325
<> 144:ef7eb2e8f9f7 326 /*@} end of group CMSIS_NVIC */
<> 144:ef7eb2e8f9f7 327
<> 144:ef7eb2e8f9f7 328
AnnaBridge 167:e84263d55307 329 /**
AnnaBridge 167:e84263d55307 330 \ingroup CMSIS_core_register
AnnaBridge 167:e84263d55307 331 \defgroup CMSIS_SCB System Control Block (SCB)
AnnaBridge 167:e84263d55307 332 \brief Type definitions for the System Control Block Registers
<> 144:ef7eb2e8f9f7 333 @{
<> 144:ef7eb2e8f9f7 334 */
<> 144:ef7eb2e8f9f7 335
AnnaBridge 167:e84263d55307 336 /**
AnnaBridge 167:e84263d55307 337 \brief Structure type to access the System Control Block (SCB).
<> 144:ef7eb2e8f9f7 338 */
<> 144:ef7eb2e8f9f7 339 typedef struct
<> 144:ef7eb2e8f9f7 340 {
AnnaBridge 167:e84263d55307 341 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
AnnaBridge 167:e84263d55307 342 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
AnnaBridge 167:e84263d55307 343 uint32_t RESERVED0;
AnnaBridge 167:e84263d55307 344 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
AnnaBridge 167:e84263d55307 345 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
AnnaBridge 167:e84263d55307 346 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
AnnaBridge 167:e84263d55307 347 uint32_t RESERVED1;
AnnaBridge 167:e84263d55307 348 __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
AnnaBridge 167:e84263d55307 349 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
<> 144:ef7eb2e8f9f7 350 } SCB_Type;
<> 144:ef7eb2e8f9f7 351
<> 144:ef7eb2e8f9f7 352 /* SCB CPUID Register Definitions */
AnnaBridge 167:e84263d55307 353 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
<> 144:ef7eb2e8f9f7 354 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
<> 144:ef7eb2e8f9f7 355
AnnaBridge 167:e84263d55307 356 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
<> 144:ef7eb2e8f9f7 357 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
<> 144:ef7eb2e8f9f7 358
AnnaBridge 167:e84263d55307 359 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
<> 144:ef7eb2e8f9f7 360 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
<> 144:ef7eb2e8f9f7 361
AnnaBridge 167:e84263d55307 362 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
<> 144:ef7eb2e8f9f7 363 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
<> 144:ef7eb2e8f9f7 364
AnnaBridge 167:e84263d55307 365 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
<> 144:ef7eb2e8f9f7 366 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
<> 144:ef7eb2e8f9f7 367
<> 144:ef7eb2e8f9f7 368 /* SCB Interrupt Control State Register Definitions */
AnnaBridge 167:e84263d55307 369 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
<> 144:ef7eb2e8f9f7 370 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
<> 144:ef7eb2e8f9f7 371
AnnaBridge 167:e84263d55307 372 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
<> 144:ef7eb2e8f9f7 373 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
<> 144:ef7eb2e8f9f7 374
AnnaBridge 167:e84263d55307 375 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
<> 144:ef7eb2e8f9f7 376 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
<> 144:ef7eb2e8f9f7 377
AnnaBridge 167:e84263d55307 378 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
<> 144:ef7eb2e8f9f7 379 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
<> 144:ef7eb2e8f9f7 380
AnnaBridge 167:e84263d55307 381 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
<> 144:ef7eb2e8f9f7 382 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
<> 144:ef7eb2e8f9f7 383
AnnaBridge 167:e84263d55307 384 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
<> 144:ef7eb2e8f9f7 385 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
<> 144:ef7eb2e8f9f7 386
AnnaBridge 167:e84263d55307 387 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
<> 144:ef7eb2e8f9f7 388 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
<> 144:ef7eb2e8f9f7 389
AnnaBridge 167:e84263d55307 390 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
<> 144:ef7eb2e8f9f7 391 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
<> 144:ef7eb2e8f9f7 392
AnnaBridge 167:e84263d55307 393 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
<> 144:ef7eb2e8f9f7 394 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
<> 144:ef7eb2e8f9f7 395
<> 144:ef7eb2e8f9f7 396 /* SCB Application Interrupt and Reset Control Register Definitions */
AnnaBridge 167:e84263d55307 397 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
<> 144:ef7eb2e8f9f7 398 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
<> 144:ef7eb2e8f9f7 399
AnnaBridge 167:e84263d55307 400 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
<> 144:ef7eb2e8f9f7 401 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
<> 144:ef7eb2e8f9f7 402
AnnaBridge 167:e84263d55307 403 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
<> 144:ef7eb2e8f9f7 404 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
<> 144:ef7eb2e8f9f7 405
AnnaBridge 167:e84263d55307 406 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
<> 144:ef7eb2e8f9f7 407 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
<> 144:ef7eb2e8f9f7 408
AnnaBridge 167:e84263d55307 409 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
<> 144:ef7eb2e8f9f7 410 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
<> 144:ef7eb2e8f9f7 411
<> 144:ef7eb2e8f9f7 412 /* SCB System Control Register Definitions */
AnnaBridge 167:e84263d55307 413 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
<> 144:ef7eb2e8f9f7 414 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
<> 144:ef7eb2e8f9f7 415
AnnaBridge 167:e84263d55307 416 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
<> 144:ef7eb2e8f9f7 417 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
<> 144:ef7eb2e8f9f7 418
AnnaBridge 167:e84263d55307 419 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
<> 144:ef7eb2e8f9f7 420 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
<> 144:ef7eb2e8f9f7 421
<> 144:ef7eb2e8f9f7 422 /* SCB Configuration Control Register Definitions */
AnnaBridge 167:e84263d55307 423 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
<> 144:ef7eb2e8f9f7 424 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
<> 144:ef7eb2e8f9f7 425
AnnaBridge 167:e84263d55307 426 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
<> 144:ef7eb2e8f9f7 427 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
<> 144:ef7eb2e8f9f7 428
<> 144:ef7eb2e8f9f7 429 /* SCB System Handler Control and State Register Definitions */
AnnaBridge 167:e84263d55307 430 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
<> 144:ef7eb2e8f9f7 431 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
<> 144:ef7eb2e8f9f7 432
<> 144:ef7eb2e8f9f7 433 /*@} end of group CMSIS_SCB */
<> 144:ef7eb2e8f9f7 434
<> 144:ef7eb2e8f9f7 435
AnnaBridge 167:e84263d55307 436 /**
AnnaBridge 167:e84263d55307 437 \ingroup CMSIS_core_register
AnnaBridge 167:e84263d55307 438 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
AnnaBridge 167:e84263d55307 439 \brief Type definitions for the System Timer Registers.
<> 144:ef7eb2e8f9f7 440 @{
<> 144:ef7eb2e8f9f7 441 */
<> 144:ef7eb2e8f9f7 442
AnnaBridge 167:e84263d55307 443 /**
AnnaBridge 167:e84263d55307 444 \brief Structure type to access the System Timer (SysTick).
<> 144:ef7eb2e8f9f7 445 */
<> 144:ef7eb2e8f9f7 446 typedef struct
<> 144:ef7eb2e8f9f7 447 {
AnnaBridge 167:e84263d55307 448 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
AnnaBridge 167:e84263d55307 449 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
AnnaBridge 167:e84263d55307 450 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
AnnaBridge 167:e84263d55307 451 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
<> 144:ef7eb2e8f9f7 452 } SysTick_Type;
<> 144:ef7eb2e8f9f7 453
<> 144:ef7eb2e8f9f7 454 /* SysTick Control / Status Register Definitions */
AnnaBridge 167:e84263d55307 455 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
<> 144:ef7eb2e8f9f7 456 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
<> 144:ef7eb2e8f9f7 457
AnnaBridge 167:e84263d55307 458 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
<> 144:ef7eb2e8f9f7 459 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
<> 144:ef7eb2e8f9f7 460
AnnaBridge 167:e84263d55307 461 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
<> 144:ef7eb2e8f9f7 462 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
<> 144:ef7eb2e8f9f7 463
AnnaBridge 167:e84263d55307 464 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
<> 144:ef7eb2e8f9f7 465 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
<> 144:ef7eb2e8f9f7 466
<> 144:ef7eb2e8f9f7 467 /* SysTick Reload Register Definitions */
AnnaBridge 167:e84263d55307 468 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
<> 144:ef7eb2e8f9f7 469 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
<> 144:ef7eb2e8f9f7 470
<> 144:ef7eb2e8f9f7 471 /* SysTick Current Register Definitions */
AnnaBridge 167:e84263d55307 472 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
<> 144:ef7eb2e8f9f7 473 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
<> 144:ef7eb2e8f9f7 474
<> 144:ef7eb2e8f9f7 475 /* SysTick Calibration Register Definitions */
AnnaBridge 167:e84263d55307 476 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
<> 144:ef7eb2e8f9f7 477 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
<> 144:ef7eb2e8f9f7 478
AnnaBridge 167:e84263d55307 479 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
<> 144:ef7eb2e8f9f7 480 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
<> 144:ef7eb2e8f9f7 481
AnnaBridge 167:e84263d55307 482 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
<> 144:ef7eb2e8f9f7 483 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
<> 144:ef7eb2e8f9f7 484
<> 144:ef7eb2e8f9f7 485 /*@} end of group CMSIS_SysTick */
<> 144:ef7eb2e8f9f7 486
<> 144:ef7eb2e8f9f7 487
AnnaBridge 167:e84263d55307 488 /**
AnnaBridge 167:e84263d55307 489 \ingroup CMSIS_core_register
AnnaBridge 167:e84263d55307 490 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
AnnaBridge 167:e84263d55307 491 \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
AnnaBridge 167:e84263d55307 492 Therefore they are not covered by the Cortex-M0 header file.
<> 144:ef7eb2e8f9f7 493 @{
<> 144:ef7eb2e8f9f7 494 */
<> 144:ef7eb2e8f9f7 495 /*@} end of group CMSIS_CoreDebug */
<> 144:ef7eb2e8f9f7 496
<> 144:ef7eb2e8f9f7 497
AnnaBridge 167:e84263d55307 498 /**
AnnaBridge 167:e84263d55307 499 \ingroup CMSIS_core_register
AnnaBridge 167:e84263d55307 500 \defgroup CMSIS_core_bitfield Core register bit field macros
AnnaBridge 167:e84263d55307 501 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
<> 144:ef7eb2e8f9f7 502 @{
<> 144:ef7eb2e8f9f7 503 */
<> 144:ef7eb2e8f9f7 504
AnnaBridge 167:e84263d55307 505 /**
AnnaBridge 167:e84263d55307 506 \brief Mask and shift a bit field value for use in a register bit range.
AnnaBridge 167:e84263d55307 507 \param[in] field Name of the register bit field.
AnnaBridge 167:e84263d55307 508 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
AnnaBridge 167:e84263d55307 509 \return Masked and shifted value.
AnnaBridge 167:e84263d55307 510 */
AnnaBridge 167:e84263d55307 511 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
AnnaBridge 167:e84263d55307 512
AnnaBridge 167:e84263d55307 513 /**
AnnaBridge 167:e84263d55307 514 \brief Mask and shift a register value to extract a bit filed value.
AnnaBridge 167:e84263d55307 515 \param[in] field Name of the register bit field.
AnnaBridge 167:e84263d55307 516 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
AnnaBridge 167:e84263d55307 517 \return Masked and shifted bit field value.
AnnaBridge 167:e84263d55307 518 */
AnnaBridge 167:e84263d55307 519 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
AnnaBridge 167:e84263d55307 520
AnnaBridge 167:e84263d55307 521 /*@} end of group CMSIS_core_bitfield */
AnnaBridge 167:e84263d55307 522
AnnaBridge 167:e84263d55307 523
AnnaBridge 167:e84263d55307 524 /**
AnnaBridge 167:e84263d55307 525 \ingroup CMSIS_core_register
AnnaBridge 167:e84263d55307 526 \defgroup CMSIS_core_base Core Definitions
AnnaBridge 167:e84263d55307 527 \brief Definitions for base addresses, unions, and structures.
AnnaBridge 167:e84263d55307 528 @{
AnnaBridge 167:e84263d55307 529 */
AnnaBridge 167:e84263d55307 530
AnnaBridge 167:e84263d55307 531 /* Memory mapping of Core Hardware */
<> 144:ef7eb2e8f9f7 532 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
AnnaBridge 167:e84263d55307 533 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
AnnaBridge 167:e84263d55307 534 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
<> 144:ef7eb2e8f9f7 535 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
<> 144:ef7eb2e8f9f7 536
AnnaBridge 167:e84263d55307 537 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
AnnaBridge 167:e84263d55307 538 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
AnnaBridge 167:e84263d55307 539 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
<> 144:ef7eb2e8f9f7 540
<> 144:ef7eb2e8f9f7 541
<> 144:ef7eb2e8f9f7 542 /*@} */
<> 144:ef7eb2e8f9f7 543
<> 144:ef7eb2e8f9f7 544
<> 144:ef7eb2e8f9f7 545
<> 144:ef7eb2e8f9f7 546 /*******************************************************************************
<> 144:ef7eb2e8f9f7 547 * Hardware Abstraction Layer
<> 144:ef7eb2e8f9f7 548 Core Function Interface contains:
<> 144:ef7eb2e8f9f7 549 - Core NVIC Functions
<> 144:ef7eb2e8f9f7 550 - Core SysTick Functions
<> 144:ef7eb2e8f9f7 551 - Core Register Access Functions
<> 144:ef7eb2e8f9f7 552 ******************************************************************************/
AnnaBridge 167:e84263d55307 553 /**
AnnaBridge 167:e84263d55307 554 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
<> 144:ef7eb2e8f9f7 555 */
<> 144:ef7eb2e8f9f7 556
<> 144:ef7eb2e8f9f7 557
<> 144:ef7eb2e8f9f7 558
<> 144:ef7eb2e8f9f7 559 /* ########################## NVIC functions #################################### */
AnnaBridge 167:e84263d55307 560 /**
AnnaBridge 167:e84263d55307 561 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 167:e84263d55307 562 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
AnnaBridge 167:e84263d55307 563 \brief Functions that manage interrupts and exceptions via the NVIC.
AnnaBridge 167:e84263d55307 564 @{
<> 144:ef7eb2e8f9f7 565 */
<> 144:ef7eb2e8f9f7 566
AnnaBridge 167:e84263d55307 567 #ifdef CMSIS_NVIC_VIRTUAL
AnnaBridge 167:e84263d55307 568 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge 167:e84263d55307 569 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
AnnaBridge 167:e84263d55307 570 #endif
AnnaBridge 167:e84263d55307 571 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge 167:e84263d55307 572 #else
AnnaBridge 167:e84263d55307 573 /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0 */
AnnaBridge 167:e84263d55307 574 /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0 */
AnnaBridge 167:e84263d55307 575 #define NVIC_EnableIRQ __NVIC_EnableIRQ
AnnaBridge 167:e84263d55307 576 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
AnnaBridge 167:e84263d55307 577 #define NVIC_DisableIRQ __NVIC_DisableIRQ
AnnaBridge 167:e84263d55307 578 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
AnnaBridge 167:e84263d55307 579 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
AnnaBridge 167:e84263d55307 580 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
AnnaBridge 167:e84263d55307 581 /*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */
AnnaBridge 167:e84263d55307 582 #define NVIC_SetPriority __NVIC_SetPriority
AnnaBridge 167:e84263d55307 583 #define NVIC_GetPriority __NVIC_GetPriority
AnnaBridge 167:e84263d55307 584 #define NVIC_SystemReset __NVIC_SystemReset
AnnaBridge 167:e84263d55307 585 #endif /* CMSIS_NVIC_VIRTUAL */
AnnaBridge 167:e84263d55307 586
AnnaBridge 167:e84263d55307 587 #ifdef CMSIS_VECTAB_VIRTUAL
AnnaBridge 167:e84263d55307 588 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge 167:e84263d55307 589 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
AnnaBridge 167:e84263d55307 590 #endif
AnnaBridge 167:e84263d55307 591 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge 167:e84263d55307 592 #else
AnnaBridge 167:e84263d55307 593 #define NVIC_SetVector __NVIC_SetVector
AnnaBridge 167:e84263d55307 594 #define NVIC_GetVector __NVIC_GetVector
AnnaBridge 167:e84263d55307 595 #endif /* (CMSIS_VECTAB_VIRTUAL) */
AnnaBridge 167:e84263d55307 596
AnnaBridge 167:e84263d55307 597 #define NVIC_USER_IRQ_OFFSET 16
AnnaBridge 167:e84263d55307 598
AnnaBridge 167:e84263d55307 599
<> 144:ef7eb2e8f9f7 600 /* Interrupt Priorities are WORD accessible only under ARMv6M */
<> 144:ef7eb2e8f9f7 601 /* The following MACROS handle generation of the register offset and byte masks */
<> 144:ef7eb2e8f9f7 602 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
<> 144:ef7eb2e8f9f7 603 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
<> 144:ef7eb2e8f9f7 604 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
<> 144:ef7eb2e8f9f7 605
<> 144:ef7eb2e8f9f7 606
AnnaBridge 167:e84263d55307 607 /**
AnnaBridge 167:e84263d55307 608 \brief Enable Interrupt
AnnaBridge 167:e84263d55307 609 \details Enables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge 167:e84263d55307 610 \param [in] IRQn Device specific interrupt number.
AnnaBridge 167:e84263d55307 611 \note IRQn must not be negative.
<> 144:ef7eb2e8f9f7 612 */
AnnaBridge 167:e84263d55307 613 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
<> 144:ef7eb2e8f9f7 614 {
AnnaBridge 167:e84263d55307 615 if ((int32_t)(IRQn) >= 0)
AnnaBridge 167:e84263d55307 616 {
AnnaBridge 167:e84263d55307 617 NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 167:e84263d55307 618 }
<> 144:ef7eb2e8f9f7 619 }
<> 144:ef7eb2e8f9f7 620
<> 144:ef7eb2e8f9f7 621
AnnaBridge 167:e84263d55307 622 /**
AnnaBridge 167:e84263d55307 623 \brief Get Interrupt Enable status
AnnaBridge 167:e84263d55307 624 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
AnnaBridge 167:e84263d55307 625 \param [in] IRQn Device specific interrupt number.
AnnaBridge 167:e84263d55307 626 \return 0 Interrupt is not enabled.
AnnaBridge 167:e84263d55307 627 \return 1 Interrupt is enabled.
AnnaBridge 167:e84263d55307 628 \note IRQn must not be negative.
<> 144:ef7eb2e8f9f7 629 */
AnnaBridge 167:e84263d55307 630 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
<> 144:ef7eb2e8f9f7 631 {
AnnaBridge 167:e84263d55307 632 if ((int32_t)(IRQn) >= 0)
AnnaBridge 167:e84263d55307 633 {
AnnaBridge 167:e84263d55307 634 return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 167:e84263d55307 635 }
AnnaBridge 167:e84263d55307 636 else
AnnaBridge 167:e84263d55307 637 {
AnnaBridge 167:e84263d55307 638 return(0U);
AnnaBridge 167:e84263d55307 639 }
<> 144:ef7eb2e8f9f7 640 }
<> 144:ef7eb2e8f9f7 641
<> 144:ef7eb2e8f9f7 642
AnnaBridge 167:e84263d55307 643 /**
AnnaBridge 167:e84263d55307 644 \brief Disable Interrupt
AnnaBridge 167:e84263d55307 645 \details Disables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge 167:e84263d55307 646 \param [in] IRQn Device specific interrupt number.
AnnaBridge 167:e84263d55307 647 \note IRQn must not be negative.
<> 144:ef7eb2e8f9f7 648 */
AnnaBridge 167:e84263d55307 649 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
<> 144:ef7eb2e8f9f7 650 {
AnnaBridge 167:e84263d55307 651 if ((int32_t)(IRQn) >= 0)
AnnaBridge 167:e84263d55307 652 {
AnnaBridge 167:e84263d55307 653 NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 167:e84263d55307 654 __DSB();
AnnaBridge 167:e84263d55307 655 __ISB();
AnnaBridge 167:e84263d55307 656 }
<> 144:ef7eb2e8f9f7 657 }
<> 144:ef7eb2e8f9f7 658
<> 144:ef7eb2e8f9f7 659
AnnaBridge 167:e84263d55307 660 /**
AnnaBridge 167:e84263d55307 661 \brief Get Pending Interrupt
AnnaBridge 167:e84263d55307 662 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
AnnaBridge 167:e84263d55307 663 \param [in] IRQn Device specific interrupt number.
AnnaBridge 167:e84263d55307 664 \return 0 Interrupt status is not pending.
AnnaBridge 167:e84263d55307 665 \return 1 Interrupt status is pending.
AnnaBridge 167:e84263d55307 666 \note IRQn must not be negative.
<> 144:ef7eb2e8f9f7 667 */
AnnaBridge 167:e84263d55307 668 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
<> 144:ef7eb2e8f9f7 669 {
AnnaBridge 167:e84263d55307 670 if ((int32_t)(IRQn) >= 0)
AnnaBridge 167:e84263d55307 671 {
AnnaBridge 167:e84263d55307 672 return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 167:e84263d55307 673 }
AnnaBridge 167:e84263d55307 674 else
AnnaBridge 167:e84263d55307 675 {
AnnaBridge 167:e84263d55307 676 return(0U);
AnnaBridge 167:e84263d55307 677 }
<> 144:ef7eb2e8f9f7 678 }
<> 144:ef7eb2e8f9f7 679
<> 144:ef7eb2e8f9f7 680
AnnaBridge 167:e84263d55307 681 /**
AnnaBridge 167:e84263d55307 682 \brief Set Pending Interrupt
AnnaBridge 167:e84263d55307 683 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge 167:e84263d55307 684 \param [in] IRQn Device specific interrupt number.
AnnaBridge 167:e84263d55307 685 \note IRQn must not be negative.
<> 144:ef7eb2e8f9f7 686 */
AnnaBridge 167:e84263d55307 687 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
<> 144:ef7eb2e8f9f7 688 {
AnnaBridge 167:e84263d55307 689 if ((int32_t)(IRQn) >= 0)
AnnaBridge 167:e84263d55307 690 {
AnnaBridge 167:e84263d55307 691 NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 144:ef7eb2e8f9f7 692 }
<> 144:ef7eb2e8f9f7 693 }
<> 144:ef7eb2e8f9f7 694
<> 144:ef7eb2e8f9f7 695
AnnaBridge 167:e84263d55307 696 /**
AnnaBridge 167:e84263d55307 697 \brief Clear Pending Interrupt
AnnaBridge 167:e84263d55307 698 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge 167:e84263d55307 699 \param [in] IRQn Device specific interrupt number.
AnnaBridge 167:e84263d55307 700 \note IRQn must not be negative.
AnnaBridge 167:e84263d55307 701 */
AnnaBridge 167:e84263d55307 702 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
AnnaBridge 167:e84263d55307 703 {
AnnaBridge 167:e84263d55307 704 if ((int32_t)(IRQn) >= 0)
AnnaBridge 167:e84263d55307 705 {
AnnaBridge 167:e84263d55307 706 NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 167:e84263d55307 707 }
AnnaBridge 167:e84263d55307 708 }
<> 144:ef7eb2e8f9f7 709
<> 144:ef7eb2e8f9f7 710
AnnaBridge 167:e84263d55307 711 /**
AnnaBridge 167:e84263d55307 712 \brief Set Interrupt Priority
AnnaBridge 167:e84263d55307 713 \details Sets the priority of a device specific interrupt or a processor exception.
AnnaBridge 167:e84263d55307 714 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 167:e84263d55307 715 or negative to specify a processor exception.
AnnaBridge 167:e84263d55307 716 \param [in] IRQn Interrupt number.
AnnaBridge 167:e84263d55307 717 \param [in] priority Priority to set.
AnnaBridge 167:e84263d55307 718 \note The priority cannot be set for every processor exception.
<> 144:ef7eb2e8f9f7 719 */
AnnaBridge 167:e84263d55307 720 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
<> 144:ef7eb2e8f9f7 721 {
AnnaBridge 167:e84263d55307 722 if ((int32_t)(IRQn) >= 0)
AnnaBridge 167:e84263d55307 723 {
AnnaBridge 167:e84263d55307 724 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
AnnaBridge 167:e84263d55307 725 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
<> 144:ef7eb2e8f9f7 726 }
AnnaBridge 167:e84263d55307 727 else
AnnaBridge 167:e84263d55307 728 {
AnnaBridge 167:e84263d55307 729 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
AnnaBridge 167:e84263d55307 730 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
<> 144:ef7eb2e8f9f7 731 }
<> 144:ef7eb2e8f9f7 732 }
<> 144:ef7eb2e8f9f7 733
<> 144:ef7eb2e8f9f7 734
AnnaBridge 167:e84263d55307 735 /**
AnnaBridge 167:e84263d55307 736 \brief Get Interrupt Priority
AnnaBridge 167:e84263d55307 737 \details Reads the priority of a device specific interrupt or a processor exception.
AnnaBridge 167:e84263d55307 738 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 167:e84263d55307 739 or negative to specify a processor exception.
AnnaBridge 167:e84263d55307 740 \param [in] IRQn Interrupt number.
AnnaBridge 167:e84263d55307 741 \return Interrupt Priority.
AnnaBridge 167:e84263d55307 742 Value is aligned automatically to the implemented priority bits of the microcontroller.
<> 144:ef7eb2e8f9f7 743 */
AnnaBridge 167:e84263d55307 744 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
AnnaBridge 167:e84263d55307 745 {
AnnaBridge 167:e84263d55307 746
AnnaBridge 167:e84263d55307 747 if ((int32_t)(IRQn) >= 0)
AnnaBridge 167:e84263d55307 748 {
AnnaBridge 167:e84263d55307 749 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge 167:e84263d55307 750 }
AnnaBridge 167:e84263d55307 751 else
AnnaBridge 167:e84263d55307 752 {
AnnaBridge 167:e84263d55307 753 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge 167:e84263d55307 754 }
AnnaBridge 167:e84263d55307 755 }
AnnaBridge 167:e84263d55307 756
AnnaBridge 167:e84263d55307 757
AnnaBridge 167:e84263d55307 758 /**
AnnaBridge 167:e84263d55307 759 \brief Set Interrupt Vector
AnnaBridge 167:e84263d55307 760 \details Sets an interrupt vector in SRAM based interrupt vector table.
AnnaBridge 167:e84263d55307 761 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 167:e84263d55307 762 or negative to specify a processor exception.
AnnaBridge 167:e84263d55307 763 Address 0 must be mapped to SRAM.
AnnaBridge 167:e84263d55307 764 \param [in] IRQn Interrupt number
AnnaBridge 167:e84263d55307 765 \param [in] vector Address of interrupt handler function
AnnaBridge 167:e84263d55307 766 */
AnnaBridge 167:e84263d55307 767 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
<> 144:ef7eb2e8f9f7 768 {
AnnaBridge 167:e84263d55307 769 uint32_t *vectors = (uint32_t *)0x0U;
AnnaBridge 167:e84263d55307 770 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
AnnaBridge 167:e84263d55307 771 }
AnnaBridge 167:e84263d55307 772
AnnaBridge 167:e84263d55307 773
AnnaBridge 167:e84263d55307 774 /**
AnnaBridge 167:e84263d55307 775 \brief Get Interrupt Vector
AnnaBridge 167:e84263d55307 776 \details Reads an interrupt vector from interrupt vector table.
AnnaBridge 167:e84263d55307 777 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 167:e84263d55307 778 or negative to specify a processor exception.
AnnaBridge 167:e84263d55307 779 \param [in] IRQn Interrupt number.
AnnaBridge 167:e84263d55307 780 \return Address of interrupt handler function
AnnaBridge 167:e84263d55307 781 */
AnnaBridge 167:e84263d55307 782 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
AnnaBridge 167:e84263d55307 783 {
AnnaBridge 167:e84263d55307 784 uint32_t *vectors = (uint32_t *)0x0U;
AnnaBridge 167:e84263d55307 785 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
AnnaBridge 167:e84263d55307 786 }
AnnaBridge 167:e84263d55307 787
AnnaBridge 167:e84263d55307 788
AnnaBridge 167:e84263d55307 789 /**
AnnaBridge 167:e84263d55307 790 \brief System Reset
AnnaBridge 167:e84263d55307 791 \details Initiates a system reset request to reset the MCU.
AnnaBridge 167:e84263d55307 792 */
AnnaBridge 167:e84263d55307 793 __STATIC_INLINE void __NVIC_SystemReset(void)
AnnaBridge 167:e84263d55307 794 {
AnnaBridge 167:e84263d55307 795 __DSB(); /* Ensure all outstanding memory accesses included
AnnaBridge 167:e84263d55307 796 buffered write are completed before reset */
<> 144:ef7eb2e8f9f7 797 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
<> 144:ef7eb2e8f9f7 798 SCB_AIRCR_SYSRESETREQ_Msk);
AnnaBridge 167:e84263d55307 799 __DSB(); /* Ensure completion of memory access */
AnnaBridge 167:e84263d55307 800
AnnaBridge 167:e84263d55307 801 for(;;) /* wait until reset */
AnnaBridge 167:e84263d55307 802 {
AnnaBridge 167:e84263d55307 803 __NOP();
AnnaBridge 167:e84263d55307 804 }
<> 144:ef7eb2e8f9f7 805 }
<> 144:ef7eb2e8f9f7 806
<> 144:ef7eb2e8f9f7 807 /*@} end of CMSIS_Core_NVICFunctions */
<> 144:ef7eb2e8f9f7 808
<> 144:ef7eb2e8f9f7 809
AnnaBridge 167:e84263d55307 810 /* ########################## FPU functions #################################### */
AnnaBridge 167:e84263d55307 811 /**
AnnaBridge 167:e84263d55307 812 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 167:e84263d55307 813 \defgroup CMSIS_Core_FpuFunctions FPU Functions
AnnaBridge 167:e84263d55307 814 \brief Function that provides FPU type.
<> 144:ef7eb2e8f9f7 815 @{
<> 144:ef7eb2e8f9f7 816 */
<> 144:ef7eb2e8f9f7 817
AnnaBridge 167:e84263d55307 818 /**
AnnaBridge 167:e84263d55307 819 \brief get FPU type
AnnaBridge 167:e84263d55307 820 \details returns the FPU type
AnnaBridge 167:e84263d55307 821 \returns
AnnaBridge 167:e84263d55307 822 - \b 0: No FPU
AnnaBridge 167:e84263d55307 823 - \b 1: Single precision FPU
AnnaBridge 167:e84263d55307 824 - \b 2: Double + Single precision FPU
AnnaBridge 167:e84263d55307 825 */
AnnaBridge 167:e84263d55307 826 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
AnnaBridge 167:e84263d55307 827 {
AnnaBridge 167:e84263d55307 828 return 0U; /* No FPU */
AnnaBridge 167:e84263d55307 829 }
<> 144:ef7eb2e8f9f7 830
<> 144:ef7eb2e8f9f7 831
AnnaBridge 167:e84263d55307 832 /*@} end of CMSIS_Core_FpuFunctions */
AnnaBridge 167:e84263d55307 833
AnnaBridge 167:e84263d55307 834
<> 144:ef7eb2e8f9f7 835
AnnaBridge 167:e84263d55307 836 /* ################################## SysTick function ############################################ */
AnnaBridge 167:e84263d55307 837 /**
AnnaBridge 167:e84263d55307 838 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 167:e84263d55307 839 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
AnnaBridge 167:e84263d55307 840 \brief Functions that configure the System.
AnnaBridge 167:e84263d55307 841 @{
AnnaBridge 167:e84263d55307 842 */
<> 144:ef7eb2e8f9f7 843
AnnaBridge 167:e84263d55307 844 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
<> 144:ef7eb2e8f9f7 845
AnnaBridge 167:e84263d55307 846 /**
AnnaBridge 167:e84263d55307 847 \brief System Tick Configuration
AnnaBridge 167:e84263d55307 848 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
AnnaBridge 167:e84263d55307 849 Counter is in free running mode to generate periodic interrupts.
AnnaBridge 167:e84263d55307 850 \param [in] ticks Number of ticks between two interrupts.
AnnaBridge 167:e84263d55307 851 \return 0 Function succeeded.
AnnaBridge 167:e84263d55307 852 \return 1 Function failed.
AnnaBridge 167:e84263d55307 853 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
AnnaBridge 167:e84263d55307 854 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
AnnaBridge 167:e84263d55307 855 must contain a vendor-specific implementation of this function.
<> 144:ef7eb2e8f9f7 856 */
<> 144:ef7eb2e8f9f7 857 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
<> 144:ef7eb2e8f9f7 858 {
AnnaBridge 167:e84263d55307 859 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
AnnaBridge 167:e84263d55307 860 {
AnnaBridge 167:e84263d55307 861 return (1UL); /* Reload value impossible */
AnnaBridge 167:e84263d55307 862 }
<> 144:ef7eb2e8f9f7 863
<> 144:ef7eb2e8f9f7 864 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
<> 144:ef7eb2e8f9f7 865 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
<> 144:ef7eb2e8f9f7 866 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
<> 144:ef7eb2e8f9f7 867 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
<> 144:ef7eb2e8f9f7 868 SysTick_CTRL_TICKINT_Msk |
<> 144:ef7eb2e8f9f7 869 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
<> 144:ef7eb2e8f9f7 870 return (0UL); /* Function successful */
<> 144:ef7eb2e8f9f7 871 }
<> 144:ef7eb2e8f9f7 872
<> 144:ef7eb2e8f9f7 873 #endif
<> 144:ef7eb2e8f9f7 874
<> 144:ef7eb2e8f9f7 875 /*@} end of CMSIS_Core_SysTickFunctions */
<> 144:ef7eb2e8f9f7 876
<> 144:ef7eb2e8f9f7 877
<> 144:ef7eb2e8f9f7 878
<> 144:ef7eb2e8f9f7 879
<> 144:ef7eb2e8f9f7 880 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 881 }
<> 144:ef7eb2e8f9f7 882 #endif
<> 144:ef7eb2e8f9f7 883
<> 144:ef7eb2e8f9f7 884 #endif /* __CORE_CM0_H_DEPENDANT */
<> 144:ef7eb2e8f9f7 885
<> 144:ef7eb2e8f9f7 886 #endif /* __CMSIS_GENERIC */