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cmsis/core_sc000.h@167:e84263d55307, 2017-06-21 (annotated)

Committer:
AnnaBridge
Date:
Wed Jun 21 17:46:44 2017 +0100
Revision:
167:e84263d55307
Parent:
152:9a67f0b066fc 
This updates the lib to the mbed lib v 145

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 25:ac5b0a371348 1 /**************************************************************************//**
mbed_official 25:ac5b0a371348 2 * @file core_sc000.h
mbed_official 25:ac5b0a371348 3 * @brief CMSIS SC000 Core Peripheral Access Layer Header File
AnnaBridge 167:e84263d55307 4 * @version V5.0.2
AnnaBridge 167:e84263d55307 5 * @date 13. February 2017
AnnaBridge 167:e84263d55307 6 ******************************************************************************/
AnnaBridge 167:e84263d55307 7 /*
AnnaBridge 167:e84263d55307 8 * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
AnnaBridge 167:e84263d55307 9 *
AnnaBridge 167:e84263d55307 10 * SPDX-License-Identifier: Apache-2.0
mbed_official 25:ac5b0a371348 11 *
AnnaBridge 167:e84263d55307 12 * Licensed under the Apache License, Version 2.0 (the License); you may
AnnaBridge 167:e84263d55307 13 * not use this file except in compliance with the License.
AnnaBridge 167:e84263d55307 14 * You may obtain a copy of the License at
AnnaBridge 167:e84263d55307 15 *
AnnaBridge 167:e84263d55307 16 * www.apache.org/licenses/LICENSE-2.0
mbed_official 25:ac5b0a371348 17 *
AnnaBridge 167:e84263d55307 18 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 167:e84263d55307 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
AnnaBridge 167:e84263d55307 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 167:e84263d55307 21 * See the License for the specific language governing permissions and
AnnaBridge 167:e84263d55307 22 * limitations under the License.
AnnaBridge 167:e84263d55307 23 */
mbed_official 25:ac5b0a371348 24
AnnaBridge 167:e84263d55307 25 #if defined ( __ICCARM__ )
AnnaBridge 167:e84263d55307 26 #pragma system_include /* treat file as system include file for MISRA check */
AnnaBridge 167:e84263d55307 27 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge 167:e84263d55307 28 #pragma clang system_header /* treat file as system include file */
mbed_official 25:ac5b0a371348 29 #endif
mbed_official 25:ac5b0a371348 30
mbed_official 25:ac5b0a371348 31 #ifndef __CORE_SC000_H_GENERIC
mbed_official 25:ac5b0a371348 32 #define __CORE_SC000_H_GENERIC
mbed_official 25:ac5b0a371348 33
AnnaBridge 167:e84263d55307 34 #include <stdint.h>
AnnaBridge 167:e84263d55307 35
mbed_official 25:ac5b0a371348 36 #ifdef __cplusplus
mbed_official 25:ac5b0a371348 37 extern "C" {
mbed_official 25:ac5b0a371348 38 #endif
mbed_official 25:ac5b0a371348 39
AnnaBridge 167:e84263d55307 40 /**
AnnaBridge 167:e84263d55307 41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
mbed_official 25:ac5b0a371348 42 CMSIS violates the following MISRA-C:2004 rules:
mbed_official 25:ac5b0a371348 43
mbed_official 25:ac5b0a371348 44 \li Required Rule 8.5, object/function definition in header file.<br>
mbed_official 25:ac5b0a371348 45 Function definitions in header files are used to allow 'inlining'.
mbed_official 25:ac5b0a371348 46
mbed_official 25:ac5b0a371348 47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
mbed_official 25:ac5b0a371348 48 Unions are used for effective representation of core registers.
mbed_official 25:ac5b0a371348 49
mbed_official 25:ac5b0a371348 50 \li Advisory Rule 19.7, Function-like macro defined.<br>
mbed_official 25:ac5b0a371348 51 Function-like macros are used to allow more efficient code.
mbed_official 25:ac5b0a371348 52 */
mbed_official 25:ac5b0a371348 53
mbed_official 25:ac5b0a371348 54
mbed_official 25:ac5b0a371348 55 /*******************************************************************************
mbed_official 25:ac5b0a371348 56 * CMSIS definitions
mbed_official 25:ac5b0a371348 57 ******************************************************************************/
AnnaBridge 167:e84263d55307 58 /**
AnnaBridge 167:e84263d55307 59 \ingroup SC000
mbed_official 25:ac5b0a371348 60 @{
mbed_official 25:ac5b0a371348 61 */
mbed_official 25:ac5b0a371348 62
mbed_official 25:ac5b0a371348 63 /* CMSIS SC000 definitions */
AnnaBridge 167:e84263d55307 64 #define __SC000_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */
AnnaBridge 167:e84263d55307 65 #define __SC000_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */
AnnaBridge 167:e84263d55307 66 #define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \
AnnaBridge 167:e84263d55307 67 __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
mbed_official 25:ac5b0a371348 68
AnnaBridge 167:e84263d55307 69 #define __CORTEX_SC (000U) /*!< Cortex secure core */
mbed_official 25:ac5b0a371348 70
mbed_official 25:ac5b0a371348 71 /** __FPU_USED indicates whether an FPU is used or not.
mbed_official 25:ac5b0a371348 72 This core does not support an FPU at all
mbed_official 25:ac5b0a371348 73 */
AnnaBridge 167:e84263d55307 74 #define __FPU_USED 0U
mbed_official 25:ac5b0a371348 75
mbed_official 25:ac5b0a371348 76 #if defined ( __CC_ARM )
mbed_official 25:ac5b0a371348 77 #if defined __TARGET_FPU_VFP
AnnaBridge 167:e84263d55307 78 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 167:e84263d55307 79 #endif
AnnaBridge 167:e84263d55307 80
AnnaBridge 167:e84263d55307 81 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge 167:e84263d55307 82 #if defined __ARM_PCS_VFP
AnnaBridge 167:e84263d55307 83 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mbed_official 25:ac5b0a371348 84 #endif
mbed_official 25:ac5b0a371348 85
mbed_official 25:ac5b0a371348 86 #elif defined ( __GNUC__ )
mbed_official 25:ac5b0a371348 87 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
AnnaBridge 167:e84263d55307 88 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mbed_official 25:ac5b0a371348 89 #endif
mbed_official 25:ac5b0a371348 90
mbed_official 25:ac5b0a371348 91 #elif defined ( __ICCARM__ )
mbed_official 25:ac5b0a371348 92 #if defined __ARMVFP__
AnnaBridge 167:e84263d55307 93 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mbed_official 25:ac5b0a371348 94 #endif
mbed_official 25:ac5b0a371348 95
AnnaBridge 167:e84263d55307 96 #elif defined ( __TI_ARM__ )
AnnaBridge 167:e84263d55307 97 #if defined __TI_VFP_SUPPORT__
AnnaBridge 167:e84263d55307 98 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mbed_official 25:ac5b0a371348 99 #endif
mbed_official 25:ac5b0a371348 100
mbed_official 25:ac5b0a371348 101 #elif defined ( __TASKING__ )
mbed_official 25:ac5b0a371348 102 #if defined __FPU_VFP__
mbed_official 25:ac5b0a371348 103 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mbed_official 25:ac5b0a371348 104 #endif
mbed_official 25:ac5b0a371348 105
AnnaBridge 167:e84263d55307 106 #elif defined ( __CSMC__ )
AnnaBridge 167:e84263d55307 107 #if ( __CSMC__ & 0x400U)
mbed_official 25:ac5b0a371348 108 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mbed_official 25:ac5b0a371348 109 #endif
AnnaBridge 167:e84263d55307 110
mbed_official 25:ac5b0a371348 111 #endif
mbed_official 25:ac5b0a371348 112
AnnaBridge 167:e84263d55307 113 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
AnnaBridge 167:e84263d55307 114
mbed_official 25:ac5b0a371348 115
mbed_official 25:ac5b0a371348 116 #ifdef __cplusplus
mbed_official 25:ac5b0a371348 117 }
mbed_official 25:ac5b0a371348 118 #endif
mbed_official 25:ac5b0a371348 119
mbed_official 25:ac5b0a371348 120 #endif /* __CORE_SC000_H_GENERIC */
mbed_official 25:ac5b0a371348 121
mbed_official 25:ac5b0a371348 122 #ifndef __CMSIS_GENERIC
mbed_official 25:ac5b0a371348 123
mbed_official 25:ac5b0a371348 124 #ifndef __CORE_SC000_H_DEPENDANT
mbed_official 25:ac5b0a371348 125 #define __CORE_SC000_H_DEPENDANT
mbed_official 25:ac5b0a371348 126
mbed_official 25:ac5b0a371348 127 #ifdef __cplusplus
mbed_official 25:ac5b0a371348 128 extern "C" {
mbed_official 25:ac5b0a371348 129 #endif
mbed_official 25:ac5b0a371348 130
mbed_official 25:ac5b0a371348 131 /* check device defines and use defaults */
mbed_official 25:ac5b0a371348 132 #if defined __CHECK_DEVICE_DEFINES
mbed_official 25:ac5b0a371348 133 #ifndef __SC000_REV
AnnaBridge 167:e84263d55307 134 #define __SC000_REV 0x0000U
mbed_official 25:ac5b0a371348 135 #warning "__SC000_REV not defined in device header file; using default!"
mbed_official 25:ac5b0a371348 136 #endif
mbed_official 25:ac5b0a371348 137
mbed_official 25:ac5b0a371348 138 #ifndef __MPU_PRESENT
AnnaBridge 167:e84263d55307 139 #define __MPU_PRESENT 0U
mbed_official 25:ac5b0a371348 140 #warning "__MPU_PRESENT not defined in device header file; using default!"
mbed_official 25:ac5b0a371348 141 #endif
mbed_official 25:ac5b0a371348 142
mbed_official 25:ac5b0a371348 143 #ifndef __NVIC_PRIO_BITS
AnnaBridge 167:e84263d55307 144 #define __NVIC_PRIO_BITS 2U
mbed_official 25:ac5b0a371348 145 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
mbed_official 25:ac5b0a371348 146 #endif
mbed_official 25:ac5b0a371348 147
mbed_official 25:ac5b0a371348 148 #ifndef __Vendor_SysTickConfig
AnnaBridge 167:e84263d55307 149 #define __Vendor_SysTickConfig 0U
mbed_official 25:ac5b0a371348 150 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
mbed_official 25:ac5b0a371348 151 #endif
mbed_official 25:ac5b0a371348 152 #endif
mbed_official 25:ac5b0a371348 153
mbed_official 25:ac5b0a371348 154 /* IO definitions (access restrictions to peripheral registers) */
mbed_official 25:ac5b0a371348 155 /**
mbed_official 25:ac5b0a371348 156 \defgroup CMSIS_glob_defs CMSIS Global Defines
mbed_official 25:ac5b0a371348 157
mbed_official 25:ac5b0a371348 158 <strong>IO Type Qualifiers</strong> are used
mbed_official 25:ac5b0a371348 159 \li to specify the access to peripheral variables.
mbed_official 25:ac5b0a371348 160 \li for automatic generation of peripheral register debug information.
mbed_official 25:ac5b0a371348 161 */
mbed_official 25:ac5b0a371348 162 #ifdef __cplusplus
AnnaBridge 167:e84263d55307 163 #define __I volatile /*!< Defines 'read only' permissions */
mbed_official 25:ac5b0a371348 164 #else
AnnaBridge 167:e84263d55307 165 #define __I volatile const /*!< Defines 'read only' permissions */
mbed_official 25:ac5b0a371348 166 #endif
AnnaBridge 167:e84263d55307 167 #define __O volatile /*!< Defines 'write only' permissions */
AnnaBridge 167:e84263d55307 168 #define __IO volatile /*!< Defines 'read / write' permissions */
AnnaBridge 167:e84263d55307 169
AnnaBridge 167:e84263d55307 170 /* following defines should be used for structure members */
AnnaBridge 167:e84263d55307 171 #define __IM volatile const /*! Defines 'read only' structure member permissions */
AnnaBridge 167:e84263d55307 172 #define __OM volatile /*! Defines 'write only' structure member permissions */
AnnaBridge 167:e84263d55307 173 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
mbed_official 25:ac5b0a371348 174
mbed_official 25:ac5b0a371348 175 /*@} end of group SC000 */
mbed_official 25:ac5b0a371348 176
mbed_official 25:ac5b0a371348 177
mbed_official 25:ac5b0a371348 178
mbed_official 25:ac5b0a371348 179 /*******************************************************************************
mbed_official 25:ac5b0a371348 180 * Register Abstraction
mbed_official 25:ac5b0a371348 181 Core Register contain:
mbed_official 25:ac5b0a371348 182 - Core Register
mbed_official 25:ac5b0a371348 183 - Core NVIC Register
mbed_official 25:ac5b0a371348 184 - Core SCB Register
mbed_official 25:ac5b0a371348 185 - Core SysTick Register
mbed_official 25:ac5b0a371348 186 - Core MPU Register
mbed_official 25:ac5b0a371348 187 ******************************************************************************/
AnnaBridge 167:e84263d55307 188 /**
AnnaBridge 167:e84263d55307 189 \defgroup CMSIS_core_register Defines and Type Definitions
AnnaBridge 167:e84263d55307 190 \brief Type definitions and defines for Cortex-M processor based devices.
mbed_official 25:ac5b0a371348 191 */
mbed_official 25:ac5b0a371348 192
AnnaBridge 167:e84263d55307 193 /**
AnnaBridge 167:e84263d55307 194 \ingroup CMSIS_core_register
AnnaBridge 167:e84263d55307 195 \defgroup CMSIS_CORE Status and Control Registers
AnnaBridge 167:e84263d55307 196 \brief Core Register type definitions.
mbed_official 25:ac5b0a371348 197 @{
mbed_official 25:ac5b0a371348 198 */
mbed_official 25:ac5b0a371348 199
AnnaBridge 167:e84263d55307 200 /**
AnnaBridge 167:e84263d55307 201 \brief Union type to access the Application Program Status Register (APSR).
mbed_official 25:ac5b0a371348 202 */
mbed_official 25:ac5b0a371348 203 typedef union
mbed_official 25:ac5b0a371348 204 {
mbed_official 25:ac5b0a371348 205 struct
mbed_official 25:ac5b0a371348 206 {
AnnaBridge 167:e84263d55307 207 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
AnnaBridge 167:e84263d55307 208 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
AnnaBridge 167:e84263d55307 209 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
AnnaBridge 167:e84263d55307 210 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
AnnaBridge 167:e84263d55307 211 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
AnnaBridge 167:e84263d55307 212 } b; /*!< Structure used for bit access */
AnnaBridge 167:e84263d55307 213 uint32_t w; /*!< Type used for word access */
mbed_official 25:ac5b0a371348 214 } APSR_Type;
mbed_official 25:ac5b0a371348 215
mbed_official 25:ac5b0a371348 216 /* APSR Register Definitions */
AnnaBridge 167:e84263d55307 217 #define APSR_N_Pos 31U /*!< APSR: N Position */
mbed_official 25:ac5b0a371348 218 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
mbed_official 25:ac5b0a371348 219
AnnaBridge 167:e84263d55307 220 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
mbed_official 25:ac5b0a371348 221 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
mbed_official 25:ac5b0a371348 222
AnnaBridge 167:e84263d55307 223 #define APSR_C_Pos 29U /*!< APSR: C Position */
mbed_official 25:ac5b0a371348 224 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
mbed_official 25:ac5b0a371348 225
AnnaBridge 167:e84263d55307 226 #define APSR_V_Pos 28U /*!< APSR: V Position */
mbed_official 25:ac5b0a371348 227 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
mbed_official 25:ac5b0a371348 228
mbed_official 25:ac5b0a371348 229
AnnaBridge 167:e84263d55307 230 /**
AnnaBridge 167:e84263d55307 231 \brief Union type to access the Interrupt Program Status Register (IPSR).
mbed_official 25:ac5b0a371348 232 */
mbed_official 25:ac5b0a371348 233 typedef union
mbed_official 25:ac5b0a371348 234 {
mbed_official 25:ac5b0a371348 235 struct
mbed_official 25:ac5b0a371348 236 {
AnnaBridge 167:e84263d55307 237 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
AnnaBridge 167:e84263d55307 238 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
AnnaBridge 167:e84263d55307 239 } b; /*!< Structure used for bit access */
AnnaBridge 167:e84263d55307 240 uint32_t w; /*!< Type used for word access */
mbed_official 25:ac5b0a371348 241 } IPSR_Type;
mbed_official 25:ac5b0a371348 242
mbed_official 25:ac5b0a371348 243 /* IPSR Register Definitions */
AnnaBridge 167:e84263d55307 244 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
mbed_official 25:ac5b0a371348 245 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
mbed_official 25:ac5b0a371348 246
mbed_official 25:ac5b0a371348 247
AnnaBridge 167:e84263d55307 248 /**
AnnaBridge 167:e84263d55307 249 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
mbed_official 25:ac5b0a371348 250 */
mbed_official 25:ac5b0a371348 251 typedef union
mbed_official 25:ac5b0a371348 252 {
mbed_official 25:ac5b0a371348 253 struct
mbed_official 25:ac5b0a371348 254 {
AnnaBridge 167:e84263d55307 255 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
AnnaBridge 167:e84263d55307 256 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
AnnaBridge 167:e84263d55307 257 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
AnnaBridge 167:e84263d55307 258 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
AnnaBridge 167:e84263d55307 259 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
AnnaBridge 167:e84263d55307 260 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
AnnaBridge 167:e84263d55307 261 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
AnnaBridge 167:e84263d55307 262 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
AnnaBridge 167:e84263d55307 263 } b; /*!< Structure used for bit access */
AnnaBridge 167:e84263d55307 264 uint32_t w; /*!< Type used for word access */
mbed_official 25:ac5b0a371348 265 } xPSR_Type;
mbed_official 25:ac5b0a371348 266
mbed_official 25:ac5b0a371348 267 /* xPSR Register Definitions */
AnnaBridge 167:e84263d55307 268 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
mbed_official 25:ac5b0a371348 269 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
mbed_official 25:ac5b0a371348 270
AnnaBridge 167:e84263d55307 271 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
mbed_official 25:ac5b0a371348 272 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
mbed_official 25:ac5b0a371348 273
AnnaBridge 167:e84263d55307 274 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
mbed_official 25:ac5b0a371348 275 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
mbed_official 25:ac5b0a371348 276
AnnaBridge 167:e84263d55307 277 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
mbed_official 25:ac5b0a371348 278 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
mbed_official 25:ac5b0a371348 279
AnnaBridge 167:e84263d55307 280 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
mbed_official 25:ac5b0a371348 281 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
mbed_official 25:ac5b0a371348 282
AnnaBridge 167:e84263d55307 283 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
mbed_official 25:ac5b0a371348 284 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
mbed_official 25:ac5b0a371348 285
mbed_official 25:ac5b0a371348 286
AnnaBridge 167:e84263d55307 287 /**
AnnaBridge 167:e84263d55307 288 \brief Union type to access the Control Registers (CONTROL).
mbed_official 25:ac5b0a371348 289 */
mbed_official 25:ac5b0a371348 290 typedef union
mbed_official 25:ac5b0a371348 291 {
mbed_official 25:ac5b0a371348 292 struct
mbed_official 25:ac5b0a371348 293 {
AnnaBridge 167:e84263d55307 294 uint32_t _reserved0:1; /*!< bit: 0 Reserved */
AnnaBridge 167:e84263d55307 295 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
AnnaBridge 167:e84263d55307 296 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
AnnaBridge 167:e84263d55307 297 } b; /*!< Structure used for bit access */
AnnaBridge 167:e84263d55307 298 uint32_t w; /*!< Type used for word access */
mbed_official 25:ac5b0a371348 299 } CONTROL_Type;
mbed_official 25:ac5b0a371348 300
mbed_official 25:ac5b0a371348 301 /* CONTROL Register Definitions */
AnnaBridge 167:e84263d55307 302 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
mbed_official 25:ac5b0a371348 303 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
mbed_official 25:ac5b0a371348 304
mbed_official 25:ac5b0a371348 305 /*@} end of group CMSIS_CORE */
mbed_official 25:ac5b0a371348 306
mbed_official 25:ac5b0a371348 307
AnnaBridge 167:e84263d55307 308 /**
AnnaBridge 167:e84263d55307 309 \ingroup CMSIS_core_register
AnnaBridge 167:e84263d55307 310 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
AnnaBridge 167:e84263d55307 311 \brief Type definitions for the NVIC Registers
mbed_official 25:ac5b0a371348 312 @{
mbed_official 25:ac5b0a371348 313 */
mbed_official 25:ac5b0a371348 314
AnnaBridge 167:e84263d55307 315 /**
AnnaBridge 167:e84263d55307 316 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
mbed_official 25:ac5b0a371348 317 */
mbed_official 25:ac5b0a371348 318 typedef struct
mbed_official 25:ac5b0a371348 319 {
AnnaBridge 167:e84263d55307 320 __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
AnnaBridge 167:e84263d55307 321 uint32_t RESERVED0[31U];
AnnaBridge 167:e84263d55307 322 __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
AnnaBridge 167:e84263d55307 323 uint32_t RSERVED1[31U];
AnnaBridge 167:e84263d55307 324 __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
AnnaBridge 167:e84263d55307 325 uint32_t RESERVED2[31U];
AnnaBridge 167:e84263d55307 326 __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
AnnaBridge 167:e84263d55307 327 uint32_t RESERVED3[31U];
AnnaBridge 167:e84263d55307 328 uint32_t RESERVED4[64U];
AnnaBridge 167:e84263d55307 329 __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
mbed_official 25:ac5b0a371348 330 } NVIC_Type;
mbed_official 25:ac5b0a371348 331
mbed_official 25:ac5b0a371348 332 /*@} end of group CMSIS_NVIC */
mbed_official 25:ac5b0a371348 333
mbed_official 25:ac5b0a371348 334
AnnaBridge 167:e84263d55307 335 /**
AnnaBridge 167:e84263d55307 336 \ingroup CMSIS_core_register
AnnaBridge 167:e84263d55307 337 \defgroup CMSIS_SCB System Control Block (SCB)
AnnaBridge 167:e84263d55307 338 \brief Type definitions for the System Control Block Registers
mbed_official 25:ac5b0a371348 339 @{
mbed_official 25:ac5b0a371348 340 */
mbed_official 25:ac5b0a371348 341
AnnaBridge 167:e84263d55307 342 /**
AnnaBridge 167:e84263d55307 343 \brief Structure type to access the System Control Block (SCB).
mbed_official 25:ac5b0a371348 344 */
mbed_official 25:ac5b0a371348 345 typedef struct
mbed_official 25:ac5b0a371348 346 {
AnnaBridge 167:e84263d55307 347 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
AnnaBridge 167:e84263d55307 348 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
AnnaBridge 167:e84263d55307 349 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
AnnaBridge 167:e84263d55307 350 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
AnnaBridge 167:e84263d55307 351 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
AnnaBridge 167:e84263d55307 352 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
AnnaBridge 167:e84263d55307 353 uint32_t RESERVED0[1U];
AnnaBridge 167:e84263d55307 354 __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
AnnaBridge 167:e84263d55307 355 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
AnnaBridge 167:e84263d55307 356 uint32_t RESERVED1[154U];
AnnaBridge 167:e84263d55307 357 __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
mbed_official 25:ac5b0a371348 358 } SCB_Type;
mbed_official 25:ac5b0a371348 359
mbed_official 25:ac5b0a371348 360 /* SCB CPUID Register Definitions */
AnnaBridge 167:e84263d55307 361 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
mbed_official 25:ac5b0a371348 362 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
mbed_official 25:ac5b0a371348 363
AnnaBridge 167:e84263d55307 364 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
mbed_official 25:ac5b0a371348 365 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
mbed_official 25:ac5b0a371348 366
AnnaBridge 167:e84263d55307 367 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
mbed_official 25:ac5b0a371348 368 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
mbed_official 25:ac5b0a371348 369
AnnaBridge 167:e84263d55307 370 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
mbed_official 25:ac5b0a371348 371 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
mbed_official 25:ac5b0a371348 372
AnnaBridge 167:e84263d55307 373 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
mbed_official 25:ac5b0a371348 374 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
mbed_official 25:ac5b0a371348 375
mbed_official 25:ac5b0a371348 376 /* SCB Interrupt Control State Register Definitions */
AnnaBridge 167:e84263d55307 377 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
mbed_official 25:ac5b0a371348 378 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
mbed_official 25:ac5b0a371348 379
AnnaBridge 167:e84263d55307 380 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
mbed_official 25:ac5b0a371348 381 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
mbed_official 25:ac5b0a371348 382
AnnaBridge 167:e84263d55307 383 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
mbed_official 25:ac5b0a371348 384 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
mbed_official 25:ac5b0a371348 385
AnnaBridge 167:e84263d55307 386 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
mbed_official 25:ac5b0a371348 387 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
mbed_official 25:ac5b0a371348 388
AnnaBridge 167:e84263d55307 389 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
mbed_official 25:ac5b0a371348 390 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
mbed_official 25:ac5b0a371348 391
AnnaBridge 167:e84263d55307 392 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
mbed_official 25:ac5b0a371348 393 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
mbed_official 25:ac5b0a371348 394
AnnaBridge 167:e84263d55307 395 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
mbed_official 25:ac5b0a371348 396 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
mbed_official 25:ac5b0a371348 397
AnnaBridge 167:e84263d55307 398 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
mbed_official 25:ac5b0a371348 399 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
mbed_official 25:ac5b0a371348 400
AnnaBridge 167:e84263d55307 401 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
mbed_official 25:ac5b0a371348 402 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
mbed_official 25:ac5b0a371348 403
mbed_official 25:ac5b0a371348 404 /* SCB Interrupt Control State Register Definitions */
AnnaBridge 167:e84263d55307 405 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
mbed_official 25:ac5b0a371348 406 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
mbed_official 25:ac5b0a371348 407
mbed_official 25:ac5b0a371348 408 /* SCB Application Interrupt and Reset Control Register Definitions */
AnnaBridge 167:e84263d55307 409 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
mbed_official 25:ac5b0a371348 410 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
mbed_official 25:ac5b0a371348 411
AnnaBridge 167:e84263d55307 412 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
mbed_official 25:ac5b0a371348 413 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
mbed_official 25:ac5b0a371348 414
AnnaBridge 167:e84263d55307 415 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
mbed_official 25:ac5b0a371348 416 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
mbed_official 25:ac5b0a371348 417
AnnaBridge 167:e84263d55307 418 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
mbed_official 25:ac5b0a371348 419 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
mbed_official 25:ac5b0a371348 420
AnnaBridge 167:e84263d55307 421 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
mbed_official 25:ac5b0a371348 422 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
mbed_official 25:ac5b0a371348 423
mbed_official 25:ac5b0a371348 424 /* SCB System Control Register Definitions */
AnnaBridge 167:e84263d55307 425 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
mbed_official 25:ac5b0a371348 426 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
mbed_official 25:ac5b0a371348 427
AnnaBridge 167:e84263d55307 428 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
mbed_official 25:ac5b0a371348 429 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
mbed_official 25:ac5b0a371348 430
AnnaBridge 167:e84263d55307 431 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
mbed_official 25:ac5b0a371348 432 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
mbed_official 25:ac5b0a371348 433
mbed_official 25:ac5b0a371348 434 /* SCB Configuration Control Register Definitions */
AnnaBridge 167:e84263d55307 435 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
mbed_official 25:ac5b0a371348 436 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
mbed_official 25:ac5b0a371348 437
AnnaBridge 167:e84263d55307 438 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
mbed_official 25:ac5b0a371348 439 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
mbed_official 25:ac5b0a371348 440
mbed_official 25:ac5b0a371348 441 /* SCB System Handler Control and State Register Definitions */
AnnaBridge 167:e84263d55307 442 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
mbed_official 25:ac5b0a371348 443 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
mbed_official 25:ac5b0a371348 444
mbed_official 25:ac5b0a371348 445 /*@} end of group CMSIS_SCB */
mbed_official 25:ac5b0a371348 446
mbed_official 25:ac5b0a371348 447
AnnaBridge 167:e84263d55307 448 /**
AnnaBridge 167:e84263d55307 449 \ingroup CMSIS_core_register
AnnaBridge 167:e84263d55307 450 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
AnnaBridge 167:e84263d55307 451 \brief Type definitions for the System Control and ID Register not in the SCB
mbed_official 25:ac5b0a371348 452 @{
mbed_official 25:ac5b0a371348 453 */
mbed_official 25:ac5b0a371348 454
AnnaBridge 167:e84263d55307 455 /**
AnnaBridge 167:e84263d55307 456 \brief Structure type to access the System Control and ID Register not in the SCB.
mbed_official 25:ac5b0a371348 457 */
mbed_official 25:ac5b0a371348 458 typedef struct
mbed_official 25:ac5b0a371348 459 {
AnnaBridge 167:e84263d55307 460 uint32_t RESERVED0[2U];
AnnaBridge 167:e84263d55307 461 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
mbed_official 25:ac5b0a371348 462 } SCnSCB_Type;
mbed_official 25:ac5b0a371348 463
mbed_official 25:ac5b0a371348 464 /* Auxiliary Control Register Definitions */
AnnaBridge 167:e84263d55307 465 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
mbed_official 25:ac5b0a371348 466 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
mbed_official 25:ac5b0a371348 467
mbed_official 25:ac5b0a371348 468 /*@} end of group CMSIS_SCnotSCB */
mbed_official 25:ac5b0a371348 469
mbed_official 25:ac5b0a371348 470
AnnaBridge 167:e84263d55307 471 /**
AnnaBridge 167:e84263d55307 472 \ingroup CMSIS_core_register
AnnaBridge 167:e84263d55307 473 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
AnnaBridge 167:e84263d55307 474 \brief Type definitions for the System Timer Registers.
mbed_official 25:ac5b0a371348 475 @{
mbed_official 25:ac5b0a371348 476 */
mbed_official 25:ac5b0a371348 477
AnnaBridge 167:e84263d55307 478 /**
AnnaBridge 167:e84263d55307 479 \brief Structure type to access the System Timer (SysTick).
mbed_official 25:ac5b0a371348 480 */
mbed_official 25:ac5b0a371348 481 typedef struct
mbed_official 25:ac5b0a371348 482 {
AnnaBridge 167:e84263d55307 483 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
AnnaBridge 167:e84263d55307 484 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
AnnaBridge 167:e84263d55307 485 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
AnnaBridge 167:e84263d55307 486 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
mbed_official 25:ac5b0a371348 487 } SysTick_Type;
mbed_official 25:ac5b0a371348 488
mbed_official 25:ac5b0a371348 489 /* SysTick Control / Status Register Definitions */
AnnaBridge 167:e84263d55307 490 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
mbed_official 25:ac5b0a371348 491 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
mbed_official 25:ac5b0a371348 492
AnnaBridge 167:e84263d55307 493 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
mbed_official 25:ac5b0a371348 494 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
mbed_official 25:ac5b0a371348 495
AnnaBridge 167:e84263d55307 496 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
mbed_official 25:ac5b0a371348 497 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
mbed_official 25:ac5b0a371348 498
AnnaBridge 167:e84263d55307 499 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
mbed_official 25:ac5b0a371348 500 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
mbed_official 25:ac5b0a371348 501
mbed_official 25:ac5b0a371348 502 /* SysTick Reload Register Definitions */
AnnaBridge 167:e84263d55307 503 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
mbed_official 25:ac5b0a371348 504 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
mbed_official 25:ac5b0a371348 505
mbed_official 25:ac5b0a371348 506 /* SysTick Current Register Definitions */
AnnaBridge 167:e84263d55307 507 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
mbed_official 25:ac5b0a371348 508 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
mbed_official 25:ac5b0a371348 509
mbed_official 25:ac5b0a371348 510 /* SysTick Calibration Register Definitions */
AnnaBridge 167:e84263d55307 511 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
mbed_official 25:ac5b0a371348 512 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
mbed_official 25:ac5b0a371348 513
AnnaBridge 167:e84263d55307 514 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
mbed_official 25:ac5b0a371348 515 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
mbed_official 25:ac5b0a371348 516
AnnaBridge 167:e84263d55307 517 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
mbed_official 25:ac5b0a371348 518 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
mbed_official 25:ac5b0a371348 519
mbed_official 25:ac5b0a371348 520 /*@} end of group CMSIS_SysTick */
mbed_official 25:ac5b0a371348 521
AnnaBridge 167:e84263d55307 522 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge 167:e84263d55307 523 /**
AnnaBridge 167:e84263d55307 524 \ingroup CMSIS_core_register
AnnaBridge 167:e84263d55307 525 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
AnnaBridge 167:e84263d55307 526 \brief Type definitions for the Memory Protection Unit (MPU)
mbed_official 25:ac5b0a371348 527 @{
mbed_official 25:ac5b0a371348 528 */
mbed_official 25:ac5b0a371348 529
AnnaBridge 167:e84263d55307 530 /**
AnnaBridge 167:e84263d55307 531 \brief Structure type to access the Memory Protection Unit (MPU).
mbed_official 25:ac5b0a371348 532 */
mbed_official 25:ac5b0a371348 533 typedef struct
mbed_official 25:ac5b0a371348 534 {
AnnaBridge 167:e84263d55307 535 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
AnnaBridge 167:e84263d55307 536 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
AnnaBridge 167:e84263d55307 537 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
AnnaBridge 167:e84263d55307 538 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
AnnaBridge 167:e84263d55307 539 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
mbed_official 25:ac5b0a371348 540 } MPU_Type;
mbed_official 25:ac5b0a371348 541
AnnaBridge 167:e84263d55307 542 /* MPU Type Register Definitions */
AnnaBridge 167:e84263d55307 543 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
mbed_official 25:ac5b0a371348 544 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
mbed_official 25:ac5b0a371348 545
AnnaBridge 167:e84263d55307 546 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
mbed_official 25:ac5b0a371348 547 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
mbed_official 25:ac5b0a371348 548
AnnaBridge 167:e84263d55307 549 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
mbed_official 25:ac5b0a371348 550 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
mbed_official 25:ac5b0a371348 551
AnnaBridge 167:e84263d55307 552 /* MPU Control Register Definitions */
AnnaBridge 167:e84263d55307 553 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
mbed_official 25:ac5b0a371348 554 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
mbed_official 25:ac5b0a371348 555
AnnaBridge 167:e84263d55307 556 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
mbed_official 25:ac5b0a371348 557 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
mbed_official 25:ac5b0a371348 558
AnnaBridge 167:e84263d55307 559 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
mbed_official 25:ac5b0a371348 560 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
mbed_official 25:ac5b0a371348 561
AnnaBridge 167:e84263d55307 562 /* MPU Region Number Register Definitions */
AnnaBridge 167:e84263d55307 563 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
mbed_official 25:ac5b0a371348 564 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
mbed_official 25:ac5b0a371348 565
AnnaBridge 167:e84263d55307 566 /* MPU Region Base Address Register Definitions */
AnnaBridge 167:e84263d55307 567 #define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
mbed_official 25:ac5b0a371348 568 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
mbed_official 25:ac5b0a371348 569
AnnaBridge 167:e84263d55307 570 #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
mbed_official 25:ac5b0a371348 571 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
mbed_official 25:ac5b0a371348 572
AnnaBridge 167:e84263d55307 573 #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
mbed_official 25:ac5b0a371348 574 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
mbed_official 25:ac5b0a371348 575
AnnaBridge 167:e84263d55307 576 /* MPU Region Attribute and Size Register Definitions */
AnnaBridge 167:e84263d55307 577 #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
mbed_official 25:ac5b0a371348 578 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
mbed_official 25:ac5b0a371348 579
AnnaBridge 167:e84263d55307 580 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
mbed_official 25:ac5b0a371348 581 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
mbed_official 25:ac5b0a371348 582
AnnaBridge 167:e84263d55307 583 #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
mbed_official 25:ac5b0a371348 584 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
mbed_official 25:ac5b0a371348 585
AnnaBridge 167:e84263d55307 586 #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
mbed_official 25:ac5b0a371348 587 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
mbed_official 25:ac5b0a371348 588
AnnaBridge 167:e84263d55307 589 #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
mbed_official 25:ac5b0a371348 590 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
mbed_official 25:ac5b0a371348 591
AnnaBridge 167:e84263d55307 592 #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
mbed_official 25:ac5b0a371348 593 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
mbed_official 25:ac5b0a371348 594
AnnaBridge 167:e84263d55307 595 #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
mbed_official 25:ac5b0a371348 596 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
mbed_official 25:ac5b0a371348 597
AnnaBridge 167:e84263d55307 598 #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
mbed_official 25:ac5b0a371348 599 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
mbed_official 25:ac5b0a371348 600
AnnaBridge 167:e84263d55307 601 #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
mbed_official 25:ac5b0a371348 602 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
mbed_official 25:ac5b0a371348 603
AnnaBridge 167:e84263d55307 604 #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
mbed_official 25:ac5b0a371348 605 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
mbed_official 25:ac5b0a371348 606
mbed_official 25:ac5b0a371348 607 /*@} end of group CMSIS_MPU */
mbed_official 25:ac5b0a371348 608 #endif
mbed_official 25:ac5b0a371348 609
mbed_official 25:ac5b0a371348 610
AnnaBridge 167:e84263d55307 611 /**
AnnaBridge 167:e84263d55307 612 \ingroup CMSIS_core_register
AnnaBridge 167:e84263d55307 613 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
AnnaBridge 167:e84263d55307 614 \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
AnnaBridge 167:e84263d55307 615 Therefore they are not covered by the SC000 header file.
mbed_official 25:ac5b0a371348 616 @{
mbed_official 25:ac5b0a371348 617 */
mbed_official 25:ac5b0a371348 618 /*@} end of group CMSIS_CoreDebug */
mbed_official 25:ac5b0a371348 619
mbed_official 25:ac5b0a371348 620
AnnaBridge 167:e84263d55307 621 /**
AnnaBridge 167:e84263d55307 622 \ingroup CMSIS_core_register
AnnaBridge 167:e84263d55307 623 \defgroup CMSIS_core_bitfield Core register bit field macros
AnnaBridge 167:e84263d55307 624 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
mbed_official 25:ac5b0a371348 625 @{
mbed_official 25:ac5b0a371348 626 */
mbed_official 25:ac5b0a371348 627
AnnaBridge 167:e84263d55307 628 /**
AnnaBridge 167:e84263d55307 629 \brief Mask and shift a bit field value for use in a register bit range.
AnnaBridge 167:e84263d55307 630 \param[in] field Name of the register bit field.
AnnaBridge 167:e84263d55307 631 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
AnnaBridge 167:e84263d55307 632 \return Masked and shifted value.
AnnaBridge 167:e84263d55307 633 */
AnnaBridge 167:e84263d55307 634 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
AnnaBridge 167:e84263d55307 635
AnnaBridge 167:e84263d55307 636 /**
AnnaBridge 167:e84263d55307 637 \brief Mask and shift a register value to extract a bit filed value.
AnnaBridge 167:e84263d55307 638 \param[in] field Name of the register bit field.
AnnaBridge 167:e84263d55307 639 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
AnnaBridge 167:e84263d55307 640 \return Masked and shifted bit field value.
AnnaBridge 167:e84263d55307 641 */
AnnaBridge 167:e84263d55307 642 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
AnnaBridge 167:e84263d55307 643
AnnaBridge 167:e84263d55307 644 /*@} end of group CMSIS_core_bitfield */
AnnaBridge 167:e84263d55307 645
AnnaBridge 167:e84263d55307 646
AnnaBridge 167:e84263d55307 647 /**
AnnaBridge 167:e84263d55307 648 \ingroup CMSIS_core_register
AnnaBridge 167:e84263d55307 649 \defgroup CMSIS_core_base Core Definitions
AnnaBridge 167:e84263d55307 650 \brief Definitions for base addresses, unions, and structures.
AnnaBridge 167:e84263d55307 651 @{
AnnaBridge 167:e84263d55307 652 */
AnnaBridge 167:e84263d55307 653
AnnaBridge 167:e84263d55307 654 /* Memory mapping of Core Hardware */
mbed_official 25:ac5b0a371348 655 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
AnnaBridge 167:e84263d55307 656 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
AnnaBridge 167:e84263d55307 657 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
mbed_official 25:ac5b0a371348 658 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
mbed_official 25:ac5b0a371348 659
mbed_official 25:ac5b0a371348 660 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
AnnaBridge 167:e84263d55307 661 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
AnnaBridge 167:e84263d55307 662 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
AnnaBridge 167:e84263d55307 663 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
mbed_official 25:ac5b0a371348 664
AnnaBridge 167:e84263d55307 665 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge 167:e84263d55307 666 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
AnnaBridge 167:e84263d55307 667 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
mbed_official 25:ac5b0a371348 668 #endif
mbed_official 25:ac5b0a371348 669
mbed_official 25:ac5b0a371348 670 /*@} */
mbed_official 25:ac5b0a371348 671
mbed_official 25:ac5b0a371348 672
mbed_official 25:ac5b0a371348 673
mbed_official 25:ac5b0a371348 674 /*******************************************************************************
mbed_official 25:ac5b0a371348 675 * Hardware Abstraction Layer
mbed_official 25:ac5b0a371348 676 Core Function Interface contains:
mbed_official 25:ac5b0a371348 677 - Core NVIC Functions
mbed_official 25:ac5b0a371348 678 - Core SysTick Functions
mbed_official 25:ac5b0a371348 679 - Core Register Access Functions
mbed_official 25:ac5b0a371348 680 ******************************************************************************/
AnnaBridge 167:e84263d55307 681 /**
AnnaBridge 167:e84263d55307 682 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
mbed_official 25:ac5b0a371348 683 */
mbed_official 25:ac5b0a371348 684
mbed_official 25:ac5b0a371348 685
mbed_official 25:ac5b0a371348 686
mbed_official 25:ac5b0a371348 687 /* ########################## NVIC functions #################################### */
AnnaBridge 167:e84263d55307 688 /**
AnnaBridge 167:e84263d55307 689 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 167:e84263d55307 690 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
AnnaBridge 167:e84263d55307 691 \brief Functions that manage interrupts and exceptions via the NVIC.
AnnaBridge 167:e84263d55307 692 @{
mbed_official 25:ac5b0a371348 693 */
mbed_official 25:ac5b0a371348 694
AnnaBridge 167:e84263d55307 695 #ifdef CMSIS_NVIC_VIRTUAL
AnnaBridge 167:e84263d55307 696 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge 167:e84263d55307 697 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
AnnaBridge 167:e84263d55307 698 #endif
AnnaBridge 167:e84263d55307 699 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge 167:e84263d55307 700 #else
AnnaBridge 167:e84263d55307 701 /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */
AnnaBridge 167:e84263d55307 702 /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */
AnnaBridge 167:e84263d55307 703 #define NVIC_EnableIRQ __NVIC_EnableIRQ
AnnaBridge 167:e84263d55307 704 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
AnnaBridge 167:e84263d55307 705 #define NVIC_DisableIRQ __NVIC_DisableIRQ
AnnaBridge 167:e84263d55307 706 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
AnnaBridge 167:e84263d55307 707 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
AnnaBridge 167:e84263d55307 708 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
AnnaBridge 167:e84263d55307 709 /*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */
AnnaBridge 167:e84263d55307 710 #define NVIC_SetPriority __NVIC_SetPriority
AnnaBridge 167:e84263d55307 711 #define NVIC_GetPriority __NVIC_GetPriority
AnnaBridge 167:e84263d55307 712 #define NVIC_SystemReset __NVIC_SystemReset
AnnaBridge 167:e84263d55307 713 #endif /* CMSIS_NVIC_VIRTUAL */
AnnaBridge 167:e84263d55307 714
AnnaBridge 167:e84263d55307 715 #ifdef CMSIS_VECTAB_VIRTUAL
AnnaBridge 167:e84263d55307 716 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge 167:e84263d55307 717 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
AnnaBridge 167:e84263d55307 718 #endif
AnnaBridge 167:e84263d55307 719 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge 167:e84263d55307 720 #else
AnnaBridge 167:e84263d55307 721 #define NVIC_SetVector __NVIC_SetVector
AnnaBridge 167:e84263d55307 722 #define NVIC_GetVector __NVIC_GetVector
AnnaBridge 167:e84263d55307 723 #endif /* (CMSIS_VECTAB_VIRTUAL) */
AnnaBridge 167:e84263d55307 724
AnnaBridge 167:e84263d55307 725 #define NVIC_USER_IRQ_OFFSET 16
AnnaBridge 167:e84263d55307 726
AnnaBridge 167:e84263d55307 727
mbed_official 25:ac5b0a371348 728 /* Interrupt Priorities are WORD accessible only under ARMv6M */
mbed_official 25:ac5b0a371348 729 /* The following MACROS handle generation of the register offset and byte masks */
mbed_official 25:ac5b0a371348 730 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
mbed_official 25:ac5b0a371348 731 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
mbed_official 25:ac5b0a371348 732 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
mbed_official 25:ac5b0a371348 733
mbed_official 25:ac5b0a371348 734
AnnaBridge 167:e84263d55307 735 /**
AnnaBridge 167:e84263d55307 736 \brief Enable Interrupt
AnnaBridge 167:e84263d55307 737 \details Enables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge 167:e84263d55307 738 \param [in] IRQn Device specific interrupt number.
AnnaBridge 167:e84263d55307 739 \note IRQn must not be negative.
mbed_official 25:ac5b0a371348 740 */
AnnaBridge 167:e84263d55307 741 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
mbed_official 25:ac5b0a371348 742 {
AnnaBridge 167:e84263d55307 743 if ((int32_t)(IRQn) >= 0)
AnnaBridge 167:e84263d55307 744 {
AnnaBridge 167:e84263d55307 745 NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 167:e84263d55307 746 }
mbed_official 25:ac5b0a371348 747 }
mbed_official 25:ac5b0a371348 748
mbed_official 25:ac5b0a371348 749
AnnaBridge 167:e84263d55307 750 /**
AnnaBridge 167:e84263d55307 751 \brief Get Interrupt Enable status
AnnaBridge 167:e84263d55307 752 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
AnnaBridge 167:e84263d55307 753 \param [in] IRQn Device specific interrupt number.
AnnaBridge 167:e84263d55307 754 \return 0 Interrupt is not enabled.
AnnaBridge 167:e84263d55307 755 \return 1 Interrupt is enabled.
AnnaBridge 167:e84263d55307 756 \note IRQn must not be negative.
mbed_official 25:ac5b0a371348 757 */
AnnaBridge 167:e84263d55307 758 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
mbed_official 25:ac5b0a371348 759 {
AnnaBridge 167:e84263d55307 760 if ((int32_t)(IRQn) >= 0)
AnnaBridge 167:e84263d55307 761 {
AnnaBridge 167:e84263d55307 762 return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 167:e84263d55307 763 }
AnnaBridge 167:e84263d55307 764 else
AnnaBridge 167:e84263d55307 765 {
AnnaBridge 167:e84263d55307 766 return(0U);
AnnaBridge 167:e84263d55307 767 }
mbed_official 25:ac5b0a371348 768 }
mbed_official 25:ac5b0a371348 769
mbed_official 25:ac5b0a371348 770
AnnaBridge 167:e84263d55307 771 /**
AnnaBridge 167:e84263d55307 772 \brief Disable Interrupt
AnnaBridge 167:e84263d55307 773 \details Disables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge 167:e84263d55307 774 \param [in] IRQn Device specific interrupt number.
AnnaBridge 167:e84263d55307 775 \note IRQn must not be negative.
mbed_official 25:ac5b0a371348 776 */
AnnaBridge 167:e84263d55307 777 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
mbed_official 25:ac5b0a371348 778 {
AnnaBridge 167:e84263d55307 779 if ((int32_t)(IRQn) >= 0)
AnnaBridge 167:e84263d55307 780 {
AnnaBridge 167:e84263d55307 781 NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 167:e84263d55307 782 __DSB();
AnnaBridge 167:e84263d55307 783 __ISB();
AnnaBridge 167:e84263d55307 784 }
mbed_official 25:ac5b0a371348 785 }
mbed_official 25:ac5b0a371348 786
mbed_official 25:ac5b0a371348 787
AnnaBridge 167:e84263d55307 788 /**
AnnaBridge 167:e84263d55307 789 \brief Get Pending Interrupt
AnnaBridge 167:e84263d55307 790 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
AnnaBridge 167:e84263d55307 791 \param [in] IRQn Device specific interrupt number.
AnnaBridge 167:e84263d55307 792 \return 0 Interrupt status is not pending.
AnnaBridge 167:e84263d55307 793 \return 1 Interrupt status is pending.
AnnaBridge 167:e84263d55307 794 \note IRQn must not be negative.
mbed_official 25:ac5b0a371348 795 */
AnnaBridge 167:e84263d55307 796 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
mbed_official 25:ac5b0a371348 797 {
AnnaBridge 167:e84263d55307 798 if ((int32_t)(IRQn) >= 0)
AnnaBridge 167:e84263d55307 799 {
AnnaBridge 167:e84263d55307 800 return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 167:e84263d55307 801 }
AnnaBridge 167:e84263d55307 802 else
AnnaBridge 167:e84263d55307 803 {
AnnaBridge 167:e84263d55307 804 return(0U);
AnnaBridge 167:e84263d55307 805 }
mbed_official 25:ac5b0a371348 806 }
mbed_official 25:ac5b0a371348 807
mbed_official 25:ac5b0a371348 808
AnnaBridge 167:e84263d55307 809 /**
AnnaBridge 167:e84263d55307 810 \brief Set Pending Interrupt
AnnaBridge 167:e84263d55307 811 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge 167:e84263d55307 812 \param [in] IRQn Device specific interrupt number.
AnnaBridge 167:e84263d55307 813 \note IRQn must not be negative.
mbed_official 25:ac5b0a371348 814 */
AnnaBridge 167:e84263d55307 815 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
mbed_official 25:ac5b0a371348 816 {
AnnaBridge 167:e84263d55307 817 if ((int32_t)(IRQn) >= 0)
AnnaBridge 167:e84263d55307 818 {
AnnaBridge 167:e84263d55307 819 NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
mbed_official 25:ac5b0a371348 820 }
mbed_official 25:ac5b0a371348 821 }
mbed_official 25:ac5b0a371348 822
mbed_official 25:ac5b0a371348 823
AnnaBridge 167:e84263d55307 824 /**
AnnaBridge 167:e84263d55307 825 \brief Clear Pending Interrupt
AnnaBridge 167:e84263d55307 826 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge 167:e84263d55307 827 \param [in] IRQn Device specific interrupt number.
AnnaBridge 167:e84263d55307 828 \note IRQn must not be negative.
AnnaBridge 167:e84263d55307 829 */
AnnaBridge 167:e84263d55307 830 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
AnnaBridge 167:e84263d55307 831 {
AnnaBridge 167:e84263d55307 832 if ((int32_t)(IRQn) >= 0)
AnnaBridge 167:e84263d55307 833 {
AnnaBridge 167:e84263d55307 834 NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 167:e84263d55307 835 }
AnnaBridge 167:e84263d55307 836 }
mbed_official 25:ac5b0a371348 837
mbed_official 25:ac5b0a371348 838
AnnaBridge 167:e84263d55307 839 /**
AnnaBridge 167:e84263d55307 840 \brief Set Interrupt Priority
AnnaBridge 167:e84263d55307 841 \details Sets the priority of a device specific interrupt or a processor exception.
AnnaBridge 167:e84263d55307 842 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 167:e84263d55307 843 or negative to specify a processor exception.
AnnaBridge 167:e84263d55307 844 \param [in] IRQn Interrupt number.
AnnaBridge 167:e84263d55307 845 \param [in] priority Priority to set.
AnnaBridge 167:e84263d55307 846 \note The priority cannot be set for every processor exception.
mbed_official 25:ac5b0a371348 847 */
AnnaBridge 167:e84263d55307 848 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
mbed_official 25:ac5b0a371348 849 {
AnnaBridge 167:e84263d55307 850 if ((int32_t)(IRQn) >= 0)
AnnaBridge 167:e84263d55307 851 {
AnnaBridge 167:e84263d55307 852 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
AnnaBridge 167:e84263d55307 853 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
mbed_official 25:ac5b0a371348 854 }
AnnaBridge 167:e84263d55307 855 else
AnnaBridge 167:e84263d55307 856 {
AnnaBridge 167:e84263d55307 857 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
AnnaBridge 167:e84263d55307 858 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
mbed_official 25:ac5b0a371348 859 }
mbed_official 25:ac5b0a371348 860 }
mbed_official 25:ac5b0a371348 861
mbed_official 25:ac5b0a371348 862
AnnaBridge 167:e84263d55307 863 /**
AnnaBridge 167:e84263d55307 864 \brief Get Interrupt Priority
AnnaBridge 167:e84263d55307 865 \details Reads the priority of a device specific interrupt or a processor exception.
AnnaBridge 167:e84263d55307 866 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 167:e84263d55307 867 or negative to specify a processor exception.
AnnaBridge 167:e84263d55307 868 \param [in] IRQn Interrupt number.
AnnaBridge 167:e84263d55307 869 \return Interrupt Priority.
AnnaBridge 167:e84263d55307 870 Value is aligned automatically to the implemented priority bits of the microcontroller.
mbed_official 25:ac5b0a371348 871 */
AnnaBridge 167:e84263d55307 872 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
AnnaBridge 167:e84263d55307 873 {
AnnaBridge 167:e84263d55307 874
AnnaBridge 167:e84263d55307 875 if ((int32_t)(IRQn) >= 0)
AnnaBridge 167:e84263d55307 876 {
AnnaBridge 167:e84263d55307 877 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge 167:e84263d55307 878 }
AnnaBridge 167:e84263d55307 879 else
AnnaBridge 167:e84263d55307 880 {
AnnaBridge 167:e84263d55307 881 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge 167:e84263d55307 882 }
AnnaBridge 167:e84263d55307 883 }
AnnaBridge 167:e84263d55307 884
AnnaBridge 167:e84263d55307 885
AnnaBridge 167:e84263d55307 886 /**
AnnaBridge 167:e84263d55307 887 \brief Set Interrupt Vector
AnnaBridge 167:e84263d55307 888 \details Sets an interrupt vector in SRAM based interrupt vector table.
AnnaBridge 167:e84263d55307 889 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 167:e84263d55307 890 or negative to specify a processor exception.
AnnaBridge 167:e84263d55307 891 VTOR must been relocated to SRAM before.
AnnaBridge 167:e84263d55307 892 \param [in] IRQn Interrupt number
AnnaBridge 167:e84263d55307 893 \param [in] vector Address of interrupt handler function
AnnaBridge 167:e84263d55307 894 */
AnnaBridge 167:e84263d55307 895 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
mbed_official 25:ac5b0a371348 896 {
AnnaBridge 167:e84263d55307 897 uint32_t *vectors = (uint32_t *)SCB->VTOR;
AnnaBridge 167:e84263d55307 898 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
AnnaBridge 167:e84263d55307 899 }
AnnaBridge 167:e84263d55307 900
AnnaBridge 167:e84263d55307 901
AnnaBridge 167:e84263d55307 902 /**
AnnaBridge 167:e84263d55307 903 \brief Get Interrupt Vector
AnnaBridge 167:e84263d55307 904 \details Reads an interrupt vector from interrupt vector table.
AnnaBridge 167:e84263d55307 905 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 167:e84263d55307 906 or negative to specify a processor exception.
AnnaBridge 167:e84263d55307 907 \param [in] IRQn Interrupt number.
AnnaBridge 167:e84263d55307 908 \return Address of interrupt handler function
AnnaBridge 167:e84263d55307 909 */
AnnaBridge 167:e84263d55307 910 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
AnnaBridge 167:e84263d55307 911 {
AnnaBridge 167:e84263d55307 912 uint32_t *vectors = (uint32_t *)SCB->VTOR;
AnnaBridge 167:e84263d55307 913 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
AnnaBridge 167:e84263d55307 914 }
AnnaBridge 167:e84263d55307 915
AnnaBridge 167:e84263d55307 916
AnnaBridge 167:e84263d55307 917 /**
AnnaBridge 167:e84263d55307 918 \brief System Reset
AnnaBridge 167:e84263d55307 919 \details Initiates a system reset request to reset the MCU.
AnnaBridge 167:e84263d55307 920 */
AnnaBridge 167:e84263d55307 921 __STATIC_INLINE void __NVIC_SystemReset(void)
AnnaBridge 167:e84263d55307 922 {
AnnaBridge 167:e84263d55307 923 __DSB(); /* Ensure all outstanding memory accesses included
AnnaBridge 167:e84263d55307 924 buffered write are completed before reset */
mbed_official 25:ac5b0a371348 925 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
mbed_official 25:ac5b0a371348 926 SCB_AIRCR_SYSRESETREQ_Msk);
AnnaBridge 167:e84263d55307 927 __DSB(); /* Ensure completion of memory access */
AnnaBridge 167:e84263d55307 928
AnnaBridge 167:e84263d55307 929 for(;;) /* wait until reset */
AnnaBridge 167:e84263d55307 930 {
AnnaBridge 167:e84263d55307 931 __NOP();
AnnaBridge 167:e84263d55307 932 }
mbed_official 25:ac5b0a371348 933 }
mbed_official 25:ac5b0a371348 934
mbed_official 25:ac5b0a371348 935 /*@} end of CMSIS_Core_NVICFunctions */
mbed_official 25:ac5b0a371348 936
mbed_official 25:ac5b0a371348 937
AnnaBridge 167:e84263d55307 938 /* ########################## FPU functions #################################### */
AnnaBridge 167:e84263d55307 939 /**
AnnaBridge 167:e84263d55307 940 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 167:e84263d55307 941 \defgroup CMSIS_Core_FpuFunctions FPU Functions
AnnaBridge 167:e84263d55307 942 \brief Function that provides FPU type.
mbed_official 25:ac5b0a371348 943 @{
mbed_official 25:ac5b0a371348 944 */
mbed_official 25:ac5b0a371348 945
AnnaBridge 167:e84263d55307 946 /**
AnnaBridge 167:e84263d55307 947 \brief get FPU type
AnnaBridge 167:e84263d55307 948 \details returns the FPU type
AnnaBridge 167:e84263d55307 949 \returns
AnnaBridge 167:e84263d55307 950 - \b 0: No FPU
AnnaBridge 167:e84263d55307 951 - \b 1: Single precision FPU
AnnaBridge 167:e84263d55307 952 - \b 2: Double + Single precision FPU
AnnaBridge 167:e84263d55307 953 */
AnnaBridge 167:e84263d55307 954 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
AnnaBridge 167:e84263d55307 955 {
AnnaBridge 167:e84263d55307 956 return 0U; /* No FPU */
AnnaBridge 167:e84263d55307 957 }
mbed_official 25:ac5b0a371348 958
mbed_official 25:ac5b0a371348 959
AnnaBridge 167:e84263d55307 960 /*@} end of CMSIS_Core_FpuFunctions */
AnnaBridge 167:e84263d55307 961
AnnaBridge 167:e84263d55307 962
mbed_official 25:ac5b0a371348 963
AnnaBridge 167:e84263d55307 964 /* ################################## SysTick function ############################################ */
AnnaBridge 167:e84263d55307 965 /**
AnnaBridge 167:e84263d55307 966 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 167:e84263d55307 967 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
AnnaBridge 167:e84263d55307 968 \brief Functions that configure the System.
AnnaBridge 167:e84263d55307 969 @{
AnnaBridge 167:e84263d55307 970 */
mbed_official 25:ac5b0a371348 971
AnnaBridge 167:e84263d55307 972 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
mbed_official 25:ac5b0a371348 973
AnnaBridge 167:e84263d55307 974 /**
AnnaBridge 167:e84263d55307 975 \brief System Tick Configuration
AnnaBridge 167:e84263d55307 976 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
AnnaBridge 167:e84263d55307 977 Counter is in free running mode to generate periodic interrupts.
AnnaBridge 167:e84263d55307 978 \param [in] ticks Number of ticks between two interrupts.
AnnaBridge 167:e84263d55307 979 \return 0 Function succeeded.
AnnaBridge 167:e84263d55307 980 \return 1 Function failed.
AnnaBridge 167:e84263d55307 981 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
AnnaBridge 167:e84263d55307 982 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
AnnaBridge 167:e84263d55307 983 must contain a vendor-specific implementation of this function.
mbed_official 25:ac5b0a371348 984 */
mbed_official 25:ac5b0a371348 985 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
mbed_official 25:ac5b0a371348 986 {
AnnaBridge 167:e84263d55307 987 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
AnnaBridge 167:e84263d55307 988 {
AnnaBridge 167:e84263d55307 989 return (1UL); /* Reload value impossible */
AnnaBridge 167:e84263d55307 990 }
mbed_official 25:ac5b0a371348 991
mbed_official 25:ac5b0a371348 992 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
mbed_official 25:ac5b0a371348 993 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
mbed_official 25:ac5b0a371348 994 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
mbed_official 25:ac5b0a371348 995 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
mbed_official 25:ac5b0a371348 996 SysTick_CTRL_TICKINT_Msk |
mbed_official 25:ac5b0a371348 997 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
mbed_official 25:ac5b0a371348 998 return (0UL); /* Function successful */
mbed_official 25:ac5b0a371348 999 }
mbed_official 25:ac5b0a371348 1000
mbed_official 25:ac5b0a371348 1001 #endif
mbed_official 25:ac5b0a371348 1002
mbed_official 25:ac5b0a371348 1003 /*@} end of CMSIS_Core_SysTickFunctions */
mbed_official 25:ac5b0a371348 1004
mbed_official 25:ac5b0a371348 1005
mbed_official 25:ac5b0a371348 1006
mbed_official 25:ac5b0a371348 1007
mbed_official 25:ac5b0a371348 1008 #ifdef __cplusplus
mbed_official 25:ac5b0a371348 1009 }
mbed_official 25:ac5b0a371348 1010 #endif
mbed_official 25:ac5b0a371348 1011
mbed_official 25:ac5b0a371348 1012 #endif /* __CORE_SC000_H_DEPENDANT */
mbed_official 25:ac5b0a371348 1013
mbed_official 25:ac5b0a371348 1014 #endif /* __CMSIS_GENERIC */