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targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_cmt.h@154:37f96f9d4de2, 2017-01-04 (annotated)

Committer:
<>
Date:
Wed Jan 04 16:58:05 2017 +0000
Revision:
154:37f96f9d4de2
This updates the lib to the mbed lib v133

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 154:37f96f9d4de2 1 /*
<> 154:37f96f9d4de2 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
<> 154:37f96f9d4de2 3 * All rights reserved.
<> 154:37f96f9d4de2 4 *
<> 154:37f96f9d4de2 5 * Redistribution and use in source and binary forms, with or without modification,
<> 154:37f96f9d4de2 6 * are permitted provided that the following conditions are met:
<> 154:37f96f9d4de2 7 *
<> 154:37f96f9d4de2 8 * o Redistributions of source code must retain the above copyright notice, this list
<> 154:37f96f9d4de2 9 * of conditions and the following disclaimer.
<> 154:37f96f9d4de2 10 *
<> 154:37f96f9d4de2 11 * o Redistributions in binary form must reproduce the above copyright notice, this
<> 154:37f96f9d4de2 12 * list of conditions and the following disclaimer in the documentation and/or
<> 154:37f96f9d4de2 13 * other materials provided with the distribution.
<> 154:37f96f9d4de2 14 *
<> 154:37f96f9d4de2 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
<> 154:37f96f9d4de2 16 * contributors may be used to endorse or promote products derived from this
<> 154:37f96f9d4de2 17 * software without specific prior written permission.
<> 154:37f96f9d4de2 18 *
<> 154:37f96f9d4de2 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
<> 154:37f96f9d4de2 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
<> 154:37f96f9d4de2 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 154:37f96f9d4de2 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
<> 154:37f96f9d4de2 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
<> 154:37f96f9d4de2 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
<> 154:37f96f9d4de2 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
<> 154:37f96f9d4de2 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
<> 154:37f96f9d4de2 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
<> 154:37f96f9d4de2 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 154:37f96f9d4de2 29 */
<> 154:37f96f9d4de2 30 #ifndef _FSL_CMT_H_
<> 154:37f96f9d4de2 31 #define _FSL_CMT_H_
<> 154:37f96f9d4de2 32
<> 154:37f96f9d4de2 33 #include "fsl_common.h"
<> 154:37f96f9d4de2 34
<> 154:37f96f9d4de2 35 /*!
<> 154:37f96f9d4de2 36 * @addtogroup cmt
<> 154:37f96f9d4de2 37 * @{
<> 154:37f96f9d4de2 38 */
<> 154:37f96f9d4de2 39
<> 154:37f96f9d4de2 40
<> 154:37f96f9d4de2 41 /*******************************************************************************
<> 154:37f96f9d4de2 42 * Definitions
<> 154:37f96f9d4de2 43 ******************************************************************************/
<> 154:37f96f9d4de2 44
<> 154:37f96f9d4de2 45 /*! @name Driver version */
<> 154:37f96f9d4de2 46 /*@{*/
<> 154:37f96f9d4de2 47 /*! @brief CMT driver version 2.0.1. */
<> 154:37f96f9d4de2 48 #define FSL_CMT_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
<> 154:37f96f9d4de2 49 /*@}*/
<> 154:37f96f9d4de2 50
<> 154:37f96f9d4de2 51 /*!
<> 154:37f96f9d4de2 52 * @brief The modes of CMT.
<> 154:37f96f9d4de2 53 */
<> 154:37f96f9d4de2 54 typedef enum _cmt_mode
<> 154:37f96f9d4de2 55 {
<> 154:37f96f9d4de2 56 kCMT_DirectIROCtl = 0x00U, /*!< Carrier modulator is disabled and the IRO signal is directly in software control */
<> 154:37f96f9d4de2 57 kCMT_TimeMode = 0x01U, /*!< Carrier modulator is enabled in time mode. */
<> 154:37f96f9d4de2 58 kCMT_FSKMode = 0x05U, /*!< Carrier modulator is enabled in FSK mode. */
<> 154:37f96f9d4de2 59 kCMT_BasebandMode = 0x09U /*!< Carrier modulator is enabled in baseband mode. */
<> 154:37f96f9d4de2 60 } cmt_mode_t;
<> 154:37f96f9d4de2 61
<> 154:37f96f9d4de2 62 /*!
<> 154:37f96f9d4de2 63 * @brief The CMT clock divide primary prescaler.
<> 154:37f96f9d4de2 64 * The primary clock divider is used to divider the bus clock to
<> 154:37f96f9d4de2 65 * get the intermediate frequency to approximately equal to 8 MHZ.
<> 154:37f96f9d4de2 66 * When the bus clock is 8 MHZ, set primary prescaler to "kCMT_PrimaryClkDiv1".
<> 154:37f96f9d4de2 67 */
<> 154:37f96f9d4de2 68 typedef enum _cmt_primary_clkdiv
<> 154:37f96f9d4de2 69 {
<> 154:37f96f9d4de2 70 kCMT_PrimaryClkDiv1 = 0U, /*!< The intermediate frequency is the bus clock divided by 1. */
<> 154:37f96f9d4de2 71 kCMT_PrimaryClkDiv2 = 1U, /*!< The intermediate frequency is the bus clock divided by 2. */
<> 154:37f96f9d4de2 72 kCMT_PrimaryClkDiv3 = 2U, /*!< The intermediate frequency is the bus clock divided by 3. */
<> 154:37f96f9d4de2 73 kCMT_PrimaryClkDiv4 = 3U, /*!< The intermediate frequency is the bus clock divided by 4. */
<> 154:37f96f9d4de2 74 kCMT_PrimaryClkDiv5 = 4U, /*!< The intermediate frequency is the bus clock divided by 5. */
<> 154:37f96f9d4de2 75 kCMT_PrimaryClkDiv6 = 5U, /*!< The intermediate frequency is the bus clock divided by 6. */
<> 154:37f96f9d4de2 76 kCMT_PrimaryClkDiv7 = 6U, /*!< The intermediate frequency is the bus clock divided by 7. */
<> 154:37f96f9d4de2 77 kCMT_PrimaryClkDiv8 = 7U, /*!< The intermediate frequency is the bus clock divided by 8. */
<> 154:37f96f9d4de2 78 kCMT_PrimaryClkDiv9 = 8U, /*!< The intermediate frequency is the bus clock divided by 9. */
<> 154:37f96f9d4de2 79 kCMT_PrimaryClkDiv10 = 9U, /*!< The intermediate frequency is the bus clock divided by 10. */
<> 154:37f96f9d4de2 80 kCMT_PrimaryClkDiv11 = 10U, /*!< The intermediate frequency is the bus clock divided by 11. */
<> 154:37f96f9d4de2 81 kCMT_PrimaryClkDiv12 = 11U, /*!< The intermediate frequency is the bus clock divided by 12. */
<> 154:37f96f9d4de2 82 kCMT_PrimaryClkDiv13 = 12U, /*!< The intermediate frequency is the bus clock divided by 13. */
<> 154:37f96f9d4de2 83 kCMT_PrimaryClkDiv14 = 13U, /*!< The intermediate frequency is the bus clock divided by 14. */
<> 154:37f96f9d4de2 84 kCMT_PrimaryClkDiv15 = 14U, /*!< The intermediate frequency is the bus clock divided by 15. */
<> 154:37f96f9d4de2 85 kCMT_PrimaryClkDiv16 = 15U /*!< The intermediate frequency is the bus clock divided by 16. */
<> 154:37f96f9d4de2 86 } cmt_primary_clkdiv_t;
<> 154:37f96f9d4de2 87
<> 154:37f96f9d4de2 88 /*!
<> 154:37f96f9d4de2 89 * @brief The CMT clock divide secondary prescaler.
<> 154:37f96f9d4de2 90 * The second prescaler can be used to divide the 8 MHZ CMT clock
<> 154:37f96f9d4de2 91 * by 1, 2, 4, or 8 according to the specification.
<> 154:37f96f9d4de2 92 */
<> 154:37f96f9d4de2 93 typedef enum _cmt_second_clkdiv
<> 154:37f96f9d4de2 94 {
<> 154:37f96f9d4de2 95 kCMT_SecondClkDiv1 = 0U, /*!< The CMT clock is the intermediate frequency frequency divided by 1. */
<> 154:37f96f9d4de2 96 kCMT_SecondClkDiv2 = 1U, /*!< The CMT clock is the intermediate frequency frequency divided by 2. */
<> 154:37f96f9d4de2 97 kCMT_SecondClkDiv4 = 2U, /*!< The CMT clock is the intermediate frequency frequency divided by 4. */
<> 154:37f96f9d4de2 98 kCMT_SecondClkDiv8 = 3U /*!< The CMT clock is the intermediate frequency frequency divided by 8. */
<> 154:37f96f9d4de2 99 } cmt_second_clkdiv_t;
<> 154:37f96f9d4de2 100
<> 154:37f96f9d4de2 101 /*!
<> 154:37f96f9d4de2 102 * @brief The CMT infrared output polarity.
<> 154:37f96f9d4de2 103 */
<> 154:37f96f9d4de2 104 typedef enum _cmt_infrared_output_polarity
<> 154:37f96f9d4de2 105 {
<> 154:37f96f9d4de2 106 kCMT_IROActiveLow = 0U, /*!< The CMT infrared output signal polarity is active-low. */
<> 154:37f96f9d4de2 107 kCMT_IROActiveHigh = 1U /*!< The CMT infrared output signal polarity is active-high. */
<> 154:37f96f9d4de2 108 } cmt_infrared_output_polarity_t;
<> 154:37f96f9d4de2 109
<> 154:37f96f9d4de2 110 /*!
<> 154:37f96f9d4de2 111 * @brief The CMT infrared output signal state control.
<> 154:37f96f9d4de2 112 */
<> 154:37f96f9d4de2 113 typedef enum _cmt_infrared_output_state
<> 154:37f96f9d4de2 114 {
<> 154:37f96f9d4de2 115 kCMT_IROCtlLow = 0U, /*!< The CMT Infrared output signal state is controlled to low. */
<> 154:37f96f9d4de2 116 kCMT_IROCtlHigh = 1U /*!< The CMT Infrared output signal state is controlled to high. */
<> 154:37f96f9d4de2 117 } cmt_infrared_output_state_t;
<> 154:37f96f9d4de2 118
<> 154:37f96f9d4de2 119 /*!
<> 154:37f96f9d4de2 120 * @brief CMT interrupt configuration structure, default settings all disabled.
<> 154:37f96f9d4de2 121 *
<> 154:37f96f9d4de2 122 * This structure contains the settings for all of the CMT interrupt configurations.
<> 154:37f96f9d4de2 123 */
<> 154:37f96f9d4de2 124 enum _cmt_interrupt_enable
<> 154:37f96f9d4de2 125 {
<> 154:37f96f9d4de2 126 kCMT_EndOfCycleInterruptEnable = CMT_MSC_EOCIE_MASK, /*!< CMT end of cycle interrupt. */
<> 154:37f96f9d4de2 127 };
<> 154:37f96f9d4de2 128
<> 154:37f96f9d4de2 129 /*!
<> 154:37f96f9d4de2 130 * @brief CMT carrier generator and modulator configuration structure
<> 154:37f96f9d4de2 131 *
<> 154:37f96f9d4de2 132 */
<> 154:37f96f9d4de2 133 typedef struct _cmt_modulate_config
<> 154:37f96f9d4de2 134 {
<> 154:37f96f9d4de2 135 uint8_t highCount1; /*!< The high time for carrier generator first register. */
<> 154:37f96f9d4de2 136 uint8_t lowCount1; /*!< The low time for carrier generator first register. */
<> 154:37f96f9d4de2 137 uint8_t highCount2; /*!< The high time for carrier generator second register for FSK mode. */
<> 154:37f96f9d4de2 138 uint8_t lowCount2; /*!< The low time for carrier generator second register for FSK mode. */
<> 154:37f96f9d4de2 139 uint16_t markCount; /*!< The mark time for the modulator gate. */
<> 154:37f96f9d4de2 140 uint16_t spaceCount; /*!< The space time for the modulator gate. */
<> 154:37f96f9d4de2 141 } cmt_modulate_config_t;
<> 154:37f96f9d4de2 142
<> 154:37f96f9d4de2 143 /*! @brief CMT basic configuration structure. */
<> 154:37f96f9d4de2 144 typedef struct _cmt_config
<> 154:37f96f9d4de2 145 {
<> 154:37f96f9d4de2 146 bool isInterruptEnabled; /*!< Timer interrupt 0-disable, 1-enable. */
<> 154:37f96f9d4de2 147 bool isIroEnabled; /*!< The IRO output 0-disabled, 1-enabled. */
<> 154:37f96f9d4de2 148 cmt_infrared_output_polarity_t iroPolarity; /*!< The IRO polarity. */
<> 154:37f96f9d4de2 149 cmt_second_clkdiv_t divider; /*!< The CMT clock divide prescaler. */
<> 154:37f96f9d4de2 150 } cmt_config_t;
<> 154:37f96f9d4de2 151
<> 154:37f96f9d4de2 152 /*******************************************************************************
<> 154:37f96f9d4de2 153 * API
<> 154:37f96f9d4de2 154 ******************************************************************************/
<> 154:37f96f9d4de2 155
<> 154:37f96f9d4de2 156 #if defined(__cplusplus)
<> 154:37f96f9d4de2 157 extern "C" {
<> 154:37f96f9d4de2 158 #endif
<> 154:37f96f9d4de2 159
<> 154:37f96f9d4de2 160 /*!
<> 154:37f96f9d4de2 161 * @name Initialization and deinitialization
<> 154:37f96f9d4de2 162 * @{
<> 154:37f96f9d4de2 163 */
<> 154:37f96f9d4de2 164
<> 154:37f96f9d4de2 165 /*!
<> 154:37f96f9d4de2 166 * @brief Gets the CMT default configuration structure. The purpose
<> 154:37f96f9d4de2 167 * of this API is to get the default configuration structure for the CMT_Init().
<> 154:37f96f9d4de2 168 * Use the initialized structure unchanged in CMT_Init(), or modify
<> 154:37f96f9d4de2 169 * some fields of the structure before calling the CMT_Init().
<> 154:37f96f9d4de2 170 *
<> 154:37f96f9d4de2 171 * @param config The CMT configuration structure pointer.
<> 154:37f96f9d4de2 172 */
<> 154:37f96f9d4de2 173 void CMT_GetDefaultConfig(cmt_config_t *config);
<> 154:37f96f9d4de2 174
<> 154:37f96f9d4de2 175 /*!
<> 154:37f96f9d4de2 176 * @brief Initializes the CMT module.
<> 154:37f96f9d4de2 177 *
<> 154:37f96f9d4de2 178 * This function ungates the module clock and sets the CMT internal clock,
<> 154:37f96f9d4de2 179 * interrupt, and infrared output signal for the CMT module.
<> 154:37f96f9d4de2 180 *
<> 154:37f96f9d4de2 181 * @param base CMT peripheral base address.
<> 154:37f96f9d4de2 182 * @param config The CMT basic configuration structure.
<> 154:37f96f9d4de2 183 * @param busClock_Hz The CMT module input clock - bus clock frequency.
<> 154:37f96f9d4de2 184 */
<> 154:37f96f9d4de2 185 void CMT_Init(CMT_Type *base, const cmt_config_t *config, uint32_t busClock_Hz);
<> 154:37f96f9d4de2 186
<> 154:37f96f9d4de2 187 /*!
<> 154:37f96f9d4de2 188 * @brief Disables the CMT module and gate control.
<> 154:37f96f9d4de2 189 *
<> 154:37f96f9d4de2 190 * This function disables CMT modulator, interrupts, and gates the
<> 154:37f96f9d4de2 191 * CMT clock control. CMT_Init must be called to use the CMT again.
<> 154:37f96f9d4de2 192 *
<> 154:37f96f9d4de2 193 * @param base CMT peripheral base address.
<> 154:37f96f9d4de2 194 */
<> 154:37f96f9d4de2 195 void CMT_Deinit(CMT_Type *base);
<> 154:37f96f9d4de2 196
<> 154:37f96f9d4de2 197 /*! @}*/
<> 154:37f96f9d4de2 198
<> 154:37f96f9d4de2 199 /*!
<> 154:37f96f9d4de2 200 * @name Basic Control Operations
<> 154:37f96f9d4de2 201 * @{
<> 154:37f96f9d4de2 202 */
<> 154:37f96f9d4de2 203
<> 154:37f96f9d4de2 204 /*!
<> 154:37f96f9d4de2 205 * @brief Selects the mode for CMT.
<> 154:37f96f9d4de2 206 *
<> 154:37f96f9d4de2 207 * @param base CMT peripheral base address.
<> 154:37f96f9d4de2 208 * @param mode The CMT feature mode enumeration. See "cmt_mode_t".
<> 154:37f96f9d4de2 209 * @param modulateConfig The carrier generation and modulator configuration.
<> 154:37f96f9d4de2 210 */
<> 154:37f96f9d4de2 211 void CMT_SetMode(CMT_Type *base, cmt_mode_t mode, cmt_modulate_config_t *modulateConfig);
<> 154:37f96f9d4de2 212
<> 154:37f96f9d4de2 213 /*!
<> 154:37f96f9d4de2 214 * @brief Gets the mode of the CMT module.
<> 154:37f96f9d4de2 215 *
<> 154:37f96f9d4de2 216 * @param base CMT peripheral base address.
<> 154:37f96f9d4de2 217 * @return The CMT mode.
<> 154:37f96f9d4de2 218 * kCMT_DirectIROCtl Carrier modulator is disabled, the IRO signal is directly in software control.
<> 154:37f96f9d4de2 219 * kCMT_TimeMode Carrier modulator is enabled in time mode.
<> 154:37f96f9d4de2 220 * kCMT_FSKMode Carrier modulator is enabled in FSK mode.
<> 154:37f96f9d4de2 221 * kCMT_BasebandMode Carrier modulator is enabled in baseband mode.
<> 154:37f96f9d4de2 222 */
<> 154:37f96f9d4de2 223 cmt_mode_t CMT_GetMode(CMT_Type *base);
<> 154:37f96f9d4de2 224
<> 154:37f96f9d4de2 225 /*!
<> 154:37f96f9d4de2 226 * @brief Gets the actual CMT clock frequency.
<> 154:37f96f9d4de2 227 *
<> 154:37f96f9d4de2 228 * @param base CMT peripheral base address.
<> 154:37f96f9d4de2 229 * @param busClock_Hz CMT module input clock - bus clock frequency.
<> 154:37f96f9d4de2 230 * @return The CMT clock frequency.
<> 154:37f96f9d4de2 231 */
<> 154:37f96f9d4de2 232 uint32_t CMT_GetCMTFrequency(CMT_Type *base, uint32_t busClock_Hz);
<> 154:37f96f9d4de2 233
<> 154:37f96f9d4de2 234 /*!
<> 154:37f96f9d4de2 235 * @brief Sets the primary data set for the CMT carrier generator counter.
<> 154:37f96f9d4de2 236 *
<> 154:37f96f9d4de2 237 * This function sets the high time and low time of the primary data set for the
<> 154:37f96f9d4de2 238 * CMT carrier generator counter to control the period and the duty cycle of the
<> 154:37f96f9d4de2 239 * output carrier signal.
<> 154:37f96f9d4de2 240 * If the CMT clock period is Tcmt, The period of the carrier generator signal equals
<> 154:37f96f9d4de2 241 * (highCount + lowCount) * Tcmt. The duty cycle equals highCount / (highCount + lowCount).
<> 154:37f96f9d4de2 242 *
<> 154:37f96f9d4de2 243 * @param base CMT peripheral base address.
<> 154:37f96f9d4de2 244 * @param highCount The number of CMT clocks for carrier generator signal high time,
<> 154:37f96f9d4de2 245 * integer in the range of 1 ~ 0xFF.
<> 154:37f96f9d4de2 246 * @param lowCount The number of CMT clocks for carrier generator signal low time,
<> 154:37f96f9d4de2 247 * integer in the range of 1 ~ 0xFF.
<> 154:37f96f9d4de2 248 */
<> 154:37f96f9d4de2 249 static inline void CMT_SetCarrirGenerateCountOne(CMT_Type *base, uint32_t highCount, uint32_t lowCount)
<> 154:37f96f9d4de2 250 {
<> 154:37f96f9d4de2 251 assert(highCount <= CMT_CGH1_PH_MASK);
<> 154:37f96f9d4de2 252 assert(highCount);
<> 154:37f96f9d4de2 253 assert(lowCount <= CMT_CGL1_PL_MASK);
<> 154:37f96f9d4de2 254 assert(lowCount);
<> 154:37f96f9d4de2 255
<> 154:37f96f9d4de2 256 base->CGH1 = highCount;
<> 154:37f96f9d4de2 257 base->CGL1 = lowCount;
<> 154:37f96f9d4de2 258 }
<> 154:37f96f9d4de2 259
<> 154:37f96f9d4de2 260 /*!
<> 154:37f96f9d4de2 261 * @brief Sets the secondary data set for the CMT carrier generator counter.
<> 154:37f96f9d4de2 262 *
<> 154:37f96f9d4de2 263 * This function is used for FSK mode setting the high time and low time of the secondary
<> 154:37f96f9d4de2 264 * data set CMT carrier generator counter to control the period and the duty cycle
<> 154:37f96f9d4de2 265 * of the output carrier signal.
<> 154:37f96f9d4de2 266 * If the CMT clock period is Tcmt, The period of the carrier generator signal equals
<> 154:37f96f9d4de2 267 * (highCount + lowCount) * Tcmt. The duty cycle equals highCount / (highCount + lowCount).
<> 154:37f96f9d4de2 268 *
<> 154:37f96f9d4de2 269 * @param base CMT peripheral base address.
<> 154:37f96f9d4de2 270 * @param highCount The number of CMT clocks for carrier generator signal high time,
<> 154:37f96f9d4de2 271 * integer in the range of 1 ~ 0xFF.
<> 154:37f96f9d4de2 272 * @param lowCount The number of CMT clocks for carrier generator signal low time,
<> 154:37f96f9d4de2 273 * integer in the range of 1 ~ 0xFF.
<> 154:37f96f9d4de2 274 */
<> 154:37f96f9d4de2 275 static inline void CMT_SetCarrirGenerateCountTwo(CMT_Type *base, uint32_t highCount, uint32_t lowCount)
<> 154:37f96f9d4de2 276 {
<> 154:37f96f9d4de2 277 assert(highCount <= CMT_CGH2_SH_MASK);
<> 154:37f96f9d4de2 278 assert(highCount);
<> 154:37f96f9d4de2 279 assert(lowCount <= CMT_CGL2_SL_MASK);
<> 154:37f96f9d4de2 280 assert(lowCount);
<> 154:37f96f9d4de2 281
<> 154:37f96f9d4de2 282 base->CGH2 = highCount;
<> 154:37f96f9d4de2 283 base->CGL2 = lowCount;
<> 154:37f96f9d4de2 284 }
<> 154:37f96f9d4de2 285
<> 154:37f96f9d4de2 286 /*!
<> 154:37f96f9d4de2 287 * @brief Sets the modulation mark and space time period for the CMT modulator.
<> 154:37f96f9d4de2 288 *
<> 154:37f96f9d4de2 289 * This function sets the mark time period of the CMT modulator counter
<> 154:37f96f9d4de2 290 * to control the mark time of the output modulated signal from the carrier generator output signal.
<> 154:37f96f9d4de2 291 * If the CMT clock frequency is Fcmt and the carrier out signal frequency is fcg:
<> 154:37f96f9d4de2 292 * - In Time and Baseband mode: The mark period of the generated signal equals (markCount + 1) / (Fcmt/8).
<> 154:37f96f9d4de2 293 * The space period of the generated signal equals spaceCount / (Fcmt/8).
<> 154:37f96f9d4de2 294 * - In FSK mode: The mark period of the generated signal equals (markCount + 1)/fcg.
<> 154:37f96f9d4de2 295 * The space period of the generated signal equals spaceCount / fcg.
<> 154:37f96f9d4de2 296 *
<> 154:37f96f9d4de2 297 * @param base Base address for current CMT instance.
<> 154:37f96f9d4de2 298 * @param markCount The number of clock period for CMT modulator signal mark period,
<> 154:37f96f9d4de2 299 * in the range of 0 ~ 0xFFFF.
<> 154:37f96f9d4de2 300 * @param spaceCount The number of clock period for CMT modulator signal space period,
<> 154:37f96f9d4de2 301 * in the range of the 0 ~ 0xFFFF.
<> 154:37f96f9d4de2 302 */
<> 154:37f96f9d4de2 303 void CMT_SetModulateMarkSpace(CMT_Type *base, uint32_t markCount, uint32_t spaceCount);
<> 154:37f96f9d4de2 304
<> 154:37f96f9d4de2 305 /*!
<> 154:37f96f9d4de2 306 * @brief Enables or disables the extended space operation.
<> 154:37f96f9d4de2 307 *
<> 154:37f96f9d4de2 308 * This function is used to make the space period longer
<> 154:37f96f9d4de2 309 * for time, baseband, and FSK modes.
<> 154:37f96f9d4de2 310 *
<> 154:37f96f9d4de2 311 * @param base CMT peripheral base address.
<> 154:37f96f9d4de2 312 * @param enable True enable the extended space, false disable the extended space.
<> 154:37f96f9d4de2 313 */
<> 154:37f96f9d4de2 314 static inline void CMT_EnableExtendedSpace(CMT_Type *base, bool enable)
<> 154:37f96f9d4de2 315 {
<> 154:37f96f9d4de2 316 if (enable)
<> 154:37f96f9d4de2 317 {
<> 154:37f96f9d4de2 318 base->MSC |= CMT_MSC_EXSPC_MASK;
<> 154:37f96f9d4de2 319 }
<> 154:37f96f9d4de2 320 else
<> 154:37f96f9d4de2 321 {
<> 154:37f96f9d4de2 322 base->MSC &= ~CMT_MSC_EXSPC_MASK;
<> 154:37f96f9d4de2 323 }
<> 154:37f96f9d4de2 324 }
<> 154:37f96f9d4de2 325
<> 154:37f96f9d4de2 326 /*!
<> 154:37f96f9d4de2 327 * @brief Sets IRO - infrared output signal state.
<> 154:37f96f9d4de2 328 *
<> 154:37f96f9d4de2 329 * Changes the states of the IRO signal when the kCMT_DirectIROMode mode is set
<> 154:37f96f9d4de2 330 * and the IRO signal is enabled.
<> 154:37f96f9d4de2 331 *
<> 154:37f96f9d4de2 332 * @param base CMT peripheral base address.
<> 154:37f96f9d4de2 333 * @param state The control of the IRO signal. See "cmt_infrared_output_state_t"
<> 154:37f96f9d4de2 334 */
<> 154:37f96f9d4de2 335 void CMT_SetIroState(CMT_Type *base, cmt_infrared_output_state_t state);
<> 154:37f96f9d4de2 336
<> 154:37f96f9d4de2 337 /*!
<> 154:37f96f9d4de2 338 * @brief Enables the CMT interrupt.
<> 154:37f96f9d4de2 339 *
<> 154:37f96f9d4de2 340 * This function enables the CMT interrupts according to the provided maskIf enabled.
<> 154:37f96f9d4de2 341 * The CMT only has the end of the cycle interrupt - an interrupt occurs at the end
<> 154:37f96f9d4de2 342 * of the modulator cycle. This interrupt provides a means for the user
<> 154:37f96f9d4de2 343 * to reload the new mark/space values into the CMT modulator data registers
<> 154:37f96f9d4de2 344 * and verify the modulator mark and space.
<> 154:37f96f9d4de2 345 * For example, to enable the end of cycle, do the following:
<> 154:37f96f9d4de2 346 * @code
<> 154:37f96f9d4de2 347 * CMT_EnableInterrupts(CMT, kCMT_EndOfCycleInterruptEnable);
<> 154:37f96f9d4de2 348 * @endcode
<> 154:37f96f9d4de2 349 * @param base CMT peripheral base address.
<> 154:37f96f9d4de2 350 * @param mask The interrupts to enable. Logical OR of @ref _cmt_interrupt_enable.
<> 154:37f96f9d4de2 351 */
<> 154:37f96f9d4de2 352 static inline void CMT_EnableInterrupts(CMT_Type *base, uint32_t mask)
<> 154:37f96f9d4de2 353 {
<> 154:37f96f9d4de2 354 base->MSC |= mask;
<> 154:37f96f9d4de2 355 }
<> 154:37f96f9d4de2 356
<> 154:37f96f9d4de2 357 /*!
<> 154:37f96f9d4de2 358 * @brief Disables the CMT interrupt.
<> 154:37f96f9d4de2 359 *
<> 154:37f96f9d4de2 360 * This function disables the CMT interrupts according to the provided maskIf enabled.
<> 154:37f96f9d4de2 361 * The CMT only has the end of the cycle interrupt.
<> 154:37f96f9d4de2 362 * For example, to disable the end of cycle, do the following:
<> 154:37f96f9d4de2 363 * @code
<> 154:37f96f9d4de2 364 * CMT_DisableInterrupts(CMT, kCMT_EndOfCycleInterruptEnable);
<> 154:37f96f9d4de2 365 * @endcode
<> 154:37f96f9d4de2 366 *
<> 154:37f96f9d4de2 367 * @param base CMT peripheral base address.
<> 154:37f96f9d4de2 368 * @param mask The interrupts to enable. Logical OR of @ref _cmt_interrupt_enable.
<> 154:37f96f9d4de2 369 */
<> 154:37f96f9d4de2 370 static inline void CMT_DisableInterrupts(CMT_Type *base, uint32_t mask)
<> 154:37f96f9d4de2 371 {
<> 154:37f96f9d4de2 372 base->MSC &= ~mask;
<> 154:37f96f9d4de2 373 }
<> 154:37f96f9d4de2 374
<> 154:37f96f9d4de2 375 /*!
<> 154:37f96f9d4de2 376 * @brief Gets the end of the cycle status flag.
<> 154:37f96f9d4de2 377 *
<> 154:37f96f9d4de2 378 * The flag is set:
<> 154:37f96f9d4de2 379 * - When the modulator is not currently active and carrier and modulator
<> 154:37f96f9d4de2 380 * are set to start the initial CMT transmission.
<> 154:37f96f9d4de2 381 * - At the end of each modulation cycle when the counter is reloaded and
<> 154:37f96f9d4de2 382 * the carrier and modulator are enabled.
<> 154:37f96f9d4de2 383 * @param base CMT peripheral base address.
<> 154:37f96f9d4de2 384 * @return Current status of the end of cycle status flag
<> 154:37f96f9d4de2 385 * @arg non-zero: End-of-cycle has occurred.
<> 154:37f96f9d4de2 386 * @arg zero: End-of-cycle has not yet occurred since the flag last cleared.
<> 154:37f96f9d4de2 387 */
<> 154:37f96f9d4de2 388 static inline uint32_t CMT_GetStatusFlags(CMT_Type *base)
<> 154:37f96f9d4de2 389 {
<> 154:37f96f9d4de2 390 return base->MSC & CMT_MSC_EOCF_MASK;
<> 154:37f96f9d4de2 391 }
<> 154:37f96f9d4de2 392
<> 154:37f96f9d4de2 393 /*! @}*/
<> 154:37f96f9d4de2 394
<> 154:37f96f9d4de2 395 #if defined(__cplusplus)
<> 154:37f96f9d4de2 396 }
<> 154:37f96f9d4de2 397 #endif
<> 154:37f96f9d4de2 398
<> 154:37f96f9d4de2 399 /*! @}*/
<> 154:37f96f9d4de2 400
<> 154:37f96f9d4de2 401 #endif /* _FSL_CMT_H_*/