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targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/drivers/fsl_slcd.h@154:37f96f9d4de2, 2017-01-04 (annotated)

Committer:
<>
Date:
Wed Jan 04 16:58:05 2017 +0000
Revision:
154:37f96f9d4de2
This updates the lib to the mbed lib v133

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 154:37f96f9d4de2 1 /*
<> 154:37f96f9d4de2 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
<> 154:37f96f9d4de2 3 * All rights reserved.
<> 154:37f96f9d4de2 4 *
<> 154:37f96f9d4de2 5 * Redistribution and use in source and binary forms, with or without modification,
<> 154:37f96f9d4de2 6 * are permitted provided that the following conditions are met:
<> 154:37f96f9d4de2 7 *
<> 154:37f96f9d4de2 8 * o Redistributions of source code must retain the above copyright notice, this list
<> 154:37f96f9d4de2 9 * of conditions and the following disclaimer.
<> 154:37f96f9d4de2 10 *
<> 154:37f96f9d4de2 11 * o Redistributions in binary form must reproduce the above copyright notice, this
<> 154:37f96f9d4de2 12 * list of conditions and the following disclaimer in the documentation and/or
<> 154:37f96f9d4de2 13 * other materials provided with the distribution.
<> 154:37f96f9d4de2 14 *
<> 154:37f96f9d4de2 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
<> 154:37f96f9d4de2 16 * contributors may be used to endorse or promote products derived from this
<> 154:37f96f9d4de2 17 * software without specific prior written permission.
<> 154:37f96f9d4de2 18 *
<> 154:37f96f9d4de2 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
<> 154:37f96f9d4de2 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
<> 154:37f96f9d4de2 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 154:37f96f9d4de2 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
<> 154:37f96f9d4de2 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
<> 154:37f96f9d4de2 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
<> 154:37f96f9d4de2 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
<> 154:37f96f9d4de2 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
<> 154:37f96f9d4de2 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
<> 154:37f96f9d4de2 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 154:37f96f9d4de2 29 */
<> 154:37f96f9d4de2 30
<> 154:37f96f9d4de2 31 #ifndef _FSL_SLCD_H_
<> 154:37f96f9d4de2 32 #define _FSL_SLCD_H_
<> 154:37f96f9d4de2 33
<> 154:37f96f9d4de2 34 #include "fsl_common.h"
<> 154:37f96f9d4de2 35
<> 154:37f96f9d4de2 36 /*!
<> 154:37f96f9d4de2 37 * @addtogroup slcd
<> 154:37f96f9d4de2 38 * @{
<> 154:37f96f9d4de2 39 */
<> 154:37f96f9d4de2 40
<> 154:37f96f9d4de2 41 /*! @file */
<> 154:37f96f9d4de2 42
<> 154:37f96f9d4de2 43 /*******************************************************************************
<> 154:37f96f9d4de2 44 * Definitions
<> 154:37f96f9d4de2 45 ******************************************************************************/
<> 154:37f96f9d4de2 46
<> 154:37f96f9d4de2 47 /*! @name Driver version */
<> 154:37f96f9d4de2 48 /*@{*/
<> 154:37f96f9d4de2 49 /*! @brief SLCD driver version 2.0.0. */
<> 154:37f96f9d4de2 50 #define FSL_SLCD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
<> 154:37f96f9d4de2 51 /*@}*/
<> 154:37f96f9d4de2 52
<> 154:37f96f9d4de2 53 /*! @brief SLCD power supply option. */
<> 154:37f96f9d4de2 54 typedef enum _slcd_power_supply_option
<> 154:37f96f9d4de2 55 {
<> 154:37f96f9d4de2 56 kSLCD_InternalVll3UseChargePump =
<> 154:37f96f9d4de2 57 2U, /*!< VLL3 connected to VDD internally, charge pump is used to generate VLL1 and VLL2. */
<> 154:37f96f9d4de2 58 kSLCD_ExternalVll3UseResistorBiasNetwork =
<> 154:37f96f9d4de2 59 4U, /*!< VLL3 is driven externally and resistor bias network is used to generate VLL1 and VLL2. */
<> 154:37f96f9d4de2 60 kSLCD_ExteranlVll3UseChargePump =
<> 154:37f96f9d4de2 61 6U, /*!< VLL3 is driven externally and charge pump is used to generate VLL1 and VLL2. */
<> 154:37f96f9d4de2 62 kSLCD_InternalVll1UseChargePump =
<> 154:37f96f9d4de2 63 7U /*!< VIREG is connected to VLL1 internally and charge pump is used to generate VLL2 and VLL3. */
<> 154:37f96f9d4de2 64 } slcd_power_supply_option_t;
<> 154:37f96f9d4de2 65
<> 154:37f96f9d4de2 66 /*! @brief SLCD regulated voltage trim parameter, be used to meet the desired contrast. */
<> 154:37f96f9d4de2 67 typedef enum _slcd_regulated_voltage_trim
<> 154:37f96f9d4de2 68 {
<> 154:37f96f9d4de2 69 kSLCD_RegulatedVolatgeTrim00 = 0U, /*!< Increase the voltage to 0.91 V. */
<> 154:37f96f9d4de2 70 kSLCD_RegulatedVolatgeTrim01, /*!< Increase the voltage to 1.01 V. */
<> 154:37f96f9d4de2 71 kSLCD_RegulatedVolatgeTrim02, /*!< Increase the voltage to 0.96 V. */
<> 154:37f96f9d4de2 72 kSLCD_RegulatedVolatgeTrim03, /*!< Increase the voltage to 1.06 V. */
<> 154:37f96f9d4de2 73 kSLCD_RegulatedVolatgeTrim04, /*!< Increase the voltage to 0.93 V. */
<> 154:37f96f9d4de2 74 kSLCD_RegulatedVolatgeTrim05, /*!< Increase the voltage to 1.02 V. */
<> 154:37f96f9d4de2 75 kSLCD_RegulatedVolatgeTrim06, /*!< Increase the voltage to 0.98 V. */
<> 154:37f96f9d4de2 76 kSLCD_RegulatedVolatgeTrim07, /*!< Increase the voltage to 1.08 V. */
<> 154:37f96f9d4de2 77 kSLCD_RegulatedVolatgeTrim08, /*!< Increase the voltage to 0.92 V. */
<> 154:37f96f9d4de2 78 kSLCD_RegulatedVolatgeTrim09, /*!< Increase the voltage to 1.02 V. */
<> 154:37f96f9d4de2 79 kSLCD_RegulatedVolatgeTrim10, /*!< Increase the voltage to 0.97 V. */
<> 154:37f96f9d4de2 80 kSLCD_RegulatedVolatgeTrim11, /*!< Increase the voltage to 1.07 V. */
<> 154:37f96f9d4de2 81 kSLCD_RegulatedVolatgeTrim12, /*!< Increase the voltage to 0.94 V. */
<> 154:37f96f9d4de2 82 kSLCD_RegulatedVolatgeTrim13, /*!< Increase the voltage to 1.05 V. */
<> 154:37f96f9d4de2 83 kSLCD_RegulatedVolatgeTrim14, /*!< Increase the voltage to 0.99 V. */
<> 154:37f96f9d4de2 84 kSLCD_RegulatedVolatgeTrim15 /*!< Increase the voltage to 1.09 V. */
<> 154:37f96f9d4de2 85 } slcd_regulated_voltage_trim_t;
<> 154:37f96f9d4de2 86
<> 154:37f96f9d4de2 87 /*! @brief SLCD load adjust to handle different LCD glass capacitance or
<> 154:37f96f9d4de2 88 * configure the LCD charge pump clock source.
<> 154:37f96f9d4de2 89 * Adjust the LCD glass capacitance if resistor bias network is enabled:
<> 154:37f96f9d4de2 90 * kSLCD_LowLoadOrFastestClkSrc - Low load (LCD glass capacitance 2000pF or lower.
<> 154:37f96f9d4de2 91 * LCD or GPIO function can be used on VLL1,VLL2,Vcap1 and Vcap2 pins)
<> 154:37f96f9d4de2 92 * kSLCD_LowLoadOrIntermediateClkSrc - low load (LCD glass capacitance 2000pF or lower.
<> 154:37f96f9d4de2 93 * LCD or GPIO function can be used on VLL1,VLL2,Vcap1 and Vcap2 pins)
<> 154:37f96f9d4de2 94 * kSLCD_HighLoadOrIntermediateClkSrc - high load (LCD glass capacitance 8000pF or lower.
<> 154:37f96f9d4de2 95 * LCD or GPIO function can be used on Vcap1 and Vcap2 pins)
<> 154:37f96f9d4de2 96 * kSLCD_HighLoadOrSlowestClkSrc - high load (LCD glass capacitance 8000pF or lower
<> 154:37f96f9d4de2 97 * LCD or GPIO function can be used on Vcap1 and Vcap2 pins)
<> 154:37f96f9d4de2 98 * Adjust clock for charge pump if charge pump is enabled:
<> 154:37f96f9d4de2 99 * kSLCD_LowLoadOrFastestClkSrc - Fasten clock source (LCD glass capacitance
<> 154:37f96f9d4de2 100 * 8000pF or 4000pF or lower if Fast Frame Rate is set)
<> 154:37f96f9d4de2 101 * kSLCD_LowLoadOrIntermediateClkSrc - Intermediate clock source (LCD glass
<> 154:37f96f9d4de2 102 * capacitance 4000pF or 2000pF or lower if Fast Frame Rate is set)
<> 154:37f96f9d4de2 103 * kSLCD_HighLoadOrIntermediateClkSrc - Intermediate clock source (LCD glass
<> 154:37f96f9d4de2 104 * capacitance 2000pF or 1000pF or lower if Fast Frame Rate is set)
<> 154:37f96f9d4de2 105 * kSLCD_HighLoadOrSlowestClkSrc - slowest clock source (LCD glass capacitance
<> 154:37f96f9d4de2 106 * 1000pF or 500pF or lower if Fast Frame Rate is set)
<> 154:37f96f9d4de2 107 */
<> 154:37f96f9d4de2 108 typedef enum _slcd_load_adjust
<> 154:37f96f9d4de2 109 {
<> 154:37f96f9d4de2 110 kSLCD_LowLoadOrFastestClkSrc = 0U, /*!< Adjust in low load or selects fastest clock. */
<> 154:37f96f9d4de2 111 kSLCD_LowLoadOrIntermediateClkSrc, /*!< Adjust in low load or selects intermediate clock. */
<> 154:37f96f9d4de2 112 kSLCD_HighLoadOrIntermediateClkSrc, /*!< Adjust in high load or selects intermediate clock. */
<> 154:37f96f9d4de2 113 kSLCD_HighLoadOrSlowestClkSrc /*!< Adjust in high load or selects slowest clock. */
<> 154:37f96f9d4de2 114 } slcd_load_adjust_t;
<> 154:37f96f9d4de2 115
<> 154:37f96f9d4de2 116 /*! @brief SLCD clock source. */
<> 154:37f96f9d4de2 117 typedef enum _slcd_clock_src
<> 154:37f96f9d4de2 118 {
<> 154:37f96f9d4de2 119 kSLCD_DefaultClk = 0U, /*!< Select default clock ERCLK32K. */
<> 154:37f96f9d4de2 120 kSLCD_AlternateClk1 = 1U, /*!< Select alternate clock source 1 : MCGIRCLK. */
<> 154:37f96f9d4de2 121 #if FSL_FEATURE_SLCD_HAS_MULTI_ALTERNATE_CLOCK_SOURCE
<> 154:37f96f9d4de2 122 kSLCD_AlternateClk2 = 3U /*!< Select alternate clock source 2 : OSCERCLK. */
<> 154:37f96f9d4de2 123 #endif /* FSL_FEATURE_SLCD_HAS_MULTI_ALTERNATE_CLOCK_SOURCE */
<> 154:37f96f9d4de2 124 } slcd_clock_src_t;
<> 154:37f96f9d4de2 125
<> 154:37f96f9d4de2 126 /*! @brief SLCD alternate clock divider. */
<> 154:37f96f9d4de2 127 typedef enum _slcd_alt_clock_div
<> 154:37f96f9d4de2 128 {
<> 154:37f96f9d4de2 129 kSLCD_AltClkDivFactor1 = 0U, /*!< No divide for alternate clock. */
<> 154:37f96f9d4de2 130 kSLCD_AltClkDivFactor64, /*!< Divide alternate clock with factor 64. */
<> 154:37f96f9d4de2 131 kSLCD_AltClkDivFactor256, /*!< Divide alternate clock with factor 256. */
<> 154:37f96f9d4de2 132 kSLCD_AltClkDivFactor512 /*!< Divide alternate clock with factor 512. */
<> 154:37f96f9d4de2 133 } slcd_alt_clock_div_t;
<> 154:37f96f9d4de2 134
<> 154:37f96f9d4de2 135 /*! @brief SLCD clock prescaler to generate frame frequency. */
<> 154:37f96f9d4de2 136 typedef enum _slcd_clock_prescaler
<> 154:37f96f9d4de2 137 {
<> 154:37f96f9d4de2 138 kSLCD_ClkPrescaler00 = 0U, /*!< Prescaler 0. */
<> 154:37f96f9d4de2 139 kSLCD_ClkPrescaler01, /*!< Prescaler 1. */
<> 154:37f96f9d4de2 140 kSLCD_ClkPrescaler02, /*!< Prescaler 2. */
<> 154:37f96f9d4de2 141 kSLCD_ClkPrescaler03, /*!< Prescaler 3. */
<> 154:37f96f9d4de2 142 kSLCD_ClkPrescaler04, /*!< Prescaler 4. */
<> 154:37f96f9d4de2 143 kSLCD_ClkPrescaler05, /*!< Prescaler 5. */
<> 154:37f96f9d4de2 144 kSLCD_ClkPrescaler06, /*!< Prescaler 6. */
<> 154:37f96f9d4de2 145 kSLCD_ClkPrescaler07 /*!< Prescaler 7. */
<> 154:37f96f9d4de2 146 } slcd_clock_prescaler_t;
<> 154:37f96f9d4de2 147
<> 154:37f96f9d4de2 148 /*! @brief SLCD duty cycle. */
<> 154:37f96f9d4de2 149 typedef enum _slcd_duty_cycle
<> 154:37f96f9d4de2 150 {
<> 154:37f96f9d4de2 151 kSLCD_1Div1DutyCycle = 0U, /*!< LCD use 1 BP 1/1 duty cycle. */
<> 154:37f96f9d4de2 152 kSLCD_1Div2DutyCycle, /*!< LCD use 2 BP 1/2 duty cycle. */
<> 154:37f96f9d4de2 153 kSLCD_1Div3DutyCycle, /*!< LCD use 3 BP 1/3 duty cycle. */
<> 154:37f96f9d4de2 154 kSLCD_1Div4DutyCycle, /*!< LCD use 4 BP 1/4 duty cycle. */
<> 154:37f96f9d4de2 155 kSLCD_1Div5DutyCycle, /*!< LCD use 5 BP 1/5 duty cycle. */
<> 154:37f96f9d4de2 156 kSLCD_1Div6DutyCycle, /*!< LCD use 6 BP 1/6 duty cycle. */
<> 154:37f96f9d4de2 157 kSLCD_1Div7DutyCycle, /*!< LCD use 7 BP 1/7 duty cycle. */
<> 154:37f96f9d4de2 158 kSLCD_1Div8DutyCycle /*!< LCD use 8 BP 1/8 duty cycle. */
<> 154:37f96f9d4de2 159 } slcd_duty_cycle_t;
<> 154:37f96f9d4de2 160
<> 154:37f96f9d4de2 161 /*! @brief SLCD segment phase type. */
<> 154:37f96f9d4de2 162 typedef enum _slcd_phase_type
<> 154:37f96f9d4de2 163 {
<> 154:37f96f9d4de2 164 kSLCD_NoPhaseActivate = 0x00U, /*!< LCD wareform no phase activates. */
<> 154:37f96f9d4de2 165 kSLCD_PhaseAActivate = 0x01U, /*!< LCD waveform phase A activates. */
<> 154:37f96f9d4de2 166 kSLCD_PhaseBActivate = 0x02U, /*!< LCD waveform phase B activates. */
<> 154:37f96f9d4de2 167 kSLCD_PhaseCActivate = 0x04U, /*!< LCD waveform phase C activates. */
<> 154:37f96f9d4de2 168 kSLCD_PhaseDActivate = 0x08U, /*!< LCD waveform phase D activates. */
<> 154:37f96f9d4de2 169 kSLCD_PhaseEActivate = 0x10U, /*!< LCD waveform phase E activates. */
<> 154:37f96f9d4de2 170 kSLCD_PhaseFActivate = 0x20U, /*!< LCD waveform phase F activates. */
<> 154:37f96f9d4de2 171 kSLCD_PhaseGActivate = 0x40U, /*!< LCD waveform phase G activates. */
<> 154:37f96f9d4de2 172 kSLCD_PhaseHActivate = 0x80U /*!< LCD waveform phase H activates. */
<> 154:37f96f9d4de2 173 } slcd_phase_type_t;
<> 154:37f96f9d4de2 174
<> 154:37f96f9d4de2 175 /*! @brief SLCD segment phase bit index. */
<> 154:37f96f9d4de2 176 typedef enum _slcd_phase_index
<> 154:37f96f9d4de2 177 {
<> 154:37f96f9d4de2 178 kSLCD_PhaseAIndex = 0x0U, /*!< LCD phase A bit index. */
<> 154:37f96f9d4de2 179 kSLCD_PhaseBIndex = 0x1U, /*!< LCD phase B bit index. */
<> 154:37f96f9d4de2 180 kSLCD_PhaseCIndex = 0x2U, /*!< LCD phase C bit index. */
<> 154:37f96f9d4de2 181 kSLCD_PhaseDIndex = 0x3U, /*!< LCD phase D bit index. */
<> 154:37f96f9d4de2 182 kSLCD_PhaseEIndex = 0x4U, /*!< LCD phase E bit index. */
<> 154:37f96f9d4de2 183 kSLCD_PhaseFIndex = 0x5U, /*!< LCD phase F bit index. */
<> 154:37f96f9d4de2 184 kSLCD_PhaseGIndex = 0x6U, /*!< LCD phase G bit index. */
<> 154:37f96f9d4de2 185 kSLCD_PhaseHIndex = 0x7U /*!< LCD phase H bit index. */
<> 154:37f96f9d4de2 186 } slcd_phase_index_t;
<> 154:37f96f9d4de2 187
<> 154:37f96f9d4de2 188 /*! @brief SLCD display mode. */
<> 154:37f96f9d4de2 189 typedef enum _slcd_display_mode
<> 154:37f96f9d4de2 190 {
<> 154:37f96f9d4de2 191 kSLCD_NormalMode = 0U, /*!< LCD Normal display mode. */
<> 154:37f96f9d4de2 192 kSLCD_AlternateMode, /*!< LCD Alternate display mode. For four back planes or less. */
<> 154:37f96f9d4de2 193 kSLCD_BlankMode /*!< LCD Blank display mode. */
<> 154:37f96f9d4de2 194 } slcd_display_mode_t;
<> 154:37f96f9d4de2 195
<> 154:37f96f9d4de2 196 /*! @brief SLCD blink mode. */
<> 154:37f96f9d4de2 197 typedef enum _slcd_blink_mode
<> 154:37f96f9d4de2 198 {
<> 154:37f96f9d4de2 199 kSLCD_BlankDisplayBlink = 0U, /*!< Display blank during the blink period. */
<> 154:37f96f9d4de2 200 kSLCD_AltDisplayBlink /*!< Display alternate display during the blink period if duty cycle is lower than 5. */
<> 154:37f96f9d4de2 201 } slcd_blink_mode_t;
<> 154:37f96f9d4de2 202
<> 154:37f96f9d4de2 203 /*! @brief SLCD blink rate. */
<> 154:37f96f9d4de2 204 typedef enum _slcd_blink_rate
<> 154:37f96f9d4de2 205 {
<> 154:37f96f9d4de2 206 kSLCD_BlinkRate00 = 0U, /*!< SLCD blink rate is LCD clock/((2^12)). */
<> 154:37f96f9d4de2 207 kSLCD_BlinkRate01, /*!< SLCD blink rate is LCD clock/((2^13)). */
<> 154:37f96f9d4de2 208 kSLCD_BlinkRate02, /*!< SLCD blink rate is LCD clock/((2^14)). */
<> 154:37f96f9d4de2 209 kSLCD_BlinkRate03, /*!< SLCD blink rate is LCD clock/((2^15)). */
<> 154:37f96f9d4de2 210 kSLCD_BlinkRate04, /*!< SLCD blink rate is LCD clock/((2^16)). */
<> 154:37f96f9d4de2 211 kSLCD_BlinkRate05, /*!< SLCD blink rate is LCD clock/((2^17)). */
<> 154:37f96f9d4de2 212 kSLCD_BlinkRate06, /*!< SLCD blink rate is LCD clock/((2^18)). */
<> 154:37f96f9d4de2 213 kSLCD_BlinkRate07 /*!< SLCD blink rate is LCD clock/((2^19)). */
<> 154:37f96f9d4de2 214 } slcd_blink_rate_t;
<> 154:37f96f9d4de2 215
<> 154:37f96f9d4de2 216 /*! @brief SLCD fault detect clock prescaler. */
<> 154:37f96f9d4de2 217 typedef enum _slcd_fault_detect_clock_prescaler
<> 154:37f96f9d4de2 218 {
<> 154:37f96f9d4de2 219 kSLCD_FaultSampleFreqDivider1 = 0U, /*!< Fault detect sample clock frequency is 1/1 bus clock. */
<> 154:37f96f9d4de2 220 kSLCD_FaultSampleFreqDivider2, /*!< Fault detect sample clock frequency is 1/2 bus clock. */
<> 154:37f96f9d4de2 221 kSLCD_FaultSampleFreqDivider4, /*!< Fault detect sample clock frequency is 1/4 bus clock. */
<> 154:37f96f9d4de2 222 kSLCD_FaultSampleFreqDivider8, /*!< Fault detect sample clock frequency is 1/8 bus clock. */
<> 154:37f96f9d4de2 223 kSLCD_FaultSampleFreqDivider16, /*!< Fault detect sample clock frequency is 1/16 bus clock. */
<> 154:37f96f9d4de2 224 kSLCD_FaultSampleFreqDivider32, /*!< Fault detect sample clock frequency is 1/32 bus clock. */
<> 154:37f96f9d4de2 225 kSLCD_FaultSampleFreqDivider64, /*!< Fault detect sample clock frequency is 1/64 bus clock. */
<> 154:37f96f9d4de2 226 kSLCD_FaultSampleFreqDivider128 /*!< Fault detect sample clock frequency is 1/128 bus clock. */
<> 154:37f96f9d4de2 227 } slcd_fault_detect_clock_prescaler_t;
<> 154:37f96f9d4de2 228
<> 154:37f96f9d4de2 229 /*! @brief SLCD fault detect sample window width. */
<> 154:37f96f9d4de2 230 typedef enum _slcd_fault_detect_sample_window_width
<> 154:37f96f9d4de2 231 {
<> 154:37f96f9d4de2 232 kSLCD_FaultDetectWindowWidth4SampleClk = 0U, /*!< Sample window width is 4 sample clock cycles. */
<> 154:37f96f9d4de2 233 kSLCD_FaultDetectWindowWidth8SampleClk, /*!< Sample window width is 8 sample clock cycles. */
<> 154:37f96f9d4de2 234 kSLCD_FaultDetectWindowWidth16SampleClk, /*!< Sample window width is 16 sample clock cycles. */
<> 154:37f96f9d4de2 235 kSLCD_FaultDetectWindowWidth32SampleClk, /*!< Sample window width is 32 sample clock cycles. */
<> 154:37f96f9d4de2 236 kSLCD_FaultDetectWindowWidth64SampleClk, /*!< Sample window width is 64 sample clock cycles. */
<> 154:37f96f9d4de2 237 kSLCD_FaultDetectWindowWidth128SampleClk, /*!< Sample window width is 128 sample clock cycles. */
<> 154:37f96f9d4de2 238 kSLCD_FaultDetectWindowWidth256SampleClk, /*!< Sample window width is 256 sample clock cycles. */
<> 154:37f96f9d4de2 239 kSLCD_FaultDetectWindowWidth512SampleClk /*!< Sample window width is 512 sample clock cycles. */
<> 154:37f96f9d4de2 240 } slcd_fault_detect_sample_window_width_t;
<> 154:37f96f9d4de2 241
<> 154:37f96f9d4de2 242 /*! @brief SLCD interrupt source. */
<> 154:37f96f9d4de2 243 typedef enum _slcd_interrupt_enable
<> 154:37f96f9d4de2 244 {
<> 154:37f96f9d4de2 245 kSLCD_FaultDetectCompleteInterrupt = 1U, /*!< SLCD fault detection complete interrupt source. */
<> 154:37f96f9d4de2 246 #if FSL_FEATURE_SLCD_HAS_FRAME_FREQUENCY_INTERRUPT
<> 154:37f96f9d4de2 247 kSLCD_FrameFreqInterrupt = 2U /*!< SLCD frame frequency interrupt source. Not available in all low-power modes. */
<> 154:37f96f9d4de2 248 #endif /* FSL_FEATURE_SLCD_HAS_FRAME_FREQUENCY_INTERRUPT */
<> 154:37f96f9d4de2 249 } slcd_interrupt_enable_t;
<> 154:37f96f9d4de2 250
<> 154:37f96f9d4de2 251 /*! @brief SLCD behavior in low power mode. */
<> 154:37f96f9d4de2 252 typedef enum _slcd_lowpower_behavior
<> 154:37f96f9d4de2 253 {
<> 154:37f96f9d4de2 254 kSLCD_EnabledInWaitStop = 0, /*!< SLCD works in wait and stop mode. */
<> 154:37f96f9d4de2 255 kSLCD_EnabledInWaitOnly, /*!< SLCD works in wait mode and is disabled in stop mode. */
<> 154:37f96f9d4de2 256 kSLCD_EnabledInStopOnly, /*!< SLCD works in stop mode and is disabled in wait mode. */
<> 154:37f96f9d4de2 257 kSLCD_DisabledInWaitStop /*!< SLCD is disabled in stop mode and wait mode. */
<> 154:37f96f9d4de2 258 } slcd_lowpower_behavior;
<> 154:37f96f9d4de2 259
<> 154:37f96f9d4de2 260 /*! @brief SLCD fault frame detection configure structure. */
<> 154:37f96f9d4de2 261 typedef struct _slcd_fault_detect_config
<> 154:37f96f9d4de2 262 {
<> 154:37f96f9d4de2 263 bool faultDetectIntEnable; /*!< Fault frame detection interrupt enable flag.*/
<> 154:37f96f9d4de2 264 bool faultDetectBackPlaneEnable; /*!< True means the pin id fault detected is back plane otherwise front plane. */
<> 154:37f96f9d4de2 265 uint8_t faultDetectPinIndex; /*!< Fault detected pin id from 0 to 63. */
<> 154:37f96f9d4de2 266 slcd_fault_detect_clock_prescaler_t faultPrescaler; /*!< Fault detect clock prescaler. */
<> 154:37f96f9d4de2 267 slcd_fault_detect_sample_window_width_t width; /*!< Fault detect sample window width. */
<> 154:37f96f9d4de2 268 } slcd_fault_detect_config_t;
<> 154:37f96f9d4de2 269
<> 154:37f96f9d4de2 270 /*! @brief SLCD clock configure structure. */
<> 154:37f96f9d4de2 271 typedef struct _slcd_clock_config
<> 154:37f96f9d4de2 272 {
<> 154:37f96f9d4de2 273 slcd_clock_src_t clkSource; /*!< Clock source. "slcd_clock_src_t" is recommended to be used.
<> 154:37f96f9d4de2 274 The SLCD is optimized to operate using a 32.768kHz clock input. */
<> 154:37f96f9d4de2 275 slcd_alt_clock_div_t
<> 154:37f96f9d4de2 276 altClkDivider; /*!< The divider to divide the alternate clock used for alternate clock source. */
<> 154:37f96f9d4de2 277 slcd_clock_prescaler_t clkPrescaler; /*!< Clock prescaler. */
<> 154:37f96f9d4de2 278 #if FSL_FEATURE_SLCD_HAS_FAST_FRAME_RATE
<> 154:37f96f9d4de2 279 bool fastFrameRateEnable; /*!< Fast frame rate enable flag. */
<> 154:37f96f9d4de2 280 #endif /* FSL_FEATURE_SLCD_HAS_FAST_FRAME_RATE */
<> 154:37f96f9d4de2 281 } slcd_clock_config_t;
<> 154:37f96f9d4de2 282
<> 154:37f96f9d4de2 283 /*! @brief SLCD configure structure. */
<> 154:37f96f9d4de2 284 typedef struct _slcd_config
<> 154:37f96f9d4de2 285 {
<> 154:37f96f9d4de2 286 slcd_power_supply_option_t powerSupply; /*!< Power supply option. */
<> 154:37f96f9d4de2 287 slcd_regulated_voltage_trim_t voltageTrim; /*!< Regulated voltage trim used for the internal regulator VIREG to
<> 154:37f96f9d4de2 288 adjust to facilitate contrast control. */
<> 154:37f96f9d4de2 289 slcd_clock_config_t *clkConfig; /*!< Clock configure. */
<> 154:37f96f9d4de2 290 slcd_display_mode_t displayMode; /*!< SLCD display mode. */
<> 154:37f96f9d4de2 291 slcd_load_adjust_t loadAdjust; /*!< Load adjust to handle glass capacitance. */
<> 154:37f96f9d4de2 292 slcd_duty_cycle_t dutyCycle; /*!< Duty cycle. */
<> 154:37f96f9d4de2 293 slcd_lowpower_behavior lowPowerBehavior; /*!< SLCD behavior in low power mode. */
<> 154:37f96f9d4de2 294 #if FSL_FEATURE_SLCD_HAS_FRAME_FREQUENCY_INTERRUPT
<> 154:37f96f9d4de2 295 bool frameFreqIntEnable; /*!< Frame frequency interrupt enable flag.*/
<> 154:37f96f9d4de2 296 #endif /* FSL_FEATURE_SLCD_HAS_FAST_FRAME_RATE */
<> 154:37f96f9d4de2 297 uint32_t slcdLowPinEnabled; /*!< Setting enabled SLCD pin 0 ~ pin 31. Setting bit n to 1 means enable pin n. */
<> 154:37f96f9d4de2 298 uint32_t
<> 154:37f96f9d4de2 299 slcdHighPinEnabled; /*!< Setting enabled SLCD pin 32 ~ pin 63. Setting bit n to 1 means enable pin (n + 32). */
<> 154:37f96f9d4de2 300 uint32_t backPlaneLowPin; /*!< Setting back plane pin 0 ~ pin 31. Setting bit n to 1 means setting pin n as back
<> 154:37f96f9d4de2 301 plane. It should never have the same bit setting as the frontPlane Pin. */
<> 154:37f96f9d4de2 302 uint32_t backPlaneHighPin; /*!< Setting back plane pin 32 ~ pin 63. Setting bit n to 1 means setting pin (n + 32) as
<> 154:37f96f9d4de2 303 back plane. It should never have the same bit setting as the frontPlane Pin. */
<> 154:37f96f9d4de2 304 slcd_fault_detect_config_t *faultConfig; /*!< Fault frame detection configure. If not requirement, set to NULL. */
<> 154:37f96f9d4de2 305 } slcd_config_t;
<> 154:37f96f9d4de2 306 /*******************************************************************************
<> 154:37f96f9d4de2 307 * API
<> 154:37f96f9d4de2 308 ******************************************************************************/
<> 154:37f96f9d4de2 309
<> 154:37f96f9d4de2 310 #if defined(__cplusplus)
<> 154:37f96f9d4de2 311 extern "C" {
<> 154:37f96f9d4de2 312 #endif /* __cplusplus*/
<> 154:37f96f9d4de2 313
<> 154:37f96f9d4de2 314 /*!
<> 154:37f96f9d4de2 315 * @name Initialization and deinitialization
<> 154:37f96f9d4de2 316 * @{
<> 154:37f96f9d4de2 317 */
<> 154:37f96f9d4de2 318
<> 154:37f96f9d4de2 319 /*!
<> 154:37f96f9d4de2 320 * @brief Initializes the SLCD, ungates the module clock, initializes the power
<> 154:37f96f9d4de2 321 * setting, enables all used plane pins, and sets with interrupt and work mode
<> 154:37f96f9d4de2 322 * with configuration.
<> 154:37f96f9d4de2 323 *
<> 154:37f96f9d4de2 324 * @param base SLCD peripheral base address.
<> 154:37f96f9d4de2 325 * @param configure SLCD configuration pointer.
<> 154:37f96f9d4de2 326 * For the configuration structure, many parameters have the default setting
<> 154:37f96f9d4de2 327 * and the SLCD_Getdefaultconfig() is provided to get them. Use it
<> 154:37f96f9d4de2 328 * verified for their applications.
<> 154:37f96f9d4de2 329 * The others have no default settings such as "clkConfig" and must be provided
<> 154:37f96f9d4de2 330 * by the application before calling the SLCD_Init() API.
<> 154:37f96f9d4de2 331 */
<> 154:37f96f9d4de2 332 void SLCD_Init(LCD_Type *base, slcd_config_t *configure);
<> 154:37f96f9d4de2 333
<> 154:37f96f9d4de2 334 /*!
<> 154:37f96f9d4de2 335 * @brief Deinitializes the SLCD module, gates the module clock, disables an interrupt,
<> 154:37f96f9d4de2 336 * and displays the SLCD.
<> 154:37f96f9d4de2 337 *
<> 154:37f96f9d4de2 338 * @param base SLCD peripheral base address.
<> 154:37f96f9d4de2 339 */
<> 154:37f96f9d4de2 340 void SLCD_Deinit(LCD_Type *base);
<> 154:37f96f9d4de2 341
<> 154:37f96f9d4de2 342 /*!
<> 154:37f96f9d4de2 343 * @brief Gets the SLCD default configuration structure. The
<> 154:37f96f9d4de2 344 * purpose of this API is to get default parameters of the configuration structure
<> 154:37f96f9d4de2 345 * for the SLCD_Init(). Use these initialized parameters unchanged in SLCD_Init(),
<> 154:37f96f9d4de2 346 * or modify some fields of the structure before the calling SLCD_Init().
<> 154:37f96f9d4de2 347 * All default parameters of the configure structure are listed:
<> 154:37f96f9d4de2 348 * @code
<> 154:37f96f9d4de2 349 config.displayMode = kSLCD_NormalMode; // SLCD normal mode
<> 154:37f96f9d4de2 350 config.powerSupply = kSLCD_InternalVll3UseChargePump; // Use charge pump internal VLL3
<> 154:37f96f9d4de2 351 config.voltageTrim = kSLCD_RegulatedVolatgeTrim00;
<> 154:37f96f9d4de2 352 config.lowPowerBehavior = kSLCD_EnabledInWaitStop; // Work on low power mode
<> 154:37f96f9d4de2 353 config.interruptSrc = 0; // No interrupt source is enabled
<> 154:37f96f9d4de2 354 config.faultConfig = NULL; // Fault detection is disabled
<> 154:37f96f9d4de2 355 config.frameFreqIntEnable = false;
<> 154:37f96f9d4de2 356 @endcode
<> 154:37f96f9d4de2 357 * @param configure The SLCD configuration structure pointer.
<> 154:37f96f9d4de2 358 */
<> 154:37f96f9d4de2 359 void SLCD_GetDefaultConfig(slcd_config_t *configure);
<> 154:37f96f9d4de2 360
<> 154:37f96f9d4de2 361 /* @}*/
<> 154:37f96f9d4de2 362
<> 154:37f96f9d4de2 363 /*!
<> 154:37f96f9d4de2 364 * @name Plane Setting and Display Control
<> 154:37f96f9d4de2 365 * @{
<> 154:37f96f9d4de2 366 */
<> 154:37f96f9d4de2 367
<> 154:37f96f9d4de2 368 /*!
<> 154:37f96f9d4de2 369 * @brief Enables the SLCD controller, starts generate, and displays the front plane and back plane waveform.
<> 154:37f96f9d4de2 370 *
<> 154:37f96f9d4de2 371 * @param base SLCD peripheral base address.
<> 154:37f96f9d4de2 372 */
<> 154:37f96f9d4de2 373 static inline void SLCD_StartDisplay(LCD_Type *base)
<> 154:37f96f9d4de2 374 {
<> 154:37f96f9d4de2 375 base->GCR |= LCD_GCR_LCDEN_MASK;
<> 154:37f96f9d4de2 376 }
<> 154:37f96f9d4de2 377
<> 154:37f96f9d4de2 378 /*!
<> 154:37f96f9d4de2 379 * @brief Stops the SLCD controller. There is no waveform generator and all enabled pins
<> 154:37f96f9d4de2 380 * only output a low value.
<> 154:37f96f9d4de2 381 *
<> 154:37f96f9d4de2 382 * @param base SLCD peripheral base address.
<> 154:37f96f9d4de2 383 */
<> 154:37f96f9d4de2 384 static inline void SLCD_StopDisplay(LCD_Type *base)
<> 154:37f96f9d4de2 385 {
<> 154:37f96f9d4de2 386 base->GCR &= ~LCD_GCR_LCDEN_MASK;
<> 154:37f96f9d4de2 387 }
<> 154:37f96f9d4de2 388
<> 154:37f96f9d4de2 389 /*!
<> 154:37f96f9d4de2 390 * @brief Starts the SLCD blink mode.
<> 154:37f96f9d4de2 391 *
<> 154:37f96f9d4de2 392 * @param base SLCD peripheral base address.
<> 154:37f96f9d4de2 393 * @param mode SLCD blink mode.
<> 154:37f96f9d4de2 394 * @param rate SLCD blink rate.
<> 154:37f96f9d4de2 395 */
<> 154:37f96f9d4de2 396 void SLCD_StartBlinkMode(LCD_Type *base, slcd_blink_mode_t mode, slcd_blink_rate_t rate);
<> 154:37f96f9d4de2 397
<> 154:37f96f9d4de2 398 /*!
<> 154:37f96f9d4de2 399 * @brief Stops the SLCD blink mode.
<> 154:37f96f9d4de2 400 *
<> 154:37f96f9d4de2 401 * @param base SLCD peripheral base address.
<> 154:37f96f9d4de2 402 */
<> 154:37f96f9d4de2 403 static inline void SLCD_StopBlinkMode(LCD_Type *base)
<> 154:37f96f9d4de2 404 {
<> 154:37f96f9d4de2 405 base->AR &= ~LCD_AR_BLINK_MASK;
<> 154:37f96f9d4de2 406 }
<> 154:37f96f9d4de2 407
<> 154:37f96f9d4de2 408 /*!
<> 154:37f96f9d4de2 409 * @brief Sets the SLCD back plane pin phase.
<> 154:37f96f9d4de2 410 *
<> 154:37f96f9d4de2 411 * This function sets the SLCD back plane pin phase. "kSLCD_PhaseXActivate" setting
<> 154:37f96f9d4de2 412 * means the phase X is active for the back plane pin. "kSLCD_NoPhaseActivate" setting
<> 154:37f96f9d4de2 413 * means there is no phase active for the back plane pin.
<> 154:37f96f9d4de2 414 * register value.
<> 154:37f96f9d4de2 415 * For example, set the back plane pin 20 for phase A:
<> 154:37f96f9d4de2 416 * @code
<> 154:37f96f9d4de2 417 * SLCD_SetBackPlanePhase(LCD, 20, kSLCD_PhaseAActivate);
<> 154:37f96f9d4de2 418 * @endcode
<> 154:37f96f9d4de2 419 *
<> 154:37f96f9d4de2 420 * @param base SLCD peripheral base address.
<> 154:37f96f9d4de2 421 * @param pinIndx SLCD back plane pin index. Range from 0 to 63.
<> 154:37f96f9d4de2 422 * @param phase The phase activates for the back plane pin.
<> 154:37f96f9d4de2 423 */
<> 154:37f96f9d4de2 424 static inline void SLCD_SetBackPlanePhase(LCD_Type *base, uint32_t pinIndx, slcd_phase_type_t phase)
<> 154:37f96f9d4de2 425 {
<> 154:37f96f9d4de2 426 base->WF8B[pinIndx] = phase;
<> 154:37f96f9d4de2 427 }
<> 154:37f96f9d4de2 428
<> 154:37f96f9d4de2 429 /*!
<> 154:37f96f9d4de2 430 * @brief Sets the SLCD front plane segment operation for a front plane pin.
<> 154:37f96f9d4de2 431 *
<> 154:37f96f9d4de2 432 * This function sets the SLCD front plane segment on or off operation.
<> 154:37f96f9d4de2 433 * Each bit turns on or off the segments associated with the front plane pin in
<> 154:37f96f9d4de2 434 * the following pattern: HGFEDCBA (most significant bit controls segment H and
<> 154:37f96f9d4de2 435 * least significant bit controls segment A).
<> 154:37f96f9d4de2 436 * For example, turn on the front plane pin 20 for phase B and phase C:
<> 154:37f96f9d4de2 437 * @code
<> 154:37f96f9d4de2 438 * SLCD_SetFrontPlaneSegments(LCD, 20, (kSLCD_PhaseBActivate | kSLCD_PhaseCActivate));
<> 154:37f96f9d4de2 439 * @endcode
<> 154:37f96f9d4de2 440 *
<> 154:37f96f9d4de2 441 * @param base SLCD peripheral base address.
<> 154:37f96f9d4de2 442 * @param pinIndx SLCD back plane pin index. Range from 0 to 63.
<> 154:37f96f9d4de2 443 * @param operation The operation for the segment on the front plane pin.
<> 154:37f96f9d4de2 444 * This is a logical OR of the enumeration :: slcd_phase_type_t.
<> 154:37f96f9d4de2 445 */
<> 154:37f96f9d4de2 446 static inline void SLCD_SetFrontPlaneSegments(LCD_Type *base, uint32_t pinIndx, uint8_t operation)
<> 154:37f96f9d4de2 447 {
<> 154:37f96f9d4de2 448 base->WF8B[pinIndx] = operation;
<> 154:37f96f9d4de2 449 }
<> 154:37f96f9d4de2 450
<> 154:37f96f9d4de2 451 /*!
<> 154:37f96f9d4de2 452 * @brief Sets one SLCD front plane pin for one phase.
<> 154:37f96f9d4de2 453 *
<> 154:37f96f9d4de2 454 * This function can be used to set one phase on or off for the front plane pin.
<> 154:37f96f9d4de2 455 * It can be call many times to set the plane pin for different phase indexes.
<> 154:37f96f9d4de2 456 * For example, turn on the front plane pin 20 for phase B and phase C:
<> 154:37f96f9d4de2 457 * @code
<> 154:37f96f9d4de2 458 * SLCD_SetFrontPlaneOnePhase(LCD, 20, kSLCD_PhaseBIndex, true);
<> 154:37f96f9d4de2 459 * SLCD_SetFrontPlaneOnePhase(LCD, 20, kSLCD_PhaseCIndex, true);
<> 154:37f96f9d4de2 460 * @endcode
<> 154:37f96f9d4de2 461 *
<> 154:37f96f9d4de2 462 * @param base SLCD peripheral base address.
<> 154:37f96f9d4de2 463 * @param pinIndx SLCD back plane pin index. Range from 0 to 63.
<> 154:37f96f9d4de2 464 * @param phaseIndx The phase bit index @ref slcd_phase_index_t.
<> 154:37f96f9d4de2 465 * @param enable True to turn on the segment for phaseIndx phase
<> 154:37f96f9d4de2 466 * false to turn off the segment for phaseIndx phase.
<> 154:37f96f9d4de2 467 */
<> 154:37f96f9d4de2 468 static inline void SLCD_SetFrontPlaneOnePhase(LCD_Type *base,
<> 154:37f96f9d4de2 469 uint32_t pinIndx,
<> 154:37f96f9d4de2 470 slcd_phase_index_t phaseIndx,
<> 154:37f96f9d4de2 471 bool enable)
<> 154:37f96f9d4de2 472 {
<> 154:37f96f9d4de2 473 uint8_t reg = base->WF8B[pinIndx];
<> 154:37f96f9d4de2 474
<> 154:37f96f9d4de2 475 if (enable)
<> 154:37f96f9d4de2 476 {
<> 154:37f96f9d4de2 477 base->WF8B[pinIndx] = (reg | (1U << phaseIndx));
<> 154:37f96f9d4de2 478 }
<> 154:37f96f9d4de2 479 else
<> 154:37f96f9d4de2 480 {
<> 154:37f96f9d4de2 481 base->WF8B[pinIndx] = (reg & ~(1U << phaseIndx));
<> 154:37f96f9d4de2 482 }
<> 154:37f96f9d4de2 483 }
<> 154:37f96f9d4de2 484
<> 154:37f96f9d4de2 485 #if FSL_FEATURE_SLCD_HAS_PAD_SAFE
<> 154:37f96f9d4de2 486 /*!
<> 154:37f96f9d4de2 487 * @brief Enables/disables the SLCD pad safe state.
<> 154:37f96f9d4de2 488 *
<> 154:37f96f9d4de2 489 * Forces the safe state on the LCD pad controls. All LCD front plane
<> 154:37f96f9d4de2 490 * and backplane functions are disabled.
<> 154:37f96f9d4de2 491 *
<> 154:37f96f9d4de2 492 * @param base SLCD peripheral base address.
<> 154:37f96f9d4de2 493 * @param enable True enable, false disable.
<> 154:37f96f9d4de2 494 */
<> 154:37f96f9d4de2 495 static inline void SLCD_EnablePadSafeState(LCD_Type *base, bool enable)
<> 154:37f96f9d4de2 496 {
<> 154:37f96f9d4de2 497 if (enable)
<> 154:37f96f9d4de2 498 { /* Enable. */
<> 154:37f96f9d4de2 499 base->GCR |= LCD_GCR_PADSAFE_MASK;
<> 154:37f96f9d4de2 500 }
<> 154:37f96f9d4de2 501 else
<> 154:37f96f9d4de2 502 { /* Disable. */
<> 154:37f96f9d4de2 503 base->GCR &= ~LCD_GCR_PADSAFE_MASK;
<> 154:37f96f9d4de2 504 }
<> 154:37f96f9d4de2 505 }
<> 154:37f96f9d4de2 506 #endif /* FSL_FEATURE_SLCD_HAS_PAD_SAFE */
<> 154:37f96f9d4de2 507
<> 154:37f96f9d4de2 508 /*!
<> 154:37f96f9d4de2 509 * @brief Gets the SLCD fault detect counter.
<> 154:37f96f9d4de2 510 *
<> 154:37f96f9d4de2 511 * This function gets the number of samples inside the
<> 154:37f96f9d4de2 512 * fault detection sample window.
<> 154:37f96f9d4de2 513 *
<> 154:37f96f9d4de2 514 * @param base SLCD peripheral base address.
<> 154:37f96f9d4de2 515 * @return The fault detect counter. The maximum return value is 255.
<> 154:37f96f9d4de2 516 * If the maximum 255 returns, the overflow may happen.
<> 154:37f96f9d4de2 517 * Reconfigure the fault detect sample window and fault detect clock prescaler
<> 154:37f96f9d4de2 518 * for proper sampling.
<> 154:37f96f9d4de2 519 */
<> 154:37f96f9d4de2 520 static inline uint32_t SLCD_GetFaultDetectCounter(LCD_Type *base)
<> 154:37f96f9d4de2 521 {
<> 154:37f96f9d4de2 522 return base->FDSR & LCD_FDSR_FDCNT_MASK;
<> 154:37f96f9d4de2 523 }
<> 154:37f96f9d4de2 524
<> 154:37f96f9d4de2 525 /* @} */
<> 154:37f96f9d4de2 526
<> 154:37f96f9d4de2 527 /*!
<> 154:37f96f9d4de2 528 * @name Interrupts.
<> 154:37f96f9d4de2 529 * @{
<> 154:37f96f9d4de2 530 */
<> 154:37f96f9d4de2 531
<> 154:37f96f9d4de2 532 /*!
<> 154:37f96f9d4de2 533 * @brief Enables the SLCD interrupt.
<> 154:37f96f9d4de2 534 * For example, to enable fault detect complete interrupt and frame frequency interrupt,
<> 154:37f96f9d4de2 535 * for FSL_FEATURE_SLCD_HAS_FRAME_FREQUENCY_INTERRUPT enabled case, do the following.
<> 154:37f96f9d4de2 536 * @code
<> 154:37f96f9d4de2 537 * SLCD_EnableInterrupts(LCD,kSLCD_FaultDetectCompleteInterrupt | kSLCD_FrameFreqInterrupt);
<> 154:37f96f9d4de2 538 * @endcode
<> 154:37f96f9d4de2 539 *
<> 154:37f96f9d4de2 540 * @param base SLCD peripheral base address.
<> 154:37f96f9d4de2 541 * @param mask SLCD interrupts to enable. This is a logical OR of the
<> 154:37f96f9d4de2 542 * enumeration :: slcd_interrupt_enable_t.
<> 154:37f96f9d4de2 543 */
<> 154:37f96f9d4de2 544 void SLCD_EnableInterrupts(LCD_Type *base, uint32_t mask);
<> 154:37f96f9d4de2 545
<> 154:37f96f9d4de2 546 /*!
<> 154:37f96f9d4de2 547 * @brief Disables the SLCD interrupt.
<> 154:37f96f9d4de2 548 * For example, to disable fault detect complete interrupt and frame frequency interrupt,
<> 154:37f96f9d4de2 549 * for FSL_FEATURE_SLCD_HAS_FRAME_FREQUENCY_INTERRUPT enabled case, do the following.
<> 154:37f96f9d4de2 550 * @code
<> 154:37f96f9d4de2 551 * SLCD_DisableInterrupts(LCD,kSLCD_FaultDetectCompleteInterrupt | kSLCD_FrameFreqInterrupt);
<> 154:37f96f9d4de2 552 * @endcode
<> 154:37f96f9d4de2 553 *
<> 154:37f96f9d4de2 554 * @param base SLCD peripheral base address.
<> 154:37f96f9d4de2 555 * @param mask SLCD interrupts to disable. This is a logical OR of the
<> 154:37f96f9d4de2 556 * enumeration :: slcd_interrupt_enable_t.
<> 154:37f96f9d4de2 557 */
<> 154:37f96f9d4de2 558 void SLCD_DisableInterrupts(LCD_Type *base, uint32_t mask);
<> 154:37f96f9d4de2 559
<> 154:37f96f9d4de2 560 /*!
<> 154:37f96f9d4de2 561 * @brief Gets the SLCD interrupt status flag.
<> 154:37f96f9d4de2 562 *
<> 154:37f96f9d4de2 563 * @param base SLCD peripheral base address.
<> 154:37f96f9d4de2 564 * @return The event status of the interrupt source. This is the logical OR of members
<> 154:37f96f9d4de2 565 * of the enumeration :: slcd_interrupt_enable_t.
<> 154:37f96f9d4de2 566 */
<> 154:37f96f9d4de2 567 uint32_t SLCD_GetInterruptStatus(LCD_Type *base);
<> 154:37f96f9d4de2 568
<> 154:37f96f9d4de2 569 /*!
<> 154:37f96f9d4de2 570 * @brief Clears the SLCD interrupt events status flag.
<> 154:37f96f9d4de2 571 *
<> 154:37f96f9d4de2 572 * @param base SLCD peripheral base address.
<> 154:37f96f9d4de2 573 * @param mask SLCD interrupt source to be cleared.
<> 154:37f96f9d4de2 574 * This is the logical OR of members of the enumeration :: slcd_interrupt_enable_t.
<> 154:37f96f9d4de2 575 */
<> 154:37f96f9d4de2 576 void SLCD_ClearInterruptStatus(LCD_Type *base, uint32_t mask);
<> 154:37f96f9d4de2 577
<> 154:37f96f9d4de2 578 /* @} */
<> 154:37f96f9d4de2 579
<> 154:37f96f9d4de2 580 #if defined(__cplusplus)
<> 154:37f96f9d4de2 581 }
<> 154:37f96f9d4de2 582 #endif /* __cplusplus*/
<> 154:37f96f9d4de2 583
<> 154:37f96f9d4de2 584 /*! @}*/
<> 154:37f96f9d4de2 585
<> 154:37f96f9d4de2 586 #endif /* _FSL_SLCD_H_*/