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targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL27Z/drivers/fsl_flexio_spi.h@154:37f96f9d4de2, 2017-01-04 (annotated)

Committer:
<>
Date:
Wed Jan 04 16:58:05 2017 +0000
Revision:
154:37f96f9d4de2
This updates the lib to the mbed lib v133

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 154:37f96f9d4de2 1 /*
<> 154:37f96f9d4de2 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
<> 154:37f96f9d4de2 3 * All rights reserved.
<> 154:37f96f9d4de2 4 *
<> 154:37f96f9d4de2 5 * Redistribution and use in source and binary forms, with or without modification,
<> 154:37f96f9d4de2 6 * are permitted provided that the following conditions are met:
<> 154:37f96f9d4de2 7 *
<> 154:37f96f9d4de2 8 * o Redistributions of source code must retain the above copyright notice, this list
<> 154:37f96f9d4de2 9 * of conditions and the following disclaimer.
<> 154:37f96f9d4de2 10 *
<> 154:37f96f9d4de2 11 * o Redistributions in binary form must reproduce the above copyright notice, this
<> 154:37f96f9d4de2 12 * list of conditions and the following disclaimer in the documentation and/or
<> 154:37f96f9d4de2 13 * other materials provided with the distribution.
<> 154:37f96f9d4de2 14 *
<> 154:37f96f9d4de2 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
<> 154:37f96f9d4de2 16 * contributors may be used to endorse or promote products derived from this
<> 154:37f96f9d4de2 17 * software without specific prior written permission.
<> 154:37f96f9d4de2 18 *
<> 154:37f96f9d4de2 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
<> 154:37f96f9d4de2 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
<> 154:37f96f9d4de2 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 154:37f96f9d4de2 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
<> 154:37f96f9d4de2 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
<> 154:37f96f9d4de2 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
<> 154:37f96f9d4de2 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
<> 154:37f96f9d4de2 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
<> 154:37f96f9d4de2 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
<> 154:37f96f9d4de2 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 154:37f96f9d4de2 29 */
<> 154:37f96f9d4de2 30
<> 154:37f96f9d4de2 31 #ifndef _FSL_FLEXIO_SPI_H_
<> 154:37f96f9d4de2 32 #define _FSL_FLEXIO_SPI_H_
<> 154:37f96f9d4de2 33
<> 154:37f96f9d4de2 34 #include "fsl_common.h"
<> 154:37f96f9d4de2 35 #include "fsl_flexio.h"
<> 154:37f96f9d4de2 36
<> 154:37f96f9d4de2 37 /*!
<> 154:37f96f9d4de2 38 * @addtogroup flexio_spi
<> 154:37f96f9d4de2 39 * @{
<> 154:37f96f9d4de2 40 */
<> 154:37f96f9d4de2 41
<> 154:37f96f9d4de2 42 /*! @file */
<> 154:37f96f9d4de2 43
<> 154:37f96f9d4de2 44 /*******************************************************************************
<> 154:37f96f9d4de2 45 * Definitions
<> 154:37f96f9d4de2 46 ******************************************************************************/
<> 154:37f96f9d4de2 47
<> 154:37f96f9d4de2 48 /*! @name Driver version */
<> 154:37f96f9d4de2 49 /*@{*/
<> 154:37f96f9d4de2 50 /*! @brief FlexIO SPI driver version 2.1.0. */
<> 154:37f96f9d4de2 51 #define FSL_FLEXIO_SPI_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))
<> 154:37f96f9d4de2 52 /*@}*/
<> 154:37f96f9d4de2 53
<> 154:37f96f9d4de2 54 /*! @brief FlexIO SPI dummy transfer data, the data is sent while txData is NULL. */
<> 154:37f96f9d4de2 55 #define FLEXIO_SPI_DUMMYDATA (0xFFFFU)
<> 154:37f96f9d4de2 56
<> 154:37f96f9d4de2 57 /*! @brief Error codes for the FlexIO SPI driver. */
<> 154:37f96f9d4de2 58 enum _flexio_spi_status
<> 154:37f96f9d4de2 59 {
<> 154:37f96f9d4de2 60 kStatus_FLEXIO_SPI_Busy = MAKE_STATUS(kStatusGroup_FLEXIO_SPI, 1), /*!< FlexIO SPI is busy. */
<> 154:37f96f9d4de2 61 kStatus_FLEXIO_SPI_Idle = MAKE_STATUS(kStatusGroup_FLEXIO_SPI, 2), /*!< SPI is idle */
<> 154:37f96f9d4de2 62 kStatus_FLEXIO_SPI_Error = MAKE_STATUS(kStatusGroup_FLEXIO_SPI, 3), /*!< FlexIO SPI error. */
<> 154:37f96f9d4de2 63 };
<> 154:37f96f9d4de2 64
<> 154:37f96f9d4de2 65 /*! @brief FlexIO SPI clock phase configuration. */
<> 154:37f96f9d4de2 66 typedef enum _flexio_spi_clock_phase
<> 154:37f96f9d4de2 67 {
<> 154:37f96f9d4de2 68 kFLEXIO_SPI_ClockPhaseFirstEdge = 0x0U, /*!< First edge on SPSCK occurs at the middle of the first
<> 154:37f96f9d4de2 69 * cycle of a data transfer. */
<> 154:37f96f9d4de2 70 kFLEXIO_SPI_ClockPhaseSecondEdge = 0x1U, /*!< First edge on SPSCK occurs at the start of the
<> 154:37f96f9d4de2 71 * first cycle of a data transfer. */
<> 154:37f96f9d4de2 72 } flexio_spi_clock_phase_t;
<> 154:37f96f9d4de2 73
<> 154:37f96f9d4de2 74 /*! @brief FlexIO SPI data shifter direction options. */
<> 154:37f96f9d4de2 75 typedef enum _flexio_spi_shift_direction
<> 154:37f96f9d4de2 76 {
<> 154:37f96f9d4de2 77 kFLEXIO_SPI_MsbFirst = 0, /*!< Data transfers start with most significant bit. */
<> 154:37f96f9d4de2 78 kFLEXIO_SPI_LsbFirst = 1, /*!< Data transfers start with least significant bit. */
<> 154:37f96f9d4de2 79 } flexio_spi_shift_direction_t;
<> 154:37f96f9d4de2 80
<> 154:37f96f9d4de2 81 /*! @brief FlexIO SPI data length mode options. */
<> 154:37f96f9d4de2 82 typedef enum _flexio_spi_data_bitcount_mode
<> 154:37f96f9d4de2 83 {
<> 154:37f96f9d4de2 84 kFLEXIO_SPI_8BitMode = 0x08U, /*!< 8-bit data transmission mode. */
<> 154:37f96f9d4de2 85 kFLEXIO_SPI_16BitMode = 0x10U, /*!< 16-bit data transmission mode. */
<> 154:37f96f9d4de2 86 } flexio_spi_data_bitcount_mode_t;
<> 154:37f96f9d4de2 87
<> 154:37f96f9d4de2 88 /*! @brief Define FlexIO SPI interrupt mask. */
<> 154:37f96f9d4de2 89 enum _flexio_spi_interrupt_enable
<> 154:37f96f9d4de2 90 {
<> 154:37f96f9d4de2 91 kFLEXIO_SPI_TxEmptyInterruptEnable = 0x1U, /*!< Transmit buffer empty interrupt enable. */
<> 154:37f96f9d4de2 92 kFLEXIO_SPI_RxFullInterruptEnable = 0x2U, /*!< Receive buffer full interrupt enable. */
<> 154:37f96f9d4de2 93 };
<> 154:37f96f9d4de2 94
<> 154:37f96f9d4de2 95 /*! @brief Define FlexIO SPI status mask. */
<> 154:37f96f9d4de2 96 enum _flexio_spi_status_flags
<> 154:37f96f9d4de2 97 {
<> 154:37f96f9d4de2 98 kFLEXIO_SPI_TxBufferEmptyFlag = 0x1U, /*!< Transmit buffer empty flag. */
<> 154:37f96f9d4de2 99 kFLEXIO_SPI_RxBufferFullFlag = 0x2U, /*!< Receive buffer full flag. */
<> 154:37f96f9d4de2 100 };
<> 154:37f96f9d4de2 101
<> 154:37f96f9d4de2 102 /*! @brief Define FlexIO SPI DMA mask. */
<> 154:37f96f9d4de2 103 enum _flexio_spi_dma_enable
<> 154:37f96f9d4de2 104 {
<> 154:37f96f9d4de2 105 kFLEXIO_SPI_TxDmaEnable = 0x1U, /*!< Tx DMA request source */
<> 154:37f96f9d4de2 106 kFLEXIO_SPI_RxDmaEnable = 0x2U, /*!< Rx DMA request source */
<> 154:37f96f9d4de2 107 kFLEXIO_SPI_DmaAllEnable = 0x3U, /*!< All DMA request source*/
<> 154:37f96f9d4de2 108 };
<> 154:37f96f9d4de2 109
<> 154:37f96f9d4de2 110 /*! @brief Define FlexIO SPI transfer flags. */
<> 154:37f96f9d4de2 111 enum _flexio_spi_transfer_flags
<> 154:37f96f9d4de2 112 {
<> 154:37f96f9d4de2 113 kFLEXIO_SPI_8bitMsb = 0x1U, /*!< FlexIO SPI 8-bit MSB first */
<> 154:37f96f9d4de2 114 kFLEXIO_SPI_8bitLsb = 0x2U, /*!< FlexIO SPI 8-bit LSB first */
<> 154:37f96f9d4de2 115 kFLEXIO_SPI_16bitMsb = 0x9U, /*!< FlexIO SPI 16-bit MSB first */
<> 154:37f96f9d4de2 116 kFLEXIO_SPI_16bitLsb = 0xaU, /*!< FlexIO SPI 16-bit LSB first */
<> 154:37f96f9d4de2 117 };
<> 154:37f96f9d4de2 118
<> 154:37f96f9d4de2 119 /*! @brief Define FlexIO SPI access structure typedef. */
<> 154:37f96f9d4de2 120 typedef struct _flexio_spi_type
<> 154:37f96f9d4de2 121 {
<> 154:37f96f9d4de2 122 FLEXIO_Type *flexioBase; /*!< FlexIO base pointer. */
<> 154:37f96f9d4de2 123 uint8_t SDOPinIndex; /*!< Pin select for data output. */
<> 154:37f96f9d4de2 124 uint8_t SDIPinIndex; /*!< Pin select for data input. */
<> 154:37f96f9d4de2 125 uint8_t SCKPinIndex; /*!< Pin select for clock. */
<> 154:37f96f9d4de2 126 uint8_t CSnPinIndex; /*!< Pin select for enable. */
<> 154:37f96f9d4de2 127 uint8_t shifterIndex[2]; /*!< Shifter index used in FlexIO SPI. */
<> 154:37f96f9d4de2 128 uint8_t timerIndex[2]; /*!< Timer index used in FlexIO SPI. */
<> 154:37f96f9d4de2 129 } FLEXIO_SPI_Type;
<> 154:37f96f9d4de2 130
<> 154:37f96f9d4de2 131 /*! @brief Define FlexIO SPI master configuration structure. */
<> 154:37f96f9d4de2 132 typedef struct _flexio_spi_master_config
<> 154:37f96f9d4de2 133 {
<> 154:37f96f9d4de2 134 bool enableMaster; /*!< Enable/disable FlexIO SPI master after configuration. */
<> 154:37f96f9d4de2 135 bool enableInDoze; /*!< Enable/disable FlexIO operation in doze mode. */
<> 154:37f96f9d4de2 136 bool enableInDebug; /*!< Enable/disable FlexIO operation in debug mode. */
<> 154:37f96f9d4de2 137 bool enableFastAccess; /*!< Enable/disable fast access to FlexIO registers,
<> 154:37f96f9d4de2 138 fast access requires the FlexIO clock to be at least
<> 154:37f96f9d4de2 139 twice the frequency of the bus clock. */
<> 154:37f96f9d4de2 140 uint32_t baudRate_Bps; /*!< Baud rate in Bps. */
<> 154:37f96f9d4de2 141 flexio_spi_clock_phase_t phase; /*!< Clock phase. */
<> 154:37f96f9d4de2 142 flexio_spi_data_bitcount_mode_t dataMode; /*!< 8bit or 16bit mode. */
<> 154:37f96f9d4de2 143 } flexio_spi_master_config_t;
<> 154:37f96f9d4de2 144
<> 154:37f96f9d4de2 145 /*! @brief Define FlexIO SPI slave configuration structure. */
<> 154:37f96f9d4de2 146 typedef struct _flexio_spi_slave_config
<> 154:37f96f9d4de2 147 {
<> 154:37f96f9d4de2 148 bool enableSlave; /*!< Enable/disable FlexIO SPI slave after configuration. */
<> 154:37f96f9d4de2 149 bool enableInDoze; /*!< Enable/disable FlexIO operation in doze mode. */
<> 154:37f96f9d4de2 150 bool enableInDebug; /*!< Enable/disable FlexIO operation in debug mode. */
<> 154:37f96f9d4de2 151 bool enableFastAccess; /*!< Enable/disable fast access to FlexIO registers,
<> 154:37f96f9d4de2 152 fast access requires the FlexIO clock to be at least
<> 154:37f96f9d4de2 153 twice the frequency of the bus clock. */
<> 154:37f96f9d4de2 154 flexio_spi_clock_phase_t phase; /*!< Clock phase. */
<> 154:37f96f9d4de2 155 flexio_spi_data_bitcount_mode_t dataMode; /*!< 8bit or 16bit mode. */
<> 154:37f96f9d4de2 156 } flexio_spi_slave_config_t;
<> 154:37f96f9d4de2 157
<> 154:37f96f9d4de2 158 /*! @brief Define FlexIO SPI transfer structure. */
<> 154:37f96f9d4de2 159 typedef struct _flexio_spi_transfer
<> 154:37f96f9d4de2 160 {
<> 154:37f96f9d4de2 161 uint8_t *txData; /*!< Send buffer. */
<> 154:37f96f9d4de2 162 uint8_t *rxData; /*!< Receive buffer. */
<> 154:37f96f9d4de2 163 size_t dataSize; /*!< Transfer bytes. */
<> 154:37f96f9d4de2 164 uint8_t flags; /*!< FlexIO SPI control flag, MSB first or LSB first. */
<> 154:37f96f9d4de2 165 } flexio_spi_transfer_t;
<> 154:37f96f9d4de2 166
<> 154:37f96f9d4de2 167 /*! @brief typedef for flexio_spi_master_handle_t in advance. */
<> 154:37f96f9d4de2 168 typedef struct _flexio_spi_master_handle flexio_spi_master_handle_t;
<> 154:37f96f9d4de2 169
<> 154:37f96f9d4de2 170 /*! @brief Slave handle is the same with master handle. */
<> 154:37f96f9d4de2 171 typedef flexio_spi_master_handle_t flexio_spi_slave_handle_t;
<> 154:37f96f9d4de2 172
<> 154:37f96f9d4de2 173 /*! @brief FlexIO SPI master callback for finished transmit */
<> 154:37f96f9d4de2 174 typedef void (*flexio_spi_master_transfer_callback_t)(FLEXIO_SPI_Type *base,
<> 154:37f96f9d4de2 175 flexio_spi_master_handle_t *handle,
<> 154:37f96f9d4de2 176 status_t status,
<> 154:37f96f9d4de2 177 void *userData);
<> 154:37f96f9d4de2 178
<> 154:37f96f9d4de2 179 /*! @brief FlexIO SPI slave callback for finished transmit */
<> 154:37f96f9d4de2 180 typedef void (*flexio_spi_slave_transfer_callback_t)(FLEXIO_SPI_Type *base,
<> 154:37f96f9d4de2 181 flexio_spi_slave_handle_t *handle,
<> 154:37f96f9d4de2 182 status_t status,
<> 154:37f96f9d4de2 183 void *userData);
<> 154:37f96f9d4de2 184
<> 154:37f96f9d4de2 185 /*! @brief Define FlexIO SPI handle structure. */
<> 154:37f96f9d4de2 186 struct _flexio_spi_master_handle
<> 154:37f96f9d4de2 187 {
<> 154:37f96f9d4de2 188 uint8_t *txData; /*!< Transfer buffer. */
<> 154:37f96f9d4de2 189 uint8_t *rxData; /*!< Receive buffer. */
<> 154:37f96f9d4de2 190 size_t transferSize; /*!< Total bytes to be transferred. */
<> 154:37f96f9d4de2 191 volatile size_t txRemainingBytes; /*!< Send data remaining in bytes. */
<> 154:37f96f9d4de2 192 volatile size_t rxRemainingBytes; /*!< Receive data remaining in bytes. */
<> 154:37f96f9d4de2 193 volatile uint32_t state; /*!< FlexIO SPI internal state. */
<> 154:37f96f9d4de2 194 uint8_t bytePerFrame; /*!< SPI mode, 2bytes or 1byte in a frame */
<> 154:37f96f9d4de2 195 flexio_spi_shift_direction_t direction; /*!< Shift direction. */
<> 154:37f96f9d4de2 196 flexio_spi_master_transfer_callback_t callback; /*!< FlexIO SPI callback. */
<> 154:37f96f9d4de2 197 void *userData; /*!< Callback parameter. */
<> 154:37f96f9d4de2 198 };
<> 154:37f96f9d4de2 199
<> 154:37f96f9d4de2 200 /*******************************************************************************
<> 154:37f96f9d4de2 201 * API
<> 154:37f96f9d4de2 202 ******************************************************************************/
<> 154:37f96f9d4de2 203
<> 154:37f96f9d4de2 204 #if defined(__cplusplus)
<> 154:37f96f9d4de2 205 extern "C" {
<> 154:37f96f9d4de2 206 #endif /*_cplusplus*/
<> 154:37f96f9d4de2 207
<> 154:37f96f9d4de2 208 /*!
<> 154:37f96f9d4de2 209 * @name FlexIO SPI Configuration
<> 154:37f96f9d4de2 210 * @{
<> 154:37f96f9d4de2 211 */
<> 154:37f96f9d4de2 212
<> 154:37f96f9d4de2 213 /*!
<> 154:37f96f9d4de2 214 * @brief Ungates the FlexIO clock, resets the FlexIO module and configures the FlexIO SPI master hardware,
<> 154:37f96f9d4de2 215 * and configures the FlexIO SPI with FlexIO SPI master configuration. The
<> 154:37f96f9d4de2 216 * configuration structure can be filled by the user, or be set with default values
<> 154:37f96f9d4de2 217 * by the FLEXIO_SPI_MasterGetDefaultConfig().
<> 154:37f96f9d4de2 218 *
<> 154:37f96f9d4de2 219 * @note FlexIO SPI master only support CPOL = 0, which means clock inactive low.
<> 154:37f96f9d4de2 220 *
<> 154:37f96f9d4de2 221 * Example
<> 154:37f96f9d4de2 222 @code
<> 154:37f96f9d4de2 223 FLEXIO_SPI_Type spiDev = {
<> 154:37f96f9d4de2 224 .flexioBase = FLEXIO,
<> 154:37f96f9d4de2 225 .SDOPinIndex = 0,
<> 154:37f96f9d4de2 226 .SDIPinIndex = 1,
<> 154:37f96f9d4de2 227 .SCKPinIndex = 2,
<> 154:37f96f9d4de2 228 .CSnPinIndex = 3,
<> 154:37f96f9d4de2 229 .shifterIndex = {0,1},
<> 154:37f96f9d4de2 230 .timerIndex = {0,1}
<> 154:37f96f9d4de2 231 };
<> 154:37f96f9d4de2 232 flexio_spi_master_config_t config = {
<> 154:37f96f9d4de2 233 .enableMaster = true,
<> 154:37f96f9d4de2 234 .enableInDoze = false,
<> 154:37f96f9d4de2 235 .enableInDebug = true,
<> 154:37f96f9d4de2 236 .enableFastAccess = false,
<> 154:37f96f9d4de2 237 .baudRate_Bps = 500000,
<> 154:37f96f9d4de2 238 .phase = kFLEXIO_SPI_ClockPhaseFirstEdge,
<> 154:37f96f9d4de2 239 .direction = kFLEXIO_SPI_MsbFirst,
<> 154:37f96f9d4de2 240 .dataMode = kFLEXIO_SPI_8BitMode
<> 154:37f96f9d4de2 241 };
<> 154:37f96f9d4de2 242 FLEXIO_SPI_MasterInit(&spiDev, &config, srcClock_Hz);
<> 154:37f96f9d4de2 243 @endcode
<> 154:37f96f9d4de2 244 *
<> 154:37f96f9d4de2 245 * @param base Pointer to the FLEXIO_SPI_Type structure.
<> 154:37f96f9d4de2 246 * @param masterConfig Pointer to the flexio_spi_master_config_t structure.
<> 154:37f96f9d4de2 247 * @param srcClock_Hz FlexIO source clock in Hz.
<> 154:37f96f9d4de2 248 */
<> 154:37f96f9d4de2 249 void FLEXIO_SPI_MasterInit(FLEXIO_SPI_Type *base, flexio_spi_master_config_t *masterConfig, uint32_t srcClock_Hz);
<> 154:37f96f9d4de2 250
<> 154:37f96f9d4de2 251 /*!
<> 154:37f96f9d4de2 252 * @brief Gates the FlexIO clock.
<> 154:37f96f9d4de2 253 *
<> 154:37f96f9d4de2 254 * @param base Pointer to the FLEXIO_SPI_Type.
<> 154:37f96f9d4de2 255 */
<> 154:37f96f9d4de2 256 void FLEXIO_SPI_MasterDeinit(FLEXIO_SPI_Type *base);
<> 154:37f96f9d4de2 257
<> 154:37f96f9d4de2 258 /*!
<> 154:37f96f9d4de2 259 * @brief Gets the default configuration to configure the FlexIO SPI master. The configuration
<> 154:37f96f9d4de2 260 * can be used directly by calling the FLEXIO_SPI_MasterConfigure().
<> 154:37f96f9d4de2 261 * Example:
<> 154:37f96f9d4de2 262 @code
<> 154:37f96f9d4de2 263 flexio_spi_master_config_t masterConfig;
<> 154:37f96f9d4de2 264 FLEXIO_SPI_MasterGetDefaultConfig(&masterConfig);
<> 154:37f96f9d4de2 265 @endcode
<> 154:37f96f9d4de2 266 * @param masterConfig Pointer to the flexio_spi_master_config_t structure.
<> 154:37f96f9d4de2 267 */
<> 154:37f96f9d4de2 268 void FLEXIO_SPI_MasterGetDefaultConfig(flexio_spi_master_config_t *masterConfig);
<> 154:37f96f9d4de2 269
<> 154:37f96f9d4de2 270 /*!
<> 154:37f96f9d4de2 271 * @brief Ungates the FlexIO clock, resets the FlexIO module, configures the FlexIO SPI slave hardware
<> 154:37f96f9d4de2 272 * configuration, and configures the FlexIO SPI with FlexIO SPI slave configuration. The
<> 154:37f96f9d4de2 273 * configuration structure can be filled by the user, or be set with default values
<> 154:37f96f9d4de2 274 * by the FLEXIO_SPI_SlaveGetDefaultConfig().
<> 154:37f96f9d4de2 275 *
<> 154:37f96f9d4de2 276 * @note Only one timer is needed in the FlexIO SPI slave. As a result, the second timer index is ignored.
<> 154:37f96f9d4de2 277 * FlexIO SPI slave only support CPOL = 0, which means clock inactive low.
<> 154:37f96f9d4de2 278 * Example
<> 154:37f96f9d4de2 279 @code
<> 154:37f96f9d4de2 280 FLEXIO_SPI_Type spiDev = {
<> 154:37f96f9d4de2 281 .flexioBase = FLEXIO,
<> 154:37f96f9d4de2 282 .SDOPinIndex = 0,
<> 154:37f96f9d4de2 283 .SDIPinIndex = 1,
<> 154:37f96f9d4de2 284 .SCKPinIndex = 2,
<> 154:37f96f9d4de2 285 .CSnPinIndex = 3,
<> 154:37f96f9d4de2 286 .shifterIndex = {0,1},
<> 154:37f96f9d4de2 287 .timerIndex = {0}
<> 154:37f96f9d4de2 288 };
<> 154:37f96f9d4de2 289 flexio_spi_slave_config_t config = {
<> 154:37f96f9d4de2 290 .enableSlave = true,
<> 154:37f96f9d4de2 291 .enableInDoze = false,
<> 154:37f96f9d4de2 292 .enableInDebug = true,
<> 154:37f96f9d4de2 293 .enableFastAccess = false,
<> 154:37f96f9d4de2 294 .phase = kFLEXIO_SPI_ClockPhaseFirstEdge,
<> 154:37f96f9d4de2 295 .direction = kFLEXIO_SPI_MsbFirst,
<> 154:37f96f9d4de2 296 .dataMode = kFLEXIO_SPI_8BitMode
<> 154:37f96f9d4de2 297 };
<> 154:37f96f9d4de2 298 FLEXIO_SPI_SlaveInit(&spiDev, &config);
<> 154:37f96f9d4de2 299 @endcode
<> 154:37f96f9d4de2 300 * @param base Pointer to the FLEXIO_SPI_Type structure.
<> 154:37f96f9d4de2 301 * @param slaveConfig Pointer to the flexio_spi_slave_config_t structure.
<> 154:37f96f9d4de2 302 */
<> 154:37f96f9d4de2 303 void FLEXIO_SPI_SlaveInit(FLEXIO_SPI_Type *base, flexio_spi_slave_config_t *slaveConfig);
<> 154:37f96f9d4de2 304
<> 154:37f96f9d4de2 305 /*!
<> 154:37f96f9d4de2 306 * @brief Gates the FlexIO clock.
<> 154:37f96f9d4de2 307 *
<> 154:37f96f9d4de2 308 * @param base Pointer to the FLEXIO_SPI_Type.
<> 154:37f96f9d4de2 309 */
<> 154:37f96f9d4de2 310 void FLEXIO_SPI_SlaveDeinit(FLEXIO_SPI_Type *base);
<> 154:37f96f9d4de2 311
<> 154:37f96f9d4de2 312 /*!
<> 154:37f96f9d4de2 313 * @brief Gets the default configuration to configure the FlexIO SPI slave. The configuration
<> 154:37f96f9d4de2 314 * can be used directly for calling the FLEXIO_SPI_SlaveConfigure().
<> 154:37f96f9d4de2 315 * Example:
<> 154:37f96f9d4de2 316 @code
<> 154:37f96f9d4de2 317 flexio_spi_slave_config_t slaveConfig;
<> 154:37f96f9d4de2 318 FLEXIO_SPI_SlaveGetDefaultConfig(&slaveConfig);
<> 154:37f96f9d4de2 319 @endcode
<> 154:37f96f9d4de2 320 * @param slaveConfig Pointer to the flexio_spi_slave_config_t structure.
<> 154:37f96f9d4de2 321 */
<> 154:37f96f9d4de2 322 void FLEXIO_SPI_SlaveGetDefaultConfig(flexio_spi_slave_config_t *slaveConfig);
<> 154:37f96f9d4de2 323
<> 154:37f96f9d4de2 324 /*@}*/
<> 154:37f96f9d4de2 325
<> 154:37f96f9d4de2 326 /*!
<> 154:37f96f9d4de2 327 * @name Status
<> 154:37f96f9d4de2 328 * @{
<> 154:37f96f9d4de2 329 */
<> 154:37f96f9d4de2 330
<> 154:37f96f9d4de2 331 /*!
<> 154:37f96f9d4de2 332 * @brief Gets FlexIO SPI status flags.
<> 154:37f96f9d4de2 333 *
<> 154:37f96f9d4de2 334 * @param base Pointer to the FLEXIO_SPI_Type structure.
<> 154:37f96f9d4de2 335 * @return status flag; Use the status flag to AND the following flag mask and get the status.
<> 154:37f96f9d4de2 336 * @arg kFLEXIO_SPI_TxEmptyFlag
<> 154:37f96f9d4de2 337 * @arg kFLEXIO_SPI_RxEmptyFlag
<> 154:37f96f9d4de2 338 */
<> 154:37f96f9d4de2 339
<> 154:37f96f9d4de2 340 uint32_t FLEXIO_SPI_GetStatusFlags(FLEXIO_SPI_Type *base);
<> 154:37f96f9d4de2 341
<> 154:37f96f9d4de2 342 /*!
<> 154:37f96f9d4de2 343 * @brief Clears FlexIO SPI status flags.
<> 154:37f96f9d4de2 344 *
<> 154:37f96f9d4de2 345 * @param base Pointer to the FLEXIO_SPI_Type structure.
<> 154:37f96f9d4de2 346 * @param mask status flag
<> 154:37f96f9d4de2 347 * The parameter can be any combination of the following values:
<> 154:37f96f9d4de2 348 * @arg kFLEXIO_SPI_TxEmptyFlag
<> 154:37f96f9d4de2 349 * @arg kFLEXIO_SPI_RxEmptyFlag
<> 154:37f96f9d4de2 350 */
<> 154:37f96f9d4de2 351
<> 154:37f96f9d4de2 352 void FLEXIO_SPI_ClearStatusFlags(FLEXIO_SPI_Type *base, uint32_t mask);
<> 154:37f96f9d4de2 353
<> 154:37f96f9d4de2 354 /*@}*/
<> 154:37f96f9d4de2 355
<> 154:37f96f9d4de2 356 /*!
<> 154:37f96f9d4de2 357 * @name Interrupts
<> 154:37f96f9d4de2 358 * @{
<> 154:37f96f9d4de2 359 */
<> 154:37f96f9d4de2 360
<> 154:37f96f9d4de2 361 /*!
<> 154:37f96f9d4de2 362 * @brief Enables the FlexIO SPI interrupt.
<> 154:37f96f9d4de2 363 *
<> 154:37f96f9d4de2 364 * This function enables the FlexIO SPI interrupt.
<> 154:37f96f9d4de2 365 *
<> 154:37f96f9d4de2 366 * @param base Pointer to the FLEXIO_SPI_Type structure.
<> 154:37f96f9d4de2 367 * @param mask interrupt source. The parameter can be any combination of the following values:
<> 154:37f96f9d4de2 368 * @arg kFLEXIO_SPI_RxFullInterruptEnable
<> 154:37f96f9d4de2 369 * @arg kFLEXIO_SPI_TxEmptyInterruptEnable
<> 154:37f96f9d4de2 370 */
<> 154:37f96f9d4de2 371 void FLEXIO_SPI_EnableInterrupts(FLEXIO_SPI_Type *base, uint32_t mask);
<> 154:37f96f9d4de2 372
<> 154:37f96f9d4de2 373 /*!
<> 154:37f96f9d4de2 374 * @brief Disables the FlexIO SPI interrupt.
<> 154:37f96f9d4de2 375 *
<> 154:37f96f9d4de2 376 * This function disables the FlexIO SPI interrupt.
<> 154:37f96f9d4de2 377 *
<> 154:37f96f9d4de2 378 * @param base Pointer to the FLEXIO_SPI_Type structure.
<> 154:37f96f9d4de2 379 * @param mask interrupt source The parameter can be any combination of the following values:
<> 154:37f96f9d4de2 380 * @arg kFLEXIO_SPI_RxFullInterruptEnable
<> 154:37f96f9d4de2 381 * @arg kFLEXIO_SPI_TxEmptyInterruptEnable
<> 154:37f96f9d4de2 382 */
<> 154:37f96f9d4de2 383 void FLEXIO_SPI_DisableInterrupts(FLEXIO_SPI_Type *base, uint32_t mask);
<> 154:37f96f9d4de2 384
<> 154:37f96f9d4de2 385 /*@}*/
<> 154:37f96f9d4de2 386
<> 154:37f96f9d4de2 387 /*!
<> 154:37f96f9d4de2 388 * @name DMA Control
<> 154:37f96f9d4de2 389 * @{
<> 154:37f96f9d4de2 390 */
<> 154:37f96f9d4de2 391
<> 154:37f96f9d4de2 392 /*!
<> 154:37f96f9d4de2 393 * @brief Enables/disables the FlexIO SPI transmit DMA. This function enables/disables the FlexIO SPI Tx DMA,
<> 154:37f96f9d4de2 394 * which means that asserting the kFLEXIO_SPI_TxEmptyFlag does/doesn't trigger the DMA request.
<> 154:37f96f9d4de2 395 *
<> 154:37f96f9d4de2 396 * @param base Pointer to the FLEXIO_SPI_Type structure.
<> 154:37f96f9d4de2 397 * @param mask SPI DMA source.
<> 154:37f96f9d4de2 398 * @param enable True means enable DMA, false means disable DMA.
<> 154:37f96f9d4de2 399 */
<> 154:37f96f9d4de2 400 void FLEXIO_SPI_EnableDMA(FLEXIO_SPI_Type *base, uint32_t mask, bool enable);
<> 154:37f96f9d4de2 401
<> 154:37f96f9d4de2 402 /*!
<> 154:37f96f9d4de2 403 * @brief Gets the FlexIO SPI transmit data register address for MSB first transfer.
<> 154:37f96f9d4de2 404 *
<> 154:37f96f9d4de2 405 * This function returns the SPI data register address, which is mainly used by DMA/eDMA.
<> 154:37f96f9d4de2 406 *
<> 154:37f96f9d4de2 407 * @param base Pointer to the FLEXIO_SPI_Type structure.
<> 154:37f96f9d4de2 408 * @param direction Shift direction of MSB first or LSB first.
<> 154:37f96f9d4de2 409 * @return FlexIO SPI transmit data register address.
<> 154:37f96f9d4de2 410 */
<> 154:37f96f9d4de2 411 static inline uint32_t FLEXIO_SPI_GetTxDataRegisterAddress(FLEXIO_SPI_Type *base,
<> 154:37f96f9d4de2 412 flexio_spi_shift_direction_t direction)
<> 154:37f96f9d4de2 413 {
<> 154:37f96f9d4de2 414 if (direction == kFLEXIO_SPI_MsbFirst)
<> 154:37f96f9d4de2 415 {
<> 154:37f96f9d4de2 416 return FLEXIO_GetShifterBufferAddress(base->flexioBase, kFLEXIO_ShifterBufferBitSwapped,
<> 154:37f96f9d4de2 417 base->shifterIndex[0]) +
<> 154:37f96f9d4de2 418 3U;
<> 154:37f96f9d4de2 419 }
<> 154:37f96f9d4de2 420 else
<> 154:37f96f9d4de2 421 {
<> 154:37f96f9d4de2 422 return FLEXIO_GetShifterBufferAddress(base->flexioBase, kFLEXIO_ShifterBuffer, base->shifterIndex[0]);
<> 154:37f96f9d4de2 423 }
<> 154:37f96f9d4de2 424 }
<> 154:37f96f9d4de2 425
<> 154:37f96f9d4de2 426 /*!
<> 154:37f96f9d4de2 427 * @brief Gets the FlexIO SPI receive data register address for the MSB first transfer.
<> 154:37f96f9d4de2 428 *
<> 154:37f96f9d4de2 429 * This function returns the SPI data register address, which is mainly used by DMA/eDMA.
<> 154:37f96f9d4de2 430 *
<> 154:37f96f9d4de2 431 * @param base Pointer to the FLEXIO_SPI_Type structure.
<> 154:37f96f9d4de2 432 * @param direction Shift direction of MSB first or LSB first.
<> 154:37f96f9d4de2 433 * @return FlexIO SPI receive data register address.
<> 154:37f96f9d4de2 434 */
<> 154:37f96f9d4de2 435 static inline uint32_t FLEXIO_SPI_GetRxDataRegisterAddress(FLEXIO_SPI_Type *base,
<> 154:37f96f9d4de2 436 flexio_spi_shift_direction_t direction)
<> 154:37f96f9d4de2 437 {
<> 154:37f96f9d4de2 438 if (direction == kFLEXIO_SPI_MsbFirst)
<> 154:37f96f9d4de2 439 {
<> 154:37f96f9d4de2 440 return FLEXIO_GetShifterBufferAddress(base->flexioBase, kFLEXIO_ShifterBufferBitSwapped, base->shifterIndex[1]);
<> 154:37f96f9d4de2 441 }
<> 154:37f96f9d4de2 442 else
<> 154:37f96f9d4de2 443 {
<> 154:37f96f9d4de2 444 return FLEXIO_GetShifterBufferAddress(base->flexioBase, kFLEXIO_ShifterBufferByteSwapped,
<> 154:37f96f9d4de2 445 base->shifterIndex[1]);
<> 154:37f96f9d4de2 446 }
<> 154:37f96f9d4de2 447 }
<> 154:37f96f9d4de2 448
<> 154:37f96f9d4de2 449 /*@}*/
<> 154:37f96f9d4de2 450
<> 154:37f96f9d4de2 451 /*!
<> 154:37f96f9d4de2 452 * @name Bus Operations
<> 154:37f96f9d4de2 453 * @{
<> 154:37f96f9d4de2 454 */
<> 154:37f96f9d4de2 455
<> 154:37f96f9d4de2 456 /*!
<> 154:37f96f9d4de2 457 * @brief Enables/disables the FlexIO SPI module operation.
<> 154:37f96f9d4de2 458 *
<> 154:37f96f9d4de2 459 * @param base Pointer to the FLEXIO_SPI_Type.
<> 154:37f96f9d4de2 460 * @param enable True to enable, false to disable.
<> 154:37f96f9d4de2 461 */
<> 154:37f96f9d4de2 462 static inline void FLEXIO_SPI_Enable(FLEXIO_SPI_Type *base, bool enable)
<> 154:37f96f9d4de2 463 {
<> 154:37f96f9d4de2 464 if (enable)
<> 154:37f96f9d4de2 465 {
<> 154:37f96f9d4de2 466 base->flexioBase->CTRL |= FLEXIO_CTRL_FLEXEN_MASK;
<> 154:37f96f9d4de2 467 }
<> 154:37f96f9d4de2 468 else
<> 154:37f96f9d4de2 469 {
<> 154:37f96f9d4de2 470 base->flexioBase->CTRL &= ~FLEXIO_CTRL_FLEXEN_MASK;
<> 154:37f96f9d4de2 471 }
<> 154:37f96f9d4de2 472 }
<> 154:37f96f9d4de2 473
<> 154:37f96f9d4de2 474 /*!
<> 154:37f96f9d4de2 475 * @brief Sets baud rate for the FlexIO SPI transfer, which is only used for the master.
<> 154:37f96f9d4de2 476 *
<> 154:37f96f9d4de2 477 * @param base Pointer to the FLEXIO_SPI_Type structure.
<> 154:37f96f9d4de2 478 * @param baudRate_Bps Baud Rate needed in Hz.
<> 154:37f96f9d4de2 479 * @param srcClockHz SPI source clock frequency in Hz.
<> 154:37f96f9d4de2 480 */
<> 154:37f96f9d4de2 481 void FLEXIO_SPI_MasterSetBaudRate(FLEXIO_SPI_Type *base, uint32_t baudRate_Bps, uint32_t srcClockHz);
<> 154:37f96f9d4de2 482
<> 154:37f96f9d4de2 483 /*!
<> 154:37f96f9d4de2 484 * @brief Writes one byte of data, which is sent using the MSB method.
<> 154:37f96f9d4de2 485 *
<> 154:37f96f9d4de2 486 * @note This is a non-blocking API, which returns directly after the data is put into the
<> 154:37f96f9d4de2 487 * data register but the data transfer is not finished on the bus. Ensure that
<> 154:37f96f9d4de2 488 * the TxEmptyFlag is asserted before calling this API.
<> 154:37f96f9d4de2 489 *
<> 154:37f96f9d4de2 490 * @param base Pointer to the FLEXIO_SPI_Type structure.
<> 154:37f96f9d4de2 491 * @param direction Shift direction of MSB first or LSB first.
<> 154:37f96f9d4de2 492 * @param data 8 bit/16 bit data.
<> 154:37f96f9d4de2 493 */
<> 154:37f96f9d4de2 494 static inline void FLEXIO_SPI_WriteData(FLEXIO_SPI_Type *base, flexio_spi_shift_direction_t direction, uint16_t data)
<> 154:37f96f9d4de2 495 {
<> 154:37f96f9d4de2 496 if (direction == kFLEXIO_SPI_MsbFirst)
<> 154:37f96f9d4de2 497 {
<> 154:37f96f9d4de2 498 base->flexioBase->SHIFTBUFBBS[base->shifterIndex[0]] = data;
<> 154:37f96f9d4de2 499 }
<> 154:37f96f9d4de2 500 else
<> 154:37f96f9d4de2 501 {
<> 154:37f96f9d4de2 502 base->flexioBase->SHIFTBUF[base->shifterIndex[0]] = data;
<> 154:37f96f9d4de2 503 }
<> 154:37f96f9d4de2 504 }
<> 154:37f96f9d4de2 505
<> 154:37f96f9d4de2 506 /*!
<> 154:37f96f9d4de2 507 * @brief Reads 8 bit/16 bit data.
<> 154:37f96f9d4de2 508 *
<> 154:37f96f9d4de2 509 * @note This is a non-blocking API, which returns directly after the data is read from the
<> 154:37f96f9d4de2 510 * data register. Ensure that the RxFullFlag is asserted before calling this API.
<> 154:37f96f9d4de2 511 *
<> 154:37f96f9d4de2 512 * @param base Pointer to the FLEXIO_SPI_Type structure.
<> 154:37f96f9d4de2 513 * @param direction Shift direction of MSB first or LSB first.
<> 154:37f96f9d4de2 514 * @return 8 bit/16 bit data received.
<> 154:37f96f9d4de2 515 */
<> 154:37f96f9d4de2 516 static inline uint16_t FLEXIO_SPI_ReadData(FLEXIO_SPI_Type *base, flexio_spi_shift_direction_t direction)
<> 154:37f96f9d4de2 517 {
<> 154:37f96f9d4de2 518 if (direction == kFLEXIO_SPI_MsbFirst)
<> 154:37f96f9d4de2 519 {
<> 154:37f96f9d4de2 520 return base->flexioBase->SHIFTBUFBIS[base->shifterIndex[1]];
<> 154:37f96f9d4de2 521 }
<> 154:37f96f9d4de2 522 else
<> 154:37f96f9d4de2 523 {
<> 154:37f96f9d4de2 524 return base->flexioBase->SHIFTBUFBYS[base->shifterIndex[1]];
<> 154:37f96f9d4de2 525 }
<> 154:37f96f9d4de2 526 }
<> 154:37f96f9d4de2 527
<> 154:37f96f9d4de2 528 /*!
<> 154:37f96f9d4de2 529 * @brief Sends a buffer of data bytes.
<> 154:37f96f9d4de2 530 *
<> 154:37f96f9d4de2 531 * @note This function blocks using the polling method until all bytes have been sent.
<> 154:37f96f9d4de2 532 *
<> 154:37f96f9d4de2 533 * @param base Pointer to the FLEXIO_SPI_Type structure.
<> 154:37f96f9d4de2 534 * @param direction Shift direction of MSB first or LSB first.
<> 154:37f96f9d4de2 535 * @param buffer The data bytes to send.
<> 154:37f96f9d4de2 536 * @param size The number of data bytes to send.
<> 154:37f96f9d4de2 537 */
<> 154:37f96f9d4de2 538 void FLEXIO_SPI_WriteBlocking(FLEXIO_SPI_Type *base,
<> 154:37f96f9d4de2 539 flexio_spi_shift_direction_t direction,
<> 154:37f96f9d4de2 540 const uint8_t *buffer,
<> 154:37f96f9d4de2 541 size_t size);
<> 154:37f96f9d4de2 542
<> 154:37f96f9d4de2 543 /*!
<> 154:37f96f9d4de2 544 * @brief Receives a buffer of bytes.
<> 154:37f96f9d4de2 545 *
<> 154:37f96f9d4de2 546 * @note This function blocks using the polling method until all bytes have been received.
<> 154:37f96f9d4de2 547 *
<> 154:37f96f9d4de2 548 * @param base Pointer to the FLEXIO_SPI_Type structure.
<> 154:37f96f9d4de2 549 * @param direction Shift direction of MSB first or LSB first.
<> 154:37f96f9d4de2 550 * @param buffer The buffer to store the received bytes.
<> 154:37f96f9d4de2 551 * @param size The number of data bytes to be received.
<> 154:37f96f9d4de2 552 * @param direction Shift direction of MSB first or LSB first.
<> 154:37f96f9d4de2 553 */
<> 154:37f96f9d4de2 554 void FLEXIO_SPI_ReadBlocking(FLEXIO_SPI_Type *base,
<> 154:37f96f9d4de2 555 flexio_spi_shift_direction_t direction,
<> 154:37f96f9d4de2 556 uint8_t *buffer,
<> 154:37f96f9d4de2 557 size_t size);
<> 154:37f96f9d4de2 558
<> 154:37f96f9d4de2 559 /*!
<> 154:37f96f9d4de2 560 * @brief Receives a buffer of bytes.
<> 154:37f96f9d4de2 561 *
<> 154:37f96f9d4de2 562 * @note This function blocks via polling until all bytes have been received.
<> 154:37f96f9d4de2 563 *
<> 154:37f96f9d4de2 564 * @param base pointer to FLEXIO_SPI_Type structure
<> 154:37f96f9d4de2 565 * @param xfer FlexIO SPI transfer structure, see #flexio_spi_transfer_t.
<> 154:37f96f9d4de2 566 */
<> 154:37f96f9d4de2 567 void FLEXIO_SPI_MasterTransferBlocking(FLEXIO_SPI_Type *base, flexio_spi_transfer_t *xfer);
<> 154:37f96f9d4de2 568
<> 154:37f96f9d4de2 569 /*Transactional APIs*/
<> 154:37f96f9d4de2 570
<> 154:37f96f9d4de2 571 /*!
<> 154:37f96f9d4de2 572 * @name Transactional
<> 154:37f96f9d4de2 573 * @{
<> 154:37f96f9d4de2 574 */
<> 154:37f96f9d4de2 575
<> 154:37f96f9d4de2 576 /*!
<> 154:37f96f9d4de2 577 * @brief Initializes the FlexIO SPI Master handle, which is used in transactional functions.
<> 154:37f96f9d4de2 578 *
<> 154:37f96f9d4de2 579 * @param base Pointer to the FLEXIO_SPI_Type structure.
<> 154:37f96f9d4de2 580 * @param handle Pointer to the flexio_spi_master_handle_t structure to store the transfer state.
<> 154:37f96f9d4de2 581 * @param callback The callback function.
<> 154:37f96f9d4de2 582 * @param userData The parameter of the callback function.
<> 154:37f96f9d4de2 583 * @retval kStatus_Success Successfully create the handle.
<> 154:37f96f9d4de2 584 * @retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range.
<> 154:37f96f9d4de2 585 */
<> 154:37f96f9d4de2 586 status_t FLEXIO_SPI_MasterTransferCreateHandle(FLEXIO_SPI_Type *base,
<> 154:37f96f9d4de2 587 flexio_spi_master_handle_t *handle,
<> 154:37f96f9d4de2 588 flexio_spi_master_transfer_callback_t callback,
<> 154:37f96f9d4de2 589 void *userData);
<> 154:37f96f9d4de2 590
<> 154:37f96f9d4de2 591 /*!
<> 154:37f96f9d4de2 592 * @brief Master transfer data using IRQ.
<> 154:37f96f9d4de2 593 *
<> 154:37f96f9d4de2 594 * This function sends data using IRQ. This is a non-blocking function, which returns
<> 154:37f96f9d4de2 595 * right away. When all data is sent out/received, the callback function is called.
<> 154:37f96f9d4de2 596 *
<> 154:37f96f9d4de2 597 * @param base Pointer to the FLEXIO_SPI_Type structure.
<> 154:37f96f9d4de2 598 * @param handle Pointer to the flexio_spi_master_handle_t structure to store the transfer state.
<> 154:37f96f9d4de2 599 * @param xfer FlexIO SPI transfer structure. See #flexio_spi_transfer_t.
<> 154:37f96f9d4de2 600 * @retval kStatus_Success Successfully start a transfer.
<> 154:37f96f9d4de2 601 * @retval kStatus_InvalidArgument Input argument is invalid.
<> 154:37f96f9d4de2 602 * @retval kStatus_FLEXIO_SPI_Busy SPI is not idle, is running another transfer.
<> 154:37f96f9d4de2 603 */
<> 154:37f96f9d4de2 604 status_t FLEXIO_SPI_MasterTransferNonBlocking(FLEXIO_SPI_Type *base,
<> 154:37f96f9d4de2 605 flexio_spi_master_handle_t *handle,
<> 154:37f96f9d4de2 606 flexio_spi_transfer_t *xfer);
<> 154:37f96f9d4de2 607
<> 154:37f96f9d4de2 608 /*!
<> 154:37f96f9d4de2 609 * @brief Aborts the master data transfer, which used IRQ.
<> 154:37f96f9d4de2 610 *
<> 154:37f96f9d4de2 611 * @param base Pointer to the FLEXIO_SPI_Type structure.
<> 154:37f96f9d4de2 612 * @param handle Pointer to the flexio_spi_master_handle_t structure to store the transfer state.
<> 154:37f96f9d4de2 613 */
<> 154:37f96f9d4de2 614 void FLEXIO_SPI_MasterTransferAbort(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle);
<> 154:37f96f9d4de2 615
<> 154:37f96f9d4de2 616 /*!
<> 154:37f96f9d4de2 617 * @brief Gets the data transfer status which used IRQ.
<> 154:37f96f9d4de2 618 *
<> 154:37f96f9d4de2 619 * @param base Pointer to the FLEXIO_SPI_Type structure.
<> 154:37f96f9d4de2 620 * @param handle Pointer to the flexio_spi_master_handle_t structure to store the transfer state.
<> 154:37f96f9d4de2 621 * @param count Number of bytes transferred so far by the non-blocking transaction.
<> 154:37f96f9d4de2 622 * @retval kStatus_InvalidArgument count is Invalid.
<> 154:37f96f9d4de2 623 * @retval kStatus_Success Successfully return the count.
<> 154:37f96f9d4de2 624 */
<> 154:37f96f9d4de2 625 status_t FLEXIO_SPI_MasterTransferGetCount(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle, size_t *count);
<> 154:37f96f9d4de2 626
<> 154:37f96f9d4de2 627 /*!
<> 154:37f96f9d4de2 628 * @brief FlexIO SPI master IRQ handler function.
<> 154:37f96f9d4de2 629 *
<> 154:37f96f9d4de2 630 * @param spiType Pointer to the FLEXIO_SPI_Type structure.
<> 154:37f96f9d4de2 631 * @param spiHandle Pointer to the flexio_spi_master_handle_t structure to store the transfer state.
<> 154:37f96f9d4de2 632 */
<> 154:37f96f9d4de2 633 void FLEXIO_SPI_MasterTransferHandleIRQ(void *spiType, void *spiHandle);
<> 154:37f96f9d4de2 634
<> 154:37f96f9d4de2 635 /*!
<> 154:37f96f9d4de2 636 * @brief Initializes the FlexIO SPI Slave handle, which is used in transactional functions.
<> 154:37f96f9d4de2 637 *
<> 154:37f96f9d4de2 638 * @param base Pointer to the FLEXIO_SPI_Type structure.
<> 154:37f96f9d4de2 639 * @param handle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state.
<> 154:37f96f9d4de2 640 * @param callback The callback function.
<> 154:37f96f9d4de2 641 * @param userData The parameter of the callback function.
<> 154:37f96f9d4de2 642 * @retval kStatus_Success Successfully create the handle.
<> 154:37f96f9d4de2 643 * @retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range.
<> 154:37f96f9d4de2 644 */
<> 154:37f96f9d4de2 645 status_t FLEXIO_SPI_SlaveTransferCreateHandle(FLEXIO_SPI_Type *base,
<> 154:37f96f9d4de2 646 flexio_spi_slave_handle_t *handle,
<> 154:37f96f9d4de2 647 flexio_spi_slave_transfer_callback_t callback,
<> 154:37f96f9d4de2 648 void *userData);
<> 154:37f96f9d4de2 649
<> 154:37f96f9d4de2 650 /*!
<> 154:37f96f9d4de2 651 * @brief Slave transfer data using IRQ.
<> 154:37f96f9d4de2 652 *
<> 154:37f96f9d4de2 653 * This function sends data using IRQ. This is a non-blocking function, which returns
<> 154:37f96f9d4de2 654 * right away. When all data is sent out/received, the callback function is called.
<> 154:37f96f9d4de2 655 * @param handle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state.
<> 154:37f96f9d4de2 656 *
<> 154:37f96f9d4de2 657 * @param base Pointer to the FLEXIO_SPI_Type structure.
<> 154:37f96f9d4de2 658 * @param xfer FlexIO SPI transfer structure. See #flexio_spi_transfer_t.
<> 154:37f96f9d4de2 659 * @retval kStatus_Success Successfully start a transfer.
<> 154:37f96f9d4de2 660 * @retval kStatus_InvalidArgument Input argument is invalid.
<> 154:37f96f9d4de2 661 * @retval kStatus_FLEXIO_SPI_Busy SPI is not idle; it is running another transfer.
<> 154:37f96f9d4de2 662 */
<> 154:37f96f9d4de2 663 status_t FLEXIO_SPI_SlaveTransferNonBlocking(FLEXIO_SPI_Type *base,
<> 154:37f96f9d4de2 664 flexio_spi_slave_handle_t *handle,
<> 154:37f96f9d4de2 665 flexio_spi_transfer_t *xfer);
<> 154:37f96f9d4de2 666
<> 154:37f96f9d4de2 667 /*!
<> 154:37f96f9d4de2 668 * @brief Aborts the slave data transfer which used IRQ, share same API with master.
<> 154:37f96f9d4de2 669 *
<> 154:37f96f9d4de2 670 * @param base Pointer to the FLEXIO_SPI_Type structure.
<> 154:37f96f9d4de2 671 * @param handle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state.
<> 154:37f96f9d4de2 672 */
<> 154:37f96f9d4de2 673 static inline void FLEXIO_SPI_SlaveTransferAbort(FLEXIO_SPI_Type *base, flexio_spi_slave_handle_t *handle)
<> 154:37f96f9d4de2 674 {
<> 154:37f96f9d4de2 675 FLEXIO_SPI_MasterTransferAbort(base, handle);
<> 154:37f96f9d4de2 676 }
<> 154:37f96f9d4de2 677 /*!
<> 154:37f96f9d4de2 678 * @brief Gets the data transfer status which used IRQ, share same API with master.
<> 154:37f96f9d4de2 679 *
<> 154:37f96f9d4de2 680 * @param base Pointer to the FLEXIO_SPI_Type structure.
<> 154:37f96f9d4de2 681 * @param handle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state.
<> 154:37f96f9d4de2 682 * @param count Number of bytes transferred so far by the non-blocking transaction.
<> 154:37f96f9d4de2 683 * @retval kStatus_InvalidArgument count is Invalid.
<> 154:37f96f9d4de2 684 * @retval kStatus_Success Successfully return the count.
<> 154:37f96f9d4de2 685 */
<> 154:37f96f9d4de2 686 static inline status_t FLEXIO_SPI_SlaveTransferGetCount(FLEXIO_SPI_Type *base,
<> 154:37f96f9d4de2 687 flexio_spi_slave_handle_t *handle,
<> 154:37f96f9d4de2 688 size_t *count)
<> 154:37f96f9d4de2 689 {
<> 154:37f96f9d4de2 690 return FLEXIO_SPI_MasterTransferGetCount(base, handle, count);
<> 154:37f96f9d4de2 691 }
<> 154:37f96f9d4de2 692
<> 154:37f96f9d4de2 693 /*!
<> 154:37f96f9d4de2 694 * @brief FlexIO SPI slave IRQ handler function.
<> 154:37f96f9d4de2 695 *
<> 154:37f96f9d4de2 696 * @param spiType Pointer to the FLEXIO_SPI_Type structure.
<> 154:37f96f9d4de2 697 * @param spiHandle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state.
<> 154:37f96f9d4de2 698 */
<> 154:37f96f9d4de2 699 void FLEXIO_SPI_SlaveTransferHandleIRQ(void *spiType, void *spiHandle);
<> 154:37f96f9d4de2 700
<> 154:37f96f9d4de2 701 /*@}*/
<> 154:37f96f9d4de2 702
<> 154:37f96f9d4de2 703 #if defined(__cplusplus)
<> 154:37f96f9d4de2 704 }
<> 154:37f96f9d4de2 705 #endif /*_cplusplus*/
<> 154:37f96f9d4de2 706 /*@}*/
<> 154:37f96f9d4de2 707
<> 154:37f96f9d4de2 708 #endif /*_FSL_FLEXIO_SPI_H_*/