Diff: arch/ext/W5500.cpp

Revision:

8:4c02de1dbf3a

Parent:

4:4930f81bbe98

Child:

10:0d17643de5fd

diff -r da6fcec0f3fe -r 4c02de1dbf3a arch/ext/W5500.cpp
--- a/arch/ext/W5500.cpp	Mon Jun 15 23:43:56 2015 +0000
+++ b/arch/ext/W5500.cpp	Tue Jun 16 11:11:11 2015 +0900
@@ -16,7 +16,7 @@
  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  */
 #include "eth_arch.h"
-#ifdef USE_W5500
+#if not defined(TARGET_WIZwiki_W7500)
 
 #include "mbed.h"
 #include "mbed_debug.h"
@@ -82,15 +82,6 @@
     return true;
 }
 
-bool WIZnet_Chip::linkstatus()
-{
-    if ( (reg_rd<uint8_t>(PHYCFGR) & 0x01) != 0x01 )
-        return false;
-
-    return true;
-}
-
-
 bool WIZnet_Chip::setProtocol(int socket, Protocol p)
 {
     if (socket < 0) {
@@ -336,6 +327,40 @@
     return port;
 }
 
+bool WIZnet_Chip::link(int wait_time_ms)
+{
+	Timer t;
+	t.reset();
+	t.start();
+	while(1) {
+		int is_link = ethernet_link();
+		printf("is_link:%d\r\n", is_link);
+		if (is_link) {
+			return true;
+		}
+		if (wait_time_ms != (-1) && t.read_ms() > wait_time_ms) {
+			break;
+		}
+	}
+	return 0;
+}
+
+void WIZnet_Chip::set_link(PHYMode phymode)
+{
+	int speed = -1;
+	int duplex = 0;
+
+	switch(phymode) {
+		case AutoNegotiate : speed = -1; duplex = 0; break;
+		case HalfDuplex10  : speed = 0;  duplex = 0; break;
+		case FullDuplex10  : speed = 0;  duplex = 1; break;
+		case HalfDuplex100 : speed = 1;  duplex = 0; break;
+		case FullDuplex100 : speed = 1;  duplex = 1; break;
+	}
+
+	ethernet_set_link(speed, duplex);
+}
+
 void WIZnet_Chip::scmd(int socket, Command cmd)
 {
     sreg<uint8_t>(socket, Sn_CR, cmd);
@@ -446,5 +471,22 @@
     debug("\n");
 }
 
+int ethernet_link(void) {
+    return (reg_rd<uint8_t>(PHYCFGR) & 0x01);
+}
+
+void ethernet_set_link(int speed, int duplex) {
+	uint32_t val=0;
+	if((speed < 0) || (speed > 1)) {
+		val = (PHYCFGR_OPMDC_ALL)<<3; 
+	} else {
+		val = (((speed&0x01)<<1)+ (duplex&0x01))<<3; 
+	}
+    reg_wr<uint32_t>(PHYCFGR, PHYCFGR_RST&(PHYCFGR_OPMD|val));
+    wait(0.2);
+	reg_wr<uint32_t>(PHYCFGR, (~PHYCFGR_RST)|(PHYCFGR_OPMD|val));
+    wait(0.2);
+}
+
 #endif