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targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_adc.c@156:95d6b41a828b, 2017-01-16 (annotated)

Committer:
<>
Date:
Mon Jan 16 15:03:32 2017 +0000
Revision:
156:95d6b41a828b
Child:
181:96ed750bd169
This updates the lib to the mbed lib v134

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 156:95d6b41a828b 1 /**
<> 156:95d6b41a828b 2 ******************************************************************************
<> 156:95d6b41a828b 3 * @file stm32f0xx_ll_adc.c
<> 156:95d6b41a828b 4 * @author MCD Application Team
<> 156:95d6b41a828b 5 * @version V1.4.0
<> 156:95d6b41a828b 6 * @date 27-May-2016
<> 156:95d6b41a828b 7 * @brief ADC LL module driver
<> 156:95d6b41a828b 8 ******************************************************************************
<> 156:95d6b41a828b 9 * @attention
<> 156:95d6b41a828b 10 *
<> 156:95d6b41a828b 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 156:95d6b41a828b 12 *
<> 156:95d6b41a828b 13 * Redistribution and use in source and binary forms, with or without modification,
<> 156:95d6b41a828b 14 * are permitted provided that the following conditions are met:
<> 156:95d6b41a828b 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 156:95d6b41a828b 16 * this list of conditions and the following disclaimer.
<> 156:95d6b41a828b 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 156:95d6b41a828b 18 * this list of conditions and the following disclaimer in the documentation
<> 156:95d6b41a828b 19 * and/or other materials provided with the distribution.
<> 156:95d6b41a828b 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 156:95d6b41a828b 21 * may be used to endorse or promote products derived from this software
<> 156:95d6b41a828b 22 * without specific prior written permission.
<> 156:95d6b41a828b 23 *
<> 156:95d6b41a828b 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 156:95d6b41a828b 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 156:95d6b41a828b 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 156:95d6b41a828b 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 156:95d6b41a828b 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 156:95d6b41a828b 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 156:95d6b41a828b 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 156:95d6b41a828b 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 156:95d6b41a828b 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 156:95d6b41a828b 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 156:95d6b41a828b 34 *
<> 156:95d6b41a828b 35 ******************************************************************************
<> 156:95d6b41a828b 36 */
<> 156:95d6b41a828b 37 #if defined(USE_FULL_LL_DRIVER)
<> 156:95d6b41a828b 38
<> 156:95d6b41a828b 39 /* Includes ------------------------------------------------------------------*/
<> 156:95d6b41a828b 40 #include "stm32f0xx_ll_adc.h"
<> 156:95d6b41a828b 41 #include "stm32f0xx_ll_bus.h"
<> 156:95d6b41a828b 42
<> 156:95d6b41a828b 43 #ifdef USE_FULL_ASSERT
<> 156:95d6b41a828b 44 #include "stm32_assert.h"
<> 156:95d6b41a828b 45 #else
<> 156:95d6b41a828b 46 #define assert_param(expr) ((void)0U)
<> 156:95d6b41a828b 47 #endif
<> 156:95d6b41a828b 48
<> 156:95d6b41a828b 49 /** @addtogroup STM32F0xx_LL_Driver
<> 156:95d6b41a828b 50 * @{
<> 156:95d6b41a828b 51 */
<> 156:95d6b41a828b 52
<> 156:95d6b41a828b 53 #if defined (ADC1)
<> 156:95d6b41a828b 54
<> 156:95d6b41a828b 55 /** @addtogroup ADC_LL ADC
<> 156:95d6b41a828b 56 * @{
<> 156:95d6b41a828b 57 */
<> 156:95d6b41a828b 58
<> 156:95d6b41a828b 59 /* Private types -------------------------------------------------------------*/
<> 156:95d6b41a828b 60 /* Private variables ---------------------------------------------------------*/
<> 156:95d6b41a828b 61 /* Private constants ---------------------------------------------------------*/
<> 156:95d6b41a828b 62 /** @addtogroup ADC_LL_Private_Constants
<> 156:95d6b41a828b 63 * @{
<> 156:95d6b41a828b 64 */
<> 156:95d6b41a828b 65
<> 156:95d6b41a828b 66 /* Definitions of ADC hardware constraints delays */
<> 156:95d6b41a828b 67 /* Note: Only ADC IP HW delays are defined in ADC LL driver driver, */
<> 156:95d6b41a828b 68 /* not timeout values: */
<> 156:95d6b41a828b 69 /* Timeout values for ADC operations are dependent to device clock */
<> 156:95d6b41a828b 70 /* configuration (system clock versus ADC clock), */
<> 156:95d6b41a828b 71 /* and therefore must be defined in user application. */
<> 156:95d6b41a828b 72 /* Refer to @ref ADC_LL_EC_HW_DELAYS for description of ADC timeout */
<> 156:95d6b41a828b 73 /* values definition. */
<> 156:95d6b41a828b 74 /* Note: ADC timeout values are defined here in CPU cycles to be independent */
<> 156:95d6b41a828b 75 /* of device clock setting. */
<> 156:95d6b41a828b 76 /* In user application, ADC timeout values should be defined with */
<> 156:95d6b41a828b 77 /* temporal values, in function of device clock settings. */
<> 156:95d6b41a828b 78 /* Highest ratio CPU clock frequency vs ADC clock frequency: */
<> 156:95d6b41a828b 79 /* - ADC clock from synchronous clock with AHB prescaler 512, */
<> 156:95d6b41a828b 80 /* APB prescaler 16, ADC prescaler 4. */
<> 156:95d6b41a828b 81 /* - ADC clock from asynchronous clock (HSI) with prescaler 1, */
<> 156:95d6b41a828b 82 /* with highest ratio CPU clock frequency vs HSI clock frequency: */
<> 156:95d6b41a828b 83 /* CPU clock frequency max 48MHz, HSI frequency 14MHz: ratio 4. */
<> 156:95d6b41a828b 84 /* Unit: CPU cycles. */
<> 156:95d6b41a828b 85 #define ADC_CLOCK_RATIO_VS_CPU_HIGHEST ((uint32_t) 512U * 16U * 4U)
<> 156:95d6b41a828b 86 #define ADC_TIMEOUT_DISABLE_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1U)
<> 156:95d6b41a828b 87 #define ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1U)
<> 156:95d6b41a828b 88
<> 156:95d6b41a828b 89 /**
<> 156:95d6b41a828b 90 * @}
<> 156:95d6b41a828b 91 */
<> 156:95d6b41a828b 92
<> 156:95d6b41a828b 93 /* Private macros ------------------------------------------------------------*/
<> 156:95d6b41a828b 94
<> 156:95d6b41a828b 95 /** @addtogroup ADC_LL_Private_Macros
<> 156:95d6b41a828b 96 * @{
<> 156:95d6b41a828b 97 */
<> 156:95d6b41a828b 98
<> 156:95d6b41a828b 99 /* Check of parameters for configuration of ADC hierarchical scope: */
<> 156:95d6b41a828b 100 /* common to several ADC instances. */
<> 156:95d6b41a828b 101 /* Check of parameters for configuration of ADC hierarchical scope: */
<> 156:95d6b41a828b 102 /* ADC instance. */
<> 156:95d6b41a828b 103 #define IS_LL_ADC_CLOCK(__CLOCK__) \
<> 156:95d6b41a828b 104 ( ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \
<> 156:95d6b41a828b 105 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \
<> 156:95d6b41a828b 106 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC) \
<> 156:95d6b41a828b 107 )
<> 156:95d6b41a828b 108
<> 156:95d6b41a828b 109 #define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \
<> 156:95d6b41a828b 110 ( ((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \
<> 156:95d6b41a828b 111 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \
<> 156:95d6b41a828b 112 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \
<> 156:95d6b41a828b 113 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B) \
<> 156:95d6b41a828b 114 )
<> 156:95d6b41a828b 115
<> 156:95d6b41a828b 116 #define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \
<> 156:95d6b41a828b 117 ( ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \
<> 156:95d6b41a828b 118 || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \
<> 156:95d6b41a828b 119 )
<> 156:95d6b41a828b 120
<> 156:95d6b41a828b 121 #define IS_LL_ADC_LOW_POWER(__LOW_POWER__) \
<> 156:95d6b41a828b 122 ( ((__LOW_POWER__) == LL_ADC_LP_MODE_NONE) \
<> 156:95d6b41a828b 123 || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT) \
<> 156:95d6b41a828b 124 || ((__LOW_POWER__) == LL_ADC_LP_AUTOPOWEROFF) \
<> 156:95d6b41a828b 125 || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF) \
<> 156:95d6b41a828b 126 )
<> 156:95d6b41a828b 127
<> 156:95d6b41a828b 128 /* Check of parameters for configuration of ADC hierarchical scope: */
<> 156:95d6b41a828b 129 /* ADC group regular */
<> 156:95d6b41a828b 130 #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
<> 156:95d6b41a828b 131 ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
<> 156:95d6b41a828b 132 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
<> 156:95d6b41a828b 133 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH4) \
<> 156:95d6b41a828b 134 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \
<> 156:95d6b41a828b 135 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
<> 156:95d6b41a828b 136 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \
<> 156:95d6b41a828b 137 )
<> 156:95d6b41a828b 138
<> 156:95d6b41a828b 139 #define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \
<> 156:95d6b41a828b 140 ( ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \
<> 156:95d6b41a828b 141 || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \
<> 156:95d6b41a828b 142 )
<> 156:95d6b41a828b 143
<> 156:95d6b41a828b 144 #define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \
<> 156:95d6b41a828b 145 ( ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \
<> 156:95d6b41a828b 146 || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \
<> 156:95d6b41a828b 147 || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \
<> 156:95d6b41a828b 148 )
<> 156:95d6b41a828b 149
<> 156:95d6b41a828b 150 #define IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__) \
<> 156:95d6b41a828b 151 ( ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED) \
<> 156:95d6b41a828b 152 || ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_OVERWRITTEN) \
<> 156:95d6b41a828b 153 )
<> 156:95d6b41a828b 154
<> 156:95d6b41a828b 155 #define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \
<> 156:95d6b41a828b 156 ( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \
<> 156:95d6b41a828b 157 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \
<> 156:95d6b41a828b 158 )
<> 156:95d6b41a828b 159
<> 156:95d6b41a828b 160 /**
<> 156:95d6b41a828b 161 * @}
<> 156:95d6b41a828b 162 */
<> 156:95d6b41a828b 163
<> 156:95d6b41a828b 164
<> 156:95d6b41a828b 165 /* Private function prototypes -----------------------------------------------*/
<> 156:95d6b41a828b 166
<> 156:95d6b41a828b 167 /* Exported functions --------------------------------------------------------*/
<> 156:95d6b41a828b 168 /** @addtogroup ADC_LL_Exported_Functions
<> 156:95d6b41a828b 169 * @{
<> 156:95d6b41a828b 170 */
<> 156:95d6b41a828b 171
<> 156:95d6b41a828b 172 /** @addtogroup ADC_LL_EF_Init
<> 156:95d6b41a828b 173 * @{
<> 156:95d6b41a828b 174 */
<> 156:95d6b41a828b 175
<> 156:95d6b41a828b 176 /**
<> 156:95d6b41a828b 177 * @brief De-initialize registers of all ADC instances belonging to
<> 156:95d6b41a828b 178 * the same ADC common instance to their default reset values.
<> 156:95d6b41a828b 179 * @note This function is performing a hard reset, using high level
<> 156:95d6b41a828b 180 * clock source RCC ADC reset.
<> 156:95d6b41a828b 181 * @param ADCxy_COMMON ADC common instance
<> 156:95d6b41a828b 182 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<> 156:95d6b41a828b 183 * @retval An ErrorStatus enumeration value:
<> 156:95d6b41a828b 184 * - SUCCESS: ADC common registers are de-initialized
<> 156:95d6b41a828b 185 * - ERROR: not applicable
<> 156:95d6b41a828b 186 */
<> 156:95d6b41a828b 187 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON)
<> 156:95d6b41a828b 188 {
<> 156:95d6b41a828b 189 /* Check the parameters */
<> 156:95d6b41a828b 190 assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
<> 156:95d6b41a828b 191
<> 156:95d6b41a828b 192 /* Force reset of ADC clock (core clock) */
<> 156:95d6b41a828b 193 LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_ADC1);
<> 156:95d6b41a828b 194
<> 156:95d6b41a828b 195 /* Release reset of ADC clock (core clock) */
<> 156:95d6b41a828b 196 LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_ADC1);
<> 156:95d6b41a828b 197
<> 156:95d6b41a828b 198 return SUCCESS;
<> 156:95d6b41a828b 199 }
<> 156:95d6b41a828b 200
<> 156:95d6b41a828b 201
<> 156:95d6b41a828b 202 /**
<> 156:95d6b41a828b 203 * @brief De-initialize registers of the selected ADC instance
<> 156:95d6b41a828b 204 * to their default reset values.
<> 156:95d6b41a828b 205 * @note To reset all ADC instances quickly (perform a hard reset),
<> 156:95d6b41a828b 206 * use function @ref LL_ADC_CommonDeInit().
<> 156:95d6b41a828b 207 * @note If this functions returns error status, it means that ADC instance
<> 156:95d6b41a828b 208 * is in an unknown state.
<> 156:95d6b41a828b 209 * In this case, perform a hard reset using high level
<> 156:95d6b41a828b 210 * clock source RCC ADC reset.
<> 156:95d6b41a828b 211 * Refer to function @ref LL_ADC_CommonDeInit().
<> 156:95d6b41a828b 212 * @param ADCx ADC instance
<> 156:95d6b41a828b 213 * @retval An ErrorStatus enumeration value:
<> 156:95d6b41a828b 214 * - SUCCESS: ADC registers are de-initialized
<> 156:95d6b41a828b 215 * - ERROR: ADC registers are not de-initialized
<> 156:95d6b41a828b 216 */
<> 156:95d6b41a828b 217 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
<> 156:95d6b41a828b 218 {
<> 156:95d6b41a828b 219 ErrorStatus status = SUCCESS;
<> 156:95d6b41a828b 220
<> 156:95d6b41a828b 221 __IO uint32_t timeout_cpu_cycles = 0U;
<> 156:95d6b41a828b 222
<> 156:95d6b41a828b 223 /* Check the parameters */
<> 156:95d6b41a828b 224 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
<> 156:95d6b41a828b 225
<> 156:95d6b41a828b 226 /* Disable ADC instance if not already disabled. */
<> 156:95d6b41a828b 227 if(LL_ADC_IsEnabled(ADCx) == 1U)
<> 156:95d6b41a828b 228 {
<> 156:95d6b41a828b 229 /* Set ADC group regular trigger source to SW start to ensure to not */
<> 156:95d6b41a828b 230 /* have an external trigger event occurring during the conversion stop */
<> 156:95d6b41a828b 231 /* ADC disable process. */
<> 156:95d6b41a828b 232 LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE);
<> 156:95d6b41a828b 233
<> 156:95d6b41a828b 234 /* Stop potential ADC conversion on going on ADC group regular. */
<> 156:95d6b41a828b 235 if(LL_ADC_REG_IsConversionOngoing(ADCx) != 0U)
<> 156:95d6b41a828b 236 {
<> 156:95d6b41a828b 237 if(LL_ADC_REG_IsStopConversionOngoing(ADCx) == 0U)
<> 156:95d6b41a828b 238 {
<> 156:95d6b41a828b 239 LL_ADC_REG_StopConversion(ADCx);
<> 156:95d6b41a828b 240 }
<> 156:95d6b41a828b 241 }
<> 156:95d6b41a828b 242
<> 156:95d6b41a828b 243 /* Wait for ADC conversions are effectively stopped */
<> 156:95d6b41a828b 244 timeout_cpu_cycles = ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES;
<> 156:95d6b41a828b 245 while (LL_ADC_REG_IsStopConversionOngoing(ADCx) == 1U)
<> 156:95d6b41a828b 246 {
<> 156:95d6b41a828b 247 if(timeout_cpu_cycles-- == 0U)
<> 156:95d6b41a828b 248 {
<> 156:95d6b41a828b 249 /* Time-out error */
<> 156:95d6b41a828b 250 status = ERROR;
<> 156:95d6b41a828b 251 }
<> 156:95d6b41a828b 252 }
<> 156:95d6b41a828b 253
<> 156:95d6b41a828b 254 /* Disable the ADC instance */
<> 156:95d6b41a828b 255 LL_ADC_Disable(ADCx);
<> 156:95d6b41a828b 256
<> 156:95d6b41a828b 257 /* Wait for ADC instance is effectively disabled */
<> 156:95d6b41a828b 258 timeout_cpu_cycles = ADC_TIMEOUT_DISABLE_CPU_CYCLES;
<> 156:95d6b41a828b 259 while (LL_ADC_IsDisableOngoing(ADCx) == 1U)
<> 156:95d6b41a828b 260 {
<> 156:95d6b41a828b 261 if(timeout_cpu_cycles-- == 0U)
<> 156:95d6b41a828b 262 {
<> 156:95d6b41a828b 263 /* Time-out error */
<> 156:95d6b41a828b 264 status = ERROR;
<> 156:95d6b41a828b 265 }
<> 156:95d6b41a828b 266 }
<> 156:95d6b41a828b 267 }
<> 156:95d6b41a828b 268
<> 156:95d6b41a828b 269 /* Check whether ADC state is compliant with expected state */
<> 156:95d6b41a828b 270 if(READ_BIT(ADCx->CR,
<> 156:95d6b41a828b 271 ( ADC_CR_ADSTP | ADC_CR_ADSTART
<> 156:95d6b41a828b 272 | ADC_CR_ADDIS | ADC_CR_ADEN )
<> 156:95d6b41a828b 273 )
<> 156:95d6b41a828b 274 == 0U)
<> 156:95d6b41a828b 275 {
<> 156:95d6b41a828b 276 /* ========== Reset ADC registers ========== */
<> 156:95d6b41a828b 277 /* Reset register IER */
<> 156:95d6b41a828b 278 CLEAR_BIT(ADCx->IER,
<> 156:95d6b41a828b 279 ( LL_ADC_IT_ADRDY
<> 156:95d6b41a828b 280 | LL_ADC_IT_EOC
<> 156:95d6b41a828b 281 | LL_ADC_IT_EOS
<> 156:95d6b41a828b 282 | LL_ADC_IT_OVR
<> 156:95d6b41a828b 283 | LL_ADC_IT_EOSMP
<> 156:95d6b41a828b 284 | LL_ADC_IT_AWD1 )
<> 156:95d6b41a828b 285 );
<> 156:95d6b41a828b 286
<> 156:95d6b41a828b 287 /* Reset register ISR */
<> 156:95d6b41a828b 288 SET_BIT(ADCx->ISR,
<> 156:95d6b41a828b 289 ( LL_ADC_FLAG_ADRDY
<> 156:95d6b41a828b 290 | LL_ADC_FLAG_EOC
<> 156:95d6b41a828b 291 | LL_ADC_FLAG_EOS
<> 156:95d6b41a828b 292 | LL_ADC_FLAG_OVR
<> 156:95d6b41a828b 293 | LL_ADC_FLAG_EOSMP
<> 156:95d6b41a828b 294 | LL_ADC_FLAG_AWD1 )
<> 156:95d6b41a828b 295 );
<> 156:95d6b41a828b 296
<> 156:95d6b41a828b 297 /* Reset register CR */
<> 156:95d6b41a828b 298 /* Bits ADC_CR_ADCAL, ADC_CR_ADSTP, ADC_CR_ADSTART are in access mode */
<> 156:95d6b41a828b 299 /* "read-set": no direct reset applicable. */
<> 156:95d6b41a828b 300 /* No action on register CR */
<> 156:95d6b41a828b 301
<> 156:95d6b41a828b 302 /* Reset register CFGR1 */
<> 156:95d6b41a828b 303 CLEAR_BIT(ADCx->CFGR1,
<> 156:95d6b41a828b 304 ( ADC_CFGR1_AWDCH | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL | ADC_CFGR1_DISCEN
<> 156:95d6b41a828b 305 | ADC_CFGR1_AUTOFF | ADC_CFGR1_WAIT | ADC_CFGR1_CONT | ADC_CFGR1_OVRMOD
<> 156:95d6b41a828b 306 | ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL | ADC_CFGR1_ALIGN | ADC_CFGR1_RES
<> 156:95d6b41a828b 307 | ADC_CFGR1_SCANDIR | ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN )
<> 156:95d6b41a828b 308 );
<> 156:95d6b41a828b 309
<> 156:95d6b41a828b 310 /* Reset register CFGR2 */
<> 156:95d6b41a828b 311 /* Note: Update of ADC clock mode is conditioned to ADC state disabled: */
<> 156:95d6b41a828b 312 /* already done above. */
<> 156:95d6b41a828b 313 CLEAR_BIT(ADCx->CFGR2, ADC_CFGR2_CKMODE);
<> 156:95d6b41a828b 314
<> 156:95d6b41a828b 315 /* Reset register SMPR */
<> 156:95d6b41a828b 316 CLEAR_BIT(ADCx->SMPR, ADC_SMPR_SMP);
<> 156:95d6b41a828b 317
<> 156:95d6b41a828b 318 /* Reset register TR */
<> 156:95d6b41a828b 319 MODIFY_REG(ADCx->TR, ADC_TR_HT | ADC_TR_LT, ADC_TR_HT);
<> 156:95d6b41a828b 320
<> 156:95d6b41a828b 321 /* Reset register CHSELR */
<> 156:95d6b41a828b 322 #if defined(ADC_CCR_VBATEN)
<> 156:95d6b41a828b 323 CLEAR_BIT(ADCx->CHSELR,
<> 156:95d6b41a828b 324 ( ADC_CHSELR_CHSEL18 | ADC_CHSELR_CHSEL17 | ADC_CHSELR_CHSEL16
<> 156:95d6b41a828b 325 | ADC_CHSELR_CHSEL15 | ADC_CHSELR_CHSEL14 | ADC_CHSELR_CHSEL13 | ADC_CHSELR_CHSEL12
<> 156:95d6b41a828b 326 | ADC_CHSELR_CHSEL11 | ADC_CHSELR_CHSEL10 | ADC_CHSELR_CHSEL9 | ADC_CHSELR_CHSEL8
<> 156:95d6b41a828b 327 | ADC_CHSELR_CHSEL7 | ADC_CHSELR_CHSEL6 | ADC_CHSELR_CHSEL5 | ADC_CHSELR_CHSEL4
<> 156:95d6b41a828b 328 | ADC_CHSELR_CHSEL3 | ADC_CHSELR_CHSEL2 | ADC_CHSELR_CHSEL1 | ADC_CHSELR_CHSEL0 )
<> 156:95d6b41a828b 329 );
<> 156:95d6b41a828b 330 #else
<> 156:95d6b41a828b 331 CLEAR_BIT(ADCx->CHSELR,
<> 156:95d6b41a828b 332 ( ADC_CHSELR_CHSEL17 | ADC_CHSELR_CHSEL16
<> 156:95d6b41a828b 333 | ADC_CHSELR_CHSEL15 | ADC_CHSELR_CHSEL14 | ADC_CHSELR_CHSEL13 | ADC_CHSELR_CHSEL12
<> 156:95d6b41a828b 334 | ADC_CHSELR_CHSEL11 | ADC_CHSELR_CHSEL10 | ADC_CHSELR_CHSEL9 | ADC_CHSELR_CHSEL8
<> 156:95d6b41a828b 335 | ADC_CHSELR_CHSEL7 | ADC_CHSELR_CHSEL6 | ADC_CHSELR_CHSEL5 | ADC_CHSELR_CHSEL4
<> 156:95d6b41a828b 336 | ADC_CHSELR_CHSEL3 | ADC_CHSELR_CHSEL2 | ADC_CHSELR_CHSEL1 | ADC_CHSELR_CHSEL0 )
<> 156:95d6b41a828b 337 );
<> 156:95d6b41a828b 338 #endif
<> 156:95d6b41a828b 339
<> 156:95d6b41a828b 340 /* Reset register DR */
<> 156:95d6b41a828b 341 /* bits in access mode read only, no direct reset applicable */
<> 156:95d6b41a828b 342
<> 156:95d6b41a828b 343 }
<> 156:95d6b41a828b 344 else
<> 156:95d6b41a828b 345 {
<> 156:95d6b41a828b 346 /* ADC instance is in an unknown state */
<> 156:95d6b41a828b 347 /* Need to performing a hard reset of ADC instance, using high level */
<> 156:95d6b41a828b 348 /* clock source RCC ADC reset. */
<> 156:95d6b41a828b 349 /* Caution: On this STM32 serie, if several ADC instances are available */
<> 156:95d6b41a828b 350 /* on the selected device, RCC ADC reset will reset */
<> 156:95d6b41a828b 351 /* all ADC instances belonging to the common ADC instance. */
<> 156:95d6b41a828b 352 status = ERROR;
<> 156:95d6b41a828b 353 }
<> 156:95d6b41a828b 354
<> 156:95d6b41a828b 355 return status;
<> 156:95d6b41a828b 356 }
<> 156:95d6b41a828b 357
<> 156:95d6b41a828b 358 /**
<> 156:95d6b41a828b 359 * @brief Initialize some features of ADC instance.
<> 156:95d6b41a828b 360 * @note These parameters have an impact on ADC scope: ADC instance.
<> 156:95d6b41a828b 361 * Refer to corresponding unitary functions into
<> 156:95d6b41a828b 362 * @ref ADC_LL_EF_Configuration_ADC_Instance .
<> 156:95d6b41a828b 363 * @note The setting of these parameters by function @ref LL_ADC_Init()
<> 156:95d6b41a828b 364 * is conditioned to ADC state:
<> 156:95d6b41a828b 365 * ADC instance must be disabled.
<> 156:95d6b41a828b 366 * This condition is applied to all ADC features, for efficiency
<> 156:95d6b41a828b 367 * and compatibility over all STM32 families. However, the different
<> 156:95d6b41a828b 368 * features can be set under different ADC state conditions
<> 156:95d6b41a828b 369 * (setting possible with ADC enabled without conversion on going,
<> 156:95d6b41a828b 370 * ADC enabled with conversion on going, ...)
<> 156:95d6b41a828b 371 * Each feature can be updated afterwards with a unitary function
<> 156:95d6b41a828b 372 * and potentially with ADC in a different state than disabled,
<> 156:95d6b41a828b 373 * refer to description of each function for setting
<> 156:95d6b41a828b 374 * conditioned to ADC state.
<> 156:95d6b41a828b 375 * @note After using this function, some other features must be configured
<> 156:95d6b41a828b 376 * using LL unitary functions.
<> 156:95d6b41a828b 377 * The minimum configuration remaining to be done is:
<> 156:95d6b41a828b 378 * - Set ADC group regular sequencer:
<> 156:95d6b41a828b 379 * map channel on rank corresponding to channel number.
<> 156:95d6b41a828b 380 * Refer to function @ref LL_ADC_REG_SetSequencerChannels();
<> 156:95d6b41a828b 381 * - Set ADC channel sampling time
<> 156:95d6b41a828b 382 * Refer to function LL_ADC_SetChannelSamplingTime();
<> 156:95d6b41a828b 383 * @param ADCx ADC instance
<> 156:95d6b41a828b 384 * @param ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
<> 156:95d6b41a828b 385 * @retval An ErrorStatus enumeration value:
<> 156:95d6b41a828b 386 * - SUCCESS: ADC registers are initialized
<> 156:95d6b41a828b 387 * - ERROR: ADC registers are not initialized
<> 156:95d6b41a828b 388 */
<> 156:95d6b41a828b 389 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
<> 156:95d6b41a828b 390 {
<> 156:95d6b41a828b 391 ErrorStatus status = SUCCESS;
<> 156:95d6b41a828b 392
<> 156:95d6b41a828b 393 /* Check the parameters */
<> 156:95d6b41a828b 394 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
<> 156:95d6b41a828b 395
<> 156:95d6b41a828b 396 assert_param(IS_LL_ADC_CLOCK(ADC_InitStruct->Clock));
<> 156:95d6b41a828b 397 assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution));
<> 156:95d6b41a828b 398 assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment));
<> 156:95d6b41a828b 399 assert_param(IS_LL_ADC_LOW_POWER(ADC_InitStruct->LowPowerMode));
<> 156:95d6b41a828b 400
<> 156:95d6b41a828b 401 /* Note: Hardware constraint (refer to description of this function): */
<> 156:95d6b41a828b 402 /* ADC instance must be disabled. */
<> 156:95d6b41a828b 403 if(LL_ADC_IsEnabled(ADCx) == 0U)
<> 156:95d6b41a828b 404 {
<> 156:95d6b41a828b 405 /* Configuration of ADC hierarchical scope: */
<> 156:95d6b41a828b 406 /* - ADC instance */
<> 156:95d6b41a828b 407 /* - Set ADC data resolution */
<> 156:95d6b41a828b 408 /* - Set ADC conversion data alignment */
<> 156:95d6b41a828b 409 /* - Set ADC low power mode */
<> 156:95d6b41a828b 410 MODIFY_REG(ADCx->CFGR1,
<> 156:95d6b41a828b 411 ADC_CFGR1_RES
<> 156:95d6b41a828b 412 | ADC_CFGR1_ALIGN
<> 156:95d6b41a828b 413 | ADC_CFGR1_WAIT
<> 156:95d6b41a828b 414 | ADC_CFGR1_AUTOFF
<> 156:95d6b41a828b 415 ,
<> 156:95d6b41a828b 416 ADC_InitStruct->Resolution
<> 156:95d6b41a828b 417 | ADC_InitStruct->DataAlignment
<> 156:95d6b41a828b 418 | ADC_InitStruct->LowPowerMode
<> 156:95d6b41a828b 419 );
<> 156:95d6b41a828b 420
<> 156:95d6b41a828b 421 }
<> 156:95d6b41a828b 422 else
<> 156:95d6b41a828b 423 {
<> 156:95d6b41a828b 424 /* Initialization error: ADC instance is not disabled. */
<> 156:95d6b41a828b 425 status = ERROR;
<> 156:95d6b41a828b 426 }
<> 156:95d6b41a828b 427 return status;
<> 156:95d6b41a828b 428 }
<> 156:95d6b41a828b 429
<> 156:95d6b41a828b 430 /**
<> 156:95d6b41a828b 431 * @brief Set each @ref LL_ADC_InitTypeDef field to default value.
<> 156:95d6b41a828b 432 * @param ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure
<> 156:95d6b41a828b 433 * whose fields will be set to default values.
<> 156:95d6b41a828b 434 * @retval None
<> 156:95d6b41a828b 435 */
<> 156:95d6b41a828b 436 void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct)
<> 156:95d6b41a828b 437 {
<> 156:95d6b41a828b 438 /* Set ADC_InitStruct fields to default values */
<> 156:95d6b41a828b 439 /* Set fields of ADC instance */
<> 156:95d6b41a828b 440 ADC_InitStruct->Clock = LL_ADC_CLOCK_SYNC_PCLK_DIV2;
<> 156:95d6b41a828b 441 ADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B;
<> 156:95d6b41a828b 442 ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
<> 156:95d6b41a828b 443 ADC_InitStruct->LowPowerMode = LL_ADC_LP_MODE_NONE;
<> 156:95d6b41a828b 444
<> 156:95d6b41a828b 445 }
<> 156:95d6b41a828b 446
<> 156:95d6b41a828b 447 /**
<> 156:95d6b41a828b 448 * @brief Initialize some features of ADC group regular.
<> 156:95d6b41a828b 449 * @note These parameters have an impact on ADC scope: ADC group regular.
<> 156:95d6b41a828b 450 * Refer to corresponding unitary functions into
<> 156:95d6b41a828b 451 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
<> 156:95d6b41a828b 452 * (functions with prefix "REG").
<> 156:95d6b41a828b 453 * @note The setting of these parameters by function @ref LL_ADC_Init()
<> 156:95d6b41a828b 454 * is conditioned to ADC state:
<> 156:95d6b41a828b 455 * ADC instance must be disabled.
<> 156:95d6b41a828b 456 * This condition is applied to all ADC features, for efficiency
<> 156:95d6b41a828b 457 * and compatibility over all STM32 families. However, the different
<> 156:95d6b41a828b 458 * features can be set under different ADC state conditions
<> 156:95d6b41a828b 459 * (setting possible with ADC enabled without conversion on going,
<> 156:95d6b41a828b 460 * ADC enabled with conversion on going, ...)
<> 156:95d6b41a828b 461 * Each feature can be updated afterwards with a unitary function
<> 156:95d6b41a828b 462 * and potentially with ADC in a different state than disabled,
<> 156:95d6b41a828b 463 * refer to description of each function for setting
<> 156:95d6b41a828b 464 * conditioned to ADC state.
<> 156:95d6b41a828b 465 * @note After using this function, other features must be configured
<> 156:95d6b41a828b 466 * using LL unitary functions.
<> 156:95d6b41a828b 467 * The minimum configuration remaining to be done is:
<> 156:95d6b41a828b 468 * - Set ADC group regular sequencer:
<> 156:95d6b41a828b 469 * map channel on rank corresponding to channel number.
<> 156:95d6b41a828b 470 * Refer to function @ref LL_ADC_REG_SetSequencerChannels();
<> 156:95d6b41a828b 471 * - Set ADC channel sampling time
<> 156:95d6b41a828b 472 * Refer to function LL_ADC_SetChannelSamplingTime();
<> 156:95d6b41a828b 473 * @param ADCx ADC instance
<> 156:95d6b41a828b 474 * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
<> 156:95d6b41a828b 475 * @retval An ErrorStatus enumeration value:
<> 156:95d6b41a828b 476 * - SUCCESS: ADC registers are initialized
<> 156:95d6b41a828b 477 * - ERROR: ADC registers are not initialized
<> 156:95d6b41a828b 478 */
<> 156:95d6b41a828b 479 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
<> 156:95d6b41a828b 480 {
<> 156:95d6b41a828b 481 ErrorStatus status = SUCCESS;
<> 156:95d6b41a828b 482
<> 156:95d6b41a828b 483 /* Check the parameters */
<> 156:95d6b41a828b 484 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
<> 156:95d6b41a828b 485 assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource));
<> 156:95d6b41a828b 486 assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont));
<> 156:95d6b41a828b 487 assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode));
<> 156:95d6b41a828b 488 assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer));
<> 156:95d6b41a828b 489 assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(ADC_REG_InitStruct->Overrun));
<> 156:95d6b41a828b 490
<> 156:95d6b41a828b 491 /* Note: Hardware constraint (refer to description of this function): */
<> 156:95d6b41a828b 492 /* ADC instance must be disabled. */
<> 156:95d6b41a828b 493 if(LL_ADC_IsEnabled(ADCx) == 0U)
<> 156:95d6b41a828b 494 {
<> 156:95d6b41a828b 495 /* Configuration of ADC hierarchical scope: */
<> 156:95d6b41a828b 496 /* - ADC group regular */
<> 156:95d6b41a828b 497 /* - Set ADC group regular trigger source */
<> 156:95d6b41a828b 498 /* - Set ADC group regular sequencer discontinuous mode */
<> 156:95d6b41a828b 499 /* - Set ADC group regular continuous mode */
<> 156:95d6b41a828b 500 /* - Set ADC group regular conversion data transfer: no transfer or */
<> 156:95d6b41a828b 501 /* transfer by DMA, and DMA requests mode */
<> 156:95d6b41a828b 502 /* - Set ADC group regular overrun behavior */
<> 156:95d6b41a828b 503 /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */
<> 156:95d6b41a828b 504 /* setting of trigger source to SW start. */
<> 156:95d6b41a828b 505 MODIFY_REG(ADCx->CFGR1,
<> 156:95d6b41a828b 506 ADC_CFGR1_EXTSEL
<> 156:95d6b41a828b 507 | ADC_CFGR1_EXTEN
<> 156:95d6b41a828b 508 | ADC_CFGR1_DISCEN
<> 156:95d6b41a828b 509 | ADC_CFGR1_CONT
<> 156:95d6b41a828b 510 | ADC_CFGR1_DMAEN
<> 156:95d6b41a828b 511 | ADC_CFGR1_DMACFG
<> 156:95d6b41a828b 512 | ADC_CFGR1_OVRMOD
<> 156:95d6b41a828b 513 ,
<> 156:95d6b41a828b 514 ADC_REG_InitStruct->TriggerSource
<> 156:95d6b41a828b 515 | ADC_REG_InitStruct->SequencerDiscont
<> 156:95d6b41a828b 516 | ADC_REG_InitStruct->ContinuousMode
<> 156:95d6b41a828b 517 | ADC_REG_InitStruct->DMATransfer
<> 156:95d6b41a828b 518 | ADC_REG_InitStruct->Overrun
<> 156:95d6b41a828b 519 );
<> 156:95d6b41a828b 520
<> 156:95d6b41a828b 521 }
<> 156:95d6b41a828b 522 else
<> 156:95d6b41a828b 523 {
<> 156:95d6b41a828b 524 /* Initialization error: ADC instance is not disabled. */
<> 156:95d6b41a828b 525 status = ERROR;
<> 156:95d6b41a828b 526 }
<> 156:95d6b41a828b 527 return status;
<> 156:95d6b41a828b 528 }
<> 156:95d6b41a828b 529
<> 156:95d6b41a828b 530 /**
<> 156:95d6b41a828b 531 * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value.
<> 156:95d6b41a828b 532 * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
<> 156:95d6b41a828b 533 * whose fields will be set to default values.
<> 156:95d6b41a828b 534 * @retval None
<> 156:95d6b41a828b 535 */
<> 156:95d6b41a828b 536 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
<> 156:95d6b41a828b 537 {
<> 156:95d6b41a828b 538 /* Set ADC_REG_InitStruct fields to default values */
<> 156:95d6b41a828b 539 /* Set fields of ADC group regular */
<> 156:95d6b41a828b 540 /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */
<> 156:95d6b41a828b 541 /* setting of trigger source to SW start. */
<> 156:95d6b41a828b 542 ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE;
<> 156:95d6b41a828b 543 ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
<> 156:95d6b41a828b 544 ADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE;
<> 156:95d6b41a828b 545 ADC_REG_InitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE;
<> 156:95d6b41a828b 546 ADC_REG_InitStruct->Overrun = LL_ADC_REG_OVR_DATA_OVERWRITTEN;
<> 156:95d6b41a828b 547 }
<> 156:95d6b41a828b 548
<> 156:95d6b41a828b 549 /**
<> 156:95d6b41a828b 550 * @}
<> 156:95d6b41a828b 551 */
<> 156:95d6b41a828b 552
<> 156:95d6b41a828b 553 /**
<> 156:95d6b41a828b 554 * @}
<> 156:95d6b41a828b 555 */
<> 156:95d6b41a828b 556
<> 156:95d6b41a828b 557 /**
<> 156:95d6b41a828b 558 * @}
<> 156:95d6b41a828b 559 */
<> 156:95d6b41a828b 560
<> 156:95d6b41a828b 561 #endif /* ADC1 */
<> 156:95d6b41a828b 562
<> 156:95d6b41a828b 563 /**
<> 156:95d6b41a828b 564 * @}
<> 156:95d6b41a828b 565 */
<> 156:95d6b41a828b 566
<> 156:95d6b41a828b 567 #endif /* USE_FULL_LL_DRIVER */
<> 156:95d6b41a828b 568
<> 156:95d6b41a828b 569 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/