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targets/TARGET_NUVOTON/TARGET_M480/device/M480.h
- Committer:
- AnnaBridge
- Date:
- 2018-02-16
- Revision:
- 182:57724642e740
- Parent:
- 179:79309dc6340a
File content as of revision 182:57724642e740:
/**************************************************************************//**
* @file M480.h
* @version V1.00
* @brief M480 peripheral access layer header file.
* This file contains all the peripheral register's definitions,
* bits definitions and memory mapping for NuMicro TC8226 MCU.
*
* @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
/**
\mainpage NuMicro M480 Driver Reference Guide
*
* <b>Introduction</b>
*
* This user manual describes the usage of M480 Series MCU device driver
*
* <b>Disclaimer</b>
*
* The Software is furnished "AS IS", without warranty as to performance or results, and
* the entire risk as to performance or results is assumed by YOU. Nuvoton disclaims all
* warranties, express, implied or otherwise, with regard to the Software, its use, or
* operation, including without limitation any and all warranties of merchantability, fitness
* for a particular purpose, and non-infringement of intellectual property rights.
*
* <b>Important Notice</b>
*
* Nuvoton Products are neither intended nor warranted for usage in systems or equipment,
* any malfunction or failure of which may cause loss of human life, bodily injury or severe
* property damage. Such applications are deemed, "Insecure Usage".
*
* Insecure usage includes, but is not limited to: equipment for surgical implementation,
* atomic energy control instruments, airplane or spaceship instruments, the control or
* operation of dynamic, brake or safety systems designed for vehicular use, traffic signal
* instruments, all types of safety devices, and other applications intended to support or
* sustain life.
*
* All Insecure Usage shall be made at customer's risk, and in the event that third parties
* lay claims to Nuvoton as a result of customer's Insecure Usage, customer shall indemnify
* the damages and liabilities thus incurred by Nuvoton.
*
* Please note that all data and specifications are subject to change without notice. All the
* trademarks of products and companies mentioned in this datasheet belong to their respective
* owners.
*
* <b>Copyright Notice</b>
*
* Copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
*/
#ifndef __M480_H__
#define __M480_H__
#ifdef __cplusplus
extern "C" {
#endif
/******************************************************************************/
/* Processor and Core Peripherals */
/******************************************************************************/
/** @addtogroup M480_CMSIS M480 Device CMSIS Definitions
Configuration of the Cortex-M4 Processor and Core Peripherals
@{
*/
/**
* @details Interrupt Number Definition.
*/
typedef enum IRQn {
/****** Cortex-M4 Processor Exceptions Numbers ***************************************************/
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
MemoryManagement_IRQn = -12, /*!< 4 Memory Management Interrupt */
BusFault_IRQn = -11, /*!< 5 Bus Fault Interrupt */
UsageFault_IRQn = -10, /*!< 6 Usage Fault Interrupt */
SVCall_IRQn = -5, /*!< 11 SV Call Interrupt */
DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor Interrupt */
PendSV_IRQn = -2, /*!< 14 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 System Tick Interrupt */
/****** M480 Specific Interrupt Numbers ********************************************************/
BOD_IRQn = 0, /*!< Brown Out detection Interrupt */
IRC_IRQn = 1, /*!< Internal RC Interrupt */
PWRWU_IRQn = 2, /*!< Power Down Wake Up Interrupt */
RAMPE_IRQn = 3, /*!< SRAM parity check failed Interrupt */
CKFAIL_IRQn = 4, /*!< Clock failed Interrupt */
RTC_IRQn = 6, /*!< Real Time Clock Interrupt */
TAMPER_IRQn = 7, /*!< Tamper detection Interrupt */
WDT_IRQn = 8, /*!< Watchdog timer Interrupt */
WWDT_IRQn = 9, /*!< Window Watchdog timer Interrupt */
EINT0_IRQn = 10, /*!< External Input 0 Interrupt */
EINT1_IRQn = 11, /*!< External Input 1 Interrupt */
EINT2_IRQn = 12, /*!< External Input 2 Interrupt */
EINT3_IRQn = 13, /*!< External Input 3 Interrupt */
EINT4_IRQn = 14, /*!< External Input 4 Interrupt */
EINT5_IRQn = 15, /*!< External Input 5 Interrupt */
GPA_IRQn = 16, /*!< GPIO Port A Interrupt */
GPB_IRQn = 17, /*!< GPIO Port B Interrupt */
GPC_IRQn = 18, /*!< GPIO Port C Interrupt */
GPD_IRQn = 19, /*!< GPIO Port D Interrupt */
GPE_IRQn = 20, /*!< GPIO Port E Interrupt */
GPF_IRQn = 21, /*!< GPIO Port F Interrupt */
SPI0_IRQn = 22, /*!< SPI0 Interrupt */
SPI1_IRQn = 23, /*!< SPI1 Interrupt */
BRAKE0_IRQn = 24, /*!< BRAKE0 Interrupt */
EPWM0P0_IRQn = 25, /*!< EPWM0P0 Interrupt */
EPWM0P1_IRQn = 26, /*!< EPWM0P1 Interrupt */
EPWM0P2_IRQn = 27, /*!< EPWM0P2 Interrupt */
BRAKE1_IRQn = 28, /*!< BRAKE1 Interrupt */
EPWM1P0_IRQn = 29, /*!< EPWM1P0 Interrupt */
EPWM1P1_IRQn = 30, /*!< EPWM1P1 Interrupt */
EPWM1P2_IRQn = 31, /*!< EPWM1P2 Interrupt */
TMR0_IRQn = 32, /*!< Timer 0 Interrupt */
TMR1_IRQn = 33, /*!< Timer 1 Interrupt */
TMR2_IRQn = 34, /*!< Timer 2 Interrupt */
TMR3_IRQn = 35, /*!< Timer 3 Interrupt */
UART0_IRQn = 36, /*!< UART 0 Interrupt */
UART1_IRQn = 37, /*!< UART 1 Interrupt */
I2C0_IRQn = 38, /*!< I2C 0 Interrupt */
I2C1_IRQn = 39, /*!< I2C 1 Interrupt */
PDMA_IRQn = 40, /*!< Peripheral DMA Interrupt */
DAC_IRQn = 41, /*!< DAC Interrupt */
ADC0_IRQn = 42, /*!< ADC0 Interrupt */
ADC1_IRQn = 43, /*!< ADC1 Interrupt */
ACMP01_IRQn = 44, /*!< Analog Comparator 0 and 1 Interrupt */
ADC2_IRQn = 46, /*!< ADC2 Interrupt */
ADC3_IRQn = 47, /*!< ADC3 Interrupt */
UART2_IRQn = 48, /*!< UART2 Interrupt */
UART3_IRQn = 49, /*!< UART3 Interrupt */
SPI2_IRQn = 51, /*!< SPI2 Interrupt */
SPI3_IRQn = 52, /*!< SPI3 Interrupt */
USBD_IRQn = 53, /*!< USB device Interrupt */
USBH_IRQn = 54, /*!< USB host Interrupt */
USBOTG_IRQn = 55, /*!< USB OTG Interrupt */
CAN0_IRQn = 56, /*!< CAN0 Interrupt */
CAN1_IRQn = 57, /*!< CAN1 Interrupt */
SC0_IRQn = 58, /*!< Smart Card 0 Interrupt */
SC1_IRQn = 59, /*!< Smart Card 1 Interrupt */
SC2_IRQn = 60, /*!< Smart Card 2 Interrupt */
SPI4_IRQn = 62, /*!< SPI4 Interrupt */
EMAC_TX_IRQn = 66, /*!< Ethernet MAC TX Interrupt */
EMAC_RX_IRQn = 67, /*!< Ethernet MAC RX Interrupt */
SDH0_IRQn = 64, /*!< Secure Digital Host Controller 0 Interrupt */
USBD20_IRQn = 65, /*!< High Speed USB device Interrupt */
I2S0_IRQn = 68, /*!< I2S0 Interrupt */
OPA_IRQn = 70, /*!< OPA Interrupt */
CRPT_IRQn = 71, /*!< CRPT Interrupt */
GPG_IRQn = 72, /*!< GPIO Port G Interrupt */
EINT6_IRQn = 73, /*!< External Input 6 Interrupt */
UART4_IRQn = 74, /*!< UART4 Interrupt */
UART5_IRQn = 75, /*!< UART5 Interrupt */
USCI0_IRQn = 76, /*!< USCI0 Interrupt */
USCI1_IRQn = 77, /*!< USCI1 Interrupt */
BPWM0_IRQn = 78, /*!< BPWM0 Interrupt */
BPWM1_IRQn = 79, /*!< BPWM1 Interrupt */
SPIM_IRQn = 80, /*!< SPIM Interrupt */
I2C2_IRQn = 82, /*!< I2C2 Interrupt */
QEI0_IRQn = 84, /*!< QEI0 Interrupt */
QEI1_IRQn = 85, /*!< QEI1 Interrupt */
ECAP0_IRQn = 86, /*!< ECAP0 Interrupt */
ECAP1_IRQn = 87, /*!< ECAP1 Interrupt */
GPH_IRQn = 88, /*!< GPIO Port H Interrupt */
EINT7_IRQn = 89, /*!< External Input 7 Interrupt */
SDH1_IRQn = 90, /*!< Secure Digital Host Controller 1 Interrupt */
HSUSBH_IRQn = 92, /*!< High speed USB host Interrupt */
USBOTG20_IRQn = 93, /*!< High speed USB OTG Interrupt */
}
IRQn_Type;
/*
* ==========================================================================
* ----------- Processor and Core Peripheral Section ------------------------
* ==========================================================================
*/
/* Configuration of the Cortex-M# Processor and Core Peripherals */
#define __CM4_REV 0x0201 /*!< Core Revision r2p1 */
#define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
#define __MPU_PRESENT 1 /*!< MPU present or not */
#define __FPU_PRESENT 1 /*!< FPU present or not */
/*@}*/ /* end of group M480_CMSIS */
#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
#include "system_M480.h" /* TC8226 System include file */
#include <stdint.h>
/******************************************************************************/
/* Device Specific Peripheral registers structures */
/******************************************************************************/
/** @addtogroup M480_Peripherals M480 Control Register
M480 Device Specific Peripheral registers structures
@{
*/
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/*---------------------- System Manger Controller -------------------------*/
/**
@addtogroup SYS System Manger Controller(SYS)
Memory Mapped Structure for SYS Controller
@{ */
typedef struct {
/**
* @var SYS_T::PDID
* Offset: 0x00 Part Device Identification Number Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |PDID |Part Device Identification Number (Read Only)
* | | |This register reflects device part number code
* | | |Software can read this register to identify which device is used.
* @var SYS_T::RSTSTS
* Offset: 0x04 System Reset Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |PORF |POR Reset Flag
* | | |The POR reset flag is set by the "Reset Signal" from the Power-on Reset (POR) Controller or bit CHIPRST (SYS_IPRST0[0]) to indicate the previous reset source.
* | | |0 = No reset from POR or CHIPRST.
* | | |1 = Power-on Reset (POR) or CHIPRST had issued the reset signal to reset the system.
* | | |Note: Write 1 to clear this bit to 0.
* |[1] |PINRF |NRESET Pin Reset Flag
* | | |The nRESET pin reset flag is set by the "Reset Signal" from the nRESET Pin to indicate the previous reset source.
* | | |0 = No reset from nRESET pin.
* | | |1 = Pin nRESET had issued the reset signal to reset the system.
* | | |Note: Write 1 to clear this bit to 0.
* |[2] |WDTRF |WDT Reset Flag
* | | |The WDT reset flag is set by the "Reset Signal" from the Watchdog Timer or Window Watchdog Timer to indicate the previous reset source.
* | | |0 = No reset from watchdog timer or window watchdog timer.
* | | |1 = The watchdog timer or window watchdog timer had issued the reset signal to reset the system.
* | | |Note1: Write 1 to clear this bit to 0.
* | | |Note2: Watchdog Timer register RSTF(WDT_CTL[2]) bit is set if the system has been reset by WDT time-out reset
* | | |Window Watchdog Timer register WWDTRF(WWDT_STATUS[1]) bit is set if the system has been reset by WWDT time-out reset.
* |[3] |LVRF |LVR Reset Flag
* | | |The LVR reset flag is set by the "Reset Signal" from the Low Voltage Reset Controller to indicate the previous reset source.
* | | |0 = No reset from LVR.
* | | |1 = LVR controller had issued the reset signal to reset the system.
* | | |Note: Write 1 to clear this bit to 0.
* |[4] |BODRF |BOD Reset Flag
* | | |The BOD reset flag is set by the "Reset Signal" from the Brown-Out Detector to indicate the previous reset source.
* | | |0 = No reset from BOD.
* | | |1 = The BOD had issued the reset signal to reset the system.
* | | |Note: Write 1 to clear this bit to 0.
* |[5] |SYSRF |System Reset Flag
* | | |The system reset flag is set by the "Reset Signal" from the Cortex-M4 Core to indicate the previous reset source.
* | | |0 = No reset from Cortex-M4.
* | | |1 = The Cortex-M4 had issued the reset signal to reset the system by writing 1 to the bit SYSRESETREQ(AIRCR[2], Application Interrupt and Reset Control Register, address = 0xE000ED0C) in system control registers of Cortex-M4 core.
* | | |Note: Write 1 to clear this bit to 0.
* |[7] |CPURF |CPU Reset Flag
* | | |The CPU reset flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset Cortex-M4 Core and Flash Memory Controller (FMC).
* | | |0 = No reset from CPU.
* | | |1 = The Cortex-M4 Core and FMC are reset by software setting CPURST to 1.
* | | |Note: Write to clear this bit to 0.
* |[8] |CPULKRF |CPU Lock-up Reset Flag
* | | |0 = No reset from CPU lock-up happened.
* | | |1 = The Cortex-M4 lock-up happened and chip is reset.
* | | |Note: Write 1 to clear this bit to 0.
* | | |Note2: When CPU lock-up happened under ICE is connected, This flag will set to 1 but chip will not reset.
* @var SYS_T::IPRST0
* Offset: 0x08 Peripheral Reset Control Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CHIPRST |Chip One-shot Reset (Write Protect)
* | | |Setting this bit will reset the whole chip, including Processor core and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles.
* | | |The CHIPRST is same as the POR reset, all the chip controllers is reset and the chip setting from flash are also reload.
* | | |About the difference between CHIPRST and SYSRESETREQ(AIRCR[2]), please refer to section 6.2.2
* | | |0 = Chip normal operation.
* | | |1 = Chip one-shot reset.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[1] |CPURST |Processor Core One-shot Reset (Write Protect)
* | | |Setting this bit will only reset the processor core and Flash Memory Controller(FMC), and this bit will automatically return to 0 after the 2 clock cycles.
* | | |0 = Processor core normal operation.
* | | |1 = Processor core one-shot reset.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[2] |PDMARST |PDMA Controller Reset (Write Protect)
* | | |Setting this bit to 1 will generate a reset signal to the PDMA
* | | |User needs to set this bit to 0 to release from reset state.
* | | |0 = PDMA controller normal operation.
* | | |1 = PDMA controller reset.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[3] |EBIRST |EBI Controller Reset (Write Protect)
* | | |Set this bit to 1 will generate a reset signal to the EBI
* | | |User needs to set this bit to 0 to release from the reset state.
* | | |0 = EBI controller normal operation.
* | | |1 = EBI controller reset.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[5] |EMACRST |EMAC Controller Reset (Write Protect)
* | | |Setting this bit to 1 will generate a reset signal to the EMAC controller
* | | |User needs to set this bit to 0 to release from the reset state.
* | | |0 = EMAC controller normal operation.
* | | |1 = EMAC controller reset.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[6] |SDH0RST |SDHOST0 Controller Reset (Write Protect)
* | | |Setting this bit to 1 will generate a reset signal to the SDHOST0 controller
* | | |User needs to set this bit to 0 to release from the reset state.
* | | |0 = SDHOST0 controller normal operation.
* | | |1 = SDHOST0 controller reset.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[7] |CRCRST |CRC Calculation Controller Reset (Write Protect)
* | | |Set this bit to 1 will generate a reset signal to the CRC calculation controller
* | | |User needs to set this bit to 0 to release from the reset state.
* | | |0 = CRC calculation controller normal operation.
* | | |1 = CRC calculation controller reset.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[10] |HSUSBDRST |HSUSBD Controller Reset (Write Protect)
* | | |Setting this bit to 1 will generate a reset signal to the HSUSBD controller
* | | |User needs to set this bit to 0 to release from the reset state.
* | | |0 = HSUSBD controller normal operation.
* | | |1 = HSUSBD controller reset.
* |[12] |CRPTRST |CRYPTO Controller Reset (Write Protect)
* | | |Setting this bit to 1 will generate a reset signal to the CRYPTO controller
* | | |User needs to set this bit to 0 to release from the reset state.
* | | |0 = CRYPTO controller normal operation.
* | | |1 = CRYPTO controller reset.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[14] |SPIMRST |SPIM Controller Reset
* | | |Setting this bit to 1 will generate a reset signal to the SPIM controller
* | | |User needs to set this bit to 0 to release from the reset state.
* | | |0 = SPIM controller normal operation.
* | | |1 = SPIM controller reset.
* |[16] |USBHRST |USBH Controller Reset (Write Protect)
* | | |Set this bit to 1 will generate a reset signal to the USBH controller
* | | |User needs to set this bit to 0 to release from the reset state.
* | | |0 = USBH controller normal operation.
* | | |1 = USBH controller reset.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[17] |SDH1RST |SDHOST1 Controller Reset (Write Protect)
* | | |Setting this bit to 1 will generate a reset signal to the SDHOST1 controller
* | | |User needs to set this bit to 0 to release from the reset state.
* | | |0 = SDHOST1 controller normal operation.
* | | |1 = SDHOST1 controller reset.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* @var SYS_T::IPRST1
* Offset: 0x0C Peripheral Reset Control Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1] |GPIORST |GPIO Controller Reset
* | | |0 = GPIO controller normal operation.
* | | |1 = GPIO controller reset.
* |[2] |TMR0RST |Timer0 Controller Reset
* | | |0 = Timer0 controller normal operation.
* | | |1 = Timer0 controller reset.
* |[3] |TMR1RST |Timer1 Controller Reset
* | | |0 = Timer1 controller normal operation.
* | | |1 = Timer1 controller reset.
* |[4] |TMR2RST |Timer2 Controller Reset
* | | |0 = Timer2 controller normal operation.
* | | |1 = Timer2 controller reset.
* |[5] |TMR3RST |Timer3 Controller Reset
* | | |0 = Timer3 controller normal operation.
* | | |1 = Timer3 controller reset.
* |[7] |ACMP01RST |Analog Comparator 0/1 Controller Reset
* | | |0 = Analog Comparator 0/1 controller normal operation.
* | | |1 = Analog Comparator 0/1 controller reset.
* |[8] |I2C0RST |I2C0 Controller Reset
* | | |0 = I2C0 controller normal operation.
* | | |1 = I2C0 controller reset.
* |[9] |I2C1RST |I2C1 Controller Reset
* | | |0 = I2C1 controller normal operation.
* | | |1 = I2C1 controller reset.
* |[10] |I2C2RST |I2C2 Controller Reset
* | | |0 = I2C2 controller normal operation.
* | | |1 = I2C2 controller reset.
* |[12] |SPI0RST |SPI0 Controller Reset
* | | |0 = SPI0 controller normal operation.
* | | |1 = SPI0 controller reset.
* |[13] |SPI1RST |SPI1 Controller Reset
* | | |0 = SPI1 controller normal operation.
* | | |1 = SPI1 controller reset.
* |[14] |SPI2RST |SPI2 Controller Reset
* | | |0 = SPI2 controller normal operation.
* | | |1 = SPI2 controller reset.
* |[15] |SPI3RST |SPI3 Controller Reset
* | | |0 = SPI3 controller normal operation.
* | | |1 = SPI3 controller reset.
* |[16] |UART0RST |UART0 Controller Reset
* | | |0 = UART0 controller normal operation.
* | | |1 = UART0 controller reset.
* |[17] |UART1RST |UART1 Controller Reset
* | | |0 = UART1 controller normal operation.
* | | |1 = UART1 controller reset.
* |[18] |UART2RST |UART2 Controller Reset
* | | |0 = UART2 controller normal operation.
* | | |1 = UART2 controller reset.
* |[19] |UART3RST |UART3 Controller Reset
* | | |0 = UART3 controller normal operation.
* | | |1 = UART3 controller reset.
* |[20] |UART4RST |UART4 Controller Reset
* | | |0 = UART4 controller normal operation.
* | | |1 = UART4 controller reset.
* |[21] |UART5RST |UART5 Controller Reset
* | | |0 = UART5 controller normal operation.
* | | |1 = UART5 controller reset.
* |[24] |CAN0RST |CAN0 Controller Reset
* | | |0 = CAN0 controller normal operation.
* | | |1 = CAN0 controller reset.
* |[25] |CAN1RST |CAN1 Controller Reset
* | | |0 = CAN1 controller normal operation.
* | | |1 = CAN1 controller reset.
* |[27] |USBDRST |USBD Controller Reset
* | | |0 = USBD controller normal operation.
* | | |1 = USBD controller reset.
* |[28] |EADCRST |EADC Controller Reset
* | | |0 = EADC controller normal operation.
* | | |1 = EADC controller reset.
* |[29] |I2S0RST |I2S0 Controller Reset
* | | |0 = I2S0 controller normal operation.
* | | |1 = I2S0 controller reset.
* @var SYS_T::IPRST2
* Offset: 0x10 Peripheral Reset Control Register 2
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SC0RST |SC0 Controller Reset
* | | |0 = SC0 controller normal operation.
* | | |1 = SC0 controller reset.
* |[1] |SC1RST |SC1 Controller Reset
* | | |0 = SC1 controller normal operation.
* | | |1 = SC1 controller reset.
* |[2] |SC2RST |SC2 Controller Reset
* | | |0 = SC2 controller normal operation.
* | | |1 = SC2 controller reset.
* |[6] |SPI4RST |SPI4 Controller Reset
* | | |0 = SPI4 controller normal operation.
* | | |1 = SPI4 controller reset.
* |[8] |USCI0RST |USCI0 Controller Reset
* | | |0 = USCI0 controller normal operation.
* | | |1 = USCI0 controller reset.
* |[9] |USCI1RST |USCI1 Controller Reset
* | | |0 = USCI1 controller normal operation.
* | | |1 = USCI1 controller reset.
* |[12] |DACRST |DAC Controller Reset
* | | |0 = DAC controller normal operation.
* | | |1 = DAC controller reset.
* |[16] |EPWM0RST |EPWM0 Controller Reset
* | | |0 = EPWM0 controller normal operation.
* | | |1 = EPWM0 controller reset.
* |[17] |EPWM1RST |EPWM1 Controller Reset
* | | |0 = EPWM1 controller normal operation.
* | | |1 = EPWM1 controller reset.
* |[18] |BPWM0RST |BPWM0 Controller Reset
* | | |0 = BPWM0 controller normal operation.
* | | |1 = BPWM0 controller reset.
* |[19] |BPWM1RST |BPWM1 Controller Reset
* | | |0 = BPWM1 controller normal operation.
* | | |1 = BPWM1 controller reset.
* |[22] |QEI0RST |QEI0 Controller Reset
* | | |0 = QEI0 controller normal operation.
* | | |1 = QEI0 controller reset.
* |[23] |QEI1RST |QEI1 Controller Reset
* | | |0 = QEI1 controller normal operation.
* | | |1 = QEI1 controller reset.
* |[26] |ECAP0RST |ECAP0 Controller Reset
* | | |0 = ECAP0 controller normal operation.
* | | |1 = ECAP0 controller reset.
* |[27] |ECAP1RST |ECAP1 Controller Reset
* | | |0 = ECAP1 controller normal operation.
* | | |1 = ECAP1 controller reset.
* |[30] |OPARST |OP Amplifier (OPA) Controller Reset
* | | |0 = OPA controller normal operation.
* | | |1 = OPA controller reset.
* @var SYS_T::BODCTL
* Offset: 0x18 Brown-Out Detector Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |BODEN |Brown-out Detector Enable Bit (Write Protect)
* | | |The default value is set by flash controller user configuration register CBODEN(CONFIG0 [19]).
* | | |0 = Brown-out Detector function Disabled.
* | | |1 = Brown-out Detector function Enabled.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[3] |BODRSTEN |Brown-out Reset Enable Bit (Write Protect)
* | | |The default value is set by flash controller user configuration register CBORST(CONFIG0[20]) bit .
* | | |0 = Brown-out INTERRUPT function Enabled.
* | | |1 = Brown-out RESET function Enabled.
* | | |Note1:
* | | |While the Brown-out Detector function is enabled (BODEN high) and BOD reset function is enabled (BODRSTEN high), BOD will assert a signal to reset chip when the detected voltage is lower than the threshold (BODOUT high).
* | | |While the BOD function is enabled (BODEN high) and BOD interrupt function is enabled (BODRSTEN low), BOD will assert an interrupt if BODOUT is high
* | | |BOD interrupt will keep till to the BODEN set to 0
* | | |BOD interrupt can be blocked by disabling the NVIC BOD interrupt or disabling BOD function (set BODEN low).
* | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[4] |BODIF |Brown-out Detector Interrupt Flag
* | | |0 = Brown-out Detector does not detect any voltage draft at VDD down through or up through the voltage of BODVL setting.
* | | |1 = When Brown-out Detector detects the VDD is dropped down through the voltage of BODVL setting or the VDD is raised up through the voltage of BODVL setting, this bit is set to 1 and the brown-out interrupt is requested if brown-out interrupt is enabled.
* | | |Note: Write 1 to clear this bit to 0.
* |[5] |BODLPM |Brown-out Detector Low Power Mode (Write Protect)
* | | |0 = BOD operate in normal mode (default).
* | | |1 = BOD Low Power mode Enabled.
* | | |Note1: The BOD consumes about 100uA in normal mode, the low power mode can reduce the current to about 1/10 but slow the BOD response.
* | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[6] |BODOUT |Brown-out Detector Output Status
* | | |0 = Brown-out Detector output status is 0.
* | | |It means the detected voltage is higher than BODVL setting or BODEN is 0.
* | | |1 = Brown-out Detector output status is 1.
* | | |It means the detected voltage is lower than BODVL setting
* | | |If the BODEN is 0, BOD function disabled , this bit always responds 0000.
* |[7] |LVREN |Low Voltage Reset Enable Bit (Write Protect)
* | | |The LVR function resets the chip when the input power voltage is lower than LVR circuit setting
* | | |LVR function is enabled by default.
* | | |0 = Low Voltage Reset function Disabled.
* | | |1 = Low Voltage Reset function Enabled.
* | | |Note1: After enabling the bit, the LVR function will be active with 100us delay for LVR output stable (default).
* | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[10:8] |BODDGSEL |Brown-out Detector Output De-glitch Time Select (Write Protect)
* | | |000 = BOD output is sampled by RC10K clock.
* | | |001 = 4 system clock (HCLK).
* | | |010 = 8 system clock (HCLK).
* | | |011 = 16 system clock (HCLK).
* | | |100 = 32 system clock (HCLK).
* | | |101 = 64 system clock (HCLK).
* | | |110 = 128 system clock (HCLK).
* | | |111 = 256 system clock (HCLK).
* | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register.
* |[14:12] |LVRDGSEL |LVR Output De-glitch Time Select (Write Protect)
* | | |000 = Without de-glitch function.
* | | |001 = 4 system clock (HCLK).
* | | |010 = 8 system clock (HCLK).
* | | |011 = 16 system clock (HCLK).
* | | |100 = 32 system clock (HCLK).
* | | |101 = 64 system clock (HCLK).
* | | |110 = 128 system clock (HCLK).
* | | |111 = 256 system clock (HCLK).
* | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register.
* |[18:16] |BODVL |Brown-out Detector Threshold Voltage Selection (Write Protect)
* | | |The default value is set by flash controller user configuration register CBOV (CONFIG0 [23:21]).
* | | |000 = Brown-Out Detector threshold voltage is 1.6V.
* | | |001 = Brown-Out Detector threshold voltage is 1.8V.
* | | |010 = Brown-Out Detector threshold voltage is 2.0V.
* | | |011 = Brown-Out Detector threshold voltage is 2.2V.
* | | |100 = Brown-Out Detector threshold voltage is 2.4V.
* | | |101 = Brown-Out Detector threshold voltage is 2.6V.
* | | |110 = Brown-Out Detector threshold voltage is 2.8V.
* | | |111 = Brown-Out Detector threshold voltage is 3.0V.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* @var SYS_T::IVSCTL
* Offset: 0x1C Internal Voltage Source Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |VTEMPEN |Temperature Sensor Enable Bit
* | | |This bit is used to enable/disable temperature sensor function.
* | | |0 = Temperature sensor function Disabled (default).
* | | |1 = Temperature sensor function Enabled.
* | | |Note: After this bit is set to 1, the value of temperature sensor output can be obtained through GPC.9.
* |[1] |VBATUGEN |VBAT Unity Gain Buffer Enable Bit
* | | |This bit is used to enable/disable VBAT unity gain buffer function.
* | | |0 = VBAT unity gain buffer function Disabled (default).
* | | |1 = VBAT unity gain buffer function Enabled.
* | | |Note: After this bit is set to 1, the value of VBAT unity gain buffer output voltage can be obtained from ADC conversion result
* @var SYS_T::PORCTL
* Offset: 0x24 Power-On-Reset Controller Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |POROFF |Power-on Reset Enable Bit (Write Protect)
* | | |When powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again
* | | |User can disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field.
* | | |The POR function will be active again when this field is set to another value or chip is reset by other reset source, including:
* | | |nRESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* @var SYS_T::VREFCTL
* Offset: 0x28 VREF Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[4:0] |VREFCTL |VREF Control Bits (Write Protect)
* | | |00000 = VREF is from external pin.
* | | |00011 = VREF is internal 1.6V.
* | | |00111 = VREF is internal 2.0V.
* | | |01011 = VREF is internal 2.5V.
* | | |01111 = VREF is internal 3.0V.
* | | |Others = Reserved.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[7:6] |PRELOAD_SEL|Pre-load Timing Selection.
* | | |00 = pre-load time is 60us for 0.1uF Capacitor.
* | | |01 = pre-load time is 310us for 1uF Capacitor.
* | | |10 = pre-load time is 1270us for 4.7uF Capacitor.
* | | |11 = pre-load time is 2650us for 10uF Capacitor.
* @var SYS_T::USBPHY
* Offset: 0x2C USB PHY Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1:0] |USBROLE |USB Role Option (Write Protect)
* | | |These two bits are used to select the role of USB.
* | | |00 = Standard USB Device mode.
* | | |01 = Standard USB Host mode.
* | | |10 = ID dependent mode.
* | | |11 = Reserved.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[2] |SBO |Note: This bit must always be kept 1. If set to 0, the result is unpredictable
* |[8] |USBEN |USB PHY Enable (Write Protect)
* | | |This bit is used to enable/disable USB PHY.
* | | |0 = USB PHY Disabled.
* | | |1 = USB PHY Enabled.
* |[17:16] |HSUSBROLE |HSUSB Role Option (Write Protect)
* | | |These two bits are used to select the role of HSUSB
* | | |00 = Standard HSUSB Device mode.
* | | |01 = Standard HSUSB Host mode.
* | | |10 = ID dependent mode.
* | | |11 = Reserved.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[24] |HSUSBEN |HSUSB PHY Enable (Write Protect)
* | | |This bit is used to enable/disable HSUSB PHY.
* | | |0 = HSUSB PHY Disabled.
* | | |1 = HSUSB PHY Enabled.
* |[25] |HSUSBACT |HSUSB PHY Active Control
* | | |This bit is used to control HSUSB PHY at reset state or active state.
* | | |0 = HSUSB PHY at reset state.
* | | |1 = HSUSB PHY at active state.
* | | |Note: After set HSUSBEN (SYS_USBPHY[24]) to enable HSUSB PHY, user should keep HSUSB PHY at reset mode at lease 10uS before changing to active mode.
* @var SYS_T::GPA_MFPL
* Offset: 0x30 GPIOA Low Byte Multiple Function Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |PA0MFP |PA.0 Multi-function Pin Selection
* |[7:4] |PA1MFP |PA.1 Multi-function Pin Selection
* |[11:8] |PA2MFP |PA.2 Multi-function Pin Selection
* |[15:12] |PA3MFP |PA.3 Multi-function Pin Selection
* |[19:16] |PA4MFP |PA.4 Multi-function Pin Selection
* |[23:20] |PA5MFP |PA.5 Multi-function Pin Selection
* |[27:24] |PA6MFP |PA.6 Multi-function Pin Selection
* |[31:28] |PA7MFP |PA.7 Multi-function Pin Selection
* @var SYS_T::GPA_MFPH
* Offset: 0x34 GPIOA High Byte Multiple Function Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |PA8MFP |PA.8 Multi-function Pin Selection
* |[7:4] |PA9MFP |PA.9 Multi-function Pin Selection
* |[11:8] |PA10MFP |PA.10 Multi-function Pin Selection
* |[15:12] |PA11MFP |PA.11 Multi-function Pin Selection
* |[19:16] |PA12MFP |PA.12 Multi-function Pin Selection
* |[23:20] |PA13MFP |PA.13 Multi-function Pin Selection
* |[27:24] |PA14MFP |PA.14 Multi-function Pin Selection
* |[31:28] |PA15MFP |PA.15 Multi-function Pin Selection
* @var SYS_T::GPB_MFPL
* Offset: 0x38 GPIOB Low Byte Multiple Function Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |PB0MFP |PB.0 Multi-function Pin Selection
* |[7:4] |PB1MFP |PB.1 Multi-function Pin Selection
* |[11:8] |PB2MFP |PB.2 Multi-function Pin Selection
* |[15:12] |PB3MFP |PB.3 Multi-function Pin Selection
* |[19:16] |PB4MFP |PB.4 Multi-function Pin Selection
* |[23:20] |PB5MFP |PB.5 Multi-function Pin Selection
* |[27:24] |PB6MFP |PB.6 Multi-function Pin Selection
* |[31:28] |PB7MFP |PB.7 Multi-function Pin Selection
* @var SYS_T::GPB_MFPH
* Offset: 0x3C GPIOB High Byte Multiple Function Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |PB8MFP |PB.8 Multi-function Pin Selection
* |[7:4] |PB9MFP |PB.9 Multi-function Pin Selection
* |[11:8] |PB10MFP |PB.10 Multi-function Pin Selection
* |[15:12] |PB11MFP |PB.11 Multi-function Pin Selection
* |[19:16] |PB12MFP |PB.12 Multi-function Pin Selection
* |[23:20] |PB13MFP |PB.13 Multi-function Pin Selection
* |[27:24] |PB14MFP |PB.14 Multi-function Pin Selection
* |[31:28] |PB15MFP |PB.15 Multi-function Pin Selection
* @var SYS_T::GPC_MFPL
* Offset: 0x40 GPIOC Low Byte Multiple Function Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |PC0MFP |PC.0 Multi-function Pin Selection
* |[7:4] |PC1MFP |PC.1 Multi-function Pin Selection
* |[11:8] |PC2MFP |PC.2 Multi-function Pin Selection
* |[15:12] |PC3MFP |PC.3 Multi-function Pin Selection
* |[19:16] |PC4MFP |PC.4 Multi-function Pin Selection
* |[23:20] |PC5MFP |PC.5 Multi-function Pin Selection
* |[27:24] |PC6MFP |PC.6 Multi-function Pin Selection
* |[31:28] |PC7MFP |PC.7 Multi-function Pin Selection
* @var SYS_T::GPC_MFPH
* Offset: 0x44 GPIOC High Byte Multiple Function Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |PC8MFP |PC.8 Multi-function Pin Selection
* |[7:4] |PC9MFP |PC.9 Multi-function Pin Selection
* |[11:8] |PC10MFP |PC.10 Multi-function Pin Selection
* |[15:12] |PC11MFP |PC.11 Multi-function Pin Selection
* |[19:16] |PC12MFP |PC.12 Multi-function Pin Selection
* |[23:20] |PC13MFP |PC.13 Multi-function Pin Selection
* |[27:24] |PC14MFP |PC.14 Multi-function Pin Selection
* |[31:28] |PC15MFP |PC.15 Multi-function Pin Selection
* @var SYS_T::GPD_MFPL
* Offset: 0x48 GPIOD Low Byte Multiple Function Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |PD0MFP |PD.0 Multi-function Pin Selection
* |[7:4] |PD1MFP |PD.1 Multi-function Pin Selection
* |[11:8] |PD2MFP |PD.2 Multi-function Pin Selection
* |[15:12] |PD3MFP |PD.3 Multi-function Pin Selection
* |[19:16] |PD4MFP |PD.4 Multi-function Pin Selection
* |[23:20] |PD5MFP |PD.5 Multi-function Pin Selection
* |[27:24] |PD6MFP |PD.6 Multi-function Pin Selection
* |[31:28] |PD7MFP |PD.7 Multi-function Pin Selection
* @var SYS_T::GPD_MFPH
* Offset: 0x4C GPIOD High Byte Multiple Function Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |PD8MFP |PD.8 Multi-function Pin Selection
* |[7:4] |PD9MFP |PD.9 Multi-function Pin Selection
* |[11:8] |PD10MFP |PD.10 Multi-function Pin Selection
* |[15:12] |PD11MFP |PD.11 Multi-function Pin Selection
* |[19:16] |PD12MFP |PD.12 Multi-function Pin Selection
* |[23:20] |PD13MFP |PD.13 Multi-function Pin Selection
* |[27:24] |PD14MFP |PD.14 Multi-function Pin Selection
* |[31:28] |PD15MFP |PD.15 Multi-function Pin Selection
* @var SYS_T::GPE_MFPL
* Offset: 0x50 GPIOE Low Byte Multiple Function Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |PE0MFP |PE.0 Multi-function Pin Selection
* |[7:4] |PE1MFP |PE.1 Multi-function Pin Selection
* |[11:8] |PE2MFP |PE.2 Multi-function Pin Selection
* |[15:12] |PE3MFP |PE.3 Multi-function Pin Selection
* |[19:16] |PE4MFP |PE.4 Multi-function Pin Selection
* |[23:20] |PE5MFP |PE.5 Multi-function Pin Selection
* |[27:24] |PE6MFP |PE.6 Multi-function Pin Selection
* |[31:28] |PE7MFP |PE.7 Multi-function Pin Selection
* @var SYS_T::GPE_MFPH
* Offset: 0x54 GPIOE High Byte Multiple Function Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |PE8MFP |PE.8 Multi-function Pin Selection
* |[7:4] |PE9MFP |PE.9 Multi-function Pin Selection
* |[11:8] |PE10MFP |PE.10 Multi-function Pin Selection
* |[15:12] |PE11MFP |PE.11 Multi-function Pin Selection
* |[19:16] |PE12MFP |PE.12 Multi-function Pin Selection
* |[23:20] |PE13MFP |PE.13 Multi-function Pin Selection
* |[27:24] |PE14MFP |PE.14 Multi-function Pin Selection
* |[31:28] |PE15MFP |PE.15 Multi-function Pin Selection
* @var SYS_T::GPF_MFPL
* Offset: 0x58 GPIOF Low Byte Multiple Function Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |PF0MFP |PF.0 Multi-function Pin Selection
* |[7:4] |PF1MFP |PF.1 Multi-function Pin Selection
* |[11:8] |PF2MFP |PF.2 Multi-function Pin Selection
* |[15:12] |PF3MFP |PF.3 Multi-function Pin Selection
* |[19:16] |PF4MFP |PF.4 Multi-function Pin Selection
* |[23:20] |PF5MFP |PF.5 Multi-function Pin Selection
* |[27:24] |PF6MFP |PF.6 Multi-function Pin Selection
* |[31:28] |PF7MFP |PF.7 Multi-function Pin Selection
* @var SYS_T::GPF_MFPH
* Offset: 0x5C GPIOF High Byte Multiple Function Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |PF8MFP |PF.8 Multi-function Pin Selection
* |[7:4] |PF9MFP |PF.9 Multi-function Pin Selection
* |[11:8] |PF10MFP |PF.10 Multi-function Pin Selection
* |[15:12] |PF11MFP |PF.11 Multi-function Pin Selection
* |[19:16] |PF12MFP |PF.12 Multi-function Pin Selection
* |[23:20] |PF13MFP |PF.13 Multi-function Pin Selection
* |[27:24] |PF14MFP |PF.14 Multi-function Pin Selection
* |[31:28] |PF15MFP |PF.15 Multi-function Pin Selection
* @var SYS_T::GPG_MFPL
* Offset: 0x60 GPIOG Low Byte Multiple Function Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |PG0MFP |PG.0 Multi-function Pin Selection
* |[7:4] |PG1MFP |PG.1 Multi-function Pin Selection
* |[11:8] |PG2MFP |PG.2 Multi-function Pin Selection
* |[15:12] |PG3MFP |PG.3 Multi-function Pin Selection
* |[19:16] |PG4MFP |PG.4 Multi-function Pin Selection
* |[23:20] |PG5MFP |PG.5 Multi-function Pin Selection
* |[27:24] |PG6MFP |PG.6 Multi-function Pin Selection
* |[31:28] |PG7MFP |PG.7 Multi-function Pin Selection
* @var SYS_T::GPG_MFPH
* Offset: 0x64 GPIOG High Byte Multiple Function Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |PG8MFP |PG.8 Multi-function Pin Selection
* |[7:4] |PG9MFP |PG.9 Multi-function Pin Selection
* |[11:8] |PG10MFP |PG.10 Multi-function Pin Selection
* |[15:12] |PG11MFP |PG.11 Multi-function Pin Selection
* |[19:16] |PG12MFP |PG.12 Multi-function Pin Selection
* |[23:20] |PG13MFP |PG.13 Multi-function Pin Selection
* |[27:24] |PG14MFP |PG.14 Multi-function Pin Selection
* |[31:28] |PG15MFP |PG.15 Multi-function Pin Selection
* @var SYS_T::GPH_MFPL
* Offset: 0x68 GPIOH Low Byte Multiple Function Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |PH0MFP |PH.0 Multi-function Pin Selection
* |[7:4] |PH1MFP |PH.1 Multi-function Pin Selection
* |[11:8] |PH2MFP |PH.2 Multi-function Pin Selection
* |[15:12] |PH3MFP |PH.3 Multi-function Pin Selection
* |[19:16] |PH4MFP |PH.4 Multi-function Pin Selection
* |[23:20] |PH5MFP |PH.5 Multi-function Pin Selection
* |[27:24] |PH6MFP |PH.6 Multi-function Pin Selection
* |[31:28] |PH7MFP |PH.7 Multi-function Pin Selection
* @var SYS_T::GPH_MFPH
* Offset: 0x6C GPIOH High Byte Multiple Function Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |PH8MFP |PH.8 Multi-function Pin Selection
* |[7:4] |PH9MFP |PH.9 Multi-function Pin Selection
* |[11:8] |PH10MFP |PH.10 Multi-function Pin Selection
* |[15:12] |PH11MFP |PH.11 Multi-function Pin Selection
* |[19:16] |PH12MFP |PH.12 Multi-function Pin Selection
* |[23:20] |PH13MFP |PH.13 Multi-function Pin Selection
* |[27:24] |PH14MFP |PH.14 Multi-function Pin Selection
* |[31:28] |PH15MFP |PH.15 Multi-function Pin Selection
* @var SYS_T::GPA_MFOS
* Offset: 0x80 GPIOA Multiple Function Output Select Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |MFOS0 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[1] |MFOS1 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[2] |MFOS2 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[3] |MFOS3 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[4] |MFOS4 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[5] |MFOS5 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[6] |MFOS6 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[7] |MFOS7 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[8] |MFOS8 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[9] |MFOS9 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[10] |MFOS10 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[11] |MFOS11 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[12] |MFOS12 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[13] |MFOS13 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[14] |MFOS14 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[15] |MFOS15 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* @var SYS_T::GPB_MFOS
* Offset: 0x84 GPIOB Multiple Function Output Select Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |MFOS0 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[1] |MFOS1 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[2] |MFOS2 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[3] |MFOS3 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[4] |MFOS4 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[5] |MFOS5 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[6] |MFOS6 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[7] |MFOS7 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[8] |MFOS8 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[9] |MFOS9 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[10] |MFOS10 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[11] |MFOS11 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[12] |MFOS12 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[13] |MFOS13 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[14] |MFOS14 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[15] |MFOS15 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* @var SYS_T::GPC_MFOS
* Offset: 0x88 GPIOC Multiple Function Output Select Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |MFOS0 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[1] |MFOS1 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[2] |MFOS2 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[3] |MFOS3 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[4] |MFOS4 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[5] |MFOS5 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[6] |MFOS6 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[7] |MFOS7 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[8] |MFOS8 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[9] |MFOS9 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[10] |MFOS10 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[11] |MFOS11 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[12] |MFOS12 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[13] |MFOS13 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[14] |MFOS14 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[15] |MFOS15 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* @var SYS_T::GPD_MFOS
* Offset: 0x8C GPIOD Multiple Function Output Select Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |MFOS0 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[1] |MFOS1 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[2] |MFOS2 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[3] |MFOS3 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[4] |MFOS4 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[5] |MFOS5 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[6] |MFOS6 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[7] |MFOS7 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[8] |MFOS8 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[9] |MFOS9 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[10] |MFOS10 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[11] |MFOS11 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[12] |MFOS12 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[13] |MFOS13 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[14] |MFOS14 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[15] |MFOS15 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* @var SYS_T::GPE_MFOS
* Offset: 0x90 GPIOE Multiple Function Output Select Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |MFOS0 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[1] |MFOS1 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[2] |MFOS2 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[3] |MFOS3 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[4] |MFOS4 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[5] |MFOS5 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[6] |MFOS6 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[7] |MFOS7 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[8] |MFOS8 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[9] |MFOS9 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[10] |MFOS10 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[11] |MFOS11 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[12] |MFOS12 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[13] |MFOS13 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[14] |MFOS14 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[15] |MFOS15 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* @var SYS_T::GPF_MFOS
* Offset: 0x94 GPIOF Multiple Function Output Select Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |MFOS0 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[1] |MFOS1 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[2] |MFOS2 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[3] |MFOS3 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[4] |MFOS4 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[5] |MFOS5 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[6] |MFOS6 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[7] |MFOS7 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[8] |MFOS8 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[9] |MFOS9 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[10] |MFOS10 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[11] |MFOS11 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[12] |MFOS12 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[13] |MFOS13 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[14] |MFOS14 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[15] |MFOS15 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* @var SYS_T::GPG_MFOS
* Offset: 0x98 GPIOG Multiple Function Output Select Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |MFOS0 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[1] |MFOS1 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[2] |MFOS2 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[3] |MFOS3 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[4] |MFOS4 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[5] |MFOS5 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[6] |MFOS6 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[7] |MFOS7 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[8] |MFOS8 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[9] |MFOS9 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[10] |MFOS10 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[11] |MFOS11 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[12] |MFOS12 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[13] |MFOS13 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[14] |MFOS14 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[15] |MFOS15 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* @var SYS_T::GPH_MFOS
* Offset: 0x9C GPIOH Multiple Function Output Select Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |MFOS0 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[1] |MFOS1 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[2] |MFOS2 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[3] |MFOS3 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[4] |MFOS4 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[5] |MFOS5 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[6] |MFOS6 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[7] |MFOS7 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[8] |MFOS8 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[9] |MFOS9 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[10] |MFOS10 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[11] |MFOS11 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[12] |MFOS12 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[13] |MFOS13 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[14] |MFOS14 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[15] |MFOS15 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin
* | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* @var SYS_T::SRAM_INTCTL
* Offset: 0xC0 System SRAM Interrupt Enable Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |PERRIEN |SRAM Parity Check Error Interrupt Enable Bit
* | | |0 = SRAM parity check error interrupt Disabled.
* | | |1 = SRAM parity check error interrupt Enabled.
* @var SYS_T::SRAM_STATUS
* Offset: 0xC4 System SRAM Parity Error Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |PERRIF |SRAM Parity Check Error Flag
* | | |This bit indicates the System SRAM parity error occurred. Write 1 to clear this to 0.
* | | |0 = No System SRAM parity error.
* | | |1 = System SRAM parity error occur.
* @var SYS_T::SRAM_ERRADDR
* Offset: 0xC8 System SRAM Parity Check Error Address Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |ERRADDR |System SRAM Parity Error Address
* | | |This register shows system SRAM parity error byte address.
* @var SYS_T::SRAM_BISTCTL
* Offset: 0xD0 System SRAM BIST Test Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SRBIST0 |SRAM Bank0 BIST Enable Bit (Write Protect)
* | | |This bit enables BIST test for SRAM bank0.
* | | |0 = system SRAM bank0 BIST Disabled.
* | | |1 = system SRAM bank0 BIST Enabled.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[1] |SRBIST1 |SRAM Bank1 BIST Enable Bit (Write Protect)
* | | |This bit enables BIST test for SRAM bank1.
* | | |0 = system SRAM bank1 BIST Disabled.
* | | |1 = system SRAM bank1 BIST Enabled.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[2] |CRBIST |CACHE BIST Enable Bit (Write Protect)
* | | |This bit enables BIST test for CACHE RAM
* | | |0 = system CACHE BIST Disabled.
* | | |1 = system CACHE BIST Enabled.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[3] |CANBIST |CAN BIST Enable Bit (Write Protect)
* | | |This bit enables BIST test for CAN RAM
* | | |0 = system CAN BIST Disabled.
* | | |1 = system CAN BIST Enabled.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[4] |USBBIST |USB BIST Enable Bit (Write Protect)
* | | |This bit enables BIST test for USB RAM
* | | |0 = system USB BIST Disabled.
* | | |1 = system USB BIST Enabled.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[5] |SPIMBIST |SPIM BIST Enable Bit (Write Protect)
* | | |This bit enables BIST test for SPIM RAM
* | | |0 = system SPIM BIST Disabled.
* | | |1 = system SPIM BIST Enabled.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[6] |EMCBIST |EMC BIST Enable Bit (Write Protect)
* | | |This bit enables BIST test for EMC RAM
* | | |0 = system EMC BIST Disabled.
* | | |1 = system EMC BIST Enabled.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[7] |PDMABIST |PDMA BIST Enable Bit (Write Protect)
* | | |This bit enables BIST test for PDMA RAM
* | | |0 = system PDMA BIST Disabled.
* | | |1 = system PDMA BIST Enabled.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[8] |HSUSBDBIST|HSUSBD BIST Enable Bit (Write Protect)
* | | |This bit enables BIST test for HSUSBD RAM
* | | |0 = system HSUSBD BIST Disabled.
* | | |1 = system HSUSBD BIST Enabled.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[9] |HSUSBHBIST|HSUSBH BIST Enable Bit (Write Protect)
* | | |This bit enables BIST test for HSUSBH RAM
* | | |0 = system HSUSBH BIST Disabled.
* | | |1 = system HSUSBH BIST Enabled.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[16] |SRB0S0 |SRAM Bank0 Section 0 BIST Select (Write Protect)
* | | |This bit define if the first 16KB section of SRAM bank0 is selected or not when doing bist test.
* | | |0 = SRAM bank0 section 0 is deselected when doing bist test.
* | | |1 = SRAM bank0 section 0 is selected when doing bist test.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* | | |Note: At least one section of SRAM bank0 should be selected when doing SRAM bank0 bist test.
* |[17] |SRB0S1 |SRAM Bank0 Section 1 BIST Select (Write Protect)
* | | |This bit define if the second 16KB section of SRAM bank0 is selected or not when doing bist test.
* | | |0 = SRAM bank0 section 1 is deselected when doing bist test.
* | | |1 = SRAM bank0 section 1 is selected when doing bist test.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* | | |Note: At least one section of SRAM bank0 should be selected when doing SRAM bank0 bist test.
* |[18] |SRB1S0 |SRAM Bank1 Section 0 BIST Select (Write Protect)
* | | |This bit define if the first 16KB section of SRAM bank1 is selected or not when doing bist test.
* | | |0 = SRAM bank1 first 16KB section is deselected when doing bist test.
* | | |1 = SRAM bank1 first 16KB section is selected when doing bist test.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* | | |Note: At least one section of SRAM bank1 should be selected when doing SRAM bank1 bist test.
* |[19] |SRB1S1 |SRAM Bank1 Section 1 BIST Select (Write Protect)
* | | |This bit define if the second 16KB section of SRAM bank1 is selected or not when doing bist test.
* | | |0 = SRAM bank1 second 16KB section is deselected when doing bist test.
* | | |1 = SRAM bank1 second 16KB section is selected when doing bist test.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* | | |Note: At least one section of SRAM bank1 should be selected when doing SRAM bank1 bist test.
* |[20] |SRB1S2 |SRAM Bank1 Section 0 BIST Select (Write Protect)
* | | |This bit define if the third 16KB section of SRAM bank1 is selected or not when doing bist test.
* | | |0 = SRAM bank1 third 16KB section is deselected when doing bist test.
* | | |1 = SRAM bank1 third 16KB section is selected when doing bist test.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* | | |Note: At least one section of SRAM bank1 should be selected when doing SRAM bank1 bist test.
* |[21] |SRB1S3 |SRAM Bank1 Section 1 BIST Select (Write Protect)
* | | |This bit define if the fourth 16KB section of SRAM bank1 is selected or not when doing bist test.
* | | |0 = SRAM bank1 fourth 16KB section is deselected when doing bist test.
* | | |1 = SRAM bank1 fourth 16KB section is selected when doing bist test.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* | | |Note: At least one section of SRAM bank1 should be selected when doing SRAM bank1 bist test.
* |[22] |SRB1S4 |SRAM Bank1 Section 0 BIST Select (Write Protect)
* | | |This bit define if the fifth 16KB section of SRAM bank1 is selected or not when doing bist test.
* | | |0 = SRAM bank1 fifth 16KB section is deselected when doing bist test.
* | | |1 = SRAM bank1 fifth 16KB section is selected when doing bist test.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* | | |Note: At least one section of SRAM bank1 should be selected when doing SRAM bank1 bist test.
* |[23] |SRB1S5 |SRAM Bank1 Section 1 BIST Select (Write Protect)
* | | |This bit define if the sixth 16KB section of SRAM bank1 is selected or not when doing bist test.
* | | |0 = SRAM bank1 sixth 16KB section is deselected when doing bist test.
* | | |1 = SRAM bank1 sixth 16KB section is selected when doing bist test.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* | | |Note: At least one section of SRAM bank1 should be selected when doing SRAM bank1 bist test.
* @var SYS_T::SRAM_BISTSTS
* Offset: 0xD4 System SRAM BIST Test Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SRBISTEF0 |1st System SRAM BIST Fail Flag
* | | |0 = 1st system SRAM BIST test pass.
* | | |1 = 1st system SRAM BIST test fail.
* |[1] |SRBISTEF1 |2nd System SRAM BIST Fail Flag
* | | |0 = 2nd system SRAM BIST test pass.
* | | |1 = 2nd system SRAM BIST test fail.
* |[2] |CRBISTEF |CACHE SRAM BIST Fail Flag
* | | |0 = System CACHE RAM BIST test pass.
* | | |1 = System CACHE RAM BIST test fail.
* |[3] |CANBEF |CAN SRAM BIST Fail Flag
* | | |0 = CAN SRAM BIST test pass.
* | | |1 = CAN SRAM BIST test fail.
* |[4] |USBBEF |USB SRAM BIST Fail Flag
* | | |0 = USB SRAM BIST test pass.
* | | |1 = USB SRAM BIST test fail.
* |[16] |SRBEND0 |1st SRAM BIST Test Finish
* | | |0 = 1st system SRAM BIST active.
* | | |1 =1st system SRAM BIST finish.
* |[17] |SRBEND1 |2nd SRAM BIST Test Finish
* | | |0 = 2nd system SRAM BIST is active.
* | | |1 = 2nd system SRAM BIST finish.
* |[18] |CRBEND |CACHE SRAM BIST Test Finish
* | | |0 = System CACHE RAM BIST is active.
* | | |1 = System CACHE RAM BIST test finish.
* |[19] |CANBEND |CAN SRAM BIST Test Finish
* | | |0 = CAN SRAM BIST is active.
* | | |1 = CAN SRAM BIST test finish.
* |[20] |USBBEND |USB SRAM BIST Test Finish
* | | |0 = USB SRAM BIST is active.
* | | |1 = USB SRAM BIST test finish.
* @var SYS_T::IRCTCTL
* Offset: 0xF0 HIRC Trim Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1:0] |FREQSEL |Trim Frequency Selection
* | | |This field indicates the target frequency of 12 MHz internal high speed RC oscillator (HIRC) auto trim.
* | | |During auto trim operation, if clock error detected with CESTOPEN is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically.
* | | |00 = Disable HIRC auto trim function.
* | | |01 = Enable HIRC auto trim function and trim HIRC to 12 MHz.
* | | |10 = Reserved..
* | | |11 = Reserved.
* |[5:4] |LOOPSEL |Trim Calculation Loop Selection
* | | |This field defines that trim value calculation is based on how many reference clocks.
* | | |00 = Trim value calculation is based on average difference in 4 clocks of reference clock.
* | | |01 = Trim value calculation is based on average difference in 8 clocks of reference clock.
* | | |10 = Trim value calculation is based on average difference in 16 clocks of reference clock.
* | | |11 = Trim value calculation is based on average difference in 32 clocks of reference clock.
* | | |Note: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 clocks of reference clock.
* |[7:6] |RETRYCNT |Trim Value Update Limitation Count
* | | |This field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked.
* | | |Once the HIRC locked, the internal trim value update counter will be reset.
* | | |If the trim value update counter reached this limitation value and frequency of HIRC still doesn't lock, the auto trim operation will be disabled and FREQSEL will be cleared to 00.
* | | |00 = Trim retry count limitation is 64 loops.
* | | |01 = Trim retry count limitation is 128 loops.
* | | |10 = Trim retry count limitation is 256 loops.
* | | |11 = Trim retry count limitation is 512 loops.
* |[8] |CESTOPEN |Clock Error Stop Enable Bit
* | | |0 = The trim operation is keep going if clock is inaccuracy.
* | | |1 = The trim operation is stopped if clock is inaccuracy.
* |[10] |REFCKSEL |Reference Clock Selection
* | | |0 = HIRC trim reference clock is from LXT (32.768 kHz).
* | | |1 = HIRC trim reference clock is from USB SOF (Start-Of-Frame) packet.
* | | |Note: HIRC trim reference clock is 20Khz in test mode.
* @var SYS_T::IRCTIEN
* Offset: 0xF4 HIRC Trim Interrupt Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1] |TFAILIEN |Trim Failure Interrupt Enable Bit
* | | |This bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL(SYS_IRCTCTL[1:0]).
* | | |If this bit is high and TFAILIF(SYS_IRCTISTS[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached.
* | | |0 = Disable TFAILIF(SYS_IRCTISTS[1]) status to trigger an interrupt to CPU.
* | | |1 = Enable TFAILIF(SYS_IRCTISTS[1]) status to trigger an interrupt to CPU.
* |[2] |CLKEIEN |Clock Error Interrupt Enable Bit
* | | |This bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation.
* | | |If this bit is set to1, and CLKERRIF(SYS_IRCTISTS[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy.
* | | |0 = Disable CLKERRIF(SYS_IRCTISTS[2]) status to trigger an interrupt to CPU.
* | | |1 = Enable CLKERRIF(SYS_IRCTISTS[2]) status to trigger an interrupt to CPU.
* @var SYS_T::IRCTISTS
* Offset: 0xF8 HIRC Trim Interrupt Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |FREQLOCK |HIRC Frequency Lock Status
* | | |This bit indicates the HIRC frequency is locked.
* | | |This is a status bit and doesn't trigger any interrupt
* | | |Write 1 to clear this to 0
* | | |This bit will be set automatically, if the frequency is lock and the RC_TRIM is enabled.
* | | |0 = The internal high-speed oscillator frequency doesn't lock at 12 MHz yet.
* | | |1 = The internal high-speed oscillator frequency locked at 12 MHz.
* |[1] |TFAILIF |Trim Failure Interrupt Status
* | | |This bit indicates that HIRC trim value update limitation count reached and the HIRC clock frequency still doesn't be locked
* | | |Once this bit is set, the auto trim operation stopped and FREQSEL(SYS_IRCTCTL[1:0]) will be cleared to 00 by hardware automatically.
* | | |If this bit is set and TFAILIEN(SYS_IRCTIEN[1]) is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached
* | | |Write 1 to clear this to 0.
* | | |0 = Trim value update limitation count does not reach.
* | | |1 = Trim value update limitation count reached and HIRC frequency still not locked.
* |[2] |CLKERRIF |Clock Error Interrupt Status
* | | |When the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or 12MHz internal high speed RC oscillator (HIRC) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy.
* | | |Once this bit is set to 1, the auto trim operation stopped and FREQSEL(SYS_IRCTCL[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN(SYS_IRCTCTL[8]) is set to 1.
* | | |If this bit is set and CLKEIEN(SYS_IRCTIEN[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy.
* | | |Write 1 to clear this to 0.
* | | |0 = Clock frequency is accuracy.
* | | |1 = Clock frequency is inaccuracy.
* @var SYS_T::REGLCTL
* Offset: 0x100 Register Lock Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |REGLCTL |Register Lock Control Code (Write Only)
* | | |Some registers have write-protection function
* | | |Writing these registers have to disable the protected function by writing the sequence value "59h", "16h", "88h" to this field.
* | | |After this sequence is completed, the REGLCTL bit will be set to 1 and write-protection registers can be normal write.
* | | |Register Lock Control Code (Read Only)
* | | |0 = Write-protection Enabled for writing protected registers
* | | |Any write to the protected register is ignored.
* | | |1 = Write-protection Disabled for writing protected registers.
* @var SYS_T::PLCTL
* Offset: 0x1F8 Power Level Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1:0] |PLSEL |Power Level Select(Write Protect)
* | | |00 = Set core voltage to 1.26V.
* | | |01 = Set core voltage to 1.2V.
* | | |10 = Set core voltage to 0.9V.
* | | |11 = Reserved.
* |[21:16] |LVSSTEP |LDO Voltage Scaling Step(Write Protect)
* | | |The LVSSTEP value is LDO voltage rising step.
* | | |Core voltage scaling voltage step = (LVSSTEP + 1) * 10mV.
* |[31:24] |LVSPRD |LDO Voltage Scaling Period(Write Protect)
* | | |The LVSPRD value is the period of each LDO voltage rising step.
* | | |LDO voltage scaling period = (LVSPRD + 1) * 1us.
* @var SYS_T::PLSTS
* Offset: 0x1FC Power Level Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |PLCBUSY |Power Level Change Busy Bit (Read Only)
* | | |This bit is set by hardware when core voltage is changing
* | | |After core voltage change is completed, this bit will be cleared automatically by hardware.
* | | |0 = Core voltage change is completed.
* | | |1 = Core voltage change is ongoing.
* |[9:8] |PLSTATUS |Power Level Status (Read Only)
* | | |00 = Power level is PL0.
* | | |01 = Power level is PL1.
* | | |Others = Reserved.
* @var SYS_T::AHBMCTL
* Offset: 0x400 AHB Bus Matrix Priority Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |INTACTEN |Highest AHB Bus Priority of Cortex M4 Core Enable Bit (Write Protect)
* | | |Enable Cortex-M4 Core With Highest AHB Bus Priority In AHB Bus Matrix
* | | |0 = Run robin mode.
* | | |1 = Cortex-M4 CPU with highest bus priority when interrupt occurred.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
*/
__I uint32_t PDID; /*!< [0x0000] Part Device Identification Number Register */
__IO uint32_t RSTSTS; /*!< [0x0004] System Reset Status Register */
__IO uint32_t IPRST0; /*!< [0x0008] Peripheral Reset Control Register 0 */
__IO uint32_t IPRST1; /*!< [0x000c] Peripheral Reset Control Register 1 */
__IO uint32_t IPRST2; /*!< [0x0010] Peripheral Reset Control Register 2 */
/** @cond HIDDEN_SYMBOLS */
__I uint32_t RESERVE0[1];
/** @endcond */
__IO uint32_t BODCTL; /*!< [0x0018] Brown-Out Detector Control Register */
__IO uint32_t IVSCTL; /*!< [0x001c] Internal Voltage Source Control Register */
/** @cond HIDDEN_SYMBOLS */
__I uint32_t RESERVE1[1];
/** @endcond */
__IO uint32_t PORCTL; /*!< [0x0024] Power-On-Reset Controller Register */
__IO uint32_t VREFCTL; /*!< [0x0028] VREF Control Register */
__IO uint32_t USBPHY; /*!< [0x002c] USB PHY Control Register */
__IO uint32_t GPA_MFPL; /*!< [0x0030] GPIOA Low Byte Multiple Function Control Register */
__IO uint32_t GPA_MFPH; /*!< [0x0034] GPIOA High Byte Multiple Function Control Register */
__IO uint32_t GPB_MFPL; /*!< [0x0038] GPIOB Low Byte Multiple Function Control Register */
__IO uint32_t GPB_MFPH; /*!< [0x003c] GPIOB High Byte Multiple Function Control Register */
__IO uint32_t GPC_MFPL; /*!< [0x0040] GPIOC Low Byte Multiple Function Control Register */
__IO uint32_t GPC_MFPH; /*!< [0x0044] GPIOC High Byte Multiple Function Control Register */
__IO uint32_t GPD_MFPL; /*!< [0x0048] GPIOD Low Byte Multiple Function Control Register */
__IO uint32_t GPD_MFPH; /*!< [0x004c] GPIOD High Byte Multiple Function Control Register */
__IO uint32_t GPE_MFPL; /*!< [0x0050] GPIOE Low Byte Multiple Function Control Register */
__IO uint32_t GPE_MFPH; /*!< [0x0054] GPIOE High Byte Multiple Function Control Register */
__IO uint32_t GPF_MFPL; /*!< [0x0058] GPIOF Low Byte Multiple Function Control Register */
__IO uint32_t GPF_MFPH; /*!< [0x005c] GPIOF High Byte Multiple Function Control Register */
__IO uint32_t GPG_MFPL; /*!< [0x0060] GPIOG Low Byte Multiple Function Control Register */
__IO uint32_t GPG_MFPH; /*!< [0x0064] GPIOG High Byte Multiple Function Control Register */
__IO uint32_t GPH_MFPL; /*!< [0x0068] GPIOH Low Byte Multiple Function Control Register */
__IO uint32_t GPH_MFPH; /*!< [0x006c] GPIOH High Byte Multiple Function Control Register */
/** @cond HIDDEN_SYMBOLS */
__I uint32_t RESERVE2[4];
/** @endcond */
__IO uint32_t GPA_MFOS; /*!< [0x0080] GPIOA Multiple Function Output Select Register */
__IO uint32_t GPB_MFOS; /*!< [0x0084] GPIOB Multiple Function Output Select Register */
__IO uint32_t GPC_MFOS; /*!< [0x0088] GPIOC Multiple Function Output Select Register */
__IO uint32_t GPD_MFOS; /*!< [0x008c] GPIOD Multiple Function Output Select Register */
__IO uint32_t GPE_MFOS; /*!< [0x0090] GPIOE Multiple Function Output Select Register */
__IO uint32_t GPF_MFOS; /*!< [0x0094] GPIOF Multiple Function Output Select Register */
__IO uint32_t GPG_MFOS; /*!< [0x0098] GPIOG Multiple Function Output Select Register */
__IO uint32_t GPH_MFOS; /*!< [0x009c] GPIOH Multiple Function Output Select Register */
/** @cond HIDDEN_SYMBOLS */
__I uint32_t RESERVE3[8];
/** @endcond */
__IO uint32_t SRAM_INTCTL; /*!< [0x00c0] System SRAM Interrupt Enable Control Register */
__IO uint32_t SRAM_STATUS; /*!< [0x00c4] System SRAM Parity Error Status Register */
__I uint32_t SRAM_ERRADDR; /*!< [0x00c8] System SRAM Parity Check Error Address Register */
/** @cond HIDDEN_SYMBOLS */
__I uint32_t RESERVE4[1];
/** @endcond */
__IO uint32_t SRAM_BISTCTL; /*!< [0x00d0] System SRAM BIST Test Control Register */
__I uint32_t SRAM_BISTSTS; /*!< [0x00d4] System SRAM BIST Test Status Register */
/** @cond HIDDEN_SYMBOLS */
__I uint32_t RESERVE5[6];
/** @endcond */
__IO uint32_t IRCTCTL; /*!< [0x00f0] HIRC Trim Control Register */
__IO uint32_t IRCTIEN; /*!< [0x00f4] HIRC Trim Interrupt Enable Register */
__IO uint32_t IRCTISTS; /*!< [0x00f8] HIRC Trim Interrupt Status Register */
/** @cond HIDDEN_SYMBOLS */
__I uint32_t RESERVE6[1];
/** @endcond */
__IO uint32_t REGLCTL; /*!< [0x0100] Register Lock Control Register */
/** @cond HIDDEN_SYMBOLS */
__I uint32_t RESERVE7[61];
/** @endcond */
__IO uint32_t PLCTL; /*!< [0x01f8] Power Level Control Register */
__I uint32_t PLSTS; /*!< [0x01fc] Power Level Status Register */
/** @cond HIDDEN_SYMBOLS */
__I uint32_t RESERVE8[128];
/** @endcond */
__IO uint32_t AHBMCTL; /*!< [0x0400] AHB Bus Matrix Priority Control Register */
} SYS_T;
/**
@addtogroup SYS_CONST SYS Bit Field Definition
Constant Definitions for SYS Controller
@{ */
#define SYS_PDID_PDID_Pos (0) /*!< SYS_T::PDID: PDID Position */
#define SYS_PDID_PDID_Msk (0xfffffffful << SYS_PDID_PDID_Pos) /*!< SYS_T::PDID: PDID Mask */
#define SYS_RSTSTS_PORF_Pos (0) /*!< SYS_T::RSTSTS: PORF Position */
#define SYS_RSTSTS_PORF_Msk (0x1ul << SYS_RSTSTS_PORF_Pos) /*!< SYS_T::RSTSTS: PORF Mask */
#define SYS_RSTSTS_PINRF_Pos (1) /*!< SYS_T::RSTSTS: PINRF Position */
#define SYS_RSTSTS_PINRF_Msk (0x1ul << SYS_RSTSTS_PINRF_Pos) /*!< SYS_T::RSTSTS: PINRF Mask */
#define SYS_RSTSTS_WDTRF_Pos (2) /*!< SYS_T::RSTSTS: WDTRF Position */
#define SYS_RSTSTS_WDTRF_Msk (0x1ul << SYS_RSTSTS_WDTRF_Pos) /*!< SYS_T::RSTSTS: WDTRF Mask */
#define SYS_RSTSTS_LVRF_Pos (3) /*!< SYS_T::RSTSTS: LVRF Position */
#define SYS_RSTSTS_LVRF_Msk (0x1ul << SYS_RSTSTS_LVRF_Pos) /*!< SYS_T::RSTSTS: LVRF Mask */
#define SYS_RSTSTS_BODRF_Pos (4) /*!< SYS_T::RSTSTS: BODRF Position */
#define SYS_RSTSTS_BODRF_Msk (0x1ul << SYS_RSTSTS_BODRF_Pos) /*!< SYS_T::RSTSTS: BODRF Mask */
#define SYS_RSTSTS_SYSRF_Pos (5) /*!< SYS_T::RSTSTS: SYSRF Position */
#define SYS_RSTSTS_SYSRF_Msk (0x1ul << SYS_RSTSTS_SYSRF_Pos) /*!< SYS_T::RSTSTS: SYSRF Mask */
#define SYS_RSTSTS_CPURF_Pos (7) /*!< SYS_T::RSTSTS: CPURF Position */
#define SYS_RSTSTS_CPURF_Msk (0x1ul << SYS_RSTSTS_CPURF_Pos) /*!< SYS_T::RSTSTS: CPURF Mask */
#define SYS_RSTSTS_CPULKRF_Pos (8) /*!< SYS_T::RSTSTS: CPULKRF Position */
#define SYS_RSTSTS_CPULKRF_Msk (0x1ul << SYS_RSTSTS_CPULKRF_Pos) /*!< SYS_T::RSTSTS: CPULKRF Mask */
#define SYS_IPRST0_CHIPRST_Pos (0) /*!< SYS_T::IPRST0: CHIPRST Position */
#define SYS_IPRST0_CHIPRST_Msk (0x1ul << SYS_IPRST0_CHIPRST_Pos) /*!< SYS_T::IPRST0: CHIPRST Mask */
#define SYS_IPRST0_CPURST_Pos (1) /*!< SYS_T::IPRST0: CPURST Position */
#define SYS_IPRST0_CPURST_Msk (0x1ul << SYS_IPRST0_CPURST_Pos) /*!< SYS_T::IPRST0: CPURST Mask */
#define SYS_IPRST0_PDMARST_Pos (2) /*!< SYS_T::IPRST0: PDMARST Position */
#define SYS_IPRST0_PDMARST_Msk (0x1ul << SYS_IPRST0_PDMARST_Pos) /*!< SYS_T::IPRST0: PDMARST Mask */
#define SYS_IPRST0_EBIRST_Pos (3) /*!< SYS_T::IPRST0: EBIRST Position */
#define SYS_IPRST0_EBIRST_Msk (0x1ul << SYS_IPRST0_EBIRST_Pos) /*!< SYS_T::IPRST0: EBIRST Mask */
#define SYS_IPRST0_EMACRST_Pos (5) /*!< SYS_T::IPRST0: EMACRST Position */
#define SYS_IPRST0_EMACRST_Msk (0x1ul << SYS_IPRST0_EMACRST_Pos) /*!< SYS_T::IPRST0: EMACRST Mask */
#define SYS_IPRST0_SDH0RST_Pos (6) /*!< SYS_T::IPRST0: SDH0RST Position */
#define SYS_IPRST0_SDH0RST_Msk (0x1ul << SYS_IPRST0_SDH0RST_Pos) /*!< SYS_T::IPRST0: SDH0RST Mask */
#define SYS_IPRST0_CRCRST_Pos (7) /*!< SYS_T::IPRST0: CRCRST Position */
#define SYS_IPRST0_CRCRST_Msk (0x1ul << SYS_IPRST0_CRCRST_Pos) /*!< SYS_T::IPRST0: CRCRST Mask */
#define SYS_IPRST0_HSUSBDRST_Pos (10) /*!< SYS_T::IPRST0: HSUSBDRST Position */
#define SYS_IPRST0_HSUSBDRST_Msk (0x1ul << SYS_IPRST0_HSUSBDRST_Pos) /*!< SYS_T::IPRST0: HSUSBDRST Mask */
#define SYS_IPRST0_CRPTRST_Pos (12) /*!< SYS_T::IPRST0: CRPTRST Position */
#define SYS_IPRST0_CRPTRST_Msk (0x1ul << SYS_IPRST0_CRPTRST_Pos) /*!< SYS_T::IPRST0: CRPTRST Mask */
#define SYS_IPRST0_SPIMRST_Pos (14) /*!< SYS_T::IPRST0: SPIMRST Position */
#define SYS_IPRST0_SPIMRST_Msk (0x1ul << SYS_IPRST0_SPIMRST_Pos) /*!< SYS_T::IPRST0: SPIMRST Mask */
#define SYS_IPRST0_USBHRST_Pos (16) /*!< SYS_T::IPRST0: USBHRST Position */
#define SYS_IPRST0_USBHRST_Msk (0x1ul << SYS_IPRST0_USBHRST_Pos) /*!< SYS_T::IPRST0: USBHRST Mask */
#define SYS_IPRST0_SDH1RST_Pos (17) /*!< SYS_T::IPRST0: SDH1RST Position */
#define SYS_IPRST0_SDH1RST_Msk (0x1ul << SYS_IPRST0_SDH1RST_Pos) /*!< SYS_T::IPRST0: SDH1RST Mask */
#define SYS_IPRST1_GPIORST_Pos (1) /*!< SYS_T::IPRST1: GPIORST Position */
#define SYS_IPRST1_GPIORST_Msk (0x1ul << SYS_IPRST1_GPIORST_Pos) /*!< SYS_T::IPRST1: GPIORST Mask */
#define SYS_IPRST1_TMR0RST_Pos (2) /*!< SYS_T::IPRST1: TMR0RST Position */
#define SYS_IPRST1_TMR0RST_Msk (0x1ul << SYS_IPRST1_TMR0RST_Pos) /*!< SYS_T::IPRST1: TMR0RST Mask */
#define SYS_IPRST1_TMR1RST_Pos (3) /*!< SYS_T::IPRST1: TMR1RST Position */
#define SYS_IPRST1_TMR1RST_Msk (0x1ul << SYS_IPRST1_TMR1RST_Pos) /*!< SYS_T::IPRST1: TMR1RST Mask */
#define SYS_IPRST1_TMR2RST_Pos (4) /*!< SYS_T::IPRST1: TMR2RST Position */
#define SYS_IPRST1_TMR2RST_Msk (0x1ul << SYS_IPRST1_TMR2RST_Pos) /*!< SYS_T::IPRST1: TMR2RST Mask */
#define SYS_IPRST1_TMR3RST_Pos (5) /*!< SYS_T::IPRST1: TMR3RST Position */
#define SYS_IPRST1_TMR3RST_Msk (0x1ul << SYS_IPRST1_TMR3RST_Pos) /*!< SYS_T::IPRST1: TMR3RST Mask */
#define SYS_IPRST1_ACMP01RST_Pos (7) /*!< SYS_T::IPRST1: ACMP01RST Position */
#define SYS_IPRST1_ACMP01RST_Msk (0x1ul << SYS_IPRST1_ACMP01RST_Pos) /*!< SYS_T::IPRST1: ACMP01RST Mask */
#define SYS_IPRST1_I2C0RST_Pos (8) /*!< SYS_T::IPRST1: I2C0RST Position */
#define SYS_IPRST1_I2C0RST_Msk (0x1ul << SYS_IPRST1_I2C0RST_Pos) /*!< SYS_T::IPRST1: I2C0RST Mask */
#define SYS_IPRST1_I2C1RST_Pos (9) /*!< SYS_T::IPRST1: I2C1RST Position */
#define SYS_IPRST1_I2C1RST_Msk (0x1ul << SYS_IPRST1_I2C1RST_Pos) /*!< SYS_T::IPRST1: I2C1RST Mask */
#define SYS_IPRST1_I2C2RST_Pos (10) /*!< SYS_T::IPRST1: I2C2RST Position */
#define SYS_IPRST1_I2C2RST_Msk (0x1ul << SYS_IPRST1_I2C2RST_Pos) /*!< SYS_T::IPRST1: I2C2RST Mask */
#define SYS_IPRST1_SPI0RST_Pos (12) /*!< SYS_T::IPRST1: SPI0RST Position */
#define SYS_IPRST1_SPI0RST_Msk (0x1ul << SYS_IPRST1_SPI0RST_Pos) /*!< SYS_T::IPRST1: SPI0RST Mask */
#define SYS_IPRST1_SPI1RST_Pos (13) /*!< SYS_T::IPRST1: SPI1RST Position */
#define SYS_IPRST1_SPI1RST_Msk (0x1ul << SYS_IPRST1_SPI1RST_Pos) /*!< SYS_T::IPRST1: SPI1RST Mask */
#define SYS_IPRST1_SPI2RST_Pos (14) /*!< SYS_T::IPRST1: SPI2RST Position */
#define SYS_IPRST1_SPI2RST_Msk (0x1ul << SYS_IPRST1_SPI2RST_Pos) /*!< SYS_T::IPRST1: SPI2RST Mask */
#define SYS_IPRST1_SPI3RST_Pos (15) /*!< SYS_T::IPRST1: SPI3RST Position */
#define SYS_IPRST1_SPI3RST_Msk (0x1ul << SYS_IPRST1_SPI3RST_Pos) /*!< SYS_T::IPRST1: SPI3RST Mask */
#define SYS_IPRST1_UART0RST_Pos (16) /*!< SYS_T::IPRST1: UART0RST Position */
#define SYS_IPRST1_UART0RST_Msk (0x1ul << SYS_IPRST1_UART0RST_Pos) /*!< SYS_T::IPRST1: UART0RST Mask */
#define SYS_IPRST1_UART1RST_Pos (17) /*!< SYS_T::IPRST1: UART1RST Position */
#define SYS_IPRST1_UART1RST_Msk (0x1ul << SYS_IPRST1_UART1RST_Pos) /*!< SYS_T::IPRST1: UART1RST Mask */
#define SYS_IPRST1_UART2RST_Pos (18) /*!< SYS_T::IPRST1: UART2RST Position */
#define SYS_IPRST1_UART2RST_Msk (0x1ul << SYS_IPRST1_UART2RST_Pos) /*!< SYS_T::IPRST1: UART2RST Mask */
#define SYS_IPRST1_UART3RST_Pos (19) /*!< SYS_T::IPRST1: UART3RST Position */
#define SYS_IPRST1_UART3RST_Msk (0x1ul << SYS_IPRST1_UART3RST_Pos) /*!< SYS_T::IPRST1: UART3RST Mask */
#define SYS_IPRST1_UART4RST_Pos (20) /*!< SYS_T::IPRST1: UART4RST Position */
#define SYS_IPRST1_UART4RST_Msk (0x1ul << SYS_IPRST1_UART4RST_Pos) /*!< SYS_T::IPRST1: UART4RST Mask */
#define SYS_IPRST1_UART5RST_Pos (21) /*!< SYS_T::IPRST1: UART5RST Position */
#define SYS_IPRST1_UART5RST_Msk (0x1ul << SYS_IPRST1_UART5RST_Pos) /*!< SYS_T::IPRST1: UART5RST Mask */
#define SYS_IPRST1_CAN0RST_Pos (24) /*!< SYS_T::IPRST1: CAN0RST Position */
#define SYS_IPRST1_CAN0RST_Msk (0x1ul << SYS_IPRST1_CAN0RST_Pos) /*!< SYS_T::IPRST1: CAN0RST Mask */
#define SYS_IPRST1_CAN1RST_Pos (25) /*!< SYS_T::IPRST1: CAN1RST Position */
#define SYS_IPRST1_CAN1RST_Msk (0x1ul << SYS_IPRST1_CAN1RST_Pos) /*!< SYS_T::IPRST1: CAN1RST Mask */
#define SYS_IPRST1_USBDRST_Pos (27) /*!< SYS_T::IPRST1: USBDRST Position */
#define SYS_IPRST1_USBDRST_Msk (0x1ul << SYS_IPRST1_USBDRST_Pos) /*!< SYS_T::IPRST1: USBDRST Mask */
#define SYS_IPRST1_EADCRST_Pos (28) /*!< SYS_T::IPRST1: EADCRST Position */
#define SYS_IPRST1_EADCRST_Msk (0x1ul << SYS_IPRST1_EADCRST_Pos) /*!< SYS_T::IPRST1: EADCRST Mask */
#define SYS_IPRST1_I2S0RST_Pos (29) /*!< SYS_T::IPRST1: I2S0RST Position */
#define SYS_IPRST1_I2S0RST_Msk (0x1ul << SYS_IPRST1_I2S0RST_Pos) /*!< SYS_T::IPRST1: I2S0RST Mask */
#define SYS_IPRST2_SC0RST_Pos (0) /*!< SYS_T::IPRST2: SC0RST Position */
#define SYS_IPRST2_SC0RST_Msk (0x1ul << SYS_IPRST2_SC0RST_Pos) /*!< SYS_T::IPRST2: SC0RST Mask */
#define SYS_IPRST2_SC1RST_Pos (1) /*!< SYS_T::IPRST2: SC1RST Position */
#define SYS_IPRST2_SC1RST_Msk (0x1ul << SYS_IPRST2_SC1RST_Pos) /*!< SYS_T::IPRST2: SC1RST Mask */
#define SYS_IPRST2_SC2RST_Pos (2) /*!< SYS_T::IPRST2: SC2RST Position */
#define SYS_IPRST2_SC2RST_Msk (0x1ul << SYS_IPRST2_SC2RST_Pos) /*!< SYS_T::IPRST2: SC2RST Mask */
#define SYS_IPRST2_SPI4RST_Pos (6) /*!< SYS_T::IPRST2: SPI4RST Position */
#define SYS_IPRST2_SPI4RST_Msk (0x1ul << SYS_IPRST2_SPI4RST_Pos) /*!< SYS_T::IPRST2: SPI4RST Mask */
#define SYS_IPRST2_USCI0RST_Pos (8) /*!< SYS_T::IPRST2: USCI0RST Position */
#define SYS_IPRST2_USCI0RST_Msk (0x1ul << SYS_IPRST2_USCI0RST_Pos) /*!< SYS_T::IPRST2: USCI0RST Mask */
#define SYS_IPRST2_USCI1RST_Pos (9) /*!< SYS_T::IPRST2: USCI1RST Position */
#define SYS_IPRST2_USCI1RST_Msk (0x1ul << SYS_IPRST2_USCI1RST_Pos) /*!< SYS_T::IPRST2: USCI1RST Mask */
#define SYS_IPRST2_DACRST_Pos (12) /*!< SYS_T::IPRST2: DACRST Position */
#define SYS_IPRST2_DACRST_Msk (0x1ul << SYS_IPRST2_DACRST_Pos) /*!< SYS_T::IPRST2: DACRST Mask */
#define SYS_IPRST2_EPWM0RST_Pos (16) /*!< SYS_T::IPRST2: EPWM0RST Position */
#define SYS_IPRST2_EPWM0RST_Msk (0x1ul << SYS_IPRST2_EPWM0RST_Pos) /*!< SYS_T::IPRST2: EPWM0RST Mask */
#define SYS_IPRST2_EPWM1RST_Pos (17) /*!< SYS_T::IPRST2: EPWM1RST Position */
#define SYS_IPRST2_EPWM1RST_Msk (0x1ul << SYS_IPRST2_EPWM1RST_Pos) /*!< SYS_T::IPRST2: EPWM1RST Mask */
#define SYS_IPRST2_BPWM0RST_Pos (18) /*!< SYS_T::IPRST2: BPWM0RST Position */
#define SYS_IPRST2_BPWM0RST_Msk (0x1ul << SYS_IPRST2_BPWM0RST_Pos) /*!< SYS_T::IPRST2: BPWM0RST Mask */
#define SYS_IPRST2_BPWM1RST_Pos (19) /*!< SYS_T::IPRST2: BPWM1RST Position */
#define SYS_IPRST2_BPWM1RST_Msk (0x1ul << SYS_IPRST2_BPWM1RST_Pos) /*!< SYS_T::IPRST2: BPWM1RST Mask */
#define SYS_IPRST2_QEI0RST_Pos (22) /*!< SYS_T::IPRST2: QEI0RST Position */
#define SYS_IPRST2_QEI0RST_Msk (0x1ul << SYS_IPRST2_QEI0RST_Pos) /*!< SYS_T::IPRST2: QEI0RST Mask */
#define SYS_IPRST2_QEI1RST_Pos (23) /*!< SYS_T::IPRST2: QEI1RST Position */
#define SYS_IPRST2_QEI1RST_Msk (0x1ul << SYS_IPRST2_QEI1RST_Pos) /*!< SYS_T::IPRST2: QEI1RST Mask */
#define SYS_IPRST2_ECAP0RST_Pos (26) /*!< SYS_T::IPRST2: ECAP0RST Position */
#define SYS_IPRST2_ECAP0RST_Msk (0x1ul << SYS_IPRST2_ECAP0RST_Pos) /*!< SYS_T::IPRST2: ECAP0RST Mask */
#define SYS_IPRST2_ECAP1RST_Pos (27) /*!< SYS_T::IPRST2: ECAP1RST Position */
#define SYS_IPRST2_ECAP1RST_Msk (0x1ul << SYS_IPRST2_ECAP1RST_Pos) /*!< SYS_T::IPRST2: ECAP1RST Mask */
#define SYS_IPRST2_OPARST_Pos (30) /*!< SYS_T::IPRST2: OPARST Position */
#define SYS_IPRST2_OPARST_Msk (0x1ul << SYS_IPRST2_OPARST_Pos) /*!< SYS_T::IPRST2: OPARST Mask */
#define SYS_BODCTL_BODEN_Pos (0) /*!< SYS_T::BODCTL: BODEN Position */
#define SYS_BODCTL_BODEN_Msk (0x1ul << SYS_BODCTL_BODEN_Pos) /*!< SYS_T::BODCTL: BODEN Mask */
#define SYS_BODCTL_BODRSTEN_Pos (3) /*!< SYS_T::BODCTL: BODRSTEN Position */
#define SYS_BODCTL_BODRSTEN_Msk (0x1ul << SYS_BODCTL_BODRSTEN_Pos) /*!< SYS_T::BODCTL: BODRSTEN Mask */
#define SYS_BODCTL_BODIF_Pos (4) /*!< SYS_T::BODCTL: BODIF Position */
#define SYS_BODCTL_BODIF_Msk (0x1ul << SYS_BODCTL_BODIF_Pos) /*!< SYS_T::BODCTL: BODIF Mask */
#define SYS_BODCTL_BODLPM_Pos (5) /*!< SYS_T::BODCTL: BODLPM Position */
#define SYS_BODCTL_BODLPM_Msk (0x1ul << SYS_BODCTL_BODLPM_Pos) /*!< SYS_T::BODCTL: BODLPM Mask */
#define SYS_BODCTL_BODOUT_Pos (6) /*!< SYS_T::BODCTL: BODOUT Position */
#define SYS_BODCTL_BODOUT_Msk (0x1ul << SYS_BODCTL_BODOUT_Pos) /*!< SYS_T::BODCTL: BODOUT Mask */
#define SYS_BODCTL_LVREN_Pos (7) /*!< SYS_T::BODCTL: LVREN Position */
#define SYS_BODCTL_LVREN_Msk (0x1ul << SYS_BODCTL_LVREN_Pos) /*!< SYS_T::BODCTL: LVREN Mask */
#define SYS_BODCTL_BODDGSEL_Pos (8) /*!< SYS_T::BODCTL: BODDGSEL Position */
#define SYS_BODCTL_BODDGSEL_Msk (0x7ul << SYS_BODCTL_BODDGSEL_Pos) /*!< SYS_T::BODCTL: BODDGSEL Mask */
#define SYS_BODCTL_LVRDGSEL_Pos (12) /*!< SYS_T::BODCTL: LVRDGSEL Position */
#define SYS_BODCTL_LVRDGSEL_Msk (0x7ul << SYS_BODCTL_LVRDGSEL_Pos) /*!< SYS_T::BODCTL: LVRDGSEL Mask */
#define SYS_BODCTL_BODVL_Pos (16) /*!< SYS_T::BODCTL: BODVL Position */
#define SYS_BODCTL_BODVL_Msk (0x7ul << SYS_BODCTL_BODVL_Pos) /*!< SYS_T::BODCTL: BODVL Mask */
#define SYS_IVSCTL_VTEMPEN_Pos (0) /*!< SYS_T::IVSCTL: VTEMPEN Position */
#define SYS_IVSCTL_VTEMPEN_Msk (0x1ul << SYS_IVSCTL_VTEMPEN_Pos) /*!< SYS_T::IVSCTL: VTEMPEN Mask */
#define SYS_IVSCTL_VBATUGEN_Pos (1) /*!< SYS_T::IVSCTL: VBATUGEN Position */
#define SYS_IVSCTL_VBATUGEN_Msk (0x1ul << SYS_IVSCTL_VBATUGEN_Pos) /*!< SYS_T::IVSCTL: VBATUGEN Mask */
#define SYS_PORCTL_POROFF_Pos (0) /*!< SYS_T::PORCTL: POROFF Position */
#define SYS_PORCTL_POROFF_Msk (0xfffful << SYS_PORCTL_POROFF_Pos) /*!< SYS_T::PORCTL: POROFF Mask */
#define SYS_VREFCTL_VREFCTL_Pos (0) /*!< SYS_T::VREFCTL: VREFCTL Position */
#define SYS_VREFCTL_VREFCTL_Msk (0x1ful << SYS_VREFCTL_VREFCTL_Pos) /*!< SYS_T::VREFCTL: VREFCTL Mask */
#define SYS_VREFCTL_PRELOAD_SEL_Pos (6) /*!< SYS_T::VREFCTL: PRELOAD_SEL Position */
#define SYS_VREFCTL_PRELOAD_SEL_Msk (0x3ul << SYS_VREFCTL_PRELOAD_SEL_Pos) /*!< SYS_T::VREFCTL: PRELOAD_SEL Mask */
#define SYS_USBPHY_USBROLE_Pos (0) /*!< SYS_T::USBPHY: USBROLE Position */
#define SYS_USBPHY_USBROLE_Msk (0x3ul << SYS_USBPHY_USBROLE_Pos) /*!< SYS_T::USBPHY: USBROLE Mask */
#define SYS_USBPHY_SBO_Pos (2) /*!< SYS_T::USBPHY: SBO Position */
#define SYS_USBPHY_SBO_Msk (0x1ul << SYS_USBPHY_SBO_Pos) /*!< SYS_T::USBPHY: SBO Mask */
#define SYS_USBPHY_USBEN_Pos (8) /*!< SYS_T::USBPHY: USBEN Position */
#define SYS_USBPHY_USBEN_Msk (0x1ul << SYS_USBPHY_USBEN_Pos) /*!< SYS_T::USBPHY: USBEN Mask */
#define SYS_USBPHY_HSUSBROLE_Pos (16) /*!< SYS_T::USBPHY: HSUSBROLE Position */
#define SYS_USBPHY_HSUSBROLE_Msk (0x3ul << SYS_USBPHY_HSUSBROLE_Pos) /*!< SYS_T::USBPHY: HSUSBROLE Mask */
#define SYS_USBPHY_HSUSBEN_Pos (24) /*!< SYS_T::USBPHY: HSUSBEN Position */
#define SYS_USBPHY_HSUSBEN_Msk (0x1ul << SYS_USBPHY_HSUSBEN_Pos) /*!< SYS_T::USBPHY: HSUSBEN Mask */
#define SYS_USBPHY_HSUSBACT_Pos (25) /*!< SYS_T::USBPHY: HSUSBACT Position */
#define SYS_USBPHY_HSUSBACT_Msk (0x1ul << SYS_USBPHY_HSUSBACT_Pos) /*!< SYS_T::USBPHY: HSUSBACT Mask */
#define SYS_GPA_MFPL_PA0MFP_Pos (0) /*!< SYS_T::GPA_MFPL: PA0MFP Position */
#define SYS_GPA_MFPL_PA0MFP_Msk (0xful << SYS_GPA_MFPL_PA0MFP_Pos) /*!< SYS_T::GPA_MFPL: PA0MFP Mask */
#define SYS_GPA_MFPL_PA1MFP_Pos (4) /*!< SYS_T::GPA_MFPL: PA1MFP Position */
#define SYS_GPA_MFPL_PA1MFP_Msk (0xful << SYS_GPA_MFPL_PA1MFP_Pos) /*!< SYS_T::GPA_MFPL: PA1MFP Mask */
#define SYS_GPA_MFPL_PA2MFP_Pos (8) /*!< SYS_T::GPA_MFPL: PA2MFP Position */
#define SYS_GPA_MFPL_PA2MFP_Msk (0xful << SYS_GPA_MFPL_PA2MFP_Pos) /*!< SYS_T::GPA_MFPL: PA2MFP Mask */
#define SYS_GPA_MFPL_PA3MFP_Pos (12) /*!< SYS_T::GPA_MFPL: PA3MFP Position */
#define SYS_GPA_MFPL_PA3MFP_Msk (0xful << SYS_GPA_MFPL_PA3MFP_Pos) /*!< SYS_T::GPA_MFPL: PA3MFP Mask */
#define SYS_GPA_MFPL_PA4MFP_Pos (16) /*!< SYS_T::GPA_MFPL: PA4MFP Position */
#define SYS_GPA_MFPL_PA4MFP_Msk (0xful << SYS_GPA_MFPL_PA4MFP_Pos) /*!< SYS_T::GPA_MFPL: PA4MFP Mask */
#define SYS_GPA_MFPL_PA5MFP_Pos (20) /*!< SYS_T::GPA_MFPL: PA5MFP Position */
#define SYS_GPA_MFPL_PA5MFP_Msk (0xful << SYS_GPA_MFPL_PA5MFP_Pos) /*!< SYS_T::GPA_MFPL: PA5MFP Mask */
#define SYS_GPA_MFPL_PA6MFP_Pos (24) /*!< SYS_T::GPA_MFPL: PA6MFP Position */
#define SYS_GPA_MFPL_PA6MFP_Msk (0xful << SYS_GPA_MFPL_PA6MFP_Pos) /*!< SYS_T::GPA_MFPL: PA6MFP Mask */
#define SYS_GPA_MFPL_PA7MFP_Pos (28) /*!< SYS_T::GPA_MFPL: PA7MFP Position */
#define SYS_GPA_MFPL_PA7MFP_Msk (0xful << SYS_GPA_MFPL_PA7MFP_Pos) /*!< SYS_T::GPA_MFPL: PA7MFP Mask */
#define SYS_GPA_MFPH_PA8MFP_Pos (0) /*!< SYS_T::GPA_MFPH: PA8MFP Position */
#define SYS_GPA_MFPH_PA8MFP_Msk (0xful << SYS_GPA_MFPH_PA8MFP_Pos) /*!< SYS_T::GPA_MFPH: PA8MFP Mask */
#define SYS_GPA_MFPH_PA9MFP_Pos (4) /*!< SYS_T::GPA_MFPH: PA9MFP Position */
#define SYS_GPA_MFPH_PA9MFP_Msk (0xful << SYS_GPA_MFPH_PA9MFP_Pos) /*!< SYS_T::GPA_MFPH: PA9MFP Mask */
#define SYS_GPA_MFPH_PA10MFP_Pos (8) /*!< SYS_T::GPA_MFPH: PA10MFP Position */
#define SYS_GPA_MFPH_PA10MFP_Msk (0xful << SYS_GPA_MFPH_PA10MFP_Pos) /*!< SYS_T::GPA_MFPH: PA10MFP Mask */
#define SYS_GPA_MFPH_PA11MFP_Pos (12) /*!< SYS_T::GPA_MFPH: PA11MFP Position */
#define SYS_GPA_MFPH_PA11MFP_Msk (0xful << SYS_GPA_MFPH_PA11MFP_Pos) /*!< SYS_T::GPA_MFPH: PA11MFP Mask */
#define SYS_GPA_MFPH_PA12MFP_Pos (16) /*!< SYS_T::GPA_MFPH: PA12MFP Position */
#define SYS_GPA_MFPH_PA12MFP_Msk (0xful << SYS_GPA_MFPH_PA12MFP_Pos) /*!< SYS_T::GPA_MFPH: PA12MFP Mask */
#define SYS_GPA_MFPH_PA13MFP_Pos (20) /*!< SYS_T::GPA_MFPH: PA13MFP Position */
#define SYS_GPA_MFPH_PA13MFP_Msk (0xful << SYS_GPA_MFPH_PA13MFP_Pos) /*!< SYS_T::GPA_MFPH: PA13MFP Mask */
#define SYS_GPA_MFPH_PA14MFP_Pos (24) /*!< SYS_T::GPA_MFPH: PA14MFP Position */
#define SYS_GPA_MFPH_PA14MFP_Msk (0xful << SYS_GPA_MFPH_PA14MFP_Pos) /*!< SYS_T::GPA_MFPH: PA14MFP Mask */
#define SYS_GPA_MFPH_PA15MFP_Pos (28) /*!< SYS_T::GPA_MFPH: PA15MFP Position */
#define SYS_GPA_MFPH_PA15MFP_Msk (0xful << SYS_GPA_MFPH_PA15MFP_Pos) /*!< SYS_T::GPA_MFPH: PA15MFP Mask */
#define SYS_GPB_MFPL_PB0MFP_Pos (0) /*!< SYS_T::GPB_MFPL: PB0MFP Position */
#define SYS_GPB_MFPL_PB0MFP_Msk (0xful << SYS_GPB_MFPL_PB0MFP_Pos) /*!< SYS_T::GPB_MFPL: PB0MFP Mask */
#define SYS_GPB_MFPL_PB1MFP_Pos (4) /*!< SYS_T::GPB_MFPL: PB1MFP Position */
#define SYS_GPB_MFPL_PB1MFP_Msk (0xful << SYS_GPB_MFPL_PB1MFP_Pos) /*!< SYS_T::GPB_MFPL: PB1MFP Mask */
#define SYS_GPB_MFPL_PB2MFP_Pos (8) /*!< SYS_T::GPB_MFPL: PB2MFP Position */
#define SYS_GPB_MFPL_PB2MFP_Msk (0xful << SYS_GPB_MFPL_PB2MFP_Pos) /*!< SYS_T::GPB_MFPL: PB2MFP Mask */
#define SYS_GPB_MFPL_PB3MFP_Pos (12) /*!< SYS_T::GPB_MFPL: PB3MFP Position */
#define SYS_GPB_MFPL_PB3MFP_Msk (0xful << SYS_GPB_MFPL_PB3MFP_Pos) /*!< SYS_T::GPB_MFPL: PB3MFP Mask */
#define SYS_GPB_MFPL_PB4MFP_Pos (16) /*!< SYS_T::GPB_MFPL: PB4MFP Position */
#define SYS_GPB_MFPL_PB4MFP_Msk (0xful << SYS_GPB_MFPL_PB4MFP_Pos) /*!< SYS_T::GPB_MFPL: PB4MFP Mask */
#define SYS_GPB_MFPL_PB5MFP_Pos (20) /*!< SYS_T::GPB_MFPL: PB5MFP Position */
#define SYS_GPB_MFPL_PB5MFP_Msk (0xful << SYS_GPB_MFPL_PB5MFP_Pos) /*!< SYS_T::GPB_MFPL: PB5MFP Mask */
#define SYS_GPB_MFPL_PB6MFP_Pos (24) /*!< SYS_T::GPB_MFPL: PB6MFP Position */
#define SYS_GPB_MFPL_PB6MFP_Msk (0xful << SYS_GPB_MFPL_PB6MFP_Pos) /*!< SYS_T::GPB_MFPL: PB6MFP Mask */
#define SYS_GPB_MFPL_PB7MFP_Pos (28) /*!< SYS_T::GPB_MFPL: PB7MFP Position */
#define SYS_GPB_MFPL_PB7MFP_Msk (0xful << SYS_GPB_MFPL_PB7MFP_Pos) /*!< SYS_T::GPB_MFPL: PB7MFP Mask */
#define SYS_GPB_MFPH_PB8MFP_Pos (0) /*!< SYS_T::GPB_MFPH: PB8MFP Position */
#define SYS_GPB_MFPH_PB8MFP_Msk (0xful << SYS_GPB_MFPH_PB8MFP_Pos) /*!< SYS_T::GPB_MFPH: PB8MFP Mask */
#define SYS_GPB_MFPH_PB9MFP_Pos (4) /*!< SYS_T::GPB_MFPH: PB9MFP Position */
#define SYS_GPB_MFPH_PB9MFP_Msk (0xful << SYS_GPB_MFPH_PB9MFP_Pos) /*!< SYS_T::GPB_MFPH: PB9MFP Mask */
#define SYS_GPB_MFPH_PB10MFP_Pos (8) /*!< SYS_T::GPB_MFPH: PB10MFP Position */
#define SYS_GPB_MFPH_PB10MFP_Msk (0xful << SYS_GPB_MFPH_PB10MFP_Pos) /*!< SYS_T::GPB_MFPH: PB10MFP Mask */
#define SYS_GPB_MFPH_PB11MFP_Pos (12) /*!< SYS_T::GPB_MFPH: PB11MFP Position */
#define SYS_GPB_MFPH_PB11MFP_Msk (0xful << SYS_GPB_MFPH_PB11MFP_Pos) /*!< SYS_T::GPB_MFPH: PB11MFP Mask */
#define SYS_GPB_MFPH_PB12MFP_Pos (16) /*!< SYS_T::GPB_MFPH: PB12MFP Position */
#define SYS_GPB_MFPH_PB12MFP_Msk (0xful << SYS_GPB_MFPH_PB12MFP_Pos) /*!< SYS_T::GPB_MFPH: PB12MFP Mask */
#define SYS_GPB_MFPH_PB13MFP_Pos (20) /*!< SYS_T::GPB_MFPH: PB13MFP Position */
#define SYS_GPB_MFPH_PB13MFP_Msk (0xful << SYS_GPB_MFPH_PB13MFP_Pos) /*!< SYS_T::GPB_MFPH: PB13MFP Mask */
#define SYS_GPB_MFPH_PB14MFP_Pos (24) /*!< SYS_T::GPB_MFPH: PB14MFP Position */
#define SYS_GPB_MFPH_PB14MFP_Msk (0xful << SYS_GPB_MFPH_PB14MFP_Pos) /*!< SYS_T::GPB_MFPH: PB14MFP Mask */
#define SYS_GPB_MFPH_PB15MFP_Pos (28) /*!< SYS_T::GPB_MFPH: PB15MFP Position */
#define SYS_GPB_MFPH_PB15MFP_Msk (0xful << SYS_GPB_MFPH_PB15MFP_Pos) /*!< SYS_T::GPB_MFPH: PB15MFP Mask */
#define SYS_GPC_MFPL_PC0MFP_Pos (0) /*!< SYS_T::GPC_MFPL: PC0MFP Position */
#define SYS_GPC_MFPL_PC0MFP_Msk (0xful << SYS_GPC_MFPL_PC0MFP_Pos) /*!< SYS_T::GPC_MFPL: PC0MFP Mask */
#define SYS_GPC_MFPL_PC1MFP_Pos (4) /*!< SYS_T::GPC_MFPL: PC1MFP Position */
#define SYS_GPC_MFPL_PC1MFP_Msk (0xful << SYS_GPC_MFPL_PC1MFP_Pos) /*!< SYS_T::GPC_MFPL: PC1MFP Mask */
#define SYS_GPC_MFPL_PC2MFP_Pos (8) /*!< SYS_T::GPC_MFPL: PC2MFP Position */
#define SYS_GPC_MFPL_PC2MFP_Msk (0xful << SYS_GPC_MFPL_PC2MFP_Pos) /*!< SYS_T::GPC_MFPL: PC2MFP Mask */
#define SYS_GPC_MFPL_PC3MFP_Pos (12) /*!< SYS_T::GPC_MFPL: PC3MFP Position */
#define SYS_GPC_MFPL_PC3MFP_Msk (0xful << SYS_GPC_MFPL_PC3MFP_Pos) /*!< SYS_T::GPC_MFPL: PC3MFP Mask */
#define SYS_GPC_MFPL_PC4MFP_Pos (16) /*!< SYS_T::GPC_MFPL: PC4MFP Position */
#define SYS_GPC_MFPL_PC4MFP_Msk (0xful << SYS_GPC_MFPL_PC4MFP_Pos) /*!< SYS_T::GPC_MFPL: PC4MFP Mask */
#define SYS_GPC_MFPL_PC5MFP_Pos (20) /*!< SYS_T::GPC_MFPL: PC5MFP Position */
#define SYS_GPC_MFPL_PC5MFP_Msk (0xful << SYS_GPC_MFPL_PC5MFP_Pos) /*!< SYS_T::GPC_MFPL: PC5MFP Mask */
#define SYS_GPC_MFPL_PC6MFP_Pos (24) /*!< SYS_T::GPC_MFPL: PC6MFP Position */
#define SYS_GPC_MFPL_PC6MFP_Msk (0xful << SYS_GPC_MFPL_PC6MFP_Pos) /*!< SYS_T::GPC_MFPL: PC6MFP Mask */
#define SYS_GPC_MFPL_PC7MFP_Pos (28) /*!< SYS_T::GPC_MFPL: PC7MFP Position */
#define SYS_GPC_MFPL_PC7MFP_Msk (0xful << SYS_GPC_MFPL_PC7MFP_Pos) /*!< SYS_T::GPC_MFPL: PC7MFP Mask */
#define SYS_GPC_MFPH_PC8MFP_Pos (0) /*!< SYS_T::GPC_MFPH: PC8MFP Position */
#define SYS_GPC_MFPH_PC8MFP_Msk (0xful << SYS_GPC_MFPH_PC8MFP_Pos) /*!< SYS_T::GPC_MFPH: PC8MFP Mask */
#define SYS_GPC_MFPH_PC9MFP_Pos (4) /*!< SYS_T::GPC_MFPH: PC9MFP Position */
#define SYS_GPC_MFPH_PC9MFP_Msk (0xful << SYS_GPC_MFPH_PC9MFP_Pos) /*!< SYS_T::GPC_MFPH: PC9MFP Mask */
#define SYS_GPC_MFPH_PC10MFP_Pos (8) /*!< SYS_T::GPC_MFPH: PC10MFP Position */
#define SYS_GPC_MFPH_PC10MFP_Msk (0xful << SYS_GPC_MFPH_PC10MFP_Pos) /*!< SYS_T::GPC_MFPH: PC10MFP Mask */
#define SYS_GPC_MFPH_PC11MFP_Pos (12) /*!< SYS_T::GPC_MFPH: PC11MFP Position */
#define SYS_GPC_MFPH_PC11MFP_Msk (0xful << SYS_GPC_MFPH_PC11MFP_Pos) /*!< SYS_T::GPC_MFPH: PC11MFP Mask */
#define SYS_GPC_MFPH_PC12MFP_Pos (16) /*!< SYS_T::GPC_MFPH: PC12MFP Position */
#define SYS_GPC_MFPH_PC12MFP_Msk (0xful << SYS_GPC_MFPH_PC12MFP_Pos) /*!< SYS_T::GPC_MFPH: PC12MFP Mask */
#define SYS_GPC_MFPH_PC13MFP_Pos (20) /*!< SYS_T::GPC_MFPH: PC13MFP Position */
#define SYS_GPC_MFPH_PC13MFP_Msk (0xful << SYS_GPC_MFPH_PC13MFP_Pos) /*!< SYS_T::GPC_MFPH: PC13MFP Mask */
#define SYS_GPC_MFPH_PC14MFP_Pos (24) /*!< SYS_T::GPC_MFPH: PC14MFP Position */
#define SYS_GPC_MFPH_PC14MFP_Msk (0xful << SYS_GPC_MFPH_PC14MFP_Pos) /*!< SYS_T::GPC_MFPH: PC14MFP Mask */
#define SYS_GPC_MFPH_PC15MFP_Pos (28) /*!< SYS_T::GPC_MFPH: PC15MFP Position */
#define SYS_GPC_MFPH_PC15MFP_Msk (0xful << SYS_GPC_MFPH_PC15MFP_Pos) /*!< SYS_T::GPC_MFPH: PC15MFP Mask */
#define SYS_GPD_MFPL_PD0MFP_Pos (0) /*!< SYS_T::GPD_MFPL: PD0MFP Position */
#define SYS_GPD_MFPL_PD0MFP_Msk (0xful << SYS_GPD_MFPL_PD0MFP_Pos) /*!< SYS_T::GPD_MFPL: PD0MFP Mask */
#define SYS_GPD_MFPL_PD1MFP_Pos (4) /*!< SYS_T::GPD_MFPL: PD1MFP Position */
#define SYS_GPD_MFPL_PD1MFP_Msk (0xful << SYS_GPD_MFPL_PD1MFP_Pos) /*!< SYS_T::GPD_MFPL: PD1MFP Mask */
#define SYS_GPD_MFPL_PD2MFP_Pos (8) /*!< SYS_T::GPD_MFPL: PD2MFP Position */
#define SYS_GPD_MFPL_PD2MFP_Msk (0xful << SYS_GPD_MFPL_PD2MFP_Pos) /*!< SYS_T::GPD_MFPL: PD2MFP Mask */
#define SYS_GPD_MFPL_PD3MFP_Pos (12) /*!< SYS_T::GPD_MFPL: PD3MFP Position */
#define SYS_GPD_MFPL_PD3MFP_Msk (0xful << SYS_GPD_MFPL_PD3MFP_Pos) /*!< SYS_T::GPD_MFPL: PD3MFP Mask */
#define SYS_GPD_MFPL_PD4MFP_Pos (16) /*!< SYS_T::GPD_MFPL: PD4MFP Position */
#define SYS_GPD_MFPL_PD4MFP_Msk (0xful << SYS_GPD_MFPL_PD4MFP_Pos) /*!< SYS_T::GPD_MFPL: PD4MFP Mask */
#define SYS_GPD_MFPL_PD5MFP_Pos (20) /*!< SYS_T::GPD_MFPL: PD5MFP Position */
#define SYS_GPD_MFPL_PD5MFP_Msk (0xful << SYS_GPD_MFPL_PD5MFP_Pos) /*!< SYS_T::GPD_MFPL: PD5MFP Mask */
#define SYS_GPD_MFPL_PD6MFP_Pos (24) /*!< SYS_T::GPD_MFPL: PD6MFP Position */
#define SYS_GPD_MFPL_PD6MFP_Msk (0xful << SYS_GPD_MFPL_PD6MFP_Pos) /*!< SYS_T::GPD_MFPL: PD6MFP Mask */
#define SYS_GPD_MFPL_PD7MFP_Pos (28) /*!< SYS_T::GPD_MFPL: PD7MFP Position */
#define SYS_GPD_MFPL_PD7MFP_Msk (0xful << SYS_GPD_MFPL_PD7MFP_Pos) /*!< SYS_T::GPD_MFPL: PD7MFP Mask */
#define SYS_GPD_MFPH_PD8MFP_Pos (0) /*!< SYS_T::GPD_MFPH: PD8MFP Position */
#define SYS_GPD_MFPH_PD8MFP_Msk (0xful << SYS_GPD_MFPH_PD8MFP_Pos) /*!< SYS_T::GPD_MFPH: PD8MFP Mask */
#define SYS_GPD_MFPH_PD9MFP_Pos (4) /*!< SYS_T::GPD_MFPH: PD9MFP Position */
#define SYS_GPD_MFPH_PD9MFP_Msk (0xful << SYS_GPD_MFPH_PD9MFP_Pos) /*!< SYS_T::GPD_MFPH: PD9MFP Mask */
#define SYS_GPD_MFPH_PD10MFP_Pos (8) /*!< SYS_T::GPD_MFPH: PD10MFP Position */
#define SYS_GPD_MFPH_PD10MFP_Msk (0xful << SYS_GPD_MFPH_PD10MFP_Pos) /*!< SYS_T::GPD_MFPH: PD10MFP Mask */
#define SYS_GPD_MFPH_PD11MFP_Pos (12) /*!< SYS_T::GPD_MFPH: PD11MFP Position */
#define SYS_GPD_MFPH_PD11MFP_Msk (0xful << SYS_GPD_MFPH_PD11MFP_Pos) /*!< SYS_T::GPD_MFPH: PD11MFP Mask */
#define SYS_GPD_MFPH_PD12MFP_Pos (16) /*!< SYS_T::GPD_MFPH: PD12MFP Position */
#define SYS_GPD_MFPH_PD12MFP_Msk (0xful << SYS_GPD_MFPH_PD12MFP_Pos) /*!< SYS_T::GPD_MFPH: PD12MFP Mask */
#define SYS_GPD_MFPH_PD13MFP_Pos (20) /*!< SYS_T::GPD_MFPH: PD13MFP Position */
#define SYS_GPD_MFPH_PD13MFP_Msk (0xful << SYS_GPD_MFPH_PD13MFP_Pos) /*!< SYS_T::GPD_MFPH: PD13MFP Mask */
#define SYS_GPD_MFPH_PD14MFP_Pos (24) /*!< SYS_T::GPD_MFPH: PD14MFP Position */
#define SYS_GPD_MFPH_PD14MFP_Msk (0xful << SYS_GPD_MFPH_PD14MFP_Pos) /*!< SYS_T::GPD_MFPH: PD14MFP Mask */
#define SYS_GPD_MFPH_PD15MFP_Pos (28) /*!< SYS_T::GPD_MFPH: PD15MFP Position */
#define SYS_GPD_MFPH_PD15MFP_Msk (0xful << SYS_GPD_MFPH_PD15MFP_Pos) /*!< SYS_T::GPD_MFPH: PD15MFP Mask */
#define SYS_GPE_MFPL_PE0MFP_Pos (0) /*!< SYS_T::GPE_MFPL: PE0MFP Position */
#define SYS_GPE_MFPL_PE0MFP_Msk (0xful << SYS_GPE_MFPL_PE0MFP_Pos) /*!< SYS_T::GPE_MFPL: PE0MFP Mask */
#define SYS_GPE_MFPL_PE1MFP_Pos (4) /*!< SYS_T::GPE_MFPL: PE1MFP Position */
#define SYS_GPE_MFPL_PE1MFP_Msk (0xful << SYS_GPE_MFPL_PE1MFP_Pos) /*!< SYS_T::GPE_MFPL: PE1MFP Mask */
#define SYS_GPE_MFPL_PE2MFP_Pos (8) /*!< SYS_T::GPE_MFPL: PE2MFP Position */
#define SYS_GPE_MFPL_PE2MFP_Msk (0xful << SYS_GPE_MFPL_PE2MFP_Pos) /*!< SYS_T::GPE_MFPL: PE2MFP Mask */
#define SYS_GPE_MFPL_PE3MFP_Pos (12) /*!< SYS_T::GPE_MFPL: PE3MFP Position */
#define SYS_GPE_MFPL_PE3MFP_Msk (0xful << SYS_GPE_MFPL_PE3MFP_Pos) /*!< SYS_T::GPE_MFPL: PE3MFP Mask */
#define SYS_GPE_MFPL_PE4MFP_Pos (16) /*!< SYS_T::GPE_MFPL: PE4MFP Position */
#define SYS_GPE_MFPL_PE4MFP_Msk (0xful << SYS_GPE_MFPL_PE4MFP_Pos) /*!< SYS_T::GPE_MFPL: PE4MFP Mask */
#define SYS_GPE_MFPL_PE5MFP_Pos (20) /*!< SYS_T::GPE_MFPL: PE5MFP Position */
#define SYS_GPE_MFPL_PE5MFP_Msk (0xful << SYS_GPE_MFPL_PE5MFP_Pos) /*!< SYS_T::GPE_MFPL: PE5MFP Mask */
#define SYS_GPE_MFPL_PE6MFP_Pos (24) /*!< SYS_T::GPE_MFPL: PE6MFP Position */
#define SYS_GPE_MFPL_PE6MFP_Msk (0xful << SYS_GPE_MFPL_PE6MFP_Pos) /*!< SYS_T::GPE_MFPL: PE6MFP Mask */
#define SYS_GPE_MFPL_PE7MFP_Pos (28) /*!< SYS_T::GPE_MFPL: PE7MFP Position */
#define SYS_GPE_MFPL_PE7MFP_Msk (0xful << SYS_GPE_MFPL_PE7MFP_Pos) /*!< SYS_T::GPE_MFPL: PE7MFP Mask */
#define SYS_GPE_MFPH_PE8MFP_Pos (0) /*!< SYS_T::GPE_MFPH: PE8MFP Position */
#define SYS_GPE_MFPH_PE8MFP_Msk (0xful << SYS_GPE_MFPH_PE8MFP_Pos) /*!< SYS_T::GPE_MFPH: PE8MFP Mask */
#define SYS_GPE_MFPH_PE9MFP_Pos (4) /*!< SYS_T::GPE_MFPH: PE9MFP Position */
#define SYS_GPE_MFPH_PE9MFP_Msk (0xful << SYS_GPE_MFPH_PE9MFP_Pos) /*!< SYS_T::GPE_MFPH: PE9MFP Mask */
#define SYS_GPE_MFPH_PE10MFP_Pos (8) /*!< SYS_T::GPE_MFPH: PE10MFP Position */
#define SYS_GPE_MFPH_PE10MFP_Msk (0xful << SYS_GPE_MFPH_PE10MFP_Pos) /*!< SYS_T::GPE_MFPH: PE10MFP Mask */
#define SYS_GPE_MFPH_PE11MFP_Pos (12) /*!< SYS_T::GPE_MFPH: PE11MFP Position */
#define SYS_GPE_MFPH_PE11MFP_Msk (0xful << SYS_GPE_MFPH_PE11MFP_Pos) /*!< SYS_T::GPE_MFPH: PE11MFP Mask */
#define SYS_GPE_MFPH_PE12MFP_Pos (16) /*!< SYS_T::GPE_MFPH: PE12MFP Position */
#define SYS_GPE_MFPH_PE12MFP_Msk (0xful << SYS_GPE_MFPH_PE12MFP_Pos) /*!< SYS_T::GPE_MFPH: PE12MFP Mask */
#define SYS_GPE_MFPH_PE13MFP_Pos (20) /*!< SYS_T::GPE_MFPH: PE13MFP Position */
#define SYS_GPE_MFPH_PE13MFP_Msk (0xful << SYS_GPE_MFPH_PE13MFP_Pos) /*!< SYS_T::GPE_MFPH: PE13MFP Mask */
#define SYS_GPE_MFPH_PE14MFP_Pos (24) /*!< SYS_T::GPE_MFPH: PE14MFP Position */
#define SYS_GPE_MFPH_PE14MFP_Msk (0xful << SYS_GPE_MFPH_PE14MFP_Pos) /*!< SYS_T::GPE_MFPH: PE14MFP Mask */
#define SYS_GPE_MFPH_PE15MFP_Pos (28) /*!< SYS_T::GPE_MFPH: PE15MFP Position */
#define SYS_GPE_MFPH_PE15MFP_Msk (0xful << SYS_GPE_MFPH_PE15MFP_Pos) /*!< SYS_T::GPE_MFPH: PE15MFP Mask */
#define SYS_GPF_MFPL_PF0MFP_Pos (0) /*!< SYS_T::GPF_MFPL: PF0MFP Position */
#define SYS_GPF_MFPL_PF0MFP_Msk (0xful << SYS_GPF_MFPL_PF0MFP_Pos) /*!< SYS_T::GPF_MFPL: PF0MFP Mask */
#define SYS_GPF_MFPL_PF1MFP_Pos (4) /*!< SYS_T::GPF_MFPL: PF1MFP Position */
#define SYS_GPF_MFPL_PF1MFP_Msk (0xful << SYS_GPF_MFPL_PF1MFP_Pos) /*!< SYS_T::GPF_MFPL: PF1MFP Mask */
#define SYS_GPF_MFPL_PF2MFP_Pos (8) /*!< SYS_T::GPF_MFPL: PF2MFP Position */
#define SYS_GPF_MFPL_PF2MFP_Msk (0xful << SYS_GPF_MFPL_PF2MFP_Pos) /*!< SYS_T::GPF_MFPL: PF2MFP Mask */
#define SYS_GPF_MFPL_PF3MFP_Pos (12) /*!< SYS_T::GPF_MFPL: PF3MFP Position */
#define SYS_GPF_MFPL_PF3MFP_Msk (0xful << SYS_GPF_MFPL_PF3MFP_Pos) /*!< SYS_T::GPF_MFPL: PF3MFP Mask */
#define SYS_GPF_MFPL_PF4MFP_Pos (16) /*!< SYS_T::GPF_MFPL: PF4MFP Position */
#define SYS_GPF_MFPL_PF4MFP_Msk (0xful << SYS_GPF_MFPL_PF4MFP_Pos) /*!< SYS_T::GPF_MFPL: PF4MFP Mask */
#define SYS_GPF_MFPL_PF5MFP_Pos (20) /*!< SYS_T::GPF_MFPL: PF5MFP Position */
#define SYS_GPF_MFPL_PF5MFP_Msk (0xful << SYS_GPF_MFPL_PF5MFP_Pos) /*!< SYS_T::GPF_MFPL: PF5MFP Mask */
#define SYS_GPF_MFPL_PF6MFP_Pos (24) /*!< SYS_T::GPF_MFPL: PF6MFP Position */
#define SYS_GPF_MFPL_PF6MFP_Msk (0xful << SYS_GPF_MFPL_PF6MFP_Pos) /*!< SYS_T::GPF_MFPL: PF6MFP Mask */
#define SYS_GPF_MFPL_PF7MFP_Pos (28) /*!< SYS_T::GPF_MFPL: PF7MFP Position */
#define SYS_GPF_MFPL_PF7MFP_Msk (0xful << SYS_GPF_MFPL_PF7MFP_Pos) /*!< SYS_T::GPF_MFPL: PF7MFP Mask */
#define SYS_GPF_MFPH_PF8MFP_Pos (0) /*!< SYS_T::GPF_MFPH: PF8MFP Position */
#define SYS_GPF_MFPH_PF8MFP_Msk (0xful << SYS_GPF_MFPH_PF8MFP_Pos) /*!< SYS_T::GPF_MFPH: PF8MFP Mask */
#define SYS_GPF_MFPH_PF9MFP_Pos (4) /*!< SYS_T::GPF_MFPH: PF9MFP Position */
#define SYS_GPF_MFPH_PF9MFP_Msk (0xful << SYS_GPF_MFPH_PF9MFP_Pos) /*!< SYS_T::GPF_MFPH: PF9MFP Mask */
#define SYS_GPF_MFPH_PF10MFP_Pos (8) /*!< SYS_T::GPF_MFPH: PF10MFP Position */
#define SYS_GPF_MFPH_PF10MFP_Msk (0xful << SYS_GPF_MFPH_PF10MFP_Pos) /*!< SYS_T::GPF_MFPH: PF10MFP Mask */
#define SYS_GPF_MFPH_PF11MFP_Pos (12) /*!< SYS_T::GPF_MFPH: PF11MFP Position */
#define SYS_GPF_MFPH_PF11MFP_Msk (0xful << SYS_GPF_MFPH_PF11MFP_Pos) /*!< SYS_T::GPF_MFPH: PF11MFP Mask */
#define SYS_GPF_MFPH_PF12MFP_Pos (16) /*!< SYS_T::GPF_MFPH: PF12MFP Position */
#define SYS_GPF_MFPH_PF12MFP_Msk (0xful << SYS_GPF_MFPH_PF12MFP_Pos) /*!< SYS_T::GPF_MFPH: PF12MFP Mask */
#define SYS_GPF_MFPH_PF13MFP_Pos (20) /*!< SYS_T::GPF_MFPH: PF13MFP Position */
#define SYS_GPF_MFPH_PF13MFP_Msk (0xful << SYS_GPF_MFPH_PF13MFP_Pos) /*!< SYS_T::GPF_MFPH: PF13MFP Mask */
#define SYS_GPF_MFPH_PF14MFP_Pos (24) /*!< SYS_T::GPF_MFPH: PF14MFP Position */
#define SYS_GPF_MFPH_PF14MFP_Msk (0xful << SYS_GPF_MFPH_PF14MFP_Pos) /*!< SYS_T::GPF_MFPH: PF14MFP Mask */
#define SYS_GPF_MFPH_PF15MFP_Pos (28) /*!< SYS_T::GPF_MFPH: PF15MFP Position */
#define SYS_GPF_MFPH_PF15MFP_Msk (0xful << SYS_GPF_MFPH_PF15MFP_Pos) /*!< SYS_T::GPF_MFPH: PF15MFP Mask */
#define SYS_GPG_MFPL_PG0MFP_Pos (0) /*!< SYS_T::GPG_MFPL: PG0MFP Position */
#define SYS_GPG_MFPL_PG0MFP_Msk (0xful << SYS_GPG_MFPL_PG0MFP_Pos) /*!< SYS_T::GPG_MFPL: PG0MFP Mask */
#define SYS_GPG_MFPL_PG1MFP_Pos (4) /*!< SYS_T::GPG_MFPL: PG1MFP Position */
#define SYS_GPG_MFPL_PG1MFP_Msk (0xful << SYS_GPG_MFPL_PG1MFP_Pos) /*!< SYS_T::GPG_MFPL: PG1MFP Mask */
#define SYS_GPG_MFPL_PG2MFP_Pos (8) /*!< SYS_T::GPG_MFPL: PG2MFP Position */
#define SYS_GPG_MFPL_PG2MFP_Msk (0xful << SYS_GPG_MFPL_PG2MFP_Pos) /*!< SYS_T::GPG_MFPL: PG2MFP Mask */
#define SYS_GPG_MFPL_PG3MFP_Pos (12) /*!< SYS_T::GPG_MFPL: PG3MFP Position */
#define SYS_GPG_MFPL_PG3MFP_Msk (0xful << SYS_GPG_MFPL_PG3MFP_Pos) /*!< SYS_T::GPG_MFPL: PG3MFP Mask */
#define SYS_GPG_MFPL_PG4MFP_Pos (16) /*!< SYS_T::GPG_MFPL: PG4MFP Position */
#define SYS_GPG_MFPL_PG4MFP_Msk (0xful << SYS_GPG_MFPL_PG4MFP_Pos) /*!< SYS_T::GPG_MFPL: PG4MFP Mask */
#define SYS_GPG_MFPL_PG5MFP_Pos (20) /*!< SYS_T::GPG_MFPL: PG5MFP Position */
#define SYS_GPG_MFPL_PG5MFP_Msk (0xful << SYS_GPG_MFPL_PG5MFP_Pos) /*!< SYS_T::GPG_MFPL: PG5MFP Mask */
#define SYS_GPG_MFPL_PG6MFP_Pos (24) /*!< SYS_T::GPG_MFPL: PG6MFP Position */
#define SYS_GPG_MFPL_PG6MFP_Msk (0xful << SYS_GPG_MFPL_PG6MFP_Pos) /*!< SYS_T::GPG_MFPL: PG6MFP Mask */
#define SYS_GPG_MFPL_PG7MFP_Pos (28) /*!< SYS_T::GPG_MFPL: PG7MFP Position */
#define SYS_GPG_MFPL_PG7MFP_Msk (0xful << SYS_GPG_MFPL_PG7MFP_Pos) /*!< SYS_T::GPG_MFPL: PG7MFP Mask */
#define SYS_GPG_MFPH_PG8MFP_Pos (0) /*!< SYS_T::GPG_MFPH: PG8MFP Position */
#define SYS_GPG_MFPH_PG8MFP_Msk (0xful << SYS_GPG_MFPH_PG8MFP_Pos) /*!< SYS_T::GPG_MFPH: PG8MFP Mask */
#define SYS_GPG_MFPH_PG9MFP_Pos (4) /*!< SYS_T::GPG_MFPH: PG9MFP Position */
#define SYS_GPG_MFPH_PG9MFP_Msk (0xful << SYS_GPG_MFPH_PG9MFP_Pos) /*!< SYS_T::GPG_MFPH: PG9MFP Mask */
#define SYS_GPG_MFPH_PG10MFP_Pos (8) /*!< SYS_T::GPG_MFPH: PG10MFP Position */
#define SYS_GPG_MFPH_PG10MFP_Msk (0xful << SYS_GPG_MFPH_PG10MFP_Pos) /*!< SYS_T::GPG_MFPH: PG10MFP Mask */
#define SYS_GPG_MFPH_PG11MFP_Pos (12) /*!< SYS_T::GPG_MFPH: PG11MFP Position */
#define SYS_GPG_MFPH_PG11MFP_Msk (0xful << SYS_GPG_MFPH_PG11MFP_Pos) /*!< SYS_T::GPG_MFPH: PG11MFP Mask */
#define SYS_GPG_MFPH_PG12MFP_Pos (16) /*!< SYS_T::GPG_MFPH: PG12MFP Position */
#define SYS_GPG_MFPH_PG12MFP_Msk (0xful << SYS_GPG_MFPH_PG12MFP_Pos) /*!< SYS_T::GPG_MFPH: PG12MFP Mask */
#define SYS_GPG_MFPH_PG13MFP_Pos (20) /*!< SYS_T::GPG_MFPH: PG13MFP Position */
#define SYS_GPG_MFPH_PG13MFP_Msk (0xful << SYS_GPG_MFPH_PG13MFP_Pos) /*!< SYS_T::GPG_MFPH: PG13MFP Mask */
#define SYS_GPG_MFPH_PG14MFP_Pos (24) /*!< SYS_T::GPG_MFPH: PG14MFP Position */
#define SYS_GPG_MFPH_PG14MFP_Msk (0xful << SYS_GPG_MFPH_PG14MFP_Pos) /*!< SYS_T::GPG_MFPH: PG14MFP Mask */
#define SYS_GPG_MFPH_PG15MFP_Pos (28) /*!< SYS_T::GPG_MFPH: PG15MFP Position */
#define SYS_GPG_MFPH_PG15MFP_Msk (0xful << SYS_GPG_MFPH_PG15MFP_Pos) /*!< SYS_T::GPG_MFPH: PG15MFP Mask */
#define SYS_GPH_MFPL_PH0MFP_Pos (0) /*!< SYS_T::GPH_MFPL: PH0MFP Position */
#define SYS_GPH_MFPL_PH0MFP_Msk (0xful << SYS_GPH_MFPL_PH0MFP_Pos) /*!< SYS_T::GPH_MFPL: PH0MFP Mask */
#define SYS_GPH_MFPL_PH1MFP_Pos (4) /*!< SYS_T::GPH_MFPL: PH1MFP Position */
#define SYS_GPH_MFPL_PH1MFP_Msk (0xful << SYS_GPH_MFPL_PH1MFP_Pos) /*!< SYS_T::GPH_MFPL: PH1MFP Mask */
#define SYS_GPH_MFPL_PH2MFP_Pos (8) /*!< SYS_T::GPH_MFPL: PH2MFP Position */
#define SYS_GPH_MFPL_PH2MFP_Msk (0xful << SYS_GPH_MFPL_PH2MFP_Pos) /*!< SYS_T::GPH_MFPL: PH2MFP Mask */
#define SYS_GPH_MFPL_PH3MFP_Pos (12) /*!< SYS_T::GPH_MFPL: PH3MFP Position */
#define SYS_GPH_MFPL_PH3MFP_Msk (0xful << SYS_GPH_MFPL_PH3MFP_Pos) /*!< SYS_T::GPH_MFPL: PH3MFP Mask */
#define SYS_GPH_MFPL_PH4MFP_Pos (16) /*!< SYS_T::GPH_MFPL: PH4MFP Position */
#define SYS_GPH_MFPL_PH4MFP_Msk (0xful << SYS_GPH_MFPL_PH4MFP_Pos) /*!< SYS_T::GPH_MFPL: PH4MFP Mask */
#define SYS_GPH_MFPL_PH5MFP_Pos (20) /*!< SYS_T::GPH_MFPL: PH5MFP Position */
#define SYS_GPH_MFPL_PH5MFP_Msk (0xful << SYS_GPH_MFPL_PH5MFP_Pos) /*!< SYS_T::GPH_MFPL: PH5MFP Mask */
#define SYS_GPH_MFPL_PH6MFP_Pos (24) /*!< SYS_T::GPH_MFPL: PH6MFP Position */
#define SYS_GPH_MFPL_PH6MFP_Msk (0xful << SYS_GPH_MFPL_PH6MFP_Pos) /*!< SYS_T::GPH_MFPL: PH6MFP Mask */
#define SYS_GPH_MFPL_PH7MFP_Pos (28) /*!< SYS_T::GPH_MFPL: PH7MFP Position */
#define SYS_GPH_MFPL_PH7MFP_Msk (0xful << SYS_GPH_MFPL_PH7MFP_Pos) /*!< SYS_T::GPH_MFPL: PH7MFP Mask */
#define SYS_GPH_MFPH_PH8MFP_Pos (0) /*!< SYS_T::GPH_MFPH: PH8MFP Position */
#define SYS_GPH_MFPH_PH8MFP_Msk (0xful << SYS_GPH_MFPH_PH8MFP_Pos) /*!< SYS_T::GPH_MFPH: PH8MFP Mask */
#define SYS_GPH_MFPH_PH9MFP_Pos (4) /*!< SYS_T::GPH_MFPH: PH9MFP Position */
#define SYS_GPH_MFPH_PH9MFP_Msk (0xful << SYS_GPH_MFPH_PH9MFP_Pos) /*!< SYS_T::GPH_MFPH: PH9MFP Mask */
#define SYS_GPH_MFPH_PH10MFP_Pos (8) /*!< SYS_T::GPH_MFPH: PH10MFP Position */
#define SYS_GPH_MFPH_PH10MFP_Msk (0xful << SYS_GPH_MFPH_PH10MFP_Pos) /*!< SYS_T::GPH_MFPH: PH10MFP Mask */
#define SYS_GPH_MFPH_PH11MFP_Pos (12) /*!< SYS_T::GPH_MFPH: PH11MFP Position */
#define SYS_GPH_MFPH_PH11MFP_Msk (0xful << SYS_GPH_MFPH_PH11MFP_Pos) /*!< SYS_T::GPH_MFPH: PH11MFP Mask */
#define SYS_GPH_MFPH_PH12MFP_Pos (16) /*!< SYS_T::GPH_MFPH: PH12MFP Position */
#define SYS_GPH_MFPH_PH12MFP_Msk (0xful << SYS_GPH_MFPH_PH12MFP_Pos) /*!< SYS_T::GPH_MFPH: PH12MFP Mask */
#define SYS_GPH_MFPH_PH13MFP_Pos (20) /*!< SYS_T::GPH_MFPH: PH13MFP Position */
#define SYS_GPH_MFPH_PH13MFP_Msk (0xful << SYS_GPH_MFPH_PH13MFP_Pos) /*!< SYS_T::GPH_MFPH: PH13MFP Mask */
#define SYS_GPH_MFPH_PH14MFP_Pos (24) /*!< SYS_T::GPH_MFPH: PH14MFP Position */
#define SYS_GPH_MFPH_PH14MFP_Msk (0xful << SYS_GPH_MFPH_PH14MFP_Pos) /*!< SYS_T::GPH_MFPH: PH14MFP Mask */
#define SYS_GPH_MFPH_PH15MFP_Pos (28) /*!< SYS_T::GPH_MFPH: PH15MFP Position */
#define SYS_GPH_MFPH_PH15MFP_Msk (0xful << SYS_GPH_MFPH_PH15MFP_Pos) /*!< SYS_T::GPH_MFPH: PH15MFP Mask */
#define SYS_GPA_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPA_MFOS: MFOS0 Position */
#define SYS_GPA_MFOS_MFOS0_Msk (0x1ul << SYS_GPA_MFOS_MFOS0_Pos) /*!< SYS_T::GPA_MFOS: MFOS0 Mask */
#define SYS_GPA_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPA_MFOS: MFOS1 Position */
#define SYS_GPA_MFOS_MFOS1_Msk (0x1ul << SYS_GPA_MFOS_MFOS1_Pos) /*!< SYS_T::GPA_MFOS: MFOS1 Mask */
#define SYS_GPA_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPA_MFOS: MFOS2 Position */
#define SYS_GPA_MFOS_MFOS2_Msk (0x1ul << SYS_GPA_MFOS_MFOS2_Pos) /*!< SYS_T::GPA_MFOS: MFOS2 Mask */
#define SYS_GPA_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPA_MFOS: MFOS3 Position */
#define SYS_GPA_MFOS_MFOS3_Msk (0x1ul << SYS_GPA_MFOS_MFOS3_Pos) /*!< SYS_T::GPA_MFOS: MFOS3 Mask */
#define SYS_GPA_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPA_MFOS: MFOS4 Position */
#define SYS_GPA_MFOS_MFOS4_Msk (0x1ul << SYS_GPA_MFOS_MFOS4_Pos) /*!< SYS_T::GPA_MFOS: MFOS4 Mask */
#define SYS_GPA_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPA_MFOS: MFOS5 Position */
#define SYS_GPA_MFOS_MFOS5_Msk (0x1ul << SYS_GPA_MFOS_MFOS5_Pos) /*!< SYS_T::GPA_MFOS: MFOS5 Mask */
#define SYS_GPA_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPA_MFOS: MFOS6 Position */
#define SYS_GPA_MFOS_MFOS6_Msk (0x1ul << SYS_GPA_MFOS_MFOS6_Pos) /*!< SYS_T::GPA_MFOS: MFOS6 Mask */
#define SYS_GPA_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPA_MFOS: MFOS7 Position */
#define SYS_GPA_MFOS_MFOS7_Msk (0x1ul << SYS_GPA_MFOS_MFOS7_Pos) /*!< SYS_T::GPA_MFOS: MFOS7 Mask */
#define SYS_GPA_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPA_MFOS: MFOS8 Position */
#define SYS_GPA_MFOS_MFOS8_Msk (0x1ul << SYS_GPA_MFOS_MFOS8_Pos) /*!< SYS_T::GPA_MFOS: MFOS8 Mask */
#define SYS_GPA_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPA_MFOS: MFOS9 Position */
#define SYS_GPA_MFOS_MFOS9_Msk (0x1ul << SYS_GPA_MFOS_MFOS9_Pos) /*!< SYS_T::GPA_MFOS: MFOS9 Mask */
#define SYS_GPA_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPA_MFOS: MFOS10 Position */
#define SYS_GPA_MFOS_MFOS10_Msk (0x1ul << SYS_GPA_MFOS_MFOS10_Pos) /*!< SYS_T::GPA_MFOS: MFOS10 Mask */
#define SYS_GPA_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPA_MFOS: MFOS11 Position */
#define SYS_GPA_MFOS_MFOS11_Msk (0x1ul << SYS_GPA_MFOS_MFOS11_Pos) /*!< SYS_T::GPA_MFOS: MFOS11 Mask */
#define SYS_GPA_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPA_MFOS: MFOS12 Position */
#define SYS_GPA_MFOS_MFOS12_Msk (0x1ul << SYS_GPA_MFOS_MFOS12_Pos) /*!< SYS_T::GPA_MFOS: MFOS12 Mask */
#define SYS_GPA_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPA_MFOS: MFOS13 Position */
#define SYS_GPA_MFOS_MFOS13_Msk (0x1ul << SYS_GPA_MFOS_MFOS13_Pos) /*!< SYS_T::GPA_MFOS: MFOS13 Mask */
#define SYS_GPA_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPA_MFOS: MFOS14 Position */
#define SYS_GPA_MFOS_MFOS14_Msk (0x1ul << SYS_GPA_MFOS_MFOS14_Pos) /*!< SYS_T::GPA_MFOS: MFOS14 Mask */
#define SYS_GPA_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPA_MFOS: MFOS15 Position */
#define SYS_GPA_MFOS_MFOS15_Msk (0x1ul << SYS_GPA_MFOS_MFOS15_Pos) /*!< SYS_T::GPA_MFOS: MFOS15 Mask */
#define SYS_GPB_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPB_MFOS: MFOS0 Position */
#define SYS_GPB_MFOS_MFOS0_Msk (0x1ul << SYS_GPB_MFOS_MFOS0_Pos) /*!< SYS_T::GPB_MFOS: MFOS0 Mask */
#define SYS_GPB_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPB_MFOS: MFOS1 Position */
#define SYS_GPB_MFOS_MFOS1_Msk (0x1ul << SYS_GPB_MFOS_MFOS1_Pos) /*!< SYS_T::GPB_MFOS: MFOS1 Mask */
#define SYS_GPB_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPB_MFOS: MFOS2 Position */
#define SYS_GPB_MFOS_MFOS2_Msk (0x1ul << SYS_GPB_MFOS_MFOS2_Pos) /*!< SYS_T::GPB_MFOS: MFOS2 Mask */
#define SYS_GPB_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPB_MFOS: MFOS3 Position */
#define SYS_GPB_MFOS_MFOS3_Msk (0x1ul << SYS_GPB_MFOS_MFOS3_Pos) /*!< SYS_T::GPB_MFOS: MFOS3 Mask */
#define SYS_GPB_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPB_MFOS: MFOS4 Position */
#define SYS_GPB_MFOS_MFOS4_Msk (0x1ul << SYS_GPB_MFOS_MFOS4_Pos) /*!< SYS_T::GPB_MFOS: MFOS4 Mask */
#define SYS_GPB_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPB_MFOS: MFOS5 Position */
#define SYS_GPB_MFOS_MFOS5_Msk (0x1ul << SYS_GPB_MFOS_MFOS5_Pos) /*!< SYS_T::GPB_MFOS: MFOS5 Mask */
#define SYS_GPB_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPB_MFOS: MFOS6 Position */
#define SYS_GPB_MFOS_MFOS6_Msk (0x1ul << SYS_GPB_MFOS_MFOS6_Pos) /*!< SYS_T::GPB_MFOS: MFOS6 Mask */
#define SYS_GPB_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPB_MFOS: MFOS7 Position */
#define SYS_GPB_MFOS_MFOS7_Msk (0x1ul << SYS_GPB_MFOS_MFOS7_Pos) /*!< SYS_T::GPB_MFOS: MFOS7 Mask */
#define SYS_GPB_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPB_MFOS: MFOS8 Position */
#define SYS_GPB_MFOS_MFOS8_Msk (0x1ul << SYS_GPB_MFOS_MFOS8_Pos) /*!< SYS_T::GPB_MFOS: MFOS8 Mask */
#define SYS_GPB_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPB_MFOS: MFOS9 Position */
#define SYS_GPB_MFOS_MFOS9_Msk (0x1ul << SYS_GPB_MFOS_MFOS9_Pos) /*!< SYS_T::GPB_MFOS: MFOS9 Mask */
#define SYS_GPB_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPB_MFOS: MFOS10 Position */
#define SYS_GPB_MFOS_MFOS10_Msk (0x1ul << SYS_GPB_MFOS_MFOS10_Pos) /*!< SYS_T::GPB_MFOS: MFOS10 Mask */
#define SYS_GPB_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPB_MFOS: MFOS11 Position */
#define SYS_GPB_MFOS_MFOS11_Msk (0x1ul << SYS_GPB_MFOS_MFOS11_Pos) /*!< SYS_T::GPB_MFOS: MFOS11 Mask */
#define SYS_GPB_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPB_MFOS: MFOS12 Position */
#define SYS_GPB_MFOS_MFOS12_Msk (0x1ul << SYS_GPB_MFOS_MFOS12_Pos) /*!< SYS_T::GPB_MFOS: MFOS12 Mask */
#define SYS_GPB_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPB_MFOS: MFOS13 Position */
#define SYS_GPB_MFOS_MFOS13_Msk (0x1ul << SYS_GPB_MFOS_MFOS13_Pos) /*!< SYS_T::GPB_MFOS: MFOS13 Mask */
#define SYS_GPB_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPB_MFOS: MFOS14 Position */
#define SYS_GPB_MFOS_MFOS14_Msk (0x1ul << SYS_GPB_MFOS_MFOS14_Pos) /*!< SYS_T::GPB_MFOS: MFOS14 Mask */
#define SYS_GPB_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPB_MFOS: MFOS15 Position */
#define SYS_GPB_MFOS_MFOS15_Msk (0x1ul << SYS_GPB_MFOS_MFOS15_Pos) /*!< SYS_T::GPB_MFOS: MFOS15 Mask */
#define SYS_GPC_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPC_MFOS: MFOS0 Position */
#define SYS_GPC_MFOS_MFOS0_Msk (0x1ul << SYS_GPC_MFOS_MFOS0_Pos) /*!< SYS_T::GPC_MFOS: MFOS0 Mask */
#define SYS_GPC_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPC_MFOS: MFOS1 Position */
#define SYS_GPC_MFOS_MFOS1_Msk (0x1ul << SYS_GPC_MFOS_MFOS1_Pos) /*!< SYS_T::GPC_MFOS: MFOS1 Mask */
#define SYS_GPC_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPC_MFOS: MFOS2 Position */
#define SYS_GPC_MFOS_MFOS2_Msk (0x1ul << SYS_GPC_MFOS_MFOS2_Pos) /*!< SYS_T::GPC_MFOS: MFOS2 Mask */
#define SYS_GPC_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPC_MFOS: MFOS3 Position */
#define SYS_GPC_MFOS_MFOS3_Msk (0x1ul << SYS_GPC_MFOS_MFOS3_Pos) /*!< SYS_T::GPC_MFOS: MFOS3 Mask */
#define SYS_GPC_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPC_MFOS: MFOS4 Position */
#define SYS_GPC_MFOS_MFOS4_Msk (0x1ul << SYS_GPC_MFOS_MFOS4_Pos) /*!< SYS_T::GPC_MFOS: MFOS4 Mask */
#define SYS_GPC_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPC_MFOS: MFOS5 Position */
#define SYS_GPC_MFOS_MFOS5_Msk (0x1ul << SYS_GPC_MFOS_MFOS5_Pos) /*!< SYS_T::GPC_MFOS: MFOS5 Mask */
#define SYS_GPC_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPC_MFOS: MFOS6 Position */
#define SYS_GPC_MFOS_MFOS6_Msk (0x1ul << SYS_GPC_MFOS_MFOS6_Pos) /*!< SYS_T::GPC_MFOS: MFOS6 Mask */
#define SYS_GPC_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPC_MFOS: MFOS7 Position */
#define SYS_GPC_MFOS_MFOS7_Msk (0x1ul << SYS_GPC_MFOS_MFOS7_Pos) /*!< SYS_T::GPC_MFOS: MFOS7 Mask */
#define SYS_GPC_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPC_MFOS: MFOS8 Position */
#define SYS_GPC_MFOS_MFOS8_Msk (0x1ul << SYS_GPC_MFOS_MFOS8_Pos) /*!< SYS_T::GPC_MFOS: MFOS8 Mask */
#define SYS_GPC_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPC_MFOS: MFOS9 Position */
#define SYS_GPC_MFOS_MFOS9_Msk (0x1ul << SYS_GPC_MFOS_MFOS9_Pos) /*!< SYS_T::GPC_MFOS: MFOS9 Mask */
#define SYS_GPC_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPC_MFOS: MFOS10 Position */
#define SYS_GPC_MFOS_MFOS10_Msk (0x1ul << SYS_GPC_MFOS_MFOS10_Pos) /*!< SYS_T::GPC_MFOS: MFOS10 Mask */
#define SYS_GPC_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPC_MFOS: MFOS11 Position */
#define SYS_GPC_MFOS_MFOS11_Msk (0x1ul << SYS_GPC_MFOS_MFOS11_Pos) /*!< SYS_T::GPC_MFOS: MFOS11 Mask */
#define SYS_GPC_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPC_MFOS: MFOS12 Position */
#define SYS_GPC_MFOS_MFOS12_Msk (0x1ul << SYS_GPC_MFOS_MFOS12_Pos) /*!< SYS_T::GPC_MFOS: MFOS12 Mask */
#define SYS_GPC_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPC_MFOS: MFOS13 Position */
#define SYS_GPC_MFOS_MFOS13_Msk (0x1ul << SYS_GPC_MFOS_MFOS13_Pos) /*!< SYS_T::GPC_MFOS: MFOS13 Mask */
#define SYS_GPC_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPC_MFOS: MFOS14 Position */
#define SYS_GPC_MFOS_MFOS14_Msk (0x1ul << SYS_GPC_MFOS_MFOS14_Pos) /*!< SYS_T::GPC_MFOS: MFOS14 Mask */
#define SYS_GPC_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPC_MFOS: MFOS15 Position */
#define SYS_GPC_MFOS_MFOS15_Msk (0x1ul << SYS_GPC_MFOS_MFOS15_Pos) /*!< SYS_T::GPC_MFOS: MFOS15 Mask */
#define SYS_GPD_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPD_MFOS: MFOS0 Position */
#define SYS_GPD_MFOS_MFOS0_Msk (0x1ul << SYS_GPD_MFOS_MFOS0_Pos) /*!< SYS_T::GPD_MFOS: MFOS0 Mask */
#define SYS_GPD_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPD_MFOS: MFOS1 Position */
#define SYS_GPD_MFOS_MFOS1_Msk (0x1ul << SYS_GPD_MFOS_MFOS1_Pos) /*!< SYS_T::GPD_MFOS: MFOS1 Mask */
#define SYS_GPD_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPD_MFOS: MFOS2 Position */
#define SYS_GPD_MFOS_MFOS2_Msk (0x1ul << SYS_GPD_MFOS_MFOS2_Pos) /*!< SYS_T::GPD_MFOS: MFOS2 Mask */
#define SYS_GPD_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPD_MFOS: MFOS3 Position */
#define SYS_GPD_MFOS_MFOS3_Msk (0x1ul << SYS_GPD_MFOS_MFOS3_Pos) /*!< SYS_T::GPD_MFOS: MFOS3 Mask */
#define SYS_GPD_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPD_MFOS: MFOS4 Position */
#define SYS_GPD_MFOS_MFOS4_Msk (0x1ul << SYS_GPD_MFOS_MFOS4_Pos) /*!< SYS_T::GPD_MFOS: MFOS4 Mask */
#define SYS_GPD_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPD_MFOS: MFOS5 Position */
#define SYS_GPD_MFOS_MFOS5_Msk (0x1ul << SYS_GPD_MFOS_MFOS5_Pos) /*!< SYS_T::GPD_MFOS: MFOS5 Mask */
#define SYS_GPD_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPD_MFOS: MFOS6 Position */
#define SYS_GPD_MFOS_MFOS6_Msk (0x1ul << SYS_GPD_MFOS_MFOS6_Pos) /*!< SYS_T::GPD_MFOS: MFOS6 Mask */
#define SYS_GPD_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPD_MFOS: MFOS7 Position */
#define SYS_GPD_MFOS_MFOS7_Msk (0x1ul << SYS_GPD_MFOS_MFOS7_Pos) /*!< SYS_T::GPD_MFOS: MFOS7 Mask */
#define SYS_GPD_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPD_MFOS: MFOS8 Position */
#define SYS_GPD_MFOS_MFOS8_Msk (0x1ul << SYS_GPD_MFOS_MFOS8_Pos) /*!< SYS_T::GPD_MFOS: MFOS8 Mask */
#define SYS_GPD_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPD_MFOS: MFOS9 Position */
#define SYS_GPD_MFOS_MFOS9_Msk (0x1ul << SYS_GPD_MFOS_MFOS9_Pos) /*!< SYS_T::GPD_MFOS: MFOS9 Mask */
#define SYS_GPD_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPD_MFOS: MFOS10 Position */
#define SYS_GPD_MFOS_MFOS10_Msk (0x1ul << SYS_GPD_MFOS_MFOS10_Pos) /*!< SYS_T::GPD_MFOS: MFOS10 Mask */
#define SYS_GPD_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPD_MFOS: MFOS11 Position */
#define SYS_GPD_MFOS_MFOS11_Msk (0x1ul << SYS_GPD_MFOS_MFOS11_Pos) /*!< SYS_T::GPD_MFOS: MFOS11 Mask */
#define SYS_GPD_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPD_MFOS: MFOS12 Position */
#define SYS_GPD_MFOS_MFOS12_Msk (0x1ul << SYS_GPD_MFOS_MFOS12_Pos) /*!< SYS_T::GPD_MFOS: MFOS12 Mask */
#define SYS_GPD_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPD_MFOS: MFOS13 Position */
#define SYS_GPD_MFOS_MFOS13_Msk (0x1ul << SYS_GPD_MFOS_MFOS13_Pos) /*!< SYS_T::GPD_MFOS: MFOS13 Mask */
#define SYS_GPD_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPD_MFOS: MFOS14 Position */
#define SYS_GPD_MFOS_MFOS14_Msk (0x1ul << SYS_GPD_MFOS_MFOS14_Pos) /*!< SYS_T::GPD_MFOS: MFOS14 Mask */
#define SYS_GPD_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPD_MFOS: MFOS15 Position */
#define SYS_GPD_MFOS_MFOS15_Msk (0x1ul << SYS_GPD_MFOS_MFOS15_Pos) /*!< SYS_T::GPD_MFOS: MFOS15 Mask */
#define SYS_GPE_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPE_MFOS: MFOS0 Position */
#define SYS_GPE_MFOS_MFOS0_Msk (0x1ul << SYS_GPE_MFOS_MFOS0_Pos) /*!< SYS_T::GPE_MFOS: MFOS0 Mask */
#define SYS_GPE_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPE_MFOS: MFOS1 Position */
#define SYS_GPE_MFOS_MFOS1_Msk (0x1ul << SYS_GPE_MFOS_MFOS1_Pos) /*!< SYS_T::GPE_MFOS: MFOS1 Mask */
#define SYS_GPE_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPE_MFOS: MFOS2 Position */
#define SYS_GPE_MFOS_MFOS2_Msk (0x1ul << SYS_GPE_MFOS_MFOS2_Pos) /*!< SYS_T::GPE_MFOS: MFOS2 Mask */
#define SYS_GPE_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPE_MFOS: MFOS3 Position */
#define SYS_GPE_MFOS_MFOS3_Msk (0x1ul << SYS_GPE_MFOS_MFOS3_Pos) /*!< SYS_T::GPE_MFOS: MFOS3 Mask */
#define SYS_GPE_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPE_MFOS: MFOS4 Position */
#define SYS_GPE_MFOS_MFOS4_Msk (0x1ul << SYS_GPE_MFOS_MFOS4_Pos) /*!< SYS_T::GPE_MFOS: MFOS4 Mask */
#define SYS_GPE_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPE_MFOS: MFOS5 Position */
#define SYS_GPE_MFOS_MFOS5_Msk (0x1ul << SYS_GPE_MFOS_MFOS5_Pos) /*!< SYS_T::GPE_MFOS: MFOS5 Mask */
#define SYS_GPE_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPE_MFOS: MFOS6 Position */
#define SYS_GPE_MFOS_MFOS6_Msk (0x1ul << SYS_GPE_MFOS_MFOS6_Pos) /*!< SYS_T::GPE_MFOS: MFOS6 Mask */
#define SYS_GPE_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPE_MFOS: MFOS7 Position */
#define SYS_GPE_MFOS_MFOS7_Msk (0x1ul << SYS_GPE_MFOS_MFOS7_Pos) /*!< SYS_T::GPE_MFOS: MFOS7 Mask */
#define SYS_GPE_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPE_MFOS: MFOS8 Position */
#define SYS_GPE_MFOS_MFOS8_Msk (0x1ul << SYS_GPE_MFOS_MFOS8_Pos) /*!< SYS_T::GPE_MFOS: MFOS8 Mask */
#define SYS_GPE_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPE_MFOS: MFOS9 Position */
#define SYS_GPE_MFOS_MFOS9_Msk (0x1ul << SYS_GPE_MFOS_MFOS9_Pos) /*!< SYS_T::GPE_MFOS: MFOS9 Mask */
#define SYS_GPE_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPE_MFOS: MFOS10 Position */
#define SYS_GPE_MFOS_MFOS10_Msk (0x1ul << SYS_GPE_MFOS_MFOS10_Pos) /*!< SYS_T::GPE_MFOS: MFOS10 Mask */
#define SYS_GPE_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPE_MFOS: MFOS11 Position */
#define SYS_GPE_MFOS_MFOS11_Msk (0x1ul << SYS_GPE_MFOS_MFOS11_Pos) /*!< SYS_T::GPE_MFOS: MFOS11 Mask */
#define SYS_GPE_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPE_MFOS: MFOS12 Position */
#define SYS_GPE_MFOS_MFOS12_Msk (0x1ul << SYS_GPE_MFOS_MFOS12_Pos) /*!< SYS_T::GPE_MFOS: MFOS12 Mask */
#define SYS_GPE_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPE_MFOS: MFOS13 Position */
#define SYS_GPE_MFOS_MFOS13_Msk (0x1ul << SYS_GPE_MFOS_MFOS13_Pos) /*!< SYS_T::GPE_MFOS: MFOS13 Mask */
#define SYS_GPE_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPE_MFOS: MFOS14 Position */
#define SYS_GPE_MFOS_MFOS14_Msk (0x1ul << SYS_GPE_MFOS_MFOS14_Pos) /*!< SYS_T::GPE_MFOS: MFOS14 Mask */
#define SYS_GPE_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPE_MFOS: MFOS15 Position */
#define SYS_GPE_MFOS_MFOS15_Msk (0x1ul << SYS_GPE_MFOS_MFOS15_Pos) /*!< SYS_T::GPE_MFOS: MFOS15 Mask */
#define SYS_GPF_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPF_MFOS: MFOS0 Position */
#define SYS_GPF_MFOS_MFOS0_Msk (0x1ul << SYS_GPF_MFOS_MFOS0_Pos) /*!< SYS_T::GPF_MFOS: MFOS0 Mask */
#define SYS_GPF_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPF_MFOS: MFOS1 Position */
#define SYS_GPF_MFOS_MFOS1_Msk (0x1ul << SYS_GPF_MFOS_MFOS1_Pos) /*!< SYS_T::GPF_MFOS: MFOS1 Mask */
#define SYS_GPF_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPF_MFOS: MFOS2 Position */
#define SYS_GPF_MFOS_MFOS2_Msk (0x1ul << SYS_GPF_MFOS_MFOS2_Pos) /*!< SYS_T::GPF_MFOS: MFOS2 Mask */
#define SYS_GPF_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPF_MFOS: MFOS3 Position */
#define SYS_GPF_MFOS_MFOS3_Msk (0x1ul << SYS_GPF_MFOS_MFOS3_Pos) /*!< SYS_T::GPF_MFOS: MFOS3 Mask */
#define SYS_GPF_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPF_MFOS: MFOS4 Position */
#define SYS_GPF_MFOS_MFOS4_Msk (0x1ul << SYS_GPF_MFOS_MFOS4_Pos) /*!< SYS_T::GPF_MFOS: MFOS4 Mask */
#define SYS_GPF_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPF_MFOS: MFOS5 Position */
#define SYS_GPF_MFOS_MFOS5_Msk (0x1ul << SYS_GPF_MFOS_MFOS5_Pos) /*!< SYS_T::GPF_MFOS: MFOS5 Mask */
#define SYS_GPF_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPF_MFOS: MFOS6 Position */
#define SYS_GPF_MFOS_MFOS6_Msk (0x1ul << SYS_GPF_MFOS_MFOS6_Pos) /*!< SYS_T::GPF_MFOS: MFOS6 Mask */
#define SYS_GPF_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPF_MFOS: MFOS7 Position */
#define SYS_GPF_MFOS_MFOS7_Msk (0x1ul << SYS_GPF_MFOS_MFOS7_Pos) /*!< SYS_T::GPF_MFOS: MFOS7 Mask */
#define SYS_GPF_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPF_MFOS: MFOS8 Position */
#define SYS_GPF_MFOS_MFOS8_Msk (0x1ul << SYS_GPF_MFOS_MFOS8_Pos) /*!< SYS_T::GPF_MFOS: MFOS8 Mask */
#define SYS_GPF_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPF_MFOS: MFOS9 Position */
#define SYS_GPF_MFOS_MFOS9_Msk (0x1ul << SYS_GPF_MFOS_MFOS9_Pos) /*!< SYS_T::GPF_MFOS: MFOS9 Mask */
#define SYS_GPF_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPF_MFOS: MFOS10 Position */
#define SYS_GPF_MFOS_MFOS10_Msk (0x1ul << SYS_GPF_MFOS_MFOS10_Pos) /*!< SYS_T::GPF_MFOS: MFOS10 Mask */
#define SYS_GPF_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPF_MFOS: MFOS11 Position */
#define SYS_GPF_MFOS_MFOS11_Msk (0x1ul << SYS_GPF_MFOS_MFOS11_Pos) /*!< SYS_T::GPF_MFOS: MFOS11 Mask */
#define SYS_GPF_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPF_MFOS: MFOS12 Position */
#define SYS_GPF_MFOS_MFOS12_Msk (0x1ul << SYS_GPF_MFOS_MFOS12_Pos) /*!< SYS_T::GPF_MFOS: MFOS12 Mask */
#define SYS_GPF_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPF_MFOS: MFOS13 Position */
#define SYS_GPF_MFOS_MFOS13_Msk (0x1ul << SYS_GPF_MFOS_MFOS13_Pos) /*!< SYS_T::GPF_MFOS: MFOS13 Mask */
#define SYS_GPF_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPF_MFOS: MFOS14 Position */
#define SYS_GPF_MFOS_MFOS14_Msk (0x1ul << SYS_GPF_MFOS_MFOS14_Pos) /*!< SYS_T::GPF_MFOS: MFOS14 Mask */
#define SYS_GPF_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPF_MFOS: MFOS15 Position */
#define SYS_GPF_MFOS_MFOS15_Msk (0x1ul << SYS_GPF_MFOS_MFOS15_Pos) /*!< SYS_T::GPF_MFOS: MFOS15 Mask */
#define SYS_GPG_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPG_MFOS: MFOS0 Position */
#define SYS_GPG_MFOS_MFOS0_Msk (0x1ul << SYS_GPG_MFOS_MFOS0_Pos) /*!< SYS_T::GPG_MFOS: MFOS0 Mask */
#define SYS_GPG_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPG_MFOS: MFOS1 Position */
#define SYS_GPG_MFOS_MFOS1_Msk (0x1ul << SYS_GPG_MFOS_MFOS1_Pos) /*!< SYS_T::GPG_MFOS: MFOS1 Mask */
#define SYS_GPG_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPG_MFOS: MFOS2 Position */
#define SYS_GPG_MFOS_MFOS2_Msk (0x1ul << SYS_GPG_MFOS_MFOS2_Pos) /*!< SYS_T::GPG_MFOS: MFOS2 Mask */
#define SYS_GPG_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPG_MFOS: MFOS3 Position */
#define SYS_GPG_MFOS_MFOS3_Msk (0x1ul << SYS_GPG_MFOS_MFOS3_Pos) /*!< SYS_T::GPG_MFOS: MFOS3 Mask */
#define SYS_GPG_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPG_MFOS: MFOS4 Position */
#define SYS_GPG_MFOS_MFOS4_Msk (0x1ul << SYS_GPG_MFOS_MFOS4_Pos) /*!< SYS_T::GPG_MFOS: MFOS4 Mask */
#define SYS_GPG_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPG_MFOS: MFOS5 Position */
#define SYS_GPG_MFOS_MFOS5_Msk (0x1ul << SYS_GPG_MFOS_MFOS5_Pos) /*!< SYS_T::GPG_MFOS: MFOS5 Mask */
#define SYS_GPG_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPG_MFOS: MFOS6 Position */
#define SYS_GPG_MFOS_MFOS6_Msk (0x1ul << SYS_GPG_MFOS_MFOS6_Pos) /*!< SYS_T::GPG_MFOS: MFOS6 Mask */
#define SYS_GPG_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPG_MFOS: MFOS7 Position */
#define SYS_GPG_MFOS_MFOS7_Msk (0x1ul << SYS_GPG_MFOS_MFOS7_Pos) /*!< SYS_T::GPG_MFOS: MFOS7 Mask */
#define SYS_GPG_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPG_MFOS: MFOS8 Position */
#define SYS_GPG_MFOS_MFOS8_Msk (0x1ul << SYS_GPG_MFOS_MFOS8_Pos) /*!< SYS_T::GPG_MFOS: MFOS8 Mask */
#define SYS_GPG_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPG_MFOS: MFOS9 Position */
#define SYS_GPG_MFOS_MFOS9_Msk (0x1ul << SYS_GPG_MFOS_MFOS9_Pos) /*!< SYS_T::GPG_MFOS: MFOS9 Mask */
#define SYS_GPG_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPG_MFOS: MFOS10 Position */
#define SYS_GPG_MFOS_MFOS10_Msk (0x1ul << SYS_GPG_MFOS_MFOS10_Pos) /*!< SYS_T::GPG_MFOS: MFOS10 Mask */
#define SYS_GPG_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPG_MFOS: MFOS11 Position */
#define SYS_GPG_MFOS_MFOS11_Msk (0x1ul << SYS_GPG_MFOS_MFOS11_Pos) /*!< SYS_T::GPG_MFOS: MFOS11 Mask */
#define SYS_GPG_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPG_MFOS: MFOS12 Position */
#define SYS_GPG_MFOS_MFOS12_Msk (0x1ul << SYS_GPG_MFOS_MFOS12_Pos) /*!< SYS_T::GPG_MFOS: MFOS12 Mask */
#define SYS_GPG_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPG_MFOS: MFOS13 Position */
#define SYS_GPG_MFOS_MFOS13_Msk (0x1ul << SYS_GPG_MFOS_MFOS13_Pos) /*!< SYS_T::GPG_MFOS: MFOS13 Mask */
#define SYS_GPG_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPG_MFOS: MFOS14 Position */
#define SYS_GPG_MFOS_MFOS14_Msk (0x1ul << SYS_GPG_MFOS_MFOS14_Pos) /*!< SYS_T::GPG_MFOS: MFOS14 Mask */
#define SYS_GPG_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPG_MFOS: MFOS15 Position */
#define SYS_GPG_MFOS_MFOS15_Msk (0x1ul << SYS_GPG_MFOS_MFOS15_Pos) /*!< SYS_T::GPG_MFOS: MFOS15 Mask */
#define SYS_GPH_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPH_MFOS: MFOS0 Position */
#define SYS_GPH_MFOS_MFOS0_Msk (0x1ul << SYS_GPH_MFOS_MFOS0_Pos) /*!< SYS_T::GPH_MFOS: MFOS0 Mask */
#define SYS_GPH_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPH_MFOS: MFOS1 Position */
#define SYS_GPH_MFOS_MFOS1_Msk (0x1ul << SYS_GPH_MFOS_MFOS1_Pos) /*!< SYS_T::GPH_MFOS: MFOS1 Mask */
#define SYS_GPH_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPH_MFOS: MFOS2 Position */
#define SYS_GPH_MFOS_MFOS2_Msk (0x1ul << SYS_GPH_MFOS_MFOS2_Pos) /*!< SYS_T::GPH_MFOS: MFOS2 Mask */
#define SYS_GPH_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPH_MFOS: MFOS3 Position */
#define SYS_GPH_MFOS_MFOS3_Msk (0x1ul << SYS_GPH_MFOS_MFOS3_Pos) /*!< SYS_T::GPH_MFOS: MFOS3 Mask */
#define SYS_GPH_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPH_MFOS: MFOS4 Position */
#define SYS_GPH_MFOS_MFOS4_Msk (0x1ul << SYS_GPH_MFOS_MFOS4_Pos) /*!< SYS_T::GPH_MFOS: MFOS4 Mask */
#define SYS_GPH_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPH_MFOS: MFOS5 Position */
#define SYS_GPH_MFOS_MFOS5_Msk (0x1ul << SYS_GPH_MFOS_MFOS5_Pos) /*!< SYS_T::GPH_MFOS: MFOS5 Mask */
#define SYS_GPH_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPH_MFOS: MFOS6 Position */
#define SYS_GPH_MFOS_MFOS6_Msk (0x1ul << SYS_GPH_MFOS_MFOS6_Pos) /*!< SYS_T::GPH_MFOS: MFOS6 Mask */
#define SYS_GPH_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPH_MFOS: MFOS7 Position */
#define SYS_GPH_MFOS_MFOS7_Msk (0x1ul << SYS_GPH_MFOS_MFOS7_Pos) /*!< SYS_T::GPH_MFOS: MFOS7 Mask */
#define SYS_GPH_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPH_MFOS: MFOS8 Position */
#define SYS_GPH_MFOS_MFOS8_Msk (0x1ul << SYS_GPH_MFOS_MFOS8_Pos) /*!< SYS_T::GPH_MFOS: MFOS8 Mask */
#define SYS_GPH_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPH_MFOS: MFOS9 Position */
#define SYS_GPH_MFOS_MFOS9_Msk (0x1ul << SYS_GPH_MFOS_MFOS9_Pos) /*!< SYS_T::GPH_MFOS: MFOS9 Mask */
#define SYS_GPH_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPH_MFOS: MFOS10 Position */
#define SYS_GPH_MFOS_MFOS10_Msk (0x1ul << SYS_GPH_MFOS_MFOS10_Pos) /*!< SYS_T::GPH_MFOS: MFOS10 Mask */
#define SYS_GPH_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPH_MFOS: MFOS11 Position */
#define SYS_GPH_MFOS_MFOS11_Msk (0x1ul << SYS_GPH_MFOS_MFOS11_Pos) /*!< SYS_T::GPH_MFOS: MFOS11 Mask */
#define SYS_GPH_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPH_MFOS: MFOS12 Position */
#define SYS_GPH_MFOS_MFOS12_Msk (0x1ul << SYS_GPH_MFOS_MFOS12_Pos) /*!< SYS_T::GPH_MFOS: MFOS12 Mask */
#define SYS_GPH_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPH_MFOS: MFOS13 Position */
#define SYS_GPH_MFOS_MFOS13_Msk (0x1ul << SYS_GPH_MFOS_MFOS13_Pos) /*!< SYS_T::GPH_MFOS: MFOS13 Mask */
#define SYS_GPH_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPH_MFOS: MFOS14 Position */
#define SYS_GPH_MFOS_MFOS14_Msk (0x1ul << SYS_GPH_MFOS_MFOS14_Pos) /*!< SYS_T::GPH_MFOS: MFOS14 Mask */
#define SYS_GPH_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPH_MFOS: MFOS15 Position */
#define SYS_GPH_MFOS_MFOS15_Msk (0x1ul << SYS_GPH_MFOS_MFOS15_Pos) /*!< SYS_T::GPH_MFOS: MFOS15 Mask */
#define SYS_SRAM_INTCTL_PERRIEN_Pos (0) /*!< SYS_T::SRAM_INTCTL: PERRIEN Position */
#define SYS_SRAM_INTCTL_PERRIEN_Msk (0x1ul << SYS_SRAM_INTCTL_PERRIEN_Pos) /*!< SYS_T::SRAM_INTCTL: PERRIEN Mask */
#define SYS_SRAM_STATUS_PERRIF_Pos (0) /*!< SYS_T::SRAM_STATUS: PERRIF Position */
#define SYS_SRAM_STATUS_PERRIF_Msk (0x1ul << SYS_SRAM_STATUS_PERRIF_Pos) /*!< SYS_T::SRAM_STATUS: PERRIF Mask */
#define SYS_SRAM_ERRADDR_ERRADDR_Pos (0) /*!< SYS_T::SRAM_ERRADDR: ERRADDR Position */
#define SYS_SRAM_ERRADDR_ERRADDR_Msk (0xfffffffful << SYS_SRAM_ERRADDR_ERRADDR_Pos) /*!< SYS_T::SRAM_ERRADDR: ERRADDR Mask */
#define SYS_SRAM_BISTCTL_SRBIST0_Pos (0) /*!< SYS_T::SRAM_BISTCTL: SRBIST0 Position */
#define SYS_SRAM_BISTCTL_SRBIST0_Msk (0x1ul << SYS_SRAM_BISTCTL_SRBIST0_Pos) /*!< SYS_T::SRAM_BISTCTL: SRBIST0 Mask */
#define SYS_SRAM_BISTCTL_SRBIST1_Pos (1) /*!< SYS_T::SRAM_BISTCTL: SRBIST1 Position */
#define SYS_SRAM_BISTCTL_SRBIST1_Msk (0x1ul << SYS_SRAM_BISTCTL_SRBIST1_Pos) /*!< SYS_T::SRAM_BISTCTL: SRBIST1 Mask */
#define SYS_SRAM_BISTCTL_CRBIST_Pos (2) /*!< SYS_T::SRAM_BISTCTL: CRBIST Position */
#define SYS_SRAM_BISTCTL_CRBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_CRBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: CRBIST Mask */
#define SYS_SRAM_BISTCTL_CANBIST_Pos (3) /*!< SYS_T::SRAM_BISTCTL: CANBIST Position */
#define SYS_SRAM_BISTCTL_CANBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_CANBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: CANBIST Mask */
#define SYS_SRAM_BISTCTL_USBBIST_Pos (4) /*!< SYS_T::SRAM_BISTCTL: USBBIST Position */
#define SYS_SRAM_BISTCTL_USBBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_USBBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: USBBIST Mask */
#define SYS_SRAM_BISTCTL_SPIMBIST_Pos (5) /*!< SYS_T::SRAM_BISTCTL: SPIMBIST Position */
#define SYS_SRAM_BISTCTL_SPIMBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_SPIMBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: SPIMBIST Mask */
#define SYS_SRAM_BISTCTL_EMCBIST_Pos (6) /*!< SYS_T::SRAM_BISTCTL: EMCBIST Position */
#define SYS_SRAM_BISTCTL_EMCBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_EMCBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: EMCBIST Mask */
#define SYS_SRAM_BISTCTL_PDMABIST_Pos (7) /*!< SYS_T::SRAM_BISTCTL: PDMABIST Position */
#define SYS_SRAM_BISTCTL_PDMABIST_Msk (0x1ul << SYS_SRAM_BISTCTL_PDMABIST_Pos) /*!< SYS_T::SRAM_BISTCTL: PDMABIST Mask */
#define SYS_SRAM_BISTCTL_HSUSBDBIST_Pos (8) /*!< SYS_T::SRAM_BISTCTL: HSUSBDBIST Position*/
#define SYS_SRAM_BISTCTL_HSUSBDBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_HSUSBDBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: HSUSBDBIST Mask */
#define SYS_SRAM_BISTCTL_HSUSBHBIST_Pos (9) /*!< SYS_T::SRAM_BISTCTL: HSUSBHBIST Position*/
#define SYS_SRAM_BISTCTL_HSUSBHBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_HSUSBHBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: HSUSBHBIST Mask */
#define SYS_SRAM_BISTCTL_SRB0S0_Pos (16) /*!< SYS_T::SRAM_BISTCTL: SRB0S0 Position */
#define SYS_SRAM_BISTCTL_SRB0S0_Msk (0x1ul << SYS_SRAM_BISTCTL_SRB0S0_Pos) /*!< SYS_T::SRAM_BISTCTL: SRB0S0 Mask */
#define SYS_SRAM_BISTCTL_SRB0S1_Pos (17) /*!< SYS_T::SRAM_BISTCTL: SRB0S1 Position */
#define SYS_SRAM_BISTCTL_SRB0S1_Msk (0x1ul << SYS_SRAM_BISTCTL_SRB0S1_Pos) /*!< SYS_T::SRAM_BISTCTL: SRB0S1 Mask */
#define SYS_SRAM_BISTCTL_SRB1S0_Pos (18) /*!< SYS_T::SRAM_BISTCTL: SRB1S0 Position */
#define SYS_SRAM_BISTCTL_SRB1S0_Msk (0x1ul << SYS_SRAM_BISTCTL_SRB1S0_Pos) /*!< SYS_T::SRAM_BISTCTL: SRB1S0 Mask */
#define SYS_SRAM_BISTCTL_SRB1S1_Pos (19) /*!< SYS_T::SRAM_BISTCTL: SRB1S1 Position */
#define SYS_SRAM_BISTCTL_SRB1S1_Msk (0x1ul << SYS_SRAM_BISTCTL_SRB1S1_Pos) /*!< SYS_T::SRAM_BISTCTL: SRB1S1 Mask */
#define SYS_SRAM_BISTCTL_SRB1S2_Pos (20) /*!< SYS_T::SRAM_BISTCTL: SRB1S2 Position */
#define SYS_SRAM_BISTCTL_SRB1S2_Msk (0x1ul << SYS_SRAM_BISTCTL_SRB1S2_Pos) /*!< SYS_T::SRAM_BISTCTL: SRB1S2 Mask */
#define SYS_SRAM_BISTCTL_SRB1S3_Pos (21) /*!< SYS_T::SRAM_BISTCTL: SRB1S3 Position */
#define SYS_SRAM_BISTCTL_SRB1S3_Msk (0x1ul << SYS_SRAM_BISTCTL_SRB1S3_Pos) /*!< SYS_T::SRAM_BISTCTL: SRB1S3 Mask */
#define SYS_SRAM_BISTCTL_SRB1S4_Pos (22) /*!< SYS_T::SRAM_BISTCTL: SRB1S4 Position */
#define SYS_SRAM_BISTCTL_SRB1S4_Msk (0x1ul << SYS_SRAM_BISTCTL_SRB1S4_Pos) /*!< SYS_T::SRAM_BISTCTL: SRB1S4 Mask */
#define SYS_SRAM_BISTCTL_SRB1S5_Pos (23) /*!< SYS_T::SRAM_BISTCTL: SRB1S5 Position */
#define SYS_SRAM_BISTCTL_SRB1S5_Msk (0x1ul << SYS_SRAM_BISTCTL_SRB1S5_Pos) /*!< SYS_T::SRAM_BISTCTL: SRB1S5 Mask */
#define SYS_SRAM_BISTSTS_SRBISTEF0_Pos (0) /*!< SYS_T::SRAM_BISTSTS: SRBISTEF0 Position*/
#define SYS_SRAM_BISTSTS_SRBISTEF0_Msk (0x1ul << SYS_SRAM_BISTSTS_SRBISTEF0_Pos) /*!< SYS_T::SRAM_BISTSTS: SRBISTEF0 Mask */
#define SYS_SRAM_BISTSTS_SRBISTEF1_Pos (1) /*!< SYS_T::SRAM_BISTSTS: SRBISTEF1 Position*/
#define SYS_SRAM_BISTSTS_SRBISTEF1_Msk (0x1ul << SYS_SRAM_BISTSTS_SRBISTEF1_Pos) /*!< SYS_T::SRAM_BISTSTS: SRBISTEF1 Mask */
#define SYS_SRAM_BISTSTS_CRBISTEF_Pos (2) /*!< SYS_T::SRAM_BISTSTS: CRBISTEF Position */
#define SYS_SRAM_BISTSTS_CRBISTEF_Msk (0x1ul << SYS_SRAM_BISTSTS_CRBISTEF_Pos) /*!< SYS_T::SRAM_BISTSTS: CRBISTEF Mask */
#define SYS_SRAM_BISTSTS_CANBEF_Pos (3) /*!< SYS_T::SRAM_BISTSTS: CANBEF Position */
#define SYS_SRAM_BISTSTS_CANBEF_Msk (0x1ul << SYS_SRAM_BISTSTS_CANBEF_Pos) /*!< SYS_T::SRAM_BISTSTS: CANBEF Mask */
#define SYS_SRAM_BISTSTS_USBBEF_Pos (4) /*!< SYS_T::SRAM_BISTSTS: USBBEF Position */
#define SYS_SRAM_BISTSTS_USBBEF_Msk (0x1ul << SYS_SRAM_BISTSTS_USBBEF_Pos) /*!< SYS_T::SRAM_BISTSTS: USBBEF Mask */
#define SYS_SRAM_BISTSTS_SRBEND0_Pos (16) /*!< SYS_T::SRAM_BISTSTS: SRBEND0 Position */
#define SYS_SRAM_BISTSTS_SRBEND0_Msk (0x1ul << SYS_SRAM_BISTSTS_SRBEND0_Pos) /*!< SYS_T::SRAM_BISTSTS: SRBEND0 Mask */
#define SYS_SRAM_BISTSTS_SRBEND1_Pos (17) /*!< SYS_T::SRAM_BISTSTS: SRBEND1 Position */
#define SYS_SRAM_BISTSTS_SRBEND1_Msk (0x1ul << SYS_SRAM_BISTSTS_SRBEND1_Pos) /*!< SYS_T::SRAM_BISTSTS: SRBEND1 Mask */
#define SYS_SRAM_BISTSTS_CRBEND_Pos (18) /*!< SYS_T::SRAM_BISTSTS: CRBEND Position */
#define SYS_SRAM_BISTSTS_CRBEND_Msk (0x1ul << SYS_SRAM_BISTSTS_CRBEND_Pos) /*!< SYS_T::SRAM_BISTSTS: CRBEND Mask */
#define SYS_SRAM_BISTSTS_CANBEND_Pos (19) /*!< SYS_T::SRAM_BISTSTS: CANBEND Position */
#define SYS_SRAM_BISTSTS_CANBEND_Msk (0x1ul << SYS_SRAM_BISTSTS_CANBEND_Pos) /*!< SYS_T::SRAM_BISTSTS: CANBEND Mask */
#define SYS_SRAM_BISTSTS_USBBEND_Pos (20) /*!< SYS_T::SRAM_BISTSTS: USBBEND Position */
#define SYS_SRAM_BISTSTS_USBBEND_Msk (0x1ul << SYS_SRAM_BISTSTS_USBBEND_Pos) /*!< SYS_T::SRAM_BISTSTS: USBBEND Mask */
#define SYS_IRCTCTL_FREQSEL_Pos (0) /*!< SYS_T::IRCTCTL: FREQSEL Position */
#define SYS_IRCTCTL_FREQSEL_Msk (0x3ul << SYS_IRCTCTL_FREQSEL_Pos) /*!< SYS_T::IRCTCTL: FREQSEL Mask */
#define SYS_IRCTCTL_LOOPSEL_Pos (4) /*!< SYS_T::IRCTCTL: LOOPSEL Position */
#define SYS_IRCTCTL_LOOPSEL_Msk (0x3ul << SYS_IRCTCTL_LOOPSEL_Pos) /*!< SYS_T::IRCTCTL: LOOPSEL Mask */
#define SYS_IRCTCTL_RETRYCNT_Pos (6) /*!< SYS_T::IRCTCTL: RETRYCNT Position */
#define SYS_IRCTCTL_RETRYCNT_Msk (0x3ul << SYS_IRCTCTL_RETRYCNT_Pos) /*!< SYS_T::IRCTCTL: RETRYCNT Mask */
#define SYS_IRCTCTL_CESTOPEN_Pos (8) /*!< SYS_T::IRCTCTL: CESTOPEN Position */
#define SYS_IRCTCTL_CESTOPEN_Msk (0x1ul << SYS_IRCTCTL_CESTOPEN_Pos) /*!< SYS_T::IRCTCTL: CESTOPEN Mask */
#define SYS_IRCTCTL_REFCKSEL_Pos (10) /*!< SYS_T::IRCTCTL: REFCKSEL Position */
#define SYS_IRCTCTL_REFCKSEL_Msk (0x1ul << SYS_IRCTCTL_REFCKSEL_Pos) /*!< SYS_T::IRCTCTL: REFCKSEL Mask */
#define SYS_IRCTIEN_TFAILIEN_Pos (1) /*!< SYS_T::IRCTIEN: TFAILIEN Position */
#define SYS_IRCTIEN_TFAILIEN_Msk (0x1ul << SYS_IRCTIEN_TFAILIEN_Pos) /*!< SYS_T::IRCTIEN: TFAILIEN Mask */
#define SYS_IRCTIEN_CLKEIEN_Pos (2) /*!< SYS_T::IRCTIEN: CLKEIEN Position */
#define SYS_IRCTIEN_CLKEIEN_Msk (0x1ul << SYS_IRCTIEN_CLKEIEN_Pos) /*!< SYS_T::IRCTIEN: CLKEIEN Mask */
#define SYS_IRCTISTS_FREQLOCK_Pos (0) /*!< SYS_T::IRCTISTS: FREQLOCK Position */
#define SYS_IRCTISTS_FREQLOCK_Msk (0x1ul << SYS_IRCTISTS_FREQLOCK_Pos) /*!< SYS_T::IRCTISTS: FREQLOCK Mask */
#define SYS_IRCTISTS_TFAILIF_Pos (1) /*!< SYS_T::IRCTISTS: TFAILIF Position */
#define SYS_IRCTISTS_TFAILIF_Msk (0x1ul << SYS_IRCTISTS_TFAILIF_Pos) /*!< SYS_T::IRCTISTS: TFAILIF Mask */
#define SYS_IRCTISTS_CLKERRIF_Pos (2) /*!< SYS_T::IRCTISTS: CLKERRIF Position */
#define SYS_IRCTISTS_CLKERRIF_Msk (0x1ul << SYS_IRCTISTS_CLKERRIF_Pos) /*!< SYS_T::IRCTISTS: CLKERRIF Mask */
#define SYS_REGLCTL_REGLCTL_Pos (0) /*!< SYS_T::REGLCTL: REGLCTL Position */
#define SYS_REGLCTL_REGLCTL_Msk (0x1ul << SYS_REGLCTL_REGLCTL_Pos) /*!< SYS_T::REGLCTL: REGLCTL Mask */
#define SYS_PLCTL_PLSEL_Pos (0) /*!< SYS_T::PLCTL: PLSEL Position */
#define SYS_PLCTL_PLSEL_Msk (0x3ul << SYS_PLCTL_PLSEL_Pos) /*!< SYS_T::PLCTL: PLSEL Mask */
#define SYS_PLCTL_LVSSTEP_Pos (16) /*!< SYS_T::PLCTL: LVSSTEP Position */
#define SYS_PLCTL_LVSSTEP_Msk (0x3ful << SYS_PLCTL_LVSSTEP_Pos) /*!< SYS_T::PLCTL: LVSSTEP Mask */
#define SYS_PLCTL_LVSPRD_Pos (24) /*!< SYS_T::PLCTL: LVSPRD Position */
#define SYS_PLCTL_LVSPRD_Msk (0xfful << SYS_PLCTL_LVSPRD_Pos) /*!< SYS_T::PLCTL: LVSPRD Mask */
#define SYS_PLSTS_PLCBUSY_Pos (0) /*!< SYS_T::PLSTS: PLCBUSY Position */
#define SYS_PLSTS_PLCBUSY_Msk (0x1ul << SYS_PLSTS_PLCBUSY_Pos) /*!< SYS_T::PLSTS: PLCBUSY Mask */
#define SYS_PLSTS_PLSTATUS_Pos (8) /*!< SYS_T::PLSTS: PLSTATUS Position */
#define SYS_PLSTS_PLSTATUS_Msk (0x3ul << SYS_PLSTS_PLSTATUS_Pos) /*!< SYS_T::PLSTS: PLSTATUS Mask */
#define SYS_AHBMCTL_INTACTEN_Pos (0) /*!< SYS_T::AHBMCTL: INTACTEN Position */
#define SYS_AHBMCTL_INTACTEN_Msk (0x1ul << SYS_AHBMCTL_INTACTEN_Pos) /*!< SYS_T::AHBMCTL: INTACTEN Mask */
/**@}*/ /* SYS_CONST */
/**@}*/ /* end of SYS register group */
/*---------------------- System Clock Controller -------------------------*/
/**
@addtogroup CLK System Clock Controller(CLK)
Memory Mapped Structure for CLK Controller
@{ */
typedef struct {
/**
* @var CLK_T::PWRCTL
* Offset: 0x00 System Power-down Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |HXTEN |HXT Enable Bit (Write Protect)
* | | |The bit default value is set by flash controller user configuration register CONFIG0 [26]
* | | |When the default clock source is from HXT, this bit is set to 1 automatically.
* | | |0 = 4~24 MHz external high speed crystal (HXT) Disabled.
* | | |1 = 4~24 MHz external high speed crystal (HXT) Enabled.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[1] |LXTEN |LXT Enable Bit (Write Protect)
* | | |0 = 32.768 kHz external low speed crystal (LXT) Disabled.
* | | |1 = 32.768 kHz external low speed crystal (LXT) Enabled.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[2] |HIRCEN |HIRC Enable Bit (Write Protect)
* | | |0 = 12 MHz internal high speed RC oscillator (HIRC) Disabled.
* | | |1 = 12 MHz internal high speed RC oscillator (HIRC) Enabled.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[3] |LIRCEN |LIRC Enable Bit (Write Protect)
* | | |0 = 10 kHz internal low speed RC oscillator (LIRC) Disabled.
* | | |1 = 10 kHz internal low speed RC oscillator (LIRC) Enabled.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[4] |PDWKDLY |Enable the Wake-up Delay Counter (Write Protect)
* | | |When the chip wakes up from Power-down mode, the clock control will delay certain clock cycles to wait system clock stable.
* | | |The delayed clock cycle is 4096 clock cycles when chip works at 4~24 MHz external high speed crystal oscillator (HXT), and 256 clock cycles when chip works at 12 MHz internal high speed RC oscillator (HIRC).
* | | |0 = Clock cycles delay Disabled.
* | | |1 = Clock cycles delay Enabled.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[5] |PDWKIEN |Power-down Mode Wake-up Interrupt Enable Bit (Write Protect)
* | | |0 = Power-down mode wake-up interrupt Disabled.
* | | |1 = Power-down mode wake-up interrupt Enabled.
* | | |Note1: The interrupt will occur when both PDWKIF and PDWKIEN are high.
* | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[6] |PDWKIF |Power-down Mode Wake-up Interrupt Status
* | | |Set by "Power-down wake-up event", it indicates that resume from Power-down mode.
* | | |The flag is set if any wake-up source is occurred. Refer Power Modes and Wake-up Sources chapter.
* | | |Note1: Write 1 to clear the bit to 0.
* | | |Note2: This bit works only if PDWKIEN (CLK_PWRCTL[5]) set to 1.
* |[7] |PDEN |System Power-down Enable (Write Protect)
* | | |When this bit is set to 1, Power-down mode is enabled and chip keeps active till the CPU sleep mode is also active and then the chip enters Power-down mode.
* | | |When chip wakes up from Power-down mode, this bit is auto cleared
* | | |Users need to set this bit again for next Power-down.
* | | |In Power-down mode, HXT and the HIRC will be disabled in this mode, but LXT and LIRC are not controlled by Power-down mode.
* | | |In Power-down mode, the PLL and system clock are disabled, and ignored the clock source selection
* | | |The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from LXT or LIRC.
* | | |0 = Chip will not enter Power-down mode after CPU sleep command WFI.
* | | |1 = Chip enters Power-down mode after CPU sleep command WFI.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[11:10] |HXTGAIN |HXT Gain Control Bit (Write Protect)
* | | |This is a protected register. Please refer to open lock sequence to program it.
* | | |Gain control is used to enlarge the gain of crystal to make sure crystal work normally
* | | |If gain control is enabled, crystal will consume more power than gain control off.
* | | |00 = HXT frequency is lower than from 8 MHz.
* | | |01 = HXT frequency is from 8 MHz to 12 MHz.
* | | |10 = HXT frequency is from 12 MHz to 16 MHz.
* | | |11 = HXT frequency is higher than 16 MHz.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[12] |HXTSELTYP |HXT Crystal Type Select Bit (Write Protect)
* | | |This is a protected register. Please refer to open lock sequence to program it.
* | | |0 = Select INV type.
* | | |1 = Select GM type.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[13] |HXTTBEN |HXT Crystal TURBO Mode (Write Protect)
* | | |This is a protected register. Please refer to open lock sequence to program it.
* | | |0 = HXT Crystal TURBO mode disabled.
* | | |1 = HXT Crystal TURBO mode enabled.
* |[17:16] |HIRCSTBS |HIRC Stable Count Select (Write Protect)
* | | |00 = HIRC stable count is 64 clocks.
* | | |01 = HIRC stable count is 24 clocks.
* | | |others = Reserved.
* @var CLK_T::AHBCLK
* Offset: 0x04 AHB Devices Clock Enable Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1] |PDMACKEN |PDMA Controller Clock Enable Bit
* | | |0 = PDMA peripheral clock Disabled.
* | | |1 = PDMA peripheral clock Enabled.
* |[2] |ISPCKEN |Flash ISP Controller Clock Enable Bit
* | | |0 = Flash ISP peripheral clock Disabled.
* | | |1 = Flash ISP peripheral clock Enabled.
* |[3] |EBICKEN |EBI Controller Clock Enable Bit
* | | |0 = EBI peripheral clock Disabled.
* | | |1 = EBI peripheral clock Enabled.
* |[5] |EMACCKEN |Ethernet Controller Clock Enable Bit
* | | |0 = Ethernet Controller engine clock Disabled.
* | | |1 = Ethernet Controller engine clock Enabled.
* |[6] |SDH0CKEN |SD0 Controller Clock Enable Bit
* | | |0 = SD0 engine clock Disabled.
* | | |1 = SD0 engine clock Enabled.
* |[7] |CRCCKEN |CRC Generator Controller Clock Enable Bit
* | | |0 = CRC peripheral clock Disabled.
* | | |1 = CRC peripheral clock Enabled.
* |[10] |HSUSBDCKEN|HSUSB Device Clock Enable Bit
* | | |0 = HSUSB device controller's clock Disabled.
* | | |1 = HSUSB device controller's clock Enabled.
* |[12] |CRPTCKEN |Cryptographic Accelerator Clock Enable Bit
* | | |0 = Cryptographic Accelerator clock Disabled.
* | | |1 = Cryptographic Accelerator clock Enabled.
* |[14] |SPIMCKEN |SPIM Controller Clock Enable Bit
* | | |0 = SPIM controller clock Disabled.
* | | |1 = SPIM controller clock Enabled.
* |[15] |FMCIDLE |Flash Memory Controller Clock Enable Bit in IDLE Mode
* | | |0 = FMC clock Disabled when chip is under IDLE mode.
* | | |1 = FMC clock Enabled when chip is under IDLE mode.
* |[16] |USBHCKEN |USB HOST Controller Clock Enable Bit
* | | |0 = USB HOST peripheral clock Disabled.
* | | |1 = USB HOST peripheral clock Enabled.
* |[17] |SDH1CKEN |SD1 Controller Clock Enable Bit
* | | |0 = SD1 engine clock Disabled.
* | | |1 = SD1 engine clock Enabled.
* @var CLK_T::APBCLK0
* Offset: 0x08 APB Devices Clock Enable Control Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |WDTCKEN |Watchdog Timer Clock Enable Bit (Write Protect)
* | | |0 = Watchdog timer clock Disabled.
* | | |1 = Watchdog timer clock Enabled.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[1] |RTCCKEN |Real-time-clock APB Interface Clock Enable Bit
* | | |This bit is used to control the RTC APB clock only
* | | |The RTC peripheral clock source is selected from RTCSEL(CLK_CLKSEL3[8])
* | | |It can be selected to 32.768 kHz external low speed crystal or 10 kHz internal low speed RC oscillator (LIRC).
* | | |0 = RTC clock Disabled.
* | | |1 = RTC clock Enabled.
* |[2] |TMR0CKEN |Timer0 Clock Enable Bit
* | | |0 = Timer0 clock Disabled.
* | | |1 = Timer0 clock Enabled.
* |[3] |TMR1CKEN |Timer1 Clock Enable Bit
* | | |0 = Timer1 clock Disabled.
* | | |1 = Timer1 clock Enabled.
* |[4] |TMR2CKEN |Timer2 Clock Enable Bit
* | | |0 = Timer2 clock Disabled.
* | | |1 = Timer2 clock Enabled.
* |[5] |TMR3CKEN |Timer3 Clock Enable Bit
* | | |0 = Timer3 clock Disabled.
* | | |1 = Timer3 clock Enabled.
* |[6] |CLKOCKEN |CLKO Clock Enable Bit
* | | |0 = CLKO clock Disabled.
* | | |1 = CLKO clock Enabled.
* |[7] |ACMP01CKEN|Analog Comparator 0/1 Clock Enable Bit
* | | |0 = Analog comparator 0/1 clock Disabled.
* | | |1 = Analog comparator 0/1 clock Enabled.
* |[8] |I2C0CKEN |I2C0 Clock Enable Bit
* | | |0 = I2C0 clock Disabled.
* | | |1 = I2C0 clock Enabled.
* |[9] |I2C1CKEN |I2C1 Clock Enable Bit
* | | |0 = I2C1 clock Disabled.
* | | |1 = I2C1 clock Enabled.
* |[10] |I2C2CKEN |I2C2 Clock Enable Bit
* | | |0 = I2C2 clock Disabled.
* | | |1 = I2C2 clock Enabled.
* |[12] |SPI0CKEN |SPI0 Clock Enable Bit
* | | |0 = SPI0 clock Disabled.
* | | |1 = SPI0 clock Enabled.
* |[13] |SPI1CKEN |SPI1 Clock Enable Bit
* | | |0 = SPI1 clock Disabled.
* | | |1 = SPI1 clock Enabled.
* |[14] |SPI2CKEN |SPI2 Clock Enable Bit
* | | |0 = SPI2 clock Disabled.
* | | |1 = SPI2 clock Enabled.
* |[15] |SPI3CKEN |SPI3 Clock Enable Bit
* | | |0 = SPI3 clock Disabled.
* | | |1 = SPI3 clock Enabled.
* |[16] |UART0CKEN |UART0 Clock Enable Bit
* | | |0 = UART0 clock Disabled.
* | | |1 = UART0 clock Enabled.
* |[17] |UART1CKEN |UART1 Clock Enable Bit
* | | |0 = UART1 clock Disabled.
* | | |1 = UART1 clock Enabled.
* |[18] |UART2CKEN |UART2 Clock Enable Bit
* | | |0 = UART2 clock Disabled.
* | | |1 = UART2 clock Enabled.
* |[19] |UART3CKEN |UART3 Clock Enable Bit
* | | |0 = UART3 clock Disabled.
* | | |1 = UART3 clock Enabled.
* |[20] |UART4CKEN |UART4 Clock Enable Bit
* | | |0 = UART4 clock Disabled.
* | | |1 = UART4 clock Enabled.
* |[21] |UART5CKEN |UART5 Clock Enable Bit
* | | |0 = UART5 clock Disabled.
* | | |1 = UART5 clock Enabled.
* |[24] |CAN0CKEN |CAN0 Clock Enable Bit
* | | |0 = CAN0 clock Disabled.
* | | |1 = CAN0 clock Enabled.
* |[25] |CAN1CKEN |CAN1 Clock Enable Bit
* | | |0 = CAN1 clock Disabled.
* | | |1 = CAN1 clock Enabled.
* |[26] |OTGCKEN |USB OTG Clock Enable Bit
* | | |0 = USB OTG clock Disabled.
* | | |1 = USB OTG clock Enabled.
* |[27] |USBDCKEN |USB Device Clock Enable Bit
* | | |0 = USB Device clock Disabled.
* | | |1 = USB Device clock Enabled.
* |[28] |EADCCKEN |Enhanced Analog-digital-converter (EADC) Clock Enable Bit
* | | |0 = EADC clock Disabled.
* | | |1 = EADC clock Enabled.
* |[29] |I2S0CKEN |I2S0 Clock Enable Bit
* | | |0 = I2S0 Clock Disabled.
* | | |1 = I2S0 Clock Enabled.
* |[30] |HSOTGCKEN |HSUSB OTG Clock Enable Bit
* | | |0 = HSUSB OTG clock Disabled.
* | | |1 = HSUSB OTG clock Enabled.
* @var CLK_T::APBCLK1
* Offset: 0x0C APB Devices Clock Enable Control Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SC0CKEN |SC0 Clock Enable Bit
* | | |0 = SC0 clock Disabled.
* | | |1 = SC0 clock Enabled.
* |[1] |SC1CKEN |SC1 Clock Enable Bit
* | | |0 = SC1 clock Disabled.
* | | |1 = SC1 clock Enabled.
* |[2] |SC2CKEN |SC2 Clock Enable Bit
* | | |0 = SC2 clock Disabled.
* | | |1 = SC2 clock Enabled.
* |[6] |SPI4CKEN |SPI4 Clock Enable Bit
* | | |0 = SPI4 clock Disabled.
* | | |1 = SPI4 clock Enabled.
* |[8] |USCI0CKEN |USCI0 Clock Enable Bit
* | | |0 = USCI0 clock Disabled.
* | | |1 = USCI0 clock Enabled.
* |[9] |USCI1CKEN |USCI1 Clock Enable Bit
* | | |0 = USCI1 clock Disabled.
* | | |1 = USCI1 clock Enabled.
* |[12] |DACCKEN |DAC Clock Enable Bit
* | | |0 = DAC clock Disabled.
* | | |1 = DAC clock Enabled.
* |[16] |EPWM0CKEN |EPWM0 Clock Enable Bit
* | | |0 = EPWM0 clock Disabled.
* | | |1 = EPWM0 clock Enabled.
* |[17] |EPWM1CKEN |EPWM1 Clock Enable Bit
* | | |0 = EPWM1 clock Disabled.
* | | |1 = EPWM1 clock Enabled.
* |[18] |BPWM0CKEN |BPWM0 Clock Enable Bit
* | | |0 = BPWM0 clock Disabled.
* | | |1 = BPWM0 clock Enabled.
* |[19] |BPWM1CKEN |BPWM1 Clock Enable Bit
* | | |0 = BPWM1 clock Disabled.
* | | |1 = BPWM1 clock Enabled.
* |[22] |QEI0CKEN |QEI0 Clock Enable Bit
* | | |0 = QEI0 clock Disabled.
* | | |1 = QEI0 clock Enabled.
* |[23] |QEI1CKEN |QEI1 Clock Enable Bit
* | | |0 = QEI1 clock Disabled.
* | | |1 = QEI1 clock Enabled.
* |[26] |ECAP0CKEN |ECAP0 Clock Enable Bit
* | | |0 = ECAP0 clock Disabled.
* | | |1 = ECAP0 clock Enabled.
* |[27] |ECAP1CKEN |ECAP1 Clock Enable Bit
* | | |0 = ECAP1 clock Disabled.
* | | |1 = ECAP1 clock Enabled.
* |[30] |OPACKEN |OP Amplifier (OPA) Clock Enable Bit
* | | |0 = OPA clock Disabled.
* | | |1 = OPA clock Enabled.
* @var CLK_T::CLKSEL0
* Offset: 0x10 Clock Source Select Control Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[2:0] |HCLKSEL |HCLK Clock Source Selection (Write Protect)
* | | |Before clock switching, the related clock sources (both pre-select and new-select) must be turned on.
* | | |The default value is reloaded from the value of CFOSC (CONFIG0[26]) in user configuration register of Flash controller by any reset
* | | |Therefore the default value is either 000b or 111b.
* | | |000 = Clock source from HXT.
* | | |001 = Clock source from LXT.
* | | |010 = Clock source from PLL.
* | | |011 = Clock source from LIRC.
* | | |111 = Clock source from HIRC.
* | | |Other = Reserved.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[5:3] |STCLKSEL |Cortex-M4 SysTick Clock Source Selection (Write Protect)
* | | |If SYST_CTRL[2]=0, SysTick uses listed clock source below.
* | | |000 = Clock source from HXT.
* | | |001 = Clock source from LXT.
* | | |010 = Clock source from HXT/2.
* | | |011 = Clock source from HCLK/2.
* | | |111 = Clock source from HIRC/2.
* | | |Note: if SysTick clock source is not from HCLK (i.e
* | | |SYST_CTRL[2] = 0), SysTick clock source must less than or equal to HCLK/2.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[21:20] |SDH0SEL |SD0 Engine Clock Source Selection (Write Protect)
* | | |00 = Clock source from HXT clock.
* | | |01 = Clock source from PLL clock.
* | | |10 = Clock source from HCLK.
* | | |11 = Clock source from HIRC clock.
* |[23:22] |SDH1SEL |SD1 Engine Clock Source Selection (Write Protect)
* | | |00 = Clock source from HXT clock.
* | | |01 = Clock source from PLL clock.
* | | |10 = Clock source from HCLK.
* | | |11 = Clock source from HIRC clock.
* @var CLK_T::CLKSEL1
* Offset: 0x14 Clock Source Select Control Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1:0] |WDTSEL |Watchdog Timer Clock Source Selection (Write Protect)
* | | |00 = Reserved.
* | | |01 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
* | | |10 = Clock source from HCLK/2048.
* | | |11 = Clock source from 10 kHz internal low speed RC oscillator (LIRC).
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[10:8] |TMR0SEL |TIMER0 Clock Source Selection
* | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
* | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
* | | |010 = Clock source from PCLK0.
* | | |011 = Clock source from external clock TM0 pin.
* | | |101 = Clock source from 10 kHz internal low speed RC oscillator (LIRC).
* | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
* | | |Others = Reserved.
* |[14:12] |TMR1SEL |TIMER1 Clock Source Selection
* | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
* | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
* | | |010 = Clock source from PCLK0.
* | | |011 = Clock source from external clock TM1 pin.
* | | |101 = Clock source from 10 kHz internal low speed RC oscillator (LIRC).
* | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
* | | |Others = Reserved.
* |[18:16] |TMR2SEL |TIMER2 Clock Source Selection
* | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
* | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
* | | |010 = Clock source from PCLK1.
* | | |011 = Clock source from external clock TM2 pin.
* | | |101 = Clock source from 10 kHz internal low speed RC oscillator (LIRC).
* | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
* | | |Others = Reserved.
* |[22:20] |TMR3SEL |TIMER3 Clock Source Selection
* | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
* | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
* | | |010 = Clock source from PCLK1.
* | | |011 = Clock source from external clock TM3 pin.
* | | |101 = Clock source from 10 kHz internal low speed RC oscillator (LIRC).
* | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
* | | |Others = Reserved.
* |[25:24] |UART0SEL |UART0 Clock Source Selection
* | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
* | | |01 = Clock source from PLL.
* | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
* | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
* |[27:26] |UART1SEL |UART1 Clock Source Selection
* | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
* | | |01 = Clock source from PLL.
* | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
* | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
* |[29:28] |CLKOSEL |Clock Divider Clock Source Selection
* | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
* | | |01 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
* | | |10 = Clock source from HCLK.
* | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
* |[31:30] |WWDTSEL |Window Watchdog Timer Clock Source Selection
* | | |10 = Clock source from HCLK/2048.
* | | |11 = Clock source from 10 kHz internal low speed RC oscillator (LIRC).
* | | |Others = Reserved.
* @var CLK_T::CLKSEL2
* Offset: 0x18 Clock Source Select Control Register 2
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |EPWM0SEL |EPWM0 Clock Source Selection
* | | |The peripheral clock source of EPWM0 is defined by EPWM0SEL.
* | | |0 = Clock source from PLL.
* | | |1 = Clock source from PCLK0.
* |[1] |EPWM1SEL |EPWM1 Clock Source Selection
* | | |The peripheral clock source of EPWM1 is defined by EPWM1SEL.
* | | |0 = Clock source from PLL.
* | | |1 = Clock source from PCLK1.
* |[3:2] |SPI0SEL |SPI0 Clock Source Selection
* | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
* | | |01 = Clock source from PLL.
* | | |10 = Clock source from PCLK0.
* | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
* |[5:4] |SPI1SEL |SPI1 Clock Source Selection
* | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
* | | |01 = Clock source from PLL.
* | | |10 = Clock source from PCLK1.
* | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
* |[7:6] |SPI2SEL |SPI2 Clock Source Selection
* | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
* | | |01 = Clock source from PLL.
* | | |10 = Clock source from PCLK0.
* | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
* |[8] |BPWM0SEL |BPWM0 Clock Source Selection
* | | |The peripheral clock source of BPWM0 is defined by BPWM0SEL.
* | | |0 = Clock source from PLL.
* | | |1 = Clock source from PCLK0.
* |[9] |BPWM1SEL |BPWM1 Clock Source Selection
* | | |The peripheral clock source of BPWM1 is defined by BPWM1SEL.
* | | |0 = Clock source from PLL.
* | | |1 = Clock source from PCLK1.
* |[11:10] |SPI3SEL |SPI3 Clock Source Selection
* | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
* | | |01 = Clock source from PLL.
* | | |10 = Clock source from PCLK1.
* | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
* |[13:12] |SPI4SEL |SPI4 Clock Source Selection
* | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
* | | |01 = Clock source from PLL.
* | | |10 = Clock source from PCLK0.
* | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
* @var CLK_T::CLKSEL3
* Offset: 0x1C Clock Source Select Control Register 3
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1:0] |SC0SEL |SC0 Clock Source Selection
* | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
* | | |01 = Clock source from PLL.
* | | |10 = Clock source from PCLK0.
* | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
* |[3:2] |SC1SEL |SC0 Clock Source Selection
* | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
* | | |01 = Clock source from PLL.
* | | |10 = Clock source from PCLK1.
* | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
* |[5:4] |SC2SEL |SC2 Clock Source Selection
* | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
* | | |01 = Clock source from PLL.
* | | |10 = Clock source from PCLK0.
* | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
* |[8] |RTCSEL |RTC Clock Source Selection
* | | |0 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
* | | |1 = Clock source from 10 kHz internal low speed RC oscillator (LIRC).
* |[17:16] |I2S0SEL |I2S0 Clock Source Selection
* | | |00 = Clock source from HXT clock.
* | | |01 = Clock source from PLL clock.
* | | |10 = Clock source from PCLK.
* | | |11 = Clock source from HIRC clock.
* |[25:24] |UART2SEL |UART2 Clock Source Selection
* | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
* | | |01 = Clock source from PLL.
* | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
* | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
* |[27:26] |UART3SEL |UART3 Clock Source Selection
* | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
* | | |01 = Clock source from PLL.
* | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
* | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
* |[29:28] |UART4SEL |UART4 Clock Source Selection
* | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
* | | |01 = Clock source from PLL.
* | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
* | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
* |[31:30] |UART5SEL |UART5 Clock Source Selection
* | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
* | | |01 = Clock source from PLL.
* | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
* | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
* @var CLK_T::CLKDIV0
* Offset: 0x20 Clock Divider Number Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |HCLKDIV |HCLK Clock Divide Number From HCLK Clock Source
* | | |HCLK clock frequency = (HCLK clock source frequency) / (HCLKDIV + 1).
* |[7:4] |USBDIV |USB Clock Divide Number From PLL Clock
* | | |USB clock frequency = (PLL frequency) / (USBDIV + 1).
* |[11:8] |UART0DIV |UART0 Clock Divide Number From UART0 Clock Source
* | | |UART0 clock frequency = (UART0 clock source frequency) / (UART0DIV + 1).
* |[15:12] |UART1DIV |UART1 Clock Divide Number From UART1 Clock Source
* | | |UART1 clock frequency = (UART1 clock source frequency) / (UART1DIV + 1).
* |[23:16] |EADCDIV |EADC Clock Divide Number From EADC Clock Source
* | | |EADC clock frequency = (EADC clock source frequency) / (EADCDIV + 1).
* |[31:24] |SDH0DIV |SD0 Clock Divide Number From SD0 Clock Source
* | | |SD0 clock frequency = (SD0 clock source frequency) / (SDH0DIV + 1).
* @var CLK_T::CLKDIV1
* Offset: 0x24 Clock Divider Number Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |SC0DIV |SC0 Clock Divide Number From SC0 Clock Source
* | | |SC0 clock frequency = (SC0 clock source frequency ) / (SC0DIV + 1).
* |[15:8] |SC1DIV |SC1 Clock Divide Number From SC1 Clock Source
* | | |SC1 clock frequency = (SC1 clock source frequency ) / (SC1DIV + 1).
* |[23:16] |SC2DIV |SC2 Clock Divide Number From SC2 Clock Source
* | | |SC2 clock frequency = (SC2 clock source frequency ) / (SC2DIV + 1).
* @var CLK_T::CLKDIV3
* Offset: 0x2C Clock Divider Number Register 3
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[23:16] |EMACDIV |Ethernet Clock Divide Number Form HCLK
* | | |EMAC MDCLK clock frequency = (HCLK) / (EMACDIV + 1).
* |[31:24] |SDH1DIV |SD1 Clock Divide Number From SD1 Clock Source
* | | |SD1 clock frequency = (SD1 clock source frequency) / (SDH1DIV + 1).
* @var CLK_T::CLKDIV4
* Offset: 0x30 Clock Divider Number Register 4
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |UART2DIV |UART2 Clock Divide Number From UART2 Clock Source
* | | |UART2 clock frequency = (UART2 clock source frequency) / (UART2DIV + 1).
* |[7:4] |UART3DIV |UART3 Clock Divide Number From UART3 Clock Source
* | | |UART3 clock frequency = (UART3 clock source frequency) / (UART3DIV + 1).
* |[11:8] |UART4DIV |UART4 Clock Divide Number From UART4 Clock Source
* | | |UART4 clock frequency = (UART4 clock source frequency) / (UART4DIV + 1).
* |[15:12] |UART5DIV |UART5 Clock Divide Number From UART5 Clock Source
* | | |UART5 clock frequency = (UART5 clock source frequency) / (UART5DIV + 1).
* @var CLK_T::PCLKDIV
* Offset: 0x34 APB Clock Divider Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[2:0] |APB0DIV |APB0 Clock Divider
* | | |APB0 clock can be divided from HCLK
* | | |000: PCLK0 = HCLK.
* | | |001: PCLK0 = 1/2 HCLK.
* | | |010: PCLK0 = 1/4 HCLK.
* | | |011: PCLK0 = 1/8 HCLK.
* | | |100: PCLK0 = 1/16 HCLK.
* | | |Others: Reserved.
* |[6:4] |APB1DIV |APB1 Clock Divider
* | | |APB1 clock can be divided from HCLK
* | | |000: PCLK1 = HCLK.
* | | |001: PCLK1 = 1/2 HCLK.
* | | |010: PCLK1 = 1/4 HCLK.
* | | |011: PCLK1 = 1/8 HCLK.
* | | |100: PCLK1 = 1/16 HCLK.
* | | |Others: Reserved.
* @var CLK_T::PLLCTL
* Offset: 0x40 PLL Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[8:0] |FBDIV |PLL Feedback Divider Control (Write Protect)
* | | |Refer to the formulas below the table.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[13:9] |INDIV |PLL Input Divider Control (Write Protect)
* | | |Refer to the formulas below the table.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[15:14] |OUTDIV |PLL Output Divider Control (Write Protect)
* | | |Refer to the formulas below the table.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[16] |PD |Power-down Mode (Write Protect)
* | | |If set the PDEN bit to 1 in CLK_PWRCTL register, the PLL will enter Power-down mode, too.
* | | |0 = PLL is in normal mode.
* | | |1 = PLL is in Power-down mode (default).
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[17] |BP |PLL Bypass Control (Write Protect)
* | | |0 = PLL is in normal mode (default).
* | | |1 = PLL clock output is same as PLL input clock FIN.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[18] |OE |PLL OE (FOUT Enable) Pin Control (Write Protect)
* | | |0 = PLL FOUT Enabled.
* | | |1 = PLL FOUT is fixed low.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[19] |PLLSRC |PLL Source Clock Selection (Write Protect)
* | | |0 = PLL source clock from 4~24 MHz external high-speed crystal oscillator (HXT).
* | | |1 = PLL source clock from 12 MHz internal high-speed oscillator (HIRC).
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[23] |STBSEL |PLL Stable Counter Selection (Write Protect)
* | | |0 = PLL stable time is 6144 PLL source clock (suitable for source clock is equal to or less than 12 MHz).
* | | |1 = PLL stable time is 12288 PLL source clock (suitable for source clock is larger than 12 MHz).
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[28] |BANDSEL |PLL Stable Counter Selection (Write Protect)
* | | |0 = PLL low band frequency select. (FVCO range is 200MHz ~ 400MHZ)
* | | |1 = PLL high band frequency select. (FVCO range is 400MHz ~ 500MHZ)
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* @var CLK_T::STATUS
* Offset: 0x50 Clock Status Monitor Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |HXTSTB |HXT Clock Source Stable Flag (Read Only)
* | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock is not stable or disabled.
* | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock is stable and enabled.
* |[1] |LXTSTB |LXT Clock Source Stable Flag (Read Only)
* | | |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock is not stable or disabled.
* | | |1 = 32.768 kHz external low speed crystal oscillator (LXT) clock is stabled and enabled.
* |[2] |PLLSTB |Internal PLL Clock Source Stable Flag (Read Only)
* | | |0 = Internal PLL clock is not stable or disabled.
* | | |1 = Internal PLL clock is stable and enabled.
* |[3] |LIRCSTB |LIRC Clock Source Stable Flag (Read Only)
* | | |0 = 10 kHz internal low speed RC oscillator (LIRC) clock is not stable or disabled.
* | | |1 = 10 kHz internal low speed RC oscillator (LIRC) clock is stable and enabled.
* |[4] |HIRCSTB |HIRC Clock Source Stable Flag (Read Only)
* | | |0 = 12 MHz internal high speed RC oscillator (HIRC) clock is not stable or disabled.
* | | |1 = 12 MHz internal high speed RC oscillator (HIRC) clock is stable and enabled.
* | | |Note: This bit is read only.
* |[7] |CLKSFAIL |Clock Switching Fail Flag (Read Only)
* | | |This bit is updated when software switches system clock source
* | | |If switch target clock is stable, this bit will be set to 0
* | | |If switch target clock is not stable, this bit will be set to 1.
* | | |0 = Clock switching success.
* | | |1 = Clock switching failure.
* | | |Note: Write 1 to clear the bit to 0.
* @var CLK_T::CLKOCTL
* Offset: 0x60 Clock Output Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |FREQSEL |Clock Output Frequency Selection
* | | |The formula of output frequency is
* | | |Fout = Fin/2(N+1).
* | | |Fin is the input clock frequency.
* | | |Fout is the frequency of divider output clock.
* | | |N is the 4-bit value of FREQSEL[3:0].
* |[4] |CLKOEN |Clock Output Enable Bit
* | | |0 = Clock Output function Disabled.
* | | |1 = Clock Output function Enabled.
* |[5] |DIV1EN |Clock Output Divide One Enable Bit
* | | |0 = Clock Output will output clock with source frequency divided by FREQSEL.
* | | |1 = Clock Output will output clock with source frequency.
* |[6] |CLK1HZEN |Clock Output 1Hz Enable Bit
* | | |0 = 1 Hz clock output for 32.768 kHz frequency compensation Disabled.
* | | |1 = 1 Hz clock output for 32.768 kHz frequency compensation Enabled.
* @var CLK_T::CLKDCTL
* Offset: 0x70 Clock Fail Detector Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[4] |HXTFDEN |HXT Clock Fail Detector Enable Bit
* | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail detector Disabled.
* | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail detector Enabled.
* |[5] |HXTFIEN |HXT Clock Fail Interrupt Enable Bit
* | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail interrupt Disabled.
* | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail interrupt Enabled.
* |[12] |LXTFDEN |LXT Clock Fail Detector Enable Bit
* | | |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail detector Disabled.
* | | |1 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail detector Enabled.
* |[13] |LXTFIEN |LXT Clock Fail Interrupt Enable Bit
* | | |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail interrupt Disabled.
* | | |1 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail interrupt Enabled.
* |[16] |HXTFQDEN |HXT Clock Frequency Range Detector Enable Bit
* | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency range detector Disabled.
* | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency range detector Enabled.
* |[17] |HXTFQIEN |HXT Clock Frequency Range Detector Interrupt Enable Bit
* | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency range detector fail interrupt Disabled.
* | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency range detector fail interrupt Enabled.
* @var CLK_T::CLKDSTS
* Offset: 0x74 Clock Fail Detector Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |HXTFIF |HXT Clock Fail Interrupt Flag
* | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock is normal.
* | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock stops.
* | | |Note: Write 1 to clear the bit to 0.
* |[1] |LXTFIF |LXT Clock Fail Interrupt Flag
* | | |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock is normal.
* | | |1 = 32.768 kHz external low speed crystal oscillator (LXT) stops.
* | | |Note: Write 1 to clear the bit to 0.
* |[8] |HXTFQIF |HXT Clock Frequency Range Detector Interrupt Flag
* | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency is normal.
* | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency is abnormal.
* | | |Note: Write 1 to clear the bit to 0.
* @var CLK_T::CDUPB
* Offset: 0x78 Clock Frequency Range Detector Upper Boundary Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[9:0] |UPERBD |HXT Clock Frequency Range Detector Upper Boundary Value
* | | |The bits define the maximum value of frequency range detector window.
* | | |When HXT frequency higher than this maximum frequency value, the HXT Clock Frequency Range Detector Interrupt Flag will set to 1.
* @var CLK_T::CDLOWB
* Offset: 0x7C Clock Frequency Range Detector Lower Boundary Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[9:0] |LOWERBD |HXT Clock Frequency Range Detector Lower Boundary Value
* | | |The bits define the minimum value of frequency range detector window.
* | | |When HXT frequency lower than this minimum frequency value, the HXT Clock Frequency Range Detector Interrupt Flag will set to 1.
* @var CLK_T::PMUCTL
* Offset: 0x90 Power Manager Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[2:0] |PDMSEL |Power-down Mode Selection (Write Protect)
* | | |This is a protected register. Please refer to open lock sequence to program it.
* | | |These bits control chip power-down mode grade selection when CPU execute WFI/WFE instruction.
* | | |000 = Power-down mode is selected. (PD)
* | | |001 = Low leakage Power-down mode is selected (LLPD).
* | | |010 =Fast wake-up Power-down mode is selected (FWPD).
* | | |011 = Reserved.
* | | |100 = Standby Power-down mode 0 is selected (SPD0) (SRAM retention).
* | | |101 = Standby Power-down mode 1 is selected (SPD1).
* | | |110 = Deep Power-down mode is selected (DPD).
* | | |111 = Reserved.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[8] |WKTMREN |Wake-up Timer Enable (Write Protect)
* | | |This is a protected register. Please refer to open lock sequence to program it.
* | | |0 = Wake-up timer disable at DPD/SPD mode.
* | | |1 = Wake-up timer enabled at DPD/SPD mode.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[11:9] |WKTMRIS |Wake-up Timer Time-out Interval Select (Write Protect)
* | | |This is a protected register. Please refer to open lock sequence to program it.
* | | |These bits control wake-up timer time-out interval when chip at DPD/SPD mode.
* | | |000 = Time-out interval is 128 OSC10K clocks (12.8 ms).
* | | |001 = Time-out interval is 256 OSC10K clocks (25.6 ms).
* | | |010 = Time-out interval is 512 OSC10K clocks (51.2 ms).
* | | |011 = Time-out interval is 1024 OSC10K clocks (102.4ms).
* | | |100 = Time-out interval is 4096 OSC10K clocks (409.6ms).
* | | |101 = Time-out interval is 8192 OSC10K clocks (819.2ms).
* | | |110 = Time-out interval is 16384 OSC10K clocks (1638.4ms).
* | | |111 = Time-out interval is 65536 OSC10K clocks (6553.6ms).
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[17:16] |WKPINEN |Wake-up Pin Enable (Write Protect)
* | | |This is a protected register. Please refer to open lock sequence to program it.
* | | |00 = Wake-up pin disable at Deep Power-down mode.
* | | |01 = Wake-up pin rising edge enabled at Deep Power-down mode.
* | | |10 = Wake-up pin falling edge enabled at Deep Power-down mode.
* | | |11 = Wake-up pin both edge enabled at Deep Power-down mode.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[18] |ACMPSPWK |ACMP Standby Power-down Mode Wake-up Enable (Write Protect)
* | | |This is a protected register. Please refer to open lock sequence to program it.
* | | |0 = ACMP wake-up disable at Standby Power-down mode.
* | | |1 = ACMP wake-up enabled at Standby Power-down mode.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[23] |RTCWKEN |RTC Wake-up Enable (Write Protect)
* | | |This is a protected register. Please refer to open lock sequence to program it.
* | | |0 = RTC wake-up disable at Deep Power-down mode or Standby Power-down mode.
* | | |1 = RTC wake-up enabled at Deep Power-down mode or Standby Power-down mode.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* @var CLK_T::PMUSTS
* Offset: 0x94 Power Manager Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |PINWK |Pin Wake-up Flag (Read Only)
* | | |This flag indicates that wake-up of chip from Deep Power-down mode was requested by a transition of the WAKEUP pin (GPC.0)
* | | |This flag is cleared when DPD mode is entered.
* |[1] |TMRWK |Timer Wake-up Flag (Read Only)
* | | |This flag indicates that wake-up of chip from Deep Power-down mode (DPD) or Standby Power-down (SPD) mode was requested by wakeup timer time-out
* | | |This flag is cleared when DPD or SPD mode is entered.
* |[2] |RTCWK |RTC Wake-up Flag (Read Only)
* | | |This flag indicates that wakeup of device from Deep Power-down mode (DPD) or Standby Power-down (SPD) mode was requested with a RTC alarm, tick time or tamper happened
* | | |This flag is cleared when DPD or SPD mode is entered.
* |[8] |GPAWK |GPA Wake-up Flag (Read Only)
* | | |This flag indicates that wake-up of chip from Standby Power-down mode was requested by a transition of selected one GPA group pins
* | | |This flag is cleared when SPD mode is entered.
* |[9] |GPBWK |GPB Wake-up Flag (Read Only)
* | | |This flag indicates that wake-up of chip from Standby Power-down mode was requested by a transition of selected one GPB group pins
* | | |This flag is cleared when SPD mode is entered.
* |[10] |GPCWK |GPC Wake-up Flag (Read Only)
* | | |This flag indicates that wake-up of chip from Standby Power-down mode was requested by a transition of selected one GPC group pins
* | | |This flag is cleared when SPD mode is entered.
* |[11] |GPDWK |GPD Wake-up Flag (Read Only)
* | | |This flag indicates that wake-up of chip from Standby Power-down mode was requested by a transition of selected one GPD group pins
* | | |This flag is cleared when SPD mode is entered.
* |[12] |LVRWK |LVR Wake-up Flag (Read Only)
* | | |This flag indicates that wakeup of device from Standby Power-down mode was requested with a LVR happened
* | | |This flag is cleared when SPD mode is entered.
* |[13] |BODWK |BOD Wake-up Flag (Read Only)
* | | |This flag indicates that wakeup of device from Standby Power-down mode (SPD) was requested with a BOD happened
* | | |This flag is cleared when SPD mode is entered.
* |[14] |ACMPWK |ACMP Wake-up Flag (Read Only)
* | | |This flag indicates that wakeup of device from Standby Power-down mode (SPD) was requested with a ACMP transition
* | | |This flag is cleared when SPD mode is entered.
* |[31] |CLRWK |Clear Wake-up Flag
* | | |0 = No clear.
* | | |1= Clear all wake-up flag.
* @var CLK_T::SWKDBCTL
* Offset: 0x9C Standby Power-down Wake-up De-bounce Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |SWKDBCLKSEL|Standby Power-down Wake-up De-bounce Sampling Cycle Selection
* | | |0000 = Sample wake-up input once per 1 clocks.
* | | |0001 = Sample wake-up input once per 2 clocks.
* | | |0010 = Sample wake-up input once per 4 clocks.
* | | |0011 = Sample wake-up input once per 8 clocks.
* | | |0100 = Sample wake-up input once per 16 clocks.
* | | |0101 = Sample wake-up input once per 32 clocks.
* | | |0110 = Sample wake-up input once per 64 clocks.
* | | |0111 = Sample wake-up input once per 128 clocks.
* | | |1000 = Sample wake-up input once per 256 clocks.
* | | |1001 = Sample wake-up input once per 2*256 clocks.
* | | |1010 = Sample wake-up input once per 4*256 clocks.
* | | |1011 = Sample wake-up input once per 8*256 clocks.
* | | |1100 = Sample wake-up input once per 16*256 clocks.
* | | |1101 = Sample wake-up input once per 32*256 clocks.
* | | |1110 = Sample wake-up input once per 64*256 clocks.
* | | |1111 = Sample wake-up input once per 128*256 clocks.
* | | |Note: De-bounce counter clock source is the 10 kHz internal low speed RC oscillator (LIRC).
* @var CLK_T::PASWKCTL
* Offset: 0xA0 GPA Standby Power-down Wake-up Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |WKEN |Standby Power-down Pin Wake-up Enable Bit
* | | |0 = GPA group pin wake-up function disabled.
* | | |1 = GPA group pin wake-up function enabled.
* |[1] |PRWKEN |Pin Rising Edge Wake-up Enable Bit
* | | |0 = GPA group pin rising edge wake-up function disabled.
* | | |1 = GPA group pin rising edge wake-up function enabled.
* |[2] |PFWKEN |Pin Falling Edge Wake-up Enable Bit
* | | |0 = GPA group pin falling edge wake-up function disabled.
* | | |1 = GPA group pin falling edge wake-up function enabled.
* |[7:4] |WKPSEL |GPA Standby Power-down Wake-up Pin Select
* | | |0000 = GPA.0 wake-up function enabled.
* | | |0001 = GPA.1 wake-up function enabled.
* | | |0010 = GPA.2 wake-up function enabled.
* | | |0011 = GPA.3 wake-up function enabled.
* | | |0100 = GPA.4 wake-up function enabled.
* | | |0101 = GPA.5 wake-up function enabled.
* | | |0110 = GPA.6 wake-up function enabled.
* | | |0111 = GPA.7 wake-up function enabled.
* | | |1000 = GPA.8 wake-up function enabled.
* | | |1001 = GPA.9 wake-up function enabled.
* | | |1010 = GPA.10 wake-up function enabled.
* | | |1011 = GPA.11 wake-up function enabled.
* | | |1100 = GPA.12 wake-up function enabled.
* | | |1101 = GPA.13 wake-up function enabled.
* | | |1110 = GPA.14 wake-up function enabled.
* | | |1111 = GPA.15 wake-up function enabled.
* |[8] |DBEN |GPA Input Signal De-bounce Enable Bit
* | | |The DBEN bit is used to enable the de-bounce function for each corresponding IO
* | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wake-up
* | | |The de-bounce clock source is the 10 kHz internal low speed RC oscillator.
* | | |0 = Standby power-down wake-up pin De-bounce function disable.
* | | |1 = Standby power-down wake-up pin De-bounce function enable.
* | | |The de-bounce function is valid only for edge triggered.
* @var CLK_T::PBSWKCTL
* Offset: 0xA4 GPB Standby Power-down Wake-up Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |WKEN |Standby Power-down Pin Wake-up Enable Bit
* | | |0 = GPB group pin wake-up function disabled.
* | | |1 = GPB group pin wake-up function enabled.
* |[1] |PRWKEN |Pin Rising Edge Wake-up Enable Bit
* | | |0 = GPB group pin rising edge wake-up function disabled.
* | | |1 = GPB group pin rising edge wake-up function enabled.
* |[2] |PFWKEN |Pin Falling Edge Wake-up Enable Bit
* | | |0 = GPB group pin falling edge wake-up function disabled.
* | | |1 = GPB group pin falling edge wake-up function enabled.
* |[7:4] |WKPSEL |GPB Standby Power-down Wake-up Pin Select
* | | |0000 = GPB.0 wake-up function enabled.
* | | |0001 = GPB.1 wake-up function enabled.
* | | |0010 = GPB.2 wake-up function enabled.
* | | |0011 = GPB.3 wake-up function enabled.
* | | |0100 = GPB.4 wake-up function enabled.
* | | |0101 = GPB.5 wake-up function enabled.
* | | |0110 = GPB.6 wake-up function enabled.
* | | |0111 = GPB.7 wake-up function enabled.
* | | |1000 = GPB.8 wake-up function enabled.
* | | |1001 = GPB.9 wake-up function enabled.
* | | |1010 = GPB.10 wake-up function enabled.
* | | |1011 = GPB.11 wake-up function enabled.
* | | |1100 = GPB.12 wake-up function enabled.
* | | |1101 = GPB.13 wake-up function enabled.
* | | |1110 = GPB.14 wake-up function enabled.
* | | |1111 = GPB.15 wake-up function enabled.
* |[8] |DBEN |GPB Input Signal De-bounce Enable Bit
* | | |The DBEN bit is used to enable the de-bounce function for each corresponding IO
* | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wake-up
* | | |The de-bounce clock source is the 10 kHz internal low speed RC oscillator.
* | | |0 = Standby power-down wake-up pin De-bounce function disable.
* | | |1 = Standby power-down wake-up pin De-bounce function enable.
* | | |The de-bounce function is valid only for edge triggered.
* @var CLK_T::PCSWKCTL
* Offset: 0xA8 GPC Standby Power-down Wake-up Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |WKEN |Standby Power-down Pin Wake-up Enable Bit
* | | |0 = GPC group pin wake-up function disabled.
* | | |1 = GPC group pin wake-up function enabled.
* |[1] |PRWKEN |Pin Rising Edge Wake-up Enable Bit
* | | |0 = GPC group pin rising edge wake-up function disabled.
* | | |1 = GPC group pin rising edge wake-up function enabled.
* |[2] |PFWKEN |Pin Falling Edge Wake-up Enable Bit
* | | |0 = GPC group pin falling edge wake-up function disabled.
* | | |1 = GPC group pin falling edge wake-up function enabled.
* |[7:4] |WKPSEL |GPC Standby Power-down Wake-up Pin Select
* | | |0000 = GPC.0 wake-up function enabled.
* | | |0001 = GPC.1 wake-up function enabled.
* | | |0010 = GPC.2 wake-up function enabled.
* | | |0011 = GPC.3 wake-up function enabled.
* | | |0100 = GPC.4 wake-up function enabled.
* | | |0101 = GPC.5 wake-up function enabled.
* | | |0110 = GPC.6 wake-up function enabled.
* | | |0111 = GPC.7 wake-up function enabled.
* | | |1000 = GPC.8 wake-up function enabled.
* | | |1001 = GPC.9 wake-up function enabled.
* | | |1010 = GPC.10 wake-up function enabled.
* | | |1011 = GPC.11 wake-up function enabled.
* | | |1100 = GPC.12 wake-up function enabled.
* | | |1101 = GPC.13 wake-up function enabled.
* | | |1110 = GPC.14 wake-up function enabled.
* | | |1111 = GPC.15 wake-up function enabled.
* |[8] |DBEN |GPC Input Signal De-bounce Enable Bit
* | | |The DBEN bit is used to enable the de-bounce function for each corresponding IO
* | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wake-up
* | | |The de-bounce clock source is the 10 kHz internal low speed RC oscillator.
* | | |0 = Standby power-down wake-up pin De-bounce function disable.
* | | |1 = Standby power-down wake-up pin De-bounce function enable.
* | | |The de-bounce function is valid only for edge triggered.
* @var CLK_T::PDSWKCTL
* Offset: 0xAC GPD Standby Power-down Wake-up Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |WKEN |Standby Power-down Pin Wake-up Enable Bit
* | | |0 = GPD group pin wake-up function disabled.
* | | |1 = GPD group pin wake-up function enabled.
* |[1] |PRWKEN |Pin Rising Edge Wake-up Enable Bit
* | | |0 = GPD group pin rising edge wake-up function disabled.
* | | |1 = GPD group pin rising edge wake-up function enabled.
* |[2] |PFWKEN |Pin Falling Edge Wake-up Enable Bit
* | | |0 = GPD group pin falling edge wake-up function disabled.
* | | |1 = GPD group pin falling edge wake-up function enabled.
* |[7:4] |WKPSEL |GPD Standby Power-down Wake-up Pin Select
* | | |0000 = GPD.0 wake-up function enabled.
* | | |0001 = GPD.1 wake-up function enabled.
* | | |0010 = GPD.2 wake-up function enabled.
* | | |0011 = GPD.3 wake-up function enabled.
* | | |0100 = GPD.4 wake-up function enabled.
* | | |0101 = GPD.5 wake-up function enabled.
* | | |0110 = GPD.6 wake-up function enabled.
* | | |0111 = GPD.7 wake-up function enabled.
* | | |1000 = GPD.8 wake-up function enabled.
* | | |1001 = GPD.9 wake-up function enabled.
* | | |1010 = GPD.10 wake-up function enabled.
* | | |1011 = GPD.11 wake-up function enabled.
* | | |1100 = GPD.12 wake-up function enabled.
* | | |1101 = GPD.13 wake-up function enabled.
* | | |1110 = GPD.14 wake-up function enabled.
* | | |1111 = GPD.15 wake-up function enabled.
* |[8] |DBEN |GPD Input Signal De-bounce Enable Bit
* | | |The DBEN bit is used to enable the de-bounce function for each corresponding IO
* | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wake-up
* | | |The de-bounce clock source is the 10 kHz internal low speed RC oscillator.
* | | |0 = Standby power-down wake-up pin De-bounce function disable.
* | | |1 = Standby power-down wake-up pin De-bounce function enable.
* | | |The de-bounce function is valid only for edge triggered.
* @var CLK_T::IOPDCTL
* Offset: 0xB0 GPIO Standby Power-down Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |IOHR |GPIO Hold Release
* | | |When GPIO enter standby power-down mode, all I/O status are hold to keep normal operating status
* | | |After chip was waked up from standby power-down mode, the I/O are still keep hold status until user set this bit to release I/O hold status.
* | | |This bit is auto cleared by hardware.
*/
__IO uint32_t PWRCTL; /*!< [0x0000] System Power-down Control Register */
__IO uint32_t AHBCLK; /*!< [0x0004] AHB Devices Clock Enable Control Register */
__IO uint32_t APBCLK0; /*!< [0x0008] APB Devices Clock Enable Control Register 0 */
__IO uint32_t APBCLK1; /*!< [0x000c] APB Devices Clock Enable Control Register 1 */
__IO uint32_t CLKSEL0; /*!< [0x0010] Clock Source Select Control Register 0 */
__IO uint32_t CLKSEL1; /*!< [0x0014] Clock Source Select Control Register 1 */
__IO uint32_t CLKSEL2; /*!< [0x0018] Clock Source Select Control Register 2 */
__IO uint32_t CLKSEL3; /*!< [0x001c] Clock Source Select Control Register 3 */
__IO uint32_t CLKDIV0; /*!< [0x0020] Clock Divider Number Register 0 */
__IO uint32_t CLKDIV1; /*!< [0x0024] Clock Divider Number Register 1 */
/** @cond HIDDEN_SYMBOLS */
__I uint32_t RESERVE0[1];
/** @endcond */
__IO uint32_t CLKDIV3; /*!< [0x002c] Clock Divider Number Register 3 */
__IO uint32_t CLKDIV4; /*!< [0x0030] Clock Divider Number Register 4 */
__IO uint32_t PCLKDIV; /*!< [0x0034] APB Clock Divider Register */
/** @cond HIDDEN_SYMBOLS */
__I uint32_t RESERVE1[2];
/** @endcond */
__IO uint32_t PLLCTL; /*!< [0x0040] PLL Control Register */
/** @cond HIDDEN_SYMBOLS */
__I uint32_t RESERVE2[3];
/** @endcond */
__I uint32_t STATUS; /*!< [0x0050] Clock Status Monitor Register */
/** @cond HIDDEN_SYMBOLS */
__I uint32_t RESERVE3[3];
/** @endcond */
__IO uint32_t CLKOCTL; /*!< [0x0060] Clock Output Control Register */
/** @cond HIDDEN_SYMBOLS */
__I uint32_t RESERVE4[3];
/** @endcond */
__IO uint32_t CLKDCTL; /*!< [0x0070] Clock Fail Detector Control Register */
__IO uint32_t CLKDSTS; /*!< [0x0074] Clock Fail Detector Status Register */
__IO uint32_t CDUPB; /*!< [0x0078] Clock Frequency Range Detector Upper Boundary Register */
__IO uint32_t CDLOWB; /*!< [0x007c] Clock Frequency Range Detector Lower Boundary Register */
/** @cond HIDDEN_SYMBOLS */
__I uint32_t RESERVE5[4];
/** @endcond */
__IO uint32_t PMUCTL; /*!< [0x0090] Power Manager Control Register */
__IO uint32_t PMUSTS; /*!< [0x0094] Power Manager Status Register */
/** @cond HIDDEN_SYMBOLS */
__I uint32_t RESERVE6[1];
/** @endcond */
__IO uint32_t SWKDBCTL; /*!< [0x009c] Standby Power-down Wake-up De-bounce Control Register */
__IO uint32_t PASWKCTL; /*!< [0x00a0] GPA Standby Power-down Wake-up Control Register */
__IO uint32_t PBSWKCTL; /*!< [0x00a4] GPB Standby Power-down Wake-up Control Register */
__IO uint32_t PCSWKCTL; /*!< [0x00a8] GPC Standby Power-down Wake-up Control Register */
__IO uint32_t PDSWKCTL; /*!< [0x00ac] GPD Standby Power-down Wake-up Control Register */
__IO uint32_t IOPDCTL; /*!< [0x00b0] GPIO Standby Power-down Control Register */
} CLK_T;
/**
@addtogroup CLK_CONST CLK Bit Field Definition
Constant Definitions for CLK Controller
@{ */
#define CLK_PWRCTL_HXTEN_Pos (0) /*!< CLK_T::PWRCTL: HXTEN Position */
#define CLK_PWRCTL_HXTEN_Msk (0x1ul << CLK_PWRCTL_HXTEN_Pos) /*!< CLK_T::PWRCTL: HXTEN Mask */
#define CLK_PWRCTL_LXTEN_Pos (1) /*!< CLK_T::PWRCTL: LXTEN Position */
#define CLK_PWRCTL_LXTEN_Msk (0x1ul << CLK_PWRCTL_LXTEN_Pos) /*!< CLK_T::PWRCTL: LXTEN Mask */
#define CLK_PWRCTL_HIRCEN_Pos (2) /*!< CLK_T::PWRCTL: HIRCEN Position */
#define CLK_PWRCTL_HIRCEN_Msk (0x1ul << CLK_PWRCTL_HIRCEN_Pos) /*!< CLK_T::PWRCTL: HIRCEN Mask */
#define CLK_PWRCTL_LIRCEN_Pos (3) /*!< CLK_T::PWRCTL: LIRCEN Position */
#define CLK_PWRCTL_LIRCEN_Msk (0x1ul << CLK_PWRCTL_LIRCEN_Pos) /*!< CLK_T::PWRCTL: LIRCEN Mask */
#define CLK_PWRCTL_PDWKDLY_Pos (4) /*!< CLK_T::PWRCTL: PDWKDLY Position */
#define CLK_PWRCTL_PDWKDLY_Msk (0x1ul << CLK_PWRCTL_PDWKDLY_Pos) /*!< CLK_T::PWRCTL: PDWKDLY Mask */
#define CLK_PWRCTL_PDWKIEN_Pos (5) /*!< CLK_T::PWRCTL: PDWKIEN Position */
#define CLK_PWRCTL_PDWKIEN_Msk (0x1ul << CLK_PWRCTL_PDWKIEN_Pos) /*!< CLK_T::PWRCTL: PDWKIEN Mask */
#define CLK_PWRCTL_PDWKIF_Pos (6) /*!< CLK_T::PWRCTL: PDWKIF Position */
#define CLK_PWRCTL_PDWKIF_Msk (0x1ul << CLK_PWRCTL_PDWKIF_Pos) /*!< CLK_T::PWRCTL: PDWKIF Mask */
#define CLK_PWRCTL_PDEN_Pos (7) /*!< CLK_T::PWRCTL: PDEN Position */
#define CLK_PWRCTL_PDEN_Msk (0x1ul << CLK_PWRCTL_PDEN_Pos) /*!< CLK_T::PWRCTL: PDEN Mask */
#define CLK_PWRCTL_HXTGAIN_Pos (10) /*!< CLK_T::PWRCTL: HXTGAIN Position */
#define CLK_PWRCTL_HXTGAIN_Msk (0x3ul << CLK_PWRCTL_HXTGAIN_Pos) /*!< CLK_T::PWRCTL: HXTGAIN Mask */
#define CLK_PWRCTL_HXTSELTYP_Pos (12) /*!< CLK_T::PWRCTL: HXTSELTYP Position */
#define CLK_PWRCTL_HXTSELTYP_Msk (0x1ul << CLK_PWRCTL_HXTSELTYP_Pos) /*!< CLK_T::PWRCTL: HXTSELTYP Mask */
#define CLK_PWRCTL_HXTTBEN_Pos (13) /*!< CLK_T::PWRCTL: HXTTBEN Position */
#define CLK_PWRCTL_HXTTBEN_Msk (0x1ul << CLK_PWRCTL_HXTTBEN_Pos) /*!< CLK_T::PWRCTL: HXTTBEN Mask */
#define CLK_PWRCTL_HIRCSTBS_Pos (16) /*!< CLK_T::PWRCTL: HIRCSTBS Position */
#define CLK_PWRCTL_HIRCSTBS_Msk (0x3ul << CLK_PWRCTL_HIRCSTBS_Pos) /*!< CLK_T::PWRCTL: HIRCSTBS Mask */
#define CLK_AHBCLK_PDMACKEN_Pos (1) /*!< CLK_T::AHBCLK: PDMACKEN Position */
#define CLK_AHBCLK_PDMACKEN_Msk (0x1ul << CLK_AHBCLK_PDMACKEN_Pos) /*!< CLK_T::AHBCLK: PDMACKEN Mask */
#define CLK_AHBCLK_ISPCKEN_Pos (2) /*!< CLK_T::AHBCLK: ISPCKEN Position */
#define CLK_AHBCLK_ISPCKEN_Msk (0x1ul << CLK_AHBCLK_ISPCKEN_Pos) /*!< CLK_T::AHBCLK: ISPCKEN Mask */
#define CLK_AHBCLK_EBICKEN_Pos (3) /*!< CLK_T::AHBCLK: EBICKEN Position */
#define CLK_AHBCLK_EBICKEN_Msk (0x1ul << CLK_AHBCLK_EBICKEN_Pos) /*!< CLK_T::AHBCLK: EBICKEN Mask */
#define CLK_AHBCLK_EMACCKEN_Pos (5) /*!< CLK_T::AHBCLK: EMACCKEN Position */
#define CLK_AHBCLK_EMACCKEN_Msk (0x1ul << CLK_AHBCLK_EMACCKEN_Pos) /*!< CLK_T::AHBCLK: EMACCKEN Mask */
#define CLK_AHBCLK_SDH0CKEN_Pos (6) /*!< CLK_T::AHBCLK: SDH0CKEN Position */
#define CLK_AHBCLK_SDH0CKEN_Msk (0x1ul << CLK_AHBCLK_SDH0CKEN_Pos) /*!< CLK_T::AHBCLK: SDH0CKEN Mask */
#define CLK_AHBCLK_CRCCKEN_Pos (7) /*!< CLK_T::AHBCLK: CRCCKEN Position */
#define CLK_AHBCLK_CRCCKEN_Msk (0x1ul << CLK_AHBCLK_CRCCKEN_Pos) /*!< CLK_T::AHBCLK: CRCCKEN Mask */
#define CLK_AHBCLK_HSUSBDCKEN_Pos (10) /*!< CLK_T::AHBCLK: HSUSBDCKEN Position */
#define CLK_AHBCLK_HSUSBDCKEN_Msk (0x1ul << CLK_AHBCLK_HSUSBDCKEN_Pos) /*!< CLK_T::AHBCLK: HSUSBDCKEN Mask */
#define CLK_AHBCLK_CRPTCKEN_Pos (12) /*!< CLK_T::AHBCLK: CRPTCKEN Position */
#define CLK_AHBCLK_CRPTCKEN_Msk (0x1ul << CLK_AHBCLK_CRPTCKEN_Pos) /*!< CLK_T::AHBCLK: CRPTCKEN Mask */
#define CLK_AHBCLK_SPIMCKEN_Pos (14) /*!< CLK_T::AHBCLK: SPIMCKEN Position */
#define CLK_AHBCLK_SPIMCKEN_Msk (0x1ul << CLK_AHBCLK_SPIMCKEN_Pos) /*!< CLK_T::AHBCLK: SPIMCKEN Mask */
#define CLK_AHBCLK_FMCIDLE_Pos (15) /*!< CLK_T::AHBCLK: FMCIDLE Position */
#define CLK_AHBCLK_FMCIDLE_Msk (0x1ul << CLK_AHBCLK_FMCIDLE_Pos) /*!< CLK_T::AHBCLK: FMCIDLE Mask */
#define CLK_AHBCLK_USBHCKEN_Pos (16) /*!< CLK_T::AHBCLK: USBHCKEN Position */
#define CLK_AHBCLK_USBHCKEN_Msk (0x1ul << CLK_AHBCLK_USBHCKEN_Pos) /*!< CLK_T::AHBCLK: USBHCKEN Mask */
#define CLK_AHBCLK_SDH1CKEN_Pos (17) /*!< CLK_T::AHBCLK: SDH1CKEN Position */
#define CLK_AHBCLK_SDH1CKEN_Msk (0x1ul << CLK_AHBCLK_SDH1CKEN_Pos) /*!< CLK_T::AHBCLK: SDH1CKEN Mask */
#define CLK_APBCLK0_WDTCKEN_Pos (0) /*!< CLK_T::APBCLK0: WDTCKEN Position */
#define CLK_APBCLK0_WDTCKEN_Msk (0x1ul << CLK_APBCLK0_WDTCKEN_Pos) /*!< CLK_T::APBCLK0: WDTCKEN Mask */
#define CLK_APBCLK0_RTCCKEN_Pos (1) /*!< CLK_T::APBCLK0: RTCCKEN Position */
#define CLK_APBCLK0_RTCCKEN_Msk (0x1ul << CLK_APBCLK0_RTCCKEN_Pos) /*!< CLK_T::APBCLK0: RTCCKEN Mask */
#define CLK_APBCLK0_TMR0CKEN_Pos (2) /*!< CLK_T::APBCLK0: TMR0CKEN Position */
#define CLK_APBCLK0_TMR0CKEN_Msk (0x1ul << CLK_APBCLK0_TMR0CKEN_Pos) /*!< CLK_T::APBCLK0: TMR0CKEN Mask */
#define CLK_APBCLK0_TMR1CKEN_Pos (3) /*!< CLK_T::APBCLK0: TMR1CKEN Position */
#define CLK_APBCLK0_TMR1CKEN_Msk (0x1ul << CLK_APBCLK0_TMR1CKEN_Pos) /*!< CLK_T::APBCLK0: TMR1CKEN Mask */
#define CLK_APBCLK0_TMR2CKEN_Pos (4) /*!< CLK_T::APBCLK0: TMR2CKEN Position */
#define CLK_APBCLK0_TMR2CKEN_Msk (0x1ul << CLK_APBCLK0_TMR2CKEN_Pos) /*!< CLK_T::APBCLK0: TMR2CKEN Mask */
#define CLK_APBCLK0_TMR3CKEN_Pos (5) /*!< CLK_T::APBCLK0: TMR3CKEN Position */
#define CLK_APBCLK0_TMR3CKEN_Msk (0x1ul << CLK_APBCLK0_TMR3CKEN_Pos) /*!< CLK_T::APBCLK0: TMR3CKEN Mask */
#define CLK_APBCLK0_CLKOCKEN_Pos (6) /*!< CLK_T::APBCLK0: CLKOCKEN Position */
#define CLK_APBCLK0_CLKOCKEN_Msk (0x1ul << CLK_APBCLK0_CLKOCKEN_Pos) /*!< CLK_T::APBCLK0: CLKOCKEN Mask */
#define CLK_APBCLK0_ACMP01CKEN_Pos (7) /*!< CLK_T::APBCLK0: ACMP01CKEN Position */
#define CLK_APBCLK0_ACMP01CKEN_Msk (0x1ul << CLK_APBCLK0_ACMP01CKEN_Pos) /*!< CLK_T::APBCLK0: ACMP01CKEN Mask */
#define CLK_APBCLK0_I2C0CKEN_Pos (8) /*!< CLK_T::APBCLK0: I2C0CKEN Position */
#define CLK_APBCLK0_I2C0CKEN_Msk (0x1ul << CLK_APBCLK0_I2C0CKEN_Pos) /*!< CLK_T::APBCLK0: I2C0CKEN Mask */
#define CLK_APBCLK0_I2C1CKEN_Pos (9) /*!< CLK_T::APBCLK0: I2C1CKEN Position */
#define CLK_APBCLK0_I2C1CKEN_Msk (0x1ul << CLK_APBCLK0_I2C1CKEN_Pos) /*!< CLK_T::APBCLK0: I2C1CKEN Mask */
#define CLK_APBCLK0_I2C2CKEN_Pos (10) /*!< CLK_T::APBCLK0: I2C2CKEN Position */
#define CLK_APBCLK0_I2C2CKEN_Msk (0x1ul << CLK_APBCLK0_I2C2CKEN_Pos) /*!< CLK_T::APBCLK0: I2C2CKEN Mask */
#define CLK_APBCLK0_SPI0CKEN_Pos (12) /*!< CLK_T::APBCLK0: SPI0CKEN Position */
#define CLK_APBCLK0_SPI0CKEN_Msk (0x1ul << CLK_APBCLK0_SPI0CKEN_Pos) /*!< CLK_T::APBCLK0: SPI0CKEN Mask */
#define CLK_APBCLK0_SPI1CKEN_Pos (13) /*!< CLK_T::APBCLK0: SPI1CKEN Position */
#define CLK_APBCLK0_SPI1CKEN_Msk (0x1ul << CLK_APBCLK0_SPI1CKEN_Pos) /*!< CLK_T::APBCLK0: SPI1CKEN Mask */
#define CLK_APBCLK0_SPI2CKEN_Pos (14) /*!< CLK_T::APBCLK0: SPI2CKEN Position */
#define CLK_APBCLK0_SPI2CKEN_Msk (0x1ul << CLK_APBCLK0_SPI2CKEN_Pos) /*!< CLK_T::APBCLK0: SPI2CKEN Mask */
#define CLK_APBCLK0_SPI3CKEN_Pos (15) /*!< CLK_T::APBCLK0: SPI3CKEN Position */
#define CLK_APBCLK0_SPI3CKEN_Msk (0x1ul << CLK_APBCLK0_SPI3CKEN_Pos) /*!< CLK_T::APBCLK0: SPI3CKEN Mask */
#define CLK_APBCLK0_UART0CKEN_Pos (16) /*!< CLK_T::APBCLK0: UART0CKEN Position */
#define CLK_APBCLK0_UART0CKEN_Msk (0x1ul << CLK_APBCLK0_UART0CKEN_Pos) /*!< CLK_T::APBCLK0: UART0CKEN Mask */
#define CLK_APBCLK0_UART1CKEN_Pos (17) /*!< CLK_T::APBCLK0: UART1CKEN Position */
#define CLK_APBCLK0_UART1CKEN_Msk (0x1ul << CLK_APBCLK0_UART1CKEN_Pos) /*!< CLK_T::APBCLK0: UART1CKEN Mask */
#define CLK_APBCLK0_UART2CKEN_Pos (18) /*!< CLK_T::APBCLK0: UART2CKEN Position */
#define CLK_APBCLK0_UART2CKEN_Msk (0x1ul << CLK_APBCLK0_UART2CKEN_Pos) /*!< CLK_T::APBCLK0: UART2CKEN Mask */
#define CLK_APBCLK0_UART3CKEN_Pos (19) /*!< CLK_T::APBCLK0: UART3CKEN Position */
#define CLK_APBCLK0_UART3CKEN_Msk (0x1ul << CLK_APBCLK0_UART3CKEN_Pos) /*!< CLK_T::APBCLK0: UART3CKEN Mask */
#define CLK_APBCLK0_UART4CKEN_Pos (20) /*!< CLK_T::APBCLK0: UART4CKEN Position */
#define CLK_APBCLK0_UART4CKEN_Msk (0x1ul << CLK_APBCLK0_UART4CKEN_Pos) /*!< CLK_T::APBCLK0: UART4CKEN Mask */
#define CLK_APBCLK0_UART5CKEN_Pos (21) /*!< CLK_T::APBCLK0: UART5CKEN Position */
#define CLK_APBCLK0_UART5CKEN_Msk (0x1ul << CLK_APBCLK0_UART5CKEN_Pos) /*!< CLK_T::APBCLK0: UART5CKEN Mask */
#define CLK_APBCLK0_CAN0CKEN_Pos (24) /*!< CLK_T::APBCLK0: CAN0CKEN Position */
#define CLK_APBCLK0_CAN0CKEN_Msk (0x1ul << CLK_APBCLK0_CAN0CKEN_Pos) /*!< CLK_T::APBCLK0: CAN0CKEN Mask */
#define CLK_APBCLK0_CAN1CKEN_Pos (25) /*!< CLK_T::APBCLK0: CAN1CKEN Position */
#define CLK_APBCLK0_CAN1CKEN_Msk (0x1ul << CLK_APBCLK0_CAN1CKEN_Pos) /*!< CLK_T::APBCLK0: CAN1CKEN Mask */
#define CLK_APBCLK0_OTGCKEN_Pos (26) /*!< CLK_T::APBCLK0: OTGCKEN Position */
#define CLK_APBCLK0_OTGCKEN_Msk (0x1ul << CLK_APBCLK0_OTGCKEN_Pos) /*!< CLK_T::APBCLK0: OTGCKEN Mask */
#define CLK_APBCLK0_USBDCKEN_Pos (27) /*!< CLK_T::APBCLK0: USBDCKEN Position */
#define CLK_APBCLK0_USBDCKEN_Msk (0x1ul << CLK_APBCLK0_USBDCKEN_Pos) /*!< CLK_T::APBCLK0: USBDCKEN Mask */
#define CLK_APBCLK0_EADCCKEN_Pos (28) /*!< CLK_T::APBCLK0: EADCCKEN Position */
#define CLK_APBCLK0_EADCCKEN_Msk (0x1ul << CLK_APBCLK0_EADCCKEN_Pos) /*!< CLK_T::APBCLK0: EADCCKEN Mask */
#define CLK_APBCLK0_I2S0CKEN_Pos (29) /*!< CLK_T::APBCLK0: I2S0CKEN Position */
#define CLK_APBCLK0_I2S0CKEN_Msk (0x1ul << CLK_APBCLK0_I2S0CKEN_Pos) /*!< CLK_T::APBCLK0: I2S0CKEN Mask */
#define CLK_APBCLK0_HSOTGCKEN_Pos (30) /*!< CLK_T::APBCLK0: HSOTGCKEN Position */
#define CLK_APBCLK0_HSOTGCKEN_Msk (0x1ul << CLK_APBCLK0_HSOTGCKEN_Pos) /*!< CLK_T::APBCLK0: HSOTGCKEN Mask */
#define CLK_APBCLK1_SC0CKEN_Pos (0) /*!< CLK_T::APBCLK1: SC0CKEN Position */
#define CLK_APBCLK1_SC0CKEN_Msk (0x1ul << CLK_APBCLK1_SC0CKEN_Pos) /*!< CLK_T::APBCLK1: SC0CKEN Mask */
#define CLK_APBCLK1_SC1CKEN_Pos (1) /*!< CLK_T::APBCLK1: SC1CKEN Position */
#define CLK_APBCLK1_SC1CKEN_Msk (0x1ul << CLK_APBCLK1_SC1CKEN_Pos) /*!< CLK_T::APBCLK1: SC1CKEN Mask */
#define CLK_APBCLK1_SC2CKEN_Pos (2) /*!< CLK_T::APBCLK1: SC2CKEN Position */
#define CLK_APBCLK1_SC2CKEN_Msk (0x1ul << CLK_APBCLK1_SC2CKEN_Pos) /*!< CLK_T::APBCLK1: SC2CKEN Mask */
#define CLK_APBCLK1_SPI4CKEN_Pos (6) /*!< CLK_T::APBCLK1: SPI4CKEN Position */
#define CLK_APBCLK1_SPI4CKEN_Msk (0x1ul << CLK_APBCLK1_SPI4CKEN_Pos) /*!< CLK_T::APBCLK1: SPI4CKEN Mask */
#define CLK_APBCLK1_USCI0CKEN_Pos (8) /*!< CLK_T::APBCLK1: USCI0CKEN Position */
#define CLK_APBCLK1_USCI0CKEN_Msk (0x1ul << CLK_APBCLK1_USCI0CKEN_Pos) /*!< CLK_T::APBCLK1: USCI0CKEN Mask */
#define CLK_APBCLK1_USCI1CKEN_Pos (9) /*!< CLK_T::APBCLK1: USCI1CKEN Position */
#define CLK_APBCLK1_USCI1CKEN_Msk (0x1ul << CLK_APBCLK1_USCI1CKEN_Pos) /*!< CLK_T::APBCLK1: USCI1CKEN Mask */
#define CLK_APBCLK1_DACCKEN_Pos (12) /*!< CLK_T::APBCLK1: DACCKEN Position */
#define CLK_APBCLK1_DACCKEN_Msk (0x1ul << CLK_APBCLK1_DACCKEN_Pos) /*!< CLK_T::APBCLK1: DACCKEN Mask */
#define CLK_APBCLK1_EPWM0CKEN_Pos (16) /*!< CLK_T::APBCLK1: EPWM0CKEN Position */
#define CLK_APBCLK1_EPWM0CKEN_Msk (0x1ul << CLK_APBCLK1_EPWM0CKEN_Pos) /*!< CLK_T::APBCLK1: EPWM0CKEN Mask */
#define CLK_APBCLK1_EPWM1CKEN_Pos (17) /*!< CLK_T::APBCLK1: EPWM1CKEN Position */
#define CLK_APBCLK1_EPWM1CKEN_Msk (0x1ul << CLK_APBCLK1_EPWM1CKEN_Pos) /*!< CLK_T::APBCLK1: EPWM1CKEN Mask */
#define CLK_APBCLK1_BPWM0CKEN_Pos (18) /*!< CLK_T::APBCLK1: BPWM0CKEN Position */
#define CLK_APBCLK1_BPWM0CKEN_Msk (0x1ul << CLK_APBCLK1_BPWM0CKEN_Pos) /*!< CLK_T::APBCLK1: BPWM0CKEN Mask */
#define CLK_APBCLK1_BPWM1CKEN_Pos (19) /*!< CLK_T::APBCLK1: BPWM1CKEN Position */
#define CLK_APBCLK1_BPWM1CKEN_Msk (0x1ul << CLK_APBCLK1_BPWM1CKEN_Pos) /*!< CLK_T::APBCLK1: BPWM1CKEN Mask */
#define CLK_APBCLK1_QEI0CKEN_Pos (22) /*!< CLK_T::APBCLK1: QEI0CKEN Position */
#define CLK_APBCLK1_QEI0CKEN_Msk (0x1ul << CLK_APBCLK1_QEI0CKEN_Pos) /*!< CLK_T::APBCLK1: QEI0CKEN Mask */
#define CLK_APBCLK1_QEI1CKEN_Pos (23) /*!< CLK_T::APBCLK1: QEI1CKEN Position */
#define CLK_APBCLK1_QEI1CKEN_Msk (0x1ul << CLK_APBCLK1_QEI1CKEN_Pos) /*!< CLK_T::APBCLK1: QEI1CKEN Mask */
#define CLK_APBCLK1_ECAP0CKEN_Pos (26) /*!< CLK_T::APBCLK1: ECAP0CKEN Position */
#define CLK_APBCLK1_ECAP0CKEN_Msk (0x1ul << CLK_APBCLK1_ECAP0CKEN_Pos) /*!< CLK_T::APBCLK1: ECAP0CKEN Mask */
#define CLK_APBCLK1_ECAP1CKEN_Pos (27) /*!< CLK_T::APBCLK1: ECAP1CKEN Position */
#define CLK_APBCLK1_ECAP1CKEN_Msk (0x1ul << CLK_APBCLK1_ECAP1CKEN_Pos) /*!< CLK_T::APBCLK1: ECAP1CKEN Mask */
#define CLK_APBCLK1_OPACKEN_Pos (30) /*!< CLK_T::APBCLK1: OPACKEN Position */
#define CLK_APBCLK1_OPACKEN_Msk (0x1ul << CLK_APBCLK1_OPACKEN_Pos) /*!< CLK_T::APBCLK1: OPACKEN Mask */
#define CLK_CLKSEL0_HCLKSEL_Pos (0) /*!< CLK_T::CLKSEL0: HCLKSEL Position */
#define CLK_CLKSEL0_HCLKSEL_Msk (0x7ul << CLK_CLKSEL0_HCLKSEL_Pos) /*!< CLK_T::CLKSEL0: HCLKSEL Mask */
#define CLK_CLKSEL0_STCLKSEL_Pos (3) /*!< CLK_T::CLKSEL0: STCLKSEL Position */
#define CLK_CLKSEL0_STCLKSEL_Msk (0x7ul << CLK_CLKSEL0_STCLKSEL_Pos) /*!< CLK_T::CLKSEL0: STCLKSEL Mask */
#if(0)
#define CLK_CLKSEL0_PCLK0SEL_Pos (6) /*!< CLK_T::CLKSEL0: PCLK0SEL Position */
#define CLK_CLKSEL0_PCLK0SEL_Msk (0x1ul << CLK_CLKSEL0_PCLK0SEL_Pos) /*!< CLK_T::CLKSEL0: PCLK0SEL Mask */
#define CLK_CLKSEL0_PCLK1SEL_Pos (7) /*!< CLK_T::CLKSEL0: PCLK1SEL Position */
#define CLK_CLKSEL0_PCLK1SEL_Msk (0x1ul << CLK_CLKSEL0_PCLK1SEL_Pos) /*!< CLK_T::CLKSEL0: PCLK1SEL Mask */
#endif
#define CLK_CLKSEL0_SDH0SEL_Pos (20) /*!< CLK_T::CLKSEL0: SDH0SEL Position */
#define CLK_CLKSEL0_SDH0SEL_Msk (0x3ul << CLK_CLKSEL0_SDH0SEL_Pos) /*!< CLK_T::CLKSEL0: SDH0SEL Mask */
#define CLK_CLKSEL0_SDH1SEL_Pos (22) /*!< CLK_T::CLKSEL0: SDH1SEL Position */
#define CLK_CLKSEL0_SDH1SEL_Msk (0x3ul << CLK_CLKSEL0_SDH1SEL_Pos) /*!< CLK_T::CLKSEL0: SDH1SEL Mask */
#define CLK_CLKSEL1_WDTSEL_Pos (0) /*!< CLK_T::CLKSEL1: WDTSEL Position */
#define CLK_CLKSEL1_WDTSEL_Msk (0x3ul << CLK_CLKSEL1_WDTSEL_Pos) /*!< CLK_T::CLKSEL1: WDTSEL Mask */
#define CLK_CLKSEL1_TMR0SEL_Pos (8) /*!< CLK_T::CLKSEL1: TMR0SEL Position */
#define CLK_CLKSEL1_TMR0SEL_Msk (0x7ul << CLK_CLKSEL1_TMR0SEL_Pos) /*!< CLK_T::CLKSEL1: TMR0SEL Mask */
#define CLK_CLKSEL1_TMR1SEL_Pos (12) /*!< CLK_T::CLKSEL1: TMR1SEL Position */
#define CLK_CLKSEL1_TMR1SEL_Msk (0x7ul << CLK_CLKSEL1_TMR1SEL_Pos) /*!< CLK_T::CLKSEL1: TMR1SEL Mask */
#define CLK_CLKSEL1_TMR2SEL_Pos (16) /*!< CLK_T::CLKSEL1: TMR2SEL Position */
#define CLK_CLKSEL1_TMR2SEL_Msk (0x7ul << CLK_CLKSEL1_TMR2SEL_Pos) /*!< CLK_T::CLKSEL1: TMR2SEL Mask */
#define CLK_CLKSEL1_TMR3SEL_Pos (20) /*!< CLK_T::CLKSEL1: TMR3SEL Position */
#define CLK_CLKSEL1_TMR3SEL_Msk (0x7ul << CLK_CLKSEL1_TMR3SEL_Pos) /*!< CLK_T::CLKSEL1: TMR3SEL Mask */
#define CLK_CLKSEL1_UART0SEL_Pos (24) /*!< CLK_T::CLKSEL1: UART0SEL Position */
#define CLK_CLKSEL1_UART0SEL_Msk (0x3ul << CLK_CLKSEL1_UART0SEL_Pos) /*!< CLK_T::CLKSEL1: UART0SEL Mask */
#define CLK_CLKSEL1_UART1SEL_Pos (26) /*!< CLK_T::CLKSEL1: UART1SEL Position */
#define CLK_CLKSEL1_UART1SEL_Msk (0x3ul << CLK_CLKSEL1_UART1SEL_Pos) /*!< CLK_T::CLKSEL1: UART1SEL Mask */
#define CLK_CLKSEL1_CLKOSEL_Pos (28) /*!< CLK_T::CLKSEL1: CLKOSEL Position */
#define CLK_CLKSEL1_CLKOSEL_Msk (0x3ul << CLK_CLKSEL1_CLKOSEL_Pos) /*!< CLK_T::CLKSEL1: CLKOSEL Mask */
#define CLK_CLKSEL1_WWDTSEL_Pos (30) /*!< CLK_T::CLKSEL1: WWDTSEL Position */
#define CLK_CLKSEL1_WWDTSEL_Msk (0x3ul << CLK_CLKSEL1_WWDTSEL_Pos) /*!< CLK_T::CLKSEL1: WWDTSEL Mask */
#define CLK_CLKSEL2_EPWM0SEL_Pos (0) /*!< CLK_T::CLKSEL2: EPWM0SEL Position */
#define CLK_CLKSEL2_EPWM0SEL_Msk (0x1ul << CLK_CLKSEL2_EPWM0SEL_Pos) /*!< CLK_T::CLKSEL2: EPWM0SEL Mask */
#define CLK_CLKSEL2_EPWM1SEL_Pos (1) /*!< CLK_T::CLKSEL2: EPWM1SEL Position */
#define CLK_CLKSEL2_EPWM1SEL_Msk (0x1ul << CLK_CLKSEL2_EPWM1SEL_Pos) /*!< CLK_T::CLKSEL2: EPWM1SEL Mask */
#define CLK_CLKSEL2_SPI0SEL_Pos (2) /*!< CLK_T::CLKSEL2: SPI0SEL Position */
#define CLK_CLKSEL2_SPI0SEL_Msk (0x3ul << CLK_CLKSEL2_SPI0SEL_Pos) /*!< CLK_T::CLKSEL2: SPI0SEL Mask */
#define CLK_CLKSEL2_SPI1SEL_Pos (4) /*!< CLK_T::CLKSEL2: SPI1SEL Position */
#define CLK_CLKSEL2_SPI1SEL_Msk (0x3ul << CLK_CLKSEL2_SPI1SEL_Pos) /*!< CLK_T::CLKSEL2: SPI1SEL Mask */
#define CLK_CLKSEL2_SPI2SEL_Pos (6) /*!< CLK_T::CLKSEL2: SPI2SEL Position */
#define CLK_CLKSEL2_SPI2SEL_Msk (0x3ul << CLK_CLKSEL2_SPI2SEL_Pos) /*!< CLK_T::CLKSEL2: SPI2SEL Mask */
#define CLK_CLKSEL2_BPWM0SEL_Pos (8) /*!< CLK_T::CLKSEL2: BPWM0SEL Position */
#define CLK_CLKSEL2_BPWM0SEL_Msk (0x1ul << CLK_CLKSEL2_BPWM0SEL_Pos) /*!< CLK_T::CLKSEL2: BPWM0SEL Mask */
#define CLK_CLKSEL2_BPWM1SEL_Pos (9) /*!< CLK_T::CLKSEL2: BPWM1SEL Position */
#define CLK_CLKSEL2_BPWM1SEL_Msk (0x1ul << CLK_CLKSEL2_BPWM1SEL_Pos) /*!< CLK_T::CLKSEL2: BPWM1SEL Mask */
#define CLK_CLKSEL2_SPI3SEL_Pos (10) /*!< CLK_T::CLKSEL2: SPI3SEL Position */
#define CLK_CLKSEL2_SPI3SEL_Msk (0x3ul << CLK_CLKSEL2_SPI3SEL_Pos) /*!< CLK_T::CLKSEL2: SPI3SEL Mask */
#define CLK_CLKSEL2_SPI4SEL_Pos (12) /*!< CLK_T::CLKSEL2: SPI4SEL Position */
#define CLK_CLKSEL2_SPI4SEL_Msk (0x3ul << CLK_CLKSEL2_SPI4SEL_Pos) /*!< CLK_T::CLKSEL2: SPI4SEL Mask */
#define CLK_CLKSEL3_SC0SEL_Pos (0) /*!< CLK_T::CLKSEL3: SC0SEL Position */
#define CLK_CLKSEL3_SC0SEL_Msk (0x3ul << CLK_CLKSEL3_SC0SEL_Pos) /*!< CLK_T::CLKSEL3: SC0SEL Mask */
#define CLK_CLKSEL3_SC1SEL_Pos (2) /*!< CLK_T::CLKSEL3: SC1SEL Position */
#define CLK_CLKSEL3_SC1SEL_Msk (0x3ul << CLK_CLKSEL3_SC1SEL_Pos) /*!< CLK_T::CLKSEL3: SC1SEL Mask */
#define CLK_CLKSEL3_SC2SEL_Pos (4) /*!< CLK_T::CLKSEL3: SC2SEL Position */
#define CLK_CLKSEL3_SC2SEL_Msk (0x3ul << CLK_CLKSEL3_SC2SEL_Pos) /*!< CLK_T::CLKSEL3: SC2SEL Mask */
#define CLK_CLKSEL3_RTCSEL_Pos (8) /*!< CLK_T::CLKSEL3: RTCSEL Position */
#define CLK_CLKSEL3_RTCSEL_Msk (0x1ul << CLK_CLKSEL3_RTCSEL_Pos) /*!< CLK_T::CLKSEL3: RTCSEL Mask */
#define CLK_CLKSEL3_I2S0SEL_Pos (16) /*!< CLK_T::CLKSEL3: I2S0SEL Position */
#define CLK_CLKSEL3_I2S0SEL_Msk (0x3ul << CLK_CLKSEL3_I2S0SEL_Pos) /*!< CLK_T::CLKSEL3: I2S0SEL Mask */
#define CLK_CLKSEL3_UART2SEL_Pos (24) /*!< CLK_T::CLKSEL3: UART2SEL Position */
#define CLK_CLKSEL3_UART2SEL_Msk (0x3ul << CLK_CLKSEL3_UART2SEL_Pos) /*!< CLK_T::CLKSEL3: UART2SEL Mask */
#define CLK_CLKSEL3_UART3SEL_Pos (26) /*!< CLK_T::CLKSEL3: UART3SEL Position */
#define CLK_CLKSEL3_UART3SEL_Msk (0x3ul << CLK_CLKSEL3_UART3SEL_Pos) /*!< CLK_T::CLKSEL3: UART3SEL Mask */
#define CLK_CLKSEL3_UART4SEL_Pos (28) /*!< CLK_T::CLKSEL3: UART4SEL Position */
#define CLK_CLKSEL3_UART4SEL_Msk (0x3ul << CLK_CLKSEL3_UART4SEL_Pos) /*!< CLK_T::CLKSEL3: UART4SEL Mask */
#define CLK_CLKSEL3_UART5SEL_Pos (30) /*!< CLK_T::CLKSEL3: UART5SEL Position */
#define CLK_CLKSEL3_UART5SEL_Msk (0x3ul << CLK_CLKSEL3_UART5SEL_Pos) /*!< CLK_T::CLKSEL3: UART5SEL Mask */
#define CLK_CLKDIV0_HCLKDIV_Pos (0) /*!< CLK_T::CLKDIV0: HCLKDIV Position */
#define CLK_CLKDIV0_HCLKDIV_Msk (0xful << CLK_CLKDIV0_HCLKDIV_Pos) /*!< CLK_T::CLKDIV0: HCLKDIV Mask */
#define CLK_CLKDIV0_USBDIV_Pos (4) /*!< CLK_T::CLKDIV0: USBDIV Position */
#define CLK_CLKDIV0_USBDIV_Msk (0xful << CLK_CLKDIV0_USBDIV_Pos) /*!< CLK_T::CLKDIV0: USBDIV Mask */
#define CLK_CLKDIV0_UART0DIV_Pos (8) /*!< CLK_T::CLKDIV0: UART0DIV Position */
#define CLK_CLKDIV0_UART0DIV_Msk (0xful << CLK_CLKDIV0_UART0DIV_Pos) /*!< CLK_T::CLKDIV0: UART0DIV Mask */
#define CLK_CLKDIV0_UART1DIV_Pos (12) /*!< CLK_T::CLKDIV0: UART1DIV Position */
#define CLK_CLKDIV0_UART1DIV_Msk (0xful << CLK_CLKDIV0_UART1DIV_Pos) /*!< CLK_T::CLKDIV0: UART1DIV Mask */
#define CLK_CLKDIV0_EADCDIV_Pos (16) /*!< CLK_T::CLKDIV0: EADCDIV Position */
#define CLK_CLKDIV0_EADCDIV_Msk (0xfful << CLK_CLKDIV0_EADCDIV_Pos) /*!< CLK_T::CLKDIV0: EADCDIV Mask */
#define CLK_CLKDIV0_SDH0DIV_Pos (24) /*!< CLK_T::CLKDIV0: SDH0DIV Position */
#define CLK_CLKDIV0_SDH0DIV_Msk (0xfful << CLK_CLKDIV0_SDH0DIV_Pos) /*!< CLK_T::CLKDIV0: SDH0DIV Mask */
#define CLK_CLKDIV1_SC0DIV_Pos (0) /*!< CLK_T::CLKDIV1: SC0DIV Position */
#define CLK_CLKDIV1_SC0DIV_Msk (0xfful << CLK_CLKDIV1_SC0DIV_Pos) /*!< CLK_T::CLKDIV1: SC0DIV Mask */
#define CLK_CLKDIV1_SC1DIV_Pos (8) /*!< CLK_T::CLKDIV1: SC1DIV Position */
#define CLK_CLKDIV1_SC1DIV_Msk (0xfful << CLK_CLKDIV1_SC1DIV_Pos) /*!< CLK_T::CLKDIV1: SC1DIV Mask */
#define CLK_CLKDIV1_SC2DIV_Pos (16) /*!< CLK_T::CLKDIV1: SC2DIV Position */
#define CLK_CLKDIV1_SC2DIV_Msk (0xfful << CLK_CLKDIV1_SC2DIV_Pos) /*!< CLK_T::CLKDIV1: SC2DIV Mask */
#define CLK_CLKDIV3_EMACDIV_Pos (16) /*!< CLK_T::CLKDIV3: EMACDIV Position */
#define CLK_CLKDIV3_EMACDIV_Msk (0xfful << CLK_CLKDIV3_EMACDIV_Pos) /*!< CLK_T::CLKDIV3: EMACDIV Mask */
#define CLK_CLKDIV3_SDH1DIV_Pos (24) /*!< CLK_T::CLKDIV3: SDH1DIV Position */
#define CLK_CLKDIV3_SDH1DIV_Msk (0xfful << CLK_CLKDIV3_SDH1DIV_Pos) /*!< CLK_T::CLKDIV3: SDH1DIV Mask */
#define CLK_CLKDIV4_UART2DIV_Pos (0) /*!< CLK_T::CLKDIV4: UART2DIV Position */
#define CLK_CLKDIV4_UART2DIV_Msk (0xful << CLK_CLKDIV4_UART2DIV_Pos) /*!< CLK_T::CLKDIV4: UART2DIV Mask */
#define CLK_CLKDIV4_UART3DIV_Pos (4) /*!< CLK_T::CLKDIV4: UART3DIV Position */
#define CLK_CLKDIV4_UART3DIV_Msk (0xful << CLK_CLKDIV4_UART3DIV_Pos) /*!< CLK_T::CLKDIV4: UART3DIV Mask */
#define CLK_CLKDIV4_UART4DIV_Pos (8) /*!< CLK_T::CLKDIV4: UART4DIV Position */
#define CLK_CLKDIV4_UART4DIV_Msk (0xful << CLK_CLKDIV4_UART4DIV_Pos) /*!< CLK_T::CLKDIV4: UART4DIV Mask */
#define CLK_CLKDIV4_UART5DIV_Pos (12) /*!< CLK_T::CLKDIV4: UART5DIV Position */
#define CLK_CLKDIV4_UART5DIV_Msk (0xful << CLK_CLKDIV4_UART5DIV_Pos) /*!< CLK_T::CLKDIV4: UART5DIV Mask */
#if(1)
#define CLK_PCLKDIV_APB0DIV_Pos (0) /*!< CLK_T::PCLKDIV: APB0DIV Position */
#define CLK_PCLKDIV_APB0DIV_Msk (0x7ul << CLK_PCLKDIV_APB0DIV_Pos) /*!< CLK_T::PCLKDIV: APB0DIV Mask */
#define CLK_PCLKDIV_APB1DIV_Pos (4) /*!< CLK_T::PCLKDIV: APB1DIV Position */
#define CLK_PCLKDIV_APB1DIV_Msk (0x7ul << CLK_PCLKDIV_APB1DIV_Pos) /*!< CLK_T::PCLKDIV: APB1DIV Mask */
#endif
#define CLK_PLLCTL_FBDIV_Pos (0) /*!< CLK_T::PLLCTL: FBDIV Position */
#define CLK_PLLCTL_FBDIV_Msk (0x1fful << CLK_PLLCTL_FBDIV_Pos) /*!< CLK_T::PLLCTL: FBDIV Mask */
#define CLK_PLLCTL_INDIV_Pos (9) /*!< CLK_T::PLLCTL: INDIV Position */
#define CLK_PLLCTL_INDIV_Msk (0x1ful << CLK_PLLCTL_INDIV_Pos) /*!< CLK_T::PLLCTL: INDIV Mask */
#define CLK_PLLCTL_OUTDIV_Pos (14) /*!< CLK_T::PLLCTL: OUTDIV Position */
#define CLK_PLLCTL_OUTDIV_Msk (0x3ul << CLK_PLLCTL_OUTDIV_Pos) /*!< CLK_T::PLLCTL: OUTDIV Mask */
#define CLK_PLLCTL_PD_Pos (16) /*!< CLK_T::PLLCTL: PD Position */
#define CLK_PLLCTL_PD_Msk (0x1ul << CLK_PLLCTL_PD_Pos) /*!< CLK_T::PLLCTL: PD Mask */
#define CLK_PLLCTL_BP_Pos (17) /*!< CLK_T::PLLCTL: BP Position */
#define CLK_PLLCTL_BP_Msk (0x1ul << CLK_PLLCTL_BP_Pos) /*!< CLK_T::PLLCTL: BP Mask */
#define CLK_PLLCTL_OE_Pos (18) /*!< CLK_T::PLLCTL: OE Position */
#define CLK_PLLCTL_OE_Msk (0x1ul << CLK_PLLCTL_OE_Pos) /*!< CLK_T::PLLCTL: OE Mask */
#define CLK_PLLCTL_PLLSRC_Pos (19) /*!< CLK_T::PLLCTL: PLLSRC Position */
#define CLK_PLLCTL_PLLSRC_Msk (0x1ul << CLK_PLLCTL_PLLSRC_Pos) /*!< CLK_T::PLLCTL: PLLSRC Mask */
#define CLK_PLLCTL_STBSEL_Pos (23) /*!< CLK_T::PLLCTL: STBSEL Position */
#define CLK_PLLCTL_STBSEL_Msk (0x1ul << CLK_PLLCTL_STBSEL_Pos) /*!< CLK_T::PLLCTL: STBSEL Mask */
#define CLK_PLLCTL_BANDSEL_Pos (28) /*!< CLK_T::PLLCTL: BANDSEL Position */
#define CLK_PLLCTL_BANDSEL_Msk (0x1ul << CLK_PLLCTL_BANDSEL_Pos) /*!< CLK_T::PLLCTL: BANDSEL Mask */
#define CLK_STATUS_HXTSTB_Pos (0) /*!< CLK_T::STATUS: HXTSTB Position */
#define CLK_STATUS_HXTSTB_Msk (0x1ul << CLK_STATUS_HXTSTB_Pos) /*!< CLK_T::STATUS: HXTSTB Mask */
#define CLK_STATUS_LXTSTB_Pos (1) /*!< CLK_T::STATUS: LXTSTB Position */
#define CLK_STATUS_LXTSTB_Msk (0x1ul << CLK_STATUS_LXTSTB_Pos) /*!< CLK_T::STATUS: LXTSTB Mask */
#define CLK_STATUS_PLLSTB_Pos (2) /*!< CLK_T::STATUS: PLLSTB Position */
#define CLK_STATUS_PLLSTB_Msk (0x1ul << CLK_STATUS_PLLSTB_Pos) /*!< CLK_T::STATUS: PLLSTB Mask */
#define CLK_STATUS_LIRCSTB_Pos (3) /*!< CLK_T::STATUS: LIRCSTB Position */
#define CLK_STATUS_LIRCSTB_Msk (0x1ul << CLK_STATUS_LIRCSTB_Pos) /*!< CLK_T::STATUS: LIRCSTB Mask */
#define CLK_STATUS_HIRCSTB_Pos (4) /*!< CLK_T::STATUS: HIRCSTB Position */
#define CLK_STATUS_HIRCSTB_Msk (0x1ul << CLK_STATUS_HIRCSTB_Pos) /*!< CLK_T::STATUS: HIRCSTB Mask */
#define CLK_STATUS_CLKSFAIL_Pos (7) /*!< CLK_T::STATUS: CLKSFAIL Position */
#define CLK_STATUS_CLKSFAIL_Msk (0x1ul << CLK_STATUS_CLKSFAIL_Pos) /*!< CLK_T::STATUS: CLKSFAIL Mask */
#define CLK_CLKOCTL_FREQSEL_Pos (0) /*!< CLK_T::CLKOCTL: FREQSEL Position */
#define CLK_CLKOCTL_FREQSEL_Msk (0xful << CLK_CLKOCTL_FREQSEL_Pos) /*!< CLK_T::CLKOCTL: FREQSEL Mask */
#define CLK_CLKOCTL_CLKOEN_Pos (4) /*!< CLK_T::CLKOCTL: CLKOEN Position */
#define CLK_CLKOCTL_CLKOEN_Msk (0x1ul << CLK_CLKOCTL_CLKOEN_Pos) /*!< CLK_T::CLKOCTL: CLKOEN Mask */
#define CLK_CLKOCTL_DIV1EN_Pos (5) /*!< CLK_T::CLKOCTL: DIV1EN Position */
#define CLK_CLKOCTL_DIV1EN_Msk (0x1ul << CLK_CLKOCTL_DIV1EN_Pos) /*!< CLK_T::CLKOCTL: DIV1EN Mask */
#define CLK_CLKOCTL_CLK1HZEN_Pos (6) /*!< CLK_T::CLKOCTL: CLK1HZEN Position */
#define CLK_CLKOCTL_CLK1HZEN_Msk (0x1ul << CLK_CLKOCTL_CLK1HZEN_Pos) /*!< CLK_T::CLKOCTL: CLK1HZEN Mask */
#define CLK_CLKDCTL_HXTFDEN_Pos (4) /*!< CLK_T::CLKDCTL: HXTFDEN Position */
#define CLK_CLKDCTL_HXTFDEN_Msk (0x1ul << CLK_CLKDCTL_HXTFDEN_Pos) /*!< CLK_T::CLKDCTL: HXTFDEN Mask */
#define CLK_CLKDCTL_HXTFIEN_Pos (5) /*!< CLK_T::CLKDCTL: HXTFIEN Position */
#define CLK_CLKDCTL_HXTFIEN_Msk (0x1ul << CLK_CLKDCTL_HXTFIEN_Pos) /*!< CLK_T::CLKDCTL: HXTFIEN Mask */
#define CLK_CLKDCTL_LXTFDEN_Pos (12) /*!< CLK_T::CLKDCTL: LXTFDEN Position */
#define CLK_CLKDCTL_LXTFDEN_Msk (0x1ul << CLK_CLKDCTL_LXTFDEN_Pos) /*!< CLK_T::CLKDCTL: LXTFDEN Mask */
#define CLK_CLKDCTL_LXTFIEN_Pos (13) /*!< CLK_T::CLKDCTL: LXTFIEN Position */
#define CLK_CLKDCTL_LXTFIEN_Msk (0x1ul << CLK_CLKDCTL_LXTFIEN_Pos) /*!< CLK_T::CLKDCTL: LXTFIEN Mask */
#define CLK_CLKDCTL_HXTFQDEN_Pos (16) /*!< CLK_T::CLKDCTL: HXTFQDEN Position */
#define CLK_CLKDCTL_HXTFQDEN_Msk (0x1ul << CLK_CLKDCTL_HXTFQDEN_Pos) /*!< CLK_T::CLKDCTL: HXTFQDEN Mask */
#define CLK_CLKDCTL_HXTFQIEN_Pos (17) /*!< CLK_T::CLKDCTL: HXTFQIEN Position */
#define CLK_CLKDCTL_HXTFQIEN_Msk (0x1ul << CLK_CLKDCTL_HXTFQIEN_Pos) /*!< CLK_T::CLKDCTL: HXTFQIEN Mask */
#define CLK_CLKDSTS_HXTFIF_Pos (0) /*!< CLK_T::CLKDSTS: HXTFIF Position */
#define CLK_CLKDSTS_HXTFIF_Msk (0x1ul << CLK_CLKDSTS_HXTFIF_Pos) /*!< CLK_T::CLKDSTS: HXTFIF Mask */
#define CLK_CLKDSTS_LXTFIF_Pos (1) /*!< CLK_T::CLKDSTS: LXTFIF Position */
#define CLK_CLKDSTS_LXTFIF_Msk (0x1ul << CLK_CLKDSTS_LXTFIF_Pos) /*!< CLK_T::CLKDSTS: LXTFIF Mask */
#define CLK_CLKDSTS_HXTFQIF_Pos (8) /*!< CLK_T::CLKDSTS: HXTFQIF Position */
#define CLK_CLKDSTS_HXTFQIF_Msk (0x1ul << CLK_CLKDSTS_HXTFQIF_Pos) /*!< CLK_T::CLKDSTS: HXTFQIF Mask */
#define CLK_CDUPB_UPERBD_Pos (0) /*!< CLK_T::CDUPB: UPERBD Position */
#define CLK_CDUPB_UPERBD_Msk (0x3fful << CLK_CDUPB_UPERBD_Pos) /*!< CLK_T::CDUPB: UPERBD Mask */
#define CLK_CDLOWB_LOWERBD_Pos (0) /*!< CLK_T::CDLOWB: LOWERBD Position */
#define CLK_CDLOWB_LOWERBD_Msk (0x3fful << CLK_CDLOWB_LOWERBD_Pos) /*!< CLK_T::CDLOWB: LOWERBD Mask */
#define CLK_PMUCTL_PDMSEL_Pos (0) /*!< CLK_T::PMUCTL: PDMSEL Position */
#define CLK_PMUCTL_PDMSEL_Msk (0x7ul << CLK_PMUCTL_PDMSEL_Pos) /*!< CLK_T::PMUCTL: PDMSEL Mask */
#define CLK_PMUCTL_WKTMREN_Pos (8) /*!< CLK_T::PMUCTL: WKTMREN Position */
#define CLK_PMUCTL_WKTMREN_Msk (0x1ul << CLK_PMUCTL_WKTMREN_Pos) /*!< CLK_T::PMUCTL: WKTMREN Mask */
#define CLK_PMUCTL_WKTMRIS_Pos (9) /*!< CLK_T::PMUCTL: WKTMRIS Position */
#define CLK_PMUCTL_WKTMRIS_Msk (0x7ul << CLK_PMUCTL_WKTMRIS_Pos) /*!< CLK_T::PMUCTL: WKTMRIS Mask */
#define CLK_PMUCTL_WKPINEN_Pos (16) /*!< CLK_T::PMUCTL: WKPINEN Position */
#define CLK_PMUCTL_WKPINEN_Msk (0x3ul << CLK_PMUCTL_WKPINEN_Pos) /*!< CLK_T::PMUCTL: WKPINEN Mask */
#define CLK_PMUCTL_ACMPSPWK_Pos (18) /*!< CLK_T::PMUCTL: ACMPSPWK Position */
#define CLK_PMUCTL_ACMPSPWK_Msk (0x1ul << CLK_PMUCTL_ACMPSPWK_Pos) /*!< CLK_T::PMUCTL: ACMPSPWK Mask */
#define CLK_PMUCTL_RTCWKEN_Pos (23) /*!< CLK_T::PMUCTL: RTCWKEN Position */
#define CLK_PMUCTL_RTCWKEN_Msk (0x1ul << CLK_PMUCTL_RTCWKEN_Pos) /*!< CLK_T::PMUCTL: RTCWKEN Mask */
#define CLK_PMUSTS_PINWK_Pos (0) /*!< CLK_T::PMUSTS: PINWK Position */
#define CLK_PMUSTS_PINWK_Msk (0x1ul << CLK_PMUSTS_PINWK_Pos) /*!< CLK_T::PMUSTS: PINWK Mask */
#define CLK_PMUSTS_TMRWK_Pos (1) /*!< CLK_T::PMUSTS: TMRWK Position */
#define CLK_PMUSTS_TMRWK_Msk (0x1ul << CLK_PMUSTS_TMRWK_Pos) /*!< CLK_T::PMUSTS: TMRWK Mask */
#define CLK_PMUSTS_RTCWK_Pos (2) /*!< CLK_T::PMUSTS: RTCWK Position */
#define CLK_PMUSTS_RTCWK_Msk (0x1ul << CLK_PMUSTS_RTCWK_Pos) /*!< CLK_T::PMUSTS: RTCWK Mask */
#define CLK_PMUSTS_GPAWK_Pos (8) /*!< CLK_T::PMUSTS: GPAWK Position */
#define CLK_PMUSTS_GPAWK_Msk (0x1ul << CLK_PMUSTS_GPAWK_Pos) /*!< CLK_T::PMUSTS: GPAWK Mask */
#define CLK_PMUSTS_GPBWK_Pos (9) /*!< CLK_T::PMUSTS: GPBWK Position */
#define CLK_PMUSTS_GPBWK_Msk (0x1ul << CLK_PMUSTS_GPBWK_Pos) /*!< CLK_T::PMUSTS: GPBWK Mask */
#define CLK_PMUSTS_GPCWK_Pos (10) /*!< CLK_T::PMUSTS: GPCWK Position */
#define CLK_PMUSTS_GPCWK_Msk (0x1ul << CLK_PMUSTS_GPCWK_Pos) /*!< CLK_T::PMUSTS: GPCWK Mask */
#define CLK_PMUSTS_GPDWK_Pos (11) /*!< CLK_T::PMUSTS: GPDWK Position */
#define CLK_PMUSTS_GPDWK_Msk (0x1ul << CLK_PMUSTS_GPDWK_Pos) /*!< CLK_T::PMUSTS: GPDWK Mask */
#define CLK_PMUSTS_LVRWK_Pos (12) /*!< CLK_T::PMUSTS: LVRWK Position */
#define CLK_PMUSTS_LVRWK_Msk (0x1ul << CLK_PMUSTS_LVRWK_Pos) /*!< CLK_T::PMUSTS: LVRWK Mask */
#define CLK_PMUSTS_BODWK_Pos (13) /*!< CLK_T::PMUSTS: BODWK Position */
#define CLK_PMUSTS_BODWK_Msk (0x1ul << CLK_PMUSTS_BODWK_Pos) /*!< CLK_T::PMUSTS: BODWK Mask */
#define CLK_PMUSTS_ACMPWK_Pos (14) /*!< CLK_T::PMUSTS: ACMPWK Position */
#define CLK_PMUSTS_ACMPWK_Msk (0x1ul << CLK_PMUSTS_ACMPWK_Pos) /*!< CLK_T::PMUSTS: ACMPWK Mask */
#define CLK_PMUSTS_CLRWK_Pos (31) /*!< CLK_T::PMUSTS: CLRWK Position */
#define CLK_PMUSTS_CLRWK_Msk (0x1ul << CLK_PMUSTS_CLRWK_Pos) /*!< CLK_T::PMUSTS: CLRWK Mask */
#define CLK_SWKDBCTL_SWKDBCLKSEL_Pos (0) /*!< CLK_T::SWKDBCTL: SWKDBCLKSEL Position */
#define CLK_SWKDBCTL_SWKDBCLKSEL_Msk (0xful << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< CLK_T::SWKDBCTL: SWKDBCLKSEL Mask */
#define CLK_PASWKCTL_WKEN_Pos (0) /*!< CLK_T::PASWKCTL: WKEN Position */
#define CLK_PASWKCTL_WKEN_Msk (0x1ul << CLK_PASWKCTL_WKEN_Pos) /*!< CLK_T::PASWKCTL: WKEN Mask */
#define CLK_PASWKCTL_PRWKEN_Pos (1) /*!< CLK_T::PASWKCTL: PRWKEN Position */
#define CLK_PASWKCTL_PRWKEN_Msk (0x1ul << CLK_PASWKCTL_PRWKEN_Pos) /*!< CLK_T::PASWKCTL: PRWKEN Mask */
#define CLK_PASWKCTL_PFWKEN_Pos (2) /*!< CLK_T::PASWKCTL: PFWKEN Position */
#define CLK_PASWKCTL_PFWKEN_Msk (0x1ul << CLK_PASWKCTL_PFWKEN_Pos) /*!< CLK_T::PASWKCTL: PFWKEN Mask */
#define CLK_PASWKCTL_WKPSEL_Pos (4) /*!< CLK_T::PASWKCTL: WKPSEL Position */
#define CLK_PASWKCTL_WKPSEL_Msk (0xful << CLK_PASWKCTL_WKPSEL_Pos) /*!< CLK_T::PASWKCTL: WKPSEL Mask */
#define CLK_PASWKCTL_DBEN_Pos (8) /*!< CLK_T::PASWKCTL: DBEN Position */
#define CLK_PASWKCTL_DBEN_Msk (0x1ul << CLK_PASWKCTL_DBEN_Pos) /*!< CLK_T::PASWKCTL: DBEN Mask */
#define CLK_PBSWKCTL_WKEN_Pos (0) /*!< CLK_T::PBSWKCTL: WKEN Position */
#define CLK_PBSWKCTL_WKEN_Msk (0x1ul << CLK_PBSWKCTL_WKEN_Pos) /*!< CLK_T::PBSWKCTL: WKEN Mask */
#define CLK_PBSWKCTL_PRWKEN_Pos (1) /*!< CLK_T::PBSWKCTL: PRWKEN Position */
#define CLK_PBSWKCTL_PRWKEN_Msk (0x1ul << CLK_PBSWKCTL_PRWKEN_Pos) /*!< CLK_T::PBSWKCTL: PRWKEN Mask */
#define CLK_PBSWKCTL_PFWKEN_Pos (2) /*!< CLK_T::PBSWKCTL: PFWKEN Position */
#define CLK_PBSWKCTL_PFWKEN_Msk (0x1ul << CLK_PBSWKCTL_PFWKEN_Pos) /*!< CLK_T::PBSWKCTL: PFWKEN Mask */
#define CLK_PBSWKCTL_WKPSEL_Pos (4) /*!< CLK_T::PBSWKCTL: WKPSEL Position */
#define CLK_PBSWKCTL_WKPSEL_Msk (0xful << CLK_PBSWKCTL_WKPSEL_Pos) /*!< CLK_T::PBSWKCTL: WKPSEL Mask */
#define CLK_PBSWKCTL_DBEN_Pos (8) /*!< CLK_T::PBSWKCTL: DBEN Position */
#define CLK_PBSWKCTL_DBEN_Msk (0x1ul << CLK_PBSWKCTL_DBEN_Pos) /*!< CLK_T::PBSWKCTL: DBEN Mask */
#define CLK_PCSWKCTL_WKEN_Pos (0) /*!< CLK_T::PCSWKCTL: WKEN Position */
#define CLK_PCSWKCTL_WKEN_Msk (0x1ul << CLK_PCSWKCTL_WKEN_Pos) /*!< CLK_T::PCSWKCTL: WKEN Mask */
#define CLK_PCSWKCTL_PRWKEN_Pos (1) /*!< CLK_T::PCSWKCTL: PRWKEN Position */
#define CLK_PCSWKCTL_PRWKEN_Msk (0x1ul << CLK_PCSWKCTL_PRWKEN_Pos) /*!< CLK_T::PCSWKCTL: PRWKEN Mask */
#define CLK_PCSWKCTL_PFWKEN_Pos (2) /*!< CLK_T::PCSWKCTL: PFWKEN Position */
#define CLK_PCSWKCTL_PFWKEN_Msk (0x1ul << CLK_PCSWKCTL_PFWKEN_Pos) /*!< CLK_T::PCSWKCTL: PFWKEN Mask */
#define CLK_PCSWKCTL_WKPSEL_Pos (4) /*!< CLK_T::PCSWKCTL: WKPSEL Position */
#define CLK_PCSWKCTL_WKPSEL_Msk (0xful << CLK_PCSWKCTL_WKPSEL_Pos) /*!< CLK_T::PCSWKCTL: WKPSEL Mask */
#define CLK_PCSWKCTL_DBEN_Pos (8) /*!< CLK_T::PCSWKCTL: DBEN Position */
#define CLK_PCSWKCTL_DBEN_Msk (0x1ul << CLK_PCSWKCTL_DBEN_Pos) /*!< CLK_T::PCSWKCTL: DBEN Mask */
#define CLK_PDSWKCTL_WKEN_Pos (0) /*!< CLK_T::PDSWKCTL: WKEN Position */
#define CLK_PDSWKCTL_WKEN_Msk (0x1ul << CLK_PDSWKCTL_WKEN_Pos) /*!< CLK_T::PDSWKCTL: WKEN Mask */
#define CLK_PDSWKCTL_PRWKEN_Pos (1) /*!< CLK_T::PDSWKCTL: PRWKEN Position */
#define CLK_PDSWKCTL_PRWKEN_Msk (0x1ul << CLK_PDSWKCTL_PRWKEN_Pos) /*!< CLK_T::PDSWKCTL: PRWKEN Mask */
#define CLK_PDSWKCTL_PFWKEN_Pos (2) /*!< CLK_T::PDSWKCTL: PFWKEN Position */
#define CLK_PDSWKCTL_PFWKEN_Msk (0x1ul << CLK_PDSWKCTL_PFWKEN_Pos) /*!< CLK_T::PDSWKCTL: PFWKEN Mask */
#define CLK_PDSWKCTL_WKPSEL_Pos (4) /*!< CLK_T::PDSWKCTL: WKPSEL Position */
#define CLK_PDSWKCTL_WKPSEL_Msk (0xful << CLK_PDSWKCTL_WKPSEL_Pos) /*!< CLK_T::PDSWKCTL: WKPSEL Mask */
#define CLK_PDSWKCTL_DBEN_Pos (8) /*!< CLK_T::PDSWKCTL: DBEN Position */
#define CLK_PDSWKCTL_DBEN_Msk (0x1ul << CLK_PDSWKCTL_DBEN_Pos) /*!< CLK_T::PDSWKCTL: DBEN Mask */
#define CLK_IOPDCTL_IOHR_Pos (0) /*!< CLK_T::IOPDCTL: IOHR Position */
#define CLK_IOPDCTL_IOHR_Msk (0x1ul << CLK_IOPDCTL_IOHR_Pos) /*!< CLK_T::IOPDCTL: IOHR Mask */
/**@}*/ /* CLK_CONST */
/**@}*/ /* end of CLK register group */
/*---------------------- Flash Memory Controller -------------------------*/
/**
@addtogroup FMC Flash Memory Controller(FMC)
Memory Mapped Structure for FMC Controller
@{ */
typedef struct {
/**
* @var FMC_T::ISPCTL
* Offset: 0x00 ISP Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ISPEN |ISP Enable Bit (Write Protect)
* | | |ISP function enable bit. Set this bit to enable ISP function.
* | | |0 = ISP function Disabled.
* | | |1 = ISP function Enabled.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[1] |BS |Boot Select (Write Protect)
* | | |When MBS in CONFIG0 is 1, set/clear this bit to select next booting from LDROM/APROM, respectively
* | | |This bit also functions as chip booting status flag, which can be used to check where chip booted from
* | | |This bit is initiated with the inversed value of CBS[1] (CONFIG0[7]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened
* | | |0 = Booting from APROM when MBS (CONFIG0[5]) is 1.
* | | |1 = Booting from LDROM when MBS (CONFIG0[5]) is 1.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[2] |SPUEN |SPROM Update Enable Bit (Write Protect)
* | | |0 = SPROM cannot be updated.
* | | |1 = SPROM can be updated.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[3] |APUEN |APROM Update Enable Bit (Write Protect)
* | | |0 = APROM cannot be updated when the chip runs in APROM.
* | | |1 = APROM can be updated when the chip runs in APROM.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[4] |CFGUEN |CONFIG Update Enable Bit (Write Protect)
* | | |0 = CONFIG cannot be updated.
* | | |1 = CONFIG can be updated.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[5] |LDUEN |LDROM Update Enable Bit (Write Protect)
* | | |LDROM update enable bit.
* | | |0 = LDROM cannot be updated.
* | | |1 = LDROM can be updated.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[6] |ISPFF |ISP Fail Flag (Write Protect)
* | | |This bit is set by hardware when a triggered ISP meets any of the following conditions:
* | | |This bit needs to be cleared by writing 1 to it.
* | | |(1) APROM writes to itself if APUEN is set to 0.
* | | |(2) LDROM writes to itself if LDUEN is set to 0.
* | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0.
* | | |(4) SPROM is erased/programmed if SPUEN is set to 0
* | | |(5) SPROM is programmed at SPROM secured mode.
* | | |(6) Page Erase command at LOCK mode with ICE connection
* | | |(7) Erase or Program command at brown-out detected
* | | |(8) Destination address is illegal, such as over an available range.
* | | |(9) Invalid ISP commands
* | | |(10) Vector address is mapping to SPROM region
* | | |(11) KPROM is erased/programmed if KEYLOCK is set to 1
* | | |(12) APROM(except for Data Flash) is erased/programmed if KEYLOCK is set to 1
* | | |(13) LDROM is erased/programmed if KEYLOCK is set to 1
* | | |(14) SPROM is erased/programmed if KEYLOCK is set to 1 and KEYENROM[1:0] are 1.
* | | |(15) CONFIG is erased/programmed if KEYLOCK is set to 1 and KEYENROM[1:0] are 1
* | | |(16) Invalid operations (except for chip erase) with ICE connection if SBLOCK is not 0x5A
* | | |(17) Read any content of boot loader with ICE connection
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[16] |BL |Boot Loader Booting (Write Protect)
* | | |This bit is initiated with the inversed value of MBS (CONFIG0[5])
* | | |Any reset, except CPU reset (CPU is 1) or system reset (SYS), BL will be reloaded
* | | |This bit is used to check chip boot from Boot Loader or not
* | | |User should keep original value of this bit when updating FMC_ISPCTL register.
* | | |0 = Booting from APROM or LDROM.
* | | |1 = Booting from Boot Loader.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* @var FMC_T::ISPADDR
* Offset: 0x04 ISP Address Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |ISPADDR |ISP Address
* | | |The NuMicro M480 series is equipped with embedded flash
* | | |ISPADDR[1:0] must be kept 00 for ISP 32-bit operation
* | | |ISPADDR[2:0] must be kept 000 for ISP 64-bit operation.
* | | |For CRC32 Checksum Calculation command, this field is the flash starting address for checksum calculation, 4 Kbytes alignment is necessary for CRC32 checksum calculation.
* | | |For FLASH 32-bit Program, ISP address needs word alignment (4-byte)
* | | |For FLASH 64-bit Program, ISP address needs double word alignment (8-byte).
* @var FMC_T::ISPDAT
* Offset: 0x08 ISP Data Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |ISPDAT |ISP Data
* | | |Write data to this register before ISP program operation.
* | | |Read data from this register after ISP read operation.
* | | |When ISPFF (FMC_ISPCTL[6]) is 1, ISPDAT = 0xffff_ffff
* | | |For Run CRC32 Checksum Calculation command, ISPDAT is the memory size (byte) and 4 Kbytes alignment
* | | |For ISP Read CRC32 Checksum command, ISPDAT is the checksum result
* | | |If ISPDAT = 0x0000_0000, it means that (1) the checksum calculation is in progress, or (2) the memory range for checksum calculation is incorrect
* @var FMC_T::ISPCMD
* Offset: 0x0C ISP Command Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[6:0] |CMD |ISP Command
* | | |ISP command table is shown below:
* | | |0x00= FLASH Read.
* | | |0x04= Read Unique ID.
* | | |0x08= Read Flash All-One Result.
* | | |0x0B= Read Company ID.
* | | |0x0C= Read Device ID.
* | | |0x0D= Read Checksum.
* | | |0x21= FLASH 32-bit Program.
* | | |0x22= FLASH Page Erase. Erase any page in two banks, except for OTP.
* | | |0x23= FLASH Bank Erase. Erase all pages of APROM in BANK0 or BANK1.
* | | |0x25= FLASH Block Erase. Erase four pages alignment of APROM in BANK0 or BANK1..
* | | |0x27= FLASH Multi-Word Program.
* | | |0x28= Run Flash All-One Verification.
* | | |0x2D= Run Checksum Calculation.
* | | |0x2E= Vector Remap.
* | | |0x40= FLASH 64-bit Read.
* | | |0x61= FLASH 64-bit Program.
* | | |The other commands are invalid.
* @var FMC_T::ISPTRG
* Offset: 0x10 ISP Trigger Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ISPGO |ISP Start Trigger (Write Protect)
* | | |Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.
* | | |0 = ISP operation is finished.
* | | |1 = ISP is progressed.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* @var FMC_T::DFBA
* Offset: 0x14 Data Flash Base Address
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |DFBA |Data Flash Base Address
* | | |This register indicates Data Flash start address. It is a read only register.
* | | |The Data Flash is shared with APROM. the content of this register is loaded from CONFIG1
* | | |This register is valid when DFEN (CONFIG0[0]) =0 .
* @var FMC_T::ISPSTS
* Offset: 0x40 ISP Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ISPBUSY |ISP Busy Flag (Read Only)
* | | |Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.
* | | |This bit is the mirror of ISPGO(FMC_ISPTRG[0]).
* | | |0 = ISP operation is finished.
* | | |1 = ISP is progressed.
* |[2:1] |CBS |Boot Selection of CONFIG (Read Only)
* | | |This bit is initiated with the CBS (CONFIG0[7:6]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened.
* | | |The following function is valid when MBS (FMC_ISPSTS[3])= 1.
* | | |00 = LDROM with IAP mode.
* | | |01 = LDROM without IAP mode.
* | | |10 = APROM with IAP mode.
* | | |11 = APROM without IAP mode.
* |[3] |MBS |Boot From Boot Loader Selection Flag (Read Only)
* | | |This bit is initiated with the MBS (CONFIG0[5]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened
* | | |0 = Booting from Boot Loader.
* | | |1 = Booting from LDROM/APROM.(.see CBS bit setting)
* |[4] |FCYCDIS |Flash Access Cycle Auto-tuning Disabled Flag (Read Only)
* | | |This bit is set if flash access cycle auto-tuning function is disabled
* | | |The auto-tunning function is disabled by FADIS(FMC_CYCCTL[8]) or HIRC clock is not ready.
* | | |0 = Flash access cycle auto-tuning is enabled.
* | | |1 = Flash access cycle auto-tuning is disabled.
* |[5] |PGFF |Flash Program with Fast Verification Flag (Read Only)
* | | |This bit is set if data is mismatched at ISP programming verification
* | | |This bit is clear by performing ISP flash erase or ISP read CID operation
* | | |0 = Flash Program is success.
* | | |1 = Flash Program is fail. Program data is different with data in the flash memory
* |[6] |ISPFF |ISP Fail Flag (Write Protect)
* | | |This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6]
* | | |This bit is set by hardware when a triggered ISP meets any of the following conditions:
* | | |(1) APROM writes to itself if APUEN is set to 0.
* | | |(2) LDROM writes to itself if LDUEN is set to 0.
* | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0.
* | | |(4) SPROM is erased/programmed if SPUEN is set to 0
* | | |(5) SPROM is programmed at SPROM secured mode.
* | | |(6) Page Erase command at LOCK mode with ICE connection
* | | |(7) Erase or Program command at brown-out detected
* | | |(8) Destination address is illegal, such as over an available range.
* | | |(9) Invalid ISP commands
* | | |(10) Vector address is mapping to SPROM region.
* | | |(11) KPROM is erased/programmed if KEYLOCK is set to 1
* | | |(12) APROM(except for Data Flash) is erased/programmed if KEYLOCK is set to 1
* | | |(13) LDROM is erased/programmed if KEYLOCK is set to 1
* | | |(14) SPROM is erased/programmed if KEYLOCK is set to 1 and KEYENROM[1:0] are 1.
* | | |(15) CONFIG is erased/programmed if KEYLOCK is set to 1 and KEYENROM[1:0] are 1.
* | | |(16) Invalid operations (except for chip erase) with ICE connection if SBLOCK is not 0x5A
* | | |(17) Read any content of boot loader with ICE connection
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[7] |ALLONE |Flash All-one Verification Flag
* | | |This bit is set by hardware if all of flash bits are 1, and clear if flash bits are not all 1 after "Run Flash All-One Verification" complete; this bit also can be clear by writing 1
* | | |0 = All of flash bits are 1 after "Run Flash All-One Verification" complete.
* | | |1 = Flash bits are not all 1 after "Run Flash All-One Verification" complete.
* |[23:9] |VECMAP |Vector Page Mapping Address (Read Only)
* | | |All access to 0x0000_0000~0x0000_01FF is remapped to the flash memory address {VECMAP[14:0], 9u2019h000} ~ {VECMAP[14:0], 9u2019h1FF}
* |[31] |SCODE |Security Code Active Flag
* | | |This bit is set by hardware when detecting SPROM secured code is active at flash initiation, or software writes 1 to this bit to make secured code active; this bit is clear by SPROM page erase operation.
* | | |0 = Secured code is inactive.
* | | |1 = Secured code is active.
* @var FMC_T::CYCCTL
* Offset: 0x4C Flash Access Cycle Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |CYCLE |Flash Access Cycle Control (Write Protect)
* | | |This register is updated automatically by hardware while FCYCDIS (FMC_ISPSTS[4]) is 0, and updated by software while auto-tuning function disabled ( FADIS (FMC_CYCTL[8]) is 1)
* | | |0000 = CPU access with zero wait cycle ; flash access cycle is 1;.
* | | |The HCLK working frequency range is <27MHz; Cache is disabled by hardware.
* | | |0001 = CPU access with one wait cycle if cache miss; flash access cycle is 1;.
* | | |The HCLK working frequency range range is<27MHz
* | | |0010 = CPU access with two wait cycles if cache miss; flash access cycle is 2;.
* | | | The optimized HCLK working frequency range is 27~54 MHz
* | | |0011 = CPU access with three wait cycles if cache miss; flash access cycle is 3;.
* | | |The optimized HCLK working frequency range is 54~81MHz
* | | |0100 = CPU access with four wait cycles if cache miss; flash access cycle is 4;.
* | | | The optimized HCLK working frequency range is81~108MHz
* | | |0101 = CPU access with five wait cycles if cache miss; flash access cycle is 5;.
* | | |The optimized HCLK working frequency range is 108~135MHz
* | | |0110 = CPU access with six wait cycles if cache miss; flash access cycle is 6;.
* | | | The optimized HCLK working frequency range is 135~162MHz
* | | |0111 = CPU access with seven wait cycles if cache miss; flash access cycle is 7;.
* | | | The optimized HCLK working frequency range is 162~192MHz
* | | |1000 = CPU access with eight wait cycles if cache miss; flash access cycle is 8;.
* | | |The optimized HCLK working frequency range is >192MHz
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[8] |FADIS |Flash Access Cycle Auto-tuning Disabled Control (Write Protect)
* | | |Set this bit to disable flash access cycle auto-tuning function
* | | |0 = Flash access cycle auto-tuning is enabled.
* | | |1 = Flash access cycle auto-tuning is disabled.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* @var FMC_T::KPKEY0
* Offset: 0x50 KPROM KEY0 Data Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |KPKEY0 |KPROM KEY0 Data (Write Only)
* | | |Write KPKEY0 data to this register before KEY Comparison operation.
* @var FMC_T::KPKEY1
* Offset: 0x54 KPROM KEY1 Data Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |KPKEY1 |KPROM KEY1 Data (Write Only)
* | | |Write KPKEY1 data to this register before KEY Comparison operation.
* @var FMC_T::KPKEY2
* Offset: 0x58 KPROM KEY2 Data Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |KPKEY2 |KPROM KEY2 Data (Write Only)
* | | |Write KPKEY2 data to this register before KEY Comparison operation.
* @var FMC_T::KPKEYTRG
* Offset: 0x5C KPROM KEY Comparison Trigger Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |KPKEYGO |KPROM KEY Comparison Start Trigger (Write Protection)
* | | |Write 1 to start KEY comparison operation and this bit will be cleared to 0 by hardware automatically when KEY comparison operation is finished
* | | |This trigger operation is valid while FORBID (FMC_KPKEYSTS [3]) is 0.
* | | |0 = KEY comparison operation is finished.
* | | |1 = KEY comparison is progressed.
* | | |Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
* |[1] |TCEN |Timeout Counting Enable (Write Protection)
* | | |0 = Timeout counting is disabled.
* | | |1 = Timeout counting is enabled if input key is matched after key comparison finish.
* | | |10 minutes is at least for timeout, and average is about 20 minutes.
* | | |Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
* @var FMC_T::KPKEYSTS
* Offset: 0x60 KPROM KEY Comparison Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |KEYBUSY |KEY Comparison Busy (Read Only)
* | | |0 = KEY comparison is finished.
* | | |1 = KEY comparison is busy.
* |[1] |KEYLOCK |KEY LOCK Flag
* | | |This bit is set to 1 if KEYMATCH (FMC_KPKEYSTS [2]) is 0 and cleared to 0 if KEYMATCH is 1 in Security Key protection
* | | |After Mass Erase operation, users must reset or power on /off to clear this bit to 0
* | | |This bit also can be set to 1 while
* | | | - CPU write 1 to KEYLOCK(FMC_KPKEYSTS[1]) or
* | | | - KEYFLAG(FMC_KPKEYSTS[4]) is 1 at power-on or reset or
* | | | - KEYENROM is programmed a non-0xFF value or
* | | | - Timeout event or
* | | | - FORBID(FMC_KPKEYSTS[3]) is 1
* | | |0 = KPROM, LDROM and APROM (not include Data Flash) is not in write protection.
* | | |1 = KPROM, LDROM and APROM (not include Data Flash) is in write protection.
* | | |SPROM write protect is depended on SPFLAG.
* | | |CONFIG write protect is depended on CFGFLAG
* |[2] |KEYMATCH |KEY Match Flag (Read Only)
* | | |This bit is set to 1 after KEY comparison complete if the KEY0, KEY1 and KEY2 are matched with the 96-bit security keys in KPROM; and cleared to 0 if KEYs are unmatched
* | | |This bit is also cleared to 0 while
* | | | - CPU writing 1 to KEYLOCK(FMC_KPKEYSTS[1]) or
* | | | - Timeout event or
* | | | - KPROM is erased or
* | | | - KEYENROM is programmed to a non-0xFF value.
* | | | - Chip is in power down mode.
* | | |0 = KEY0, KEY1, and KEY2 are unmatched with the KPROM setting.
* | | |1 = KEY0, KEY1, and KEY2 are matched with the KPROM setting.
* |[3] |FORBID |KEY Comparison Forbidden Flag (Read Only)
* | | |This bit is set to 1 when KPKECNT(FMC_KPKEY0[4:0]) is more than KPKEMAX (FMC_KPKEY0[12:8]) or KPCNT (FMC_KPCNT [2:0]) is more than KPMAX (FMC_KPCNT [10:8]).
* | | |0 = KEY comparison is not forbidden.
* | | |1 = KEY comparison is forbidden, KEYGO (FMC_KEYTRG [0]) cannot trigger.
* |[4] |KEYFLAG |KEY Protection Enabled Flag (Read Only)
* | | |This bit is set while the KEYENROM [7:0] is not 0xFF at power-on or reset
* | | |This bit is cleared to 0 by hardware while KPROM is erased
* | | |This bit is set to 1 by hardware while KEYENROM is programmed to a non-0xFF value.
* | | |0 = Security Key protection is disabled.
* | | |1 = Security Key protection is enabled.
* |[5] |CFGFLAG |CONFIG Write-protection Enabled Flag (Read Only)
* | | |This bit is set while the KEYENROM [0] is 0 at power-on or reset
* | | |This bit is cleared to 0 by hardware while KPROM is erased
* | | |This bit is set to 1 by hardware while KEYENROM[0] is programmed to 0.
* | | |0 = CONFIG write-protection is disabled.
* | | |1 = CONFIG write-protection is enabled.
* |[6] |SPFLAG |SPROM Write-protection Enabled Flag (Read Only)
* | | |This bit is set while the KEYENROM [1] is 0 at power-on or reset
* | | |This bit is cleared to 0 by hardware while KPROM is erased
* | | |This bit is set to 1 by hardware while KEYENROM[1] is programmed to 0.
* | | |0 = SPROM write-protection is disabled.
* | | |1 = SPROM write-protection is enabled.
* @var FMC_T::KPKEYCNT
* Offset: 0x64 KPROM KEY-Unmatched Counting Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[5:0] |KPKECNT |Error Key Entry Counter at Each Power-on (Read Only)
* | | |KPKECNT is increased when entry keys is wrong in Security Key protection
* | | |KPKECNT is cleared to 0 if key comparison is matched or system power-on.
* |[13:8] |KPKEMAX |Maximum Number for Error Key Entry at Each Power-on (Read Only)
* | | |KPKEMAX is the maximum error key entry number at each power-on
* | | |When KPKEMAXROM of KPROM is erased or programmed, KPKEMAX will also be updated
* | | |KPKEMAX is used to limit KPKECNT(FMC_KPKEY0[5:0]) maximum counting
* | | |The FORBID (FMC_KPKEYSTS [3]) will be set to 1 when KPKECNT is more than KPKEMAX.
* @var FMC_T::KPCNT
* Offset: 0x68 KPROM KEY-Unmatched Power-On Counting Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |KPCNT |Power-on Counter for Error Key Entry(Read Only)
* | | |KPCNT is the power-on counting for error key entry in Security Key protection
* | | |KPCNT is cleared to 0 if key comparison is matched.
* |[11:8] |KPMAX |Power-on Maximum Number for Error Key Entry (Read Only)
* | | |KPMAX is the power-on maximum number for error key entry
* | | |When KPMAXROM of KPROM is erased or programmed, KPMAX will also be updated
* | | |KPMAX is used to limit KPCNT (FMC_KPCNT [3:0]) maximum counting
* | | |The FORBID(FMC_KPKEYSTS[3]) will be set to 1 when KPCNT is more than KPMAX
* @var FMC_T::MPDAT0
* Offset: 0x80 ISP Data0 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |ISPDAT0 |ISP Data 0
* | | |This register is the first 32-bit data for 32-bit/64-bit/multi-word programming, and it is also the mirror of FMC_ISPDAT, both registers keep the same data
* @var FMC_T::MPDAT1
* Offset: 0x84 ISP Data1 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |ISPDAT1 |ISP Data 1
* | | |This register is the second 32-bit data for 64-bit/multi-word programming.
* @var FMC_T::MPDAT2
* Offset: 0x88 ISP Data2 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |ISPDAT2 |ISP Data 2
* | | |This register is the third 32-bit data for multi-word programming.
* @var FMC_T::MPDAT3
* Offset: 0x8C ISP Data3 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |ISPDAT3 |ISP Data 3
* | | |This register is the fourth 32-bit data for multi-word programming.
* @var FMC_T::MPSTS
* Offset: 0xC0 ISP Multi-Program Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |MPBUSY |ISP Multi-word Program Busy Flag (Read Only)
* | | |Write 1 to start ISP Multi-Word program operation and this bit will be cleared to 0 by hardware automatically when ISP Multi-Word program operation is finished.
* | | |This bit is the mirror of ISPGO(FMC_ISPTRG[0]).
* | | |0 = ISP Multi-Word program operation is finished.
* | | |1 = ISP Multi-Word program operation is progressed.
* |[1] |PPGO |ISP Multi-program Status (Read Only)
* | | |0 = ISP multi-word program operation is not active.
* | | |1 = ISP multi-word program operation is in progress.
* |[2] |ISPFF |ISP Fail Flag (Read Only)
* | | |This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6]
* | | |This bit is set by hardware when a triggered ISP meets any of the following conditions:
* | | |(1) APROM writes to itself if APUEN is set to 0.
* | | |(2) LDROM writes to itself if LDUEN is set to 0.
* | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0.
* | | |(4) SPROM is erased/programmed if SPUEN is set to 0
* | | |(5) SPROM is programmed at SPROM secured mode.
* | | |(6) Page Erase command at LOCK mode with ICE connection
* | | |(7) Erase or Program command at brown-out detected
* | | |(8) Destination address is illegal, such as over an available range.
* | | |(9) Invalid ISP commands
* | | |(10) Vector address is mapping to SPROM region.
* |[4] |D0 |ISP DATA 0 Flag (Read Only)
* | | |This bit is set when FMC_MPDAT0 is written and auto-clear to 0 when the FMC_MPDAT0 data is programmed to flash complete.
* | | |0 = FMC_MPDAT0 register is empty, or program to flash complete.
* | | |1 = FMC_MPDAT0 register has been written, and not program to flash complete.
* |[5] |D1 |ISP DATA 1 Flag (Read Only)
* | | |This bit is set when FMC_MPDAT1 is written and auto-clear to 0 when the FMC_MPDAT1 data is programmed to flash complete.
* | | |0 = FMC_MPDAT1 register is empty, or program to flash complete.
* | | |1 = FMC_MPDAT1 register has been written, and not program to flash complete.
* |[6] |D2 |ISP DATA 2 Flag (Read Only)
* | | |This bit is set when FMC_MPDAT2 is written and auto-clear to 0 when the FMC_MPDAT2 data is programmed to flash complete.
* | | |0 = FMC_MPDAT2 register is empty, or program to flash complete.
* | | |1 = FMC_MPDAT2 register has been written, and not program to flash complete.
* |[7] |D3 |ISP DATA 3 Flag (Read Only)
* | | |This bit is set when FMC_MPDAT3 is written and auto-clear to 0 when the FMC_MPDAT3 data is programmed to flash complete.
* | | |0 = FMC_MPDAT3 register is empty, or program to flash complete.
* | | |1 = FMC_MPDAT3 register has been written, and not program to flash complete.
* @var FMC_T::MPADDR
* Offset: 0xC4 ISP Multi-Program Address Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |MPADDR |ISP Multi-word Program Address
* | | |MPADDR is the address of ISP multi-word program operation when ISPGO flag is 1.
* | | |MPADDR will keep the final ISP address when ISP multi-word program is complete.
*/
__IO uint32_t ISPCTL; /*!< [0x0000] ISP Control Register */
__IO uint32_t ISPADDR; /*!< [0x0004] ISP Address Register */
__IO uint32_t ISPDAT; /*!< [0x0008] ISP Data Register */
__IO uint32_t ISPCMD; /*!< [0x000c] ISP Command Register */
__IO uint32_t ISPTRG; /*!< [0x0010] ISP Trigger Control Register */
__I uint32_t DFBA; /*!< [0x0014] Data Flash Base Address */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE0[10];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t ISPSTS; /*!< [0x0040] ISP Status Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE1[2];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t CYCCTL; /*!< [0x004c] Flash Access Cycle Control Register */
__O uint32_t KPKEY0; /*!< [0x0050] KPROM KEY0 Data Register */
__O uint32_t KPKEY1; /*!< [0x0054] KPROM KEY1 Data Register */
__O uint32_t KPKEY2; /*!< [0x0058] KPROM KEY2 Data Register */
__IO uint32_t KPKEYTRG; /*!< [0x005c] KPROM KEY Comparison Trigger Control Register */
__IO uint32_t KPKEYSTS; /*!< [0x0060] KPROM KEY Comparison Status Register */
__I uint32_t KPKEYCNT; /*!< [0x0064] KPROM KEY-Unmatched Counting Register */
__I uint32_t KPCNT; /*!< [0x0068] KPROM KEY-Unmatched Power-On Counting Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE2[5];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t MPDAT0; /*!< [0x0080] ISP Data0 Register */
__IO uint32_t MPDAT1; /*!< [0x0084] ISP Data1 Register */
__IO uint32_t MPDAT2; /*!< [0x0088] ISP Data2 Register */
__IO uint32_t MPDAT3; /*!< [0x008c] ISP Data3 Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE3[12];
/// @endcond //HIDDEN_SYMBOLS
__I uint32_t MPSTS; /*!< [0x00c0] ISP Multi-Program Status Register */
__I uint32_t MPADDR; /*!< [0x00c4] ISP Multi-Program Address Register */
} FMC_T;
/**
@addtogroup FMC_CONST FMC Bit Field Definition
Constant Definitions for FMC Controller
@{ */
#define FMC_ISPCTL_ISPEN_Pos (0) /*!< FMC_T::ISPCTL: ISPEN Position */
#define FMC_ISPCTL_ISPEN_Msk (0x1ul << FMC_ISPCTL_ISPEN_Pos) /*!< FMC_T::ISPCTL: ISPEN Mask */
#define FMC_ISPCTL_BS_Pos (1) /*!< FMC_T::ISPCTL: BS Position */
#define FMC_ISPCTL_BS_Msk (0x1ul << FMC_ISPCTL_BS_Pos) /*!< FMC_T::ISPCTL: BS Mask */
#define FMC_ISPCTL_SPUEN_Pos (2) /*!< FMC_T::ISPCTL: SPUEN Position */
#define FMC_ISPCTL_SPUEN_Msk (0x1ul << FMC_ISPCTL_SPUEN_Pos) /*!< FMC_T::ISPCTL: SPUEN Mask */
#define FMC_ISPCTL_APUEN_Pos (3) /*!< FMC_T::ISPCTL: APUEN Position */
#define FMC_ISPCTL_APUEN_Msk (0x1ul << FMC_ISPCTL_APUEN_Pos) /*!< FMC_T::ISPCTL: APUEN Mask */
#define FMC_ISPCTL_CFGUEN_Pos (4) /*!< FMC_T::ISPCTL: CFGUEN Position */
#define FMC_ISPCTL_CFGUEN_Msk (0x1ul << FMC_ISPCTL_CFGUEN_Pos) /*!< FMC_T::ISPCTL: CFGUEN Mask */
#define FMC_ISPCTL_LDUEN_Pos (5) /*!< FMC_T::ISPCTL: LDUEN Position */
#define FMC_ISPCTL_LDUEN_Msk (0x1ul << FMC_ISPCTL_LDUEN_Pos) /*!< FMC_T::ISPCTL: LDUEN Mask */
#define FMC_ISPCTL_ISPFF_Pos (6) /*!< FMC_T::ISPCTL: ISPFF Position */
#define FMC_ISPCTL_ISPFF_Msk (0x1ul << FMC_ISPCTL_ISPFF_Pos) /*!< FMC_T::ISPCTL: ISPFF Mask */
#define FMC_ISPCTL_BL_Pos (16) /*!< FMC_T::ISPCTL: BL Position */
#define FMC_ISPCTL_BL_Msk (0x1ul << FMC_ISPCTL_BL_Pos) /*!< FMC_T::ISPCTL: BL Mask */
#define FMC_ISPADDR_ISPADDR_Pos (0) /*!< FMC_T::ISPADDR: ISPADDR Position */
#define FMC_ISPADDR_ISPADDR_Msk (0xfffffffful << FMC_ISPADDR_ISPADDR_Pos) /*!< FMC_T::ISPADDR: ISPADDR Mask */
#define FMC_ISPDAT_ISPDAT_Pos (0) /*!< FMC_T::ISPDAT: ISPDAT Position */
#define FMC_ISPDAT_ISPDAT_Msk (0xfffffffful << FMC_ISPDAT_ISPDAT_Pos) /*!< FMC_T::ISPDAT: ISPDAT Mask */
#define FMC_ISPCMD_CMD_Pos (0) /*!< FMC_T::ISPCMD: CMD Position */
#define FMC_ISPCMD_CMD_Msk (0x7ful << FMC_ISPCMD_CMD_Pos) /*!< FMC_T::ISPCMD: CMD Mask */
#define FMC_ISPTRG_ISPGO_Pos (0) /*!< FMC_T::ISPTRG: ISPGO Position */
#define FMC_ISPTRG_ISPGO_Msk (0x1ul << FMC_ISPTRG_ISPGO_Pos) /*!< FMC_T::ISPTRG: ISPGO Mask */
#define FMC_DFBA_DFBA_Pos (0) /*!< FMC_T::DFBA: DFBA Position */
#define FMC_DFBA_DFBA_Msk (0xfffffffful << FMC_DFBA_DFBA_Pos) /*!< FMC_T::DFBA: DFBA Mask */
#define FMC_ISPSTS_ISPBUSY_Pos (0) /*!< FMC_T::ISPSTS: ISPBUSY Position */
#define FMC_ISPSTS_ISPBUSY_Msk (0x1ul << FMC_ISPSTS_ISPBUSY_Pos) /*!< FMC_T::ISPSTS: ISPBUSY Mask */
#define FMC_ISPSTS_CBS_Pos (1) /*!< FMC_T::ISPSTS: CBS Position */
#define FMC_ISPSTS_CBS_Msk (0x3ul << FMC_ISPSTS_CBS_Pos) /*!< FMC_T::ISPSTS: CBS Mask */
#define FMC_ISPSTS_MBS_Pos (3) /*!< FMC_T::ISPSTS: MBS Position */
#define FMC_ISPSTS_MBS_Msk (0x1ul << FMC_ISPSTS_MBS_Pos) /*!< FMC_T::ISPSTS: MBS Mask */
#define FMC_ISPSTS_FCYCDIS_Pos (4) /*!< FMC_T::ISPSTS: FCYCDIS Position */
#define FMC_ISPSTS_FCYCDIS_Msk (0x1ul << FMC_ISPSTS_FCYCDIS_Pos) /*!< FMC_T::ISPSTS: FCYCDIS Mask */
#define FMC_ISPSTS_PGFF_Pos (5) /*!< FMC_T::ISPSTS: PGFF Position */
#define FMC_ISPSTS_PGFF_Msk (0x1ul << FMC_ISPSTS_PGFF_Pos) /*!< FMC_T::ISPSTS: PGFF Mask */
#define FMC_ISPSTS_ISPFF_Pos (6) /*!< FMC_T::ISPSTS: ISPFF Position */
#define FMC_ISPSTS_ISPFF_Msk (0x1ul << FMC_ISPSTS_ISPFF_Pos) /*!< FMC_T::ISPSTS: ISPFF Mask */
#define FMC_ISPSTS_ALLONE_Pos (7) /*!< FMC_T::ISPSTS: ALLONE Position */
#define FMC_ISPSTS_ALLONE_Msk (0x1ul << FMC_ISPSTS_ALLONE_Pos) /*!< FMC_T::ISPSTS: ALLONE Mask */
#define FMC_ISPSTS_VECMAP_Pos (9) /*!< FMC_T::ISPSTS: VECMAP Position */
#define FMC_ISPSTS_VECMAP_Msk (0x7ffful << FMC_ISPSTS_VECMAP_Pos) /*!< FMC_T::ISPSTS: VECMAP Mask */
#define FMC_ISPSTS_SCODE_Pos (31) /*!< FMC_T::ISPSTS: SCODE Position */
#define FMC_ISPSTS_SCODE_Msk (0x1ul << FMC_ISPSTS_SCODE_Pos) /*!< FMC_T::ISPSTS: SCODE Mask */
#define FMC_CYCCTL_CYCLE_Pos (0) /*!< FMC_T::CYCCTL: CYCLE Position */
#define FMC_CYCCTL_CYCLE_Msk (0xful << FMC_CYCCTL_CYCLE_Pos) /*!< FMC_T::CYCCTL: CYCLE Mask */
#define FMC_CYCCTL_FADIS_Pos (8) /*!< FMC_T::CYCCTL: FADIS Position */
#define FMC_CYCCTL_FADIS_Msk (0x1ul << FMC_CYCCTL_FADIS_Pos) /*!< FMC_T::CYCCTL: FADIS Mask */
#define FMC_KPKEY0_KPKEY0_Pos (0) /*!< FMC_T::KPKEY0: KPKEY0 Position */
#define FMC_KPKEY0_KPKEY0_Msk (0xfffffffful << FMC_KPKEY0_KPKEY0_Pos) /*!< FMC_T::KPKEY0: KPKEY0 Mask */
#define FMC_KPKEY1_KPKEY1_Pos (0) /*!< FMC_T::KPKEY1: KPKEY1 Position */
#define FMC_KPKEY1_KPKEY1_Msk (0xfffffffful << FMC_KPKEY1_KPKEY1_Pos) /*!< FMC_T::KPKEY1: KPKEY1 Mask */
#define FMC_KPKEY2_KPKEY2_Pos (0) /*!< FMC_T::KPKEY2: KPKEY2 Position */
#define FMC_KPKEY2_KPKEY2_Msk (0xfffffffful << FMC_KPKEY2_KPKEY2_Pos) /*!< FMC_T::KPKEY2: KPKEY2 Mask */
#define FMC_KPKEYTRG_KPKEYGO_Pos (0) /*!< FMC_T::KPKEYTRG: KPKEYGO Position */
#define FMC_KPKEYTRG_KPKEYGO_Msk (0x1ul << FMC_KPKEYTRG_KPKEYGO_Pos) /*!< FMC_T::KPKEYTRG: KPKEYGO Mask */
#define FMC_KPKEYTRG_TCEN_Pos (1) /*!< FMC_T::KPKEYTRG: TCEN Position */
#define FMC_KPKEYTRG_TCEN_Msk (0x1ul << FMC_KPKEYTRG_TCEN_Pos) /*!< FMC_T::KPKEYTRG: TCEN Mask */
#define FMC_KPKEYSTS_KEYBUSY_Pos (0) /*!< FMC_T::KPKEYSTS: KEYBUSY Position */
#define FMC_KPKEYSTS_KEYBUSY_Msk (0x1ul << FMC_KPKEYSTS_KEYBUSY_Pos) /*!< FMC_T::KPKEYSTS: KEYBUSY Mask */
#define FMC_KPKEYSTS_KEYLOCK_Pos (1) /*!< FMC_T::KPKEYSTS: KEYLOCK Position */
#define FMC_KPKEYSTS_KEYLOCK_Msk (0x1ul << FMC_KPKEYSTS_KEYLOCK_Pos) /*!< FMC_T::KPKEYSTS: KEYLOCK Mask */
#define FMC_KPKEYSTS_KEYMATCH_Pos (2) /*!< FMC_T::KPKEYSTS: KEYMATCH Position */
#define FMC_KPKEYSTS_KEYMATCH_Msk (0x1ul << FMC_KPKEYSTS_KEYMATCH_Pos) /*!< FMC_T::KPKEYSTS: KEYMATCH Mask */
#define FMC_KPKEYSTS_FORBID_Pos (3) /*!< FMC_T::KPKEYSTS: FORBID Position */
#define FMC_KPKEYSTS_FORBID_Msk (0x1ul << FMC_KPKEYSTS_FORBID_Pos) /*!< FMC_T::KPKEYSTS: FORBID Mask */
#define FMC_KPKEYSTS_KEYFLAG_Pos (4) /*!< FMC_T::KPKEYSTS: KEYFLAG Position */
#define FMC_KPKEYSTS_KEYFLAG_Msk (0x1ul << FMC_KPKEYSTS_KEYFLAG_Pos) /*!< FMC_T::KPKEYSTS: KEYFLAG Mask */
#define FMC_KPKEYSTS_CFGFLAG_Pos (5) /*!< FMC_T::KPKEYSTS: CFGFLAG Position */
#define FMC_KPKEYSTS_CFGFLAG_Msk (0x1ul << FMC_KPKEYSTS_CFGFLAG_Pos) /*!< FMC_T::KPKEYSTS: CFGFLAG Mask */
#define FMC_KPKEYSTS_SPFLAG_Pos (6) /*!< FMC_T::KPKEYSTS: SPFLAG Position */
#define FMC_KPKEYSTS_SPFLAG_Msk (0x1ul << FMC_KPKEYSTS_SPFLAG_Pos) /*!< FMC_T::KPKEYSTS: SPFLAG Mask */
#define FMC_KPKEYCNT_KPKECNT_Pos (0) /*!< FMC_T::KPKEYCNT: KPKECNT Position */
#define FMC_KPKEYCNT_KPKECNT_Msk (0x3ful << FMC_KPKEYCNT_KPKECNT_Pos) /*!< FMC_T::KPKEYCNT: KPKECNT Mask */
#define FMC_KPKEYCNT_KPKEMAX_Pos (8) /*!< FMC_T::KPKEYCNT: KPKEMAX Position */
#define FMC_KPKEYCNT_KPKEMAX_Msk (0x3ful << FMC_KPKEYCNT_KPKEMAX_Pos) /*!< FMC_T::KPKEYCNT: KPKEMAX Mask */
#define FMC_KPCNT_KPCNT_Pos (0) /*!< FMC_T::KPCNT: KPCNT Position */
#define FMC_KPCNT_KPCNT_Msk (0xful << FMC_KPCNT_KPCNT_Pos) /*!< FMC_T::KPCNT: KPCNT Mask */
#define FMC_KPCNT_KPMAX_Pos (8) /*!< FMC_T::KPCNT: KPMAX Position */
#define FMC_KPCNT_KPMAX_Msk (0xful << FMC_KPCNT_KPMAX_Pos) /*!< FMC_T::KPCNT: KPMAX Mask */
#define FMC_MPDAT0_ISPDAT0_Pos (0) /*!< FMC_T::MPDAT0: ISPDAT0 Position */
#define FMC_MPDAT0_ISPDAT0_Msk (0xfffffffful << FMC_MPDAT0_ISPDAT0_Pos) /*!< FMC_T::MPDAT0: ISPDAT0 Mask */
#define FMC_MPDAT1_ISPDAT1_Pos (0) /*!< FMC_T::MPDAT1: ISPDAT1 Position */
#define FMC_MPDAT1_ISPDAT1_Msk (0xfffffffful << FMC_MPDAT1_ISPDAT1_Pos) /*!< FMC_T::MPDAT1: ISPDAT1 Mask */
#define FMC_MPDAT2_ISPDAT2_Pos (0) /*!< FMC_T::MPDAT2: ISPDAT2 Position */
#define FMC_MPDAT2_ISPDAT2_Msk (0xfffffffful << FMC_MPDAT2_ISPDAT2_Pos) /*!< FMC_T::MPDAT2: ISPDAT2 Mask */
#define FMC_MPDAT3_ISPDAT3_Pos (0) /*!< FMC_T::MPDAT3: ISPDAT3 Position */
#define FMC_MPDAT3_ISPDAT3_Msk (0xfffffffful << FMC_MPDAT3_ISPDAT3_Pos) /*!< FMC_T::MPDAT3: ISPDAT3 Mask */
#define FMC_MPSTS_MPBUSY_Pos (0) /*!< FMC_T::MPSTS: MPBUSY Position */
#define FMC_MPSTS_MPBUSY_Msk (0x1ul << FMC_MPSTS_MPBUSY_Pos) /*!< FMC_T::MPSTS: MPBUSY Mask */
#define FMC_MPSTS_PPGO_Pos (1) /*!< FMC_T::MPSTS: PPGO Position */
#define FMC_MPSTS_PPGO_Msk (0x1ul << FMC_MPSTS_PPGO_Pos) /*!< FMC_T::MPSTS: PPGO Mask */
#define FMC_MPSTS_ISPFF_Pos (2) /*!< FMC_T::MPSTS: ISPFF Position */
#define FMC_MPSTS_ISPFF_Msk (0x1ul << FMC_MPSTS_ISPFF_Pos) /*!< FMC_T::MPSTS: ISPFF Mask */
#define FMC_MPSTS_D0_Pos (4) /*!< FMC_T::MPSTS: D0 Position */
#define FMC_MPSTS_D0_Msk (0x1ul << FMC_MPSTS_D0_Pos) /*!< FMC_T::MPSTS: D0 Mask */
#define FMC_MPSTS_D1_Pos (5) /*!< FMC_T::MPSTS: D1 Position */
#define FMC_MPSTS_D1_Msk (0x1ul << FMC_MPSTS_D1_Pos) /*!< FMC_T::MPSTS: D1 Mask */
#define FMC_MPSTS_D2_Pos (6) /*!< FMC_T::MPSTS: D2 Position */
#define FMC_MPSTS_D2_Msk (0x1ul << FMC_MPSTS_D2_Pos) /*!< FMC_T::MPSTS: D2 Mask */
#define FMC_MPSTS_D3_Pos (7) /*!< FMC_T::MPSTS: D3 Position */
#define FMC_MPSTS_D3_Msk (0x1ul << FMC_MPSTS_D3_Pos) /*!< FMC_T::MPSTS: D3 Mask */
#define FMC_MPADDR_MPADDR_Pos (0) /*!< FMC_T::MPADDR: MPADDR Position */
#define FMC_MPADDR_MPADDR_Msk (0xfffffffful << FMC_MPADDR_MPADDR_Pos) /*!< FMC_T::MPADDR: MPADDR Mask */
/**@}*/ /* FMC_CONST */
/**@}*/ /* end of FMC register group */
/*---------------------- General Purpose Input/Output Controller -------------------------*/
/**
@addtogroup GPIO General Purpose Input/Output Controller(GPIO)
Memory Mapped Structure for GPIO Controller
@{ */
typedef struct {
/**
* @var GPIO_T::MODE
* Offset: 0x00/0x40/0x80/0xC0/0x100/0x140/0x180/0x1C0 Port A-H I/O Mode Control
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[2n+1:2n]|MODEn |Port A-H I/O Pin[n] Mode Control
* | | |Determine each I/O mode of Px.n pins.
* | | |00 = Px.n is in Input mode.
* | | |01 = Px.n is in Push-pull Output mode.
* | | |10 = Px.n is in Open-drain Output mode.
* | | |11 = Px.n is in Quasi-bidirectional mode.
* | | |Note1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).
* | | |If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.
* | | |If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
* | | |Note2:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* @var GPIO_T::DINOFF
* Offset: 0x04/0x44/0x84/0xC4/0x104/0x144/0x184/0x1C4 Port A-H Digital Input Path Disable Control
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[n+16] |DINOFFn |Port A-H Pin[n] Digital Input Path Disable Control
* | | |Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled.
* | | |If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
* | | |0 = Px.n digital input path Enabled.
* | | |1 = Px.n digital input path Disabled (digital input tied to low).
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* @var GPIO_T::DOUT
* Offset: 0x08/0x48/0x88/0xC8/0x108/0x148/0x188/0x1C8 Port A-H Data Output Value
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[n] |DOUTn |Port A-H Pin[n] Output Value
* | | |Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
* | | |0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
* | | |1 = Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* @var GPIO_T::DATMSK
* Offset: 0x0C/0x4C/0x8C/0xCC/0x10C/0x14C/0x18C/0x1CC Port A-H Data Output Write Mask
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[n] |DATMSKn |Port A-H Pin[n] Data Output Write Mask
* | | |These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit.
* | | |When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected.
* | | |If the write signal is masked, writing data to the protect bit is ignored.
* | | |0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated.
* | | |1 = Corresponding DOUT (Px_DOUT[n]) bit protected.
* | | |Note1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[n]) bit.
* | | |Note2:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* @var GPIO_T::PIN
* Offset: 0x10/0x50/0x90/0xD0/0x110/0x150/0x190/0x1D0 Port A-H Pin Value
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[n] |PINn |Port A-H Pin[n] Pin Value
* | | |Each bit of the register reflects the actual status of the respective Px.n pin.
* | | |If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* @var GPIO_T::DBEN
* Offset: 0x14/0x54/0x94/0xD4/0x114/0x154/0x194/0x1D4 Port A-H De-Bounce Enable Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[n] |DBENn |Port A-H Pin[n] Input Signal De-Bounce Enable Bit
* | | |The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit.
* | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt.
* | | |The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
* | | |0 = Px.n de-bounce function Disabled.
* | | |1 = Px.n de-bounce function Enabled.
* | | |The de-bounce function is valid only for edge triggered interrupt.
* | | |If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* @var GPIO_T::INTTYPE
* Offset: 0x18/0x58/0x98/0xD8/0x118/0x158/0x198/0x1D8 Port A-H Interrupt Trigger Type Control
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[n] |TYPEn |Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control
* | | |TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger.
* | | |If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce.
* | | |If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
* | | |0 = Edge trigger interrupt.
* | | |1 = Level trigger interrupt.
* | | |If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]).
* | | |If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
* | | |The de-bounce function is valid only for edge triggered interrupt.
* | | |If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* @var GPIO_T::INTEN
* Offset: 0x1C/0x5C/0x9C/0xDC/0x11C/0x15C/0x19C/0x1DC Port A-H Interrupt Enable Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[n] |FLIENn |Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
* | | |The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin.
* | | |Set bit to 1 also enable the pin wake-up function.
* | | |When setting the FLIEN (Px_INTEN[n]) bit to 1 :
* | | |If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
* | | |If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
* | | |0 = Px.n level low or high to low interrupt Disabled.
* | | |1 = Px.n level low or high to low interrupt Enabled.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* |[n+16] |RHIENn |Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
* | | |The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin
* | | |Set bit to 1 also enable the pin wake-up function.
* | | |When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
* | | |If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
* | | |If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
* | | |0 = Px.n level high or low to high interrupt Disabled.
* | | |1 = Px.n level high or low to high interrupt Enabled.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* @var GPIO_T::INTSRC
* Offset: 0x20/0x60/0xA0/0xE0/0x120/0x160/0x1A0/0x1E0 Port A-H Interrupt Source Flag
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[n] |INTSRCn |Port A-H Pin[n] Interrupt Source Flag
* | | |Write Operation :
* | | |0 = No action.
* | | |1 = Clear the corresponding pending interrupt.
* | | |Read Operation :
* | | |0 = No interrupt at Px.n.
* | | |1 = Px.n generates an interrupt.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* @var GPIO_T::SMTEN
* Offset: 0x24/0x64/0xA4/0xE4/0x124/0x164/0x1A4/0x1E4 Port A-H Input Schmitt Trigger Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[n] |SMTENn |Port A-H Pin[n] Input Schmitt Trigger Enable Bit
* | | |0 = Px.n input Schmitt trigger function Disabled.
* | | |1 = Px.n input Schmitt trigger function Enabled.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* @var GPIO_T::SLEWCTL
* Offset: 0x28/0x68/0xA8/0xE8/0x128/0x168/0x1A8/0x1E8 Port A-H High Slew Rate Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[2n+1:2n]|HSRENn |Port A-H Pin[n] High Slew Rate Control
* | | |00 = Px.n output with normal slew rate mode (maximum 40 MHz at 2.7V).
* | | |01 = Px.n output with high slew rate mode (maximum 80 MHz at 2.7V).
* | | |10 = Px.n output with fast slew rate mode (maximum 100 MHz at 2.7V.
* | | |11 = Reserved.
* | | |Note:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
* @var GPIO_T::PUSEL
* Offset: 0x30/0x70/0xB0/0xF0/0x130/0x170/0x1B0/0x1F0 Port A-H Pull-up and Pull-down Selection Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[2n+1:2n]|PUSELn |Port A-H Pin[n] Pull-up and Pull-down Enable Register
* | | |Determine each I/O Pull-up/pull-down of Px.n pins.
* | | |00 = Px.n pull-up and pull-up disable.
* | | |01 = Px.n pull-up enable.
* | | |10 = Px.n pull-down enable.
* | | |11 = Px.n pull-up and pull-up disable.
* | | |Note1:
* | | |Basically, the pull-up control and pull-down control has following behavior limitation
* | | |The independent pull-up control register only valid when MODEn set as tri-state and open-drain mode
* | | |The independent pull-down control register only valid when MODEn set as tri-state mode
* | | |When both pull-up pull-down is set as 1 at tri-state mode, keep I/O in tri-state mode
* | | |Note2:
* | | |Max. n=15 for port A/B/E/G.
* | | |Max. n=14 for port C/D.
* | | |Max. n=11 for port F/H.
*/
__IO uint32_t MODE; /* Offset: 0x00/0x40/0x80/0xC0/0x100/0x140/0x180/0x1C0 Port A-H I/O Mode Control */
__IO uint32_t DINOFF; /* Offset: 0x04/0x44/0x84/0xC4/0x104/0x144/0x184/0x1C4 Port A-H Digital Input Path Disable Control */
__IO uint32_t DOUT; /* Offset: 0x08/0x48/0x88/0xC8/0x108/0x148/0x188/0x1C8 Port A-H Data Output Value */
__IO uint32_t DATMSK; /* Offset: 0x0C/0x4C/0x8C/0xCC/0x10C/0x14C/0x18C/0x1CC Port A-H Data Output Write Mask */
__I uint32_t PIN; /* Offset: 0x10/0x50/0x90/0xD0/0x110/0x150/0x190/0x1D0 Port A-H Pin Value */
__IO uint32_t DBEN; /* Offset: 0x14/0x54/0x94/0xD4/0x114/0x154/0x194/0x1D4 Port A-H De-Bounce Enable Control Register */
__IO uint32_t INTTYPE; /* Offset: 0x18/0x58/0x98/0xD8/0x118/0x158/0x198/0x1D8 Port A-H Interrupt Trigger Type Control */
__IO uint32_t INTEN; /* Offset: 0x1C/0x5C/0x9C/0xDC/0x11C/0x15C/0x19C/0x1DC Port A-H Interrupt Enable Control Register */
__IO uint32_t INTSRC; /* Offset: 0x20/0x60/0xA0/0xE0/0x120/0x160/0x1A0/0x1E0 Port A-H Interrupt Source Flag */
__IO uint32_t SMTEN; /* Offset: 0x24/0x64/0xA4/0xE4/0x124/0x164/0x1A4/0x1E4 Port A-H Input Schmitt Trigger Enable Register */
__IO uint32_t SLEWCTL; /* Offset: 0x28/0x68/0xA8/0xE8/0x128/0x168/0x1A8/0x1E8 Port A-H High Slew Rate Control Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE0[1];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t PUSEL; /* Offset: 0x30/0x70/0xB0/0xF0/0x130/0x170/0x1B0/0x1F0 Port A-H Pull-up and Pull-down Enable Register */
} GPIO_T;
typedef struct {
/**
* @var GPIO_DBCTL_T::DBCTL
* Offset: 0x440 Interrupt De-bounce Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |DBCLKSEL |De-Bounce Sampling Cycle Selection
* | | |0000 = Sample interrupt input once per 1 clocks.
* | | |0001 = Sample interrupt input once per 2 clocks.
* | | |0010 = Sample interrupt input once per 4 clocks.
* | | |0011 = Sample interrupt input once per 8 clocks.
* | | |0100 = Sample interrupt input once per 16 clocks.
* | | |0101 = Sample interrupt input once per 32 clocks.
* | | |0110 = Sample interrupt input once per 64 clocks.
* | | |0111 = Sample interrupt input once per 128 clocks.
* | | |1000 = Sample interrupt input once per 256 clocks.
* | | |1001 = Sample interrupt input once per 2*256 clocks.
* | | |1010 = Sample interrupt input once per 4*256 clocks.
* | | |1011 = Sample interrupt input once per 8*256 clocks.
* | | |1100 = Sample interrupt input once per 16*256 clocks.
* | | |1101 = Sample interrupt input once per 32*256 clocks.
* | | |1110 = Sample interrupt input once per 64*256 clocks.
* | | |1111 = Sample interrupt input once per 128*256 clocks.
* |[4] |DBCLKSRC |De-Bounce Counter Clock Source Selection
* | | |0 = De-bounce counter clock source is the HCLK.
* | | |1 = De-bounce counter clock source is the 10 kHz internal low speed RC oscillator (LIRC).
* |[5] |ICLKON |Interrupt Clock On Mode
* | | |0 = Edge detection circuit is active only if I/O pin corresponding RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) bit is set to 1.
* | | |1 = All I/O pins edge detection circuit is always active after reset.
* | | |Note: It is recommended to disable this bit to save system power if no special application concern.
*/
__IO uint32_t DBCTL; /* Offset: 0x440 Interrupt De-bounce Control Register */
} GPIO_DBCTL_T;
/**
@addtogroup GPIO_CONST GPIO Bit Field Definition
Constant Definitions for GPIO Controller
@{ */
#define GPIO_MODE_MODE0_Pos (0) /*!< GPIO_T::MODE: MODE0 Position */
#define GPIO_MODE_MODE0_Msk (0x3ul << GPIO_MODE_MODE0_Pos) /*!< GPIO_T::MODE: MODE0 Mask */
#define GPIO_MODE_MODE1_Pos (2) /*!< GPIO_T::MODE: MODE1 Position */
#define GPIO_MODE_MODE1_Msk (0x3ul << GPIO_MODE_MODE1_Pos) /*!< GPIO_T::MODE: MODE1 Mask */
#define GPIO_MODE_MODE2_Pos (4) /*!< GPIO_T::MODE: MODE2 Position */
#define GPIO_MODE_MODE2_Msk (0x3ul << GPIO_MODE_MODE2_Pos) /*!< GPIO_T::MODE: MODE2 Mask */
#define GPIO_MODE_MODE3_Pos (6) /*!< GPIO_T::MODE: MODE3 Position */
#define GPIO_MODE_MODE3_Msk (0x3ul << GPIO_MODE_MODE3_Pos) /*!< GPIO_T::MODE: MODE3 Mask */
#define GPIO_MODE_MODE4_Pos (8) /*!< GPIO_T::MODE: MODE4 Position */
#define GPIO_MODE_MODE4_Msk (0x3ul << GPIO_MODE_MODE4_Pos) /*!< GPIO_T::MODE: MODE4 Mask */
#define GPIO_MODE_MODE5_Pos (10) /*!< GPIO_T::MODE: MODE5 Position */
#define GPIO_MODE_MODE5_Msk (0x3ul << GPIO_MODE_MODE5_Pos) /*!< GPIO_T::MODE: MODE5 Mask */
#define GPIO_MODE_MODE6_Pos (12) /*!< GPIO_T::MODE: MODE6 Position */
#define GPIO_MODE_MODE6_Msk (0x3ul << GPIO_MODE_MODE6_Pos) /*!< GPIO_T::MODE: MODE6 Mask */
#define GPIO_MODE_MODE7_Pos (14) /*!< GPIO_T::MODE: MODE7 Position */
#define GPIO_MODE_MODE7_Msk (0x3ul << GPIO_MODE_MODE7_Pos) /*!< GPIO_T::MODE: MODE7 Mask */
#define GPIO_MODE_MODE8_Pos (16) /*!< GPIO_T::MODE: MODE8 Position */
#define GPIO_MODE_MODE8_Msk (0x3ul << GPIO_MODE_MODE8_Pos) /*!< GPIO_T::MODE: MODE8 Mask */
#define GPIO_MODE_MODE9_Pos (18) /*!< GPIO_T::MODE: MODE9 Position */
#define GPIO_MODE_MODE9_Msk (0x3ul << GPIO_MODE_MODE9_Pos) /*!< GPIO_T::MODE: MODE9 Mask */
#define GPIO_MODE_MODE10_Pos (20) /*!< GPIO_T::MODE: MODE10 Position */
#define GPIO_MODE_MODE10_Msk (0x3ul << GPIO_MODE_MODE10_Pos) /*!< GPIO_T::MODE: MODE10 Mask */
#define GPIO_MODE_MODE11_Pos (22) /*!< GPIO_T::MODE: MODE11 Position */
#define GPIO_MODE_MODE11_Msk (0x3ul << GPIO_MODE_MODE11_Pos) /*!< GPIO_T::MODE: MODE11 Mask */
#define GPIO_MODE_MODE12_Pos (24) /*!< GPIO_T::MODE: MODE12 Position */
#define GPIO_MODE_MODE12_Msk (0x3ul << GPIO_MODE_MODE12_Pos) /*!< GPIO_T::MODE: MODE12 Mask */
#define GPIO_MODE_MODE13_Pos (26) /*!< GPIO_T::MODE: MODE13 Position */
#define GPIO_MODE_MODE13_Msk (0x3ul << GPIO_MODE_MODE13_Pos) /*!< GPIO_T::MODE: MODE13 Mask */
#define GPIO_MODE_MODE14_Pos (28) /*!< GPIO_T::MODE: MODE14 Position */
#define GPIO_MODE_MODE14_Msk (0x3ul << GPIO_MODE_MODE14_Pos) /*!< GPIO_T::MODE: MODE14 Mask */
#define GPIO_MODE_MODE15_Pos (30) /*!< GPIO_T::MODE: MODE15 Position */
#define GPIO_MODE_MODE15_Msk (0x3ul << GPIO_MODE_MODE15_Pos) /*!< GPIO_T::MODE: MODE15 Mask */
#define GPIO_DINOFF_DINOFF0_Pos (16) /*!< GPIO_T::DINOFF: DINOFF0 Position */
#define GPIO_DINOFF_DINOFF0_Msk (0x1ul << GPIO_DINOFF_DINOFF0_Pos) /*!< GPIO_T::DINOFF: DINOFF0 Mask */
#define GPIO_DINOFF_DINOFF1_Pos (17) /*!< GPIO_T::DINOFF: DINOFF1 Position */
#define GPIO_DINOFF_DINOFF1_Msk (0x1ul << GPIO_DINOFF_DINOFF1_Pos) /*!< GPIO_T::DINOFF: DINOFF1 Mask */
#define GPIO_DINOFF_DINOFF2_Pos (18) /*!< GPIO_T::DINOFF: DINOFF2 Position */
#define GPIO_DINOFF_DINOFF2_Msk (0x1ul << GPIO_DINOFF_DINOFF2_Pos) /*!< GPIO_T::DINOFF: DINOFF2 Mask */
#define GPIO_DINOFF_DINOFF3_Pos (19) /*!< GPIO_T::DINOFF: DINOFF3 Position */
#define GPIO_DINOFF_DINOFF3_Msk (0x1ul << GPIO_DINOFF_DINOFF3_Pos) /*!< GPIO_T::DINOFF: DINOFF3 Mask */
#define GPIO_DINOFF_DINOFF4_Pos (20) /*!< GPIO_T::DINOFF: DINOFF4 Position */
#define GPIO_DINOFF_DINOFF4_Msk (0x1ul << GPIO_DINOFF_DINOFF4_Pos) /*!< GPIO_T::DINOFF: DINOFF4 Mask */
#define GPIO_DINOFF_DINOFF5_Pos (21) /*!< GPIO_T::DINOFF: DINOFF5 Position */
#define GPIO_DINOFF_DINOFF5_Msk (0x1ul << GPIO_DINOFF_DINOFF5_Pos) /*!< GPIO_T::DINOFF: DINOFF5 Mask */
#define GPIO_DINOFF_DINOFF6_Pos (22) /*!< GPIO_T::DINOFF: DINOFF6 Position */
#define GPIO_DINOFF_DINOFF6_Msk (0x1ul << GPIO_DINOFF_DINOFF6_Pos) /*!< GPIO_T::DINOFF: DINOFF6 Mask */
#define GPIO_DINOFF_DINOFF7_Pos (23) /*!< GPIO_T::DINOFF: DINOFF7 Position */
#define GPIO_DINOFF_DINOFF7_Msk (0x1ul << GPIO_DINOFF_DINOFF7_Pos) /*!< GPIO_T::DINOFF: DINOFF7 Mask */
#define GPIO_DINOFF_DINOFF8_Pos (24) /*!< GPIO_T::DINOFF: DINOFF8 Position */
#define GPIO_DINOFF_DINOFF8_Msk (0x1ul << GPIO_DINOFF_DINOFF8_Pos) /*!< GPIO_T::DINOFF: DINOFF8 Mask */
#define GPIO_DINOFF_DINOFF9_Pos (25) /*!< GPIO_T::DINOFF: DINOFF9 Position */
#define GPIO_DINOFF_DINOFF9_Msk (0x1ul << GPIO_DINOFF_DINOFF9_Pos) /*!< GPIO_T::DINOFF: DINOFF9 Mask */
#define GPIO_DINOFF_DINOFF10_Pos (26) /*!< GPIO_T::DINOFF: DINOFF10 Position */
#define GPIO_DINOFF_DINOFF10_Msk (0x1ul << GPIO_DINOFF_DINOFF10_Pos) /*!< GPIO_T::DINOFF: DINOFF10 Mask */
#define GPIO_DINOFF_DINOFF11_Pos (27) /*!< GPIO_T::DINOFF: DINOFF11 Position */
#define GPIO_DINOFF_DINOFF11_Msk (0x1ul << GPIO_DINOFF_DINOFF11_Pos) /*!< GPIO_T::DINOFF: DINOFF11 Mask */
#define GPIO_DINOFF_DINOFF12_Pos (28) /*!< GPIO_T::DINOFF: DINOFF12 Position */
#define GPIO_DINOFF_DINOFF12_Msk (0x1ul << GPIO_DINOFF_DINOFF12_Pos) /*!< GPIO_T::DINOFF: DINOFF12 Mask */
#define GPIO_DINOFF_DINOFF13_Pos (29) /*!< GPIO_T::DINOFF: DINOFF13 Position */
#define GPIO_DINOFF_DINOFF13_Msk (0x1ul << GPIO_DINOFF_DINOFF13_Pos) /*!< GPIO_T::DINOFF: DINOFF13 Mask */
#define GPIO_DINOFF_DINOFF14_Pos (30) /*!< GPIO_T::DINOFF: DINOFF14 Position */
#define GPIO_DINOFF_DINOFF14_Msk (0x1ul << GPIO_DINOFF_DINOFF14_Pos) /*!< GPIO_T::DINOFF: DINOFF14 Mask */
#define GPIO_DINOFF_DINOFF15_Pos (31) /*!< GPIO_T::DINOFF: DINOFF15 Position */
#define GPIO_DINOFF_DINOFF15_Msk (0x1ul << GPIO_DINOFF_DINOFF15_Pos) /*!< GPIO_T::DINOFF: DINOFF15 Mask */
#define GPIO_DOUT_DOUT0_Pos (0) /*!< GPIO_T::DOUT: DOUT0 Position */
#define GPIO_DOUT_DOUT0_Msk (0x1ul << GPIO_DOUT_DOUT0_Pos) /*!< GPIO_T::DOUT: DOUT0 Mask */
#define GPIO_DOUT_DOUT1_Pos (1) /*!< GPIO_T::DOUT: DOUT1 Position */
#define GPIO_DOUT_DOUT1_Msk (0x1ul << GPIO_DOUT_DOUT1_Pos) /*!< GPIO_T::DOUT: DOUT1 Mask */
#define GPIO_DOUT_DOUT2_Pos (2) /*!< GPIO_T::DOUT: DOUT2 Position */
#define GPIO_DOUT_DOUT2_Msk (0x1ul << GPIO_DOUT_DOUT2_Pos) /*!< GPIO_T::DOUT: DOUT2 Mask */
#define GPIO_DOUT_DOUT3_Pos (3) /*!< GPIO_T::DOUT: DOUT3 Position */
#define GPIO_DOUT_DOUT3_Msk (0x1ul << GPIO_DOUT_DOUT3_Pos) /*!< GPIO_T::DOUT: DOUT3 Mask */
#define GPIO_DOUT_DOUT4_Pos (4) /*!< GPIO_T::DOUT: DOUT4 Position */
#define GPIO_DOUT_DOUT4_Msk (0x1ul << GPIO_DOUT_DOUT4_Pos) /*!< GPIO_T::DOUT: DOUT4 Mask */
#define GPIO_DOUT_DOUT5_Pos (5) /*!< GPIO_T::DOUT: DOUT5 Position */
#define GPIO_DOUT_DOUT5_Msk (0x1ul << GPIO_DOUT_DOUT5_Pos) /*!< GPIO_T::DOUT: DOUT5 Mask */
#define GPIO_DOUT_DOUT6_Pos (6) /*!< GPIO_T::DOUT: DOUT6 Position */
#define GPIO_DOUT_DOUT6_Msk (0x1ul << GPIO_DOUT_DOUT6_Pos) /*!< GPIO_T::DOUT: DOUT6 Mask */
#define GPIO_DOUT_DOUT7_Pos (7) /*!< GPIO_T::DOUT: DOUT7 Position */
#define GPIO_DOUT_DOUT7_Msk (0x1ul << GPIO_DOUT_DOUT7_Pos) /*!< GPIO_T::DOUT: DOUT7 Mask */
#define GPIO_DOUT_DOUT8_Pos (8) /*!< GPIO_T::DOUT: DOUT8 Position */
#define GPIO_DOUT_DOUT8_Msk (0x1ul << GPIO_DOUT_DOUT8_Pos) /*!< GPIO_T::DOUT: DOUT8 Mask */
#define GPIO_DOUT_DOUT9_Pos (9) /*!< GPIO_T::DOUT: DOUT9 Position */
#define GPIO_DOUT_DOUT9_Msk (0x1ul << GPIO_DOUT_DOUT9_Pos) /*!< GPIO_T::DOUT: DOUT9 Mask */
#define GPIO_DOUT_DOUT10_Pos (10) /*!< GPIO_T::DOUT: DOUT10 Position */
#define GPIO_DOUT_DOUT10_Msk (0x1ul << GPIO_DOUT_DOUT10_Pos) /*!< GPIO_T::DOUT: DOUT10 Mask */
#define GPIO_DOUT_DOUT11_Pos (11) /*!< GPIO_T::DOUT: DOUT11 Position */
#define GPIO_DOUT_DOUT11_Msk (0x1ul << GPIO_DOUT_DOUT11_Pos) /*!< GPIO_T::DOUT: DOUT11 Mask */
#define GPIO_DOUT_DOUT12_Pos (12) /*!< GPIO_T::DOUT: DOUT12 Position */
#define GPIO_DOUT_DOUT12_Msk (0x1ul << GPIO_DOUT_DOUT12_Pos) /*!< GPIO_T::DOUT: DOUT12 Mask */
#define GPIO_DOUT_DOUT13_Pos (13) /*!< GPIO_T::DOUT: DOUT13 Position */
#define GPIO_DOUT_DOUT13_Msk (0x1ul << GPIO_DOUT_DOUT13_Pos) /*!< GPIO_T::DOUT: DOUT13 Mask */
#define GPIO_DOUT_DOUT14_Pos (14) /*!< GPIO_T::DOUT: DOUT14 Position */
#define GPIO_DOUT_DOUT14_Msk (0x1ul << GPIO_DOUT_DOUT14_Pos) /*!< GPIO_T::DOUT: DOUT14 Mask */
#define GPIO_DOUT_DOUT15_Pos (15) /*!< GPIO_T::DOUT: DOUT15 Position */
#define GPIO_DOUT_DOUT15_Msk (0x1ul << GPIO_DOUT_DOUT15_Pos) /*!< GPIO_T::DOUT: DOUT15 Mask */
#define GPIO_DATMSK_DATMSK0_Pos (0) /*!< GPIO_T::DATMSK: DATMSK0 Position */
#define GPIO_DATMSK_DATMSK0_Msk (0x1ul << GPIO_DATMSK_DATMSK0_Pos) /*!< GPIO_T::DATMSK: DATMSK0 Mask */
#define GPIO_DATMSK_DATMSK1_Pos (1) /*!< GPIO_T::DATMSK: DATMSK1 Position */
#define GPIO_DATMSK_DATMSK1_Msk (0x1ul << GPIO_DATMSK_DATMSK1_Pos) /*!< GPIO_T::DATMSK: DATMSK1 Mask */
#define GPIO_DATMSK_DATMSK2_Pos (2) /*!< GPIO_T::DATMSK: DATMSK2 Position */
#define GPIO_DATMSK_DATMSK2_Msk (0x1ul << GPIO_DATMSK_DATMSK2_Pos) /*!< GPIO_T::DATMSK: DATMSK2 Mask */
#define GPIO_DATMSK_DATMSK3_Pos (3) /*!< GPIO_T::DATMSK: DATMSK3 Position */
#define GPIO_DATMSK_DATMSK3_Msk (0x1ul << GPIO_DATMSK_DATMSK3_Pos) /*!< GPIO_T::DATMSK: DATMSK3 Mask */
#define GPIO_DATMSK_DATMSK4_Pos (4) /*!< GPIO_T::DATMSK: DATMSK4 Position */
#define GPIO_DATMSK_DATMSK4_Msk (0x1ul << GPIO_DATMSK_DATMSK4_Pos) /*!< GPIO_T::DATMSK: DATMSK4 Mask */
#define GPIO_DATMSK_DATMSK5_Pos (5) /*!< GPIO_T::DATMSK: DATMSK5 Position */
#define GPIO_DATMSK_DATMSK5_Msk (0x1ul << GPIO_DATMSK_DATMSK5_Pos) /*!< GPIO_T::DATMSK: DATMSK5 Mask */
#define GPIO_DATMSK_DATMSK6_Pos (6) /*!< GPIO_T::DATMSK: DATMSK6 Position */
#define GPIO_DATMSK_DATMSK6_Msk (0x1ul << GPIO_DATMSK_DATMSK6_Pos) /*!< GPIO_T::DATMSK: DATMSK6 Mask */
#define GPIO_DATMSK_DATMSK7_Pos (7) /*!< GPIO_T::DATMSK: DATMSK7 Position */
#define GPIO_DATMSK_DATMSK7_Msk (0x1ul << GPIO_DATMSK_DATMSK7_Pos) /*!< GPIO_T::DATMSK: DATMSK7 Mask */
#define GPIO_DATMSK_DATMSK8_Pos (8) /*!< GPIO_T::DATMSK: DATMSK8 Position */
#define GPIO_DATMSK_DATMSK8_Msk (0x1ul << GPIO_DATMSK_DATMSK8_Pos) /*!< GPIO_T::DATMSK: DATMSK8 Mask */
#define GPIO_DATMSK_DATMSK9_Pos (9) /*!< GPIO_T::DATMSK: DATMSK9 Position */
#define GPIO_DATMSK_DATMSK9_Msk (0x1ul << GPIO_DATMSK_DATMSK9_Pos) /*!< GPIO_T::DATMSK: DATMSK9 Mask */
#define GPIO_DATMSK_DATMSK10_Pos (10) /*!< GPIO_T::DATMSK: DATMSK10 Position */
#define GPIO_DATMSK_DATMSK10_Msk (0x1ul << GPIO_DATMSK_DATMSK10_Pos) /*!< GPIO_T::DATMSK: DATMSK10 Mask */
#define GPIO_DATMSK_DATMSK11_Pos (11) /*!< GPIO_T::DATMSK: DATMSK11 Position */
#define GPIO_DATMSK_DATMSK11_Msk (0x1ul << GPIO_DATMSK_DATMSK11_Pos) /*!< GPIO_T::DATMSK: DATMSK11 Mask */
#define GPIO_DATMSK_DATMSK12_Pos (12) /*!< GPIO_T::DATMSK: DATMSK12 Position */
#define GPIO_DATMSK_DATMSK12_Msk (0x1ul << GPIO_DATMSK_DATMSK12_Pos) /*!< GPIO_T::DATMSK: DATMSK12 Mask */
#define GPIO_DATMSK_DATMSK13_Pos (13) /*!< GPIO_T::DATMSK: DATMSK13 Position */
#define GPIO_DATMSK_DATMSK13_Msk (0x1ul << GPIO_DATMSK_DATMSK13_Pos) /*!< GPIO_T::DATMSK: DATMSK13 Mask */
#define GPIO_DATMSK_DATMSK14_Pos (14) /*!< GPIO_T::DATMSK: DATMSK14 Position */
#define GPIO_DATMSK_DATMSK14_Msk (0x1ul << GPIO_DATMSK_DATMSK14_Pos) /*!< GPIO_T::DATMSK: DATMSK14 Mask */
#define GPIO_DATMSK_DATMSK15_Pos (15) /*!< GPIO_T::DATMSK: DATMSK15 Position */
#define GPIO_DATMSK_DATMSK15_Msk (0x1ul << GPIO_DATMSK_DATMSK15_Pos) /*!< GPIO_T::DATMSK: DATMSK15 Mask */
#define GPIO_PIN_PIN0_Pos (0) /*!< GPIO_T::PIN: PIN0 Position */
#define GPIO_PIN_PIN0_Msk (0x1ul << GPIO_PIN_PIN0_Pos) /*!< GPIO_T::PIN: PIN0 Mask */
#define GPIO_PIN_PIN1_Pos (1) /*!< GPIO_T::PIN: PIN1 Position */
#define GPIO_PIN_PIN1_Msk (0x1ul << GPIO_PIN_PIN1_Pos) /*!< GPIO_T::PIN: PIN1 Mask */
#define GPIO_PIN_PIN2_Pos (2) /*!< GPIO_T::PIN: PIN2 Position */
#define GPIO_PIN_PIN2_Msk (0x1ul << GPIO_PIN_PIN2_Pos) /*!< GPIO_T::PIN: PIN2 Mask */
#define GPIO_PIN_PIN3_Pos (3) /*!< GPIO_T::PIN: PIN3 Position */
#define GPIO_PIN_PIN3_Msk (0x1ul << GPIO_PIN_PIN3_Pos) /*!< GPIO_T::PIN: PIN3 Mask */
#define GPIO_PIN_PIN4_Pos (4) /*!< GPIO_T::PIN: PIN4 Position */
#define GPIO_PIN_PIN4_Msk (0x1ul << GPIO_PIN_PIN4_Pos) /*!< GPIO_T::PIN: PIN4 Mask */
#define GPIO_PIN_PIN5_Pos (5) /*!< GPIO_T::PIN: PIN5 Position */
#define GPIO_PIN_PIN5_Msk (0x1ul << GPIO_PIN_PIN5_Pos) /*!< GPIO_T::PIN: PIN5 Mask */
#define GPIO_PIN_PIN6_Pos (6) /*!< GPIO_T::PIN: PIN6 Position */
#define GPIO_PIN_PIN6_Msk (0x1ul << GPIO_PIN_PIN6_Pos) /*!< GPIO_T::PIN: PIN6 Mask */
#define GPIO_PIN_PIN7_Pos (7) /*!< GPIO_T::PIN: PIN7 Position */
#define GPIO_PIN_PIN7_Msk (0x1ul << GPIO_PIN_PIN7_Pos) /*!< GPIO_T::PIN: PIN7 Mask */
#define GPIO_PIN_PIN8_Pos (8) /*!< GPIO_T::PIN: PIN8 Position */
#define GPIO_PIN_PIN8_Msk (0x1ul << GPIO_PIN_PIN8_Pos) /*!< GPIO_T::PIN: PIN8 Mask */
#define GPIO_PIN_PIN9_Pos (9) /*!< GPIO_T::PIN: PIN9 Position */
#define GPIO_PIN_PIN9_Msk (0x1ul << GPIO_PIN_PIN9_Pos) /*!< GPIO_T::PIN: PIN9 Mask */
#define GPIO_PIN_PIN10_Pos (10) /*!< GPIO_T::PIN: PIN10 Position */
#define GPIO_PIN_PIN10_Msk (0x1ul << GPIO_PIN_PIN10_Pos) /*!< GPIO_T::PIN: PIN10 Mask */
#define GPIO_PIN_PIN11_Pos (11) /*!< GPIO_T::PIN: PIN11 Position */
#define GPIO_PIN_PIN11_Msk (0x1ul << GPIO_PIN_PIN11_Pos) /*!< GPIO_T::PIN: PIN11 Mask */
#define GPIO_PIN_PIN12_Pos (12) /*!< GPIO_T::PIN: PIN12 Position */
#define GPIO_PIN_PIN12_Msk (0x1ul << GPIO_PIN_PIN12_Pos) /*!< GPIO_T::PIN: PIN12 Mask */
#define GPIO_PIN_PIN13_Pos (13) /*!< GPIO_T::PIN: PIN13 Position */
#define GPIO_PIN_PIN13_Msk (0x1ul << GPIO_PIN_PIN13_Pos) /*!< GPIO_T::PIN: PIN13 Mask */
#define GPIO_PIN_PIN14_Pos (14) /*!< GPIO_T::PIN: PIN14 Position */
#define GPIO_PIN_PIN14_Msk (0x1ul << GPIO_PIN_PIN14_Pos) /*!< GPIO_T::PIN: PIN14 Mask */
#define GPIO_PIN_PIN15_Pos (15) /*!< GPIO_T::PIN: PIN15 Position */
#define GPIO_PIN_PIN15_Msk (0x1ul << GPIO_PIN_PIN15_Pos) /*!< GPIO_T::PIN: PIN15 Mask */
#define GPIO_DBEN_DBEN0_Pos (0) /*!< GPIO_T::DBEN: DBEN0 Position */
#define GPIO_DBEN_DBEN0_Msk (0x1ul << GPIO_DBEN_DBEN0_Pos) /*!< GPIO_T::DBEN: DBEN0 Mask */
#define GPIO_DBEN_DBEN1_Pos (1) /*!< GPIO_T::DBEN: DBEN1 Position */
#define GPIO_DBEN_DBEN1_Msk (0x1ul << GPIO_DBEN_DBEN1_Pos) /*!< GPIO_T::DBEN: DBEN1 Mask */
#define GPIO_DBEN_DBEN2_Pos (2) /*!< GPIO_T::DBEN: DBEN2 Position */
#define GPIO_DBEN_DBEN2_Msk (0x1ul << GPIO_DBEN_DBEN2_Pos) /*!< GPIO_T::DBEN: DBEN2 Mask */
#define GPIO_DBEN_DBEN3_Pos (3) /*!< GPIO_T::DBEN: DBEN3 Position */
#define GPIO_DBEN_DBEN3_Msk (0x1ul << GPIO_DBEN_DBEN3_Pos) /*!< GPIO_T::DBEN: DBEN3 Mask */
#define GPIO_DBEN_DBEN4_Pos (4) /*!< GPIO_T::DBEN: DBEN4 Position */
#define GPIO_DBEN_DBEN4_Msk (0x1ul << GPIO_DBEN_DBEN4_Pos) /*!< GPIO_T::DBEN: DBEN4 Mask */
#define GPIO_DBEN_DBEN5_Pos (5) /*!< GPIO_T::DBEN: DBEN5 Position */
#define GPIO_DBEN_DBEN5_Msk (0x1ul << GPIO_DBEN_DBEN5_Pos) /*!< GPIO_T::DBEN: DBEN5 Mask */
#define GPIO_DBEN_DBEN6_Pos (6) /*!< GPIO_T::DBEN: DBEN6 Position */
#define GPIO_DBEN_DBEN6_Msk (0x1ul << GPIO_DBEN_DBEN6_Pos) /*!< GPIO_T::DBEN: DBEN6 Mask */
#define GPIO_DBEN_DBEN7_Pos (7) /*!< GPIO_T::DBEN: DBEN7 Position */
#define GPIO_DBEN_DBEN7_Msk (0x1ul << GPIO_DBEN_DBEN7_Pos) /*!< GPIO_T::DBEN: DBEN7 Mask */
#define GPIO_DBEN_DBEN8_Pos (8) /*!< GPIO_T::DBEN: DBEN8 Position */
#define GPIO_DBEN_DBEN8_Msk (0x1ul << GPIO_DBEN_DBEN8_Pos) /*!< GPIO_T::DBEN: DBEN8 Mask */
#define GPIO_DBEN_DBEN9_Pos (9) /*!< GPIO_T::DBEN: DBEN9 Position */
#define GPIO_DBEN_DBEN9_Msk (0x1ul << GPIO_DBEN_DBEN9_Pos) /*!< GPIO_T::DBEN: DBEN9 Mask */
#define GPIO_DBEN_DBEN10_Pos (10) /*!< GPIO_T::DBEN: DBEN10 Position */
#define GPIO_DBEN_DBEN10_Msk (0x1ul << GPIO_DBEN_DBEN10_Pos) /*!< GPIO_T::DBEN: DBEN10 Mask */
#define GPIO_DBEN_DBEN11_Pos (11) /*!< GPIO_T::DBEN: DBEN11 Position */
#define GPIO_DBEN_DBEN11_Msk (0x1ul << GPIO_DBEN_DBEN11_Pos) /*!< GPIO_T::DBEN: DBEN11 Mask */
#define GPIO_DBEN_DBEN12_Pos (12) /*!< GPIO_T::DBEN: DBEN12 Position */
#define GPIO_DBEN_DBEN12_Msk (0x1ul << GPIO_DBEN_DBEN12_Pos) /*!< GPIO_T::DBEN: DBEN12 Mask */
#define GPIO_DBEN_DBEN13_Pos (13) /*!< GPIO_T::DBEN: DBEN13 Position */
#define GPIO_DBEN_DBEN13_Msk (0x1ul << GPIO_DBEN_DBEN13_Pos) /*!< GPIO_T::DBEN: DBEN13 Mask */
#define GPIO_DBEN_DBEN14_Pos (14) /*!< GPIO_T::DBEN: DBEN14 Position */
#define GPIO_DBEN_DBEN14_Msk (0x1ul << GPIO_DBEN_DBEN14_Pos) /*!< GPIO_T::DBEN: DBEN14 Mask */
#define GPIO_DBEN_DBEN15_Pos (15) /*!< GPIO_T::DBEN: DBEN15 Position */
#define GPIO_DBEN_DBEN15_Msk (0x1ul << GPIO_DBEN_DBEN15_Pos) /*!< GPIO_T::DBEN: DBEN15 Mask */
#define GPIO_INTTYPE_TYPE0_Pos (0) /*!< GPIO_T::INTTYPE: TYPE0 Position */
#define GPIO_INTTYPE_TYPE0_Msk (0x1ul << GPIO_INTTYPE_TYPE0_Pos) /*!< GPIO_T::INTTYPE: TYPE0 Mask */
#define GPIO_INTTYPE_TYPE1_Pos (1) /*!< GPIO_T::INTTYPE: TYPE1 Position */
#define GPIO_INTTYPE_TYPE1_Msk (0x1ul << GPIO_INTTYPE_TYPE1_Pos) /*!< GPIO_T::INTTYPE: TYPE1 Mask */
#define GPIO_INTTYPE_TYPE2_Pos (2) /*!< GPIO_T::INTTYPE: TYPE2 Position */
#define GPIO_INTTYPE_TYPE2_Msk (0x1ul << GPIO_INTTYPE_TYPE2_Pos) /*!< GPIO_T::INTTYPE: TYPE2 Mask */
#define GPIO_INTTYPE_TYPE3_Pos (3) /*!< GPIO_T::INTTYPE: TYPE3 Position */
#define GPIO_INTTYPE_TYPE3_Msk (0x1ul << GPIO_INTTYPE_TYPE3_Pos) /*!< GPIO_T::INTTYPE: TYPE3 Mask */
#define GPIO_INTTYPE_TYPE4_Pos (4) /*!< GPIO_T::INTTYPE: TYPE4 Position */
#define GPIO_INTTYPE_TYPE4_Msk (0x1ul << GPIO_INTTYPE_TYPE4_Pos) /*!< GPIO_T::INTTYPE: TYPE4 Mask */
#define GPIO_INTTYPE_TYPE5_Pos (5) /*!< GPIO_T::INTTYPE: TYPE5 Position */
#define GPIO_INTTYPE_TYPE5_Msk (0x1ul << GPIO_INTTYPE_TYPE5_Pos) /*!< GPIO_T::INTTYPE: TYPE5 Mask */
#define GPIO_INTTYPE_TYPE6_Pos (6) /*!< GPIO_T::INTTYPE: TYPE6 Position */
#define GPIO_INTTYPE_TYPE6_Msk (0x1ul << GPIO_INTTYPE_TYPE6_Pos) /*!< GPIO_T::INTTYPE: TYPE6 Mask */
#define GPIO_INTTYPE_TYPE7_Pos (7) /*!< GPIO_T::INTTYPE: TYPE7 Position */
#define GPIO_INTTYPE_TYPE7_Msk (0x1ul << GPIO_INTTYPE_TYPE7_Pos) /*!< GPIO_T::INTTYPE: TYPE7 Mask */
#define GPIO_INTTYPE_TYPE8_Pos (8) /*!< GPIO_T::INTTYPE: TYPE8 Position */
#define GPIO_INTTYPE_TYPE8_Msk (0x1ul << GPIO_INTTYPE_TYPE8_Pos) /*!< GPIO_T::INTTYPE: TYPE8 Mask */
#define GPIO_INTTYPE_TYPE9_Pos (9) /*!< GPIO_T::INTTYPE: TYPE9 Position */
#define GPIO_INTTYPE_TYPE9_Msk (0x1ul << GPIO_INTTYPE_TYPE9_Pos) /*!< GPIO_T::INTTYPE: TYPE9 Mask */
#define GPIO_INTTYPE_TYPE10_Pos (10) /*!< GPIO_T::INTTYPE: TYPE10 Position */
#define GPIO_INTTYPE_TYPE10_Msk (0x1ul << GPIO_INTTYPE_TYPE10_Pos) /*!< GPIO_T::INTTYPE: TYPE10 Mask */
#define GPIO_INTTYPE_TYPE11_Pos (11) /*!< GPIO_T::INTTYPE: TYPE11 Position */
#define GPIO_INTTYPE_TYPE11_Msk (0x1ul << GPIO_INTTYPE_TYPE11_Pos) /*!< GPIO_T::INTTYPE: TYPE11 Mask */
#define GPIO_INTTYPE_TYPE12_Pos (12) /*!< GPIO_T::INTTYPE: TYPE12 Position */
#define GPIO_INTTYPE_TYPE12_Msk (0x1ul << GPIO_INTTYPE_TYPE12_Pos) /*!< GPIO_T::INTTYPE: TYPE12 Mask */
#define GPIO_INTTYPE_TYPE13_Pos (13) /*!< GPIO_T::INTTYPE: TYPE13 Position */
#define GPIO_INTTYPE_TYPE13_Msk (0x1ul << GPIO_INTTYPE_TYPE13_Pos) /*!< GPIO_T::INTTYPE: TYPE13 Mask */
#define GPIO_INTTYPE_TYPE14_Pos (14) /*!< GPIO_T::INTTYPE: TYPE14 Position */
#define GPIO_INTTYPE_TYPE14_Msk (0x1ul << GPIO_INTTYPE_TYPE14_Pos) /*!< GPIO_T::INTTYPE: TYPE14 Mask */
#define GPIO_INTTYPE_TYPE15_Pos (15) /*!< GPIO_T::INTTYPE: TYPE15 Position */
#define GPIO_INTTYPE_TYPE15_Msk (0x1ul << GPIO_INTTYPE_TYPE15_Pos) /*!< GPIO_T::INTTYPE: TYPE15 Mask */
#define GPIO_INTEN_FLIEN0_Pos (0) /*!< GPIO_T::INTEN: FLIEN0 Position */
#define GPIO_INTEN_FLIEN0_Msk (0x1ul << GPIO_INTEN_FLIEN0_Pos) /*!< GPIO_T::INTEN: FLIEN0 Mask */
#define GPIO_INTEN_FLIEN1_Pos (1) /*!< GPIO_T::INTEN: FLIEN1 Position */
#define GPIO_INTEN_FLIEN1_Msk (0x1ul << GPIO_INTEN_FLIEN1_Pos) /*!< GPIO_T::INTEN: FLIEN1 Mask */
#define GPIO_INTEN_FLIEN2_Pos (2) /*!< GPIO_T::INTEN: FLIEN2 Position */
#define GPIO_INTEN_FLIEN2_Msk (0x1ul << GPIO_INTEN_FLIEN2_Pos) /*!< GPIO_T::INTEN: FLIEN2 Mask */
#define GPIO_INTEN_FLIEN3_Pos (3) /*!< GPIO_T::INTEN: FLIEN3 Position */
#define GPIO_INTEN_FLIEN3_Msk (0x1ul << GPIO_INTEN_FLIEN3_Pos) /*!< GPIO_T::INTEN: FLIEN3 Mask */
#define GPIO_INTEN_FLIEN4_Pos (4) /*!< GPIO_T::INTEN: FLIEN4 Position */
#define GPIO_INTEN_FLIEN4_Msk (0x1ul << GPIO_INTEN_FLIEN4_Pos) /*!< GPIO_T::INTEN: FLIEN4 Mask */
#define GPIO_INTEN_FLIEN5_Pos (5) /*!< GPIO_T::INTEN: FLIEN5 Position */
#define GPIO_INTEN_FLIEN5_Msk (0x1ul << GPIO_INTEN_FLIEN5_Pos) /*!< GPIO_T::INTEN: FLIEN5 Mask */
#define GPIO_INTEN_FLIEN6_Pos (6) /*!< GPIO_T::INTEN: FLIEN6 Position */
#define GPIO_INTEN_FLIEN6_Msk (0x1ul << GPIO_INTEN_FLIEN6_Pos) /*!< GPIO_T::INTEN: FLIEN6 Mask */
#define GPIO_INTEN_FLIEN7_Pos (7) /*!< GPIO_T::INTEN: FLIEN7 Position */
#define GPIO_INTEN_FLIEN7_Msk (0x1ul << GPIO_INTEN_FLIEN7_Pos) /*!< GPIO_T::INTEN: FLIEN7 Mask */
#define GPIO_INTEN_FLIEN8_Pos (8) /*!< GPIO_T::INTEN: FLIEN8 Position */
#define GPIO_INTEN_FLIEN8_Msk (0x1ul << GPIO_INTEN_FLIEN8_Pos) /*!< GPIO_T::INTEN: FLIEN8 Mask */
#define GPIO_INTEN_FLIEN9_Pos (9) /*!< GPIO_T::INTEN: FLIEN9 Position */
#define GPIO_INTEN_FLIEN9_Msk (0x1ul << GPIO_INTEN_FLIEN9_Pos) /*!< GPIO_T::INTEN: FLIEN9 Mask */
#define GPIO_INTEN_FLIEN10_Pos (10) /*!< GPIO_T::INTEN: FLIEN10 Position */
#define GPIO_INTEN_FLIEN10_Msk (0x1ul << GPIO_INTEN_FLIEN10_Pos) /*!< GPIO_T::INTEN: FLIEN10 Mask */
#define GPIO_INTEN_FLIEN11_Pos (11) /*!< GPIO_T::INTEN: FLIEN11 Position */
#define GPIO_INTEN_FLIEN11_Msk (0x1ul << GPIO_INTEN_FLIEN11_Pos) /*!< GPIO_T::INTEN: FLIEN11 Mask */
#define GPIO_INTEN_FLIEN12_Pos (12) /*!< GPIO_T::INTEN: FLIEN12 Position */
#define GPIO_INTEN_FLIEN12_Msk (0x1ul << GPIO_INTEN_FLIEN12_Pos) /*!< GPIO_T::INTEN: FLIEN12 Mask */
#define GPIO_INTEN_FLIEN13_Pos (13) /*!< GPIO_T::INTEN: FLIEN13 Position */
#define GPIO_INTEN_FLIEN13_Msk (0x1ul << GPIO_INTEN_FLIEN13_Pos) /*!< GPIO_T::INTEN: FLIEN13 Mask */
#define GPIO_INTEN_FLIEN14_Pos (14) /*!< GPIO_T::INTEN: FLIEN14 Position */
#define GPIO_INTEN_FLIEN14_Msk (0x1ul << GPIO_INTEN_FLIEN14_Pos) /*!< GPIO_T::INTEN: FLIEN14 Mask */
#define GPIO_INTEN_FLIEN15_Pos (15) /*!< GPIO_T::INTEN: FLIEN15 Position */
#define GPIO_INTEN_FLIEN15_Msk (0x1ul << GPIO_INTEN_FLIEN15_Pos) /*!< GPIO_T::INTEN: FLIEN15 Mask */
#define GPIO_INTEN_RHIEN0_Pos (16) /*!< GPIO_T::INTEN: RHIEN0 Position */
#define GPIO_INTEN_RHIEN0_Msk (0x1ul << GPIO_INTEN_RHIEN0_Pos) /*!< GPIO_T::INTEN: RHIEN0 Mask */
#define GPIO_INTEN_RHIEN1_Pos (17) /*!< GPIO_T::INTEN: RHIEN1 Position */
#define GPIO_INTEN_RHIEN1_Msk (0x1ul << GPIO_INTEN_RHIEN1_Pos) /*!< GPIO_T::INTEN: RHIEN1 Mask */
#define GPIO_INTEN_RHIEN2_Pos (18) /*!< GPIO_T::INTEN: RHIEN2 Position */
#define GPIO_INTEN_RHIEN2_Msk (0x1ul << GPIO_INTEN_RHIEN2_Pos) /*!< GPIO_T::INTEN: RHIEN2 Mask */
#define GPIO_INTEN_RHIEN3_Pos (19) /*!< GPIO_T::INTEN: RHIEN3 Position */
#define GPIO_INTEN_RHIEN3_Msk (0x1ul << GPIO_INTEN_RHIEN3_Pos) /*!< GPIO_T::INTEN: RHIEN3 Mask */
#define GPIO_INTEN_RHIEN4_Pos (20) /*!< GPIO_T::INTEN: RHIEN4 Position */
#define GPIO_INTEN_RHIEN4_Msk (0x1ul << GPIO_INTEN_RHIEN4_Pos) /*!< GPIO_T::INTEN: RHIEN4 Mask */
#define GPIO_INTEN_RHIEN5_Pos (21) /*!< GPIO_T::INTEN: RHIEN5 Position */
#define GPIO_INTEN_RHIEN5_Msk (0x1ul << GPIO_INTEN_RHIEN5_Pos) /*!< GPIO_T::INTEN: RHIEN5 Mask */
#define GPIO_INTEN_RHIEN6_Pos (22) /*!< GPIO_T::INTEN: RHIEN6 Position */
#define GPIO_INTEN_RHIEN6_Msk (0x1ul << GPIO_INTEN_RHIEN6_Pos) /*!< GPIO_T::INTEN: RHIEN6 Mask */
#define GPIO_INTEN_RHIEN7_Pos (23) /*!< GPIO_T::INTEN: RHIEN7 Position */
#define GPIO_INTEN_RHIEN7_Msk (0x1ul << GPIO_INTEN_RHIEN7_Pos) /*!< GPIO_T::INTEN: RHIEN7 Mask */
#define GPIO_INTEN_RHIEN8_Pos (24) /*!< GPIO_T::INTEN: RHIEN8 Position */
#define GPIO_INTEN_RHIEN8_Msk (0x1ul << GPIO_INTEN_RHIEN8_Pos) /*!< GPIO_T::INTEN: RHIEN8 Mask */
#define GPIO_INTEN_RHIEN9_Pos (25) /*!< GPIO_T::INTEN: RHIEN9 Position */
#define GPIO_INTEN_RHIEN9_Msk (0x1ul << GPIO_INTEN_RHIEN9_Pos) /*!< GPIO_T::INTEN: RHIEN9 Mask */
#define GPIO_INTEN_RHIEN10_Pos (26) /*!< GPIO_T::INTEN: RHIEN10 Position */
#define GPIO_INTEN_RHIEN10_Msk (0x1ul << GPIO_INTEN_RHIEN10_Pos) /*!< GPIO_T::INTEN: RHIEN10 Mask */
#define GPIO_INTEN_RHIEN11_Pos (27) /*!< GPIO_T::INTEN: RHIEN11 Position */
#define GPIO_INTEN_RHIEN11_Msk (0x1ul << GPIO_INTEN_RHIEN11_Pos) /*!< GPIO_T::INTEN: RHIEN11 Mask */
#define GPIO_INTEN_RHIEN12_Pos (28) /*!< GPIO_T::INTEN: RHIEN12 Position */
#define GPIO_INTEN_RHIEN12_Msk (0x1ul << GPIO_INTEN_RHIEN12_Pos) /*!< GPIO_T::INTEN: RHIEN12 Mask */
#define GPIO_INTEN_RHIEN13_Pos (29) /*!< GPIO_T::INTEN: RHIEN13 Position */
#define GPIO_INTEN_RHIEN13_Msk (0x1ul << GPIO_INTEN_RHIEN13_Pos) /*!< GPIO_T::INTEN: RHIEN13 Mask */
#define GPIO_INTEN_RHIEN14_Pos (30) /*!< GPIO_T::INTEN: RHIEN14 Position */
#define GPIO_INTEN_RHIEN14_Msk (0x1ul << GPIO_INTEN_RHIEN14_Pos) /*!< GPIO_T::INTEN: RHIEN14 Mask */
#define GPIO_INTEN_RHIEN15_Pos (31) /*!< GPIO_T::INTEN: RHIEN15 Position */
#define GPIO_INTEN_RHIEN15_Msk (0x1ul << GPIO_INTEN_RHIEN15_Pos) /*!< GPIO_T::INTEN: RHIEN15 Mask */
#define GPIO_INTSRC_INTSRC0_Pos (0) /*!< GPIO_T::INTSRC: INTSRC0 Position */
#define GPIO_INTSRC_INTSRC0_Msk (0x1ul << GPIO_INTSRC_INTSRC0_Pos) /*!< GPIO_T::INTSRC: INTSRC0 Mask */
#define GPIO_INTSRC_INTSRC1_Pos (1) /*!< GPIO_T::INTSRC: INTSRC1 Position */
#define GPIO_INTSRC_INTSRC1_Msk (0x1ul << GPIO_INTSRC_INTSRC1_Pos) /*!< GPIO_T::INTSRC: INTSRC1 Mask */
#define GPIO_INTSRC_INTSRC2_Pos (2) /*!< GPIO_T::INTSRC: INTSRC2 Position */
#define GPIO_INTSRC_INTSRC2_Msk (0x1ul << GPIO_INTSRC_INTSRC2_Pos) /*!< GPIO_T::INTSRC: INTSRC2 Mask */
#define GPIO_INTSRC_INTSRC3_Pos (3) /*!< GPIO_T::INTSRC: INTSRC3 Position */
#define GPIO_INTSRC_INTSRC3_Msk (0x1ul << GPIO_INTSRC_INTSRC3_Pos) /*!< GPIO_T::INTSRC: INTSRC3 Mask */
#define GPIO_INTSRC_INTSRC4_Pos (4) /*!< GPIO_T::INTSRC: INTSRC4 Position */
#define GPIO_INTSRC_INTSRC4_Msk (0x1ul << GPIO_INTSRC_INTSRC4_Pos) /*!< GPIO_T::INTSRC: INTSRC4 Mask */
#define GPIO_INTSRC_INTSRC5_Pos (5) /*!< GPIO_T::INTSRC: INTSRC5 Position */
#define GPIO_INTSRC_INTSRC5_Msk (0x1ul << GPIO_INTSRC_INTSRC5_Pos) /*!< GPIO_T::INTSRC: INTSRC5 Mask */
#define GPIO_INTSRC_INTSRC6_Pos (6) /*!< GPIO_T::INTSRC: INTSRC6 Position */
#define GPIO_INTSRC_INTSRC6_Msk (0x1ul << GPIO_INTSRC_INTSRC6_Pos) /*!< GPIO_T::INTSRC: INTSRC6 Mask */
#define GPIO_INTSRC_INTSRC7_Pos (7) /*!< GPIO_T::INTSRC: INTSRC7 Position */
#define GPIO_INTSRC_INTSRC7_Msk (0x1ul << GPIO_INTSRC_INTSRC7_Pos) /*!< GPIO_T::INTSRC: INTSRC7 Mask */
#define GPIO_INTSRC_INTSRC8_Pos (8) /*!< GPIO_T::INTSRC: INTSRC8 Position */
#define GPIO_INTSRC_INTSRC8_Msk (0x1ul << GPIO_INTSRC_INTSRC8_Pos) /*!< GPIO_T::INTSRC: INTSRC8 Mask */
#define GPIO_INTSRC_INTSRC9_Pos (9) /*!< GPIO_T::INTSRC: INTSRC9 Position */
#define GPIO_INTSRC_INTSRC9_Msk (0x1ul << GPIO_INTSRC_INTSRC9_Pos) /*!< GPIO_T::INTSRC: INTSRC9 Mask */
#define GPIO_INTSRC_INTSRC10_Pos (10) /*!< GPIO_T::INTSRC: INTSRC10 Position */
#define GPIO_INTSRC_INTSRC10_Msk (0x1ul << GPIO_INTSRC_INTSRC10_Pos) /*!< GPIO_T::INTSRC: INTSRC10 Mask */
#define GPIO_INTSRC_INTSRC11_Pos (11) /*!< GPIO_T::INTSRC: INTSRC11 Position */
#define GPIO_INTSRC_INTSRC11_Msk (0x1ul << GPIO_INTSRC_INTSRC11_Pos) /*!< GPIO_T::INTSRC: INTSRC11 Mask */
#define GPIO_INTSRC_INTSRC12_Pos (12) /*!< GPIO_T::INTSRC: INTSRC12 Position */
#define GPIO_INTSRC_INTSRC12_Msk (0x1ul << GPIO_INTSRC_INTSRC12_Pos) /*!< GPIO_T::INTSRC: INTSRC12 Mask */
#define GPIO_INTSRC_INTSRC13_Pos (13) /*!< GPIO_T::INTSRC: INTSRC13 Position */
#define GPIO_INTSRC_INTSRC13_Msk (0x1ul << GPIO_INTSRC_INTSRC13_Pos) /*!< GPIO_T::INTSRC: INTSRC13 Mask */
#define GPIO_INTSRC_INTSRC14_Pos (14) /*!< GPIO_T::INTSRC: INTSRC14 Position */
#define GPIO_INTSRC_INTSRC14_Msk (0x1ul << GPIO_INTSRC_INTSRC14_Pos) /*!< GPIO_T::INTSRC: INTSRC14 Mask */
#define GPIO_INTSRC_INTSRC15_Pos (15) /*!< GPIO_T::INTSRC: INTSRC15 Position */
#define GPIO_INTSRC_INTSRC15_Msk (0x1ul << GPIO_INTSRC_INTSRC15_Pos) /*!< GPIO_T::INTSRC: INTSRC15 Mask */
#define GPIO_SMTEN_SMTEN0_Pos (0) /*!< GPIO_T::SMTEN: SMTEN0 Position */
#define GPIO_SMTEN_SMTEN0_Msk (0x1ul << GPIO_SMTEN_SMTEN0_Pos) /*!< GPIO_T::SMTEN: SMTEN0 Mask */
#define GPIO_SMTEN_SMTEN1_Pos (1) /*!< GPIO_T::SMTEN: SMTEN1 Position */
#define GPIO_SMTEN_SMTEN1_Msk (0x1ul << GPIO_SMTEN_SMTEN1_Pos) /*!< GPIO_T::SMTEN: SMTEN1 Mask */
#define GPIO_SMTEN_SMTEN2_Pos (2) /*!< GPIO_T::SMTEN: SMTEN2 Position */
#define GPIO_SMTEN_SMTEN2_Msk (0x1ul << GPIO_SMTEN_SMTEN2_Pos) /*!< GPIO_T::SMTEN: SMTEN2 Mask */
#define GPIO_SMTEN_SMTEN3_Pos (3) /*!< GPIO_T::SMTEN: SMTEN3 Position */
#define GPIO_SMTEN_SMTEN3_Msk (0x1ul << GPIO_SMTEN_SMTEN3_Pos) /*!< GPIO_T::SMTEN: SMTEN3 Mask */
#define GPIO_SMTEN_SMTEN4_Pos (4) /*!< GPIO_T::SMTEN: SMTEN4 Position */
#define GPIO_SMTEN_SMTEN4_Msk (0x1ul << GPIO_SMTEN_SMTEN4_Pos) /*!< GPIO_T::SMTEN: SMTEN4 Mask */
#define GPIO_SMTEN_SMTEN5_Pos (5) /*!< GPIO_T::SMTEN: SMTEN5 Position */
#define GPIO_SMTEN_SMTEN5_Msk (0x1ul << GPIO_SMTEN_SMTEN5_Pos) /*!< GPIO_T::SMTEN: SMTEN5 Mask */
#define GPIO_SMTEN_SMTEN6_Pos (6) /*!< GPIO_T::SMTEN: SMTEN6 Position */
#define GPIO_SMTEN_SMTEN6_Msk (0x1ul << GPIO_SMTEN_SMTEN6_Pos) /*!< GPIO_T::SMTEN: SMTEN6 Mask */
#define GPIO_SMTEN_SMTEN7_Pos (7) /*!< GPIO_T::SMTEN: SMTEN7 Position */
#define GPIO_SMTEN_SMTEN7_Msk (0x1ul << GPIO_SMTEN_SMTEN7_Pos) /*!< GPIO_T::SMTEN: SMTEN7 Mask */
#define GPIO_SMTEN_SMTEN8_Pos (8) /*!< GPIO_T::SMTEN: SMTEN8 Position */
#define GPIO_SMTEN_SMTEN8_Msk (0x1ul << GPIO_SMTEN_SMTEN8_Pos) /*!< GPIO_T::SMTEN: SMTEN8 Mask */
#define GPIO_SMTEN_SMTEN9_Pos (9) /*!< GPIO_T::SMTEN: SMTEN9 Position */
#define GPIO_SMTEN_SMTEN9_Msk (0x1ul << GPIO_SMTEN_SMTEN9_Pos) /*!< GPIO_T::SMTEN: SMTEN9 Mask */
#define GPIO_SMTEN_SMTEN10_Pos (10) /*!< GPIO_T::SMTEN: SMTEN10 Position */
#define GPIO_SMTEN_SMTEN10_Msk (0x1ul << GPIO_SMTEN_SMTEN10_Pos) /*!< GPIO_T::SMTEN: SMTEN10 Mask */
#define GPIO_SMTEN_SMTEN11_Pos (11) /*!< GPIO_T::SMTEN: SMTEN11 Position */
#define GPIO_SMTEN_SMTEN11_Msk (0x1ul << GPIO_SMTEN_SMTEN11_Pos) /*!< GPIO_T::SMTEN: SMTEN11 Mask */
#define GPIO_SMTEN_SMTEN12_Pos (12) /*!< GPIO_T::SMTEN: SMTEN12 Position */
#define GPIO_SMTEN_SMTEN12_Msk (0x1ul << GPIO_SMTEN_SMTEN12_Pos) /*!< GPIO_T::SMTEN: SMTEN12 Mask */
#define GPIO_SMTEN_SMTEN13_Pos (13) /*!< GPIO_T::SMTEN: SMTEN13 Position */
#define GPIO_SMTEN_SMTEN13_Msk (0x1ul << GPIO_SMTEN_SMTEN13_Pos) /*!< GPIO_T::SMTEN: SMTEN13 Mask */
#define GPIO_SMTEN_SMTEN14_Pos (14) /*!< GPIO_T::SMTEN: SMTEN14 Position */
#define GPIO_SMTEN_SMTEN14_Msk (0x1ul << GPIO_SMTEN_SMTEN14_Pos) /*!< GPIO_T::SMTEN: SMTEN14 Mask */
#define GPIO_SMTEN_SMTEN15_Pos (15) /*!< GPIO_T::SMTEN: SMTEN15 Position */
#define GPIO_SMTEN_SMTEN15_Msk (0x1ul << GPIO_SMTEN_SMTEN15_Pos) /*!< GPIO_T::SMTEN: SMTEN15 Mask */
#define GPIO_SLEWCTL_HSREN0_Pos (0) /*!< GPIO_T::SLEWCTL: HSREN0 Position */
#define GPIO_SLEWCTL_HSREN0_Msk (0x3ul << GPIO_SLEWCTL_HSREN0_Pos) /*!< GPIO_T::SLEWCTL: HSREN0 Mask */
#define GPIO_SLEWCTL_HSREN1_Pos (2) /*!< GPIO_T::SLEWCTL: HSREN1 Position */
#define GPIO_SLEWCTL_HSREN1_Msk (0x3ul << GPIO_SLEWCTL_HSREN1_Pos) /*!< GPIO_T::SLEWCTL: HSREN1 Mask */
#define GPIO_SLEWCTL_HSREN2_Pos (4) /*!< GPIO_T::SLEWCTL: HSREN2 Position */
#define GPIO_SLEWCTL_HSREN2_Msk (0x3ul << GPIO_SLEWCTL_HSREN2_Pos) /*!< GPIO_T::SLEWCTL: HSREN2 Mask */
#define GPIO_SLEWCTL_HSREN3_Pos (6) /*!< GPIO_T::SLEWCTL: HSREN3 Position */
#define GPIO_SLEWCTL_HSREN3_Msk (0x3ul << GPIO_SLEWCTL_HSREN3_Pos) /*!< GPIO_T::SLEWCTL: HSREN3 Mask */
#define GPIO_SLEWCTL_HSREN4_Pos (8) /*!< GPIO_T::SLEWCTL: HSREN4 Position */
#define GPIO_SLEWCTL_HSREN4_Msk (0x3ul << GPIO_SLEWCTL_HSREN4_Pos) /*!< GPIO_T::SLEWCTL: HSREN4 Mask */
#define GPIO_SLEWCTL_HSREN5_Pos (10) /*!< GPIO_T::SLEWCTL: HSREN5 Position */
#define GPIO_SLEWCTL_HSREN5_Msk (0x3ul << GPIO_SLEWCTL_HSREN5_Pos) /*!< GPIO_T::SLEWCTL: HSREN5 Mask */
#define GPIO_SLEWCTL_HSREN6_Pos (12) /*!< GPIO_T::SLEWCTL: HSREN6 Position */
#define GPIO_SLEWCTL_HSREN6_Msk (0x3ul << GPIO_SLEWCTL_HSREN6_Pos) /*!< GPIO_T::SLEWCTL: HSREN6 Mask */
#define GPIO_SLEWCTL_HSREN7_Pos (14) /*!< GPIO_T::SLEWCTL: HSREN7 Position */
#define GPIO_SLEWCTL_HSREN7_Msk (0x3ul << GPIO_SLEWCTL_HSREN7_Pos) /*!< GPIO_T::SLEWCTL: HSREN7 Mask */
#define GPIO_SLEWCTL_HSREN8_Pos (16) /*!< GPIO_T::SLEWCTL: HSREN8 Position */
#define GPIO_SLEWCTL_HSREN8_Msk (0x3ul << GPIO_SLEWCTL_HSREN8_Pos) /*!< GPIO_T::SLEWCTL: HSREN8 Mask */
#define GPIO_SLEWCTL_HSREN9_Pos (18) /*!< GPIO_T::SLEWCTL: HSREN9 Position */
#define GPIO_SLEWCTL_HSREN9_Msk (0x3ul << GPIO_SLEWCTL_HSREN9_Pos) /*!< GPIO_T::SLEWCTL: HSREN9 Mask */
#define GPIO_SLEWCTL_HSREN10_Pos (20) /*!< GPIO_T::SLEWCTL: HSREN10 Position */
#define GPIO_SLEWCTL_HSREN10_Msk (0x3ul << GPIO_SLEWCTL_HSREN10_Pos) /*!< GPIO_T::SLEWCTL: HSREN10 Mask */
#define GPIO_SLEWCTL_HSREN11_Pos (22) /*!< GPIO_T::SLEWCTL: HSREN11 Position */
#define GPIO_SLEWCTL_HSREN11_Msk (0x3ul << GPIO_SLEWCTL_HSREN11_Pos) /*!< GPIO_T::SLEWCTL: HSREN11 Mask */
#define GPIO_SLEWCTL_HSREN12_Pos (24) /*!< GPIO_T::SLEWCTL: HSREN12 Position */
#define GPIO_SLEWCTL_HSREN12_Msk (0x3ul << GPIO_SLEWCTL_HSREN12_Pos) /*!< GPIO_T::SLEWCTL: HSREN12 Mask */
#define GPIO_SLEWCTL_HSREN13_Pos (26) /*!< GPIO_T::SLEWCTL: HSREN13 Position */
#define GPIO_SLEWCTL_HSREN13_Msk (0x3ul << GPIO_SLEWCTL_HSREN13_Pos) /*!< GPIO_T::SLEWCTL: HSREN13 Mask */
#define GPIO_SLEWCTL_HSREN14_Pos (28) /*!< GPIO_T::SLEWCTL: HSREN14 Position */
#define GPIO_SLEWCTL_HSREN14_Msk (0x3ul << GPIO_SLEWCTL_HSREN14_Pos) /*!< GPIO_T::SLEWCTL: HSREN14 Mask */
#define GPIO_SLEWCTL_HSREN15_Pos (30) /*!< GPIO_T::SLEWCTL: HSREN15 Position */
#define GPIO_SLEWCTL_HSREN15_Msk (0x3ul << GPIO_SLEWCTL_HSREN15_Pos) /*!< GPIO_T::SLEWCTL: HSREN15 Mask */
#define GPIO_PUSEL_PUSEL0_Pos (0) /*!< GPIO_T::PUSEL: PUSEL0 Position */
#define GPIO_PUSEL_PUSEL0_Msk (0x3ul << GPIO_PUSEL_PUSEL0_Pos) /*!< GPIO_T::PUSEL: PUSEL0 Mask */
#define GPIO_PUSEL_PUSEL1_Pos (2) /*!< GPIO_T::PUSEL: PUSEL1 Position */
#define GPIO_PUSEL_PUSEL1_Msk (0x3ul << GPIO_PUSEL_PUSEL1_Pos) /*!< GPIO_T::PUSEL: PUSEL1 Mask */
#define GPIO_PUSEL_PUSEL2_Pos (4) /*!< GPIO_T::PUSEL: PUSEL2 Position */
#define GPIO_PUSEL_PUSEL2_Msk (0x3ul << GPIO_PUSEL_PUSEL2_Pos) /*!< GPIO_T::PUSEL: PUSEL2 Mask */
#define GPIO_PUSEL_PUSEL3_Pos (6) /*!< GPIO_T::PUSEL: PUSEL3 Position */
#define GPIO_PUSEL_PUSEL3_Msk (0x3ul << GPIO_PUSEL_PUSEL3_Pos) /*!< GPIO_T::PUSEL: PUSEL3 Mask */
#define GPIO_PUSEL_PUSEL4_Pos (8) /*!< GPIO_T::PUSEL: PUSEL4 Position */
#define GPIO_PUSEL_PUSEL4_Msk (0x3ul << GPIO_PUSEL_PUSEL4_Pos) /*!< GPIO_T::PUSEL: PUSEL4 Mask */
#define GPIO_PUSEL_PUSEL5_Pos (10) /*!< GPIO_T::PUSEL: PUSEL5 Position */
#define GPIO_PUSEL_PUSEL5_Msk (0x3ul << GPIO_PUSEL_PUSEL5_Pos) /*!< GPIO_T::PUSEL: PUSEL5 Mask */
#define GPIO_PUSEL_PUSEL6_Pos (12) /*!< GPIO_T::PUSEL: PUSEL6 Position */
#define GPIO_PUSEL_PUSEL6_Msk (0x3ul << GPIO_PUSEL_PUSEL6_Pos) /*!< GPIO_T::PUSEL: PUSEL6 Mask */
#define GPIO_PUSEL_PUSEL7_Pos (14) /*!< GPIO_T::PUSEL: PUSEL7 Position */
#define GPIO_PUSEL_PUSEL7_Msk (0x3ul << GPIO_PUSEL_PUSEL7_Pos) /*!< GPIO_T::PUSEL: PUSEL7 Mask */
#define GPIO_PUSEL_PUSEL8_Pos (16) /*!< GPIO_T::PUSEL: PUSEL8 Position */
#define GPIO_PUSEL_PUSEL8_Msk (0x3ul << GPIO_PUSEL_PUSEL8_Pos) /*!< GPIO_T::PUSEL: PUSEL8 Mask */
#define GPIO_PUSEL_PUSEL9_Pos (18) /*!< GPIO_T::PUSEL: PUSEL9 Position */
#define GPIO_PUSEL_PUSEL9_Msk (0x3ul << GPIO_PUSEL_PUSEL9_Pos) /*!< GPIO_T::PUSEL: PUSEL9 Mask */
#define GPIO_PUSEL_PUSEL10_Pos (20) /*!< GPIO_T::PUSEL: PUSEL10 Position */
#define GPIO_PUSEL_PUSEL10_Msk (0x3ul << GPIO_PUSEL_PUSEL10_Pos) /*!< GPIO_T::PUSEL: PUSEL10 Mask */
#define GPIO_PUSEL_PUSEL11_Pos (22) /*!< GPIO_T::PUSEL: PUSEL11 Position */
#define GPIO_PUSEL_PUSEL11_Msk (0x3ul << GPIO_PUSEL_PUSEL11_Pos) /*!< GPIO_T::PUSEL: PUSEL11 Mask */
#define GPIO_PUSEL_PUSEL12_Pos (24) /*!< GPIO_T::PUSEL: PUSEL12 Position */
#define GPIO_PUSEL_PUSEL12_Msk (0x3ul << GPIO_PUSEL_PUSEL12_Pos) /*!< GPIO_T::PUSEL: PUSEL12 Mask */
#define GPIO_PUSEL_PUSEL13_Pos (26) /*!< GPIO_T::PUSEL: PUSEL13 Position */
#define GPIO_PUSEL_PUSEL13_Msk (0x3ul << GPIO_PUSEL_PUSEL13_Pos) /*!< GPIO_T::PUSEL: PUSEL13 Mask */
#define GPIO_PUSEL_PUSEL14_Pos (28) /*!< GPIO_T::PUSEL: PUSEL14 Position */
#define GPIO_PUSEL_PUSEL14_Msk (0x3ul << GPIO_PUSEL_PUSEL14_Pos) /*!< GPIO_T::PUSEL: PUSEL14 Mask */
#define GPIO_PUSEL_PUSEL15_Pos (30) /*!< GPIO_T::PUSEL: PUSEL15 Position */
#define GPIO_PUSEL_PUSEL15_Msk (0x3ul << GPIO_PUSEL_PUSEL15_Pos) /*!< GPIO_T::PUSEL: PUSEL15 Mask */
#define GPIO_DBCTL_DBCLKSEL_Pos (0) /*!< GPIO_T::DBCTL: DBCLKSEL Position */
#define GPIO_DBCTL_DBCLKSEL_Msk (0xFul << GPIO_DBCTL_DBCLKSEL_Pos) /*!< GPIO_T::DBCTL: DBCLKSEL Mask */
#define GPIO_DBCTL_DBCLKSRC_Pos (4) /*!< GPIO_T::DBCTL: DBCLKSRC Position */
#define GPIO_DBCTL_DBCLKSRC_Msk (1ul << GPIO_DBCTL_DBCLKSRC_Pos) /*!< GPIO_T::DBCTL: DBCLKSRC Mask */
#define GPIO_DBCTL_ICLKON_Pos (5) /*!< GPIO_T::DBCTL: ICLKON Position */
#define GPIO_DBCTL_ICLKON_Msk (1ul << GPIO_DBCTL_ICLKON_Pos) /*!< GPIO_T::DBCTL: ICLKON Mask */
/**@}*/ /* GPIO_CONST */
/**@}*/ /* end of GPIO register group */
/*---------------------- Peripheral Direct Memory Access Controller -------------------------*/
/**
@addtogroup PDMA Peripheral Direct Memory Access Controller(PDMA)
Memory Mapped Structure for PDMA Controller
@{ */
typedef struct {
/**
* @var DSCT_T::CTL
* Offset: 0x00 Descriptor Table Control Register of PDMA Channel n.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1:0] |OPMODE |PDMA Operation Mode Selection
* | | |00 = Idle state: Channel is stopped or this table is complete, when PDMA finish channel table task, OPMODE will be cleared to idle state automatically.
* | | |01 = Basic mode: The descriptor table only has one task
* | | |When this task is finished, the PDMA_INTSTS[n] will be asserted.
* | | |10 = Scatter-Gather mode: When operating in this mode, user must give the next descriptor table address in PDMA_DSCT_NEXT register; PDMA controller will ignore this task, then load the next task to execute.
* | | |11 = Reserved.
* | | |Note: Before filling transfer task in the Descriptor Table, user must check if the descriptor table is complete.
* |[2] |TXTYPE |Transfer Type
* | | |0 = Burst transfer type.
* | | |1 = Single transfer type.
* |[6:4] |BURSIZE |Burst Size
* | | |This field is used for peripheral to determine the burst size or used for determine the re-arbitration size.
* | | |000 = 128 Transfers.
* | | |001 = 64 Transfers.
* | | |010 = 32 Transfers.
* | | |011 = 16 Transfers.
* | | |100 = 8 Transfers.
* | | |101 = 4 Transfers.
* | | |110 = 2 Transfers.
* | | |111 = 1 Transfers.
* | | |Note: This field is only useful in burst transfer type.
* |[7] |TBINTDIS |Table Interrupt Disable Bit
* | | |This field can be used to decide whether to enable table interrupt or not
* | | |If the TBINTDIS bit is enabled when PDMA controller finishes transfer task, it will not generates transfer done interrupt.
* | | |0 = Table interrupt Enabled.
* | | |1 = Table interrupt Disabled.
* |[9:8] |SAINC |Source Address Increment
* | | |This field is used to set the source address increment size.
* | | |11 = No increment (fixed address).
* | | |Others = Increment and size is depended on TXWIDTH selection.
* |[11:10] |DAINC |Destination Address Increment
* | | |This field is used to set the destination address increment size.
* | | |11 = No increment (fixed address).
* | | |Others = Increment and size is depended on TXWIDTH selection.
* |[13:12] |TXWIDTH |Transfer Width Selection
* | | |This field is used for transfer width.
* | | |00 = One byte (8 bit) is transferred for every operation.
* | | |01= One half-word (16 bit) is transferred for every operation.
* | | |10 = One word (32-bit) is transferred for every operation.
* | | |11 = Reserved.
* | | |Note: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection
* |[14] |TXACK |Transfer Acknowledge Selection
* | | |0 = transfer ack when transfer done.
* | | |1 = transfer ack when PDMA get transfer data.
* |[15] |STRIDEEN |Stride Mode Enable Bit
* | | |0 = Stride transfer mode Disabled.
* | | |1 = Stride transfer mode Enabled.
* |[31:16] |TXCNT |Transfer Count
* | | |The TXCNT represents the required number of PDMA transfer, the real transfer count is (TXCNT + 1); The maximum transfer count is 16384 , every transfer may be byte, half-word or word that is dependent on TXWIDTH field.
* | | |Note: When PDMA finish each transfer data, this field will be decrease immediately.
* @var DSCT_T::SA
* Offset: 0x04 Source Address Register of PDMA Channel n
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |SA |PDMA Transfer Source Address Register
* | | |This field indicates a 32-bit source address of PDMA controller.
* @var DSCT_T::DA
* Offset: 0x08 Destination Address Register of PDMA Channel n
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |DA |PDMA Transfer Destination Address Register
* | | |This field indicates a 32-bit destination address of PDMA controller.
* @var DSCT_T::NEXT
* Offset: 0x0C Next Scatter-Gather Descriptor Table Offset Address of PDMA Channel n
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |EXENEXT |PDMA Execution Next Descriptor Table Offset
* | | |This field indicates the offset of next descriptor table address of current execution descriptor table in system memory.
* | | |Note: write operation is useless in this field.
* |[31:16] |NEXT |PDMA Next Descriptor Table Offset.
* | | |This field indicates the offset of the next descriptor table address in system memory.
* | | |Write Operation:
* | | |If the system memory based address is 0x2000_0000 (PDMA_SCATBA), and the next descriptor table is start from 0x2000_0100, then this field must fill in 0x0100.
* | | |Read Operation:
* | | |When operating in scatter-gather mode, the last two bits NEXT[1:0] will become reserved, and indicate the first next address of system memory.
* | | |Note1: The descriptor table address must be word boundary.
* | | |Note2: Before filled transfer task in the descriptor table, user must check if the descriptor table is complete.
*/
__IO uint32_t CTL; /*!< [0x0000] Descriptor Table Control Register of PDMA Channel n. */
__IO uint32_t SA; /*!< [0x0004] Source Address Register of PDMA Channel n */
__IO uint32_t DA; /*!< [0x0008] Destination Address Register of PDMA Channel n */
__IO uint32_t NEXT; /*!< [0x000c] First Scatter-Gather Descriptor Table Offset Address of PDMA Channel n */
} DSCT_T;
typedef struct {
/**
* @var STRIDE_T::STCR
* Offset: 0x500 Stride Transfer Count Register of PDMA Channel n
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |STC |PDMA Stride Transfer Count
* | | |The 16-bit register defines the stride transfer count of each row.
* @var STRIDE_T::ASOCR
* Offset: 0x504 Address Stride Offset Register of PDMA Channel n
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |SASOL |VDMA Source Address Stride Offset Length
* | | |The 16-bit register defines the source address stride transfer offset count of each row.
* |[31:16] |DASOL |VDMA Destination Address Stride Offset Length
* | | |The 16-bit register defines the destination address stride transfer offset count of each row.
*/
__IO uint32_t STCR; /*!< [0x0500] Stride Transfer Count Register of PDMA Channel 0 */
__IO uint32_t ASOCR; /*!< [0x0504] Address Stride Offset Register of PDMA Channel 0 */
} STRIDE_T;
typedef struct {
/**
* @var PDMA_T::CURSCAT
* Offset: 0x100 Current Scatter-Gather Descriptor Table Address of PDMA Channel n
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |CURADDR |PDMA Current Description Address Register (Read Only)
* | | |This field indicates a 32-bit current external description address of PDMA controller.
* | | |Note: This field is read only and only used for Scatter-Gather mode to indicate the current external description address.
* @var PDMA_T::CHCTL
* Offset: 0x400 PDMA Channel Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |CHENn |PDMA Channel Enable Bit
* | | |Set this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.
* | | |0 = PDMA channel [n] Disabled.
* | | |1 = PDMA channel [n] Enabled.
* | | |Note: Set corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit.
* @var PDMA_T::PAUSE
* Offset: 0x404 PDMA Transfer Stop Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |PAUSEn |PDMA Transfer Pause Control Register (Write Only)
* | | |User can set PAUSEn bit field to pause the PDMA transfer
* | | |When user sets PAUSEn bit, the PDMA controller will pause the on-going transfer, then clear the channel enable bit CHEN(PDMA_CHCTL [n], n=0,1..7) and clear request active flag
* | | |If re-enable the paused channel again, the remaining transfers will be processed.
* | | |0 = No effect.
* | | |1 = Pause PDMA channel n transfer.
* @var PDMA_T::SWREQ
* Offset: 0x408 PDMA Software Request Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |SWREQn |PDMA Software Request Register (Write Only)
* | | |Set this bit to 1 to generate a software request to PDMA [n].
* | | |0 = No effect.
* | | |1 = Generate a software request.
* | | |Note1: User can read PDMA_TRGSTS register to know which channel is on active
* | | |Active flag may be triggered by software request or peripheral request.
* | | |Note2: If user does not enable corresponding PDMA channel, the software request will be ignored.
* @var PDMA_T::TRGSTS
* Offset: 0x40C PDMA Channel Request Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |REQSTSn |PDMA Channel Request Status (Read Only)
* | | |This flag indicates whether channel[n] have a request or not, no matter request from software or peripheral
* | | |When PDMA controller finishes channel transfer, this bit will be cleared automatically.
* | | |0 = PDMA Channel n has no request.
* | | |1 = PDMA Channel n has a request.
* | | |Note: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing current transfer.
* @var PDMA_T::PRISET
* Offset: 0x410 PDMA Fixed Priority Setting Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |FPRISETn |PDMA Fixed Priority Setting Register
* | | |Set this bit to 1 to enable fixed priority level.
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Set PDMA channel [n] to fixed priority channel.
* | | |Read Operation:
* | | |0 = Corresponding PDMA channel is round-robin priority.
* | | |1 = Corresponding PDMA channel is fixed priority.
* | | |Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
* @var PDMA_T::PRICLR
* Offset: 0x414 PDMA Fixed Priority Clear Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |FPRICLRn |PDMA Fixed Priority Clear Register (Write Only)
* | | |Set this bit to 1 to clear fixed priority level.
* | | |0 = No effect.
* | | |1 = Clear PDMA channel [n] fixed priority setting.
* | | |Note: User can read PDMA_PRISET register to know the channel priority.
* @var PDMA_T::INTEN
* Offset: 0x418 PDMA Interrupt Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |INTENn |PDMA Interrupt Enable Register
* | | |This field is used for enabling PDMA channel[n] interrupt.
* | | |0 = PDMA channel n interrupt Disabled.
* | | |1 = PDMA channel n interrupt Enabled.
* @var PDMA_T::INTSTS
* Offset: 0x41C PDMA Interrupt Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ABTIF |PDMA Read/Write Target Abort Interrupt Flag (Read-only)
* | | |This bit indicates that PDMA has target abort error; Software can read PDMA_ABTSTS register to find which channel has target abort error.
* | | |0 = No AHB bus ERROR response received.
* | | |1 = AHB bus ERROR response received.
* |[1] |TDIF |Transfer Done Interrupt Flag (Read Only)
* | | |This bit indicates that PDMA controller has finished transmission; User can read PDMA_TDSTS register to indicate which channel finished transfer.
* | | |0 = Not finished yet.
* | | |1 = PDMA channel has finished transmission.
* |[2] |ALIGNF |Transfer Alignment Interrupt Flag (Read Only)
* | | |0 = PDMA channel source address and destination address both follow transfer width setting.
* | | |1 = PDMA channel source address or destination address is not follow transfer width setting.
* |[8] |REQTOF0 |Request Time-out Flag for Channel 0
* | | |This flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOC0, user can write 1 to clear these bits.
* | | |0 = No request time-out.
* | | |1 = Peripheral request time-out.
* |[9] |REQTOF1 |Request Time-out Flag for Channel 1
* | | |This flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOC1, user can write 1 to clear these bits.
* | | |0 = No request time-out.
* | | |1 = Peripheral request time-out.
* @var PDMA_T::ABTSTS
* Offset: 0x420 PDMA Channel Read/Write Target Abort Flag Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |ABTIFn |PDMA Read/Write Target Abort Interrupt Status Flag
* | | |This bit indicates which PDMA controller has target abort error; User can write 1 to clear these bits.
* | | |0 = No AHB bus ERROR response received when channel n transfer.
* | | |1 = AHB bus ERROR response received when channel n transfer.
* @var PDMA_T::TDSTS
* Offset: 0x424 PDMA Channel Transfer Done Flag Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |TDIFn |Transfer Done Flag Register
* | | |This bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
* | | |0 = PDMA channel transfer has not finished.
* | | |1 = PDMA channel has finished transmission.
* @var PDMA_T::ALIGN
* Offset: 0x428 PDMA Transfer Alignment Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |ALIGNn |Transfer Alignment Flag Register
* | | |0 = PDMA channel source address and destination address both follow transfer width setting.
* | | |1 = PDMA channel source address or destination address is not follow transfer width setting.
* @var PDMA_T::TACTSTS
* Offset: 0x42C PDMA Transfer Active Flag Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |TXACTFn |Transfer on Active Flag Register (Read Only)
* | | |This bit indicates which PDMA channel is in active.
* | | |0 = PDMA channel is not finished.
* | | |1 = PDMA channel is active.
* @var PDMA_T::TOUTPSC
* Offset: 0x430 PDMA Time-out Prescaler Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[2:0] |TOUTPSC0 |PDMA Channel 0 Time-out Clock Source Prescaler Bits
* | | |000 = PDMA channel 0 time-out clock source is HCLK/28.
* | | |001 = PDMA channel 0 time-out clock source is HCLK/29.
* | | |010 = PDMA channel 0 time-out clock source is HCLK/210.
* | | |011 = PDMA channel 0 time-out clock source is HCLK/211.
* | | |100 = PDMA channel 0 time-out clock source is HCLK/212.
* | | |101 = PDMA channel 0 time-out clock source is HCLK/213.
* | | |110 = PDMA channel 0 time-out clock source is HCLK/214.
* | | |111 = PDMA channel 0 time-out clock source is HCLK/215.
* |[6:4] |TOUTPSC1 |PDMA Channel 1 Time-out Clock Source Prescaler Bits
* | | |000 = PDMA channel 1 time-out clock source is HCLK/28.
* | | |001 = PDMA channel 1 time-out clock source is HCLK/29.
* | | |010 = PDMA channel 1 time-out clock source is HCLK/210.
* | | |011 = PDMA channel 1 time-out clock source is HCLK/211.
* | | |100 = PDMA channel 1 time-out clock source is HCLK/212.
* | | |101 = PDMA channel 1 time-out clock source is HCLK/213.
* | | |110 = PDMA channel 1 time-out clock source is HCLK/214.
* | | |111 = PDMA channel 1 time-out clock source is HCLK/215.
* @var PDMA_T::TOUTEN
* Offset: 0x434 PDMA Time-out Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1:0] |TOUTENn |PDMA Time-out Enable Bits
* | | |0 = PDMA Channel n time-out function Disable.
* | | |1 = PDMA Channel n time-out function Enable.
* @var PDMA_T::TOUTIEN
* Offset: 0x438 PDMA Time-out Interrupt Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1:0] |TOUTIENn |PDMA Time-out Interrupt Enable Bits
* | | |0 = PDMA Channel n time-out interrupt Disable.
* | | |1 = PDMA Channel n time-out interrupt Enable.
* @var PDMA_T::SCATBA
* Offset: 0x43C PDMA Scatter-Gather Descriptor Table Base Address Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:16] |SCATBA |PDMA Scatter-gather Descriptor Table Address Register
* | | |In Scatter-Gather mode, this is the base address for calculating the next link - list address
* | | |The next link address equation is
* | | |Next Link Address = PDMA_SCATBA + PDMA_DSCT_NEXT.
* | | |Note: Only useful in Scatter-Gather mode.
* @var PDMA_T::TOC0_1
* Offset: 0x440 PDMA Time-out Counter Ch1 and Ch0 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |TOC0 |Time-out Counter for Channel 0
* | | |This controls the period of time-out function for channel 0
* | | |The calculation unit is based on 10 kHz clock.
* |[31:16] |TOC1 |Time-out Counter for Channel 1
* | | |This controls the period of time-out function for channel 1
* | | |The calculation unit is based on 10 kHz clock.
* @var PDMA_T::CHRST
* Offset: 0x460 PDMA Channel Reset Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |CHnRST |Channel N Reset
* | | |0 = corresponding channel n not reset.
* | | |1 = corresponding channel n is reset.
* @var PDMA_T::REQSEL0_3
* Offset: 0x480 PDMA Request Source Select Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[6:0] |REQSRC0 |Channel 0 Request Source Selection
* | | |This filed defines which peripheral is connected to PDMA channel 0
* | | |User can configure the peripheral by setting REQSRC0.
* | | |0 = Disable PDMA peripheral request.
* | | |1 = Reserved.
* | | |2 = Channel connects to USB_TX.
* | | |3 = Channel connects to USB_RX.
* | | |4 = Channel connects to UART0_TX.
* | | |5 = Channel connects to UART0_RX.
* | | |6 = Channel connects to UART1_TX.
* | | |7 = Channel connects to UART1_RX.
* | | |8 = Channel connects to UART2_TX.
* | | |9 = Channel connects to UART2_RX.
* | | |10=Channel connects to UART3_TX.
* | | |11 = Channel connects to UART3_RX.
* | | |12 = Channel connects to UART4_TX.
* | | |13 = Channel connects to UART4_RX.
* | | |14 = Channel connects to UART5_TX.
* | | |15 = Channel connects to UART5_RX.
* | | |16 = Channel connects to USCI0_TX.
* | | |17 = Channel connects to USCI0_RX.
* | | |18 = Channel connects to USCI1_TX.
* | | |19 = Channel connects to USCI1_RX.
* | | |20 = Channel connects to SPI0_TX.
* | | |21 = Channel connects to SPI0_RX.
* | | |22 = Channel connects to SPI1_TX.
* | | |23 = Channel connects to SPI1_RX.
* | | |24 = Channel connects to SPI2_TX.
* | | |25 = Channel connects to SPI2_RX.
* | | |26 = Channel connects to SPI3_TX.
* | | |27 = Channel connects to SPI3_RX.
* | | |28 = Channel connects to SPI4_TX.
* | | |29 = Channel connects to SPI4_RX.
* | | |30 = Reserved.
* | | |31 = Reserved.
* | | |32 = Channel connects to EPWM0_P1_RX.
* | | |33 = Channel connects to EPWM0_P2_RX.
* | | |34 = Channel connects to EPWM0_P3_RX.
* | | |35 = Channel connects to EPWM1_P1_RX.
* | | |36 = Channel connects to EPWM1_P2_RX.
* | | |37 = Channel connects to EPWM1_P3_RX.
* | | |38 = Channel connects to I2C0_TX.
* | | |39 = Channel connects to I2C0_RX.
* | | |40 = Channel connects to I2C1_TX.
* | | |41 = Channel connects to I2C1_RX.
* | | |42 = Channel connects to I2C2_TX.
* | | |43 = Channel connects to I2C2_RX.
* | | |44 = Channel connects to I2S0_TX.
* | | |45 = Channel connects to I2S0_RX.
* | | |46 = Channel connects to TMR0.
* | | |47 = Channel connects to TMR1.
* | | |48 = Channel connects to TMR2.
* | | |49 = Channel connects to TMR3.
* | | |50 = Channel connects to ADC_RX.
* | | |51 = Channel connects to DAC0_TX.
* | | |52 = Channel connects to DAC1_TX.
* | | |53 = Channel connects to EPWM0_CH0_TX.
* | | |54 = Channel connects to EPWM0_CH1_TX.
* | | |55 = Channel connects to EPWM0_CH2_TX.
* | | |56 = Channel connects to EPWM0_CH3_TX.
* | | |57 = Channel connects to EPWM0_CH4_TX.
* | | |58 = Channel connects to EPWM0_CH5_TX.
* | | |59 = Channel connects to EPWM1_CH0_TX.
* | | |60 = Channel connects to EPWM1_CH1_TX.
* | | |61 = Channel connects to EPWM1_CH2_TX.
* | | |62 = Channel connects to EPWM1_CH3_TX.
* | | |63 = Channel connects to EPWM1_CH4_TX.
* | | |64 = Channel connects to EPWM1_CH5_TX.
* | | |65 = Channel connects to ETMC_RX.
* | | |Others = Reserved.
* | | |Note 1: A peripheral can't assign to two channels at the same time.
* | | |Note 2: This field is useless when transfer between memory and memory.
* |[14:8] |REQSRC1 |Channel 1 Request Source Selection
* | | |This filed defines which peripheral is connected to PDMA channel 1
* | | |User can configure the peripheral setting by REQSRC1.
* | | |Note: The channel configuration is the same as REQSRC0 field
* | | |Please refer to the explanation of REQSRC0.
* |[22:16] |REQSRC2 |Channel 2 Request Source Selection
* | | |This filed defines which peripheral is connected to PDMA channel 2
* | | |User can configure the peripheral setting by REQSRC2.
* | | |Note: The channel configuration is the same as REQSRC0 field
* | | |Please refer to the explanation of REQSRC0.
* |[30:24] |REQSRC3 |Channel 3 Request Source Selection
* | | |This filed defines which peripheral is connected to PDMA channel 3
* | | |User can configure the peripheral setting by REQSRC3.
* | | |Note: The channel configuration is the same as REQSRC0 field
* | | |Please refer to the explanation of REQSRC0.
* @var PDMA_T::REQSEL4_7
* Offset: 0x484 PDMA Request Source Select Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[6:0] |REQSRC4 |Channel 4 Request Source Selection
* | | |This filed defines which peripheral is connected to PDMA channel 4
* | | |User can configure the peripheral setting by REQSRC4.
* | | |Note: The channel configuration is the same as REQSRC0 field
* | | |Please refer to the explanation of REQSRC0.
* |[14:8] |REQSRC5 |Channel 5 Request Source Selection
* | | |This filed defines which peripheral is connected to PDMA channel 5
* | | |User can configure the peripheral setting by REQSRC5.
* | | |Note: The channel configuration is the same as REQSRC0 field
* | | |Please refer to the explanation of REQSRC0.
* |[22:16] |REQSRC6 |Channel 6 Request Source Selection
* | | |This filed defines which peripheral is connected to PDMA channel 6
* | | |User can configure the peripheral setting by REQSRC6.
* | | |Note: The channel configuration is the same as REQSRC0 field
* | | |Please refer to the explanation of REQSRC0.
* |[30:24] |REQSRC7 |Channel 7 Request Source Selection
* | | |This filed defines which peripheral is connected to PDMA channel 7
* | | |User can configure the peripheral setting by REQSRC7.
* | | |Note: The channel configuration is the same as REQSRC0 field
* | | |Please refer to the explanation of REQSRC0.
* @var PDMA_T::REQSEL8_11
* Offset: 0x488 PDMA Request Source Select Register 2
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[6:0] |REQSRC8 |Channel 8 Request Source Selection
* | | |This filed defines which peripheral is connected to PDMA channel 8
* | | |User can configure the peripheral setting by REQSRC8.
* | | |Note: The channel configuration is the same as REQSRC0 field
* | | |Please refer to the explanation of REQSRC0.
* |[14:8] |REQSRC9 |Channel 9 Request Source Selection
* | | |This filed defines which peripheral is connected to PDMA channel 9
* | | |User can configure the peripheral setting by REQSRC9.
* | | |Note: The channel configuration is the same as REQSRC0 field
* | | |Please refer to the explanation of REQSRC0.
* |[22:16] |REQSRC10 |Channel 10 Request Source Selection
* | | |This filed defines which peripheral is connected to PDMA channel 10
* | | |User can configure the peripheral setting by REQSRC10.
* | | |Note: The channel configuration is the same as REQSRC0 field
* | | |Please refer to the explanation of REQSRC0.
* |[30:24] |REQSRC11 |Channel 11 Request Source Selection
* | | |This filed defines which peripheral is connected to PDMA channel 11
* | | |User can configure the peripheral setting by REQSRC11.
* | | |Note: The channel configuration is the same as REQSRC0 field
* | | |Please refer to the explanation of REQSRC0.
* @var PDMA_T::REQSEL12_15
* Offset: 0x48C PDMA Request Source Select Register 3
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[6:0] |REQSRC12 |Channel 12 Request Source Selection
* | | |This filed defines which peripheral is connected to PDMA channel 12
* | | |User can configure the peripheral setting by REQSRC12.
* | | |Note: The channel configuration is the same as REQSRC0 field
* | | |Please refer to the explanation of REQSRC0.
* |[14:8] |REQSRC13 |Channel 13 Request Source Selection
* | | |This filed defines which peripheral is connected to PDMA channel 13
* | | |User can configure the peripheral setting by REQSRC13.
* | | |Note: The channel configuration is the same as REQSRC0 field
* | | |Please refer to the explanation of REQSRC0.
* |[22:16] |REQSRC14 |Channel 14 Request Source Selection
* | | |This filed defines which peripheral is connected to PDMA channel 14
* | | |User can configure the peripheral setting by REQSRC14.
* | | |Note: The channel configuration is the same as REQSRC0 field
* | | |Please refer to the explanation of REQSRC0.
* |[30:24] |REQSRC15 |Channel 15 Request Source Selection
* | | |This filed defines which peripheral is connected to PDMA channel 15
* | | |User can configure the peripheral setting by REQSRC15.
* | | |Note: The channel configuration is the same as REQSRC0 field
* | | |Please refer to the explanation of REQSRC0.
*/
DSCT_T DSCT[16];
__I uint32_t CURSCAT[16]; /*!< [0x0100] Current Scatter-Gather Descriptor Table Address of PDMA Channel n */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE1[176];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t CHCTL; /*!< [0x0400] PDMA Channel Control Register */
__O uint32_t PAUSE; /*!< [0x0404] PDMA Transfer Pause Control Register */
__O uint32_t SWREQ; /*!< [0x0408] PDMA Software Request Register */
__I uint32_t TRGSTS; /*!< [0x040c] PDMA Channel Request Status Register */
__IO uint32_t PRISET; /*!< [0x0410] PDMA Fixed Priority Setting Register */
__O uint32_t PRICLR; /*!< [0x0414] PDMA Fixed Priority Clear Register */
__IO uint32_t INTEN; /*!< [0x0418] PDMA Interrupt Enable Register */
__IO uint32_t INTSTS; /*!< [0x041c] PDMA Interrupt Status Register */
__IO uint32_t ABTSTS; /*!< [0x0420] PDMA Channel Read/Write Target Abort Flag Register */
__IO uint32_t TDSTS; /*!< [0x0424] PDMA Channel Transfer Done Flag Register */
__IO uint32_t ALIGN; /*!< [0x0428] PDMA Transfer Alignment Status Register */
__I uint32_t TACTSTS; /*!< [0x042c] PDMA Transfer Active Flag Register */
__IO uint32_t TOUTPSC; /*!< [0x0430] PDMA Time-out Prescaler Register */
__IO uint32_t TOUTEN; /*!< [0x0434] PDMA Time-out Enable Register */
__IO uint32_t TOUTIEN; /*!< [0x0438] PDMA Time-out Interrupt Enable Register */
__IO uint32_t SCATBA; /*!< [0x043c] PDMA Scatter-Gather Descriptor Table Base Address Register */
__IO uint32_t TOC0_1; /*!< [0x0440] PDMA Time-out Counter Ch1 and Ch0 Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE2[7];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t CHRST; /*!< [0x0460] PDMA Channel Reset Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE3[7];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t REQSEL0_3; /*!< [0x0480] PDMA Request Source Select Register 0 */
__IO uint32_t REQSEL4_7; /*!< [0x0484] PDMA Request Source Select Register 1 */
__IO uint32_t REQSEL8_11; /*!< [0x0488] PDMA Request Source Select Register 2 */
__IO uint32_t REQSEL12_15; /*!< [0x048c] PDMA Request Source Select Register 3 */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE4[28];
/// @endcond //HIDDEN_SYMBOLS
STRIDE_T STRIDE[6];
} PDMA_T;
/**
@addtogroup PDMA_CONST PDMA Bit Field Definition
Constant Definitions for PDMA Controller
@{ */
#define PDMA_DSCT_CTL_OPMODE_Pos (0) /*!< PDMA_T::DSCT_CTL: OPMODE Position */
#define PDMA_DSCT_CTL_OPMODE_Msk (0x3ul << PDMA_DSCT_CTL_OPMODE_Pos) /*!< PDMA_T::DSCT_CTL: OPMODE Mask */
#define PDMA_DSCT_CTL_TXTYPE_Pos (2) /*!< PDMA_T::DSCT_CTL: TXTYPE Position */
#define PDMA_DSCT_CTL_TXTYPE_Msk (0x1ul << PDMA_DSCT_CTL_TXTYPE_Pos) /*!< PDMA_T::DSCT_CTL: TXTYPE Mask */
#define PDMA_DSCT_CTL_BURSIZE_Pos (4) /*!< PDMA_T::DSCT_CTL: BURSIZE Position */
#define PDMA_DSCT_CTL_BURSIZE_Msk (0x7ul << PDMA_DSCT_CTL_BURSIZE_Pos) /*!< PDMA_T::DSCT_CTL: BURSIZE Mask */
#define PDMA_DSCT_CTL_TBINTDIS_Pos (7) /*!< PDMA_T::DSCT_CTL: TBINTDIS Position */
#define PDMA_DSCT_CTL_TBINTDIS_Msk (0x1ul << PDMA_DSCT_CTL_TBINTDIS_Pos) /*!< PDMA_T::DSCT_CTL: TBINTDIS Mask */
#define PDMA_DSCT_CTL_SAINC_Pos (8) /*!< PDMA_T::DSCT_CTL: SAINC Position */
#define PDMA_DSCT_CTL_SAINC_Msk (0x3ul << PDMA_DSCT_CTL_SAINC_Pos) /*!< PDMA_T::DSCT_CTL: SAINC Mask */
#define PDMA_DSCT_CTL_DAINC_Pos (10) /*!< PDMA_T::DSCT_CTL: DAINC Position */
#define PDMA_DSCT_CTL_DAINC_Msk (0x3ul << PDMA_DSCT_CTL_DAINC_Pos) /*!< PDMA_T::DSCT_CTL: DAINC Mask */
#define PDMA_DSCT_CTL_TXWIDTH_Pos (12) /*!< PDMA_T::DSCT_CTL: TXWIDTH Position */
#define PDMA_DSCT_CTL_TXWIDTH_Msk (0x3ul << PDMA_DSCT_CTL_TXWIDTH_Pos) /*!< PDMA_T::DSCT_CTL: TXWIDTH Mask */
#define PDMA_DSCT_CTL_TXACK_Pos (14) /*!< PDMA_T::DSCT_CTL: TXACK Position */
#define PDMA_DSCT_CTL_TXACK_Msk (0x1ul << PDMA_DSCT_CTL_TXACK_Pos) /*!< PDMA_T::DSCT_CTL: TXACK Mask */
#define PDMA_DSCT_CTL_STRIDEEN_Pos (15) /*!< PDMA_T::DSCT_CTL: STRIDEEN Position */
#define PDMA_DSCT_CTL_STRIDEEN_Msk (0x1ul << PDMA_DSCT_CTL_STRIDEEN_Pos) /*!< PDMA_T::DSCT_CTL: STRIDEEN Mask */
#define PDMA_DSCT_CTL_TXCNT_Pos (16) /*!< PDMA_T::DSCT_CTL: TXCNT Position */
#define PDMA_DSCT_CTL_TXCNT_Msk (0xfffful << PDMA_DSCT_CTL_TXCNT_Pos) /*!< PDMA_T::DSCT_CTL: TXCNT Mask */
#define PDMA_DSCT_SA_SA_Pos (0) /*!< PDMA_T::DSCT_SA: SA Position */
#define PDMA_DSCT_SA_SA_Msk (0xfffffffful << PDMA_DSCT_SA_SA_Pos) /*!< PDMA_T::DSCT_SA: SA Mask */
#define PDMA_DSCT_DA_DA_Pos (0) /*!< PDMA_T::DSCT_DA: DA Position */
#define PDMA_DSCT_DA_DA_Msk (0xfffffffful << PDMA_DSCT_DA_DA_Pos) /*!< PDMA_T::DSCT_DA: DA Mask */
#define PDMA_DSCT_NEXT_NEXT_Pos (0) /*!< PDMA_T::DSCT_NEXT: NEXT Position */
#define PDMA_DSCT_NEXT_NEXT_Msk (0xfffful << PDMA_DSCT_NEXT_NEXT_Pos) /*!< PDMA_T::DSCT_NEXT: NEXT Mask */
#define PDMA_DSCT_NEXT_EXENEXT_Pos (16) /*!< PDMA_T::DSCT_FIRST: NEXT Position */
#define PDMA_DSCT_NEXT_EXENEXT_Msk (0xfffful << PDMA_DSCT_NEXT_EXENEXT_Pos) /*!< PDMA_T::DSCT_FIRST: NEXT Mask */
#define PDMA_CURSCAT_CURADDR_Pos (0) /*!< PDMA_T::CURSCAT: CURADDR Position */
#define PDMA_CURSCAT_CURADDR_Msk (0xfffffffful << PDMA_CURSCAT_CURADDR_Pos) /*!< PDMA_T::CURSCAT: CURADDR Mask */
#define PDMA_CHCTL_CHENn_Pos (0) /*!< PDMA_T::CHCTL: CHENn Position */
#define PDMA_CHCTL_CHENn_Msk (0xfffful << PDMA_CHCTL_CHENn_Pos) /*!< PDMA_T::CHCTL: CHENn Mask */
#define PDMA_PAUSE_PAUSEn_Pos (0) /*!< PDMA_T::PAUSE: PAUSEn Position */
#define PDMA_PAUSE_PAUSEn_Msk (0xfffful << PDMA_PAUSE_PAUSEn_Pos) /*!< PDMA_T::PAUSE: PAUSEn Mask */
#define PDMA_SWREQ_SWREQn_Pos (0) /*!< PDMA_T::SWREQ: SWREQn Position */
#define PDMA_SWREQ_SWREQn_Msk (0xfffful << PDMA_SWREQ_SWREQn_Pos) /*!< PDMA_T::SWREQ: SWREQn Mask */
#define PDMA_TRGSTS_REQSTSn_Pos (0) /*!< PDMA_T::TRGSTS: REQSTSn Position */
#define PDMA_TRGSTS_REQSTSn_Msk (0xfffful << PDMA_TRGSTS_REQSTSn_Pos) /*!< PDMA_T::TRGSTS: REQSTSn Mask */
#define PDMA_PRISET_FPRISETn_Pos (0) /*!< PDMA_T::PRISET: FPRISETn Position */
#define PDMA_PRISET_FPRISETn_Msk (0xfffful << PDMA_PRISET_FPRISETn_Pos) /*!< PDMA_T::PRISET: FPRISETn Mask */
#define PDMA_PRICLR_FPRICLRn_Pos (0) /*!< PDMA_T::PRICLR: FPRICLRn Position */
#define PDMA_PRICLR_FPRICLRn_Msk (0xfffful << PDMA_PRICLR_FPRICLRn_Pos) /*!< PDMA_T::PRICLR: FPRICLRn Mask */
#define PDMA_INTEN_INTENn_Pos (0) /*!< PDMA_T::INTEN: INTENn Position */
#define PDMA_INTEN_INTENn_Msk (0xfffful << PDMA_INTEN_INTENn_Pos) /*!< PDMA_T::INTEN: INTENn Mask */
#define PDMA_INTSTS_ABTIF_Pos (0) /*!< PDMA_T::INTSTS: ABTIF Position */
#define PDMA_INTSTS_ABTIF_Msk (0x1ul << PDMA_INTSTS_ABTIF_Pos) /*!< PDMA_T::INTSTS: ABTIF Mask */
#define PDMA_INTSTS_TDIF_Pos (1) /*!< PDMA_T::INTSTS: TDIF Position */
#define PDMA_INTSTS_TDIF_Msk (0x1ul << PDMA_INTSTS_TDIF_Pos) /*!< PDMA_T::INTSTS: TDIF Mask */
#define PDMA_INTSTS_ALIGNF_Pos (2) /*!< PDMA_T::INTSTS: ALIGNF Position */
#define PDMA_INTSTS_ALIGNF_Msk (0x1ul << PDMA_INTSTS_ALIGNF_Pos) /*!< PDMA_T::INTSTS: ALIGNF Mask */
#define PDMA_INTSTS_REQTOF0_Pos (8) /*!< PDMA_T::INTSTS: REQTOF0 Position */
#define PDMA_INTSTS_REQTOF0_Msk (0x1ul << PDMA_INTSTS_REQTOF0_Pos) /*!< PDMA_T::INTSTS: REQTOF0 Mask */
#define PDMA_INTSTS_REQTOF1_Pos (9) /*!< PDMA_T::INTSTS: REQTOF1 Position */
#define PDMA_INTSTS_REQTOF1_Msk (0x1ul << PDMA_INTSTS_REQTOF1_Pos) /*!< PDMA_T::INTSTS: REQTOF1 Mask */
#define PDMA_ABTSTS_ABTIF0_Pos (0) /*!< PDMA_T::ABTSTS: ABTIF0 Position */
#define PDMA_ABTSTS_ABTIF0_Msk (0x1ul << PDMA_ABTSTS_ABTIF0_Pos) /*!< PDMA_T::ABTSTS: ABTIF0 Mask */
#define PDMA_ABTSTS_ABTIF1_Pos (1) /*!< PDMA_T::ABTSTS: ABTIF1 Position */
#define PDMA_ABTSTS_ABTIF1_Msk (0x1ul << PDMA_ABTSTS_ABTIF1_Pos) /*!< PDMA_T::ABTSTS: ABTIF1 Mask */
#define PDMA_ABTSTS_ABTIF2_Pos (2) /*!< PDMA_T::ABTSTS: ABTIF2 Position */
#define PDMA_ABTSTS_ABTIF2_Msk (0x1ul << PDMA_ABTSTS_ABTIF2_Pos) /*!< PDMA_T::ABTSTS: ABTIF2 Mask */
#define PDMA_ABTSTS_ABTIF3_Pos (3) /*!< PDMA_T::ABTSTS: ABTIF3 Position */
#define PDMA_ABTSTS_ABTIF3_Msk (0x1ul << PDMA_ABTSTS_ABTIF3_Pos) /*!< PDMA_T::ABTSTS: ABTIF3 Mask */
#define PDMA_ABTSTS_ABTIF4_Pos (4) /*!< PDMA_T::ABTSTS: ABTIF4 Position */
#define PDMA_ABTSTS_ABTIF4_Msk (0x1ul << PDMA_ABTSTS_ABTIF4_Pos) /*!< PDMA_T::ABTSTS: ABTIF4 Mask */
#define PDMA_ABTSTS_ABTIF5_Pos (5) /*!< PDMA_T::ABTSTS: ABTIF5 Position */
#define PDMA_ABTSTS_ABTIF5_Msk (0x1ul << PDMA_ABTSTS_ABTIF5_Pos) /*!< PDMA_T::ABTSTS: ABTIF5 Mask */
#define PDMA_ABTSTS_ABTIF6_Pos (6) /*!< PDMA_T::ABTSTS: ABTIF6 Position */
#define PDMA_ABTSTS_ABTIF6_Msk (0x1ul << PDMA_ABTSTS_ABTIF6_Pos) /*!< PDMA_T::ABTSTS: ABTIF6 Mask */
#define PDMA_ABTSTS_ABTIF7_Pos (7) /*!< PDMA_T::ABTSTS: ABTIF7 Position */
#define PDMA_ABTSTS_ABTIF7_Msk (0x1ul << PDMA_ABTSTS_ABTIF7_Pos) /*!< PDMA_T::ABTSTS: ABTIF7 Mask */
#define PDMA_ABTSTS_ABTIF8_Pos (8) /*!< PDMA_T::ABTSTS: ABTIF8 Position */
#define PDMA_ABTSTS_ABTIF8_Msk (0x1ul << PDMA_ABTSTS_ABTIF8_Pos) /*!< PDMA_T::ABTSTS: ABTIF8 Mask */
#define PDMA_ABTSTS_ABTIF9_Pos (9) /*!< PDMA_T::ABTSTS: ABTIF9 Position */
#define PDMA_ABTSTS_ABTIF9_Msk (0x1ul << PDMA_ABTSTS_ABTIF9_Pos) /*!< PDMA_T::ABTSTS: ABTIF9 Mask */
#define PDMA_ABTSTS_ABTIF10_Pos (10) /*!< PDMA_T::ABTSTS: ABTIF10 Position */
#define PDMA_ABTSTS_ABTIF10_Msk (0x1ul << PDMA_ABTSTS_ABTIF10_Pos) /*!< PDMA_T::ABTSTS: ABTIF10 Mask */
#define PDMA_ABTSTS_ABTIF11_Pos (11) /*!< PDMA_T::ABTSTS: ABTIF11 Position */
#define PDMA_ABTSTS_ABTIF11_Msk (0x1ul << PDMA_ABTSTS_ABTIF11_Pos) /*!< PDMA_T::ABTSTS: ABTIF11 Mask */
#define PDMA_ABTSTS_ABTIF12_Pos (12) /*!< PDMA_T::ABTSTS: ABTIF12 Position */
#define PDMA_ABTSTS_ABTIF12_Msk (0x1ul << PDMA_ABTSTS_ABTIF12_Pos) /*!< PDMA_T::ABTSTS: ABTIF12 Mask */
#define PDMA_ABTSTS_ABTIF13_Pos (13) /*!< PDMA_T::ABTSTS: ABTIF13 Position */
#define PDMA_ABTSTS_ABTIF13_Msk (0x1ul << PDMA_ABTSTS_ABTIF13_Pos) /*!< PDMA_T::ABTSTS: ABTIF13 Mask */
#define PDMA_ABTSTS_ABTIF14_Pos (14) /*!< PDMA_T::ABTSTS: ABTIF14 Position */
#define PDMA_ABTSTS_ABTIF14_Msk (0x1ul << PDMA_ABTSTS_ABTIF14_Pos) /*!< PDMA_T::ABTSTS: ABTIF14 Mask */
#define PDMA_ABTSTS_ABTIF15_Pos (15) /*!< PDMA_T::ABTSTS: ABTIF15 Position */
#define PDMA_ABTSTS_ABTIF15_Msk (0x1ul << PDMA_ABTSTS_ABTIF15_Pos) /*!< PDMA_T::ABTSTS: ABTIF15 Mask */
#define PDMA_TDSTS_TDIF0_Pos (0) /*!< PDMA_T::TDSTS: TDIF0 Position */
#define PDMA_TDSTS_TDIF0_Msk (0x1ul << PDMA_TDSTS_TDIF0_Pos) /*!< PDMA_T::TDSTS: TDIF0 Mask */
#define PDMA_TDSTS_TDIF1_Pos (1) /*!< PDMA_T::TDSTS: TDIF1 Position */
#define PDMA_TDSTS_TDIF1_Msk (0x1ul << PDMA_TDSTS_TDIF1_Pos) /*!< PDMA_T::TDSTS: TDIF1 Mask */
#define PDMA_TDSTS_TDIF2_Pos (2) /*!< PDMA_T::TDSTS: TDIF2 Position */
#define PDMA_TDSTS_TDIF2_Msk (0x1ul << PDMA_TDSTS_TDIF2_Pos) /*!< PDMA_T::TDSTS: TDIF2 Mask */
#define PDMA_TDSTS_TDIF3_Pos (3) /*!< PDMA_T::TDSTS: TDIF3 Position */
#define PDMA_TDSTS_TDIF3_Msk (0x1ul << PDMA_TDSTS_TDIF3_Pos) /*!< PDMA_T::TDSTS: TDIF3 Mask */
#define PDMA_TDSTS_TDIF4_Pos (4) /*!< PDMA_T::TDSTS: TDIF4 Position */
#define PDMA_TDSTS_TDIF4_Msk (0x1ul << PDMA_TDSTS_TDIF4_Pos) /*!< PDMA_T::TDSTS: TDIF4 Mask */
#define PDMA_TDSTS_TDIF5_Pos (5) /*!< PDMA_T::TDSTS: TDIF5 Position */
#define PDMA_TDSTS_TDIF5_Msk (0x1ul << PDMA_TDSTS_TDIF5_Pos) /*!< PDMA_T::TDSTS: TDIF5 Mask */
#define PDMA_TDSTS_TDIF6_Pos (6) /*!< PDMA_T::TDSTS: TDIF6 Position */
#define PDMA_TDSTS_TDIF6_Msk (0x1ul << PDMA_TDSTS_TDIF6_Pos) /*!< PDMA_T::TDSTS: TDIF6 Mask */
#define PDMA_TDSTS_TDIF7_Pos (7) /*!< PDMA_T::TDSTS: TDIF7 Position */
#define PDMA_TDSTS_TDIF7_Msk (0x1ul << PDMA_TDSTS_TDIF7_Pos) /*!< PDMA_T::TDSTS: TDIF7 Mask */
#define PDMA_TDSTS_TDIF8_Pos (8) /*!< PDMA_T::TDSTS: TDIF8 Position */
#define PDMA_TDSTS_TDIF8_Msk (0x1ul << PDMA_TDSTS_TDIF8_Pos) /*!< PDMA_T::TDSTS: TDIF8 Mask */
#define PDMA_TDSTS_TDIF9_Pos (9) /*!< PDMA_T::TDSTS: TDIF9 Position */
#define PDMA_TDSTS_TDIF9_Msk (0x1ul << PDMA_TDSTS_TDIF9_Pos) /*!< PDMA_T::TDSTS: TDIF9 Mask */
#define PDMA_TDSTS_TDIF10_Pos (10) /*!< PDMA_T::TDSTS: TDIF10 Position */
#define PDMA_TDSTS_TDIF10_Msk (0x1ul << PDMA_TDSTS_TDIF10_Pos) /*!< PDMA_T::TDSTS: TDIF10 Mask */
#define PDMA_TDSTS_TDIF11_Pos (11) /*!< PDMA_T::TDSTS: TDIF11 Position */
#define PDMA_TDSTS_TDIF11_Msk (0x1ul << PDMA_TDSTS_TDIF11_Pos) /*!< PDMA_T::TDSTS: TDIF11 Mask */
#define PDMA_TDSTS_TDIF12_Pos (12) /*!< PDMA_T::TDSTS: TDIF12 Position */
#define PDMA_TDSTS_TDIF12_Msk (0x1ul << PDMA_TDSTS_TDIF12_Pos) /*!< PDMA_T::TDSTS: TDIF12 Mask */
#define PDMA_TDSTS_TDIF13_Pos (13) /*!< PDMA_T::TDSTS: TDIF13 Position */
#define PDMA_TDSTS_TDIF13_Msk (0x1ul << PDMA_TDSTS_TDIF13_Pos) /*!< PDMA_T::TDSTS: TDIF13 Mask */
#define PDMA_TDSTS_TDIF14_Pos (14) /*!< PDMA_T::TDSTS: TDIF14 Position */
#define PDMA_TDSTS_TDIF14_Msk (0x1ul << PDMA_TDSTS_TDIF14_Pos) /*!< PDMA_T::TDSTS: TDIF14 Mask */
#define PDMA_TDSTS_TDIF15_Pos (15) /*!< PDMA_T::TDSTS: TDIF15 Position */
#define PDMA_TDSTS_TDIF15_Msk (0x1ul << PDMA_TDSTS_TDIF15_Pos) /*!< PDMA_T::TDSTS: TDIF15 Mask */
#define PDMA_ALIGN_ALIGNn_Pos (0) /*!< PDMA_T::ALIGN: ALIGNn Position */
#define PDMA_ALIGN_ALIGNn_Msk (0xfffful << PDMA_ALIGN_ALIGNn_Pos) /*!< PDMA_T::ALIGN: ALIGNn Mask */
#define PDMA_TACTSTS_TXACTFn_Pos (0) /*!< PDMA_T::TACTSTS: TXACTFn Position */
#define PDMA_TACTSTS_TXACTFn_Msk (0xfffful << PDMA_TACTSTS_TXACTFn_Pos) /*!< PDMA_T::TACTSTS: TXACTFn Mask */
#define PDMA_TOUTPSC_TOUTPSC0_Pos (0) /*!< PDMA_T::TOUTPSC: TOUTPSC0 Position */
#define PDMA_TOUTPSC_TOUTPSC0_Msk (0x7ul << PDMA_TOUTPSC_TOUTPSC0_Pos) /*!< PDMA_T::TOUTPSC: TOUTPSC0 Mask */
#define PDMA_TOUTPSC_TOUTPSC1_Pos (4) /*!< PDMA_T::TOUTPSC: TOUTPSC1 Position */
#define PDMA_TOUTPSC_TOUTPSC1_Msk (0x7ul << PDMA_TOUTPSC_TOUTPSC1_Pos) /*!< PDMA_T::TOUTPSC: TOUTPSC1 Mask */
#define PDMA_TOUTEN_TOUTENn_Pos (0) /*!< PDMA_T::TOUTEN: TOUTENn Position */
#define PDMA_TOUTEN_TOUTENn_Msk (0x3ul << PDMA_TOUTEN_TOUTENn_Pos) /*!< PDMA_T::TOUTEN: TOUTENn Mask */
#define PDMA_TOUTIEN_TOUTIENn_Pos (0) /*!< PDMA_T::TOUTIEN: TOUTIENn Position */
#define PDMA_TOUTIEN_TOUTIENn_Msk (0x3ul << PDMA_TOUTIEN_TOUTIENn_Pos) /*!< PDMA_T::TOUTIEN: TOUTIENn Mask */
#define PDMA_SCATBA_SCATBA_Pos (16) /*!< PDMA_T::SCATBA: SCATBA Position */
#define PDMA_SCATBA_SCATBA_Msk (0xfffful << PDMA_SCATBA_SCATBA_Pos) /*!< PDMA_T::SCATBA: SCATBA Mask */
#define PDMA_TOC0_1_TOC0_Pos (0) /*!< PDMA_T::TOC0_1: TOC0 Position */
#define PDMA_TOC0_1_TOC0_Msk (0xfffful << PDMA_TOC0_1_TOC0_Pos) /*!< PDMA_T::TOC0_1: TOC0 Mask */
#define PDMA_TOC0_1_TOC1_Pos (16) /*!< PDMA_T::TOC0_1: TOC1 Position */
#define PDMA_TOC0_1_TOC1_Msk (0xfffful << PDMA_TOC0_1_TOC1_Pos) /*!< PDMA_T::TOC0_1: TOC1 Mask */
#define PDMA_CHRST_CHnRST_Pos (0) /*!< PDMA_T::CHRST: CHnRST Position */
#define PDMA_CHRST_CHnRST_Msk (0xfffful << PDMA_CHRST_CHnRST_Pos) /*!< PDMA_T::CHRST: CHnRST Mask */
#define PDMA_REQSEL0_3_REQSRC0_Pos (0) /*!< PDMA_T::REQSEL0_3: REQSRC0 Position */
#define PDMA_REQSEL0_3_REQSRC0_Msk (0x7ful << PDMA_REQSEL0_3_REQSRC0_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC0 Mask */
#define PDMA_REQSEL0_3_REQSRC1_Pos (8) /*!< PDMA_T::REQSEL0_3: REQSRC1 Position */
#define PDMA_REQSEL0_3_REQSRC1_Msk (0x7ful << PDMA_REQSEL0_3_REQSRC1_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC1 Mask */
#define PDMA_REQSEL0_3_REQSRC2_Pos (16) /*!< PDMA_T::REQSEL0_3: REQSRC2 Position */
#define PDMA_REQSEL0_3_REQSRC2_Msk (0x7ful << PDMA_REQSEL0_3_REQSRC2_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC2 Mask */
#define PDMA_REQSEL0_3_REQSRC3_Pos (24) /*!< PDMA_T::REQSEL0_3: REQSRC3 Position */
#define PDMA_REQSEL0_3_REQSRC3_Msk (0x7ful << PDMA_REQSEL0_3_REQSRC3_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC3 Mask */
#define PDMA_REQSEL4_7_REQSRC4_Pos (0) /*!< PDMA_T::REQSEL4_7: REQSRC4 Position */
#define PDMA_REQSEL4_7_REQSRC4_Msk (0x7ful << PDMA_REQSEL4_7_REQSRC4_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC4 Mask */
#define PDMA_REQSEL4_7_REQSRC5_Pos (8) /*!< PDMA_T::REQSEL4_7: REQSRC5 Position */
#define PDMA_REQSEL4_7_REQSRC5_Msk (0x7ful << PDMA_REQSEL4_7_REQSRC5_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC5 Mask */
#define PDMA_REQSEL4_7_REQSRC6_Pos (16) /*!< PDMA_T::REQSEL4_7: REQSRC6 Position */
#define PDMA_REQSEL4_7_REQSRC6_Msk (0x7ful << PDMA_REQSEL4_7_REQSRC6_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC6 Mask */
#define PDMA_REQSEL4_7_REQSRC7_Pos (24) /*!< PDMA_T::REQSEL4_7: REQSRC7 Position */
#define PDMA_REQSEL4_7_REQSRC7_Msk (0x7ful << PDMA_REQSEL4_7_REQSRC7_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC7 Mask */
#define PDMA_REQSEL8_11_REQSRC8_Pos (0) /*!< PDMA_T::REQSEL8_11: REQSRC8 Position */
#define PDMA_REQSEL8_11_REQSRC8_Msk (0x7ful << PDMA_REQSEL8_11_REQSRC8_Pos) /*!< PDMA_T::REQSEL8_11: REQSRC8 Mask */
#define PDMA_REQSEL8_11_REQSRC9_Pos (8) /*!< PDMA_T::REQSEL8_11: REQSRC9 Position */
#define PDMA_REQSEL8_11_REQSRC9_Msk (0x7ful << PDMA_REQSEL8_11_REQSRC9_Pos) /*!< PDMA_T::REQSEL8_11: REQSRC9 Mask */
#define PDMA_REQSEL8_11_REQSRC10_Pos (16) /*!< PDMA_T::REQSEL8_11: REQSRC10 Position */
#define PDMA_REQSEL8_11_REQSRC10_Msk (0x7ful << PDMA_REQSEL8_11_REQSRC10_Pos) /*!< PDMA_T::REQSEL8_11: REQSRC10 Mask */
#define PDMA_REQSEL8_11_REQSRC11_Pos (24) /*!< PDMA_T::REQSEL8_11: REQSRC11 Position */
#define PDMA_REQSEL8_11_REQSRC11_Msk (0x7ful << PDMA_REQSEL8_11_REQSRC11_Pos) /*!< PDMA_T::REQSEL8_11: REQSRC11 Mask */
#define PDMA_REQSEL12_15_REQSRC12_Pos (0) /*!< PDMA_T::REQSEL12_15: REQSRC12 Position */
#define PDMA_REQSEL12_15_REQSRC12_Msk (0x7ful << PDMA_REQSEL12_15_REQSRC12_Pos) /*!< PDMA_T::REQSEL12_15: REQSRC12 Mask */
#define PDMA_REQSEL12_15_REQSRC13_Pos (8) /*!< PDMA_T::REQSEL12_15: REQSRC13 Position */
#define PDMA_REQSEL12_15_REQSRC13_Msk (0x7ful << PDMA_REQSEL12_15_REQSRC13_Pos) /*!< PDMA_T::REQSEL12_15: REQSRC13 Mask */
#define PDMA_REQSEL12_15_REQSRC14_Pos (16) /*!< PDMA_T::REQSEL12_15: REQSRC14 Position */
#define PDMA_REQSEL12_15_REQSRC14_Msk (0x7ful << PDMA_REQSEL12_15_REQSRC14_Pos) /*!< PDMA_T::REQSEL12_15: REQSRC14 Mask */
#define PDMA_REQSEL12_15_REQSRC15_Pos (24) /*!< PDMA_T::REQSEL12_15: REQSRC15 Position */
#define PDMA_REQSEL12_15_REQSRC15_Msk (0x7ful << PDMA_REQSEL12_15_REQSRC15_Pos) /*!< PDMA_T::REQSEL12_15: REQSRC15 Mask */
#define PDMA_STCRn_STC_Pos (0) /*!< PDMA_T::STCRn: STC Position */
#define PDMA_STCRn_STC_Msk (0xfffful << PDMA_STCRn_STC_Pos) /*!< PDMA_T::STCRn: STC Mask */
#define PDMA_ASOCRn_SASOL_Pos (0) /*!< PDMA_T::ASOCRn: SASOL Position */
#define PDMA_ASOCRn_SASOL_Msk (0xfffful << PDMA_ASOCRn_SASOL_Pos) /*!< PDMA_T::ASOCRn: SASOL Mask */
#define PDMA_ASOCRn_DASOL_Pos (16) /*!< PDMA_T::ASOCRn: DASOL Position */
#define PDMA_ASOCRn_DASOL_Msk (0xfffful << PDMA_ASOCRn_DASOL_Pos) /*!< PDMA_T::ASOCRn: DASOL Mask */
/**@}*/ /* PDMA_CONST */
/**@}*/ /* end of PDMA register group */
/*---------------------- Timer Controller -------------------------*/
/**
@addtogroup TIMER Timer Controller(TIMER)
Memory Mapped Structure for TIMER Controller
@{ */
typedef struct {
/**
* @var TIMER_T::CTL
* Offset: 0x00 Timer Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |PSC |Prescale Counter
* | | |Timer input clock or event source is divided by (PSC+1) before it is fed to the timer up counter
* | | |If this field is 0 (PSC = 0), then there is no scaling.
* | | |Note: Update prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value.
* |[19] |INTRGEN |Inter-timer Trigger Mode Enable Control
* | | |Setting this bit will enable the inter-timer trigger capture function.
* | | |The Timer0/2 will be in event counter mode and counting with external clock source or event
* | | |Also, Timer1/3 will be in trigger-counting mode of capture function.
* | | |0 = Inter-Timer Trigger Capture mode Disabled.
* | | |1 = Inter-Timer Trigger Capture mode Enabled.
* | | |Note: For Timer1/3, this bit is ignored and the read back value is always 0.
* |[20] |PERIOSEL |Periodic Mode Behavior Selection Enable Bit
* | | |0 = The behavior selection in periodic mode is Disabled.
* | | |When user updates CMPDAT while timer is running in periodic mode,
* | | |CNT will be reset to default value.
* | | |1 = The behavior selection in periodic mode is Enabled.
* | | |When user update CMPDAT while timer is running in periodic mode, the limitations as bellows list,
* | | |If updated CMPDAT value > CNT, CMPDAT will be updated and CNT keep running continually.
* | | |If updated CMPDAT value = CNT, timer time-out interrupt will be asserted immediately.
* | | |If updated CMPDAT value < CNT, CNT will be reset to default value.
* |[21] |TGLPINSEL |Toggle-output Pin Select
* | | |0 = Toggle mode output to TMx (Timer Event Counter Pin).
* | | |1 = Toggle mode output to TMx_EXT (Timer External Capture Pin).
* |[22] |CAPSRC |Capture Pin Source Selection
* | | |0 = Capture Function source is from TMx_EXT (x= 0~3) pin.
* | | |1 = Capture Function source is from internal ACMP output signal
* | | |User can set ACMPSSEL (TIMERx_EXTCTL[8]) to decide which internal ACMP output signal as timer capture source.
* |[23] |WKEN |Wake-up Function Enable Bit
* | | |If this bit is set to 1, while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled, the timer interrupt signal will generate a wake-up trigger event to CPU.
* | | |0 = Wake-up function Disabled if timer interrupt signal generated.
* | | |1 = Wake-up function Enabled if timer interrupt signal generated.
* |[24] |EXTCNTEN |Event Counter Mode Enable Bit
* | | |This bit is for external counting pin function enabled.
* | | |0 = Event counter mode Disabled.
* | | |1 = Event counter mode Enabled.
* | | |Note: When timer is used as an event counter, this bit should be set to 1 and select PCLK as timer clock source.
* |[25] |ACTSTS |Timer Active Status Bit (Read Only)
* | | |This bit indicates the 24-bit up counter status.
* | | |0 = 24-bit up counter is not active.
* | | |1 = 24-bit up counter is active.
* | | |Note: This bit may active when CNT 0 transition to CNT 1.
* |[28:27] |OPMODE |Timer Counting Mode Select
* | | |00 = The Timer controller is operated in One-shot mode.
* | | |01 = The Timer controller is operated in Periodic mode.
* | | |10 = The Timer controller is operated in Toggle-output mode.
* | | |11 = The Timer controller is operated in Continuous Counting mode.
* |[29] |INTEN |Timer Interrupt Enable Bit
* | | |0 = Timer time-out interrupt Disabled.
* | | |1 = Timer time-out interrupt Enabled.
* | | |Note: If this bit is enabled, when the timer time-out interrupt flag TIF is set to 1, the timer interrupt signal is generated and inform to CPU.
* |[30] |CNTEN |Timer Counting Enable Bit
* | | |0 = Stops/Suspends counting.
* | | |1 = Starts counting.
* | | |Note1: In stop status, and then set CNTEN to 1 will enable the 24-bit up counter to keep counting from the last stop counting value.
* | | |Note2: This bit is auto-cleared by hardware in one-shot mode (TIMER_CTL[28:27] = 00) when the timer time-out interrupt flag TIF (TIMERx_INTSTS[0]) is generated.
* | | |Note3: Set enable/disable this bit needs 2 * TMR_CLK period to become active, user can read ACTSTS (TIMERx_CTL[25]) to check enable/disable command is completed or not.
* |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Control (Write Protect)
* | | |0 = ICE debug mode acknowledgement effects TIMER counting.
* | | |TIMER counter will be held while CPU is held by ICE.
* | | |1 = ICE debug mode acknowledgement Disabled.
* | | |TIMER counter will keep going no matter CPU is held by ICE or not.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* @var TIMER_T::CMP
* Offset: 0x04 Timer Comparator Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[23:0] |CMPDAT |Timer Comparator Value
* | | |CMPDAT is a 24-bit compared value register
* | | |When the internal 24-bit up counter value is equal to CMPDAT value, the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will set to 1.
* | | |Time-out period = (Period of timer clock input) * (8-bit PSC + 1) * (24-bit CMPDAT).
* | | |Note1: Never write 0x0 or 0x1 in CMPDAT field, or the core will run into unknown state.
* | | |Note2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if user writes a new value into CMPDAT field
* | | |But if timer is operating at other modes, the 24-bit up counter will restart counting from 0 and using newest CMPDAT value to be the timer compared value while user writes a new value into CMPDAT field.
* @var TIMER_T::INTSTS
* Offset: 0x08 Timer Interrupt Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |TIF |Timer Interrupt Flag
* | | |This bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value.
* | | |0 = No effect.
* | | |1 = CNT value matches the CMPDAT value.
* | | |Note: This bit is cleared by writing 1 to it.
* |[1] |TWKF |Timer Wake-up Flag
* | | |This bit indicates the interrupt wake-up flag status of timer.
* | | |0 = Timer does not cause CPU wake-up.
* | | |1 = CPU wake-up from Idle or Power-down mode if timer time-out interrupt signal generated.
* | | |Note: This bit is cleared by writing 1 to it.
* @var TIMER_T::CNT
* Offset: 0x0C Timer Data Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[23:0] |CNT |Timer Data Register
* | | |Read operation.
* | | |Read this register to get CNT value. For example:
* | | |If EXTCNTEN (TIMERx_CTL[24] ) is 0, user can read CNT value for getting current 24-bit counter value.
* | | |If EXTCNTEN (TIMERx_CTL[24] ) is 1, user can read CNT value for getting current 24-bit event input counter value.
* | | |Write operation.
* | | |Writing any value to this register will reset current CNT value to 0 and reload internal 8-bit prescale counter.
* |[31] |RSTACT |Timer Data Register Reset Active (Read Only)
* | | |This bit indicates if the counter reset operation active.
* | | |When user writes this CNT register, timer starts to reset its internal 24-bit timer up-counter to 0 and reload 8-bit pre-scale counter
* | | |At the same time, timer set this flag to 1 to indicate the counter reset operation is in progress
* | | |Once the counter reset operation done, timer clear this bit to 0 automatically.
* | | |0 = Reset operation is done.
* | | |1 = Reset operation triggered by writing TIMERx_CNT is in progress.
* | | |Note: This bit is read only.
* @var TIMER_T::CAP
* Offset: 0x10 Timer Capture Data Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[23:0] |CAPDAT |Timer Capture Data Register
* | | |When CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[14:12]) setting, CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current timer counter value CNT (TIMERx_CNT[23:0]) will be auto-loaded into this CAPDAT field.
* @var TIMER_T::EXTCTL
* Offset: 0x14 Timer External Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CNTPHASE |Timer External Count Phase
* | | |This bit indicates the detection phase of external counting pin TMx (x= 0~3).
* | | |0 = A falling edge of external counting pin will be counted.
* | | |1 = A rising edge of external counting pin will be counted.
* |[3] |CAPEN |Timer External Capture Pin Enable Bit
* | | |This bit enables the TMx_EXT capture pin input function.
* | | |0 =TMx_EXT (x= 0~3) pin Disabled.
* | | |1 =TMx_EXT (x= 0~3) pin Enabled.
* |[4] |CAPFUNCS |Capture Function Selection
* | | |0 = External Capture Mode Enabled.
* | | |1 = External Reset Mode Enabled.
* | | |Note1: When CAPFUNCS is 0, transition on TMx_EXT (x= 0~3) pin is using to save current 24-bit timer counter value (CNT value) to CAPDAT field.
* | | |Note2: When CAPFUNCS is 1, transition on TMx_EXT (x= 0~3) pin is using to save current 24-bit timer counter value (CNT value) to CAPDAT field then CNT value will be reset immediately.
* |[5] |CAPIEN |Timer External Capture Interrupt Enable Bit
* | | |0 = TMx_EXT (x= 0~3) pin detection Interrupt Disabled.
* | | |1 = TMx_EXT (x= 0~3) pin detection Interrupt Enabled.
* | | |Note: CAPIEN is used to enable timer external interrupt
* | | |If CAPIEN enabled, timer will rise an interrupt when CAPIF (TIMERx_EINTSTS[0]) is 1.
* | | |For example, while CAPIEN = 1, CAPEN = 1, and CAPEDGE = 00, a 1 to 0 transition on the TMx_EXT pin will cause the CAPIF to be set then the interrupt signal is generated and sent to NVIC to inform CPU.
* |[6] |CAPDBEN |Timer External Capture Pin De-bounce Enable Bit
* | | |0 = TMx_EXT (x= 0~3) pin de-bounce or ACMP output de-bounce Disabled.
* | | |1 = TMx_EXT (x= 0~3) pin de-bounce or ACMP output de-bounce Enabled.
* | | |Note: If this bit is enabled, the edge detection of TMx_EXT pin or ACMP output is detected with de-bounce circuit.
* |[7] |CNTDBEN |Timer Counter Pin De-bounce Enable Bit
* | | |0 = TMx (x= 0~3) pin de-bounce Disabled.
* | | |1 = TMx (x= 0~3) pin de-bounce Enabled.
* | | |Note: If this bit is enabled, the edge detection of TMx pin is detected with de-bounce circuit.
* |[8] |ACMPSSEL |ACMP Source Selection to Trigger Capture Function
* | | |0 = Capture Function source is from internal ACMP0 output signal.
* | | |1 = Capture Function source is from internal ACMP1 output signal.
* | | |Note: these bits only available when CAPSRC (TIMERx_CTL[22]) is 1.
* |[14:12] |CAPEDGE |Timer External Capture Pin Edge Detect
* | | |When first capture event is generated, the CNT (TIMERx_CNT[23:0]) will be reset to 0 and first CAPDAT (TIMERx_CAP[23:0]) should be to 0.
* | | |000 = Capture event occurred when detect falling edge transfer on TMx_EXT (x= 0~3) pin.
* | | |001 = Capture event occurred when detect rising edge transfer on TMx_EXT (x= 0~3) pin.
* | | |010 = Capture event occurred when detect both falling and rising edge transfer on TMx_EXT (x= 0~3) pin, and first capture event occurred at falling edge transfer.
* | | |011 = Capture event occurred when detect both rising and falling edge transfer on TMx_EXT (x= 0~3) pin, and first capture event occurred at rising edge transfer..
* | | |110 = First capture event occurred at falling edge, follows capture events are at rising edge transfer on TMx_EXT (x= 0~3) pin.
* | | |111 = First capture event occurred at rising edge, follows capture events are at falling edge transfer on TMx_EXT (x= 0~3) pin.
* | | |100, 101 = Reserved.
* |[16] |ECNTSSEL |Event Counter Source Selection to Trigger Event Counter Function
* | | |0 = Event Counter input source is from TMx (x= 0~3) pin.
* | | |1 = Event Counter input source is from USB internal SOF output signal.
* @var TIMER_T::EINTSTS
* Offset: 0x18 Timer External Interrupt Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CAPIF |Timer External Capture Interrupt Flag
* | | |This bit indicates the timer external capture interrupt flag status.
* | | |0 = TMx_EXT (x= 0~3) pin interrupt did not occur.
* | | |1 = TMx_EXT (x= 0~3) pin interrupt occurred.
* | | |Note1: This bit is cleared by writing 1 to it.
* | | |Note2: When CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on TMx_EXT (x= 0~3) pin matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting, this bit will set to 1 by hardware.
* | | |Note3: There is a new incoming capture event detected before CPU clearing the CAPIF status
* | | |If the above condition occurred, the Timer will keep register TIMERx_CAP unchanged and drop the new capture value.
* @var TIMER_T::TRGCTL
* Offset: 0x1C Timer Trigger Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |TRGSSEL |Trigger Source Select Bit
* | | |This bit is used to select internal trigger source is form timer time-out interrupt signal or
* | | |capture interrupt signal.
* | | |0 = Time-out interrupt signal is used to internal trigger EPWM, PDMA, DAC, and EADC.
* | | |1 = Capture interrupt signal is used to internal trigger EPWM, PDMA, DAC, and EADC.
* |[1] |TRGEPWM |Trigger EPWM Enable Bit
* | | |If this bit is set to 1, each timer time-out event or capture event can be as EPWM counter clock source.
* | | |0 = Timer interrupt trigger EPWM Disabled.
* | | |1 = Timer interrupt trigger EPWM Enabled.
* | | |Note: If TRGSSEL (TIMERx_TRGCTL[0]) = 0, time-out interrupt signal as EPWM counter clock source.
* | | |If TRGSSEL (TIMERx_TRGCTL[0]) = 1, capture interrupt signal as EPWM counter clock source.
* |[2] |TRGEADC |Trigger EADC Enable Bit
* | | |If this bit is set to 1, each timer time-out event or capture event can be triggered EADC conversion.
* | | |0 = Timer interrupt trigger EADC Disabled.
* | | |1 = Timer interrupt trigger EADC Enabled.
* | | |Note: If TRGSSEL (TIMERx_TRGCTL[0]) = 0, time-out interrupt signal will trigger EADC conversion.
* | | |If TRGSSEL (TIMERx_TRGCTL[0]) = 1, capture interrupt signal will trigger EADC conversion.
* |[3] |TRGDAC |Trigger DAC Enable Bit
* | | |If this bit is set to 1, timer time-out interrupt or capture interrupt can be triggered DAC.
* | | |0 = Timer interrupt trigger DAC Disabled.
* | | |1 = Timer interrupt trigger DAC Enabled.
* | | |Note: If TRGSSEL (TIMERx_TRGCTL[0]) = 0, time-out interrupt signal will trigger DAC.
* | | |If TRGSSEL (TIMERx_TRGCTL[0]) = 1, capture interrupt signal will trigger DAC.
* |[4] |TRGPDMA |Trigger PDMA Enable Bit
* | | |If this bit is set to 1, each timer time-out event or capture event can be triggered PDMA transfer.
* | | |0 = Timer interrupt trigger PDMA Disabled.
* | | |1 = Timer interrupt trigger PDMA Enabled.
* | | |Note: If TRGSSEL (TIMERx_TRGCTL[0]) = 0, time-out interrupt signal will trigger PDMA transfer.
* | | |If TRGSSEL (TIMERx_TRGCTL[0]) = 1, capture interrupt signal will trigger PDMA transfer.
* @var TIMER_T::ALTCTL
* Offset: 0x20 Timer Alternative Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |FUNCSEL |Function Selection
* | | |0 = Timer controller is used as timer function.
* | | |1 = Timer controller is used as PWM function.
* | | |Note: When timer is used as PWM, the clock source of time controller will be forced to PCLKx automatically.
* @var TIMER_T::PWMCTL
* Offset: 0x40 Timer PWM Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CNTEN |PWM Counter Enable Bit
* | | |0 = PWM counter and clock prescale Stop Running.
* | | |1 = PWM counter and clock prescale Start Running.
* |[2:1] |CNTTYPE |PWM Counter Behavior Type
* | | |00 = Up count type.
* | | |01 = Down count type.
* | | |10 = Up-down count type.
* | | |11 = Reserved.
* |[3] |CNTMODE |PWM Counter Mode
* | | |0 = Auto-reload mode.
* | | |1 = One-shot mode.
* |[8] |CTRLD |Center Re-load
* | | |In up-down count type, PERIOD will load to PBUF when current PWM period is completed always and CMP will load to CMPBUF at the center point of current period.
* |[9] |IMMLDEN |Immediately Load Enable Bit
* | | |0 = PERIOD will load to PBUF when current PWM period is completed no matter CTRLD is enabled/disabled
* | | |If CTRLD is disabled, CMP will load to CMPBUF when current PWM period is completed; if CTRLD is enabled in up-down count type, CMP will load to CMPBUF at the center point of current period.
* | | |1 = PERIOD/CMP will load to PBUF/CMPBUF immediately when user update PERIOD/CMP.
* | | |Note: If IMMLDEN is enabled, CTRLD will be invalid.
* |[16] |OUTMODE |PWM Output Mode
* | | |This bit controls the output mode of corresponding PWM channel.
* | | |0 = PWM independent mode.
* | | |1 = PWM complementary mode.
* |[30] |DBGHALT |ICE Debug Mode Counter Halt (Write Protect)
* | | |If debug mode counter halt is enabled, PWM counter will keep current value until exit ICE debug mode.
* | | |0 = ICE debug mode counter halt disable.
* | | |1 = ICE debug mode counter halt enable.
* | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
* |[31] |DBGTRIOFF |ICE Debug Mode Acknowledge Disable Bit (Write Protect)
* | | |0 = ICE debug mode acknowledgement effects PWM output.
* | | |PWM output pin will be forced as tri-state while ICE debug mode acknowledged.
* | | |1 = ICE debug mode acknowledgement disabled.
* | | |PWM output pin will keep output no matter ICE debug mode acknowledged or not.
* | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
* @var TIMER_T::PWMCLKSRC
* Offset: 0x44 Timer PWM Counter Clock Source Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[2:0] |CLKSRC |PWM Counter Clock Source Select
* | | |The PWM counter clock source can be selected from TMRx_CLK or internal timer time-out or capture event.
* | | |000 = TMRx_CLK.
* | | |001 = Internal TIMER0 time-out or capture event.
* | | |010 = Internal TIMER1 time-out or capture event.
* | | |011 = Internal TIMER2 time-out or capture event.
* | | |100 = Internal TIMER3 time-out or capture event.
* | | |Others = Reserved.
* | | |Note: If TIMER0 PWM function is enabled, the PWM counter clock source can be selected from TMR0_CLK, TIMER1 interrupt events, TIMER2 interrupt events, or TIMER3 interrupt events.
* @var TIMER_T::PWMCLKPSC
* Offset: 0x48 Timer PWM Counter Clock Pre-scale Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[11:0] |CLKPSC |PWM Counter Clock Pre-scale
* | | |The active clock of PWM counter is decided by counter clock prescale and divided by (CLKPSC + 1)
* | | |If CLKPSC is 0, then there is no scaling in PWM counter clock source.
* @var TIMER_T::PWMCNTCLR
* Offset: 0x4C Timer PWM Clear Counter Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CNTCLR |Clear PWM Counter Control Bit
* | | |It is automatically cleared by hardware.
* | | |0 = No effect.
* | | |1 = Clear 16-bit PWM counter to 0x10000 in up and up-down count type and reset counter value to PERIOD in down count type.
* @var TIMER_T::PWMPERIOD
* Offset: 0x50 Timer PWM Period Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |PERIOD |PWM Period Register
* | | |In up count type: PWM counter counts from 0 to PERIOD, and restarts from 0.
* | | |In down count type: PWM counter counts from PERIOD to 0, and restarts from PERIOD.
* | | |In up-down count type: PWM counter counts from 0 to PERIOD, then decrements to 0 and repeats again.
* | | |In up and down count type:
* | | |PWM period time = (PERIOD + 1) * (CLKPSC + 1) * TMRx_PWMCLK.
* | | |In up-down count type:
* | | |PWM period time = 2 * PERIOD * (CLKPSC+ 1) * TMRx_PWMCLK.
* | | |Note: User should take care DIRF (TIMERx_PWMCNT[16]) bit in up/down/up-down count type to monitor current counter direction in each count type.
* @var TIMER_T::PWMCMPDAT
* Offset: 0x54 Timer PWM Comparator Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |CMP |PWM Comparator Register
* | | |PWM CMP is used to compare with PWM CNT to generate PWM output waveform, interrupt events and trigger ADC to start convert.
* @var TIMER_T::PWMDTCTL
* Offset: 0x58 Timer PWM Dead-Time Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[11:0] |DTCNT |Dead-time Counter (Write Protect)
* | | |The dead-time can be calculated from the following two formulas:
* | | |Dead-time = (DTCNT[11:0] + 1) * TMRx_PWMCLK, if DTCKSEL is 0.
* | | |Dead-time = (DTCNT[11:0] + 1) * TMRx_PWMCLK * (CLKPSC + 1), if DTCKSEL is 1.
* | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
* |[16] |DTEN |Enable Dead-time Insertion for PWMx_CH0 and PWMx_CH1 (Write Protect)
* | | |Dead-time insertion function is only active when PWM complementary mode is enabled
* | | |If dead- time insertion is inactive, the outputs of PWMx_CH0 and PWMx_CH1 are complementary without any delay.
* | | |0 = Dead-time insertion Disabled on the pin pair.
* | | |1 = Dead-time insertion Enabled on the pin pair.
* | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
* |[24] |DTCKSEL |Dead-time Clock Select (Write Protect)
* | | |0 = Dead-time clock source from TMRx_PWMCLK without counter clock prescale.
* | | |1 = Dead-time clock source from TMRx_PWMCLK with counter clock prescale.
* | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
* @var TIMER_T::PWMCNT
* Offset: 0x5C Timer PWM Counter Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |CNT |PWM Counter Value Register (Read Only)
* | | |User can monitor CNT to know the current counter value in 16-bit period counter.
* |[16] |DIRF |PWM Counter Direction Indicator Flag (Read Only)
* | | |0 = Counter is active in down count.
* | | |1 = Counter is active up count.
* @var TIMER_T::PWMMSKEN
* Offset: 0x60 Timer PWM Output Mask Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |MSKEN0 |PWMx_CH0 Output Mask Enable Bit
* | | |The PWMx_CH0 output signal will be masked when this bit is enabled
* | | |The PWMx_CH0 will output MSKDAT0 (TIMER_PWMMSK[0]) data.
* | | |0 = PWMx_CH0 output signal is non-masked.
* | | |1 = PWMx_CH0 output signal is masked and output MSKDAT0 data.
* |[1] |MSKEN1 |PWMx_CH1 Output Mask Enable Bit
* | | |The PWMx_CH1 output signal will be masked when this bit is enabled
* | | |The PWMx_CH1 will output MSKDAT1 (TIMER_PWMMSK[1]) data.
* | | |0 = PWMx_CH1 output signal is non-masked.
* | | |1 = PWMx_CH1 output signal is masked and output MSKDAT1 data.
* @var TIMER_T::PWMMSK
* Offset: 0x64 Timer PWM Output Mask Data Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |MSKDAT0 |PWMx_CH0 Output Mask Data Control Bit
* | | |This bit is used to control the output state of PWMx_CH0 pin when PWMx_CH0 output mask function is enabled (MSKEN0 = 1).
* | | |0 = Output logic Low to PWMx_CH0.
* | | |1 = Output logic High to PWMx_CH0.
* |[1] |MSKDAT1 |PWMx_CH1 Output Mask Data Control Bit
* | | |This bit is used to control the output state of PWMx_CH1 pin when PWMx_CH1 output mask function is enabled (MSKEN1 = 1).
* | | |0 = Output logic Low to PWMx_CH1.
* | | |1 = Output logic High to PWMx_CH1.
* @var TIMER_T::PWMBNF
* Offset: 0x68 Timer PWM Brake Pin Noise Filter Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |BRKNFEN |Brake Pin Noise Filter Enable Bit
* | | |0 = Pin noise filter detect of PWMx_BRAKEy Disabled.
* | | |1 = Pin noise filter detect of PWMx_BRAKEy Enabled.
* |[3:1] |BRKNFSEL |Brake Pin Noise Filter Clock Selection
* | | |000 = Noise filter clock is PCLKx.
* | | |001 = Noise filter clock is PCLKx/2.
* | | |010 = Noise filter clock is PCLKx/4.
* | | |011 = Noise filter clock is PCLKx/8.
* | | |100 = Noise filter clock is PCLKx/16.
* | | |101 = Noise filter clock is PCLKx/32.
* | | |110 = Noise filter clock is PCLKx/64.
* | | |111 = Noise filter clock is PCLKx/128.
* |[6:4] |BRKFCNT |Brake Pin Noise Filter Count
* | | |The fields is used to control the active noise filter sample time.
* | | |Once noise filter sample time = (Period time of BRKDBCS) * BRKFCNT.
* |[7] |BRKPINV |Brake Pin Detection Control Bit
* | | |0 = Brake pin event will be detected if PWMx_BRAKEy pin status transfer from low to high in edge-detect, or pin status is high in level-detect.
* | | |1 = Brake pin event will be detected if PWMx_BRAKEy pin status transfer from high to low in edge-detect, or pin status is low in level-detect .
* |[17:16] |BKPINSRC |Brake Pin Source Select
* | | |00 = Brake pin source comes from PWM0_BRAKE0 pin.
* | | |01 = Brake pin source comes from PWM0_BRAKE1 pin.
* | | |10 = Brake pin source comes from PWM1_BRAKE0 pin.
* | | |11 = Brake pin source comes from PWM1_BRAKE1 pin.
* @var TIMER_T::PWMFAILBRK
* Offset: 0x6C Timer PWM System Fail Brake Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CSSBRKEN |Clock Security System Detection Trigger PWM Brake Function Enable Bit
* | | |0 = Brake Function triggered by clock fail detection Disabled.
* | | |1 = Brake Function triggered by clock fail detection Enabled.
* |[1] |BODBRKEN |Brown-out Detection Trigger PWM Brake Function Enable Bit
* | | |0 = Brake Function triggered by BOD event Disabled.
* | | |1 = Brake Function triggered by BOD event Enabled.
* |[2] |RAMBRKEN |SRAM Parity Error Detection Trigger PWM Brake Function Enable Bit
* | | |0 = Brake Function triggered by SRAM parity error detection Disabled.
* | | |1 = Brake Function triggered by SRAM parity error detection Enabled.
* |[3] |CORBRKEN |Core Lockup Detection Trigger PWM Brake Function Enable Bit
* | | |0 = Brake Function triggered by core lockup event Disabled.
* | | |1 = Brake Function triggered by core lockup event Enabled.
* @var TIMER_T::PWMBRKCTL
* Offset: 0x70 Timer PWM Brake Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CPO0EBEN |Enable Internal ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)
* | | |0 = Internal ACMP0_O signal as edge-detect brake source Disabled.
* | | |1 = Internal ACMP0_O signal as edge-detect brake source Enabled.
* | | |Note1: Only internal ACMP0_O signal from low to high will be detected as brake event.
* | | |Note2: This register is write protected. Refer toSYS_REGLCTL register.
* |[1] |CPO1EBEN |Enable Internal ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)
* | | |0 = Internal ACMP1_O signal as edge-detect brake source Disabled.
* | | |1 = Internal ACMP1_O signal as edge-detect brake source Enabled.
* | | |Note1: Only internal ACMP1_O signal from low to high will be detected as brake event.
* | | |Note2: This register is write protected. Refer toSYS_REGLCTL register.
* |[4] |BRKPEEN |Enable TM_BRAKEx Pin As Edge-detect Brake Source (Write Protect)
* | | |0 = PWMx_BRAKEy pin event as edge-detect brake source Disabled.
* | | |1 = PWMx_BRAKEy pin event as edge-detect brake source Enabled.
* | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
* |[7] |SYSEBEN |Enable System Fail As Edge-detect Brake Source (Write Protect)
* | | |0 = System fail condition as edge-detect brake source Disabled.
* | | |1 = System fail condition as edge-detect brake source Enabled.
* | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
* |[8] |CPO0LBEN |Enable Internal ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)
* | | |0 = Internal ACMP0_O signal as level-detect brake source Disabled.
* | | |1 = Internal ACMP0_O signal as level-detect brake source Enabled.
* | | |Note1: Only internal ACMP0_O signal from low to high will be detected as brake event.
* | | |Note2: This register is write protected. Refer toSYS_REGLCTL register.
* |[9] |CPO1LBEN |Enable Internal ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)
* | | |0 = Internal ACMP1_O signal as level-detect brake source Disabled.
* | | |1 = Internal ACMP1_O signal as level-detect brake source Enabled.
* | | |Note1: Only internal ACMP1_O signal from low to high will be detected as brake event.
* | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
* |[12] |BRKPLEN |Enable TM_BRAKEx Pin As Level-detect Brake Source (Write Protect)
* | | |0 = PWMx_BRAKEy pin event as level-detect brake source Disabled.
* | | |1 = PWMx_BRAKEy pin event as level-detect brake source Enabled.
* | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
* |[15] |SYSLBEN |Enable System Fail As Level-detect Brake Source (Write Protect)
* | | |0 = System fail condition as level-detect brake source Disabled.
* | | |1 = System fail condition as level-detect brake source Enabled.
* | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
* |[17:16] |BRKAEVEN |PWM Brake Action Select for PWMx_CH0 (Write Protect)
* | | |00 = PWMx_BRAKEy brake event will not affect PWMx_CH0 output.
* | | |01 = PWMx_CH0 output tri-state when PWMx_BRAKEy brake event happened.
* | | |10 = PWMx_CH0 output low level when PWMx_BRAKEy brake event happened.
* | | |11 = PWMx_CH0 output high level when PWMx_BRAKEy brake event happened.
* | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
* |[19:18] |BRKAODD |PWM Brake Action Select for PWMx_CH1 (Write Protect)
* | | |00 = PWMx_BRAKEy brake event will not affect PWMx_CH1 output.
* | | |01 = PWMx_CH1 output tri-state when PWMx_BRAKEy brake event happened.
* | | |10 = PWMx_CH1 output low level when PWMx_BRAKEy brake event happened.
* | | |11 = PWMx_CH1 output high level when PWMx_BRAKEy brake event happened.
* | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
* @var TIMER_T::PWMPOLCTL
* Offset: 0x74 Timer PWM Pin Output Polar Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |PINV0 |PWMx_CH0 Output Pin Polar Control Bit
* | | |The bit is used to control polarity state of PWMx_CH0 output pin.
* | | |0 = PWMx_CH0 output pin polar inverse Disabled.
* | | |1 = PWMx_CH0 output pin polar inverse Enabled.
* |[1] |PINV1 |PWMx_CH1 Output Pin Polar Control Bit
* | | |The bit is used to control polarity state of PWMx_CH1 output pin.
* | | |0 = PWMx_CH1 output pin polar inverse Disabled.
* | | |1 = PWMx_CH1 output pin polar inverse Enabled.
* @var TIMER_T::PWMPOEN
* Offset: 0x78 Timer PWM Pin Output Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |POEN0 |PWMx_CH0 Output Pin Enable Bit
* | | |0 = PWMx_CH0 pin at tri-state mode.
* | | |1 = PWMx_CH0 pin in output mode.
* |[1] |POEN1 |PWMx_CH1 Output Pin Enable Bit
* | | |0 = PWMx_CH1 pin at tri-state mode.
* | | |1 = PWMx_CH1 pin in output mode.
* @var TIMER_T::PWMSWBRK
* Offset: 0x7C Timer PWM Software Trigger Brake Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |BRKETRG |Software Trigger Edge-detect Brake Source (Write Only) (Write Protect)
* | | |Write 1 to this bit will trigger PWM edge-detect brake source, then BRKEIF0 and BRKEIF1 will set to 1 automatically in TIMERx_PWMINTSTS1 register.
* | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
* |[8] |BRKLTRG |Software Trigger Level-detect Brake Source (Write Only) (Write Protect)
* | | |Write 1 to this bit will trigger PWM level-detect brake source, then BRKLIF0 and BRKLIF1 will set to 1 automatically in TIMERx_PWMINTSTS1 register.
* | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
* @var TIMER_T::PWMINTEN0
* Offset: 0x80 Timer PWM Interrupt Enable Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ZIEN |PWM Zero Point Interrupt Enable Bit
* | | |0 = Zero point interrupt Disabled.
* | | |1 = Zero point interrupt Enabled.
* |[1] |PIEN |PWM Period Point Interrupt Enable Bit
* | | |0 = Period point interrupt Disabled.
* | | |1 = Period point interrupt Enabled.
* | | |Note: When in up-down count type, period point means the center point of current PWM period.
* |[2] |CMPUIEN |PWM Compare Up Count Interrupt Enable Bit
* | | |0 = Compare up count interrupt Disabled.
* | | |1 = Compare up count interrupt Enabled.
* |[3] |CMPDIEN |PWM Compare Down Count Interrupt Enable Bit
* | | |0 = Compare down count interrupt Disabled.
* | | |1 = Compare down count interrupt Enabled.
* @var TIMER_T::PWMINTEN1
* Offset: 0x84 Timer PWM Interrupt Enable Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |BRKEIEN |PWM Edge-detect Brake Interrupt Enable (Write Protect)
* | | |0 = PWM edge-detect brake interrupt Disabled.
* | | |1 = PWM edge-detect brake interrupt Enabled.
* | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
* |[8] |BRKLIEN |PWM Level-detect Brake Interrupt Enable (Write Protect)
* | | |0 = PWM level-detect brake interrupt Disabled.
* | | |1 = PWM level-detect brake interrupt Enabled.
* | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
* @var TIMER_T::PWMINTSTS0
* Offset: 0x88 Timer PWM Interrupt Status Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ZIF |PWM Zero Point Interrupt Flag
* | | |This bit is set by hardware when TIMERx_PWM counter reaches zero.
* | | |Note: This bit is cleared by writing 1 to it.
* |[1] |PIF |PWM Period Point Interrupt Flag
* | | |This bit is set by hardware when TIMERx_PWM counter reaches PERIOD.
* | | |Note1: When in up-down count type, PIF flag means the center point flag of current PWM period.
* | | |Note2: This bit is cleared by writing 1 to it.
* |[2] |CMPUIF |PWM Compare Up Count Interrupt Flag
* | | |This bit is set by hardware when TIMERx_PWM counter in up count direction and reaches CMP.
* | | |Note1: If CMP equal to PERIOD, there is no CMPUIF flag in up count type and up-down count type.
* | | |Note2: This bit is cleared by writing 1 to it.
* |[3] |CMPDIF |PWM Compare Down Count Interrupt Flag
* | | |This bit is set by hardware when TIMERx_PWM counter in down count direction and reaches CMP.
* | | |Note1: If CMP equal to PERIOD, there is no CMPDIF flag in down count type.
* | | |Note2: This bit is cleared by writing 1 to it.
* @var TIMER_T::PWMINTSTS1
* Offset: 0x8C Timer PWM Interrupt Status Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |BRKEIF0 |Edge-detect Brake Interrupt Flag on PWMx_CH0 (Write Protect)
* | | |0 = PWMx_CH0 edge-detect brake event do not happened.
* | | |1 = PWMx_CH0 edge-detect brake event happened.
* | | |Note1: This bit is cleared by writing 1 to it.
* | | |Note2: This register is write protected. Refer toSYS_REGLCTL register.
* |[1] |BRKEIF1 |Edge-detect Brake Interrupt Flag PWMx_CH1 (Write Protect)
* | | |0 = PWMx_CH1 edge-detect brake event do not happened.
* | | |1 = PWMx_CH1 edge-detect brake event happened.
* | | |Note1: This bit is cleared by writing 1 to it.
* | | |Note2: This register is write protected. Refer toSYS_REGLCTL register.
* |[8] |BRKLIF0 |Level-detect Brake Interrupt Flag on PWMx_CH0 (Write Protect)
* | | |0 = PWMx_CH0 level-detect brake event do not happened.
* | | |1 = PWMx_CH0 level-detect brake event happened.
* | | |Note1: This bit is cleared by writing 1 to it.
* | | |Note2: This register is write protected. Refer toSYS_REGLCTL register.
* |[9] |BRKLIF1 |Level-detect Brake Interrupt Flag on PWMx_CH1 (Write Protect)
* | | |0 = PWMx_CH1 level-detect brake event do not happened.
* | | |1 = PWMx_CH1 level-detect brake event happened.
* | | |Note1: This bit is cleared by writing 1 to it.
* | | |Note2: This register is write protected. Refer toSYS_REGLCTL register.
* |[16] |BRKESTS0 |Edge -detect Brake Status of PWMx_CH0 (Read Only)
* | | |0 = PWMx_CH0 edge-detect brake state is released.
* | | |1 = PWMx_CH0 at edge-detect brake state.
* | | |Note: User can set BRKEIF0 1 to clear BRKEIF0 flag and PWMx_CH0 will release brake state when current PWM period finished and resume PWMx_CH0 output waveform start from next full PWM period.
* |[17] |BRKESTS1 |Edge-detect Brake Status of PWMx_CH1 (Read Only)
* | | |0 = PWMx_CH1 edge-detect brake state is released.
* | | |1 = PWMx_CH1 at edge-detect brake state.
* | | |Note: User can set BRKEIF1 1 to clear BRKEIF1 flag and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH1 output waveform start from next full PWM period.
* |[24] |BRKLSTS0 |Level-detect Brake Status of PWMx_CH0 (Read Only)
* | | |0 = PWMx_CH0 level-detect brake state is released.
* | | |1 = PWMx_CH0 at level-detect brake state.
* | | |Note: If TIMERx_PWM level-detect brake source has released, both PWMx_CH0 and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH0 and PWMx_CH1 output waveform start from next full PWM period.
* |[25] |BRKLSTS1 |Level-detect Brake Status of PWMx_CH1 (Read Only)
* | | |0 = PWMx_CH1 level-detect brake state is released.
* | | |1 = PWMx_CH1 at level-detect brake state.
* | | |Note: If TIMERx_PWM level-detect brake source has released, both PWMx_CH0 and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH0 and PWMx_CH1 output waveform start from next full PWM period.
* @var TIMER_T::PWMEADCTS
* Offset: 0x90 Timer PWM ADC Trigger Source Select Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[2:0] |TRGSEL |PWM Counter Event Source Select to Trigger EADC Conversion
* | | |000 = Trigger EADC conversion at zero point (ZIF).
* | | |001 = Trigger EADC conversion at period point (PIF).
* | | |010 = Trigger EADC conversion at zero or period point (ZIF or PIF).
* | | |011 = Trigger EADC conversion at compare up count point (CMPUIF).
* | | |100 = Trigger EADC conversion at compare down count point (CMPDIF).
* | | |Others = Reserved.
* |[7] |TRGEN |PWM Counter Event Trigger EADC Conversion Enable Bit
* | | |0 = PWM counter event trigger EADC conversion Disabled.
* | | |1 = PWM counter event trigger EADC conversion Enabled.
* @var TIMER_T::PWMSCTL
* Offset: 0x94 Timer PWM Synchronous Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1:0] |SYNCMODE |PWM Synchronous Mode Enable Select
* | | |00 = PWM synchronous function Disabled.
* | | |01 = PWM synchronous counter start function Enabled.
* | | |10 = Reserved.
* | | |11 = PWM synchronous counter clear function Enabled.
* |[8] |SYNCSRC |PWM Synchronous Counter Start/Clear Source Select
* | | |0 = Counter synchronous start/clear by trigger TIMER0_PWMSTRG STRGEN.
* | | |1 = Counter synchronous start/clear by trigger TIMER2_PWMSTRG STRGEN.
* | | |Note1: If TIMER0/1/2/3 PWM counter synchronous source are from TIMER0, TIMER0_PWMSCTL[8], TIMER1_PWMSCTL[8], TIMER2_PWMSCTL[8] and TIMER3_PWMSCTL[8] should be 0.
* | | |Note2: If TIMER0/1/ PWM counter synchronous source are from TIMER0, TIMER0_PWMSCTL[8] and TIMER1_PWMSCTL[8] should be set 0, and TIMER2/3/ PWM counter synchronous source are from TIMER2, TIME2_PWMSCTL[8] and TIMER3_PWMSCTL[8] should be set 1.
* @var TIMER_T::PWMSTRG
* Offset: 0x98 Timer PWM Synchronous Trigger Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |STRGEN |PWM Counter Synchronous Trigger Enable Bit (Write Only)
* | | |PMW counter synchronous function is used to make selected PWM channels (include TIMER0/1/2/3 PWM, TIMER0/1 PWM and TIMER2/3 PWM) start counting or clear counter at the same time according to TIMERx_PWMSCTL setting.
* | | |Note: This bit is only available in TIMER0 and TIMER2.
* @var TIMER_T::PWMSTATUS
* Offset: 0x9C Timer PWM Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CNTMAXF |PWM Counter Equal to 0xFFFF Flag
* | | |0 = Indicates the PWM counter value never reached its maximum value 0xFFFF.
* | | |1 = Indicates the PWM counter value has reached its maximum value.
* | | |Note: This bit is cleared by writing 1 to it.
* |[16] |EADCTRGF |Trigger EADC Start Conversion Flag
* | | |0 = PWM counter event trigger EADC start conversion is not occurred.
* | | |1 = PWM counter event trigger EADC start conversion has occurred.
* | | |Note: This bit is cleared by writing 1 to it.
* @var TIMER_T::PWMPBUF
* Offset: 0xA0 Timer PWM Period Buffer Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |PBUF |PWM Period Buffer Register (Read Only)
* | | |Used as PERIOD active register.
* @var TIMER_T::PWMCMPBUF
* Offset: 0xA4 Timer PWM Comparator Buffer Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |CMPBUF |PWM Comparator Buffer Register (Read Only)
* | | |Used as CMP active register.
*/
__IO uint32_t CTL; /*!< [0x0000] Timer Control Register */
__IO uint32_t CMP; /*!< [0x0004] Timer Comparator Register */
__IO uint32_t INTSTS; /*!< [0x0008] Timer Interrupt Status Register */
__IO uint32_t CNT; /*!< [0x000c] Timer Data Register */
__I uint32_t CAP; /*!< [0x0010] Timer Capture Data Register */
__IO uint32_t EXTCTL; /*!< [0x0014] Timer External Control Register */
__IO uint32_t EINTSTS; /*!< [0x0018] Timer External Interrupt Status Register */
__IO uint32_t TRGCTL; /*!< [0x001c] Timer Trigger Control Register */
__IO uint32_t ALTCTL; /*!< [0x0020] Timer Alternative Control Register */
/** @cond HIDDEN_SYMBOLS */
__I uint32_t RESERVE0[7];
/** @endcond */
__IO uint32_t PWMCTL; /*!< [0x0040] Timer PWM Control Register */
__IO uint32_t PWMCLKSRC; /*!< [0x0044] Timer PWM Counter Clock Source Register */
__IO uint32_t PWMCLKPSC; /*!< [0x0048] Timer PWM Counter Clock Pre-scale Register */
__IO uint32_t PWMCNTCLR; /*!< [0x004c] Timer PWM Clear Counter Register */
__IO uint32_t PWMPERIOD; /*!< [0x0050] Timer PWM Period Register */
__IO uint32_t PWMCMPDAT; /*!< [0x0054] Timer PWM Comparator Register */
__IO uint32_t PWMDTCTL; /*!< [0x0058] Timer PWM Dead-Time Control Register */
__I uint32_t PWMCNT; /*!< [0x005c] Timer PWM Counter Register */
__IO uint32_t PWMMSKEN; /*!< [0x0060] Timer PWM Output Mask Enable Register */
__IO uint32_t PWMMSK; /*!< [0x0064] Timer PWM Output Mask Data Control Register */
__IO uint32_t PWMBNF; /*!< [0x0068] Timer PWM Brake Pin Noise Filter Register */
__IO uint32_t PWMFAILBRK; /*!< [0x006c] Timer PWM System Fail Brake Control Register */
__IO uint32_t PWMBRKCTL; /*!< [0x0070] Timer PWM Brake Control Register */
__IO uint32_t PWMPOLCTL; /*!< [0x0074] Timer PWM Pin Output Polar Control Register */
__IO uint32_t PWMPOEN; /*!< [0x0078] Timer PWM Pin Output Enable Register */
__O uint32_t PWMSWBRK; /*!< [0x007c] Timer PWM Software Trigger Brake Control Register */
__IO uint32_t PWMINTEN0; /*!< [0x0080] Timer PWM Interrupt Enable Register 0 */
__IO uint32_t PWMINTEN1; /*!< [0x0084] Timer PWM Interrupt Enable Register 1 */
__IO uint32_t PWMINTSTS0; /*!< [0x0088] Timer PWM Interrupt Status Register 0 */
__IO uint32_t PWMINTSTS1; /*!< [0x008c] Timer PWM Interrupt Status Register 1 */
__IO uint32_t PWMEADCTS; /*!< [0x0090] Timer PWM EADC Trigger Source Select Register */
__IO uint32_t PWMSCTL; /*!< [0x0094] Timer PWM Synchronous Control Register */
__O uint32_t PWMSTRG; /*!< [0x0098] Timer PWM Synchronous Trigger Register */
__IO uint32_t PWMSTATUS; /*!< [0x009c] Timer PWM Status Register */
__I uint32_t PWMPBUF; /*!< [0x00a0] Timer PWM Period Buffer Register */
__I uint32_t PWMCMPBUF; /*!< [0x00a4] Timer PWM Comparator Buffer Register */
} TIMER_T;
/**
@addtogroup TIMER_CONST TIMER Bit Field Definition
Constant Definitions for TIMER Controller
@{ */
#define TIMER_CTL_PSC_Pos (0) /*!< TIMER_T::CTL: PSC Position */
#define TIMER_CTL_PSC_Msk (0xfful << TIMER_CTL_PSC_Pos) /*!< TIMER_T::CTL: PSC Mask */
#define TIMER_CTL_INTRGEN_Pos (19) /*!< TIMER_T::CTL: INTRGEN Position */
#define TIMER_CTL_INTRGEN_Msk (0x1ul << TIMER_CTL_INTRGEN_Pos) /*!< TIMER_T::CTL: INTRGEN Mask */
#define TIMER_CTL_PERIOSEL_Pos (20) /*!< TIMER_T::CTL: PERIOSEL Position */
#define TIMER_CTL_PERIOSEL_Msk (0x1ul << TIMER_CTL_PERIOSEL_Pos) /*!< TIMER_T::CTL: PERIOSEL Mask */
#define TIMER_CTL_TGLPINSEL_Pos (21) /*!< TIMER_T::CTL: TGLPINSEL Position */
#define TIMER_CTL_TGLPINSEL_Msk (0x1ul << TIMER_CTL_TGLPINSEL_Pos) /*!< TIMER_T::CTL: TGLPINSEL Mask */
#define TIMER_CTL_CAPSRC_Pos (22) /*!< TIMER_T::CTL: CAPSRC Position */
#define TIMER_CTL_CAPSRC_Msk (0x1ul << TIMER_CTL_CAPSRC_Pos) /*!< TIMER_T::CTL: CAPSRC Mask */
#define TIMER_CTL_WKEN_Pos (23) /*!< TIMER_T::CTL: WKEN Position */
#define TIMER_CTL_WKEN_Msk (0x1ul << TIMER_CTL_WKEN_Pos) /*!< TIMER_T::CTL: WKEN Mask */
#define TIMER_CTL_EXTCNTEN_Pos (24) /*!< TIMER_T::CTL: EXTCNTEN Position */
#define TIMER_CTL_EXTCNTEN_Msk (0x1ul << TIMER_CTL_EXTCNTEN_Pos) /*!< TIMER_T::CTL: EXTCNTEN Mask */
#define TIMER_CTL_ACTSTS_Pos (25) /*!< TIMER_T::CTL: ACTSTS Position */
#define TIMER_CTL_ACTSTS_Msk (0x1ul << TIMER_CTL_ACTSTS_Pos) /*!< TIMER_T::CTL: ACTSTS Mask */
#define TIMER_CTL_OPMODE_Pos (27) /*!< TIMER_T::CTL: OPMODE Position */
#define TIMER_CTL_OPMODE_Msk (0x3ul << TIMER_CTL_OPMODE_Pos) /*!< TIMER_T::CTL: OPMODE Mask */
#define TIMER_CTL_INTEN_Pos (29) /*!< TIMER_T::CTL: INTEN Position */
#define TIMER_CTL_INTEN_Msk (0x1ul << TIMER_CTL_INTEN_Pos) /*!< TIMER_T::CTL: INTEN Mask */
#define TIMER_CTL_CNTEN_Pos (30) /*!< TIMER_T::CTL: CNTEN Position */
#define TIMER_CTL_CNTEN_Msk (0x1ul << TIMER_CTL_CNTEN_Pos) /*!< TIMER_T::CTL: CNTEN Mask */
#define TIMER_CTL_ICEDEBUG_Pos (31) /*!< TIMER_T::CTL: ICEDEBUG Position */
#define TIMER_CTL_ICEDEBUG_Msk (0x1ul << TIMER_CTL_ICEDEBUG_Pos) /*!< TIMER_T::CTL: ICEDEBUG Mask */
#define TIMER_CMP_CMPDAT_Pos (0) /*!< TIMER_T::CMP: CMPDAT Position */
#define TIMER_CMP_CMPDAT_Msk (0xfffffful << TIMER_CMP_CMPDAT_Pos) /*!< TIMER_T::CMP: CMPDAT Mask */
#define TIMER_INTSTS_TIF_Pos (0) /*!< TIMER_T::INTSTS: TIF Position */
#define TIMER_INTSTS_TIF_Msk (0x1ul << TIMER_INTSTS_TIF_Pos) /*!< TIMER_T::INTSTS: TIF Mask */
#define TIMER_INTSTS_TWKF_Pos (1) /*!< TIMER_T::INTSTS: TWKF Position */
#define TIMER_INTSTS_TWKF_Msk (0x1ul << TIMER_INTSTS_TWKF_Pos) /*!< TIMER_T::INTSTS: TWKF Mask */
#define TIMER_CNT_CNT_Pos (0) /*!< TIMER_T::CNT: CNT Position */
#define TIMER_CNT_CNT_Msk (0xfffffful << TIMER_CNT_CNT_Pos) /*!< TIMER_T::CNT: CNT Mask */
#define TIMER_CNT_RSTACT_Pos (31) /*!< TIMER_T::CNT: RSTACT Position */
#define TIMER_CNT_RSTACT_Msk (0x1ul << TIMER_CNT_RSTACT_Pos) /*!< TIMER_T::CNT: RSTACT Mask */
#define TIMER_CAP_CAPDAT_Pos (0) /*!< TIMER_T::CAP: CAPDAT Position */
#define TIMER_CAP_CAPDAT_Msk (0xfffffful << TIMER_CAP_CAPDAT_Pos) /*!< TIMER_T::CAP: CAPDAT Mask */
#define TIMER_EXTCTL_CNTPHASE_Pos (0) /*!< TIMER_T::EXTCTL: CNTPHASE Position */
#define TIMER_EXTCTL_CNTPHASE_Msk (0x1ul << TIMER_EXTCTL_CNTPHASE_Pos) /*!< TIMER_T::EXTCTL: CNTPHASE Mask */
#define TIMER_EXTCTL_CAPEN_Pos (3) /*!< TIMER_T::EXTCTL: CAPEN Position */
#define TIMER_EXTCTL_CAPEN_Msk (0x1ul << TIMER_EXTCTL_CAPEN_Pos) /*!< TIMER_T::EXTCTL: CAPEN Mask */
#define TIMER_EXTCTL_CAPFUNCS_Pos (4) /*!< TIMER_T::EXTCTL: CAPFUNCS Position */
#define TIMER_EXTCTL_CAPFUNCS_Msk (0x1ul << TIMER_EXTCTL_CAPFUNCS_Pos) /*!< TIMER_T::EXTCTL: CAPFUNCS Mask */
#define TIMER_EXTCTL_CAPIEN_Pos (5) /*!< TIMER_T::EXTCTL: CAPIEN Position */
#define TIMER_EXTCTL_CAPIEN_Msk (0x1ul << TIMER_EXTCTL_CAPIEN_Pos) /*!< TIMER_T::EXTCTL: CAPIEN Mask */
#define TIMER_EXTCTL_CAPDBEN_Pos (6) /*!< TIMER_T::EXTCTL: CAPDBEN Position */
#define TIMER_EXTCTL_CAPDBEN_Msk (0x1ul << TIMER_EXTCTL_CAPDBEN_Pos) /*!< TIMER_T::EXTCTL: CAPDBEN Mask */
#define TIMER_EXTCTL_CNTDBEN_Pos (7) /*!< TIMER_T::EXTCTL: CNTDBEN Position */
#define TIMER_EXTCTL_CNTDBEN_Msk (0x1ul << TIMER_EXTCTL_CNTDBEN_Pos) /*!< TIMER_T::EXTCTL: CNTDBEN Mask */
#define TIMER_EXTCTL_ACMPSSEL_Pos (8) /*!< TIMER_T::EXTCTL: ACMPSSEL Position */
#define TIMER_EXTCTL_ACMPSSEL_Msk (0x1ul << TIMER_EXTCTL_ACMPSSEL_Pos) /*!< TIMER_T::EXTCTL: ACMPSSEL Mask */
#define TIMER_EXTCTL_CAPEDGE_Pos (12) /*!< TIMER_T::EXTCTL: CAPEDGE Position */
#define TIMER_EXTCTL_CAPEDGE_Msk (0x7ul << TIMER_EXTCTL_CAPEDGE_Pos) /*!< TIMER_T::EXTCTL: CAPEDGE Mask */
#define TIMER_EXTCTL_ECNTSSEL_Pos (16) /*!< TIMER_T::EXTCTL: ECNTSSEL Position */
#define TIMER_EXTCTL_ECNTSSEL_Msk (0x1ul << TIMER_EXTCTL_ECNTSSEL_Pos) /*!< TIMER_T::EXTCTL: ECNTSSEL Mask */
#define TIMER_EINTSTS_CAPIF_Pos (0) /*!< TIMER_T::EINTSTS: CAPIF Position */
#define TIMER_EINTSTS_CAPIF_Msk (0x1ul << TIMER_EINTSTS_CAPIF_Pos) /*!< TIMER_T::EINTSTS: CAPIF Mask */
#define TIMER_TRGCTL_TRGSSEL_Pos (0) /*!< TIMER_T::TRGCTL: TRGSSEL Position */
#define TIMER_TRGCTL_TRGSSEL_Msk (0x1ul << TIMER_TRGCTL_TRGSSEL_Pos) /*!< TIMER_T::TRGCTL: TRGSSEL Mask */
#define TIMER_TRGCTL_TRGEPWM_Pos (1) /*!< TIMER_T::TRGCTL: TRGEPWM Position */
#define TIMER_TRGCTL_TRGEPWM_Msk (0x1ul << TIMER_TRGCTL_TRGEPWM_Pos) /*!< TIMER_T::TRGCTL: TRGEPWM Mask */
#define TIMER_TRGCTL_TRGEADC_Pos (2) /*!< TIMER_T::TRGCTL: TRGEADC Position */
#define TIMER_TRGCTL_TRGEADC_Msk (0x1ul << TIMER_TRGCTL_TRGEADC_Pos) /*!< TIMER_T::TRGCTL: TRGEADC Mask */
#define TIMER_TRGCTL_TRGDAC_Pos (3) /*!< TIMER_T::TRGCTL: TRGDAC Position */
#define TIMER_TRGCTL_TRGDAC_Msk (0x1ul << TIMER_TRGCTL_TRGDAC_Pos) /*!< TIMER_T::TRGCTL: TRGDAC Mask */
#define TIMER_TRGCTL_TRGPDMA_Pos (4) /*!< TIMER_T::TRGCTL: TRGPDMA Position */
#define TIMER_TRGCTL_TRGPDMA_Msk (0x1ul << TIMER_TRGCTL_TRGPDMA_Pos) /*!< TIMER_T::TRGCTL: TRGPDMA Mask */
#define TIMER_ALTCTL_FUNCSEL_Pos (0) /*!< TIMER_T::ALTCTL: FUNCSEL Position */
#define TIMER_ALTCTL_FUNCSEL_Msk (0x1ul << TIMER_ALTCTL_FUNCSEL_Pos) /*!< TIMER_T::ALTCTL: FUNCSEL Mask */
#define TIMER_PWMCTL_CNTEN_Pos (0) /*!< TIMER_T::PWMCTL: CNTEN Position */
#define TIMER_PWMCTL_CNTEN_Msk (0x1ul << TIMER_PWMCTL_CNTEN_Pos) /*!< TIMER_T::PWMCTL: CNTEN Mask */
#define TIMER_PWMCTL_CNTTYPE_Pos (1) /*!< TIMER_T::PWMCTL: CNTTYPE Position */
#define TIMER_PWMCTL_CNTTYPE_Msk (0x3ul << TIMER_PWMCTL_CNTTYPE_Pos) /*!< TIMER_T::PWMCTL: CNTTYPE Mask */
#define TIMER_PWMCTL_CNTMODE_Pos (3) /*!< TIMER_T::PWMCTL: CNTMODE Position */
#define TIMER_PWMCTL_CNTMODE_Msk (0x1ul << TIMER_PWMCTL_CNTMODE_Pos) /*!< TIMER_T::PWMCTL: CNTMODE Mask */
#define TIMER_PWMCTL_CTRLD_Pos (8) /*!< TIMER_T::PWMCTL: CTRLD Position */
#define TIMER_PWMCTL_CTRLD_Msk (0x1ul << TIMER_PWMCTL_CTRLD_Pos) /*!< TIMER_T::PWMCTL: CTRLD Mask */
#define TIMER_PWMCTL_IMMLDEN_Pos (9) /*!< TIMER_T::PWMCTL: IMMLDEN Position */
#define TIMER_PWMCTL_IMMLDEN_Msk (0x1ul << TIMER_PWMCTL_IMMLDEN_Pos) /*!< TIMER_T::PWMCTL: IMMLDEN Mask */
#define TIMER_PWMCTL_OUTMODE_Pos (16) /*!< TIMER_T::PWMCTL: OUTMODE Position */
#define TIMER_PWMCTL_OUTMODE_Msk (0x1ul << TIMER_PWMCTL_OUTMODE_Pos) /*!< TIMER_T::PWMCTL: OUTMODE Mask */
#define TIMER_PWMCTL_DBGHALT_Pos (30) /*!< TIMER_T::PWMCTL: DBGHALT Position */
#define TIMER_PWMCTL_DBGHALT_Msk (0x1ul << TIMER_PWMCTL_DBGHALT_Pos) /*!< TIMER_T::PWMCTL: DBGHALT Mask */
#define TIMER_PWMCTL_DBGTRIOFF_Pos (31) /*!< TIMER_T::PWMCTL: DBGTRIOFF Position */
#define TIMER_PWMCTL_DBGTRIOFF_Msk (0x1ul << TIMER_PWMCTL_DBGTRIOFF_Pos) /*!< TIMER_T::PWMCTL: DBGTRIOFF Mask */
#define TIMER_PWMCLKSRC_CLKSRC_Pos (0) /*!< TIMER_T::PWMCLKSRC: CLKSRC Position */
#define TIMER_PWMCLKSRC_CLKSRC_Msk (0x7ul << TIMER_PWMCLKSRC_CLKSRC_Pos) /*!< TIMER_T::PWMCLKSRC: CLKSRC Mask */
#define TIMER_PWMCLKPSC_CLKPSC_Pos (0) /*!< TIMER_T::PWMCLKPSC: CLKPSC Position */
#define TIMER_PWMCLKPSC_CLKPSC_Msk (0xffful << TIMER_PWMCLKPSC_CLKPSC_Pos) /*!< TIMER_T::PWMCLKPSC: CLKPSC Mask */
#define TIMER_PWMCNTCLR_CNTCLR_Pos (0) /*!< TIMER_T::PWMCNTCLR: CNTCLR Position */
#define TIMER_PWMCNTCLR_CNTCLR_Msk (0x1ul << TIMER_PWMCNTCLR_CNTCLR_Pos) /*!< TIMER_T::PWMCNTCLR: CNTCLR Mask */
#define TIMER_PWMPERIOD_PERIOD_Pos (0) /*!< TIMER_T::PWMPERIOD: PERIOD Position */
#define TIMER_PWMPERIOD_PERIOD_Msk (0xfffful << TIMER_PWMPERIOD_PERIOD_Pos) /*!< TIMER_T::PWMPERIOD: PERIOD Mask */
#define TIMER_PWMCMPDAT_CMP_Pos (0) /*!< TIMER_T::PWMCMPDAT: CMP Position */
#define TIMER_PWMCMPDAT_CMP_Msk (0xfffful << TIMER_PWMCMPDAT_CMP_Pos) /*!< TIMER_T::PWMCMPDAT: CMP Mask */
#define TIMER_PWMDTCTL_DTCNT_Pos (0) /*!< TIMER_T::PWMDTCTL: DTCNT Position */
#define TIMER_PWMDTCTL_DTCNT_Msk (0xffful << TIMER_PWMDTCTL_DTCNT_Pos) /*!< TIMER_T::PWMDTCTL: DTCNT Mask */
#define TIMER_PWMDTCTL_DTEN_Pos (16) /*!< TIMER_T::PWMDTCTL: DTEN Position */
#define TIMER_PWMDTCTL_DTEN_Msk (0x1ul << TIMER_PWMDTCTL_DTEN_Pos) /*!< TIMER_T::PWMDTCTL: DTEN Mask */
#define TIMER_PWMDTCTL_DTCKSEL_Pos (24) /*!< TIMER_T::PWMDTCTL: DTCKSEL Position */
#define TIMER_PWMDTCTL_DTCKSEL_Msk (0x1ul << TIMER_PWMDTCTL_DTCKSEL_Pos) /*!< TIMER_T::PWMDTCTL: DTCKSEL Mask */
#define TIMER_PWMCNT_CNT_Pos (0) /*!< TIMER_T::PWMCNT: CNT Position */
#define TIMER_PWMCNT_CNT_Msk (0xfffful << TIMER_PWMCNT_CNT_Pos) /*!< TIMER_T::PWMCNT: CNT Mask */
#define TIMER_PWMCNT_DIRF_Pos (16) /*!< TIMER_T::PWMCNT: DIRF Position */
#define TIMER_PWMCNT_DIRF_Msk (0x1ul << TIMER_PWMCNT_DIRF_Pos) /*!< TIMER_T::PWMCNT: DIRF Mask */
#define TIMER_PWMMSKEN_MSKEN0_Pos (0) /*!< TIMER_T::PWMMSKEN: MSKEN0 Position */
#define TIMER_PWMMSKEN_MSKEN0_Msk (0x1ul << TIMER_PWMMSKEN_MSKEN0_Pos) /*!< TIMER_T::PWMMSKEN: MSKEN0 Mask */
#define TIMER_PWMMSKEN_MSKEN1_Pos (1) /*!< TIMER_T::PWMMSKEN: MSKEN1 Position */
#define TIMER_PWMMSKEN_MSKEN1_Msk (0x1ul << TIMER_PWMMSKEN_MSKEN1_Pos) /*!< TIMER_T::PWMMSKEN: MSKEN1 Mask */
#define TIMER_PWMMSK_MSKDAT0_Pos (0) /*!< TIMER_T::PWMMSK: MSKDAT0 Position */
#define TIMER_PWMMSK_MSKDAT0_Msk (0x1ul << TIMER_PWMMSK_MSKDAT0_Pos) /*!< TIMER_T::PWMMSK: MSKDAT0 Mask */
#define TIMER_PWMMSK_MSKDAT1_Pos (1) /*!< TIMER_T::PWMMSK: MSKDAT1 Position */
#define TIMER_PWMMSK_MSKDAT1_Msk (0x1ul << TIMER_PWMMSK_MSKDAT1_Pos) /*!< TIMER_T::PWMMSK: MSKDAT1 Mask */
#define TIMER_PWMBNF_BRKNFEN_Pos (0) /*!< TIMER_T::PWMBNF: BRKNFEN Position */
#define TIMER_PWMBNF_BRKNFEN_Msk (0x1ul << TIMER_PWMBNF_BRKNFEN_Pos) /*!< TIMER_T::PWMBNF: BRKNFEN Mask */
#define TIMER_PWMBNF_BRKNFSEL_Pos (1) /*!< TIMER_T::PWMBNF: BRKNFSEL Position */
#define TIMER_PWMBNF_BRKNFSEL_Msk (0x7ul << TIMER_PWMBNF_BRKNFSEL_Pos) /*!< TIMER_T::PWMBNF: BRKNFSEL Mask */
#define TIMER_PWMBNF_BRKFCNT_Pos (4) /*!< TIMER_T::PWMBNF: BRKFCNT Position */
#define TIMER_PWMBNF_BRKFCNT_Msk (0x7ul << TIMER_PWMBNF_BRKFCNT_Pos) /*!< TIMER_T::PWMBNF: BRKFCNT Mask */
#define TIMER_PWMBNF_BRKPINV_Pos (7) /*!< TIMER_T::PWMBNF: BRKPINV Position */
#define TIMER_PWMBNF_BRKPINV_Msk (0x1ul << TIMER_PWMBNF_BRKPINV_Pos) /*!< TIMER_T::PWMBNF: BRKPINV Mask */
#define TIMER_PWMBNF_BKPINSRC_Pos (16) /*!< TIMER_T::PWMBNF: BKPINSRC Position */
#define TIMER_PWMBNF_BKPINSRC_Msk (0x3ul << TIMER_PWMBNF_BKPINSRC_Pos) /*!< TIMER_T::PWMBNF: BKPINSRC Mask */
#define TIMER_PWMFAILBRK_CSSBRKEN_Pos (0) /*!< TIMER_T::PWMFAILBRK: CSSBRKEN Position */
#define TIMER_PWMFAILBRK_CSSBRKEN_Msk (0x1ul << TIMER_PWMFAILBRK_CSSBRKEN_Pos) /*!< TIMER_T::PWMFAILBRK: CSSBRKEN Mask */
#define TIMER_PWMFAILBRK_BODBRKEN_Pos (1) /*!< TIMER_T::PWMFAILBRK: BODBRKEN Position */
#define TIMER_PWMFAILBRK_BODBRKEN_Msk (0x1ul << TIMER_PWMFAILBRK_BODBRKEN_Pos) /*!< TIMER_T::PWMFAILBRK: BODBRKEN Mask */
#define TIMER_PWMFAILBRK_RAMBRKEN_Pos (2) /*!< TIMER_T::PWMFAILBRK: RAMBRKEN Position */
#define TIMER_PWMFAILBRK_RAMBRKEN_Msk (0x1ul << TIMER_PWMFAILBRK_RAMBRKEN_Pos) /*!< TIMER_T::PWMFAILBRK: RAMBRKEN Mask */
#define TIMER_PWMFAILBRK_CORBRKEN_Pos (3) /*!< TIMER_T::PWMFAILBRK: CORBRKEN Position */
#define TIMER_PWMFAILBRK_CORBRKEN_Msk (0x1ul << TIMER_PWMFAILBRK_CORBRKEN_Pos) /*!< TIMER_T::PWMFAILBRK: CORBRKEN Mask */
#define TIMER_PWMBRKCTL_CPO0EBEN_Pos (0) /*!< TIMER_T::PWMBRKCTL: CPO0EBEN Position */
#define TIMER_PWMBRKCTL_CPO0EBEN_Msk (0x1ul << TIMER_PWMBRKCTL_CPO0EBEN_Pos) /*!< TIMER_T::PWMBRKCTL: CPO0EBEN Mask */
#define TIMER_PWMBRKCTL_CPO1EBEN_Pos (1) /*!< TIMER_T::PWMBRKCTL: CPO1EBEN Position */
#define TIMER_PWMBRKCTL_CPO1EBEN_Msk (0x1ul << TIMER_PWMBRKCTL_CPO1EBEN_Pos) /*!< TIMER_T::PWMBRKCTL: CPO1EBEN Mask */
#define TIMER_PWMBRKCTL_BRKPEEN_Pos (4) /*!< TIMER_T::PWMBRKCTL: BRKPEEN Position */
#define TIMER_PWMBRKCTL_BRKPEEN_Msk (0x1ul << TIMER_PWMBRKCTL_BRKPEEN_Pos) /*!< TIMER_T::PWMBRKCTL: BRKPEEN Mask */
#define TIMER_PWMBRKCTL_SYSEBEN_Pos (7) /*!< TIMER_T::PWMBRKCTL: SYSEBEN Position */
#define TIMER_PWMBRKCTL_SYSEBEN_Msk (0x1ul << TIMER_PWMBRKCTL_SYSEBEN_Pos) /*!< TIMER_T::PWMBRKCTL: SYSEBEN Mask */
#define TIMER_PWMBRKCTL_CPO0LBEN_Pos (8) /*!< TIMER_T::PWMBRKCTL: CPO0LBEN Position */
#define TIMER_PWMBRKCTL_CPO0LBEN_Msk (0x1ul << TIMER_PWMBRKCTL_CPO0LBEN_Pos) /*!< TIMER_T::PWMBRKCTL: CPO0LBEN Mask */
#define TIMER_PWMBRKCTL_CPO1LBEN_Pos (9) /*!< TIMER_T::PWMBRKCTL: CPO1LBEN Position */
#define TIMER_PWMBRKCTL_CPO1LBEN_Msk (0x1ul << TIMER_PWMBRKCTL_CPO1LBEN_Pos) /*!< TIMER_T::PWMBRKCTL: CPO1LBEN Mask */
#define TIMER_PWMBRKCTL_BRKPLEN_Pos (12) /*!< TIMER_T::PWMBRKCTL: BRKPLEN Position */
#define TIMER_PWMBRKCTL_BRKPLEN_Msk (0x1ul << TIMER_PWMBRKCTL_BRKPLEN_Pos) /*!< TIMER_T::PWMBRKCTL: BRKPLEN Mask */
#define TIMER_PWMBRKCTL_SYSLBEN_Pos (15) /*!< TIMER_T::PWMBRKCTL: SYSLBEN Position */
#define TIMER_PWMBRKCTL_SYSLBEN_Msk (0x1ul << TIMER_PWMBRKCTL_SYSLBEN_Pos) /*!< TIMER_T::PWMBRKCTL: SYSLBEN Mask */
#define TIMER_PWMBRKCTL_BRKAEVEN_Pos (16) /*!< TIMER_T::PWMBRKCTL: BRKAEVEN Position */
#define TIMER_PWMBRKCTL_BRKAEVEN_Msk (0x3ul << TIMER_PWMBRKCTL_BRKAEVEN_Pos) /*!< TIMER_T::PWMBRKCTL: BRKAEVEN Mask */
#define TIMER_PWMBRKCTL_BRKAODD_Pos (18) /*!< TIMER_T::PWMBRKCTL: BRKAODD Position */
#define TIMER_PWMBRKCTL_BRKAODD_Msk (0x3ul << TIMER_PWMBRKCTL_BRKAODD_Pos) /*!< TIMER_T::PWMBRKCTL: BRKAODD Mask */
#define TIMER_PWMPOLCTL_PINV0_Pos (0) /*!< TIMER_T::PWMPOLCTL: PINV0 Position */
#define TIMER_PWMPOLCTL_PINV0_Msk (0x1ul << TIMER_PWMPOLCTL_PINV0_Pos) /*!< TIMER_T::PWMPOLCTL: PINV0 Mask */
#define TIMER_PWMPOLCTL_PINV1_Pos (1) /*!< TIMER_T::PWMPOLCTL: PINV1 Position */
#define TIMER_PWMPOLCTL_PINV1_Msk (0x1ul << TIMER_PWMPOLCTL_PINV1_Pos) /*!< TIMER_T::PWMPOLCTL: PINV1 Mask */
#define TIMER_PWMPOEN_POEN0_Pos (0) /*!< TIMER_T::PWMPOEN: POEN0 Position */
#define TIMER_PWMPOEN_POEN0_Msk (0x1ul << TIMER_PWMPOEN_POEN0_Pos) /*!< TIMER_T::PWMPOEN: POEN0 Mask */
#define TIMER_PWMPOEN_POEN1_Pos (1) /*!< TIMER_T::PWMPOEN: POEN1 Position */
#define TIMER_PWMPOEN_POEN1_Msk (0x1ul << TIMER_PWMPOEN_POEN1_Pos) /*!< TIMER_T::PWMPOEN: POEN1 Mask */
#define TIMER_PWMSWBRK_BRKETRG_Pos (0) /*!< TIMER_T::PWMSWBRK: BRKETRG Position */
#define TIMER_PWMSWBRK_BRKETRG_Msk (0x1ul << TIMER_PWMSWBRK_BRKETRG_Pos) /*!< TIMER_T::PWMSWBRK: BRKETRG Mask */
#define TIMER_PWMSWBRK_BRKLTRG_Pos (8) /*!< TIMER_T::PWMSWBRK: BRKLTRG Position */
#define TIMER_PWMSWBRK_BRKLTRG_Msk (0x1ul << TIMER_PWMSWBRK_BRKLTRG_Pos) /*!< TIMER_T::PWMSWBRK: BRKLTRG Mask */
#define TIMER_PWMINTEN0_ZIEN_Pos (0) /*!< TIMER_T::PWMINTEN0: ZIEN Position */
#define TIMER_PWMINTEN0_ZIEN_Msk (0x1ul << TIMER_PWMINTEN0_ZIEN_Pos) /*!< TIMER_T::PWMINTEN0: ZIEN Mask */
#define TIMER_PWMINTEN0_PIEN_Pos (1) /*!< TIMER_T::PWMINTEN0: PIEN Position */
#define TIMER_PWMINTEN0_PIEN_Msk (0x1ul << TIMER_PWMINTEN0_PIEN_Pos) /*!< TIMER_T::PWMINTEN0: PIEN Mask */
#define TIMER_PWMINTEN0_CMPUIEN_Pos (2) /*!< TIMER_T::PWMINTEN0: CMPUIEN Position */
#define TIMER_PWMINTEN0_CMPUIEN_Msk (0x1ul << TIMER_PWMINTEN0_CMPUIEN_Pos) /*!< TIMER_T::PWMINTEN0: CMPUIEN Mask */
#define TIMER_PWMINTEN0_CMPDIEN_Pos (3) /*!< TIMER_T::PWMINTEN0: CMPDIEN Position */
#define TIMER_PWMINTEN0_CMPDIEN_Msk (0x1ul << TIMER_PWMINTEN0_CMPDIEN_Pos) /*!< TIMER_T::PWMINTEN0: CMPDIEN Mask */
#define TIMER_PWMINTEN1_BRKEIEN_Pos (0) /*!< TIMER_T::PWMINTEN1: BRKEIEN Position */
#define TIMER_PWMINTEN1_BRKEIEN_Msk (0x1ul << TIMER_PWMINTEN1_BRKEIEN_Pos) /*!< TIMER_T::PWMINTEN1: BRKEIEN Mask */
#define TIMER_PWMINTEN1_BRKLIEN_Pos (8) /*!< TIMER_T::PWMINTEN1: BRKLIEN Position */
#define TIMER_PWMINTEN1_BRKLIEN_Msk (0x1ul << TIMER_PWMINTEN1_BRKLIEN_Pos) /*!< TIMER_T::PWMINTEN1: BRKLIEN Mask */
#define TIMER_PWMINTSTS0_ZIF_Pos (0) /*!< TIMER_T::PWMINTSTS0: ZIF Position */
#define TIMER_PWMINTSTS0_ZIF_Msk (0x1ul << TIMER_PWMINTSTS0_ZIF_Pos) /*!< TIMER_T::PWMINTSTS0: ZIF Mask */
#define TIMER_PWMINTSTS0_PIF_Pos (1) /*!< TIMER_T::PWMINTSTS0: PIF Position */
#define TIMER_PWMINTSTS0_PIF_Msk (0x1ul << TIMER_PWMINTSTS0_PIF_Pos) /*!< TIMER_T::PWMINTSTS0: PIF Mask */
#define TIMER_PWMINTSTS0_CMPUIF_Pos (2) /*!< TIMER_T::PWMINTSTS0: CMPUIF Position */
#define TIMER_PWMINTSTS0_CMPUIF_Msk (0x1ul << TIMER_PWMINTSTS0_CMPUIF_Pos) /*!< TIMER_T::PWMINTSTS0: CMPUIF Mask */
#define TIMER_PWMINTSTS0_CMPDIF_Pos (3) /*!< TIMER_T::PWMINTSTS0: CMPDIF Position */
#define TIMER_PWMINTSTS0_CMPDIF_Msk (0x1ul << TIMER_PWMINTSTS0_CMPDIF_Pos) /*!< TIMER_T::PWMINTSTS0: CMPDIF Mask */
#define TIMER_PWMINTSTS1_BRKEIF0_Pos (0) /*!< TIMER_T::PWMINTSTS1: BRKEIF0 Position */
#define TIMER_PWMINTSTS1_BRKEIF0_Msk (0x1ul << TIMER_PWMINTSTS1_BRKEIF0_Pos) /*!< TIMER_T::PWMINTSTS1: BRKEIF0 Mask */
#define TIMER_PWMINTSTS1_BRKEIF1_Pos (1) /*!< TIMER_T::PWMINTSTS1: BRKEIF1 Position */
#define TIMER_PWMINTSTS1_BRKEIF1_Msk (0x1ul << TIMER_PWMINTSTS1_BRKEIF1_Pos) /*!< TIMER_T::PWMINTSTS1: BRKEIF1 Mask */
#define TIMER_PWMINTSTS1_BRKLIF0_Pos (8) /*!< TIMER_T::PWMINTSTS1: BRKLIF0 Position */
#define TIMER_PWMINTSTS1_BRKLIF0_Msk (0x1ul << TIMER_PWMINTSTS1_BRKLIF0_Pos) /*!< TIMER_T::PWMINTSTS1: BRKLIF0 Mask */
#define TIMER_PWMINTSTS1_BRKLIF1_Pos (9) /*!< TIMER_T::PWMINTSTS1: BRKLIF1 Position */
#define TIMER_PWMINTSTS1_BRKLIF1_Msk (0x1ul << TIMER_PWMINTSTS1_BRKLIF1_Pos) /*!< TIMER_T::PWMINTSTS1: BRKLIF1 Mask */
#define TIMER_PWMINTSTS1_BRKESTS0_Pos (16) /*!< TIMER_T::PWMINTSTS1: BRKESTS0 Position */
#define TIMER_PWMINTSTS1_BRKESTS0_Msk (0x1ul << TIMER_PWMINTSTS1_BRKESTS0_Pos) /*!< TIMER_T::PWMINTSTS1: BRKESTS0 Mask */
#define TIMER_PWMINTSTS1_BRKESTS1_Pos (17) /*!< TIMER_T::PWMINTSTS1: BRKESTS1 Position */
#define TIMER_PWMINTSTS1_BRKESTS1_Msk (0x1ul << TIMER_PWMINTSTS1_BRKESTS1_Pos) /*!< TIMER_T::PWMINTSTS1: BRKESTS1 Mask */
#define TIMER_PWMINTSTS1_BRKLSTS0_Pos (24) /*!< TIMER_T::PWMINTSTS1: BRKLSTS0 Position */
#define TIMER_PWMINTSTS1_BRKLSTS0_Msk (0x1ul << TIMER_PWMINTSTS1_BRKLSTS0_Pos) /*!< TIMER_T::PWMINTSTS1: BRKLSTS0 Mask */
#define TIMER_PWMINTSTS1_BRKLSTS1_Pos (25) /*!< TIMER_T::PWMINTSTS1: BRKLSTS1 Position */
#define TIMER_PWMINTSTS1_BRKLSTS1_Msk (0x1ul << TIMER_PWMINTSTS1_BRKLSTS1_Pos) /*!< TIMER_T::PWMINTSTS1: BRKLSTS1 Mask */
#define TIMER_PWMEADCTS_TRGSEL_Pos (0) /*!< TIMER_T::PWMEADCTS: TRGSEL Position */
#define TIMER_PWMEADCTS_TRGSEL_Msk (0x7ul << TIMER_PWMEADCTS_TRGSEL_Pos) /*!< TIMER_T::PWMEADCTS: TRGSEL Mask */
#define TIMER_PWMEADCTS_TRGEN_Pos (7) /*!< TIMER_T::PWMEADCTS: TRGEN Position */
#define TIMER_PWMEADCTS_TRGEN_Msk (0x1ul << TIMER_PWMEADCTS_TRGEN_Pos) /*!< TIMER_T::PWMEADCTS: TRGEN Mask */
#define TIMER_PWMSCTL_SYNCMODE_Pos (0) /*!< TIMER_T::PWMSCTL: SYNCMODE Position */
#define TIMER_PWMSCTL_SYNCMODE_Msk (0x3ul << TIMER_PWMSCTL_SYNCMODE_Pos) /*!< TIMER_T::PWMSCTL: SYNCMODE Mask */
#define TIMER_PWMSCTL_SYNCSRC_Pos (8) /*!< TIMER_T::PWMSCTL: SYNCSRC Position */
#define TIMER_PWMSCTL_SYNCSRC_Msk (0x1ul << TIMER_PWMSCTL_SYNCSRC_Pos) /*!< TIMER_T::PWMSCTL: SYNCSRC Mask */
#define TIMER_PWMSTRG_STRGEN_Pos (0) /*!< TIMER_T::PWMSTRG: STRGEN Position */
#define TIMER_PWMSTRG_STRGEN_Msk (0x1ul << TIMER_PWMSTRG_STRGEN_Pos) /*!< TIMER_T::PWMSTRG: STRGEN Mask */
#define TIMER_PWMSTATUS_CNTMAXF_Pos (0) /*!< TIMER_T::PWMSTATUS: CNTMAXF Position */
#define TIMER_PWMSTATUS_CNTMAXF_Msk (0x1ul << TIMER_PWMSTATUS_CNTMAXF_Pos) /*!< TIMER_T::PWMSTATUS: CNTMAXF Mask */
#define TIMER_PWMSTATUS_EADCTRGF_Pos (16) /*!< TIMER_T::PWMSTATUS: EADCTRGF Position */
#define TIMER_PWMSTATUS_EADCTRGF_Msk (0x1ul << TIMER_PWMSTATUS_EADCTRGF_Pos) /*!< TIMER_T::PWMSTATUS: EADCTRGF Mask */
#define TIMER_PWMPBUF_PBUF_Pos (0) /*!< TIMER_T::PWMPBUF: PBUF Position */
#define TIMER_PWMPBUF_PBUF_Msk (0xfffful << TIMER_PWMPBUF_PBUF_Pos) /*!< TIMER_T::PWMPBUF: PBUF Mask */
#define TIMER_PWMCMPBUF_CMPBUF_Pos (0) /*!< TIMER_T::PWMCMPBUF: CMPBUF Position */
#define TIMER_PWMCMPBUF_CMPBUF_Msk (0xfffful << TIMER_PWMCMPBUF_CMPBUF_Pos) /*!< TIMER_T::PWMCMPBUF: CMPBUF Mask */
/**@}*/ /* TIMER_CONST */
/**@}*/ /* end of TIMER register group */
/*---------------------- Watch Dog Timer Controller -------------------------*/
/**
@addtogroup WDT Watch Dog Timer Controller(WDT)
Memory Mapped Structure for WDT Controller
@{ */
typedef struct {
/**
* @var WDT_T::CTL
* Offset: 0x00 WDT Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |RSTCNT |Reset WDT Up Counter (Write Protect)
* | | |0 = No effect.
* | | |1 = Reset the internal 18-bit WDT up counter value.
* | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
* | | |Note2: This bit will be automatically cleared by hardware.
* |[1] |RSTEN |WDT Time-out Reset Enable Control (Write Protect)
* | | |Setting this bit will enable the WDT time-out reset function If the WDT up counter value has not been cleared after the specific WDT reset delay period expires.
* | | |0 = WDT time-out reset function Disabled.
* | | |1 = WDT time-out reset function Enabled.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[2] |RSTF |WDT Time-out Reset Flag
* | | |This bit indicates the system has been reset by WDT time-out reset or not.
* | | |0 = WDT time-out reset did not occur.
* | | |1 = WDT time-out reset occurred.
* | | |Note: This bit is cleared by writing 1 to it.
* |[3] |IF |WDT Time-out Interrupt Flag
* | | |This bit will set to 1 while WDT up counter value reaches the selected WDT time-out interval
* | | |0 = WDT time-out interrupt did not occur.
* | | |1 = WDT time-out interrupt occurred.
* | | |Note: This bit is cleared by writing 1 to it.
* |[4] |WKEN |WDT Time-out Wake-up Function Control (Write Protect)
* | | |If this bit is set to 1, while WDT time-out interrupt flag IF (WDT_CTL[3]) is generated to 1 and interrupt enable bit INTEN (WDT_CTL[6]) is enabled, the WDT time-out interrupt signal will generate a wake-up trigger event to chip.
* | | |0 = Wake-up trigger event Disabled if WDT time-out interrupt signal generated.
* | | |1 = Wake-up trigger event Enabled if WDT time-out interrupt signal generated.
* | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
* | | |Note2: Chip can be woken-up by WDT time-out interrupt signal generated only if WDT clock source is selected to 10 kHz internal low speed RC oscillator (LIRC) or LXT.
* |[5] |WKF |WDT Time-out Wake-up Flag (Write Protect)
* | | |This bit indicates the interrupt wake-up flag status of WDT
* | | |0 = WDT does not cause chip wake-up.
* | | |1 = Chip wake-up from Idle or Power-down mode if WDT time-out interrupt signal generated.
* | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
* | | |Note2: This bit is cleared by writing 1 to it.
* |[6] |INTEN |WDT Time-out Interrupt Enable Control (Write Protect)
* | | |If this bit is enabled, the WDT time-out interrupt signal is generated and inform to CPU.
* | | |0 = WDT time-out interrupt Disabled.
* | | |1 = WDT time-out interrupt Enabled.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[7] |WDTEN |WDT Enable Control (Write Protect)
* | | |0 = WDT Disabled (This action will reset the internal up counter value).
* | | |1 = WDT Enabled.
* | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
* | | |Note2: If CWDTEN[2:0] (combined by Config0[31] and Config0[4:3]) bits is not configure to 111, this bit is forced as 1 and user cannot change this bit to 0.
* |[10:8] |TOUTSEL |WDT Time-out Interval Selection (Write Protect)
* | | |These three bits select the time-out interval period for the WDT.
* | | |000 = 24 * WDT_CLK.
* | | |001 = 26 * WDT_CLK.
* | | |010 = 28 * WDT_CLK.
* | | |011 = 210 * WDT_CLK.
* | | |100 = 212 * WDT_CLK.
* | | |101 = 214 * WDT_CLK.
* | | |110 = 216 * WDT_CLK.
* | | |111 = 218 * WDT_CLK.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[30] |SYNC |WDT Enable Control SYNC Flag Indicator (Read Only)
* | | |If user execute enable/disable WDTEN (WDT_CTL[7]), this flag can be indicated enable/disable WDTEN function is completed or not.
* | | |0 = Set WDTEN bit is completed.
* | | |1 = Set WDTEN bit is synchronizing and not become active yet..
* | | |Note: Perform enable or disable WDTEN bit needs 2 * WDT_CLK period to become active.
* |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Control (Write Protect)
* | | |0 = ICE debug mode acknowledgement affects WDT counting.
* | | |WDT up counter will be held while CPU is held by ICE.
* | | |1 = ICE debug mode acknowledgement Disabled.
* | | |WDT up counter will keep going no matter CPU is held by ICE or not.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* @var WDT_T::ALTCTL
* Offset: 0x04 WDT Alternative Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1:0] |RSTDSEL |WDT Reset Delay Selection (Write Protect)
* | | |When WDT time-out happened, user has a time named WDT Reset Delay Period to clear WDT counter by setting RSTCNT (WDT_CTL[0]) to prevent WDT time-out reset happened
* | | |User can select a suitable setting of RSTDSEL for different WDT Reset Delay Period.
* | | |00 = WDT Reset Delay Period is 1026 * WDT_CLK.
* | | |01 = WDT Reset Delay Period is 130 * WDT_CLK.
* | | |10 = WDT Reset Delay Period is 18 * WDT_CLK.
* | | |11 = WDT Reset Delay Period is 3 * WDT_CLK.
* | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
* | | |Note2: This register will be reset to 0 if WDT time-out reset happened.
* @var WDT_T::RSTCNT
* Offset: 0x08 WDT Reset Counter Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |RSTCNT |WDT Reset Counter Register
* | | |Writing 0x00005AA5 to this field will reset the internal 18-bit WDT up counter value to 0.
* | | |Note: Perform RSTCNT to reset counter needs 2 * WDT_CLK period to become active.
* | | |Note: RSTCNT (WDT_CTL[0]) bit is a write protected bit
* | | |RSTCNT (WDT_RSTCNT[31:0]) bits are not write protected.
*/
__IO uint32_t CTL; /*!< [0x0000] WDT Control Register */
__IO uint32_t ALTCTL; /*!< [0x0004] WDT Alternative Control Register */
__O uint32_t RSTCNT; /*!< [0x0008] WDT Reset Counter Register */
} WDT_T;
/**
@addtogroup WDT_CONST WDT Bit Field Definition
Constant Definitions for WDT Controller
@{ */
#define WDT_CTL_RSTCNT_Pos (0) /*!< WDT_T::CTL: RSTCNT Position */
#define WDT_CTL_RSTCNT_Msk (0x1ul << WDT_CTL_RSTCNT_Pos) /*!< WDT_T::CTL: RSTCNT Mask */
#define WDT_CTL_RSTEN_Pos (1) /*!< WDT_T::CTL: RSTEN Position */
#define WDT_CTL_RSTEN_Msk (0x1ul << WDT_CTL_RSTEN_Pos) /*!< WDT_T::CTL: RSTEN Mask */
#define WDT_CTL_RSTF_Pos (2) /*!< WDT_T::CTL: RSTF Position */
#define WDT_CTL_RSTF_Msk (0x1ul << WDT_CTL_RSTF_Pos) /*!< WDT_T::CTL: RSTF Mask */
#define WDT_CTL_IF_Pos (3) /*!< WDT_T::CTL: IF Position */
#define WDT_CTL_IF_Msk (0x1ul << WDT_CTL_IF_Pos) /*!< WDT_T::CTL: IF Mask */
#define WDT_CTL_WKEN_Pos (4) /*!< WDT_T::CTL: WKEN Position */
#define WDT_CTL_WKEN_Msk (0x1ul << WDT_CTL_WKEN_Pos) /*!< WDT_T::CTL: WKEN Mask */
#define WDT_CTL_WKF_Pos (5) /*!< WDT_T::CTL: WKF Position */
#define WDT_CTL_WKF_Msk (0x1ul << WDT_CTL_WKF_Pos) /*!< WDT_T::CTL: WKF Mask */
#define WDT_CTL_INTEN_Pos (6) /*!< WDT_T::CTL: INTEN Position */
#define WDT_CTL_INTEN_Msk (0x1ul << WDT_CTL_INTEN_Pos) /*!< WDT_T::CTL: INTEN Mask */
#define WDT_CTL_WDTEN_Pos (7) /*!< WDT_T::CTL: WDTEN Position */
#define WDT_CTL_WDTEN_Msk (0x1ul << WDT_CTL_WDTEN_Pos) /*!< WDT_T::CTL: WDTEN Mask */
#define WDT_CTL_TOUTSEL_Pos (8) /*!< WDT_T::CTL: TOUTSEL Position */
#define WDT_CTL_TOUTSEL_Msk (0x7ul << WDT_CTL_TOUTSEL_Pos) /*!< WDT_T::CTL: TOUTSEL Mask */
#define WDT_CTL_SYNC_Pos (30) /*!< WDT_T::CTL: SYNC Position */
#define WDT_CTL_SYNC_Msk (0x1ul << WDT_CTL_SYNC_Pos) /*!< WDT_T::CTL: SYNC Mask */
#define WDT_CTL_ICEDEBUG_Pos (31) /*!< WDT_T::CTL: ICEDEBUG Position */
#define WDT_CTL_ICEDEBUG_Msk (0x1ul << WDT_CTL_ICEDEBUG_Pos) /*!< WDT_T::CTL: ICEDEBUG Mask */
#define WDT_ALTCTL_RSTDSEL_Pos (0) /*!< WDT_T::ALTCTL: RSTDSEL Position */
#define WDT_ALTCTL_RSTDSEL_Msk (0x3ul << WDT_ALTCTL_RSTDSEL_Pos) /*!< WDT_T::ALTCTL: RSTDSEL Mask */
#define WDT_RSTCNT_RSTCNT_Pos (0) /*!< WDT_T::RSTCNT: RSTCNT Position */
#define WDT_RSTCNT_RSTCNT_Msk (0xfffffffful << WDT_RSTCNT_RSTCNT_Pos) /*!< WDT_T::RSTCNT: RSTCNT Mask */
/**@}*/ /* WDT_CONST */
/**@}*/ /* end of WDT register group */
/*---------------------- Window Watchdog Timer -------------------------*/
/**
@addtogroup WWDT Window Watchdog Timer(WWDT)
Memory Mapped Structure for WWDT Controller
@{ */
typedef struct {
/**
* @var WWDT_T::RLDCNT
* Offset: 0x00 WWDT Reload Counter Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |RLDCNT |WWDT Reload Counter Register
* | | |Writing 0x00005AA5 to this register will reload the WWDT counter value to 0x3F.
* | | |Note: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT (WWDT_CTL[21:16])
* | | |If user writes WWDT_RLDCNT when current WWDT counter value is larger than CMPDAT , WWDT reset signal will generate immediately.
* @var WWDT_T::CTL
* Offset: 0x04 WWDT Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |WWDTEN |WWDT Enable Control Bit
* | | |Set this bit to enable WWDT counter counting.
* | | |0 = WWDT counter is stopped.
* | | |1 = WWDT counter is starting counting.
* |[1] |INTEN |WWDT Interrupt Enable Control Bit
* | | |If this bit is enabled, the WWDT counter compare match interrupt signal is generated and inform to CPU.
* | | |0 = WWDT counter compare match interrupt Disabled.
* | | |1 = WWDT counter compare match interrupt Enabled.
* |[11:8] |PSCSEL |WWDT Counter Prescale Period Selection
* | | |0000 = Pre-scale is 1; Max time-out period is 1 * 64 * WWDT_CLK.
* | | |0001 = Pre-scale is 2; Max time-out period is 2 * 64 * WWDT_CLK.
* | | |0010 = Pre-scale is 4; Max time-out period is 4 * 64 * WWDT_CLK.
* | | |0011 = Pre-scale is 8; Max time-out period is 8 * 64 * WWDT_CLK.
* | | |0100 = Pre-scale is 16; Max time-out period is 16 * 64 * WWDT_CLK.
* | | |0101 = Pre-scale is 32; Max time-out period is 32 * 64 * WWDT_CLK.
* | | |0110 = Pre-scale is 64; Max time-out period is 64 * 64 * WWDT_CLK.
* | | |0111 = Pre-scale is 128; Max time-out period is 128 * 64 * WWDT_CLK.
* | | |1000 = Pre-scale is 192; Max time-out period is 192 * 64 * WWDT_CLK.
* | | |1001 = Pre-scale is 256; Max time-out period is 256 * 64 * WWDT_CLK.
* | | |1010 = Pre-scale is 384; Max time-out period is 384 * 64 * WWDT_CLK.
* | | |1011 = Pre-scale is 512; Max time-out period is 512 * 64 * WWDT_CLK.
* | | |1100 = Pre-scale is 768; Max time-out period is 768 * 64 * WWDT_CLK.
* | | |1101 = Pre-scale is 1024; Max time-out period is 1024 * 64 * WWDT_CLK.
* | | |1110 = Pre-scale is 1536; Max time-out period is 1536 * 64 * WWDT_CLK.
* | | |1111 = Pre-scale is 2048; Max time-out period is 2048 * 64 * WWDT_CLK.
* |[21:16] |CMPDAT |WWDT Window Compare Register
* | | |Set this register to adjust the valid reload window.
* | | |Note: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT
* | | |If user writes WWDT_RLDCNT register when current WWDT counter value larger than CMPDAT, WWDT reset signal will generate immediately.
* |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Control
* | | |0 = ICE debug mode acknowledgement effects WWDT counting.
* | | |WWDT down counter will be held while CPU is held by ICE.
* | | |1 = ICE debug mode acknowledgement Disabled.
* | | |WWDT down counter will keep going no matter CPU is held by ICE or not.
* @var WWDT_T::STATUS
* Offset: 0x08 WWDT Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |WWDTIF |WWDT Compare Match Interrupt Flag
* | | |This bit indicates the interrupt flag status of WWDT while WWDT counter value matches CMPDAT (WWDT_CTL[21:16]).
* | | |0 = No effect.
* | | |1 = WWDT counter value matches CMPDAT.
* | | |Note: This bit is cleared by writing 1 to it.
* |[1] |WWDTRF |WWDT Timer-out Reset Flag
* | | |This bit indicates the system has been reset by WWDT time-out reset or not.
* | | |0 = WWDT time-out reset did not occur.
* | | |1 = WWDT time-out reset occurred.
* | | |Note: This bit is cleared by writing 1 to it.
* @var WWDT_T::CNT
* Offset: 0x0C WWDT Counter Value Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[5:0] |CNTDAT |WWDT Counter Value
* | | |CNTDAT will be updated continuously to monitor 6-bit WWDT down counter value.
*/
__O uint32_t RLDCNT; /*!< [0x0000] WWDT Reload Counter Register */
__IO uint32_t CTL; /*!< [0x0004] WWDT Control Register */
__IO uint32_t STATUS; /*!< [0x0008] WWDT Status Register */
__I uint32_t CNT; /*!< [0x000c] WWDT Counter Value Register */
} WWDT_T;
/**
@addtogroup WWDT_CONST WWDT Bit Field Definition
Constant Definitions for WWDT Controller
@{ */
#define WWDT_RLDCNT_RLDCNT_Pos (0) /*!< WWDT_T::RLDCNT: RLDCNT Position */
#define WWDT_RLDCNT_RLDCNT_Msk (0xfffffffful << WWDT_RLDCNT_RLDCNT_Pos) /*!< WWDT_T::RLDCNT: RLDCNT Mask */
#define WWDT_CTL_WWDTEN_Pos (0) /*!< WWDT_T::CTL: WWDTEN Position */
#define WWDT_CTL_WWDTEN_Msk (0x1ul << WWDT_CTL_WWDTEN_Pos) /*!< WWDT_T::CTL: WWDTEN Mask */
#define WWDT_CTL_INTEN_Pos (1) /*!< WWDT_T::CTL: INTEN Position */
#define WWDT_CTL_INTEN_Msk (0x1ul << WWDT_CTL_INTEN_Pos) /*!< WWDT_T::CTL: INTEN Mask */
#define WWDT_CTL_PSCSEL_Pos (8) /*!< WWDT_T::CTL: PSCSEL Position */
#define WWDT_CTL_PSCSEL_Msk (0xful << WWDT_CTL_PSCSEL_Pos) /*!< WWDT_T::CTL: PSCSEL Mask */
#define WWDT_CTL_CMPDAT_Pos (16) /*!< WWDT_T::CTL: CMPDAT Position */
#define WWDT_CTL_CMPDAT_Msk (0x3ful << WWDT_CTL_CMPDAT_Pos) /*!< WWDT_T::CTL: CMPDAT Mask */
#define WWDT_CTL_ICEDEBUG_Pos (31) /*!< WWDT_T::CTL: ICEDEBUG Position */
#define WWDT_CTL_ICEDEBUG_Msk (0x1ul << WWDT_CTL_ICEDEBUG_Pos) /*!< WWDT_T::CTL: ICEDEBUG Mask */
#define WWDT_STATUS_WWDTIF_Pos (0) /*!< WWDT_T::STATUS: WWDTIF Position */
#define WWDT_STATUS_WWDTIF_Msk (0x1ul << WWDT_STATUS_WWDTIF_Pos) /*!< WWDT_T::STATUS: WWDTIF Mask */
#define WWDT_STATUS_WWDTRF_Pos (1) /*!< WWDT_T::STATUS: WWDTRF Position */
#define WWDT_STATUS_WWDTRF_Msk (0x1ul << WWDT_STATUS_WWDTRF_Pos) /*!< WWDT_T::STATUS: WWDTRF Mask */
#define WWDT_CNT_CNTDAT_Pos (0) /*!< WWDT_T::CNT: CNTDAT Position */
#define WWDT_CNT_CNTDAT_Msk (0x3ful << WWDT_CNT_CNTDAT_Pos) /*!< WWDT_T::CNT: CNTDAT Mask */
/**@}*/ /* WWDT_CONST */
/**@}*/ /* end of WWDT register group */
/*---------------------- Real Time Clock Controller -------------------------*/
/**
@addtogroup RTC Real Time Clock Controller(RTC)
Memory Mapped Structure for RTC Controller
@{ */
typedef struct {
/**
* @var RTC_T::INIT
* Offset: 0x00 RTC Initiation Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |INIT_ACTIVE|RTC Active Status (Read Only)
* | | |0 = RTC is at reset state.
* | | |1 = RTC is at normal active state.
* |[31:1] |INIT |RTC Initiation (Write Only)
* | | |When RTC block is powered on, RTC is at reset state
* | | |User has to write a number (0xa5eb1357) to INIT to make RTC leaving reset state
* | | |Once the INIT is written as 0xa5eb1357, the RTC will be in un-reset state permanently.
* | | |The INIT is a write-only field and read value will be always 0.
* @var RTC_T::RWEN
* Offset: 0x04 RTC Access Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[16] |RWENF |RTC Register Access Enable Flag (Read Only)
* | | |0 = RTC register read/write Disabled.
* | | |1 = RTC register read/write Enabled.
* | | |Note: RWENF will be mask to 0 during RTCBUSY is 1, and first turn on RTCCKEN (CLK_APBCLK[1]) also.
* |[24] |RTCBUSY |RTC Write Busy Flag
* | | |This bit indicates RTC registers are writable or not.
* | | |0: RTC registers are writable.
* | | |1: RTC registers can't write, RTC under Busy Status.
* | | |Note: RTCBUSY flag will be set when execute write RTC register command exceed 6 times within 1120 PCLK cycles.
* @var RTC_T::FREQADJ
* Offset: 0x08 RTC Frequency Compensation Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[21:0] |FREQADJ |Frequency Compensation Register
* | | |User must to get actual LXT frequency for RTC application.
* | | |FCR = 0x200000 * (32768 / LXT frequency).
* | | |Note: This formula is suitable only when RTC clock source is from LXT, RTCSEL (CLK_CLKSEL3[8]) is 0.
* @var RTC_T::TIME
* Offset: 0x0C RTC Time Loading Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |SEC |1-Sec Time Digit (0~9)
* |[6:4] |TENSEC |10-Sec Time Digit (0~5)
* |[11:8] |MIN |1-Min Time Digit (0~9)
* |[14:12] |TENMIN |10-Min Time Digit (0~5)
* |[19:16] |HR |1-Hour Time Digit (0~9)
* |[21:20] |TENHR |10-Hour Time Digit (0~2)
* | | |When RTC runs as 12-hour time scale mode, RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication
* | | |(If RTC_TIME[21] is 1, it indicates PM time message).
* @var RTC_T::CAL
* Offset: 0x10 RTC Calendar Loading Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |DAY |1-Day Calendar Digit (0~9)
* |[5:4] |TENDAY |10-Day Calendar Digit (0~3)
* |[11:8] |MON |1-Month Calendar Digit (0~9)
* |[12] |TENMON |10-Month Calendar Digit (0~1)
* |[19:16] |YEAR |1-Year Calendar Digit (0~9)
* |[23:20] |TENYEAR |10-Year Calendar Digit (0~9)
* @var RTC_T::CLKFMT
* Offset: 0x14 RTC Time Scale Selection Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |24HEN |24-hour / 12-hour Time Scale Selection
* | | |Indicates that RTC_TIME and RTC_TALM are in 24-hour time scale or 12-hour time scale
* | | |0 = 12-hour time scale with AM and PM indication selected.
* | | |1 = 24-hour time scale selected.
* @var RTC_T::WEEKDAY
* Offset: 0x18 RTC Day of the Week Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[2:0] |WEEKDAY |Day of the Week Register
* | | |000 = Sunday.
* | | |001 = Monday.
* | | |010 = Tuesday.
* | | |011 = Wednesday.
* | | |100 = Thursday.
* | | |101 = Friday.
* | | |110 = Saturday.
* | | |111 = Reserved.
* @var RTC_T::TALM
* Offset: 0x1C RTC Time Alarm Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |SEC |1-Sec Time Digit of Alarm Setting (0~9)
* |[6:4] |TENSEC |10-Sec Time Digit of Alarm Setting (0~5)
* |[11:8] |MIN |1-Min Time Digit of Alarm Setting (0~9)
* |[14:12] |TENMIN |10-Min Time Digit of Alarm Setting (0~5)
* |[19:16] |HR |1-Hour Time Digit of Alarm Setting (0~9)
* |[21:20] |TENHR |10-Hour Time Digit of Alarm Setting (0~2)
* | | |When RTC runs as 12-hour time scale mode, RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication
* | | |(If RTC_TIME[21] is 1, it indicates PM time message).
* @var RTC_T::CALM
* Offset: 0x20 RTC Calendar Alarm Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |DAY |1-Day Calendar Digit of Alarm Setting (0~9)
* |[5:4] |TENDAY |10-Day Calendar Digit of Alarm Setting (0~3)
* |[11:8] |MON |1-Month Calendar Digit of Alarm Setting (0~9)
* |[12] |TENMON |10-Month Calendar Digit of Alarm Setting (0~1)
* |[19:16] |YEAR |1-Year Calendar Digit of Alarm Setting (0~9)
* |[23:20] |TENYEAR |10-Year Calendar Digit of Alarm Setting (0~9)
* @var RTC_T::LEAPYEAR
* Offset: 0x24 RTC Leap Year Indicator Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |LEAPYEAR |Leap Year Indication Register (Read Only)
* | | |0 = This year is not a leap year.
* | | |1 = This year is leap year.
* @var RTC_T::INTEN
* Offset: 0x28 RTC Interrupt Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ALMIEN |Alarm Interrupt Enable Bit
* | | |Set ALMIEN to 1 can also enable chip wake-up function when RTC alarm interrupt event is generated.
* | | |0 = RTC Alarm interrupt Disabled.
* | | |1 = RTC Alarm interrupt Enabled.
* |[1] |TICKIEN |Time Tick Interrupt Enable Bit
* | | |Set TICKIEN to 1 can also enable chip wake-up function when RTC tick interrupt event is generated.
* | | |0 = RTC Time Tick interrupt Disabled.
* | | |1 = RTC Time Tick interrupt Enabled.
* |[8] |TAMP0IEN |Tamper 0 Interrupt Enable Bit
* | | |Set TAMP0IEN to 1 can also enable chip wake-up function when tamper 0 interrupt event is generated.
* | | |0 = Tamper 0 interrupt Disabled.
* | | |1 = Tamper 0 interrupt Enabled.
* |[9] |TAMP1IEN |Tamper 1 or Pair 0 Interrupt Enable Bit
* | | |Set TAMP1IEN to 1 can also enable chip wake-up function when tamper 1 interrupt event is generated.
* | | |0 = Tamper 1 or Pair 0 interrupt Disabled.
* | | |1 = Tamper 1 or Pair 0 interrupt Enabled.
* |[10] |TAMP2IEN |Tamper 2 Interrupt Enable Bit
* | | |Set TAMP2IEN to 1 can also enable chip wake-up function when tamper 2 interrupt event is generated.
* | | |0 = Tamper 2 interrupt Disabled.
* | | |1 = Tamper 2 interrupt Enabled.
* |[11] |TAMP3IEN |Tamper 3 or Pair 1 Interrupt Enable Bit
* | | |Set TAMP3IEN to 1 can also enable chip wake-up function when tamper 3 interrupt event is generated.
* | | |0 = Tamper 3 or Pair 1 interrupt Disabled.
* | | |1 = Tamper 3 or Pair 1 interrupt Enabled.
* |[12] |TAMP4IEN |Tamper 4 Interrupt Enable Bit
* | | |Set TAMP4IEN to 1 can also enable chip wake-up function when tamper 4 interrupt event is generated.
* | | |0 = Tamper 4 interrupt Disabled.
* | | |1 = Tamper 4 interrupt Enabled.
* |[13] |TAMP5IEN |Tamper 5 or Pair 2 Interrupt Enable Bit
* | | |Set TAMP5IEN to 1 can also enable chip wake-up function when tamper 5 interrupt event is generated.
* | | |0 = Tamper 5 or Pair 2 interrupt Disabled.
* | | |1 = Tamper 5 or Pair 2 interrupt Enabled.
* @var RTC_T::INTSTS
* Offset: 0x2C RTC Interrupt Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ALMIF |RTC Alarm Interrupt Flag
* | | |0 = Alarm condition is not matched.
* | | |1 = Alarm condition is matched.
* | | |Note: Write 1 to clear this bit.
* |[1] |TICKIF |RTC Time Tick Interrupt Flag
* | | |0 = Tick condition does not occur.
* | | |1 = Tick condition occur.
* | | |Note: Write 1 to clear this bit.
* |[8] |TAMP0IF |Tamper 0 Interrupt Flag
* | | |This bit is set when TAMP0_PIN detected level non-equal TAMP0LV (RTC_TAMPCTL[9]).
* | | |0 = No Tamper 0 interrupt flag is generated.
* | | |1 = Tamper 0 interrupt flag is generated.
* | | |Note1: Write 1 to clear this bit.
* | | |Note2: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically.
* |[9] |TAMP1IF |Tamper 1 or Pair 0 Interrupt Flag
* | | |This bit is set when TAMP1_PIN detected level non-equal TAMP1LV (RTC_TAMPCTL[13])
* | | |or TAMP0_PIN and TAMP1_PIN disconnected during DYNPR0EN (RTC_TAMPCTL[15]) is activated.
* | | |0 = No Tamper 1 or Pair 0 interrupt flag is generated.
* | | |1 = Tamper 1 or Pair 0 interrupt flag is generated.
* | | |Note1: Write 1 to clear this bit.
* | | |Note2: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically.
* |[10] |TAMP2IF |Tamper 2 Interrupt Flag
* | | |This bit is set when TAMP2_PIN detected level non-equal TAMP2LV (RTC_TAMPCTL[17]).
* | | |0 = No Tamper 2 interrupt flag is generated.
* | | |1 = Tamper 2 interrupt flag is generated.
* | | |Note1: Write 1 to clear this bit.
* | | |Note2: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically.
* |[11] |TAMP3IF |Tamper 3 or Pair 1 Interrupt Flag
* | | |This bit is set when TAMP3_PIN detected level non-equal TAMP3LV (RTC_TAMPCTL[21])
* | | |or TAMP2_PIN and TAMP3_PIN disconnected during DYNPR1EN (RTC_TAMPCTL[23]) is activated
* | | |or TAMP0_PIN and TAMP3_PIN disconnected during DYNPR1EN (RTC_TAMPCTL[23]) and DYN1ISS (RTC_TAMPCTL[0]) are activated.
* | | |0 = No Tamper 3 or Pair 1 interrupt flag is generated.
* | | |1 = Tamper 3 or Pair 1 interrupt flag is generated.
* | | |Note1: Write 1 to clear this bit.
* | | |Note2: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically.
* |[12] |TAMP4IF |Tamper 4 Interrupt Flag
* | | |This bit is set when TAMP4_PIN detected level non-equal TAMP4LV (RTC_TAMPCTL[25]).
* | | |0 = No Tamper 4 interrupt flag is generated.
* | | |1 = Tamper 4 interrupt flag is generated.
* | | |Note1: Write 1 to clear this bit.
* | | |Note2: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically.
* |[13] |TAMP5IF |Tamper 5 or Pair 2 Interrupt Flag
* | | |This bit is set when TAMP5_PIN detected level non-equal TAMP5LV (RTC_TAMPCTL[29])
* | | |or TAMP4_PIN and TAMP5_PIN disconnected during DYNPR2EN (RTC_TAMPCTL[31]) is activated
* | | |or TAMP0_PIN and TAMP5_PIN disconnected during DYNPR2EN (RTC_TAMPCTL[31]) and DYN2ISS (RTC_TAMPCTL[1]) are activated.
* | | |0 = No Tamper 5 or Pair 2 interrupt flag is generated.
* | | |1 = Tamper 5 or Pair 2 interrupt flag is generated.
* | | |Note1: Write 1 to clear this bit.
* | | |Note2: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically.
* @var RTC_T::TICK
* Offset: 0x30 RTC Time Tick Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[2:0] |TICK |Time Tick Register
* | | |These bits are used to select RTC time tick period for Periodic Time Tick Interrupt request.
* | | |000 = Time tick is 1 second.
* | | |001 = Time tick is 1/2 second.
* | | |010 = Time tick is 1/4 second.
* | | |011 = Time tick is 1/8 second.
* | | |100 = Time tick is 1/16 second.
* | | |101 = Time tick is 1/32 second.
* | | |110 = Time tick is 1/64 second.
* | | |111 = Time tick is 1/128 second.
* | | |Note: This register can be read back after the RTC register access enable bit RWENF (RTC_RWEN[16]) is active.
* @var RTC_T::TAMSK
* Offset: 0x34 RTC Time Alarm Mask Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |MSEC |Mask 1-Sec Time Digit of Alarm Setting (0~9)
* |[1] |MTENSEC |Mask 10-Sec Time Digit of Alarm Setting (0~5)
* |[2] |MMIN |Mask 1-Min Time Digit of Alarm Setting (0~9)
* |[3] |MTENMIN |Mask 10-Min Time Digit of Alarm Setting (0~5)
* |[4] |MHR |Mask 1-Hour Time Digit of Alarm Setting (0~9)
* |[5] |MTENHR |Mask 10-Hour Time Digit of Alarm Setting (0~2)
* @var RTC_T::CAMSK
* Offset: 0x38 RTC Calendar Alarm Mask Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |MDAY |Mask 1-Day Calendar Digit of Alarm Setting (0~9)
* |[1] |MTENDAY |Mask 10-Day Calendar Digit of Alarm Setting (0~3)
* |[2] |MMON |Mask 1-Month Calendar Digit of Alarm Setting (0~9)
* |[3] |MTENMON |Mask 10-Month Calendar Digit of Alarm Setting (0~1)
* |[4] |MYEAR |Mask 1-Year Calendar Digit of Alarm Setting (0~9)
* |[5] |MTENYEAR |Mask 10-Year Calendar Digit of Alarm Setting (0~9)
* @var RTC_T::SPRCTL
* Offset: 0x3C RTC Spare Functional Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[2] |SPRRWEN |Spare Register Enable Bit
* | | |0 = Spare register is Disabled.
* | | |1 = Spare register is Enabled.
* | | |Note: When spare register is disabled, RTC_SPR0 ~ RTC_SPR19 cannot be accessed.
* |[5] |SPRCSTS |SPR Clear Flag
* | | |This bit indicates if the RTC_SPR0 ~RTC_SPR19 content is cleared when specify tamper event is detected.
* | | |0 = Spare register content is not cleared.
* | | |1 = Spare register content is cleared.
* | | |Writes 1 to clear this bit.
* | | |Note: This bit keep 1 when RTC_INTSTS[13:8] not equal zero.
* @var RTC_T::SPR[20]
* Offset: 0x40 ~ 0x8C RTC Spare Register 0 ~ 19
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |SPARE |Spare Register
* | | |This field is used to store back-up information defined by user.
* | | |This field will be cleared by hardware automatically once a tamper pin event is detected.
* | | |Before storing back-up information in to RTC_SPRx register,
* | | |user should check REWNF (RTC_RWEN[16]) is enabled.
* @var RTC_T::LXTCTL
* Offset: 0x100 RTC 32.768 kHz Oscillator Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[2:1] |GAIN |Oscillator Gain Option
* | | |User can select oscillator gain according to crystal external loading and operating temperature range
* | | |The larger gain value corresponding to stronger driving capability and higher power consumption.
* | | |00 = L0 mode.
* | | |01 = L1 mode.
* | | |10 = L2 mode.
* | | |11 = L3 mode.
* @var RTC_T::GPIOCTL0
* Offset: 0x104 RTC GPIO Control 0 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1:0] |OPMODE0 |IO Operation Mode
* | | |00 = PF.4 is input only mode, without pull-up resistor.
* | | |01 = PF.4 is output push pull mode.
* | | |10 = PF.4 is open drain mode.
* | | |11 = PF.4 is quasi-bidirectional mode with internal pull up.
* |[2] |DOUT0 |IO Output Data
* | | |0 = PF.4 output low.
* | | |1 = PF.4 output high.
* |[3] |CTLSEL0 |IO Pin State Backup Selection
* | | |When low speed 32 kHz oscillator is disabled, PF.4 pin (X32KO pin) can be used as GPIO function
* | | |User can program CTLSEL0 to decide PF.4 I/O function is controlled by system power domain GPIO module or
* | | |VBAT power domain RTC_GPIOCTL0 control register.
* | | |0 = PF.4 pin I/O function is controlled by GPIO module.
* | | |Hardware auto becomes CTLSEL0 = 1 when system power is turned off.
* | | |1 = PF.4 pin I/O function is controlled by VBAT power domain.
* | | |PF.4 pin function and I/O status are controlled by OPMODE0[1:0] and DOUT0 after CTLSEL0 is set to 1.
* | | |Note: CTLSEL0 will automatically be set by hardware to 1 when system power is off and INIT[0] (RTC_INIT[0]) is 1.
* |[5:4] |PUSEL0 |IO Pull-up and Pull-down Enable
* | | |Determine PF.4 I/O pull-up or pull-down.
* | | |00 = PF.4 pull-up and pull-up disable.
* | | |01 = PF.4 pull-down enable.
* | | |10 = PF.4 pull-up enable.
* | | |11 = PF.4 pull-up and pull-up disable.
* | | |Note:
* | | |Basically, the pull-up control and pull-down control has following behavior limitation.
* | | |The independent pull-up control register only valid when OPMODE0 set as input tri-state and open-drain mode.
* | | |The independent pull-down control register only valid when OPMODE0 set as input tri-state mode.
* |[9:8] |OPMODE1 |IO Operation Mode
* | | |00 = PF.5 is input only mode, without pull-up resistor.
* | | |01 = PF.5 is output push pull mode.
* | | |10 = PF.5 is open drain mode.
* | | |11 = PF.5 is quasi-bidirectional mode with internal pull up.
* |[10] |DOUT1 |IO Output Data
* | | |0 = PF.5 output low.
* | | |1 = PF.5 output high.
* |[11] |CTLSEL1 |IO Pin State Backup Selection
* | | |When low speed 32 kHz oscillator is disabled, PF.5 pin (X32KI pin) can be used as GPIO function
* | | |User can program CTLSEL1 to decide PF.5 I/O function is controlled by system power domain GPIO module or
* | | |VBAT power domain RTC_GPIOCTL0 control register.
* | | |0 = PF.5 pin I/O function is controlled by GPIO module.
* | | |Hardware auto becomes CTLSEL1 = 1 when system power is turned off.
* | | |1 = PF.5 pin I/O function is controlled by VBAT power domain.
* | | |PF.5 pin function and I/O status are controlled by OPMODE1[1:0] and DOUT1 after CTLSEL1 is set to 1.
* | | |Note: CTLSEL1 will automatically be set by hardware to 1 when system power is off and INIT[0] (RTC_INIT[0]) is 1.
* |[13:12] |PUSEL1 |IO Pull-up and Pull-down Enable
* | | |Determine PF.5 I/O pull-up or pull-down.
* | | |00 = PF.5 pull-up and pull-up disable.
* | | |01 = PF.5 pull-down enable.
* | | |10 = PF.5 pull-up enable.
* | | |11 = PF.5 pull-up and pull-up disable.
* | | |Note:
* | | |Basically, the pull-up control and pull-down control has following behavior limitation.
* | | |The independent pull-up control register only valid when OPMODE1 set as input tri-state and open-drain mode.
* | | |The independent pull-down control register only valid when OPMODE1 set as input tri-state mode.
* |[17:16] |OPMODE2 |IO Operation Mode
* | | |00 = PF.6 is input only mode, without pull-up resistor.
* | | |01 = PF.6 is output push pull mode.
* | | |10 = PF.6 is open drain mode.
* | | |11 = PF.6 is quasi-bidirectional mode with internal pull up.
* |[18] |DOUT2 |IO Output Data
* | | |0 = PF.6 output low.
* | | |1 = PF.6 output high.
* |[19] |CTLSEL2 |IO Pin State Backup Selection
* | | |When TAMP0EN is disabled, PF.6 pin (TAMPER0 pin) can be used as GPIO function
* | | |User can program CTLSEL2 to decide PF.6 I/O function is controlled by system power domain GPIO module or
* | | |VBAT power domain RTC_GPIOCTL0 control register.
* | | |0 = PF.6 pin I/O function is controlled by GPIO module.
* | | |Hardware auto becomes CTLSEL2 = 1 when system power is turned off.
* | | |1 = PF.6 pin I/O function is controlled by VBAT power domain.
* | | |PF.6 pin function and I/O status are controlled by OPMODE2[1:0] and DOUT2 after CTLSEL2 is set to 1.
* | | |Note: CTLSEL2 will automatically be set by hardware to 1 when system power is off and INIT[0] (RTC_INIT[0]) is 1.
* |[21:20] |PUSEL2 |IO Pull-up and Pull-down Enable
* | | |Determine PF.6 I/O pull-up or pull-down.
* | | |00 = PF.6 pull-up and pull-up disable.
* | | |01 = PF.6 pull-down enable.
* | | |10 = PF.6 pull-up enable.
* | | |11 = PF.6 pull-up and pull-up disable.
* | | |Note1:
* | | |Basically, the pull-up control and pull-down control has following behavior limitation.
* | | |The independent pull-up control register only valid when OPMODE2 set as input tri-state and open-drain mode.
* | | |The independent pull-down control register only valid when OPMODE2 set as input tri-state mode.
* |[25:24] |OPMODE3 |IO Operation Mode
* | | |00 = PF.7 is input only mode, without pull-up resistor.
* | | |01 = PF.7 is output push pull mode.
* | | |10 = PF.7 is open drain mode.
* | | |11 = PF.7 is quasi-bidirectional mode.
* |[26] |DOUT3 |IO Output Data
* | | |0 = PF.7 output low.
* | | |1 = PF.7 output high.
* |[27] |CTLSEL3 |IO Pin State Backup Selection
* | | |When TAMP1EN is disabled, PF.7 pin (TAMPER1 pin) can be used as GPIO function
* | | |User can program CTLSEL3 to decide PF.7 I/O function is controlled by system power domain GPIO module or
* | | |VBAT power domain RTC_GPIOCTL0 control register.
* | | |0 = PF.7 pin I/O function is controlled by GPIO module.
* | | |Hardware auto becomes CTLSEL3 = 1 when system power is turned off.
* | | |1 = PF.7 pin I/O function is controlled by VBAT power domain.
* | | |PF.7 pin function and I/O status are controlled by OPMODE3[1:0] and DOUT3 after CTLSEL3 is set to 1.
* | | |Note: CTLSEL3 will automatically be set by hardware to 1 when system power is off and RTC_INIT[0] (RTC Active Status) is 1.
* |[29:28] |PUSEL3 |IO Pull-up and Pull-down Enable
* | | |Determine PF.7 I/O pull-up or pull-down.
* | | |00 = PF.7 pull-up and pull-down disable.
* | | |01 = PF.7 pull-down enable.
* | | |10 = PF.7 pull-up enable.
* | | |11 = PF.7 pull-up and pull-down disable.
* | | |Note:
* | | |Basically, the pull-up control and pull-down control has following behavior limitation.
* | | |The independent pull-up control register only valid when OPMODE3 set as input tri-state and open-drain mode.
* | | |The independent pull-down control register only valid when OPMODE3 set as input tri-state mode.
* @var RTC_T::GPIOCTL1
* Offset: 0x108 RTC GPIO Control 1 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1:0] |OPMODE4 |IO Operation Mode
* | | |00 = PF.8 is input only mode, without pull-up resistor.
* | | |01 = PF.8 is output push pull mode.
* | | |10 = PF.8 is open drain mode.
* | | |11 = PF.8 is quasi-bidirectional mode.
* |[2] |DOUT4 |IO Output Data
* | | |0 = PF.8 output low.
* | | |1 = PF.8 output high.
* |[3] |CTLSEL4 |IO Pin State Backup Selection
* | | |When TAMP2EN is disabled, PF.8 pin (TAMPER2 pin) can be used as GPIO function
* | | |User can program CTLSEL4 to decide PF.8 I/O function is controlled by system power domain GPIO module or
* | | |VBAT power domain RTC_GPIOCTL1 control register.
* | | |0 = PF.8 pin I/O function is controlled by GPIO module.
* | | |Hardware auto becomes CTLSEL4 = 1 when system power is turned off.
* | | |1 = PF.8 pin I/O function is controlled by VBAT power domain.
* | | |PF.8 pin function and I/O status are controlled by OPMODE4[1:0] and DOUT4 after CTLSEL4 is set to 1.
* | | |Note: CTLSEL4 will automatically be set by hardware to 1 when system power is off and RTC_INIT[0] (RTC Active Status) is 1.
* |[5:4] |PUSEL4 |IO Pull-up and Pull-down Enable
* | | |Determine PF.8 I/O pull-up or pull-down.
* | | |00 = PF.8 pull-up and pull-down disable.
* | | |01 = PF.8 pull-down enable.
* | | |10 = PF.8 pull-up enable.
* | | |11 = PF.8 pull-up and pull-down disable.
* | | |Note:
* | | |Basically, the pull-up control and pull-down control has following behavior limitation.
* | | |The independent pull-up control register only valid when OPMODE4 set as input tri-state and open-drain mode.
* | | |The independent pull-down control register only valid when OPMODE4 set as input tri-state mode.
* |[9:8] |OPMODE5 |IO Operation Mode
* | | |00 = PF.9 is input only mode, without pull-up resistor.
* | | |01 = PF.9 is output push pull mode.
* | | |10 = PF.9 is open drain mode.
* | | |11 = PF.9 is quasi-bidirectional mode.
* |[10] |DOUT5 |IO Output Data
* | | |0 = PF.9 output low.
* | | |1 = PF.9 output high.
* |[11] |CTLSEL5 |IO Pin State Backup Selection
* | | |When TAMP3EN is disabled, PF.9 pin (TAMPER3 pin) can be used as GPIO function
* | | |User can program CTLSEL5 to decide PF.9 I/O function is controlled by system power domain GPIO module or
* | | |VBAT power domain RTC_GPIOCTL1 control register.
* | | |0 = PF.9 pin I/O function is controlled by GPIO module.
* | | |Hardware auto becomes CTLSEL5 = 1 when system power is turned off.
* | | |1 = PF.9 pin I/O function is controlled by VBAT power domain.
* | | |PF.9 pin function and I/O status are controlled by OPMODE5[1:0] and DOUT5 after CTLSEL5 is set to 1.
* | | |Note: CTLSEL5 will automatically be set by hardware to 1 when system power is off and INIT[0] (RTC_INIT[0]) is 1.
* |[13:12] |PUSEL5 |IO Pull-up and Pull-down Enable
* | | |Determine PF.9 I/O pull-up or pull-down.
* | | |00 = PF.9 pull-up and pull-down disable.
* | | |01 = PF.9 pull-down enable.
* | | |10 = PF.9 pull-up enable.
* | | |11 = PF.9 pull-up and pull-down disable.
* | | |Note:
* | | |Basically, the pull-up control and pull-down control has following behavior limitation.
* | | |The independent pull-up control register only valid when OPMODE5 set as input tri-state and open-drain mode.
* | | |The independent pull-down control register only valid when OPMODE5 set as input tri-state mode.
* |[17:16] |OPMODE6 |IO Operation Mode
* | | |00 = PF.10 is input only mode, without pull-up resistor.
* | | |01 = PF.10 is output push pull mode.
* | | |10 = PF.10 is open drain mode.
* | | |11 = PF.10 is quasi-bidirectional mode.
* |[18] |DOUT6 |IO Output Data
* | | |0 = PF.10 output low.
* | | |1 = PF.10 output high.
* |[19] |CTLSEL6 |IO Pin State Backup Selection
* | | |When TAMP4EN is disabled, PF.10 pin (TAMPER4 pin) can be used as GPIO function
* | | |User can program CTLSEL6 to decide PF.10 I/O function is controlled by system power domain GPIO module or
* | | |VBAT power domain RTC_GPIOCTL1 control register.
* | | |0 = PF.10 pin I/O function is controlled by GPIO module.
* | | |Hardware auto becomes CTLSEL6 = 1 when system power is turned off.
* | | |1 = PF.10 pin I/O function is controlled by VBAT power domain.
* | | |PF.10 pin function and I/O status are controlled by OPMODE6[1:0] and DOUT6 after CTLSEL6 is set to 1.
* | | |Note: CTLSEL6 will automatically be set by hardware to 1 when system power is off and INIT[0] (RTC_INIT[0]) is 1.
* |[21:20] |PUSEL6 |IO Pull-up and Pull-down Enable
* | | |Determine PF.10 I/O pull-up or pull-down.
* | | |00 = PF.10 pull-up and pull-down disable.
* | | |01 = PF.10 pull-down enable.
* | | |10 = PF.10 pull-up enable.
* | | |11 = PF.10 pull-up and pull-down disable.
* | | |Note:
* | | |Basically, the pull-up control and pull-down control has following behavior limitation.
* | | |The independent pull-up control register only valid when OPMODE6 set as input tri-state and open-drain mode.
* | | |The independent pull-down control register only valid when OPMODE6 set as input tri-state mode.
* |[25:24] |OPMODE7 |IO Operation Mode
* | | |00 = PF.11 is input only mode, without pull-up resistor.
* | | |01 = PF.11 is output push pull mode.
* | | |10 = PF.11 is open drain mode.
* | | |11 = PF.11 is quasi-bidirectional mode.
* |[26] |DOUT7 |IO Output Data
* | | |0 = PF.11 output low.
* | | |1 = PF.11 output high.
* |[27] |CTLSEL7 |IO Pin State Backup Selection
* | | |When TAMP5EN is disabled, PF.11 pin (TAMPER5 pin) can be used as GPIO function
* | | |User can program CTLSEL7 to decide PF.11 I/O function is controlled by system power domain GPIO module or
* | | |VBAT power domain RTC_GPIOCTL1 control register.
* | | |0 = PF.11 pin I/O function is controlled by GPIO module.
* | | |Hardware auto becomes CTLSEL7 = 1 when system power is turned off.
* | | |1 = PF.11 pin I/O function is controlled by VBAT power domain.
* | | |PF.11 pin function and I/O status are controlled by OPMODE7[1:0] and DOUT7 after CTLSEL7 is set to 1.
* | | |Note: CTLSEL7 will automatically be set by hardware to 1 when system power is off and INIT[0] (RTC_INIT[0]) is 1.
* |[29:28] |PUSEL7 |IO Pull-up and Pull-down Enable
* | | |Determine PF.11 I/O pull-up or pull-down.
* | | |00 = PF.11 pull-up and pull-down disable.
* | | |01 = PF.11 pull-down enable.
* | | |10 = PF.11 pull-up enable.
* | | |11 = PF.11 pull-up and pull-down disable.
* | | |Note:
* | | |Basically, the pull-up control and pull-down control has following behavior limitation.
* | | |The independent pull-up control register only valid when OPMODE7 set as input tri-state and open-drain mode.
* | | |The independent pull-down control register only valid when OPMODE7 set as input tri-state mode.
* @var RTC_T::DSTCTL
* Offset: 0x110 RTC Daylight Saving Time Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ADDHR |Add 1 Hour
* | | |0 = No effect.
* | | |1 = Indicates RTC hour digit has been added one hour for summer time change.
* |[1] |SUBHR |Subtract 1 Hour
* | | |0 = No effect.
* | | |1 = Indicates RTC hour digit has been subtracted one hour for winter time change.
* |[2] |DSBAK |Daylight Saving Back
* | | |0= Normal mode.
* | | |1= Daylight saving mode.
* @var RTC_T::TAMPCTL
* Offset: 0x120 RTC Tamper Pin Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |DYN1ISS |Dynamic Pair 1 Input Source Select
* | | |This bit determine Tamper 3 input is from Tamper 2 or Tamper 0 in dynamic mode.
* | | |0 = Tamper input is from Tamper 2.
* | | |1 = Tamper input is from Tamper 0.
* | | |Note: This bit has effect only when DYNPR1EN (RTC_TAMPCTL[16]) and DYNPR0EN (RTC_TAMPCTL[15]) are set
* |[1] |DYN2ISS |Dynamic Pair 2 Input Source Select
* | | |This bit determine Tamper 5 input is from Tamper 4 or Tamper 0 in dynamic mode.
* | | |0 = Tamper input is from Tamper 4.
* | | |1 = Tamper input is from Tamper 0.
* | | |Note: This bit has effect only when DYNPR2EN (RTC_TAMPCTL[24]) and DYNPR0EN (RTC_TAMPCTL[15]) are set
* |[3:2] |DYNSRC |Dynamic Reference Pattern
* | | |This fields determine the new reference pattern when current pattern run out in dynamic pair mode.
* | | |00 or 10 = The new reference pattern is generated by random number generator when the reference pattern run out.
* | | |01 = The new reference pattern is repeated previous random value when the reference pattern run out.
* | | |11 = The new reference pattern is repeated from SEED (RTC_TAMPSEED[31:0]) when the reference pattern run out.
* | | |Note: After revise this bit, the SEEDRLD (RTC_TAMPCTL[4]) should be set.
* |[4] |SEEDRLD |Reload New Seed for PRNG Engine
* | | |Setting this bit, the tamper configuration will be reload.
* | | |0 = Generating key based on the current seed.
* | | |1 = Reload new seed.
* | | |Note: Before set this bit, the tamper configuration should be set to complete.
* |[7:5] |DYNRATE |Dynamic Change Rate
* | | |This item is choice the dynamic tamper output change rate.
* | | |000 = 210 * RTC_CLK.
* | | |001 = 211 * RTC_CLK.
* | | |010 = 212 * RTC_CLK.
* | | |011 = 213 * RTC_CLK.
* | | |100 = 214 * RTC_CLK.
* | | |101 = 215 * RTC_CLK.
* | | |110 = 216 * RTC_CLK.
* | | |111 = 217 * RTC_CLK.
* | | |Note: After revise this field, set SEEDRLD (RTC_TAMPCTL[4]) can reload change rate immediately.
* |[8] |TAMP0EN |Tamper0 Detect Enable Bit
* | | |0 = Tamper 0 detect Disabled.
* | | |1 = Tamper 0 detect Enabled.
* | | |Note1: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock.
* |[9] |TAMP0LV |Tamper 0 Level
* | | |This bit depend on level attribute of tamper pin for static tamper detection.
* | | |0 = Detect voltage level is low.
* | | |1 = Detect voltage level is high.
* |[10] |TAMP0DBEN |Tamper 0 De-bounce Enable Bit
* | | |0 = Tamper 0 de-bounce Disabled.
* | | |1 = Tamper 0 de-bounce Enabled.
* |[12] |TAMP1EN |Tamper 1 Detect Enable Bit
* | | |0 = Tamper 1 detect Disabled.
* | | |1 = Tamper 1 detect Enabled.
* | | |Note1: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock.
* |[13] |TAMP1LV |Tamper 1 Level
* | | |This bit depend on level attribute of tamper pin for static tamper detection.
* | | |0 = Detect voltage level is low.
* | | |1 = Detect voltage level is high.
* |[14] |TAMP1DBEN |Tamper 1 De-bounce Enable Bit
* | | |0 = Tamper 1 de-bounce Disabled.
* | | |1 = Tamper 1 de-bounce Enabled.
* |[15] |DYNPR0EN |Dynamic Pair 0 Enable Bit
* | | |0 = Static detect.
* | | |1 = Dynamic detect.
* |[16] |TAMP2EN |Tamper 2 Detect Enable Bit
* | | |0 = Tamper 2 detect Disabled.
* | | |1 = Tamper 2 detect Enabled.
* | | |Note1: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock.
* |[17] |TAMP2LV |Tamper 2 Level
* | | |This bit depend on level attribute of tamper pin for static tamper detection.
* | | |0 = Detect voltage level is low.
* | | |1 = Detect voltage level is high.
* |[18] |TAMP2DBEN |Tamper 2 De-bounce Enable Bit
* | | |0 = Tamper 2 de-bounce Disabled.
* | | |1 = Tamper 2 de-bounce Enabled.
* |[20] |TAMP3EN |Tamper 3 Detect Enable Bit
* | | |0 = Tamper 3 detect Disabled.
* | | |1 = Tamper 3 detect Enabled.
* | | |Note1: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock.
* |[21] |TAMP3LV |Tamper 3 Level
* | | |This bit depend on level attribute of tamper pin for static tamper detection.
* | | |0 = Detect voltage level is low.
* | | |1 = Detect voltage level is high.
* |[22] |TAMP3DBEN |Tamper 3 De-bounce Enable Bit
* | | |0 = Tamper 3 de-bounce Disabled.
* | | |1 = Tamper 3 de-bounce Enabled.
* |[23] |DYNPR1EN |Dynamic Pair 1 Enable Bit
* | | |0 = Static detect.
* | | |1 = Dynamic detect.
* |[24] |TAMP4EN |Tamper4 Detect Enable Bit
* | | |0 = Tamper 4 detect Disabled.
* | | |1 = Tamper 4 detect Enabled.
* | | |Note1: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock.
* |[25] |TAMP4LV |Tamper 4 Level
* | | |This bit depends on level attribute of tamper pin for static tamper detection.
* | | |0 = Detect voltage level is low.
* | | |1 = Detect voltage level is high.
* |[26] |TAMP4DBEN |Tamper 4 De-bounce Enable Bit
* | | |0 = Tamper 4 de-bounce Disabled.
* | | |1 = Tamper 4 de-bounce Enabled.
* |[28] |TAMP5EN |Tamper 5 Detect Enable Bit
* | | |0 = Tamper 5 detect Disabled.
* | | |1 = Tamper 5 detect Enabled.
* | | |Note1: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock.
* |[29] |TAMP5LV |Tamper 5 Level
* | | |This bit depend on level attribute of tamper pin for static tamper detection.
* | | |0 = Detect voltage level is low.
* | | |1 = Detect voltage level is high.
* |[30] |TAMP5DBEN |Tamper 5 De-bounce Enable Bit
* | | |0 = Tamper 5 de-bounce Disabled.
* | | |1 = Tamper 5 de-bounce Enabled.
* |[31] |DYNPR2EN |Dynamic Pair 2 Enable Bit
* | | |0 = Static detect.
* | | |1 = Dynamic detect.
* @var RTC_T::TAMPSEED
* Offset: 0x128 RTC Tamper Dynamic Seed Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |SEED |Seed Value
* @var RTC_T::TAMPTIME
* Offset: 0x130 RTC Tamper Time Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |SEC |1-Sec Time Digit of TAMPER Time (0~9)
* |[6:4] |TENSEC |10-Sec Time Digit of TAMPER Time (0~5)
* |[11:8] |MIN |1-Min Time Digit of TAMPER Time (0~9)
* |[14:12] |TENMIN |10-Min Time Digit of TAMPER Time (0~5)
* |[19:16] |HR |1-Hour Time Digit of TAMPER Time (0~9)
* |[21:20] |TENHR |10-Hour Time Digit of TAMPER Time (0~2)
* | | |Note: 24-hour time scale only.
* @var RTC_T::TAMPCAL
* Offset: 0x134 RTC Tamper Calendar Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |DAY |1-Day Calendar Digit of TAMPER Calendar (0~9)
* |[5:4] |TENDAY |10-Day Calendar Digit of TAMPER Calendar (0~3)
* |[11:8] |MON |1-Month Calendar Digit of TAMPER Calendar (0~9)
* |[12] |TENMON |10-Month Calendar Digit of TAMPER Calendar (0~1)
* |[19:16] |YEAR |1-Year Calendar Digit of TAMPER Calendar (0~9)
* |[23:20] |TENYEAR |10-Year Calendar Digit of TAMPER Calendar (0~9)
*/
__IO uint32_t INIT; /*!< [0x0000] RTC Initiation Register */
__IO uint32_t RWEN; /*!< [0x0004] RTC Access Enable Register */
__IO uint32_t FREQADJ; /*!< [0x0008] RTC Frequency Compensation Register */
__IO uint32_t TIME; /*!< [0x000c] RTC Time Loading Register */
__IO uint32_t CAL; /*!< [0x0010] RTC Calendar Loading Register */
__IO uint32_t CLKFMT; /*!< [0x0014] RTC Time Scale Selection Register */
__IO uint32_t WEEKDAY; /*!< [0x0018] RTC Day of the Week Register */
__IO uint32_t TALM; /*!< [0x001c] RTC Time Alarm Register */
__IO uint32_t CALM; /*!< [0x0020] RTC Calendar Alarm Register */
__I uint32_t LEAPYEAR; /*!< [0x0024] RTC Leap Year Indicator Register */
__IO uint32_t INTEN; /*!< [0x0028] RTC Interrupt Enable Register */
__IO uint32_t INTSTS; /*!< [0x002c] RTC Interrupt Status Register */
__IO uint32_t TICK; /*!< [0x0030] RTC Time Tick Register */
__IO uint32_t TAMSK; /*!< [0x0034] RTC Time Alarm Mask Register */
__IO uint32_t CAMSK; /*!< [0x0038] RTC Calendar Alarm Mask Register */
__IO uint32_t SPRCTL; /*!< [0x003c] RTC Spare Functional Control Register */
__IO uint32_t SPR[20]; /*!< [0x0040] ~ [0x008c] RTC Spare Register 0 ~ 19 */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE0[28];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t LXTCTL; /*!< [0x0100] RTC 32.768 kHz Oscillator Control Register */
__IO uint32_t GPIOCTL0; /*!< [0x0104] RTC GPIO Control 0 Register */
__IO uint32_t GPIOCTL1; /*!< [0x0108] RTC GPIO Control 1 Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE1[1];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t DSTCTL; /*!< [0x0110] RTC Daylight Saving Time Control Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE2[3];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t TAMPCTL; /*!< [0x0120] RTC Tamper Pin Control Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE3[1];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t TAMPSEED; /*!< [0x0128] RTC Tamper Dynamic Seed Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE4[1];
/// @endcond //HIDDEN_SYMBOLS
__I uint32_t TAMPTIME; /*!< [0x0130] RTC Tamper Time Register */
__I uint32_t TAMPCAL; /*!< [0x0134] RTC Tamper Calendar Register */
} RTC_T;
/**
@addtogroup RTC_CONST RTC Bit Field Definition
Constant Definitions for RTC Controller
@{ */
#define RTC_INIT_ACTIVE_Pos (0) /*!< RTC_T::INIT: INIT_ACTIVE Position */
#define RTC_INIT_ACTIVE_Msk (0x1ul << RTC_INIT_ACTIVE_Pos) /*!< RTC_T::INIT: INIT_ACTIVE Mask */
#define RTC_INIT_INIT_Pos (1) /*!< RTC_T::INIT: INIT Position */
#define RTC_INIT_INIT_Msk (0x7ffffffful << RTC_INIT_INIT_Pos) /*!< RTC_T::INIT: INIT Mask */
#define RTC_RWEN_RWENF_Pos (16) /*!< RTC_T::RWEN: RWENF Position */
#define RTC_RWEN_RWENF_Msk (0x1ul << RTC_RWEN_RWENF_Pos) /*!< RTC_T::RWEN: RWENF Mask */
#define RTC_RWEN_RTCBUSY_Pos (24) /*!< RTC_T::RWEN: RTCBUSY Position */
#define RTC_RWEN_RTCBUSY_Msk (0x1ul << RTC_RWEN_RTCBUSY_Pos) /*!< RTC_T::RWEN: RTCBUSY Mask */
#define RTC_FREQADJ_FREQADJ_Pos (0) /*!< RTC_T::FREQADJ: FREQADJ Position */
#define RTC_FREQADJ_FREQADJ_Msk (0x3ffffful << RTC_FREQADJ_FREQADJ_Pos) /*!< RTC_T::FREQADJ: FREQADJ Mask */
#define RTC_TIME_SEC_Pos (0) /*!< RTC_T::TIME: SEC Position */
#define RTC_TIME_SEC_Msk (0xful << RTC_TIME_SEC_Pos) /*!< RTC_T::TIME: SEC Mask */
#define RTC_TIME_TENSEC_Pos (4) /*!< RTC_T::TIME: TENSEC Position */
#define RTC_TIME_TENSEC_Msk (0x7ul << RTC_TIME_TENSEC_Pos) /*!< RTC_T::TIME: TENSEC Mask */
#define RTC_TIME_MIN_Pos (8) /*!< RTC_T::TIME: MIN Position */
#define RTC_TIME_MIN_Msk (0xful << RTC_TIME_MIN_Pos) /*!< RTC_T::TIME: MIN Mask */
#define RTC_TIME_TENMIN_Pos (12) /*!< RTC_T::TIME: TENMIN Position */
#define RTC_TIME_TENMIN_Msk (0x7ul << RTC_TIME_TENMIN_Pos) /*!< RTC_T::TIME: TENMIN Mask */
#define RTC_TIME_HR_Pos (16) /*!< RTC_T::TIME: HR Position */
#define RTC_TIME_HR_Msk (0xful << RTC_TIME_HR_Pos) /*!< RTC_T::TIME: HR Mask */
#define RTC_TIME_TENHR_Pos (20) /*!< RTC_T::TIME: TENHR Position */
#define RTC_TIME_TENHR_Msk (0x3ul << RTC_TIME_TENHR_Pos) /*!< RTC_T::TIME: TENHR Mask */
#define RTC_CAL_DAY_Pos (0) /*!< RTC_T::CAL: DAY Position */
#define RTC_CAL_DAY_Msk (0xful << RTC_CAL_DAY_Pos) /*!< RTC_T::CAL: DAY Mask */
#define RTC_CAL_TENDAY_Pos (4) /*!< RTC_T::CAL: TENDAY Position */
#define RTC_CAL_TENDAY_Msk (0x3ul << RTC_CAL_TENDAY_Pos) /*!< RTC_T::CAL: TENDAY Mask */
#define RTC_CAL_MON_Pos (8) /*!< RTC_T::CAL: MON Position */
#define RTC_CAL_MON_Msk (0xful << RTC_CAL_MON_Pos) /*!< RTC_T::CAL: MON Mask */
#define RTC_CAL_TENMON_Pos (12) /*!< RTC_T::CAL: TENMON Position */
#define RTC_CAL_TENMON_Msk (0x1ul << RTC_CAL_TENMON_Pos) /*!< RTC_T::CAL: TENMON Mask */
#define RTC_CAL_YEAR_Pos (16) /*!< RTC_T::CAL: YEAR Position */
#define RTC_CAL_YEAR_Msk (0xful << RTC_CAL_YEAR_Pos) /*!< RTC_T::CAL: YEAR Mask */
#define RTC_CAL_TENYEAR_Pos (20) /*!< RTC_T::CAL: TENYEAR Position */
#define RTC_CAL_TENYEAR_Msk (0xful << RTC_CAL_TENYEAR_Pos) /*!< RTC_T::CAL: TENYEAR Mask */
#define RTC_CLKFMT_24HEN_Pos (0) /*!< RTC_T::CLKFMT: 24HEN Position */
#define RTC_CLKFMT_24HEN_Msk (0x1ul << RTC_CLKFMT_24HEN_Pos) /*!< RTC_T::CLKFMT: 24HEN Mask */
#define RTC_WEEKDAY_WEEKDAY_Pos (0) /*!< RTC_T::WEEKDAY: WEEKDAY Position */
#define RTC_WEEKDAY_WEEKDAY_Msk (0x7ul << RTC_WEEKDAY_WEEKDAY_Pos) /*!< RTC_T::WEEKDAY: WEEKDAY Mask */
#define RTC_TALM_SEC_Pos (0) /*!< RTC_T::TALM: SEC Position */
#define RTC_TALM_SEC_Msk (0xful << RTC_TALM_SEC_Pos) /*!< RTC_T::TALM: SEC Mask */
#define RTC_TALM_TENSEC_Pos (4) /*!< RTC_T::TALM: TENSEC Position */
#define RTC_TALM_TENSEC_Msk (0x7ul << RTC_TALM_TENSEC_Pos) /*!< RTC_T::TALM: TENSEC Mask */
#define RTC_TALM_MIN_Pos (8) /*!< RTC_T::TALM: MIN Position */
#define RTC_TALM_MIN_Msk (0xful << RTC_TALM_MIN_Pos) /*!< RTC_T::TALM: MIN Mask */
#define RTC_TALM_TENMIN_Pos (12) /*!< RTC_T::TALM: TENMIN Position */
#define RTC_TALM_TENMIN_Msk (0x7ul << RTC_TALM_TENMIN_Pos) /*!< RTC_T::TALM: TENMIN Mask */
#define RTC_TALM_HR_Pos (16) /*!< RTC_T::TALM: HR Position */
#define RTC_TALM_HR_Msk (0xful << RTC_TALM_HR_Pos) /*!< RTC_T::TALM: HR Mask */
#define RTC_TALM_TENHR_Pos (20) /*!< RTC_T::TALM: TENHR Position */
#define RTC_TALM_TENHR_Msk (0x3ul << RTC_TALM_TENHR_Pos) /*!< RTC_T::TALM: TENHR Mask */
#define RTC_CALM_DAY_Pos (0) /*!< RTC_T::CALM: DAY Position */
#define RTC_CALM_DAY_Msk (0xful << RTC_CALM_DAY_Pos) /*!< RTC_T::CALM: DAY Mask */
#define RTC_CALM_TENDAY_Pos (4) /*!< RTC_T::CALM: TENDAY Position */
#define RTC_CALM_TENDAY_Msk (0x3ul << RTC_CALM_TENDAY_Pos) /*!< RTC_T::CALM: TENDAY Mask */
#define RTC_CALM_MON_Pos (8) /*!< RTC_T::CALM: MON Position */
#define RTC_CALM_MON_Msk (0xful << RTC_CALM_MON_Pos) /*!< RTC_T::CALM: MON Mask */
#define RTC_CALM_TENMON_Pos (12) /*!< RTC_T::CALM: TENMON Position */
#define RTC_CALM_TENMON_Msk (0x1ul << RTC_CALM_TENMON_Pos) /*!< RTC_T::CALM: TENMON Mask */
#define RTC_CALM_YEAR_Pos (16) /*!< RTC_T::CALM: YEAR Position */
#define RTC_CALM_YEAR_Msk (0xful << RTC_CALM_YEAR_Pos) /*!< RTC_T::CALM: YEAR Mask */
#define RTC_CALM_TENYEAR_Pos (20) /*!< RTC_T::CALM: TENYEAR Position */
#define RTC_CALM_TENYEAR_Msk (0xful << RTC_CALM_TENYEAR_Pos) /*!< RTC_T::CALM: TENYEAR Mask */
#define RTC_LEAPYEAR_LEAPYEAR_Pos (0) /*!< RTC_T::LEAPYEAR: LEAPYEAR Position */
#define RTC_LEAPYEAR_LEAPYEAR_Msk (0x1ul << RTC_LEAPYEAR_LEAPYEAR_Pos) /*!< RTC_T::LEAPYEAR: LEAPYEAR Mask */
#define RTC_INTEN_ALMIEN_Pos (0) /*!< RTC_T::INTEN: ALMIEN Position */
#define RTC_INTEN_ALMIEN_Msk (0x1ul << RTC_INTEN_ALMIEN_Pos) /*!< RTC_T::INTEN: ALMIEN Mask */
#define RTC_INTEN_TICKIEN_Pos (1) /*!< RTC_T::INTEN: TICKIEN Position */
#define RTC_INTEN_TICKIEN_Msk (0x1ul << RTC_INTEN_TICKIEN_Pos) /*!< RTC_T::INTEN: TICKIEN Mask */
#define RTC_INTEN_TAMP0IEN_Pos (8) /*!< RTC_T::INTEN: TAMP0IEN Position */
#define RTC_INTEN_TAMP0IEN_Msk (0x1ul << RTC_INTEN_TAMP0IEN_Pos) /*!< RTC_T::INTEN: TAMP0IEN Mask */
#define RTC_INTEN_TAMP1IEN_Pos (9) /*!< RTC_T::INTEN: TAMP1IEN Position */
#define RTC_INTEN_TAMP1IEN_Msk (0x1ul << RTC_INTEN_TAMP1IEN_Pos) /*!< RTC_T::INTEN: TAMP1IEN Mask */
#define RTC_INTEN_TAMP2IEN_Pos (10) /*!< RTC_T::INTEN: TAMP2IEN Position */
#define RTC_INTEN_TAMP2IEN_Msk (0x1ul << RTC_INTEN_TAMP2IEN_Pos) /*!< RTC_T::INTEN: TAMP2IEN Mask */
#define RTC_INTEN_TAMP3IEN_Pos (11) /*!< RTC_T::INTEN: TAMP3IEN Position */
#define RTC_INTEN_TAMP3IEN_Msk (0x1ul << RTC_INTEN_TAMP3IEN_Pos) /*!< RTC_T::INTEN: TAMP3IEN Mask */
#define RTC_INTEN_TAMP4IEN_Pos (12) /*!< RTC_T::INTEN: TAMP4IEN Position */
#define RTC_INTEN_TAMP4IEN_Msk (0x1ul << RTC_INTEN_TAMP4IEN_Pos) /*!< RTC_T::INTEN: TAMP4IEN Mask */
#define RTC_INTEN_TAMP5IEN_Pos (13) /*!< RTC_T::INTEN: TAMP5IEN Position */
#define RTC_INTEN_TAMP5IEN_Msk (0x1ul << RTC_INTEN_TAMP5IEN_Pos) /*!< RTC_T::INTEN: TAMP5IEN Mask */
#define RTC_INTSTS_ALMIF_Pos (0) /*!< RTC_T::INTSTS: ALMIF Position */
#define RTC_INTSTS_ALMIF_Msk (0x1ul << RTC_INTSTS_ALMIF_Pos) /*!< RTC_T::INTSTS: ALMIF Mask */
#define RTC_INTSTS_TICKIF_Pos (1) /*!< RTC_T::INTSTS: TICKIF Position */
#define RTC_INTSTS_TICKIF_Msk (0x1ul << RTC_INTSTS_TICKIF_Pos) /*!< RTC_T::INTSTS: TICKIF Mask */
#define RTC_INTSTS_TAMP0IF_Pos (8) /*!< RTC_T::INTSTS: TAMP0IF Position */
#define RTC_INTSTS_TAMP0IF_Msk (0x1ul << RTC_INTSTS_TAMP0IF_Pos) /*!< RTC_T::INTSTS: TAMP0IF Mask */
#define RTC_INTSTS_TAMP1IF_Pos (9) /*!< RTC_T::INTSTS: TAMP1IF Position */
#define RTC_INTSTS_TAMP1IF_Msk (0x1ul << RTC_INTSTS_TAMP1IF_Pos) /*!< RTC_T::INTSTS: TAMP1IF Mask */
#define RTC_INTSTS_TAMP2IF_Pos (10) /*!< RTC_T::INTSTS: TAMP2IF Position */
#define RTC_INTSTS_TAMP2IF_Msk (0x1ul << RTC_INTSTS_TAMP2IF_Pos) /*!< RTC_T::INTSTS: TAMP2IF Mask */
#define RTC_INTSTS_TAMP3IF_Pos (11) /*!< RTC_T::INTSTS: TAMP3IF Position */
#define RTC_INTSTS_TAMP3IF_Msk (0x1ul << RTC_INTSTS_TAMP3IF_Pos) /*!< RTC_T::INTSTS: TAMP3IF Mask */
#define RTC_INTSTS_TAMP4IF_Pos (12) /*!< RTC_T::INTSTS: TAMP4IF Position */
#define RTC_INTSTS_TAMP4IF_Msk (0x1ul << RTC_INTSTS_TAMP4IF_Pos) /*!< RTC_T::INTSTS: TAMP4IF Mask */
#define RTC_INTSTS_TAMP5IF_Pos (13) /*!< RTC_T::INTSTS: TAMP5IF Position */
#define RTC_INTSTS_TAMP5IF_Msk (0x1ul << RTC_INTSTS_TAMP5IF_Pos) /*!< RTC_T::INTSTS: TAMP5IF Mask */
#define RTC_TICK_TICK_Pos (0) /*!< RTC_T::TICK: TICK Position */
#define RTC_TICK_TICK_Msk (0x7ul << RTC_TICK_TICK_Pos) /*!< RTC_T::TICK: TICK Mask */
#define RTC_TAMSK_MSEC_Pos (0) /*!< RTC_T::TAMSK: MSEC Position */
#define RTC_TAMSK_MSEC_Msk (0x1ul << RTC_TAMSK_MSEC_Pos) /*!< RTC_T::TAMSK: MSEC Mask */
#define RTC_TAMSK_MTENSEC_Pos (1) /*!< RTC_T::TAMSK: MTENSEC Position */
#define RTC_TAMSK_MTENSEC_Msk (0x1ul << RTC_TAMSK_MTENSEC_Pos) /*!< RTC_T::TAMSK: MTENSEC Mask */
#define RTC_TAMSK_MMIN_Pos (2) /*!< RTC_T::TAMSK: MMIN Position */
#define RTC_TAMSK_MMIN_Msk (0x1ul << RTC_TAMSK_MMIN_Pos) /*!< RTC_T::TAMSK: MMIN Mask */
#define RTC_TAMSK_MTENMIN_Pos (3) /*!< RTC_T::TAMSK: MTENMIN Position */
#define RTC_TAMSK_MTENMIN_Msk (0x1ul << RTC_TAMSK_MTENMIN_Pos) /*!< RTC_T::TAMSK: MTENMIN Mask */
#define RTC_TAMSK_MHR_Pos (4) /*!< RTC_T::TAMSK: MHR Position */
#define RTC_TAMSK_MHR_Msk (0x1ul << RTC_TAMSK_MHR_Pos) /*!< RTC_T::TAMSK: MHR Mask */
#define RTC_TAMSK_MTENHR_Pos (5) /*!< RTC_T::TAMSK: MTENHR Position */
#define RTC_TAMSK_MTENHR_Msk (0x1ul << RTC_TAMSK_MTENHR_Pos) /*!< RTC_T::TAMSK: MTENHR Mask */
#define RTC_CAMSK_MDAY_Pos (0) /*!< RTC_T::CAMSK: MDAY Position */
#define RTC_CAMSK_MDAY_Msk (0x1ul << RTC_CAMSK_MDAY_Pos) /*!< RTC_T::CAMSK: MDAY Mask */
#define RTC_CAMSK_MTENDAY_Pos (1) /*!< RTC_T::CAMSK: MTENDAY Position */
#define RTC_CAMSK_MTENDAY_Msk (0x1ul << RTC_CAMSK_MTENDAY_Pos) /*!< RTC_T::CAMSK: MTENDAY Mask */
#define RTC_CAMSK_MMON_Pos (2) /*!< RTC_T::CAMSK: MMON Position */
#define RTC_CAMSK_MMON_Msk (0x1ul << RTC_CAMSK_MMON_Pos) /*!< RTC_T::CAMSK: MMON Mask */
#define RTC_CAMSK_MTENMON_Pos (3) /*!< RTC_T::CAMSK: MTENMON Position */
#define RTC_CAMSK_MTENMON_Msk (0x1ul << RTC_CAMSK_MTENMON_Pos) /*!< RTC_T::CAMSK: MTENMON Mask */
#define RTC_CAMSK_MYEAR_Pos (4) /*!< RTC_T::CAMSK: MYEAR Position */
#define RTC_CAMSK_MYEAR_Msk (0x1ul << RTC_CAMSK_MYEAR_Pos) /*!< RTC_T::CAMSK: MYEAR Mask */
#define RTC_CAMSK_MTENYEAR_Pos (5) /*!< RTC_T::CAMSK: MTENYEAR Position */
#define RTC_CAMSK_MTENYEAR_Msk (0x1ul << RTC_CAMSK_MTENYEAR_Pos) /*!< RTC_T::CAMSK: MTENYEAR Mask */
#define RTC_SPRCTL_SPRRWEN_Pos (2) /*!< RTC_T::SPRCTL: SPRRWEN Position */
#define RTC_SPRCTL_SPRRWEN_Msk (0x1ul << RTC_SPRCTL_SPRRWEN_Pos) /*!< RTC_T::SPRCTL: SPRRWEN Mask */
#define RTC_SPRCTL_SPRCSTS_Pos (5) /*!< RTC_T::SPRCTL: SPRCSTS Position */
#define RTC_SPRCTL_SPRCSTS_Msk (0x1ul << RTC_SPRCTL_SPRCSTS_Pos) /*!< RTC_T::SPRCTL: SPRCSTS Mask */
#define RTC_SPR0_SPARE_Pos (0) /*!< RTC_T::SPR0: SPARE Position */
#define RTC_SPR0_SPARE_Msk (0xfffffffful << RTC_SPR0_SPARE_Pos) /*!< RTC_T::SPR0: SPARE Mask */
#define RTC_SPR1_SPARE_Pos (0) /*!< RTC_T::SPR1: SPARE Position */
#define RTC_SPR1_SPARE_Msk (0xfffffffful << RTC_SPR1_SPARE_Pos) /*!< RTC_T::SPR1: SPARE Mask */
#define RTC_SPR2_SPARE_Pos (0) /*!< RTC_T::SPR2: SPARE Position */
#define RTC_SPR2_SPARE_Msk (0xfffffffful << RTC_SPR2_SPARE_Pos) /*!< RTC_T::SPR2: SPARE Mask */
#define RTC_SPR3_SPARE_Pos (0) /*!< RTC_T::SPR3: SPARE Position */
#define RTC_SPR3_SPARE_Msk (0xfffffffful << RTC_SPR3_SPARE_Pos) /*!< RTC_T::SPR3: SPARE Mask */
#define RTC_SPR4_SPARE_Pos (0) /*!< RTC_T::SPR4: SPARE Position */
#define RTC_SPR4_SPARE_Msk (0xfffffffful << RTC_SPR4_SPARE_Pos) /*!< RTC_T::SPR4: SPARE Mask */
#define RTC_SPR5_SPARE_Pos (0) /*!< RTC_T::SPR5: SPARE Position */
#define RTC_SPR5_SPARE_Msk (0xfffffffful << RTC_SPR5_SPARE_Pos) /*!< RTC_T::SPR5: SPARE Mask */
#define RTC_SPR6_SPARE_Pos (0) /*!< RTC_T::SPR6: SPARE Position */
#define RTC_SPR6_SPARE_Msk (0xfffffffful << RTC_SPR6_SPARE_Pos) /*!< RTC_T::SPR6: SPARE Mask */
#define RTC_SPR7_SPARE_Pos (0) /*!< RTC_T::SPR7: SPARE Position */
#define RTC_SPR7_SPARE_Msk (0xfffffffful << RTC_SPR7_SPARE_Pos) /*!< RTC_T::SPR7: SPARE Mask */
#define RTC_SPR8_SPARE_Pos (0) /*!< RTC_T::SPR8: SPARE Position */
#define RTC_SPR8_SPARE_Msk (0xfffffffful << RTC_SPR8_SPARE_Pos) /*!< RTC_T::SPR8: SPARE Mask */
#define RTC_SPR9_SPARE_Pos (0) /*!< RTC_T::SPR9: SPARE Position */
#define RTC_SPR9_SPARE_Msk (0xfffffffful << RTC_SPR9_SPARE_Pos) /*!< RTC_T::SPR9: SPARE Mask */
#define RTC_SPR10_SPARE_Pos (0) /*!< RTC_T::SPR10: SPARE Position */
#define RTC_SPR10_SPARE_Msk (0xfffffffful << RTC_SPR10_SPARE_Pos) /*!< RTC_T::SPR10: SPARE Mask */
#define RTC_SPR11_SPARE_Pos (0) /*!< RTC_T::SPR11: SPARE Position */
#define RTC_SPR11_SPARE_Msk (0xfffffffful << RTC_SPR11_SPARE_Pos) /*!< RTC_T::SPR11: SPARE Mask */
#define RTC_SPR12_SPARE_Pos (0) /*!< RTC_T::SPR12: SPARE Position */
#define RTC_SPR12_SPARE_Msk (0xfffffffful << RTC_SPR12_SPARE_Pos) /*!< RTC_T::SPR12: SPARE Mask */
#define RTC_SPR13_SPARE_Pos (0) /*!< RTC_T::SPR13: SPARE Position */
#define RTC_SPR13_SPARE_Msk (0xfffffffful << RTC_SPR13_SPARE_Pos) /*!< RTC_T::SPR13: SPARE Mask */
#define RTC_SPR14_SPARE_Pos (0) /*!< RTC_T::SPR14: SPARE Position */
#define RTC_SPR14_SPARE_Msk (0xfffffffful << RTC_SPR14_SPARE_Pos) /*!< RTC_T::SPR14: SPARE Mask */
#define RTC_SPR15_SPARE_Pos (0) /*!< RTC_T::SPR15: SPARE Position */
#define RTC_SPR15_SPARE_Msk (0xfffffffful << RTC_SPR15_SPARE_Pos) /*!< RTC_T::SPR15: SPARE Mask */
#define RTC_SPR16_SPARE_Pos (0) /*!< RTC_T::SPR16: SPARE Position */
#define RTC_SPR16_SPARE_Msk (0xfffffffful << RTC_SPR16_SPARE_Pos) /*!< RTC_T::SPR16: SPARE Mask */
#define RTC_SPR17_SPARE_Pos (0) /*!< RTC_T::SPR17: SPARE Position */
#define RTC_SPR17_SPARE_Msk (0xfffffffful << RTC_SPR17_SPARE_Pos) /*!< RTC_T::SPR17: SPARE Mask */
#define RTC_SPR18_SPARE_Pos (0) /*!< RTC_T::SPR18: SPARE Position */
#define RTC_SPR18_SPARE_Msk (0xfffffffful << RTC_SPR18_SPARE_Pos) /*!< RTC_T::SPR18: SPARE Mask */
#define RTC_SPR19_SPARE_Pos (0) /*!< RTC_T::SPR19: SPARE Position */
#define RTC_SPR19_SPARE_Msk (0xfffffffful << RTC_SPR19_SPARE_Pos) /*!< RTC_T::SPR19: SPARE Mask */
#define RTC_LXTCTL_GAIN_Pos (1) /*!< RTC_T::LXTCTL: GAIN Position */
#define RTC_LXTCTL_GAIN_Msk (0x3ul << RTC_LXTCTL_GAIN_Pos) /*!< RTC_T::LXTCTL: GAIN Mask */
#define RTC_GPIOCTL0_OPMODE0_Pos (0) /*!< RTC_T::GPIOCTL0: OPMODE0 Position */
#define RTC_GPIOCTL0_OPMODE0_Msk (0x3ul << RTC_GPIOCTL0_OPMODE0_Pos) /*!< RTC_T::GPIOCTL0: OPMODE0 Mask */
#define RTC_GPIOCTL0_DOUT0_Pos (2) /*!< RTC_T::GPIOCTL0: DOUT0 Position */
#define RTC_GPIOCTL0_DOUT0_Msk (0x1ul << RTC_GPIOCTL0_DOUT0_Pos) /*!< RTC_T::GPIOCTL0: DOUT0 Mask */
#define RTC_GPIOCTL0_CTLSEL0_Pos (3) /*!< RTC_T::GPIOCTL0: CTLSEL0 Position */
#define RTC_GPIOCTL0_CTLSEL0_Msk (0x1ul << RTC_GPIOCTL0_CTLSEL0_Pos) /*!< RTC_T::GPIOCTL0: CTLSEL0 Mask */
#define RTC_GPIOCTL0_PUSEL0_Pos (4) /*!< RTC_T::GPIOCTL0: PUSEL0 Position */
#define RTC_GPIOCTL0_PUSEL0_Msk (0x3ul << RTC_GPIOCTL0_PUSEL0_Pos) /*!< RTC_T::GPIOCTL0: PUSEL0 Mask */
#define RTC_GPIOCTL0_OPMODE1_Pos (8) /*!< RTC_T::GPIOCTL0: OPMODE1 Position */
#define RTC_GPIOCTL0_OPMODE1_Msk (0x3ul << RTC_GPIOCTL0_OPMODE1_Pos) /*!< RTC_T::GPIOCTL0: OPMODE1 Mask */
#define RTC_GPIOCTL0_DOUT1_Pos (10) /*!< RTC_T::GPIOCTL0: DOUT1 Position */
#define RTC_GPIOCTL0_DOUT1_Msk (0x1ul << RTC_GPIOCTL0_DOUT1_Pos) /*!< RTC_T::GPIOCTL0: DOUT1 Mask */
#define RTC_GPIOCTL0_CTLSEL1_Pos (11) /*!< RTC_T::GPIOCTL0: CTLSEL1 Position */
#define RTC_GPIOCTL0_CTLSEL1_Msk (0x1ul << RTC_GPIOCTL0_CTLSEL1_Pos) /*!< RTC_T::GPIOCTL0: CTLSEL1 Mask */
#define RTC_GPIOCTL0_PUSEL1_Pos (12) /*!< RTC_T::GPIOCTL0: PUSEL1 Position */
#define RTC_GPIOCTL0_PUSEL1_Msk (0x3ul << RTC_GPIOCTL0_PUSEL1_Pos) /*!< RTC_T::GPIOCTL0: PUSEL1 Mask */
#define RTC_GPIOCTL0_OPMODE2_Pos (16) /*!< RTC_T::GPIOCTL0: OPMODE2 Position */
#define RTC_GPIOCTL0_OPMODE2_Msk (0x3ul << RTC_GPIOCTL0_OPMODE2_Pos) /*!< RTC_T::GPIOCTL0: OPMODE2 Mask */
#define RTC_GPIOCTL0_DOUT2_Pos (18) /*!< RTC_T::GPIOCTL0: DOUT2 Position */
#define RTC_GPIOCTL0_DOUT2_Msk (0x1ul << RTC_GPIOCTL0_DOUT2_Pos) /*!< RTC_T::GPIOCTL0: DOUT2 Mask */
#define RTC_GPIOCTL0_CTLSEL2_Pos (19) /*!< RTC_T::GPIOCTL0: CTLSEL2 Position */
#define RTC_GPIOCTL0_CTLSEL2_Msk (0x1ul << RTC_GPIOCTL0_CTLSEL2_Pos) /*!< RTC_T::GPIOCTL0: CTLSEL2 Mask */
#define RTC_GPIOCTL0_PUSEL2_Pos (20) /*!< RTC_T::GPIOCTL0: PUSEL2 Position */
#define RTC_GPIOCTL0_PUSEL2_Msk (0x3ul << RTC_GPIOCTL0_PUSEL2_Pos) /*!< RTC_T::GPIOCTL0: PUSEL2 Mask */
#define RTC_GPIOCTL0_OPMODE3_Pos (24) /*!< RTC_T::GPIOCTL0: OPMODE3 Position */
#define RTC_GPIOCTL0_OPMODE3_Msk (0x3ul << RTC_GPIOCTL0_OPMODE3_Pos) /*!< RTC_T::GPIOCTL0: OPMODE3 Mask */
#define RTC_GPIOCTL0_DOUT3_Pos (26) /*!< RTC_T::GPIOCTL0: DOUT3 Position */
#define RTC_GPIOCTL0_DOUT3_Msk (0x1ul << RTC_GPIOCTL0_DOUT3_Pos) /*!< RTC_T::GPIOCTL0: DOUT3 Mask */
#define RTC_GPIOCTL0_CTLSEL3_Pos (27) /*!< RTC_T::GPIOCTL0: CTLSEL3 Position */
#define RTC_GPIOCTL0_CTLSEL3_Msk (0x1ul << RTC_GPIOCTL0_CTLSEL3_Pos) /*!< RTC_T::GPIOCTL0: CTLSEL3 Mask */
#define RTC_GPIOCTL0_PUSEL3_Pos (28) /*!< RTC_T::GPIOCTL0: PUSEL3 Position */
#define RTC_GPIOCTL0_PUSEL3_Msk (0x3ul << RTC_GPIOCTL0_PUSEL3_Pos) /*!< RTC_T::GPIOCTL0: PUSEL3 Mask */
#define RTC_GPIOCTL1_OPMODE4_Pos (0) /*!< RTC_T::GPIOCTL1: OPMODE4 Position */
#define RTC_GPIOCTL1_OPMODE4_Msk (0x3ul << RTC_GPIOCTL1_OPMODE4_Pos) /*!< RTC_T::GPIOCTL1: OPMODE4 Mask */
#define RTC_GPIOCTL1_DOUT4_Pos (2) /*!< RTC_T::GPIOCTL1: DOUT4 Position */
#define RTC_GPIOCTL1_DOUT4_Msk (0x1ul << RTC_GPIOCTL1_DOUT4_Pos) /*!< RTC_T::GPIOCTL1: DOUT4 Mask */
#define RTC_GPIOCTL1_CTLSEL4_Pos (3) /*!< RTC_T::GPIOCTL1: CTLSEL4 Position */
#define RTC_GPIOCTL1_CTLSEL4_Msk (0x1ul << RTC_GPIOCTL1_CTLSEL4_Pos) /*!< RTC_T::GPIOCTL1: CTLSEL4 Mask */
#define RTC_GPIOCTL1_PUSEL4_Pos (4) /*!< RTC_T::GPIOCTL1: PUSEL4 Position */
#define RTC_GPIOCTL1_PUSEL4_Msk (0x3ul << RTC_GPIOCTL1_PUSEL4_Pos) /*!< RTC_T::GPIOCTL1: PUSEL4 Mask */
#define RTC_GPIOCTL1_OPMODE5_Pos (8) /*!< RTC_T::GPIOCTL1: OPMODE5 Position */
#define RTC_GPIOCTL1_OPMODE5_Msk (0x3ul << RTC_GPIOCTL1_OPMODE5_Pos) /*!< RTC_T::GPIOCTL1: OPMODE5 Mask */
#define RTC_GPIOCTL1_DOUT5_Pos (10) /*!< RTC_T::GPIOCTL1: DOUT5 Position */
#define RTC_GPIOCTL1_DOUT5_Msk (0x1ul << RTC_GPIOCTL1_DOUT5_Pos) /*!< RTC_T::GPIOCTL1: DOUT5 Mask */
#define RTC_GPIOCTL1_CTLSEL5_Pos (11) /*!< RTC_T::GPIOCTL1: CTLSEL5 Position */
#define RTC_GPIOCTL1_CTLSEL5_Msk (0x1ul << RTC_GPIOCTL1_CTLSEL5_Pos) /*!< RTC_T::GPIOCTL1: CTLSEL5 Mask */
#define RTC_GPIOCTL1_PUSEL5_Pos (12) /*!< RTC_T::GPIOCTL1: PUSEL5 Position */
#define RTC_GPIOCTL1_PUSEL5_Msk (0x3ul << RTC_GPIOCTL1_PUSEL5_Pos) /*!< RTC_T::GPIOCTL1: PUSEL5 Mask */
#define RTC_GPIOCTL1_OPMODE6_Pos (16) /*!< RTC_T::GPIOCTL1: OPMODE6 Position */
#define RTC_GPIOCTL1_OPMODE6_Msk (0x3ul << RTC_GPIOCTL1_OPMODE6_Pos) /*!< RTC_T::GPIOCTL1: OPMODE6 Mask */
#define RTC_GPIOCTL1_DOUT6_Pos (18) /*!< RTC_T::GPIOCTL1: DOUT6 Position */
#define RTC_GPIOCTL1_DOUT6_Msk (0x1ul << RTC_GPIOCTL1_DOUT6_Pos) /*!< RTC_T::GPIOCTL1: DOUT6 Mask */
#define RTC_GPIOCTL1_CTLSEL6_Pos (19) /*!< RTC_T::GPIOCTL1: CTLSEL6 Position */
#define RTC_GPIOCTL1_CTLSEL6_Msk (0x1ul << RTC_GPIOCTL1_CTLSEL6_Pos) /*!< RTC_T::GPIOCTL1: CTLSEL6 Mask */
#define RTC_GPIOCTL1_PUSEL6_Pos (20) /*!< RTC_T::GPIOCTL1: PUSEL6 Position */
#define RTC_GPIOCTL1_PUSEL6_Msk (0x3ul << RTC_GPIOCTL1_PUSEL6_Pos) /*!< RTC_T::GPIOCTL1: PUSEL6 Mask */
#define RTC_GPIOCTL1_OPMODE7_Pos (24) /*!< RTC_T::GPIOCTL1: OPMODE7 Position */
#define RTC_GPIOCTL1_OPMODE7_Msk (0x3ul << RTC_GPIOCTL1_OPMODE7_Pos) /*!< RTC_T::GPIOCTL1: OPMODE7 Mask */
#define RTC_GPIOCTL1_DOUT7_Pos (26) /*!< RTC_T::GPIOCTL1: DOUT7 Position */
#define RTC_GPIOCTL1_DOUT7_Msk (0x1ul << RTC_GPIOCTL1_DOUT7_Pos) /*!< RTC_T::GPIOCTL1: DOUT7 Mask */
#define RTC_GPIOCTL1_CTLSEL7_Pos (27) /*!< RTC_T::GPIOCTL1: CTLSEL7 Position */
#define RTC_GPIOCTL1_CTLSEL7_Msk (0x1ul << RTC_GPIOCTL1_CTLSEL7_Pos) /*!< RTC_T::GPIOCTL1: CTLSEL7 Mask */
#define RTC_GPIOCTL1_PUSEL7_Pos (28) /*!< RTC_T::GPIOCTL1: PUSEL7 Position */
#define RTC_GPIOCTL1_PUSEL7_Msk (0x3ul << RTC_GPIOCTL1_PUSEL7_Pos) /*!< RTC_T::GPIOCTL1: PUSEL7 Mask */
#define RTC_DSTCTL_ADDHR_Pos (0) /*!< RTC_T::DSTCTL: ADDHR Position */
#define RTC_DSTCTL_ADDHR_Msk (0x1ul << RTC_DSTCTL_ADDHR_Pos) /*!< RTC_T::DSTCTL: ADDHR Mask */
#define RTC_DSTCTL_SUBHR_Pos (1) /*!< RTC_T::DSTCTL: SUBHR Position */
#define RTC_DSTCTL_SUBHR_Msk (0x1ul << RTC_DSTCTL_SUBHR_Pos) /*!< RTC_T::DSTCTL: SUBHR Mask */
#define RTC_DSTCTL_DSBAK_Pos (2) /*!< RTC_T::DSTCTL: DSBAK Position */
#define RTC_DSTCTL_DSBAK_Msk (0x1ul << RTC_DSTCTL_DSBAK_Pos) /*!< RTC_T::DSTCTL: DSBAK Mask */
#define RTC_TAMPCTL_DYN1ISS_Pos (0) /*!< RTC_T::TAMPCTL: DYN1ISS Position */
#define RTC_TAMPCTL_DYN1ISS_Msk (0x1ul << RTC_TAMPCTL_DYN1ISS_Pos) /*!< RTC_T::TAMPCTL: DYN1ISS Mask */
#define RTC_TAMPCTL_DYN2ISS_Pos (1) /*!< RTC_T::TAMPCTL: DYN2ISS Position */
#define RTC_TAMPCTL_DYN2ISS_Msk (0x1ul << RTC_TAMPCTL_DYN2ISS_Pos) /*!< RTC_T::TAMPCTL: DYN2ISS Mask */
#define RTC_TAMPCTL_DYNSRC_Pos (2) /*!< RTC_T::TAMPCTL: DYNSRC Position */
#define RTC_TAMPCTL_DYNSRC_Msk (0x3ul << RTC_TAMPCTL_DYNSRC_Pos) /*!< RTC_T::TAMPCTL: DYNSRC Mask */
#define RTC_TAMPCTL_SEEDRLD_Pos (4) /*!< RTC_T::TAMPCTL: SEEDRLD Position */
#define RTC_TAMPCTL_SEEDRLD_Msk (0x1ul << RTC_TAMPCTL_SEEDRLD_Pos) /*!< RTC_T::TAMPCTL: SEEDRLD Mask */
#define RTC_TAMPCTL_DYNRATE_Pos (5) /*!< RTC_T::TAMPCTL: DYNRATE Position */
#define RTC_TAMPCTL_DYNRATE_Msk (0x7ul << RTC_TAMPCTL_DYNRATE_Pos) /*!< RTC_T::TAMPCTL: DYNRATE Mask */
#define RTC_TAMPCTL_TAMP0EN_Pos (8) /*!< RTC_T::TAMPCTL: TAMP0EN Position */
#define RTC_TAMPCTL_TAMP0EN_Msk (0x1ul << RTC_TAMPCTL_TAMP0EN_Pos) /*!< RTC_T::TAMPCTL: TAMP0EN Mask */
#define RTC_TAMPCTL_TAMP0LV_Pos (9) /*!< RTC_T::TAMPCTL: TAMP0LV Position */
#define RTC_TAMPCTL_TAMP0LV_Msk (0x1ul << RTC_TAMPCTL_TAMP0LV_Pos) /*!< RTC_T::TAMPCTL: TAMP0LV Mask */
#define RTC_TAMPCTL_TAMP0DBEN_Pos (10) /*!< RTC_T::TAMPCTL: TAMP0DBEN Position */
#define RTC_TAMPCTL_TAMP0DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP0DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP0DBEN Mask */
#define RTC_TAMPCTL_TAMP1EN_Pos (12) /*!< RTC_T::TAMPCTL: TAMP1EN Position */
#define RTC_TAMPCTL_TAMP1EN_Msk (0x1ul << RTC_TAMPCTL_TAMP1EN_Pos) /*!< RTC_T::TAMPCTL: TAMP1EN Mask */
#define RTC_TAMPCTL_TAMP1LV_Pos (13) /*!< RTC_T::TAMPCTL: TAMP1LV Position */
#define RTC_TAMPCTL_TAMP1LV_Msk (0x1ul << RTC_TAMPCTL_TAMP1LV_Pos) /*!< RTC_T::TAMPCTL: TAMP1LV Mask */
#define RTC_TAMPCTL_TAMP1DBEN_Pos (14) /*!< RTC_T::TAMPCTL: TAMP1DBEN Position */
#define RTC_TAMPCTL_TAMP1DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP1DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP1DBEN Mask */
#define RTC_TAMPCTL_DYNPR0EN_Pos (15) /*!< RTC_T::TAMPCTL: DYNPR0EN Position */
#define RTC_TAMPCTL_DYNPR0EN_Msk (0x1ul << RTC_TAMPCTL_DYNPR0EN_Pos) /*!< RTC_T::TAMPCTL: DYNPR0EN Mask */
#define RTC_TAMPCTL_TAMP2EN_Pos (16) /*!< RTC_T::TAMPCTL: TAMP2EN Position */
#define RTC_TAMPCTL_TAMP2EN_Msk (0x1ul << RTC_TAMPCTL_TAMP2EN_Pos) /*!< RTC_T::TAMPCTL: TAMP2EN Mask */
#define RTC_TAMPCTL_TAMP2LV_Pos (17) /*!< RTC_T::TAMPCTL: TAMP2LV Position */
#define RTC_TAMPCTL_TAMP2LV_Msk (0x1ul << RTC_TAMPCTL_TAMP2LV_Pos) /*!< RTC_T::TAMPCTL: TAMP2LV Mask */
#define RTC_TAMPCTL_TAMP2DBEN_Pos (18) /*!< RTC_T::TAMPCTL: TAMP2DBEN Position */
#define RTC_TAMPCTL_TAMP2DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP2DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP2DBEN Mask */
#define RTC_TAMPCTL_TAMP3EN_Pos (20) /*!< RTC_T::TAMPCTL: TAMP3EN Position */
#define RTC_TAMPCTL_TAMP3EN_Msk (0x1ul << RTC_TAMPCTL_TAMP3EN_Pos) /*!< RTC_T::TAMPCTL: TAMP3EN Mask */
#define RTC_TAMPCTL_TAMP3LV_Pos (21) /*!< RTC_T::TAMPCTL: TAMP3LV Position */
#define RTC_TAMPCTL_TAMP3LV_Msk (0x1ul << RTC_TAMPCTL_TAMP3LV_Pos) /*!< RTC_T::TAMPCTL: TAMP3LV Mask */
#define RTC_TAMPCTL_TAMP3DBEN_Pos (22) /*!< RTC_T::TAMPCTL: TAMP3DBEN Position */
#define RTC_TAMPCTL_TAMP3DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP3DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP3DBEN Mask */
#define RTC_TAMPCTL_DYNPR1EN_Pos (23) /*!< RTC_T::TAMPCTL: DYNPR1EN Position */
#define RTC_TAMPCTL_DYNPR1EN_Msk (0x1ul << RTC_TAMPCTL_DYNPR1EN_Pos) /*!< RTC_T::TAMPCTL: DYNPR1EN Mask */
#define RTC_TAMPCTL_TAMP4EN_Pos (24) /*!< RTC_T::TAMPCTL: TAMP4EN Position */
#define RTC_TAMPCTL_TAMP4EN_Msk (0x1ul << RTC_TAMPCTL_TAMP4EN_Pos) /*!< RTC_T::TAMPCTL: TAMP4EN Mask */
#define RTC_TAMPCTL_TAMP4LV_Pos (25) /*!< RTC_T::TAMPCTL: TAMP4LV Position */
#define RTC_TAMPCTL_TAMP4LV_Msk (0x1ul << RTC_TAMPCTL_TAMP4LV_Pos) /*!< RTC_T::TAMPCTL: TAMP4LV Mask */
#define RTC_TAMPCTL_TAMP4DBEN_Pos (26) /*!< RTC_T::TAMPCTL: TAMP4DBEN Position */
#define RTC_TAMPCTL_TAMP4DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP4DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP4DBEN Mask */
#define RTC_TAMPCTL_TAMP5EN_Pos (28) /*!< RTC_T::TAMPCTL: TAMP5EN Position */
#define RTC_TAMPCTL_TAMP5EN_Msk (0x1ul << RTC_TAMPCTL_TAMP5EN_Pos) /*!< RTC_T::TAMPCTL: TAMP5EN Mask */
#define RTC_TAMPCTL_TAMP5LV_Pos (29) /*!< RTC_T::TAMPCTL: TAMP5LV Position */
#define RTC_TAMPCTL_TAMP5LV_Msk (0x1ul << RTC_TAMPCTL_TAMP5LV_Pos) /*!< RTC_T::TAMPCTL: TAMP5LV Mask */
#define RTC_TAMPCTL_TAMP5DBEN_Pos (30) /*!< RTC_T::TAMPCTL: TAMP5DBEN Position */
#define RTC_TAMPCTL_TAMP5DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP5DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP5DBEN Mask */
#define RTC_TAMPCTL_DYNPR2EN_Pos (31) /*!< RTC_T::TAMPCTL: DYNPR2EN Position */
#define RTC_TAMPCTL_DYNPR2EN_Msk (0x1ul << RTC_TAMPCTL_DYNPR2EN_Pos) /*!< RTC_T::TAMPCTL: DYNPR2EN Mask */
#define RTC_TAMPSEED_SEED_Pos (0) /*!< RTC_T::TAMPSEED: SEED Position */
#define RTC_TAMPSEED_SEED_Msk (0xfffffffful << RTC_TAMPSEED_SEED_Pos) /*!< RTC_T::TAMPSEED: SEED Mask */
#define RTC_TAMPTIME_SEC_Pos (0) /*!< RTC_T::TAMPTIME: SEC Position */
#define RTC_TAMPTIME_SEC_Msk (0xful << RTC_TAMPTIME_SEC_Pos) /*!< RTC_T::TAMPTIME: SEC Mask */
#define RTC_TAMPTIME_TENSEC_Pos (4) /*!< RTC_T::TAMPTIME: TENSEC Position */
#define RTC_TAMPTIME_TENSEC_Msk (0x7ul << RTC_TAMPTIME_TENSEC_Pos) /*!< RTC_T::TAMPTIME: TENSEC Mask */
#define RTC_TAMPTIME_MIN_Pos (8) /*!< RTC_T::TAMPTIME: MIN Position */
#define RTC_TAMPTIME_MIN_Msk (0xful << RTC_TAMPTIME_MIN_Pos) /*!< RTC_T::TAMPTIME: MIN Mask */
#define RTC_TAMPTIME_TENMIN_Pos (12) /*!< RTC_T::TAMPTIME: TENMIN Position */
#define RTC_TAMPTIME_TENMIN_Msk (0x7ul << RTC_TAMPTIME_TENMIN_Pos) /*!< RTC_T::TAMPTIME: TENMIN Mask */
#define RTC_TAMPTIME_HR_Pos (16) /*!< RTC_T::TAMPTIME: HR Position */
#define RTC_TAMPTIME_HR_Msk (0xful << RTC_TAMPTIME_HR_Pos) /*!< RTC_T::TAMPTIME: HR Mask */
#define RTC_TAMPTIME_TENHR_Pos (20) /*!< RTC_T::TAMPTIME: TENHR Position */
#define RTC_TAMPTIME_TENHR_Msk (0x3ul << RTC_TAMPTIME_TENHR_Pos) /*!< RTC_T::TAMPTIME: TENHR Mask */
#define RTC_TAMPCAL_DAY_Pos (0) /*!< RTC_T::TAMPCAL: DAY Position */
#define RTC_TAMPCAL_DAY_Msk (0xful << RTC_TAMPCAL_DAY_Pos) /*!< RTC_T::TAMPCAL: DAY Mask */
#define RTC_TAMPCAL_TENDAY_Pos (4) /*!< RTC_T::TAMPCAL: TENDAY Position */
#define RTC_TAMPCAL_TENDAY_Msk (0x3ul << RTC_TAMPCAL_TENDAY_Pos) /*!< RTC_T::TAMPCAL: TENDAY Mask */
#define RTC_TAMPCAL_MON_Pos (8) /*!< RTC_T::TAMPCAL: MON Position */
#define RTC_TAMPCAL_MON_Msk (0xful << RTC_TAMPCAL_MON_Pos) /*!< RTC_T::TAMPCAL: MON Mask */
#define RTC_TAMPCAL_TENMON_Pos (12) /*!< RTC_T::TAMPCAL: TENMON Position */
#define RTC_TAMPCAL_TENMON_Msk (0x1ul << RTC_TAMPCAL_TENMON_Pos) /*!< RTC_T::TAMPCAL: TENMON Mask */
#define RTC_TAMPCAL_YEAR_Pos (16) /*!< RTC_T::TAMPCAL: YEAR Position */
#define RTC_TAMPCAL_YEAR_Msk (0xful << RTC_TAMPCAL_YEAR_Pos) /*!< RTC_T::TAMPCAL: YEAR Mask */
#define RTC_TAMPCAL_TENYEAR_Pos (20) /*!< RTC_T::TAMPCAL: TENYEAR Position */
#define RTC_TAMPCAL_TENYEAR_Msk (0xful << RTC_TAMPCAL_TENYEAR_Pos) /*!< RTC_T::TAMPCAL: TENYEAR Mask */
/**@}*/ /* RTC_CONST */
/**@}*/ /* end of RTC register group */
/*---------------------- Pulse Width Modulation Controller -------------------------*/
/**
@addtogroup EPWM Pulse Width Modulation Controller(EPWM)
Memory Mapped Structure for EPWM Controller
@{ */
typedef struct {
/**
* @var EPWM_T::CTL0
* Offset: 0x00 EPWM Control Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CTRLD0 |Center Re-load
* | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period
* | | |CMPDAT will load to CMPBUF at the center point of a period
* |[1] |CTRLD1 |Center Re-load
* | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period
* | | |CMPDAT will load to CMPBUF at the center point of a period
* |[2] |CTRLD2 |Center Re-load
* | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period
* | | |CMPDAT will load to CMPBUF at the center point of a period
* |[3] |CTRLD3 |Center Re-load
* | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period
* | | |CMPDAT will load to CMPBUF at the center point of a period
* |[4] |CTRLD4 |Center Re-load
* | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period
* | | |CMPDAT will load to CMPBUF at the center point of a period
* |[5] |CTRLD5 |Center Re-load
* | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period
* | | |CMPDAT will load to CMPBUF at the center point of a period
* |[8] |WINLDEN0 |Window Load Enable Bits
* | | |0 = PERIOD will load to PBUF at the end point of each period
* | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
* | | |1 = PERIOD will load to PBUF at the end point of each period
* | | |CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set
* | | |The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success.
* |[9] |WINLDEN1 |Window Load Enable Bits
* | | |0 = PERIOD will load to PBUF at the end point of each period
* | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
* | | |1 = PERIOD will load to PBUF at the end point of each period
* | | |CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set
* | | |The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success.
* |[10] |WINLDEN2 |Window Load Enable Bits
* | | |0 = PERIOD will load to PBUF at the end point of each period
* | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
* | | |1 = PERIOD will load to PBUF at the end point of each period
* | | |CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set
* | | |The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success.
* |[11] |WINLDEN3 |Window Load Enable Bits
* | | |0 = PERIOD will load to PBUF at the end point of each period
* | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
* | | |1 = PERIOD will load to PBUF at the end point of each period
* | | |CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set
* | | |The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success.
* |[12] |WINLDEN4 |Window Load Enable Bits
* | | |0 = PERIOD will load to PBUF at the end point of each period
* | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
* | | |1 = PERIOD will load to PBUF at the end point of each period
* | | |CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set
* | | |The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success.
* |[13] |WINLDEN5 |Window Load Enable Bits
* | | |0 = PERIOD will load to PBUF at the end point of each period
* | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
* | | |1 = PERIOD will load to PBUF at the end point of each period
* | | |CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set
* | | |The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success.
* |[16] |IMMLDEN0 |Immediately Load Enable Bits
* | | |0 = PERIOD will load to PBUF at the end point of each period
* | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
* | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT.
* | | |Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid.
* |[17] |IMMLDEN1 |Immediately Load Enable Bits
* | | |0 = PERIOD will load to PBUF at the end point of each period
* | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
* | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT.
* | | |Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid.
* |[18] |IMMLDEN2 |Immediately Load Enable Bits
* | | |0 = PERIOD will load to PBUF at the end point of each period
* | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
* | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT.
* | | |Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid.
* |[19] |IMMLDEN3 |Immediately Load Enable Bits
* | | |0 = PERIOD will load to PBUF at the end point of each period
* | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
* | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT.
* | | |Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid.
* |[20] |IMMLDEN4 |Immediately Load Enable Bits
* | | |0 = PERIOD will load to PBUF at the end point of each period
* | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
* | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT.
* | | |Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid.
* |[21] |IMMLDEN5 |Immediately Load Enable Bits
* | | |0 = PERIOD will load to PBUF at the end point of each period
* | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
* | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT.
* | | |Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid.
* |[24] |GROUPEN |Group Function Enable Bit(S)
* | | |0 = The output waveform of each EPWM channel are independent.
* | | |1 = Unify the EPWM_CH2 and EPWM_CH4 to output the same waveform as EPWM_CH0 and unify the EPWM_CH3 and EPWM_CH5 to output the same waveform as EPWM_CH1.
* |[30] |DBGHALT |ICE Debug Mode Counter Halt (Write Protect)
* | | |If counter halt is enabled, EPWM all counters will keep current value until exit ICE debug mode.
* | | |0 = ICE debug mode counter halt disable.
* | | |1 = ICE debug mode counter halt enable.
* | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
* |[31] |DBGTRIOFF |ICE Debug Mode Acknowledge Disable (Write Protect)
* | | |0 = ICE debug mode acknowledgement effects EPWM output.
* | | |EPWM pin will be forced as tri-state while ICE debug mode acknowledged.
* | | |1 = ICE debug mode acknowledgement disabled.
* | | |EPWM pin will keep output no matter ICE debug mode acknowledged or not.
* | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
* @var EPWM_T::CTL1
* Offset: 0x04 EPWM Control Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1:0] |CNTTYPE0 |EPWM Counter Behavior Type
* | | |00 = Up counter type (supports in capture mode).
* | | |01 = Down count type (supports in capture mode).
* | | |10 = Up-down counter type.
* | | |11 = Reserved.
* |[3:2] |CNTTYPE1 |EPWM Counter Behavior Type
* | | |00 = Up counter type (supports in capture mode).
* | | |01 = Down count type (supports in capture mode).
* | | |10 = Up-down counter type.
* | | |11 = Reserved.
* |[5:4] |CNTTYPE2 |EPWM Counter Behavior Type
* | | |00 = Up counter type (supports in capture mode).
* | | |01 = Down count type (supports in capture mode).
* | | |10 = Up-down counter type.
* | | |11 = Reserved.
* |[7:6] |CNTTYPE3 |EPWM Counter Behavior Type
* | | |00 = Up counter type (supports in capture mode).
* | | |01 = Down count type (supports in capture mode).
* | | |10 = Up-down counter type.
* | | |11 = Reserved.
* |[9:8] |CNTTYPE4 |EPWM Counter Behavior Type
* | | |00 = Up counter type (supports in capture mode).
* | | |01 = Down count type (supports in capture mode).
* | | |10 = Up-down counter type.
* | | |11 = Reserved.
* |[11:10] |CNTTYPE5 |EPWM Counter Behavior Type
* | | |00 = Up counter type (supports in capture mode).
* | | |01 = Down count type (supports in capture mode).
* | | |10 = Up-down counter type.
* | | |11 = Reserved.
* |[16] |CNTMODE0 |EPWM Counter Mode
* | | |0 = Auto-reload mode.
* | | |1 = One-shot mode.
* |[17] |CNTMODE1 |EPWM Counter Mode
* | | |0 = Auto-reload mode.
* | | |1 = One-shot mode.
* |[18] |CNTMODE2 |EPWM Counter Mode
* | | |0 = Auto-reload mode.
* | | |1 = One-shot mode.
* |[19] |CNTMODE3 |EPWM Counter Mode
* | | |0 = Auto-reload mode.
* | | |1 = One-shot mode.
* |[20] |CNTMODE4 |EPWM Counter Mode
* | | |0 = Auto-reload mode.
* | | |1 = One-shot mode.
* |[21] |CNTMODE5 |EPWM Counter Mode
* | | |0 = Auto-reload mode.
* | | |1 = One-shot mode.
* |[24] |OUTMODE0 |EPWM Output Mode
* | | |Each bit n controls the output mode of corresponding EPWM channel n.
* | | |0 = EPWM independent mode.
* | | |1 = EPWM complementary mode.
* | | |Note: When operating in group function, these bits must all set to the same mode.
* |[25] |OUTMODE2 |EPWM Output Mode
* | | |Each bit n controls the output mode of corresponding EPWM channel n.
* | | |0 = EPWM independent mode.
* | | |1 = EPWM complementary mode.
* | | |Note: When operating in group function, these bits must all set to the same mode.
* |[26] |OUTMODE4 |EPWM Output Mode
* | | |Each bit n controls the output mode of corresponding EPWM channel n.
* | | |0 = EPWM independent mode.
* | | |1 = EPWM complementary mode.
* | | |Note: When operating in group function, these bits must all set to the same mode.
* @var EPWM_T::SYNC
* Offset: 0x08 EPWM Synchronization Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |PHSEN0 |SYNC Phase Enable Bits
* | | |0 = EPWM counter disable to load PHS value.
* | | |1 = EPWM counter enable to load PHS value.
* |[1] |PHSEN2 |SYNC Phase Enable Bits
* | | |0 = EPWM counter disable to load PHS value.
* | | |1 = EPWM counter enable to load PHS value.
* |[2] |PHSEN4 |SYNC Phase Enable Bits
* | | |0 = EPWM counter disable to load PHS value.
* | | |1 = EPWM counter enable to load PHS value.
* |[9:8] |SINSRC0 |EPWM0_SYNC_IN Source Selection
* | | |00 = Synchronize source from SYNC_IN or SWSYNC.
* | | |01 = Counter equal to 0.
* | | |10 = Counter equal to EPWM_CMPDATm, m denotes 1, 3, 5.
* | | |11 = SYNC_OUT will not be generated.
* |[11:10] |SINSRC2 |EPWM0_SYNC_IN Source Selection
* | | |00 = Synchronize source from SYNC_IN or SWSYNC.
* | | |01 = Counter equal to 0.
* | | |10 = Counter equal to EPWM_CMPDATm, m denotes 1, 3, 5.
* | | |11 = SYNC_OUT will not be generated.
* |[13:12] |SINSRC4 |EPWM0_SYNC_IN Source Selection
* | | |00 = Synchronize source from SYNC_IN or SWSYNC.
* | | |01 = Counter equal to 0.
* | | |10 = Counter equal to EPWM_CMPDATm, m denotes 1, 3, 5.
* | | |11 = SYNC_OUT will not be generated.
* |[16] |SNFLTEN |EPWM0_SYNC_IN Noise Filter Enable Bits
* | | |0 = Noise filter of input pin EPWM0_SYNC_IN is Disabled.
* | | |1 = Noise filter of input pin EPWM0_SYNC_IN is Enabled.
* |[19:17] |SFLTCSEL |SYNC Edge Detector Filter Clock Selection
* | | |000 = Filter clock = HCLK.
* | | |001 = Filter clock = HCLK/2.
* | | |010 = Filter clock = HCLK/4.
* | | |011 = Filter clock = HCLK/8.
* | | |100 = Filter clock = HCLK/16.
* | | |101 = Filter clock = HCLK/32.
* | | |110 = Filter clock = HCLK/64.
* | | |111 = Filter clock = HCLK/128.
* |[22:20] |SFLTCNT |SYNC Edge Detector Filter Count
* | | |The register bits control the counter number of edge detector.
* |[23] |SINPINV |SYNC Input Pin Inverse
* | | |0 = The state of pin SYNC is passed to the negative edge detector.
* | | |1 = The inversed state of pin SYNC is passed to the negative edge detector.
* |[24] |PHSDIR0 |EPWM Phase Direction Control
* | | |0 = Control EPWM counter count decrement after synchronizing.
* | | |1 = Control EPWM counter count increment after synchronizing.
* |[25] |PHSDIR2 |EPWM Phase Direction Control
* | | |0 = Control EPWM counter count decrement after synchronizing.
* | | |1 = Control EPWM counter count increment after synchronizing.
* |[26] |PHSDIR4 |EPWM Phase Direction Control
* | | |0 = Control EPWM counter count decrement after synchronizing.
* | | |1 = Control EPWM counter count increment after synchronizing.
* @var EPWM_T::SWSYNC
* Offset: 0x0C EPWM Software Control Synchronization Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SWSYNC0 |Software SYNC Function
* | | |When SINSRCn (EPWM_SYNC[13:8]) is selected to 0, SYNC_OUT source is come from SYNC_IN or this bit.
* |[1] |SWSYNC2 |Software SYNC Function
* | | |When SINSRCn (EPWM_SYNC[13:8]) is selected to 0, SYNC_OUT source is come from SYNC_IN or this bit.
* |[2] |SWSYNC4 |Software SYNC Function
* | | |When SINSRCn (EPWM_SYNC[13:8]) is selected to 0, SYNC_OUT source is come from SYNC_IN or this bit.
* @var EPWM_T::CLKSRC
* Offset: 0x10 EPWM Clock Source Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[2:0] |ECLKSRC0 |EPWM_CH01 External Clock Source Select
* | | |000 = EPWMx_CLK, x denotes 0 or 1.
* | | |001 = TIMER0 overflow.
* | | |010 = TIMER1 overflow.
* | | |011 = TIMER2 overflow.
* | | |100 = TIMER3 overflow.
* | | |Others = Reserved.
* |[10:8] |ECLKSRC2 |EPWM_CH23 External Clock Source Select
* | | |000 = EPWMx_CLK, x denotes 0 or 1.
* | | |001 = TIMER0 overflow.
* | | |010 = TIMER1 overflow.
* | | |011 = TIMER2 overflow.
* | | |100 = TIMER3 overflow.
* | | |Others = Reserved.
* |[18:16] |ECLKSRC4 |EPWM_CH45 External Clock Source Select
* | | |000 = EPWMx_CLK, x denotes 0 or 1.
* | | |001 = TIMER0 overflow.
* | | |010 = TIMER1 overflow.
* | | |011 = TIMER2 overflow.
* | | |100 = TIMER3 overflow.
* | | |Others = Reserved.
* @var EPWM_T::CLKPSC[3]
* Offset: 0x14 EPWM Clock Prescale Register 0/1, 2/3, 4/5
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[11:0] |CLKPSC |EPWM Counter Clock Prescale
* | | |The clock of EPWM counter is decided by clock prescaler
* | | |Each EPWM pair share one EPWM counter clock prescaler
* | | |The clock of EPWM counter is divided by (CLKPSC+ 1)
* @var EPWM_T::CNTEN
* Offset: 0x20 EPWM Counter Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CNTEN0 |EPWM Counter Enable Bits
* | | |0 = EPWM Counter and clock prescaler Stop Running.
* | | |1 = EPWM Counter and clock prescaler Start Running.
* |[1] |CNTEN1 |EPWM Counter Enable Bits
* | | |0 = EPWM Counter and clock prescaler Stop Running.
* | | |1 = EPWM Counter and clock prescaler Start Running.
* |[2] |CNTEN2 |EPWM Counter Enable Bits
* | | |0 = EPWM Counter and clock prescaler Stop Running.
* | | |1 = EPWM Counter and clock prescaler Start Running.
* |[3] |CNTEN3 |EPWM Counter Enable Bits
* | | |0 = EPWM Counter and clock prescaler Stop Running.
* | | |1 = EPWM Counter and clock prescaler Start Running.
* |[4] |CNTEN4 |EPWM Counter Enable Bits
* | | |0 = EPWM Counter and clock prescaler Stop Running.
* | | |1 = EPWM Counter and clock prescaler Start Running.
* |[5] |CNTEN5 |EPWM Counter Enable Bits
* | | |0 = EPWM Counter and clock prescaler Stop Running.
* | | |1 = EPWM Counter and clock prescaler Start Running.
* @var EPWM_T::CNTCLR
* Offset: 0x24 EPWM Clear Counter Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CNTCLR0 |Clear EPWM Counter Control Bit
* | | |It is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n.
* | | |0 = No effect.
* | | |1 = Clear 16-bit EPWM counter to 0000H.
* |[1] |CNTCLR1 |Clear EPWM Counter Control Bit
* | | |It is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n.
* | | |0 = No effect.
* | | |1 = Clear 16-bit EPWM counter to 0000H.
* |[2] |CNTCLR2 |Clear EPWM Counter Control Bit
* | | |It is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n.
* | | |0 = No effect.
* | | |1 = Clear 16-bit EPWM counter to 0000H.
* |[3] |CNTCLR3 |Clear EPWM Counter Control Bit
* | | |It is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n.
* | | |0 = No effect.
* | | |1 = Clear 16-bit EPWM counter to 0000H.
* |[4] |CNTCLR4 |Clear EPWM Counter Control Bit
* | | |It is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n.
* | | |0 = No effect.
* | | |1 = Clear 16-bit EPWM counter to 0000H.
* |[5] |CNTCLR5 |Clear EPWM Counter Control Bit
* | | |It is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n.
* | | |0 = No effect.
* | | |1 = Clear 16-bit EPWM counter to 0000H.
* @var EPWM_T::LOAD
* Offset: 0x28 EPWM Load Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |LOAD0 |Re-load EPWM Comparator Register (CMPDAT) Control Bit
* | | |This bit is software write, hardware clear when current EPWM period end.
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Set load window of window loading mode.
* | | |Read Operation:
* | | |0 = No load window is set.
* | | |1 = Load window is set.
* | | |Note: This bit only use in window loading mode, WINLDENn(EPWM_CTL0[13:8]) = 1.
* |[1] |LOAD1 |Re-load EPWM Comparator Register (CMPDAT) Control Bit
* | | |This bit is software write, hardware clear when current EPWM period end.
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Set load window of window loading mode.
* | | |Read Operation:
* | | |0 = No load window is set.
* | | |1 = Load window is set.
* | | |Note: This bit only use in window loading mode, WINLDENn(EPWM_CTL0[13:8]) = 1.
* |[2] |LOAD2 |Re-load EPWM Comparator Register (CMPDAT) Control Bit
* | | |This bit is software write, hardware clear when current EPWM period end.
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Set load window of window loading mode.
* | | |Read Operation:
* | | |0 = No load window is set.
* | | |1 = Load window is set.
* | | |Note: This bit only use in window loading mode, WINLDENn(EPWM_CTL0[13:8]) = 1.
* |[3] |LOAD3 |Re-load EPWM Comparator Register (CMPDAT) Control Bit
* | | |This bit is software write, hardware clear when current EPWM period end.
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Set load window of window loading mode.
* | | |Read Operation:
* | | |0 = No load window is set.
* | | |1 = Load window is set.
* | | |Note: This bit only use in window loading mode, WINLDENn(EPWM_CTL0[13:8]) = 1.
* |[4] |LOAD4 |Re-load EPWM Comparator Register (CMPDAT) Control Bit
* | | |This bit is software write, hardware clear when current EPWM period end.
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Set load window of window loading mode.
* | | |Read Operation:
* | | |0 = No load window is set.
* | | |1 = Load window is set.
* | | |Note: This bit only use in window loading mode, WINLDENn(EPWM_CTL0[13:8]) = 1.
* |[5] |LOAD5 |Re-load EPWM Comparator Register (CMPDAT) Control Bit
* | | |This bit is software write, hardware clear when current EPWM period end.
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Set load window of window loading mode.
* | | |Read Operation:
* | | |0 = No load window is set.
* | | |1 = Load window is set.
* | | |Note: This bit only use in window loading mode, WINLDENn(EPWM_CTL0[13:8]) = 1.
* @var EPWM_T::PERIOD[6]
* Offset: 0x30 EPWM Period Register 0~5
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |PERIOD |EPWM Period Register
* | | |Up-Count mode: In this mode, EPWM counter counts from 0 to PERIOD, and restarts from 0.
* | | |Down-Count mode: In this mode, EPWM counter counts from PERIOD to 0, and restarts from PERIOD.
* | | |EPWM period time = (PERIOD+1) * EPWM_CLK period.
* | | |Up-Down-Count mode: In this mode, EPWM counter counts from 0 to PERIOD, then decrements to 0 and repeats again.
* | | |EPWM period time = 2 * PERIOD * EPWM_CLK period.
* @var EPWM_T::CMPDAT[6]
* Offset: 0x50 EPWM Comparator Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |CMP |EPWM Comparator Register
* | | |CMP use to compare with CNTR to generate EPWM waveform, interrupt and trigger EADC/DAC.
* | | |In independent mode, CMPDAT0~5 denote as 6 independent EPWM_CH0~5 compared point.
* | | |In complementary mode, CMPDAT0, 2, 4 denote as first compared point, and CMPDAT1, 3, 5 denote as second compared point for the corresponding 3 complementary pairs EPWM_CH0 and EPWM_CH1, EPWM_CH2 and EPWM_CH3, EPWM_CH4 and EPWM_CH5.
* @var EPWM_T::DTCTL[3]
* Offset: 0x70 EPWM Dead-Time Control Register 0/1,2/3,4/5
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[11:0] |DTCNT |Dead-time Counter (Write Protect)
* | | |The dead-time can be calculated from the following formula:
* | | |Dead-time = (DTCNT[11:0]+1) * EPWM_CLK period.
* | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
* |[16] |DTEN |Enable Dead-time Insertion for EPWM Pair (EPWM_CH0, EPWM_CH1) (EPWM_CH2, EPWM_CH3) (EPWM_CH4, EPWM_CH5) (Write Protect)
* | | |Dead-time insertion is only active when this pair of complementary EPWM is enabled
* | | |If dead- time insertion is inactive, the outputs of pin pair are complementary without any delay.
* | | |0 = Dead-time insertion Disabled on the pin pair.
* | | |1 = Dead-time insertion Enabled on the pin pair.
* | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
* |[24] |DTCKSEL |Dead-time Clock Select (Write Protect)
* | | |0 = Dead-time clock source from EPWM_CLK.
* | | |1 = Dead-time clock source from prescaler output.
* | | |Note: This register is write protected. Refer toREGWRPROT register.
* @var EPWM_T::PHS[3]
* Offset: 0x80 EPWM Counter Phase Register 0/1,2/3,4/5
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |PHS |EPWM Synchronous Start Phase Bits
* | | |PHS determines the EPWM synchronous start phase value. These bits only use in synchronous function.
* @var EPWM_T::CNT[6]
* Offset: 0x90 EPWM Counter Register 0~5
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |CNT |EPWM Data Register (Read Only)
* | | |User can monitor CNTR to know the current value in 16-bit period counter.
* |[16] |DIRF |EPWM Direction Indicator Flag (Read Only)
* | | |0 = Counter is Down count.
* | | |1 = Counter is UP count.
* @var EPWM_T::WGCTL0
* Offset: 0xB0 EPWM Generation Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1:0] |ZPCTL0 |EPWM Zero Point Control
* | | |00 = Do nothing.
* | | |01 = EPWM zero point output Low.
* | | |10 = EPWM zero point output High.
* | | |11 = EPWM zero point output Toggle.
* | | |EPWM can control output level when EPWM counter count to zero.
* |[3:2] |ZPCTL1 |EPWM Zero Point Control
* | | |00 = Do nothing.
* | | |01 = EPWM zero point output Low.
* | | |10 = EPWM zero point output High.
* | | |11 = EPWM zero point output Toggle.
* | | |EPWM can control output level when EPWM counter count to zero.
* |[5:4] |ZPCTL2 |EPWM Zero Point Control
* | | |00 = Do nothing.
* | | |01 = EPWM zero point output Low.
* | | |10 = EPWM zero point output High.
* | | |11 = EPWM zero point output Toggle.
* | | |EPWM can control output level when EPWM counter count to zero.
* |[7:6] |ZPCTL3 |EPWM Zero Point Control
* | | |00 = Do nothing.
* | | |01 = EPWM zero point output Low.
* | | |10 = EPWM zero point output High.
* | | |11 = EPWM zero point output Toggle.
* | | |EPWM can control output level when EPWM counter count to zero.
* |[9:8] |ZPCTL4 |EPWM Zero Point Control
* | | |00 = Do nothing.
* | | |01 = EPWM zero point output Low.
* | | |10 = EPWM zero point output High.
* | | |11 = EPWM zero point output Toggle.
* | | |EPWM can control output level when EPWM counter count to zero.
* |[11:10] |ZPCTL5 |EPWM Zero Point Control
* | | |00 = Do nothing.
* | | |01 = EPWM zero point output Low.
* | | |10 = EPWM zero point output High.
* | | |11 = EPWM zero point output Toggle.
* | | |EPWM can control output level when EPWM counter count to zero.
* |[17:16] |PRDPCTL0 |EPWM Period (Center) Point Control
* | | |00 = Do nothing.
* | | |01 = EPWM period (center) point output Low.
* | | |10 = EPWM period (center) point output High.
* | | |11 = EPWM period (center) point output Toggle.
* | | |EPWM can control output level when EPWM counter count to (PERIODn+1).
* | | |Note: This bit is center point control when EPWM counter operating in up-down counter type.
* |[19:18] |PRDPCTL1 |EPWM Period (Center) Point Control
* | | |00 = Do nothing.
* | | |01 = EPWM period (center) point output Low.
* | | |10 = EPWM period (center) point output High.
* | | |11 = EPWM period (center) point output Toggle.
* | | |EPWM can control output level when EPWM counter count to (PERIODn+1).
* | | |Note: This bit is center point control when EPWM counter operating in up-down counter type.
* |[21:20] |PRDPCTL2 |EPWM Period (Center) Point Control
* | | |00 = Do nothing.
* | | |01 = EPWM period (center) point output Low.
* | | |10 = EPWM period (center) point output High.
* | | |11 = EPWM period (center) point output Toggle.
* | | |EPWM can control output level when EPWM counter count to (PERIODn+1).
* | | |Note: This bit is center point control when EPWM counter operating in up-down counter type.
* |[23:22] |PRDPCTL3 |EPWM Period (Center) Point Control
* | | |00 = Do nothing.
* | | |01 = EPWM period (center) point output Low.
* | | |10 = EPWM period (center) point output High.
* | | |11 = EPWM period (center) point output Toggle.
* | | |EPWM can control output level when EPWM counter count to (PERIODn+1).
* | | |Note: This bit is center point control when EPWM counter operating in up-down counter type.
* |[25:24] |PRDPCTL4 |EPWM Period (Center) Point Control
* | | |00 = Do nothing.
* | | |01 = EPWM period (center) point output Low.
* | | |10 = EPWM period (center) point output High.
* | | |11 = EPWM period (center) point output Toggle.
* | | |EPWM can control output level when EPWM counter count to (PERIODn+1).
* | | |Note: This bit is center point control when EPWM counter operating in up-down counter type.
* |[27:26] |PRDPCTL5 |EPWM Period (Center) Point Control
* | | |00 = Do nothing.
* | | |01 = EPWM period (center) point output Low.
* | | |10 = EPWM period (center) point output High.
* | | |11 = EPWM period (center) point output Toggle.
* | | |EPWM can control output level when EPWM counter count to (PERIODn+1).
* | | |Note: This bit is center point control when EPWM counter operating in up-down counter type.
* @var EPWM_T::WGCTL1
* Offset: 0xB4 EPWM Generation Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1:0] |CMPUCTL0 |EPWM Compare Up Point Control
* | | |00 = Do nothing.
* | | |01 = EPWM compare up point output Low.
* | | |10 = EPWM compare up point output High.
* | | |11 = EPWM compare up point output Toggle.
* | | |EPWM can control output level when EPWM counter up count to CMPDAT.
* | | |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4.
* |[3:2] |CMPUCTL1 |EPWM Compare Up Point Control
* | | |00 = Do nothing.
* | | |01 = EPWM compare up point output Low.
* | | |10 = EPWM compare up point output High.
* | | |11 = EPWM compare up point output Toggle.
* | | |EPWM can control output level when EPWM counter up count to CMPDAT.
* | | |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4.
* |[5:4] |CMPUCTL2 |EPWM Compare Up Point Control
* | | |00 = Do nothing.
* | | |01 = EPWM compare up point output Low.
* | | |10 = EPWM compare up point output High.
* | | |11 = EPWM compare up point output Toggle.
* | | |EPWM can control output level when EPWM counter up count to CMPDAT.
* | | |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4.
* |[7:6] |CMPUCTL3 |EPWM Compare Up Point Control
* | | |00 = Do nothing.
* | | |01 = EPWM compare up point output Low.
* | | |10 = EPWM compare up point output High.
* | | |11 = EPWM compare up point output Toggle.
* | | |EPWM can control output level when EPWM counter up count to CMPDAT.
* | | |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4.
* |[9:8] |CMPUCTL4 |EPWM Compare Up Point Control
* | | |00 = Do nothing.
* | | |01 = EPWM compare up point output Low.
* | | |10 = EPWM compare up point output High.
* | | |11 = EPWM compare up point output Toggle.
* | | |EPWM can control output level when EPWM counter up count to CMPDAT.
* | | |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4.
* |[11:10] |CMPUCTL5 |EPWM Compare Up Point Control
* | | |00 = Do nothing.
* | | |01 = EPWM compare up point output Low.
* | | |10 = EPWM compare up point output High.
* | | |11 = EPWM compare up point output Toggle.
* | | |EPWM can control output level when EPWM counter up count to CMPDAT.
* | | |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4.
* |[17:16] |CMPDCTL0 |EPWM Compare Down Point Control
* | | |00 = Do nothing.
* | | |01 = EPWM compare down point output Low.
* | | |10 = EPWM compare down point output High.
* | | |11 = EPWM compare down point output Toggle.
* | | |EPWM can control output level when EPWM counter down count to CMPDAT.
* | | |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4.
* |[19:18] |CMPDCTL1 |EPWM Compare Down Point Control
* | | |00 = Do nothing.
* | | |01 = EPWM compare down point output Low.
* | | |10 = EPWM compare down point output High.
* | | |11 = EPWM compare down point output Toggle.
* | | |EPWM can control output level when EPWM counter down count to CMPDAT.
* | | |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4.
* |[21:20] |CMPDCTL2 |EPWM Compare Down Point Control
* | | |00 = Do nothing.
* | | |01 = EPWM compare down point output Low.
* | | |10 = EPWM compare down point output High.
* | | |11 = EPWM compare down point output Toggle.
* | | |EPWM can control output level when EPWM counter down count to CMPDAT.
* | | |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4.
* |[23:22] |CMPDCTL3 |EPWM Compare Down Point Control
* | | |00 = Do nothing.
* | | |01 = EPWM compare down point output Low.
* | | |10 = EPWM compare down point output High.
* | | |11 = EPWM compare down point output Toggle.
* | | |EPWM can control output level when EPWM counter down count to CMPDAT.
* | | |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4.
* |[25:24] |CMPDCTL4 |EPWM Compare Down Point Control
* | | |00 = Do nothing.
* | | |01 = EPWM compare down point output Low.
* | | |10 = EPWM compare down point output High.
* | | |11 = EPWM compare down point output Toggle.
* | | |EPWM can control output level when EPWM counter down count to CMPDAT.
* | | |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4.
* |[27:26] |CMPDCTL5 |EPWM Compare Down Point Control
* | | |00 = Do nothing.
* | | |01 = EPWM compare down point output Low.
* | | |10 = EPWM compare down point output High.
* | | |11 = EPWM compare down point output Toggle.
* | | |EPWM can control output level when EPWM counter down count to CMPDAT.
* | | |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4.
* @var EPWM_T::MSKEN
* Offset: 0xB8 EPWM Mask Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |MSKEN0 |EPWM Mask Enable Bits
* | | |The EPWM output signal will be masked when this bit is enabled
* | | |The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data.
* | | |0 = EPWM output signal is non-masked.
* | | |1 = EPWM output signal is masked and output MSKDATn data.
* |[1] |MSKEN1 |EPWM Mask Enable Bits
* | | |The EPWM output signal will be masked when this bit is enabled
* | | |The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data.
* | | |0 = EPWM output signal is non-masked.
* | | |1 = EPWM output signal is masked and output MSKDATn data.
* |[2] |MSKEN2 |EPWM Mask Enable Bits
* | | |The EPWM output signal will be masked when this bit is enabled
* | | |The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data.
* | | |0 = EPWM output signal is non-masked.
* | | |1 = EPWM output signal is masked and output MSKDATn data.
* |[3] |MSKEN3 |EPWM Mask Enable Bits
* | | |The EPWM output signal will be masked when this bit is enabled
* | | |The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data.
* | | |0 = EPWM output signal is non-masked.
* | | |1 = EPWM output signal is masked and output MSKDATn data.
* |[4] |MSKEN4 |EPWM Mask Enable Bits
* | | |The EPWM output signal will be masked when this bit is enabled
* | | |The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data.
* | | |0 = EPWM output signal is non-masked.
* | | |1 = EPWM output signal is masked and output MSKDATn data.
* |[5] |MSKEN5 |EPWM Mask Enable Bits
* | | |The EPWM output signal will be masked when this bit is enabled
* | | |The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data.
* | | |0 = EPWM output signal is non-masked.
* | | |1 = EPWM output signal is masked and output MSKDATn data.
* @var EPWM_T::MSK
* Offset: 0xBC EPWM Mask Data Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |MSKDAT0 |EPWM Mask Data Bit
* | | |This data bit control the state of EPWMn output pin, if corresponding mask function is enabled.
* | | |0 = Output logic low to EPWM channel n.
* | | |1 = Output logic high to EPWM channel n.
* |[1] |MSKDAT1 |EPWM Mask Data Bit
* | | |This data bit control the state of EPWMn output pin, if corresponding mask function is enabled.
* | | |0 = Output logic low to EPWM channel n.
* | | |1 = Output logic high to EPWM channel n.
* |[2] |MSKDAT2 |EPWM Mask Data Bit
* | | |This data bit control the state of EPWMn output pin, if corresponding mask function is enabled.
* | | |0 = Output logic low to EPWM channel n.
* | | |1 = Output logic high to EPWM channel n.
* |[3] |MSKDAT3 |EPWM Mask Data Bit
* | | |This data bit control the state of EPWMn output pin, if corresponding mask function is enabled.
* | | |0 = Output logic low to EPWM channel n.
* | | |1 = Output logic high to EPWM channel n.
* |[4] |MSKDAT4 |EPWM Mask Data Bit
* | | |This data bit control the state of EPWMn output pin, if corresponding mask function is enabled.
* | | |0 = Output logic low to EPWM channel n.
* | | |1 = Output logic high to EPWM channel n.
* |[5] |MSKDAT5 |EPWM Mask Data Bit
* | | |This data bit control the state of EPWMn output pin, if corresponding mask function is enabled.
* | | |0 = Output logic low to EPWM channel n.
* | | |1 = Output logic high to EPWM channel n.
* @var EPWM_T::BNF
* Offset: 0xC0 EPWM Brake Noise Filter Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |BRK0NFEN |EPWM Brake 0 Noise Filter Enable Bit
* | | |0 = Noise filter of EPWM Brake 0 Disabled.
* | | |1 = Noise filter of EPWM Brake 0 Enabled.
* |[3:1] |BRK0NFSEL |Brake 0 Edge Detector Filter Clock Selection
* | | |000 = Filter clock = HCLK.
* | | |001 = Filter clock = HCLK/2.
* | | |010 = Filter clock = HCLK/4.
* | | |011 = Filter clock = HCLK/8.
* | | |100 = Filter clock = HCLK/16.
* | | |101 = Filter clock = HCLK/32.
* | | |110 = Filter clock = HCLK/64.
* | | |111 = Filter clock = HCLK/128.
* |[6:4] |BRK0FCNT |Brake 0 Edge Detector Filter Count
* | | |The register bits control the Brake0 filter counter to count from 0 to BRK1FCNT.
* |[7] |BRK0PINV |Brake 0 Pin Inverse
* | | |0 = The state of pin EPWMx_BRAKE0 is passed to the negative edge detector.
* | | |1 = The inversed state of pin EPWMx_BRAKE10 is passed to the negative edge detector.
* |[8] |BRK1NFEN |EPWM Brake 1 Noise Filter Enable Bit
* | | |0 = Noise filter of EPWM Brake 1 Disabled.
* | | |1 = Noise filter of EPWM Brake 1 Enabled.
* |[11:9] |BRK1NFSEL |Brake 1 Edge Detector Filter Clock Selection
* | | |000 = Filter clock = HCLK.
* | | |001 = Filter clock = HCLK/2.
* | | |010 = Filter clock = HCLK/4.
* | | |011 = Filter clock = HCLK/8.
* | | |100 = Filter clock = HCLK/16.
* | | |101 = Filter clock = HCLK/32.
* | | |110 = Filter clock = HCLK/64.
* | | |111 = Filter clock = HCLK/128.
* |[14:12] |BRK1FCNT |Brake 1 Edge Detector Filter Count
* | | |The register bits control the Brake1 filter counter to count from 0 to BRK1FCNT.
* |[15] |BRK1PINV |Brake 1 Pin Inverse
* | | |0 = The state of pin EPWMx_BRAKE1 is passed to the negative edge detector.
* | | |1 = The inversed state of pin EPWMx_BRAKE1 is passed to the negative edge detector.
* |[16] |BK0SRC |Brake 0 Pin Source Select
* | | |For EPWM0 setting:
* | | |0 = Brake 0 pin source come from EPWM0_BRAKE0.
* | | |1 = Brake 0 pin source come from EPWM1_BRAKE0.
* | | |For EPWM1 setting:
* | | |0 = Brake 0 pin source come from EPWM1_BRAKE0.
* | | |1 = Brake 0 pin source come from EPWM0_BRAKE0.
* |[24] |BK1SRC |Brake 1 Pin Source Select
* | | |For EPWM0 setting:
* | | |0 = Brake 1 pin source come from EPWM0_BRAKE1.
* | | |1 = Brake 1 pin source come from EPWM1_BRAKE1.
* | | |For EPWM1 setting:
* | | |0 = Brake 1 pin source come from EPWM1_BRAKE1.
* | | |1 = Brake 1 pin source come from EPWM0_BRAKE1.
* @var EPWM_T::FAILBRK
* Offset: 0xC4 EPWM System Fail Brake Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CSSBRKEN |Clock Security System Detection Trigger EPWM Brake Function 0 Enable Bit
* | | |0 = Brake Function triggered by CSS detection Disabled.
* | | |1 = Brake Function triggered by CSS detection Enabled.
* |[1] |BODBRKEN |Brown-out Detection Trigger EPWM Brake Function 0 Enable Bit
* | | |0 = Brake Function triggered by BOD Disabled.
* | | |1 = Brake Function triggered by BOD Enabled.
* |[2] |RAMBRKEN |SRAM Parity Error Detection Trigger EPWM Brake Function 0 Enable Bit
* | | |0 = Brake Function triggered by SRAM parity error detection Disabled.
* | | |1 = Brake Function triggered by SRAM parity error detection Enabled.
* |[3] |CORBRKEN |Core Lockup Detection Trigger EPWM Brake Function 0 Enable Bit
* | | |0 = Brake Function triggered by Core lockup detection Disabled.
* | | |1 = Brake Function triggered by Core lockup detection Enabled.
* @var EPWM_T::BRKCTL[3]
* Offset: 0xC8 EPWM Brake Edge Detect Control Register 0/1,2/3,4/5
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CPO0EBEN |Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)
* | | |0 = ACMP0_O as edge-detect brake source Disabled.
* | | |1 = ACMP0_O as edge-detect brake source Enabled.
* | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
* |[1] |CPO1EBEN |Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)
* | | |0 = ACMP1_O as edge-detect brake source Disabled.
* | | |1 = ACMP1_O as edge-detect brake source Enabled.
* | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
* |[4] |BRKP0EEN |Enable EPWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect)
* | | |0 = EPWMx_BRAKE0 pin as edge-detect brake source Disabled.
* | | |1 = EPWMx_BRAKE0 pin as edge-detect brake source Enabled.
* | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
* |[5] |BRKP1EEN |Enable EPWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect)
* | | |0 = EPWMx_BRAKE1 pin as edge-detect brake source Disabled.
* | | |1 = EPWMx_BRAKE1 pin as edge-detect brake source Enabled.
* | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
* |[7] |SYSEBEN |Enable System Fail As Edge-detect Brake Source (Write Protect)
* | | |0 = System Fail condition as edge-detect brake source Disabled.
* | | |1 = System Fail condition as edge-detect brake source Enabled.
* | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
* |[8] |CPO0LBEN |Enable ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)
* | | |0 = ACMP0_O as level-detect brake source Disabled.
* | | |1 = ACMP0_O as level-detect brake source Enabled.
* | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
* |[9] |CPO1LBEN |Enable ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)
* | | |0 = ACMP1_O as level-detect brake source Disabled.
* | | |1 = ACMP1_O as level-detect brake source Enabled.
* | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
* |[12] |BRKP0LEN |Enable BKP0 Pin As Level-detect Brake Source (Write Protect)
* | | |0 = EPWMx_BRAKE0 pin as level-detect brake source Disabled.
* | | |1 = EPWMx_BRAKE0 pin as level-detect brake source Enabled.
* | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
* |[13] |BRKP1LEN |Enable BKP1 Pin As Level-detect Brake Source (Write Protect)
* | | |0 = EPWMx_BRAKE1 pin as level-detect brake source Disabled.
* | | |1 = EPWMx_BRAKE1 pin as level-detect brake source Enabled.
* | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
* |[15] |SYSLBEN |Enable System Fail As Level-detect Brake Source (Write Protect)
* | | |0 = System Fail condition as level-detect brake source Disabled.
* | | |1 = System Fail condition as level-detect brake source Enabled.
* | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
* |[17:16] |BRKAEVEN |EPWM Brake Action Select for Even Channel (Write Protect)
* | | |00 = EPWMx brake event will not affect even channels output.
* | | |01 = EPWM even channel output tri-state when EPWMx brake event happened.
* | | |10 = EPWM even channel output low level when EPWMx brake event happened.
* | | |11 = EPWM even channel output high level when EPWMx brake event happened.
* | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
* |[19:18] |BRKAODD |EPWM Brake Action Select for Odd Channel (Write Protect)
* | | |00 = EPWMx brake event will not affect odd channels output.
* | | |01 = EPWM odd channel output tri-state when EPWMx brake event happened.
* | | |10 = EPWM odd channel output low level when EPWMx brake event happened.
* | | |11 = EPWM odd channel output high level when EPWMx brake event happened.
* | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
* |[20] |EADCEBEN |Enable EADC Result Monitor (EADCRM) As Edge-detect Brake Source (Write Protect)
* | | |0 = EADCRM as edge-detect brake source Disabled.
* | | |1 = EADCRM as edge-detect brake source Enabled.
* | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
* |[28] |EADCLBEN |Enable EADC Result Monitor (EADCRM) As Level-detect Brake Source (Write Protect)
* | | |0 = EADCRM as level-detect brake source Disabled.
* | | |1 = EADCRM as level-detect brake source Enabled.
* | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
* @var EPWM_T::POLCTL
* Offset: 0xD4 EPWM Pin Polar Inverse Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |PINV0 |EPWM PIN Polar Inverse Control
* | | |The register controls polarity state of EPWM output.
* | | |0 = EPWM output polar inverse Disabled.
* | | |1 = EPWM output polar inverse Enabled.
* |[1] |PINV1 |EPWM PIN Polar Inverse Control
* | | |The register controls polarity state of EPWM output.
* | | |0 = EPWM output polar inverse Disabled.
* | | |1 = EPWM output polar inverse Enabled.
* |[2] |PINV2 |EPWM PIN Polar Inverse Control
* | | |The register controls polarity state of EPWM output.
* | | |0 = EPWM output polar inverse Disabled.
* | | |1 = EPWM output polar inverse Enabled.
* |[3] |PINV3 |EPWM PIN Polar Inverse Control
* | | |The register controls polarity state of EPWM output.
* | | |0 = EPWM output polar inverse Disabled.
* | | |1 = EPWM output polar inverse Enabled.
* |[4] |PINV4 |EPWM PIN Polar Inverse Control
* | | |The register controls polarity state of EPWM output.
* | | |0 = EPWM output polar inverse Disabled.
* | | |1 = EPWM output polar inverse Enabled.
* |[5] |PINV5 |EPWM PIN Polar Inverse Control
* | | |The register controls polarity state of EPWM output.
* | | |0 = EPWM output polar inverse Disabled.
* | | |1 = EPWM output polar inverse Enabled.
* @var EPWM_T::POEN
* Offset: 0xD8 EPWM Output Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |POEN0 |EPWM Pin Output Enable Bits
* | | |0 = EPWM pin at tri-state.
* | | |1 = EPWM pin in output mode.
* |[1] |POEN1 |EPWM Pin Output Enable Bits
* | | |0 = EPWM pin at tri-state.
* | | |1 = EPWM pin in output mode.
* |[2] |POEN2 |EPWM Pin Output Enable Bits
* | | |0 = EPWM pin at tri-state.
* | | |1 = EPWM pin in output mode.
* |[3] |POEN3 |EPWM Pin Output Enable Bits
* | | |0 = EPWM pin at tri-state.
* | | |1 = EPWM pin in output mode.
* |[4] |POEN4 |EPWM Pin Output Enable Bits
* | | |0 = EPWM pin at tri-state.
* | | |1 = EPWM pin in output mode.
* |[5] |POEN5 |EPWM Pin Output Enable Bits
* | | |0 = EPWM pin at tri-state.
* | | |1 = EPWM pin in output mode.
* @var EPWM_T::SWBRK
* Offset: 0xDC EPWM Software Brake Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |BRKETRG0 |EPWM Edge Brake Software Trigger (Write Only) (Write Protect)
* | | |Write 1 to this bit will trigger edge brake, and set BRKEIFn to 1 in EPWM_INTSTS1 register.
* | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
* |[1] |BRKETRG2 |EPWM Edge Brake Software Trigger (Write Only) (Write Protect)
* | | |Write 1 to this bit will trigger edge brake, and set BRKEIFn to 1 in EPWM_INTSTS1 register.
* | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
* |[2] |BRKETRG4 |EPWM Edge Brake Software Trigger (Write Only) (Write Protect)
* | | |Write 1 to this bit will trigger edge brake, and set BRKEIFn to 1 in EPWM_INTSTS1 register.
* | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
* |[8] |BRKLTRG0 |EPWM Level Brake Software Trigger (Write Only) (Write Protect)
* | | |Write 1 to this bit will trigger level brake, and set BRKLIFn to 1 in EPWM_INTSTS1 register.
* | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
* |[9] |BRKLTRG2 |EPWM Level Brake Software Trigger (Write Only) (Write Protect)
* | | |Write 1 to this bit will trigger level brake, and set BRKLIFn to 1 in EPWM_INTSTS1 register.
* | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
* |[10] |BRKLTRG4 |EPWM Level Brake Software Trigger (Write Only) (Write Protect)
* | | |Write 1 to this bit will trigger level brake, and set BRKLIFn to 1 in EPWM_INTSTS1 register.
* | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
* @var EPWM_T::INTEN0
* Offset: 0xE0 EPWM Interrupt Enable Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ZIEN0 |EPWM Zero Point Interrupt Enable Bits
* | | |0 = Zero point interrupt Disabled.
* | | |1 = Zero point interrupt Enabled.
* | | |Note: Odd channels will read always 0 at complementary mode.
* |[1] |ZIEN1 |EPWM Zero Point Interrupt Enable Bits
* | | |0 = Zero point interrupt Disabled.
* | | |1 = Zero point interrupt Enabled.
* | | |Note: Odd channels will read always 0 at complementary mode.
* |[2] |ZIEN2 |EPWM Zero Point Interrupt Enable Bits
* | | |0 = Zero point interrupt Disabled.
* | | |1 = Zero point interrupt Enabled.
* | | |Note: Odd channels will read always 0 at complementary mode.
* |[3] |ZIEN3 |EPWM Zero Point Interrupt Enable Bits
* | | |0 = Zero point interrupt Disabled.
* | | |1 = Zero point interrupt Enabled.
* | | |Note: Odd channels will read always 0 at complementary mode.
* |[4] |ZIEN4 |EPWM Zero Point Interrupt Enable Bits
* | | |0 = Zero point interrupt Disabled.
* | | |1 = Zero point interrupt Enabled.
* | | |Note: Odd channels will read always 0 at complementary mode.
* |[5] |ZIEN5 |EPWM Zero Point Interrupt Enable Bits
* | | |0 = Zero point interrupt Disabled.
* | | |1 = Zero point interrupt Enabled.
* | | |Note: Odd channels will read always 0 at complementary mode.
* |[8] |PIEN0 |EPWM Period Point Interrupt Enable Bits
* | | |0 = Period point interrupt Disabled.
* | | |1 = Period point interrupt Enabled.
* | | |Note1: When up-down counter type period point means center point.
* | | |Note2: Odd channels will read always 0 at complementary mode.
* |[9] |PIEN1 |EPWM Period Point Interrupt Enable Bits
* | | |0 = Period point interrupt Disabled.
* | | |1 = Period point interrupt Enabled.
* | | |Note1: When up-down counter type period point means center point.
* | | |Note2: Odd channels will read always 0 at complementary mode.
* |[10] |PIEN2 |EPWM Period Point Interrupt Enable Bits
* | | |0 = Period point interrupt Disabled.
* | | |1 = Period point interrupt Enabled.
* | | |Note1: When up-down counter type period point means center point.
* | | |Note2: Odd channels will read always 0 at complementary mode.
* |[11] |PIEN3 |EPWM Period Point Interrupt Enable Bits
* | | |0 = Period point interrupt Disabled.
* | | |1 = Period point interrupt Enabled.
* | | |Note1: When up-down counter type period point means center point.
* | | |Note2: Odd channels will read always 0 at complementary mode.
* |[12] |PIEN4 |EPWM Period Point Interrupt Enable Bits
* | | |0 = Period point interrupt Disabled.
* | | |1 = Period point interrupt Enabled.
* | | |Note1: When up-down counter type period point means center point.
* | | |Note2: Odd channels will read always 0 at complementary mode.
* |[13] |PIEN5 |EPWM Period Point Interrupt Enable Bits
* | | |0 = Period point interrupt Disabled.
* | | |1 = Period point interrupt Enabled.
* | | |Note1: When up-down counter type period point means center point.
* | | |Note2: Odd channels will read always 0 at complementary mode.
* |[16] |CMPUIEN0 |EPWM Compare Up Count Interrupt Enable Bits
* | | |0 = Compare up count interrupt Disabled.
* | | |1 = Compare up count interrupt Enabled.
* | | |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4.
* |[17] |CMPUIEN1 |EPWM Compare Up Count Interrupt Enable Bits
* | | |0 = Compare up count interrupt Disabled.
* | | |1 = Compare up count interrupt Enabled.
* | | |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4.
* |[18] |CMPUIEN2 |EPWM Compare Up Count Interrupt Enable Bits
* | | |0 = Compare up count interrupt Disabled.
* | | |1 = Compare up count interrupt Enabled.
* | | |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4.
* |[19] |CMPUIEN3 |EPWM Compare Up Count Interrupt Enable Bits
* | | |0 = Compare up count interrupt Disabled.
* | | |1 = Compare up count interrupt Enabled.
* | | |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4.
* |[20] |CMPUIEN4 |EPWM Compare Up Count Interrupt Enable Bits
* | | |0 = Compare up count interrupt Disabled.
* | | |1 = Compare up count interrupt Enabled.
* | | |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4.
* |[21] |CMPUIEN5 |EPWM Compare Up Count Interrupt Enable Bits
* | | |0 = Compare up count interrupt Disabled.
* | | |1 = Compare up count interrupt Enabled.
* | | |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4.
* |[24] |CMPDIEN0 |EPWM Compare Down Count Interrupt Enable Bits
* | | |0 = Compare down count interrupt Disabled.
* | | |1 = Compare down count interrupt Enabled.
* | | |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4.
* |[25] |CMPDIEN1 |EPWM Compare Down Count Interrupt Enable Bits
* | | |0 = Compare down count interrupt Disabled.
* | | |1 = Compare down count interrupt Enabled.
* | | |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4.
* |[26] |CMPDIEN2 |EPWM Compare Down Count Interrupt Enable Bits
* | | |0 = Compare down count interrupt Disabled.
* | | |1 = Compare down count interrupt Enabled.
* | | |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4.
* |[27] |CMPDIEN3 |EPWM Compare Down Count Interrupt Enable Bits
* | | |0 = Compare down count interrupt Disabled.
* | | |1 = Compare down count interrupt Enabled.
* | | |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4.
* |[28] |CMPDIEN4 |EPWM Compare Down Count Interrupt Enable Bits
* | | |0 = Compare down count interrupt Disabled.
* | | |1 = Compare down count interrupt Enabled.
* | | |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4.
* |[29] |CMPDIEN5 |EPWM Compare Down Count Interrupt Enable Bits
* | | |0 = Compare down count interrupt Disabled.
* | | |1 = Compare down count interrupt Enabled.
* | | |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4.
* @var EPWM_T::INTEN1
* Offset: 0xE4 EPWM Interrupt Enable Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |BRKEIEN0_1|EPWM Edge-detect Brake Interrupt Enable for Channel0/1 (Write Protect)
* | | |0 = Edge-detect Brake interrupt for channel0/1 Disabled.
* | | |1 = Edge-detect Brake interrupt for channel0/1 Enabled.
* | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
* |[1] |BRKEIEN2_3|EPWM Edge-detect Brake Interrupt Enable for Channel2/3 (Write Protect)
* | | |0 = Edge-detect Brake interrupt for channel2/3 Disabled.
* | | |1 = Edge-detect Brake interrupt for channel2/3 Enabled.
* | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
* |[2] |BRKEIEN4_5|EPWM Edge-detect Brake Interrupt Enable for Channel4/5 (Write Protect)
* | | |0 = Edge-detect Brake interrupt for channel4/5 Disabled.
* | | |1 = Edge-detect Brake interrupt for channel4/5 Enabled.
* | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
* |[8] |BRKLIEN0_1|EPWM Level-detect Brake Interrupt Enable for Channel0/1 (Write Protect)
* | | |0 = Level-detect Brake interrupt for channel0/1 Disabled.
* | | |1 = Level-detect Brake interrupt for channel0/1 Enabled.
* | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
* |[9] |BRKLIEN2_3|EPWM Level-detect Brake Interrupt Enable for Channel2/3 (Write Protect)
* | | |0 = Level-detect Brake interrupt for channel2/3 Disabled.
* | | |1 = Level-detect Brake interrupt for channel2/3 Enabled.
* | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
* |[10] |BRKLIEN4_5|EPWM Level-detect Brake Interrupt Enable for Channel4/5 (Write Protect)
* | | |0 = Level-detect Brake interrupt for channel4/5 Disabled.
* | | |1 = Level-detect Brake interrupt for channel4/5 Enabled.
* | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
* @var EPWM_T::INTSTS0
* Offset: 0xE8 EPWM Interrupt Flag Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ZIF0 |EPWM Zero Point Interrupt Flag
* | | |This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero.
* |[1] |ZIF1 |EPWM Zero Point Interrupt Flag
* | | |This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero.
* |[2] |ZIF2 |EPWM Zero Point Interrupt Flag
* | | |This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero.
* |[3] |ZIF3 |EPWM Zero Point Interrupt Flag
* | | |This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero.
* |[4] |ZIF4 |EPWM Zero Point Interrupt Flag
* | | |This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero.
* |[5] |ZIF5 |EPWM Zero Point Interrupt Flag
* | | |This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero.
* |[8] |PIF0 |EPWM Period Point Interrupt Flag
* | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIODn, software can write 1 to clear this bit to zero.
* |[9] |PIF1 |EPWM Period Point Interrupt Flag
* | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIODn, software can write 1 to clear this bit to zero.
* |[10] |PIF2 |EPWM Period Point Interrupt Flag
* | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIODn, software can write 1 to clear this bit to zero.
* |[11] |PIF3 |EPWM Period Point Interrupt Flag
* | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIODn, software can write 1 to clear this bit to zero.
* |[12] |PIF4 |EPWM Period Point Interrupt Flag
* | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIODn, software can write 1 to clear this bit to zero.
* |[13] |PIF5 |EPWM Period Point Interrupt Flag
* | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIODn, software can write 1 to clear this bit to zero.
* |[16] |CMPUIF0 |EPWM Compare Up Count Interrupt Flag
* | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it.
* | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
* | | |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4.
* |[17] |CMPUIF1 |EPWM Compare Up Count Interrupt Flag
* | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it.
* | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
* | | |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4.
* |[18] |CMPUIF2 |EPWM Compare Up Count Interrupt Flag
* | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it.
* | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
* | | |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4.
* |[19] |CMPUIF3 |EPWM Compare Up Count Interrupt Flag
* | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it.
* | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
* | | |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4.
* |[20] |CMPUIF4 |EPWM Compare Up Count Interrupt Flag
* | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it.
* | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
* | | |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4.
* |[21] |CMPUIF5 |EPWM Compare Up Count Interrupt Flag
* | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it.
* | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
* | | |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4.
* |[24] |CMPDIF0 |EPWM Compare Down Count Interrupt Flag
* | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it.
* | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
* | | |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4.
* |[25] |CMPDIF1 |EPWM Compare Down Count Interrupt Flag
* | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it.
* | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
* | | |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4.
* |[26] |CMPDIF2 |EPWM Compare Down Count Interrupt Flag
* | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it.
* | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
* | | |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4.
* |[27] |CMPDIF3 |EPWM Compare Down Count Interrupt Flag
* | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it.
* | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
* | | |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4.
* |[28] |CMPDIF4 |EPWM Compare Down Count Interrupt Flag
* | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it.
* | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
* | | |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4.
* |[29] |CMPDIF5 |EPWM Compare Down Count Interrupt Flag
* | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it.
* | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
* | | |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4.
* @var EPWM_T::INTSTS1
* Offset: 0xEC EPWM Interrupt Flag Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |BRKEIF0 |EPWM Channel0 Edge-detect Brake Interrupt Flag (Write Protect)
* | | |0 = EPWM channel0 edge-detect brake event do not happened.
* | | |1 = When EPWM channel0 edge-detect brake event happened, this bit is set to 1, writing 1 to clear.
* | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
* |[1] |BRKEIF1 |EPWM Channel1 Edge-detect Brake Interrupt Flag (Write Protect)
* | | |0 = EPWM channel1 edge-detect brake event do not happened.
* | | |1 = When EPWM channel1 edge-detect brake event happened, this bit is set to 1, writing 1 to clear.
* | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
* |[2] |BRKEIF2 |EPWM Channel2 Edge-detect Brake Interrupt Flag (Write Protect)
* | | |0 = EPWM channel2 edge-detect brake event do not happened.
* | | |1 = When EPWM channel2 edge-detect brake event happened, this bit is set to 1, writing 1 to clear.
* | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
* |[3] |BRKEIF3 |EPWM Channel3 Edge-detect Brake Interrupt Flag (Write Protect)
* | | |0 = EPWM channel3 edge-detect brake event do not happened.
* | | |1 = When EPWM channel3 edge-detect brake event happened, this bit is set to 1, writing 1 to clear.
* | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
* |[4] |BRKEIF4 |EPWM Channel4 Edge-detect Brake Interrupt Flag (Write Protect)
* | | |0 = EPWM channel4 edge-detect brake event do not happened.
* | | |1 = When EPWM channel4 edge-detect brake event happened, this bit is set to 1, writing 1 to clear.
* | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
* |[5] |BRKEIF5 |EPWM Channel5 Edge-detect Brake Interrupt Flag (Write Protect)
* | | |0 = EPWM channel5 edge-detect brake event do not happened.
* | | |1 = When EPWM channel5 edge-detect brake event happened, this bit is set to 1, writing 1 to clear.
* | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
* |[8] |BRKLIF0 |EPWM Channel0 Level-detect Brake Interrupt Flag (Write Protect)
* | | |0 = EPWM channel0 level-detect brake event do not happened.
* | | |1 = When EPWM channel0 level-detect brake event happened, this bit is set to 1, writing 1 to clear.
* | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
* |[9] |BRKLIF1 |EPWM Channel1 Level-detect Brake Interrupt Flag (Write Protect)
* | | |0 = EPWM channel1 level-detect brake event do not happened.
* | | |1 = When EPWM channel1 level-detect brake event happened, this bit is set to 1, writing 1 to clear.
* | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
* |[10] |BRKLIF2 |EPWM Channel2 Level-detect Brake Interrupt Flag (Write Protect)
* | | |0 = EPWM channel2 level-detect brake event do not happened.
* | | |1 = When EPWM channel2 level-detect brake event happened, this bit is set to 1, writing 1 to clear.
* | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
* |[11] |BRKLIF3 |EPWM Channel3 Level-detect Brake Interrupt Flag (Write Protect)
* | | |0 = EPWM channel3 level-detect brake event do not happened.
* | | |1 = When EPWM channel3 level-detect brake event happened, this bit is set to 1, writing 1 to clear.
* | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
* |[12] |BRKLIF4 |EPWM Channel4 Level-detect Brake Interrupt Flag (Write Protect)
* | | |0 = EPWM channel4 level-detect brake event do not happened.
* | | |1 = When EPWM channel4 level-detect brake event happened, this bit is set to 1, writing 1 to clear.
* | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
* |[13] |BRKLIF5 |EPWM Channel5 Level-detect Brake Interrupt Flag (Write Protect)
* | | |0 = EPWM channel5 level-detect brake event do not happened.
* | | |1 = When EEPWM channel5 level-detect brake event happened, this bit is set to 1, writing 1 to clear.
* | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
* |[16] |BRKESTS0 |EPWM Channel0 Edge-detect Brake Status (Read Only)
* | | |0 = EPWM channel0 edge-detect brake state is released.
* | | |1 = When EPWM channel0 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel0 at brake state, writing 1 to clear.
* |[17] |BRKESTS1 |EPWM Channel1 Edge-detect Brake Status (Read Only)
* | | |0 = EPWM channel1 edge-detect brake state is released.
* | | |1 = When EPWM channel1 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel1 at brake state, writing 1 to clear.
* |[18] |BRKESTS2 |EPWM Channel2 Edge-detect Brake Status (Read Only)
* | | |0 = EPWM channel2 edge-detect brake state is released.
* | | |1 = When EPWM channel2 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel2 at brake state, writing 1 to clear.
* |[19] |BRKESTS3 |EPWM Channel3 Edge-detect Brake Status (Read Only)
* | | |0 = EPWM channel3 edge-detect brake state is released.
* | | |1 = When EPWM channel3 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel3 at brake state, writing 1 to clear.
* |[20] |BRKESTS4 |EPWM Channel4 Edge-detect Brake Status (Read Only)
* | | |0 = EPWM channel4 edge-detect brake state is released.
* | | |1 = When EPWM channel4 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel4 at brake state, writing 1 to clear.
* |[21] |BRKESTS5 |EPWM Channel5 Edge-detect Brake Status (Read Only)
* | | |0 = EPWM channel5 edge-detect brake state is released.
* | | |1 = When EPWM channel5 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel5 at brake state, writing 1 to clear.
* |[24] |BRKLSTS0 |EPWM Channel0 Level-detect Brake Status (Read Only)
* | | |0 = EPWM channel0 level-detect brake state is released.
* | | |1 = When EPWM channel0 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel0 at brake state.
* | | |Note: This bit is read only and auto cleared by hardware
* | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished
* | | |The EPWM waveform will start output from next full EPWM period.
* |[25] |BRKLSTS1 |EPWM Channel1 Level-detect Brake Status (Read Only)
* | | |0 = EPWM channel1 level-detect brake state is released.
* | | |1 = When EPWM channel1 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel1 at brake state.
* | | |Note: This bit is read only and auto cleared by hardware
* | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished
* | | |The EPWM waveform will start output from next full EPWM period.
* |[26] |BRKLSTS2 |EPWM Channel2 Level-detect Brake Status (Read Only)
* | | |0 = EPWM channel2 level-detect brake state is released.
* | | |1 = When EPWM channel2 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel2 at brake state.
* | | |Note: This bit is read only and auto cleared by hardware
* | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished
* | | |The EPWM waveform will start output from next full EPWM period.
* |[27] |BRKLSTS3 |EPWM Channel3 Level-detect Brake Status (Read Only)
* | | |0 = EPWM channel3 level-detect brake state is released.
* | | |1 = When EPWM channel3 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel3 at brake state.
* | | |Note: This bit is read only and auto cleared by hardware
* | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished
* | | |The EPWM waveform will start output from next full EPWM period.
* |[28] |BRKLSTS4 |EPWM Channel4 Level-detect Brake Status (Read Only)
* | | |0 = EPWM channel4 level-detect brake state is released.
* | | |1 = When EPWM channel4 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel4 at brake state.
* | | |Note: This bit is read only and auto cleared by hardware
* | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished
* | | |The EPWM waveform will start output from next full EPWM period.
* |[29] |BRKLSTS5 |EPWM Channel5 Level-detect Brake Status (Read Only)
* | | |0 = EPWM channel5 level-detect brake state is released.
* | | |1 = When EPWM channel5 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel5 at brake state.
* | | |Note: This bit is read only and auto cleared by hardware
* | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished
* | | |The EPWM waveform will start output from next full EPWM period.
* @var EPWM_T::DACTRGEN
* Offset: 0xF4 EPWM Trigger DAC Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ZTE0 |EPWM Zero Point Trigger DAC Enable Bits
* | | |EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1.
* | | |0 = EPWM period point trigger DAC function Disabled.
* | | |1 = EPWM period point trigger DAC function Enabled.
* |[1] |ZTE1 |EPWM Zero Point Trigger DAC Enable Bits
* | | |EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1.
* | | |0 = EPWM period point trigger DAC function Disabled.
* | | |1 = EPWM period point trigger DAC function Enabled.
* |[2] |ZTE2 |EPWM Zero Point Trigger DAC Enable Bits
* | | |EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1.
* | | |0 = EPWM period point trigger DAC function Disabled.
* | | |1 = EPWM period point trigger DAC function Enabled.
* |[3] |ZTE3 |EPWM Zero Point Trigger DAC Enable Bits
* | | |EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1.
* | | |0 = EPWM period point trigger DAC function Disabled.
* | | |1 = EPWM period point trigger DAC function Enabled.
* |[4] |ZTE4 |EPWM Zero Point Trigger DAC Enable Bits
* | | |EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1.
* | | |0 = EPWM period point trigger DAC function Disabled.
* | | |1 = EPWM period point trigger DAC function Enabled.
* |[5] |ZTE5 |EPWM Zero Point Trigger DAC Enable Bits
* | | |EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1.
* | | |0 = EPWM period point trigger DAC function Disabled.
* | | |1 = EPWM period point trigger DAC function Enabled.
* |[8] |PTE0 |EPWM Period Point Trigger DAC Enable Bits
* | | |EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1.
* | | |0 = EPWM period point trigger DAC function Disabled.
* | | |1 = EPWM period point trigger DAC function Enabled.
* |[9] |PTE1 |EPWM Period Point Trigger DAC Enable Bits
* | | |EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1.
* | | |0 = EPWM period point trigger DAC function Disabled.
* | | |1 = EPWM period point trigger DAC function Enabled.
* |[10] |PTE2 |EPWM Period Point Trigger DAC Enable Bits
* | | |EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1.
* | | |0 = EPWM period point trigger DAC function Disabled.
* | | |1 = EPWM period point trigger DAC function Enabled.
* |[11] |PTE3 |EPWM Period Point Trigger DAC Enable Bits
* | | |EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1.
* | | |0 = EPWM period point trigger DAC function Disabled.
* | | |1 = EPWM period point trigger DAC function Enabled.
* |[12] |PTE4 |EPWM Period Point Trigger DAC Enable Bits
* | | |EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1.
* | | |0 = EPWM period point trigger DAC function Disabled.
* | | |1 = EPWM period point trigger DAC function Enabled.
* |[13] |PTE5 |EPWM Period Point Trigger DAC Enable Bits
* | | |EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1.
* | | |0 = EPWM period point trigger DAC function Disabled.
* | | |1 = EPWM period point trigger DAC function Enabled.
* |[16] |CUTRGE0 |EPWM Compare Up Count Point Trigger DAC Enable Bits
* | | |EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1.
* | | |0 = EPWM Compare Up point trigger DAC function Disabled.
* | | |1 = EPWM Compare Up point trigger DAC function Enabled.
* | | |Note1: This bit should keep at 0 when EPWM counter operating in down counter type.
* | | |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4.
* |[17] |CUTRGE1 |EPWM Compare Up Count Point Trigger DAC Enable Bits
* | | |EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1.
* | | |0 = EPWM Compare Up point trigger DAC function Disabled.
* | | |1 = EPWM Compare Up point trigger DAC function Enabled.
* | | |Note1: This bit should keep at 0 when EPWM counter operating in down counter type.
* | | |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4.
* |[18] |CUTRGE2 |EPWM Compare Up Count Point Trigger DAC Enable Bits
* | | |EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1.
* | | |0 = EPWM Compare Up point trigger DAC function Disabled.
* | | |1 = EPWM Compare Up point trigger DAC function Enabled.
* | | |Note1: This bit should keep at 0 when EPWM counter operating in down counter type.
* | | |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4.
* |[19] |CUTRGE3 |EPWM Compare Up Count Point Trigger DAC Enable Bits
* | | |EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1.
* | | |0 = EPWM Compare Up point trigger DAC function Disabled.
* | | |1 = EPWM Compare Up point trigger DAC function Enabled.
* | | |Note1: This bit should keep at 0 when EPWM counter operating in down counter type.
* | | |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4.
* |[20] |CUTRGE4 |EPWM Compare Up Count Point Trigger DAC Enable Bits
* | | |EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1.
* | | |0 = EPWM Compare Up point trigger DAC function Disabled.
* | | |1 = EPWM Compare Up point trigger DAC function Enabled.
* | | |Note1: This bit should keep at 0 when EPWM counter operating in down counter type.
* | | |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4.
* |[21] |CUTRGE5 |EPWM Compare Up Count Point Trigger DAC Enable Bits
* | | |EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1.
* | | |0 = EPWM Compare Up point trigger DAC function Disabled.
* | | |1 = EPWM Compare Up point trigger DAC function Enabled.
* | | |Note1: This bit should keep at 0 when EPWM counter operating in down counter type.
* | | |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4.
* |[24] |CDTRGE0 |EPWM Compare Down Count Point Trigger DAC Enable Bits
* | | |EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1.
* | | |0 = EPWM Compare Down count point trigger DAC function Disabled.
* | | |1 = EPWM Compare Down count point trigger DAC function Enabled.
* | | |Note1: This bit should keep at 0 when EPWM counter operating in up counter type.
* | | |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4.
* |[25] |CDTRGE1 |EPWM Compare Down Count Point Trigger DAC Enable Bits
* | | |EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1.
* | | |0 = EPWM Compare Down count point trigger DAC function Disabled.
* | | |1 = EPWM Compare Down count point trigger DAC function Enabled.
* | | |Note1: This bit should keep at 0 when EPWM counter operating in up counter type.
* | | |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4.
* |[26] |CDTRGE2 |EPWM Compare Down Count Point Trigger DAC Enable Bits
* | | |EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1.
* | | |0 = EPWM Compare Down count point trigger DAC function Disabled.
* | | |1 = EPWM Compare Down count point trigger DAC function Enabled.
* | | |Note1: This bit should keep at 0 when EPWM counter operating in up counter type.
* | | |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4.
* |[27] |CDTRGE3 |EPWM Compare Down Count Point Trigger DAC Enable Bits
* | | |EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1.
* | | |0 = EPWM Compare Down count point trigger DAC function Disabled.
* | | |1 = EPWM Compare Down count point trigger DAC function Enabled.
* | | |Note1: This bit should keep at 0 when EPWM counter operating in up counter type.
* | | |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4.
* |[28] |CDTRGE4 |EPWM Compare Down Count Point Trigger DAC Enable Bits
* | | |EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1.
* | | |0 = EPWM Compare Down count point trigger DAC function Disabled.
* | | |1 = EPWM Compare Down count point trigger DAC function Enabled.
* | | |Note1: This bit should keep at 0 when EPWM counter operating in up counter type.
* | | |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4.
* |[29] |CDTRGE5 |EPWM Compare Down Count Point Trigger DAC Enable Bits
* | | |EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1.
* | | |0 = EPWM Compare Down count point trigger DAC function Disabled.
* | | |1 = EPWM Compare Down count point trigger DAC function Enabled.
* | | |Note1: This bit should keep at 0 when EPWM counter operating in up counter type.
* | | |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4.
* @var EPWM_T::EADCTS0
* Offset: 0xF8 EPWM Trigger EADC Source Select Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |TRGSEL0 |EPWM_CH0 Trigger EADC Source Select
* | | |0000 = EPWM_CH0 zero point.
* | | |0001 = EPWM_CH0 period point.
* | | |0010 = EPWM_CH0 zero or period point.
* | | |0011 = EPWM_CH0 up-count CMPDAT point.
* | | |0100 = EPWM_CH0 down-count CMPDAT point.
* | | |0101 = EPWM_CH1 zero point.
* | | |0110 = EPWM_CH1 period point.
* | | |0111 = EPWM_CH1 zero or period point.
* | | |1000 = EPWM_CH1 up-count CMPDAT point.
* | | |1001 = EPWM_CH1 down-count CMPDAT point.
* | | |1010 = EPWM_CH0 up-count free CMPDAT point.
* | | |1011 = EPWM_CH0 down-count free CMPDAT point.
* | | |1100 = EPWM_CH2 up-count free CMPDAT point.
* | | |1101 = EPWM_CH2 down-count free CMPDAT point.
* | | |1110 = EPWM_CH4 up-count free CMPDAT point.
* | | |1111 = EPWM_CH4 down-count free CMPDAT point.
* |[7] |TRGEN0 |EPWM_CH0 Trigger EADC enable bit
* |[11:8] |TRGSEL1 |EPWM_CH1 Trigger EADC Source Select
* | | |0000 = EPWM_CH0 zero point.
* | | |0001 = EPWM_CH0 period point.
* | | |0010 = EPWM_CH0 zero or period point.
* | | |0011 = EPWM_CH0 up-count CMPDAT point.
* | | |0100 = EPWM_CH0 down-count CMPDAT point.
* | | |0101 = EPWM_CH1 zero point.
* | | |0110 = EPWM_CH1 period point.
* | | |0111 = EPWM_CH1 zero or period point.
* | | |1000 = EPWM_CH1 up-count CMPDAT point.
* | | |1001 = EPWM_CH1 down-count CMPDAT point.
* | | |1010 = EPWM_CH0 up-count free CMPDAT point.
* | | |1011 = EPWM_CH0 down-count free CMPDAT point.
* | | |1100 = EPWM_CH2 up-count free CMPDAT point.
* | | |1101 = EPWM_CH2 down-count free CMPDAT point.
* | | |1110 = EPWM_CH4 up-count free CMPDAT point.
* | | |1111 = EPWM_CH4 down-count free CMPDAT point.
* |[15] |TRGEN1 |EPWM_CH1 Trigger EADC enable bit
* |[19:16] |TRGSEL2 |EPWM_CH2 Trigger EADC Source Select
* | | |0000 = EPWM_CH2 zero point.
* | | |0001 = EPWM_CH2 period point.
* | | |0010 = EPWM_CH2 zero or period point.
* | | |0011 = EPWM_CH2 up-count CMPDAT point.
* | | |0100 = EPWM_CH2 down-count CMPDAT point.
* | | |0101 = EPWM_CH3 zero point.
* | | |0110 = EPWM_CH3 period point.
* | | |0111 = EPWM_CH3 zero or period point.
* | | |1000 = EPWM_CH3 up-count CMPDAT point.
* | | |1001 = EPWM_CH3 down-count CMPDAT point.
* | | |1010 = EPWM_CH0 up-count free CMPDAT point.
* | | |1011 = EPWM_CH0 down-count free CMPDAT point.
* | | |1100 = EPWM_CH2 up-count free CMPDAT point.
* | | |1101 = EPWM_CH2 down-count free CMPDAT point.
* | | |1110 = EPWM_CH4 up-count free CMPDAT point.
* | | |1111 = EPWM_CH4 down-count free CMPDAT point.
* |[23] |TRGEN2 |EPWM_CH2 Trigger EADC enable bit
* |[27:24] |TRGSEL3 |EPWM_CH3 Trigger EADC Source Select
* | | |0000 = EPWM_CH2 zero point.
* | | |0001 = EPWM_CH2 period point.
* | | |0010 = EPWM_CH2 zero or period point.
* | | |0011 = EPWM_CH2 up-count CMPDAT point.
* | | |0100 = EPWM_CH2 down-count CMPDAT point.
* | | |0101 = EPWM_CH3 zero point.
* | | |0110 = EPWM_CH3 period point.
* | | |0111 = EPWM_CH3 zero or period point.
* | | |1000 = EPWM_CH3 up-count CMPDAT point.
* | | |1001 = EPWM_CH3 down-count CMPDAT point.
* | | |1010 = EPWM_CH0 up-count free CMPDAT point.
* | | |1011 = EPWM_CH0 down-count free CMPDAT point.
* | | |1100 = EPWM_CH2 up-count free CMPDAT point.
* | | |1101 = EPWM_CH2 down-count free CMPDAT point.
* | | |1110 = EPWM_CH4 up-count free CMPDAT point.
* | | |1111 = EPWM_CH4 down-count free CMPDAT point.
* |[31] |TRGEN3 |EPWM_CH3 Trigger EADC enable bit
* @var EPWM_T::EADCTS1
* Offset: 0xFC EPWM Trigger EADC Source Select Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |TRGSEL4 |EPWM_CH4 Trigger EADC Source Select
* | | |0000 = EPWM_CH4 zero point.
* | | |0001 = EPWM_CH4 period point.
* | | |0010 = EPWM_CH4 zero or period point.
* | | |0011 = EPWM_CH4 up-count CMPDAT point.
* | | |0100 = EPWM_CH4 down-count CMPDAT point.
* | | |0101 = EPWM_CH5 zero point.
* | | |0110 = EPWM_CH5 period point.
* | | |0111 = EPWM_CH5 zero or period point.
* | | |1000 = EPWM_CH5 up-count CMPDAT point.
* | | |1001 = EPWM_CH5 down-count CMPDAT point.
* | | |1010 = EPWM_CH0 up-count free CMPDAT point.
* | | |1011 = EPWM_CH0 down-count free CMPDAT point.
* | | |1100 = EPWM_CH2 up-count free CMPDAT point.
* | | |1101 = EPWM_CH2 down-count free CMPDAT point.
* | | |1110 = EPWM_CH4 up-count free CMPDAT point.
* | | |1111 = EPWM_CH4 down-count free CMPDAT point.
* |[7] |TRGEN4 |EPWM_CH4 Trigger EADC enable bit
* |[11:8] |TRGSEL5 |EPWM_CH5 Trigger EADC Source Select
* | | |0000 = EPWM_CH4 zero point.
* | | |0001 = EPWM_CH4 period point.
* | | |0010 = EPWM_CH4 zero or period point.
* | | |0011 = EPWM_CH4 up-count CMPDAT point.
* | | |0100 = EPWM_CH4 down-count CMPDAT point.
* | | |0101 = EPWM_CH5 zero point.
* | | |0110 = EPWM_CH5 period point.
* | | |0111 = EPWM_CH5 zero or period point.
* | | |1000 = EPWM_CH5 up-count CMPDAT point.
* | | |1001 = EPWM_CH5 down-count CMPDAT point.
* | | |1010 = EPWM_CH0 up-count free CMPDAT point.
* | | |1011 = EPWM_CH0 down-count free CMPDAT point.
* | | |1100 = EPWM_CH2 up-count free CMPDAT point.
* | | |1101 = EPWM_CH2 down-count free CMPDAT point.
* | | |1110 = EPWM_CH4 up-count free CMPDAT point.
* | | |1111 = EPWM_CH4 down-count free CMPDAT point.
* |[15] |TRGEN5 |EPWM_CH5 Trigger EADC enable bit
* @var EPWM_T::FTCMPDAT[3]
* Offset: 0x100 EPWM Free Trigger Compare Register 0/1,2/3,4/5
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |FTCMP |EPWM Free Trigger Compare Register
* | | |FTCMP use to compare with even CNTR to trigger EADC
* | | |FTCMPDAT0, 2, 4 corresponding complementary pairs EPWM_CH0 and EPWM_CH1, EPWM_CH2 and EPWM_CH3, EPWM_CH4 and EPWM_CH5.
* @var EPWM_T::SSCTL
* Offset: 0x110 EPWM Synchronous Start Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SSEN0 |EPWM Synchronous Start Function Enable Bits
* | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN).
* | | |0 = EPWM synchronous start function Disabled.
* | | |1 = EPWM synchronous start function Enabled.
* |[1] |SSEN1 |EPWM Synchronous Start Function Enable Bits
* | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN).
* | | |0 = EPWM synchronous start function Disabled.
* | | |1 = EPWM synchronous start function Enabled.
* |[2] |SSEN2 |EPWM Synchronous Start Function Enable Bits
* | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN).
* | | |0 = EPWM synchronous start function Disabled.
* | | |1 = EPWM synchronous start function Enabled.
* |[3] |SSEN3 |EPWM Synchronous Start Function Enable Bits
* | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN).
* | | |0 = EPWM synchronous start function Disabled.
* | | |1 = EPWM synchronous start function Enabled.
* |[4] |SSEN4 |EPWM Synchronous Start Function Enable Bits
* | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN).
* | | |0 = EPWM synchronous start function Disabled.
* | | |1 = EPWM synchronous start function Enabled.
* |[5] |SSEN5 |EPWM Synchronous Start Function Enable Bits
* | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN).
* | | |0 = EPWM synchronous start function Disabled.
* | | |1 = EPWM synchronous start function Enabled.
* |[9:8] |SSRC |EPWM Synchronous Start Source Select Bits
* | | |00 = Synchronous start source come from EPWM0.
* | | |01 = Synchronous start source come from EPWM1.
* | | |10 = Synchronous start source come from BPWM0.
* | | |11 = Synchronous start source come from BPWM1.
* @var EPWM_T::SSTRG
* Offset: 0x114 EPWM Synchronous Start Trigger Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CNTSEN |EPWM Counter Synchronous Start Enable (Write Only)
* | | |PMW counter synchronous enable function is used to make selected EPWM channels (include EPWM0_CHx and EPWM1_CHx) start counting at the same time.
* | | |Writing this bit to 1 will also set the counter enable bit (CNTENn, n denotes channel 0 to 5) if correlated EPWM channel counter synchronous start function is enabled.
* @var EPWM_T::LEBCTL
* Offset: 0x118 EPWM Leading Edge Blanking Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |LEBEN |EPWM Leading Edge Blanking Enable Bit
* | | |0 = EPWM Leading Edge Blanking Disabled.
* | | |1 = EPWM Leading Edge Blanking Enabled.
* |[8] |SRCEN0 |EPWM Leading Edge Blanking Source From EPWM_CH0 Enable Bit
* | | |0 = EPWM Leading Edge Blanking Source from EPWM_CH0 Disabled.
* | | |1 = EPWM Leading Edge Blanking Source from EPWM_CH0 Enabled.
* |[9] |SRCEN2 |EPWM Leading Edge Blanking Source From EPWM_CH2 Enable Bit
* | | |0 = EPWM Leading Edge Blanking Source from EPWM_CH2 Disabled.
* | | |1 = EPWM Leading Edge Blanking Source from EPWM_CH2 Enabled.
* |[10] |SRCEN4 |EPWM Leading Edge Blanking Source From EPWM_CH4 Enable Bit
* | | |0 = EPWM Leading Edge Blanking Source from EPWM_CH4 Disabled.
* | | |1 = EPWM Leading Edge Blanking Source from EPWM_CH4 Enabled.
* |[17:16] |TRGTYPE |EPWM Leading Edge Blanking Trigger Type
* | | |0 = When detect leading edge blanking source rising edge, blanking counter start counting.
* | | |1 = When detect leading edge blanking source falling edge, blanking counter start counting.
* | | |2 = When detect leading edge blanking source rising or falling edge, blanking counter start counting.
* | | |3 = Reserved.
* @var EPWM_T::LEBCNT
* Offset: 0x11C EPWM Leading Edge Blanking Counter Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[8:0] |LEBCNT |EPWM Leading Edge Blanking Counter
* | | |This counter value decides leading edge blanking window size
* | | |Blanking window size = LEBCNT+1, and LEB counter clock base is ECLK.
* @var EPWM_T::STATUS
* Offset: 0x120 EPWM Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CNTMAXF0 |Time-base Counter Equal to 0xFFFF Latched Flag
* | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF.
* | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit.
* |[1] |CNTMAXF1 |Time-base Counter Equal to 0xFFFF Latched Flag
* | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF.
* | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit.
* |[2] |CNTMAXF2 |Time-base Counter Equal to 0xFFFF Latched Flag
* | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF.
* | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit.
* |[3] |CNTMAXF3 |Time-base Counter Equal to 0xFFFF Latched Flag
* | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF.
* | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit.
* |[4] |CNTMAXF4 |Time-base Counter Equal to 0xFFFF Latched Flag
* | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF.
* | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit.
* |[5] |CNTMAXF5 |Time-base Counter Equal to 0xFFFF Latched Flag
* | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF.
* | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit.
* |[8] |SYNCINF0 |Input Synchronization Latched Flag
* | | |0 = Indicates no SYNC_IN event has occurred.
* | | |1 = Indicates an SYNC_IN event has occurred, software can write 1 to clear this bit.
* |[9] |SYNCINF2 |Input Synchronization Latched Flag
* | | |0 = Indicates no SYNC_IN event has occurred.
* | | |1 = Indicates an SYNC_IN event has occurred, software can write 1 to clear this bit.
* |[10] |SYNCINF4 |Input Synchronization Latched Flag
* | | |0 = Indicates no SYNC_IN event has occurred.
* | | |1 = Indicates an SYNC_IN event has occurred, software can write 1 to clear this bit.
* |[16] |EADCTRGF0 |EADC Start of Conversion Flag
* | | |0 = Indicates no EADC start of conversion trigger event has occurred.
* | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.
* |[17] |EADCTRGF1 |EADC Start of Conversion Flag
* | | |0 = Indicates no EADC start of conversion trigger event has occurred.
* | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.
* |[18] |EADCTRGF2 |EADC Start of Conversion Flag
* | | |0 = Indicates no EADC start of conversion trigger event has occurred.
* | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.
* |[19] |EADCTRGF3 |EADC Start of Conversion Flag
* | | |0 = Indicates no EADC start of conversion trigger event has occurred.
* | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.
* |[20] |EADCTRGF4 |EADC Start of Conversion Flag
* | | |0 = Indicates no EADC start of conversion trigger event has occurred.
* | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.
* |[21] |EADCTRGF5 |EADC Start of Conversion Flag
* | | |0 = Indicates no EADC start of conversion trigger event has occurred.
* | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.
* |[24] |DACTRGF |DAC Start of Conversion Flag
* | | |0 = Indicates no DAC start of conversion trigger event has occurred.
* | | |1 = Indicates an DAC start of conversion trigger event has occurred, software can write 1 to clear this bit
* @var EPWM_T::IFA[6]
* Offset: 0x130 EPWM Interrupt Flag Accumulator Register 0~5
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |IFACNT |EPWM_CHn Interrupt Flag Counter
* | | |The register sets the count number which defines how many times of EPWM_CHn period occurs to set bit IFAIFn to request the EPWM period interrupt.
* | | |EPWM flag will be set in every IFACNT[15:0] times of EPWM period.
* |[29:28] |IFASEL |EPWM_CHn Interrupt Flag Accumulator Source Select
* | | |00 = CNT equal to Zero in channel n.
* | | |01 = CNT equal to PERIOD in channel n.
* | | |10 = CNT equal to CMPU in channel n.
* | | |11 = CNT equal to CMPD in channel n.
* |[31] |IFAEN |EPWM_CHn Interrupt Flag Accumulator Enable Bits
* | | |0 = EPWM_CHn interrupt flag accumulator disable.
* | | |1 = EPWM_CHn interrupt flag accumulator enable.
* @var EPWM_T::AINTSTS
* Offset: 0x150 EPWM Accumulator Interrupt Flag Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |IFAIF0 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag
* | | |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it.
* |[1] |IFAIF1 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag
* | | |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it.
* |[2] |IFAIF2 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag
* | | |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it.
* |[3] |IFAIF3 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag
* | | |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it.
* |[4] |IFAIF4 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag
* | | |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it.
* |[5] |IFAIF5 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag
* | | |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it.
* @var EPWM_T::AINTEN
* Offset: 0x154 EPWM Accumulator Interrupt Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |IFAIEN0 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits
* | | |0 = Interrupt Flag accumulator interrupt Disabled.
* | | |1 = Interrupt Flag accumulator interrupt Enabled.
* |[1] |IFAIEN1 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits
* | | |0 = Interrupt Flag accumulator interrupt Disabled.
* | | |1 = Interrupt Flag accumulator interrupt Enabled.
* |[2] |IFAIEN2 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits
* | | |0 = Interrupt Flag accumulator interrupt Disabled.
* | | |1 = Interrupt Flag accumulator interrupt Enabled.
* |[3] |IFAIEN3 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits
* | | |0 = Interrupt Flag accumulator interrupt Disabled.
* | | |1 = Interrupt Flag accumulator interrupt Enabled.
* |[4] |IFAIEN4 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits
* | | |0 = Interrupt Flag accumulator interrupt Disabled.
* | | |1 = Interrupt Flag accumulator interrupt Enabled.
* |[5] |IFAIEN5 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits
* | | |0 = Interrupt Flag accumulator interrupt Disabled.
* | | |1 = Interrupt Flag accumulator interrupt Enabled.
* @var EPWM_T::APDMACTL
* Offset: 0x158 EPWM Accumulator PDMA Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |APDMAEN0 |Channel N Accumulator PDMA Enable Bits
* | | |0 = Channel n PDMA function Disabled.
* | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register.
* |[1] |APDMAEN1 |Channel N Accumulator PDMA Enable Bits
* | | |0 = Channel n PDMA function Disabled.
* | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register.
* |[2] |APDMAEN2 |Channel N Accumulator PDMA Enable Bits
* | | |0 = Channel n PDMA function Disabled.
* | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register.
* |[3] |APDMAEN3 |Channel N Accumulator PDMA Enable Bits
* | | |0 = Channel n PDMA function Disabled.
* | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register.
* |[4] |APDMAEN4 |Channel N Accumulator PDMA Enable Bits
* | | |0 = Channel n PDMA function Disabled.
* | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register.
* |[5] |APDMAEN5 |Channel N Accumulator PDMA Enable Bits
* | | |0 = Channel n PDMA function Disabled.
* | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register.
* @var EPWM_T::CAPINEN
* Offset: 0x200 EPWM Capture Input Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CAPINEN0 |Capture Input Enable Bits
* | | |0 = EPWM Channel capture input path Disabled
* | | |The input of EPWM channel capture function is always regarded as 0.
* | | |1 = EPWM Channel capture input path Enabled
* | | |The input of EPWM channel capture function comes from correlative multifunction pin.
* |[1] |CAPINEN1 |Capture Input Enable Bits
* | | |0 = EPWM Channel capture input path Disabled
* | | |The input of EPWM channel capture function is always regarded as 0.
* | | |1 = EPWM Channel capture input path Enabled
* | | |The input of EPWM channel capture function comes from correlative multifunction pin.
* |[2] |CAPINEN2 |Capture Input Enable Bits
* | | |0 = EPWM Channel capture input path Disabled
* | | |The input of EPWM channel capture function is always regarded as 0.
* | | |1 = EPWM Channel capture input path Enabled
* | | |The input of EPWM channel capture function comes from correlative multifunction pin.
* |[3] |CAPINEN3 |Capture Input Enable Bits
* | | |0 = EPWM Channel capture input path Disabled
* | | |The input of EPWM channel capture function is always regarded as 0.
* | | |1 = EPWM Channel capture input path Enabled
* | | |The input of EPWM channel capture function comes from correlative multifunction pin.
* |[4] |CAPINEN4 |Capture Input Enable Bits
* | | |0 = EPWM Channel capture input path Disabled
* | | |The input of EPWM channel capture function is always regarded as 0.
* | | |1 = EPWM Channel capture input path Enabled
* | | |The input of EPWM channel capture function comes from correlative multifunction pin.
* |[5] |CAPINEN5 |Capture Input Enable Bits
* | | |0 = EPWM Channel capture input path Disabled
* | | |The input of EPWM channel capture function is always regarded as 0.
* | | |1 = EPWM Channel capture input path Enabled
* | | |The input of EPWM channel capture function comes from correlative multifunction pin.
* @var EPWM_T::CAPCTL
* Offset: 0x204 EPWM Capture Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CAPEN0 |Capture Function Enable Bits
* | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.
* | | |1 = Capture function Enabled
* | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
* |[1] |CAPEN1 |Capture Function Enable Bits
* | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.
* | | |1 = Capture function Enabled
* | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
* |[2] |CAPEN2 |Capture Function Enable Bits
* | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.
* | | |1 = Capture function Enabled
* | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
* |[3] |CAPEN3 |Capture Function Enable Bits
* | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.
* | | |1 = Capture function Enabled
* | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
* |[4] |CAPEN4 |Capture Function Enable Bits
* | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.
* | | |1 = Capture function Enabled
* | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
* |[5] |CAPEN5 |Capture Function Enable Bits
* | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.
* | | |1 = Capture function Enabled
* | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
* |[8] |CAPINV0 |Capture Inverter Enable Bits
* | | |0 = Capture source inverter Disabled.
* | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
* |[9] |CAPINV1 |Capture Inverter Enable Bits
* | | |0 = Capture source inverter Disabled.
* | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
* |[10] |CAPINV2 |Capture Inverter Enable Bits
* | | |0 = Capture source inverter Disabled.
* | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
* |[11] |CAPINV3 |Capture Inverter Enable Bits
* | | |0 = Capture source inverter Disabled.
* | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
* |[12] |CAPINV4 |Capture Inverter Enable Bits
* | | |0 = Capture source inverter Disabled.
* | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
* |[13] |CAPINV5 |Capture Inverter Enable Bits
* | | |0 = Capture source inverter Disabled.
* | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
* |[16] |RCRLDEN0 |Rising Capture Reload Enable Bits
* | | |0 = Rising capture reload counter Disabled.
* | | |1 = Rising capture reload counter Enabled.
* |[17] |RCRLDEN1 |Rising Capture Reload Enable Bits
* | | |0 = Rising capture reload counter Disabled.
* | | |1 = Rising capture reload counter Enabled.
* |[18] |RCRLDEN2 |Rising Capture Reload Enable Bits
* | | |0 = Rising capture reload counter Disabled.
* | | |1 = Rising capture reload counter Enabled.
* |[19] |RCRLDEN3 |Rising Capture Reload Enable Bits
* | | |0 = Rising capture reload counter Disabled.
* | | |1 = Rising capture reload counter Enabled.
* |[20] |RCRLDEN4 |Rising Capture Reload Enable Bits
* | | |0 = Rising capture reload counter Disabled.
* | | |1 = Rising capture reload counter Enabled.
* |[21] |RCRLDEN5 |Rising Capture Reload Enable Bits
* | | |0 = Rising capture reload counter Disabled.
* | | |1 = Rising capture reload counter Enabled.
* |[24] |FCRLDEN0 |Falling Capture Reload Enable Bits
* | | |0 = Falling capture reload counter Disabled.
* | | |1 = Falling capture reload counter Enabled.
* |[25] |FCRLDEN1 |Falling Capture Reload Enable Bits
* | | |0 = Falling capture reload counter Disabled.
* | | |1 = Falling capture reload counter Enabled.
* |[26] |FCRLDEN2 |Falling Capture Reload Enable Bits
* | | |0 = Falling capture reload counter Disabled.
* | | |1 = Falling capture reload counter Enabled.
* |[27] |FCRLDEN3 |Falling Capture Reload Enable Bits
* | | |0 = Falling capture reload counter Disabled.
* | | |1 = Falling capture reload counter Enabled.
* |[28] |FCRLDEN4 |Falling Capture Reload Enable Bits
* | | |0 = Falling capture reload counter Disabled.
* | | |1 = Falling capture reload counter Enabled.
* |[29] |FCRLDEN5 |Falling Capture Reload Enable Bits
* | | |0 = Falling capture reload counter Disabled.
* | | |1 = Falling capture reload counter Enabled.
* @var EPWM_T::CAPSTS
* Offset: 0x208 EPWM Capture Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CRLIFOV0 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only)
* | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1.
* | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF.
* |[1] |CRLIFOV1 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only)
* | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1.
* | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF.
* |[2] |CRLIFOV2 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only)
* | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1.
* | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF.
* |[3] |CRLIFOV3 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only)
* | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1.
* | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF.
* |[4] |CRLIFOV4 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only)
* | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1.
* | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF.
* |[5] |CRLIFOV5 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only)
* | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1.
* | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF.
* |[8] |CFLIFOV0 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only)
* | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1.
* | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF.
* |[9] |CFLIFOV1 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only)
* | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1.
* | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF.
* |[10] |CFLIFOV2 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only)
* | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1.
* | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF.
* |[11] |CFLIFOV3 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only)
* | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1.
* | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF.
* |[12] |CFLIFOV4 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only)
* | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1.
* | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF.
* |[13] |CFLIFOV5 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only)
* | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1.
* | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF.
* @var EPWM_T::RCAPDAT0
* Offset: 0x20C EPWM Rising Capture Data Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |RCAPDAT |EPWM Rising Capture Data Register (Read Only)
* | | |When rising capture condition happened, the EPWM counter value will be saved in this register.
* @var EPWM_T::FCAPDAT0
* Offset: 0x210 EPWM Falling Capture Data Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |FCAPDAT |EPWM Falling Capture Data Register (Read Only)
* | | |When falling capture condition happened, the EPWM counter value will be saved in this register.
* @var EPWM_T::RCAPDAT1
* Offset: 0x214 EPWM Rising Capture Data Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |RCAPDAT |EPWM Rising Capture Data Register (Read Only)
* | | |When rising capture condition happened, the EPWM counter value will be saved in this register.
* @var EPWM_T::FCAPDAT1
* Offset: 0x218 EPWM Falling Capture Data Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |FCAPDAT |EPWM Falling Capture Data Register (Read Only)
* | | |When falling capture condition happened, the EPWM counter value will be saved in this register.
* @var EPWM_T::RCAPDAT2
* Offset: 0x21C EPWM Rising Capture Data Register 2
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |RCAPDAT |EPWM Rising Capture Data Register (Read Only)
* | | |When rising capture condition happened, the EPWM counter value will be saved in this register.
* @var EPWM_T::FCAPDAT2
* Offset: 0x220 EPWM Falling Capture Data Register 2
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |FCAPDAT |EPWM Falling Capture Data Register (Read Only)
* | | |When falling capture condition happened, the EPWM counter value will be saved in this register.
* @var EPWM_T::RCAPDAT3
* Offset: 0x224 EPWM Rising Capture Data Register 3
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |RCAPDAT |EPWM Rising Capture Data Register (Read Only)
* | | |When rising capture condition happened, the EPWM counter value will be saved in this register.
* @var EPWM_T::FCAPDAT3
* Offset: 0x228 EPWM Falling Capture Data Register 3
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |FCAPDAT |EPWM Falling Capture Data Register (Read Only)
* | | |When falling capture condition happened, the EPWM counter value will be saved in this register.
* @var EPWM_T::RCAPDAT4
* Offset: 0x22C EPWM Rising Capture Data Register 4
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |RCAPDAT |EPWM Rising Capture Data Register (Read Only)
* | | |When rising capture condition happened, the EPWM counter value will be saved in this register.
* @var EPWM_T::FCAPDAT4
* Offset: 0x230 EPWM Falling Capture Data Register 4
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |FCAPDAT |EPWM Falling Capture Data Register (Read Only)
* | | |When falling capture condition happened, the EPWM counter value will be saved in this register.
* @var EPWM_T::RCAPDAT5
* Offset: 0x234 EPWM Rising Capture Data Register 5
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |RCAPDAT |EPWM Rising Capture Data Register (Read Only)
* | | |When rising capture condition happened, the EPWM counter value will be saved in this register.
* @var EPWM_T::FCAPDAT5
* Offset: 0x238 EPWM Falling Capture Data Register 5
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |FCAPDAT |EPWM Falling Capture Data Register (Read Only)
* | | |When falling capture condition happened, the EPWM counter value will be saved in this register.
* @var EPWM_T::PDMACTL
* Offset: 0x23C EPWM PDMA Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CHEN0_1 |Channel 0/1 PDMA Enable
* | | |0 = Channel 0/1 PDMA function Disabled.
* | | |1 = Channel 0/1 PDMA function Enabled for the channel 0/1 captured data and transfer to memory.
* |[2:1] |CAPMOD0_1 |Select EPWM_RCAPDAT0/1 or EPWM_FCAPDAT0/1 to Do PDMA Transfer
* | | |00 = Reserved.
* | | |01 = EPWM_RCAPDAT0/1.
* | | |10 = EPWM_FCAPDAT0/1.
* | | |11 = Both EPWM_RCAPDAT0/1 and EPWM_FCAPDAT0/1.
* |[3] |CAPORD0_1 |Capture Channel 0/1 Rising/Falling Order
* | | |Set this bit to determine whether the EPWM_RCAPDAT0/1 or EPWM_FCAPDAT0/1 is the first captured data transferred to memory through PDMA when CAPMOD0_1 =11.
* | | |0 = EPWM_FCAPDAT0/1 is the first captured data to memory.
* | | |1 = EPWM_RCAPDAT0/1 is the first captured data to memory.
* |[4] |CHSEL0_1 |Select Channel 0/1 to Do PDMA Transfer
* | | |0 = Channel0.
* | | |1 = Channel1.
* |[8] |CHEN2_3 |Channel 2/3 PDMA Enable
* | | |0 = Channel 2/3 PDMA function Disabled.
* | | |1 = Channel 2/3 PDMA function Enabled for the channel 2/3 captured data and transfer to memory.
* |[10:9] |CAPMOD2_3 |Select EPWM_RCAPDAT2/3 or EPWM_FCAODAT2/3 to Do PDMA Transfer
* | | |00 = Reserved.
* | | |01 = EPWM_RCAPDAT2/3.
* | | |10 = EPWM_FCAPDAT2/3.
* | | |11 = Both EPWM_RCAPDAT2/3 and EPWM_FCAPDAT2/3.
* |[11] |CAPORD2_3 |Capture Channel 2/3 Rising/Falling Order
* | | |Set this bit to determine whether the EPWM_RCAPDAT2/3 or EPWM_FCAPDAT2/3 is the first captured data transferred to memory through PDMA when CAPMOD2_3 =11.
* | | |0 = EPWM_FCAPDAT2/3 is the first captured data to memory.
* | | |1 = EPWM_RCAPDAT2/3 is the first captured data to memory.
* |[12] |CHSEL2_3 |Select Channel 2/3 to Do PDMA Transfer
* | | |0 = Channel2.
* | | |1 = Channel3.
* |[16] |CHEN4_5 |Channel 4/5 PDMA Enable
* | | |0 = Channel 4/5 PDMA function Disabled.
* | | |1 = Channel 4/5 PDMA function Enabled for the channel 4/5 captured data and transfer to memory.
* |[18:17] |CAPMOD4_5 |Select EPWM_RCAPDAT4/5 or EPWM_FCAPDAT4/5 to Do PDMA Transfer
* | | |00 = Reserved.
* | | |01 = EPWM_RCAPDAT4/5.
* | | |10 = EPWM_FCAPDAT4/5.
* | | |11 = Both EPWM_RCAPDAT4/5 and EPWM_FCAPDAT4/5.
* |[19] |CAPORD4_5 |Capture Channel 4/5 Rising/Falling Order
* | | |Set this bit to determine whether the EPWM_RCAPDAT4/5 or EPWM_FCAPDAT4/5 is the first captured data transferred to memory through PDMA when CAPMOD4_5 =11.
* | | |0 = EPWM_FCAPDAT4/5 is the first captured data to memory.
* | | |1 = EPWM_RCAPDAT4/5 is the first captured data to memory.
* |[20] |CHSEL4_5 |Select Channel 4/5 to Do PDMA Transfer
* | | |0 = Channel4.
* | | |1 = Channel5.
* @var EPWM_T::PDMACAP[3]
* Offset: 0x240 EPWM Capture Channel 01 PDMA Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |CAPBUF |EPWM Capture PDMA Register (Read Only)
* | | |This register is use as a buffer to transfer EPWM capture rising or falling data to memory by PDMA.
* @var EPWM_T::CAPIEN
* Offset: 0x250 EPWM Capture Interrupt Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CAPRIEN0 |EPWM Capture Rising Latch Interrupt Enable Bits
* | | |0 = Capture rising edge latch interrupt Disabled.
* | | |1 = Capture rising edge latch interrupt Enabled.
* |[1] |CAPRIEN1 |EPWM Capture Rising Latch Interrupt Enable Bits
* | | |0 = Capture rising edge latch interrupt Disabled.
* | | |1 = Capture rising edge latch interrupt Enabled.
* |[2] |CAPRIEN2 |EPWM Capture Rising Latch Interrupt Enable Bits
* | | |0 = Capture rising edge latch interrupt Disabled.
* | | |1 = Capture rising edge latch interrupt Enabled.
* |[3] |CAPRIEN3 |EPWM Capture Rising Latch Interrupt Enable Bits
* | | |0 = Capture rising edge latch interrupt Disabled.
* | | |1 = Capture rising edge latch interrupt Enabled.
* |[4] |CAPRIEN4 |EPWM Capture Rising Latch Interrupt Enable Bits
* | | |0 = Capture rising edge latch interrupt Disabled.
* | | |1 = Capture rising edge latch interrupt Enabled.
* |[5] |CAPRIEN5 |EPWM Capture Rising Latch Interrupt Enable Bits
* | | |0 = Capture rising edge latch interrupt Disabled.
* | | |1 = Capture rising edge latch interrupt Enabled.
* |[8] |CAPFIEN0 |EPWM Capture Falling Latch Interrupt Enable Bits
* | | |0 = Capture falling edge latch interrupt Disabled.
* | | |1 = Capture falling edge latch interrupt Enabled.
* |[9] |CAPFIEN1 |EPWM Capture Falling Latch Interrupt Enable Bits
* | | |0 = Capture falling edge latch interrupt Disabled.
* | | |1 = Capture falling edge latch interrupt Enabled.
* |[10] |CAPFIEN2 |EPWM Capture Falling Latch Interrupt Enable Bits
* | | |0 = Capture falling edge latch interrupt Disabled.
* | | |1 = Capture falling edge latch interrupt Enabled.
* |[11] |CAPFIEN3 |EPWM Capture Falling Latch Interrupt Enable Bits
* | | |0 = Capture falling edge latch interrupt Disabled.
* | | |1 = Capture falling edge latch interrupt Enabled.
* |[12] |CAPFIEN4 |EPWM Capture Falling Latch Interrupt Enable Bits
* | | |0 = Capture falling edge latch interrupt Disabled.
* | | |1 = Capture falling edge latch interrupt Enabled.
* |[13] |CAPFIEN5 |EPWM Capture Falling Latch Interrupt Enable Bits
* | | |0 = Capture falling edge latch interrupt Disabled.
* | | |1 = Capture falling edge latch interrupt Enabled.
* @var EPWM_T::CAPIF
* Offset: 0x254 EPWM Capture Interrupt Flag Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CRLIF0 |EPWM Capture Rising Latch Interrupt Flag
* | | |This bit is writing 1 to clear.
* | | |0 = No capture rising latch condition happened.
* | | |1 = Capture rising latch condition happened, this flag will be set to high.
* | | |Note: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will cleared by hardware after PDMA transfer data.
* |[1] |CRLIF1 |EPWM Capture Rising Latch Interrupt Flag
* | | |This bit is writing 1 to clear.
* | | |0 = No capture rising latch condition happened.
* | | |1 = Capture rising latch condition happened, this flag will be set to high.
* | | |Note: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will cleared by hardware after PDMA transfer data.
* |[2] |CRLIF2 |EPWM Capture Rising Latch Interrupt Flag
* | | |This bit is writing 1 to clear.
* | | |0 = No capture rising latch condition happened.
* | | |1 = Capture rising latch condition happened, this flag will be set to high.
* | | |Note: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will cleared by hardware after PDMA transfer data.
* |[3] |CRLIF3 |EPWM Capture Rising Latch Interrupt Flag
* | | |This bit is writing 1 to clear.
* | | |0 = No capture rising latch condition happened.
* | | |1 = Capture rising latch condition happened, this flag will be set to high.
* | | |Note: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will cleared by hardware after PDMA transfer data.
* |[4] |CRLIF4 |EPWM Capture Rising Latch Interrupt Flag
* | | |This bit is writing 1 to clear.
* | | |0 = No capture rising latch condition happened.
* | | |1 = Capture rising latch condition happened, this flag will be set to high.
* | | |Note: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will cleared by hardware after PDMA transfer data.
* |[5] |CRLIF5 |EPWM Capture Rising Latch Interrupt Flag
* | | |This bit is writing 1 to clear.
* | | |0 = No capture rising latch condition happened.
* | | |1 = Capture rising latch condition happened, this flag will be set to high.
* | | |Note: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will cleared by hardware after PDMA transfer data.
* |[8] |CFLIF0 |EPWM Capture Falling Latch Interrupt Flag
* | | |This bit is writing 1 to clear.
* | | |0 = No capture falling latch condition happened.
* | | |1 = Capture falling latch condition happened, this flag will be set to high.
* | | |Note: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will cleared by hardware after PDMA transfer data.
* |[9] |CFLIF1 |EPWM Capture Falling Latch Interrupt Flag
* | | |This bit is writing 1 to clear.
* | | |0 = No capture falling latch condition happened.
* | | |1 = Capture falling latch condition happened, this flag will be set to high.
* | | |Note: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will cleared by hardware after PDMA transfer data.
* |[10] |CFLIF2 |EPWM Capture Falling Latch Interrupt Flag
* | | |This bit is writing 1 to clear.
* | | |0 = No capture falling latch condition happened.
* | | |1 = Capture falling latch condition happened, this flag will be set to high.
* | | |Note: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will cleared by hardware after PDMA transfer data.
* |[11] |CFLIF3 |EPWM Capture Falling Latch Interrupt Flag
* | | |This bit is writing 1 to clear.
* | | |0 = No capture falling latch condition happened.
* | | |1 = Capture falling latch condition happened, this flag will be set to high.
* | | |Note: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will cleared by hardware after PDMA transfer data.
* |[12] |CFLIF4 |EPWM Capture Falling Latch Interrupt Flag
* | | |This bit is writing 1 to clear.
* | | |0 = No capture falling latch condition happened.
* | | |1 = Capture falling latch condition happened, this flag will be set to high.
* | | |Note: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will cleared by hardware after PDMA transfer data.
* |[13] |CFLIF5 |EPWM Capture Falling Latch Interrupt Flag
* | | |This bit is writing 1 to clear.
* | | |0 = No capture falling latch condition happened.
* | | |1 = Capture falling latch condition happened, this flag will be set to high.
* | | |Note: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will cleared by hardware after PDMA transfer data.
* @var EPWM_T::PBUF[6]
* Offset: 0x304 EPWM PERIOD0~5 Buffer
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |PBUF |EPWM Period Register Buffer (Read Only)
* | | |Used as PERIOD active register.
* @var EPWM_T::CMPBUF[6]
* Offset: 0x31C EPWM CMPDAT0~5 Buffer
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |CMPBUF |EPWM Comparator Register Buffer (Read Only)
* | | |Used as CMP active register.
* @var EPWM_T::CPSCBUF[3]
* Offset: 0x334 EPWM CLKPSC0_1/2_3/4_5 Buffer
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[11:0] |CPSCBUF |EPWM Counter Clock Prescale Buffer
* | | |Use as EPWM counter clock prescale active register.
* @var EPWM_T::FTCBUF[3]
* Offset: 0x340 EPWM FTCMPDAT0_1/2_3/4_5 Buffer
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |FTCMPBUF |EPWM FTCMPDAT Buffer (Read Only)
* | | |Used as FTCMPDAT active register.
* @var EPWM_T::FTCI
* Offset: 0x34C EPWM FTCMPDAT Indicator Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |FTCMU0 |EPWM FTCMPDAT Up Indicator
* | | |Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=1, software can write 1 to clear this bit.
* |[1] |FTCMU2 |EPWM FTCMPDAT Up Indicator
* | | |Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=1, software can write 1 to clear this bit.
* |[2] |FTCMU4 |EPWM FTCMPDAT Up Indicator
* | | |Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=1, software can write 1 to clear this bit.
* |[8] |FTCMD0 |EPWM FTCMPDAT Down Indicator
* | | |Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=0, software can write 1 to clear this bit.
* |[9] |FTCMD2 |EPWM FTCMPDAT Down Indicator
* | | |Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=0, software can write 1 to clear this bit.
* |[10] |FTCMD4 |EPWM FTCMPDAT Down Indicator
* | | |Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=0, software can write 1 to clear this bit.
*/
__IO uint32_t CTL0; /*!< [0x0000] EPWM Control Register 0 */
__IO uint32_t CTL1; /*!< [0x0004] EPWM Control Register 1 */
__IO uint32_t SYNC; /*!< [0x0008] EPWM Synchronization Register */
__IO uint32_t SWSYNC; /*!< [0x000c] EPWM Software Control Synchronization Register */
__IO uint32_t CLKSRC; /*!< [0x0010] EPWM Clock Source Register */
__IO uint32_t CLKPSC[3]; /*!< [0x0014] EPWM Clock Prescale Register 0/1,2/3,4/5 */
__IO uint32_t CNTEN; /*!< [0x0020] EPWM Counter Enable Register */
__IO uint32_t CNTCLR; /*!< [0x0024] EPWM Clear Counter Register */
__IO uint32_t LOAD; /*!< [0x0028] EPWM Load Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE0[1];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t PERIOD[6]; /*!< [0x0030] EPWM Period Register 0~5 */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE1[2];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t CMPDAT[6]; /*!< [0x0050] EPWM Comparator Register 0~5 */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE2[2];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t DTCTL[3]; /*!< [0x0070] EPWM Dead-Time Control Register 0/1,2/3,4/5 */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE3[1];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t PHS[3]; /*!< [0x0080] EPWM Counter Phase Register 0/1,2/3,4/5 */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE4[1];
/// @endcond //HIDDEN_SYMBOLS
__I uint32_t CNT[6]; /*!< [0x0090] EPWM Counter Register 0~5 */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE5[2];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t WGCTL0; /*!< [0x00b0] EPWM Generation Register 0 */
__IO uint32_t WGCTL1; /*!< [0x00b4] EPWM Generation Register 1 */
__IO uint32_t MSKEN; /*!< [0x00b8] EPWM Mask Enable Register */
__IO uint32_t MSK; /*!< [0x00bc] EPWM Mask Data Register */
__IO uint32_t BNF; /*!< [0x00c0] EPWM Brake Noise Filter Register */
__IO uint32_t FAILBRK; /*!< [0x00c4] EPWM System Fail Brake Control Register */
__IO uint32_t BRKCTL[3]; /*!< [0x00c8] EPWM Brake Edge Detect Control Register 0/1,2/3,4/5 */
__IO uint32_t POLCTL; /*!< [0x00d4] EPWM Pin Polar Inverse Register */
__IO uint32_t POEN; /*!< [0x00d8] EPWM Output Enable Register */
__O uint32_t SWBRK; /*!< [0x00dc] EPWM Software Brake Control Register */
__IO uint32_t INTEN0; /*!< [0x00e0] EPWM Interrupt Enable Register 0 */
__IO uint32_t INTEN1; /*!< [0x00e4] EPWM Interrupt Enable Register 1 */
__IO uint32_t INTSTS0; /*!< [0x00e8] EPWM Interrupt Flag Register 0 */
__IO uint32_t INTSTS1; /*!< [0x00ec] EPWM Interrupt Flag Register 1 */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE6[1];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t DACTRGEN; /*!< [0x00f4] EPWM Trigger DAC Enable Register */
__IO uint32_t EADCTS0; /*!< [0x00f8] EPWM Trigger EADC Source Select Register 0 */
__IO uint32_t EADCTS1; /*!< [0x00fc] EPWM Trigger EADC Source Select Register 1 */
__IO uint32_t FTCMPDAT[3]; /*!< [0x0100] EPWM Free Trigger Compare Register 0/1,2/3,4/5 */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE7[1];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t SSCTL; /*!< [0x0110] EPWM Synchronous Start Control Register */
__O uint32_t SSTRG; /*!< [0x0114] EPWM Synchronous Start Trigger Register */
__IO uint32_t LEBCTL; /*!< [0x0118] EPWM Leading Edge Blanking Control Register */
__IO uint32_t LEBCNT; /*!< [0x011c] EPWM Leading Edge Blanking Counter Register */
__IO uint32_t STATUS; /*!< [0x0120] EPWM Status Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE8[3];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t IFA[6]; /*!< [0x0130] EPWM Interrupt Flag Accumulator Register 0~5 */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE9[2];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t AINTSTS; /*!< [0x0150] EPWM Accumulator Interrupt Flag Register */
__IO uint32_t AINTEN; /*!< [0x0154] EPWM Accumulator Interrupt Enable Register */
__IO uint32_t APDMACTL; /*!< [0x0158] EPWM Accumulator PDMA Control Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE10[41];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t CAPINEN; /*!< [0x0200] EPWM Capture Input Enable Register */
__IO uint32_t CAPCTL; /*!< [0x0204] EPWM Capture Control Register */
__I uint32_t CAPSTS; /*!< [0x0208] EPWM Capture Status Register */
__I uint32_t RCAPDAT0; /*!< [0x020c] EPWM Rising Capture Data Register 0 */
__I uint32_t FCAPDAT0; /*!< [0x0210] EPWM Falling Capture Data Register 0 */
__I uint32_t RCAPDAT1; /*!< [0x0214] EPWM Rising Capture Data Register 1 */
__I uint32_t FCAPDAT1; /*!< [0x0218] EPWM Falling Capture Data Register 1 */
__I uint32_t RCAPDAT2; /*!< [0x021c] EPWM Rising Capture Data Register 2 */
__I uint32_t FCAPDAT2; /*!< [0x0220] EPWM Falling Capture Data Register 2 */
__I uint32_t RCAPDAT3; /*!< [0x0224] EPWM Rising Capture Data Register 3 */
__I uint32_t FCAPDAT3; /*!< [0x0228] EPWM Falling Capture Data Register 3 */
__I uint32_t RCAPDAT4; /*!< [0x022c] EPWM Rising Capture Data Register 4 */
__I uint32_t FCAPDAT4; /*!< [0x0230] EPWM Falling Capture Data Register 4 */
__I uint32_t RCAPDAT5; /*!< [0x0234] EPWM Rising Capture Data Register 5 */
__I uint32_t FCAPDAT5; /*!< [0x0238] EPWM Falling Capture Data Register 5 */
__IO uint32_t PDMACTL; /*!< [0x023c] EPWM PDMA Control Register */
__I uint32_t PDMACAP[3]; /*!< [0x0240] EPWM Capture Channel 01,23,45 PDMA Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE11[1];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t CAPIEN; /*!< [0x0250] EPWM Capture Interrupt Enable Register */
__IO uint32_t CAPIF; /*!< [0x0254] EPWM Capture Interrupt Flag Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE12[43];
/// @endcond //HIDDEN_SYMBOLS
__I uint32_t PBUF[6]; /*!< [0x0304] EPWM PERIOD0~5 Buffer */
__I uint32_t CMPBUF[6]; /*!< [0x031c] EPWM CMPDAT0~5 Buffer */
__I uint32_t CPSCBUF[3]; /*!< [0x0334] EPWM CLKPSC0_1/2_3/4_5 Buffer */
__I uint32_t FTCBUF[3]; /*!< [0x0340] EPWM FTCMPDAT0_1/2_3/4_5 Buffer */
__IO uint32_t FTCI; /*!< [0x034c] EPWM FTCMPDAT Indicator Register */
} EPWM_T;
/**
@addtogroup EPWM_CONST EPWM Bit Field Definition
Constant Definitions for EPWM Controller
@{ */
#define EPWM_CTL0_CTRLD0_Pos (0) /*!< EPWM_T::CTL0: CTRLD0 Position */
#define EPWM_CTL0_CTRLD0_Msk (0x1ul << EPWM_CTL0_CTRLD0_Pos) /*!< EPWM_T::CTL0: CTRLD0 Mask */
#define EPWM_CTL0_CTRLD1_Pos (1) /*!< EPWM_T::CTL0: CTRLD1 Position */
#define EPWM_CTL0_CTRLD1_Msk (0x1ul << EPWM_CTL0_CTRLD1_Pos) /*!< EPWM_T::CTL0: CTRLD1 Mask */
#define EPWM_CTL0_CTRLD2_Pos (2) /*!< EPWM_T::CTL0: CTRLD2 Position */
#define EPWM_CTL0_CTRLD2_Msk (0x1ul << EPWM_CTL0_CTRLD2_Pos) /*!< EPWM_T::CTL0: CTRLD2 Mask */
#define EPWM_CTL0_CTRLD3_Pos (3) /*!< EPWM_T::CTL0: CTRLD3 Position */
#define EPWM_CTL0_CTRLD3_Msk (0x1ul << EPWM_CTL0_CTRLD3_Pos) /*!< EPWM_T::CTL0: CTRLD3 Mask */
#define EPWM_CTL0_CTRLD4_Pos (4) /*!< EPWM_T::CTL0: CTRLD4 Position */
#define EPWM_CTL0_CTRLD4_Msk (0x1ul << EPWM_CTL0_CTRLD4_Pos) /*!< EPWM_T::CTL0: CTRLD4 Mask */
#define EPWM_CTL0_CTRLD5_Pos (5) /*!< EPWM_T::CTL0: CTRLD5 Position */
#define EPWM_CTL0_CTRLD5_Msk (0x1ul << EPWM_CTL0_CTRLD5_Pos) /*!< EPWM_T::CTL0: CTRLD5 Mask */
#define EPWM_CTL0_WINLDEN0_Pos (8) /*!< EPWM_T::CTL0: WINLDEN0 Position */
#define EPWM_CTL0_WINLDEN0_Msk (0x1ul << EPWM_CTL0_WINLDEN0_Pos) /*!< EPWM_T::CTL0: WINLDEN0 Mask */
#define EPWM_CTL0_WINLDEN1_Pos (9) /*!< EPWM_T::CTL0: WINLDEN1 Position */
#define EPWM_CTL0_WINLDEN1_Msk (0x1ul << EPWM_CTL0_WINLDEN1_Pos) /*!< EPWM_T::CTL0: WINLDEN1 Mask */
#define EPWM_CTL0_WINLDEN2_Pos (10) /*!< EPWM_T::CTL0: WINLDEN2 Position */
#define EPWM_CTL0_WINLDEN2_Msk (0x1ul << EPWM_CTL0_WINLDEN2_Pos) /*!< EPWM_T::CTL0: WINLDEN2 Mask */
#define EPWM_CTL0_WINLDEN3_Pos (11) /*!< EPWM_T::CTL0: WINLDEN3 Position */
#define EPWM_CTL0_WINLDEN3_Msk (0x1ul << EPWM_CTL0_WINLDEN3_Pos) /*!< EPWM_T::CTL0: WINLDEN3 Mask */
#define EPWM_CTL0_WINLDEN4_Pos (12) /*!< EPWM_T::CTL0: WINLDEN4 Position */
#define EPWM_CTL0_WINLDEN4_Msk (0x1ul << EPWM_CTL0_WINLDEN4_Pos) /*!< EPWM_T::CTL0: WINLDEN4 Mask */
#define EPWM_CTL0_WINLDEN5_Pos (13) /*!< EPWM_T::CTL0: WINLDEN5 Position */
#define EPWM_CTL0_WINLDEN5_Msk (0x1ul << EPWM_CTL0_WINLDEN5_Pos) /*!< EPWM_T::CTL0: WINLDEN5 Mask */
#define EPWM_CTL0_IMMLDEN0_Pos (16) /*!< EPWM_T::CTL0: IMMLDEN0 Position */
#define EPWM_CTL0_IMMLDEN0_Msk (0x1ul << EPWM_CTL0_IMMLDEN0_Pos) /*!< EPWM_T::CTL0: IMMLDEN0 Mask */
#define EPWM_CTL0_IMMLDEN1_Pos (17) /*!< EPWM_T::CTL0: IMMLDEN1 Position */
#define EPWM_CTL0_IMMLDEN1_Msk (0x1ul << EPWM_CTL0_IMMLDEN1_Pos) /*!< EPWM_T::CTL0: IMMLDEN1 Mask */
#define EPWM_CTL0_IMMLDEN2_Pos (18) /*!< EPWM_T::CTL0: IMMLDEN2 Position */
#define EPWM_CTL0_IMMLDEN2_Msk (0x1ul << EPWM_CTL0_IMMLDEN2_Pos) /*!< EPWM_T::CTL0: IMMLDEN2 Mask */
#define EPWM_CTL0_IMMLDEN3_Pos (19) /*!< EPWM_T::CTL0: IMMLDEN3 Position */
#define EPWM_CTL0_IMMLDEN3_Msk (0x1ul << EPWM_CTL0_IMMLDEN3_Pos) /*!< EPWM_T::CTL0: IMMLDEN3 Mask */
#define EPWM_CTL0_IMMLDEN4_Pos (20) /*!< EPWM_T::CTL0: IMMLDEN4 Position */
#define EPWM_CTL0_IMMLDEN4_Msk (0x1ul << EPWM_CTL0_IMMLDEN4_Pos) /*!< EPWM_T::CTL0: IMMLDEN4 Mask */
#define EPWM_CTL0_IMMLDEN5_Pos (21) /*!< EPWM_T::CTL0: IMMLDEN5 Position */
#define EPWM_CTL0_IMMLDEN5_Msk (0x1ul << EPWM_CTL0_IMMLDEN5_Pos) /*!< EPWM_T::CTL0: IMMLDEN5 Mask */
#define EPWM_CTL0_GROUPEN_Pos (24) /*!< EPWM_T::CTL0: GROUPEN Position */
#define EPWM_CTL0_GROUPEN_Msk (0x1ul << EPWM_CTL0_GROUPEN_Pos) /*!< EPWM_T::CTL0: GROUPEN Mask */
#define EPWM_CTL0_DBGHALT_Pos (30) /*!< EPWM_T::CTL0: DBGHALT Position */
#define EPWM_CTL0_DBGHALT_Msk (0x1ul << EPWM_CTL0_DBGHALT_Pos) /*!< EPWM_T::CTL0: DBGHALT Mask */
#define EPWM_CTL0_DBGTRIOFF_Pos (31) /*!< EPWM_T::CTL0: DBGTRIOFF Position */
#define EPWM_CTL0_DBGTRIOFF_Msk (0x1ul << EPWM_CTL0_DBGTRIOFF_Pos) /*!< EPWM_T::CTL0: DBGTRIOFF Mask */
#define EPWM_CTL1_CNTTYPE0_Pos (0) /*!< EPWM_T::CTL1: CNTTYPE0 Position */
#define EPWM_CTL1_CNTTYPE0_Msk (0x3ul << EPWM_CTL1_CNTTYPE0_Pos) /*!< EPWM_T::CTL1: CNTTYPE0 Mask */
#define EPWM_CTL1_CNTTYPE1_Pos (2) /*!< EPWM_T::CTL1: CNTTYPE1 Position */
#define EPWM_CTL1_CNTTYPE1_Msk (0x3ul << EPWM_CTL1_CNTTYPE1_Pos) /*!< EPWM_T::CTL1: CNTTYPE1 Mask */
#define EPWM_CTL1_CNTTYPE2_Pos (4) /*!< EPWM_T::CTL1: CNTTYPE2 Position */
#define EPWM_CTL1_CNTTYPE2_Msk (0x3ul << EPWM_CTL1_CNTTYPE2_Pos) /*!< EPWM_T::CTL1: CNTTYPE2 Mask */
#define EPWM_CTL1_CNTTYPE3_Pos (6) /*!< EPWM_T::CTL1: CNTTYPE3 Position */
#define EPWM_CTL1_CNTTYPE3_Msk (0x3ul << EPWM_CTL1_CNTTYPE3_Pos) /*!< EPWM_T::CTL1: CNTTYPE3 Mask */
#define EPWM_CTL1_CNTTYPE4_Pos (8) /*!< EPWM_T::CTL1: CNTTYPE4 Position */
#define EPWM_CTL1_CNTTYPE4_Msk (0x3ul << EPWM_CTL1_CNTTYPE4_Pos) /*!< EPWM_T::CTL1: CNTTYPE4 Mask */
#define EPWM_CTL1_CNTTYPE5_Pos (10) /*!< EPWM_T::CTL1: CNTTYPE5 Position */
#define EPWM_CTL1_CNTTYPE5_Msk (0x3ul << EPWM_CTL1_CNTTYPE5_Pos) /*!< EPWM_T::CTL1: CNTTYPE5 Mask */
#define EPWM_CTL1_CNTMODE0_Pos (16) /*!< EPWM_T::CTL1: CNTMODE0 Position */
#define EPWM_CTL1_CNTMODE0_Msk (0x1ul << EPWM_CTL1_CNTMODE0_Pos) /*!< EPWM_T::CTL1: CNTMODE0 Mask */
#define EPWM_CTL1_CNTMODE1_Pos (17) /*!< EPWM_T::CTL1: CNTMODE1 Position */
#define EPWM_CTL1_CNTMODE1_Msk (0x1ul << EPWM_CTL1_CNTMODE1_Pos) /*!< EPWM_T::CTL1: CNTMODE1 Mask */
#define EPWM_CTL1_CNTMODE2_Pos (18) /*!< EPWM_T::CTL1: CNTMODE2 Position */
#define EPWM_CTL1_CNTMODE2_Msk (0x1ul << EPWM_CTL1_CNTMODE2_Pos) /*!< EPWM_T::CTL1: CNTMODE2 Mask */
#define EPWM_CTL1_CNTMODE3_Pos (19) /*!< EPWM_T::CTL1: CNTMODE3 Position */
#define EPWM_CTL1_CNTMODE3_Msk (0x1ul << EPWM_CTL1_CNTMODE3_Pos) /*!< EPWM_T::CTL1: CNTMODE3 Mask */
#define EPWM_CTL1_CNTMODE4_Pos (20) /*!< EPWM_T::CTL1: CNTMODE4 Position */
#define EPWM_CTL1_CNTMODE4_Msk (0x1ul << EPWM_CTL1_CNTMODE4_Pos) /*!< EPWM_T::CTL1: CNTMODE4 Mask */
#define EPWM_CTL1_CNTMODE5_Pos (21) /*!< EPWM_T::CTL1: CNTMODE5 Position */
#define EPWM_CTL1_CNTMODE5_Msk (0x1ul << EPWM_CTL1_CNTMODE5_Pos) /*!< EPWM_T::CTL1: CNTMODE5 Mask */
#define EPWM_CTL1_OUTMODE0_Pos (24) /*!< EPWM_T::CTL1: OUTMODE0 Position */
#define EPWM_CTL1_OUTMODE0_Msk (0x1ul << EPWM_CTL1_OUTMODE0_Pos) /*!< EPWM_T::CTL1: OUTMODE0 Mask */
#define EPWM_CTL1_OUTMODE2_Pos (25) /*!< EPWM_T::CTL1: OUTMODE2 Position */
#define EPWM_CTL1_OUTMODE2_Msk (0x1ul << EPWM_CTL1_OUTMODE2_Pos) /*!< EPWM_T::CTL1: OUTMODE2 Mask */
#define EPWM_CTL1_OUTMODE4_Pos (26) /*!< EPWM_T::CTL1: OUTMODE4 Position */
#define EPWM_CTL1_OUTMODE4_Msk (0x1ul << EPWM_CTL1_OUTMODE4_Pos) /*!< EPWM_T::CTL1: OUTMODE4 Mask */
#define EPWM_SYNC_PHSEN0_Pos (0) /*!< EPWM_T::SYNC: PHSEN0 Position */
#define EPWM_SYNC_PHSEN0_Msk (0x1ul << EPWM_SYNC_PHSEN0_Pos) /*!< EPWM_T::SYNC: PHSEN0 Mask */
#define EPWM_SYNC_PHSEN2_Pos (1) /*!< EPWM_T::SYNC: PHSEN2 Position */
#define EPWM_SYNC_PHSEN2_Msk (0x1ul << EPWM_SYNC_PHSEN2_Pos) /*!< EPWM_T::SYNC: PHSEN2 Mask */
#define EPWM_SYNC_PHSEN4_Pos (2) /*!< EPWM_T::SYNC: PHSEN4 Position */
#define EPWM_SYNC_PHSEN4_Msk (0x1ul << EPWM_SYNC_PHSEN4_Pos) /*!< EPWM_T::SYNC: PHSEN4 Mask */
#define EPWM_SYNC_SINSRC0_Pos (8) /*!< EPWM_T::SYNC: SINSRC0 Position */
#define EPWM_SYNC_SINSRC0_Msk (0x3ul << EPWM_SYNC_SINSRC0_Pos) /*!< EPWM_T::SYNC: SINSRC0 Mask */
#define EPWM_SYNC_SINSRC2_Pos (10) /*!< EPWM_T::SYNC: SINSRC2 Position */
#define EPWM_SYNC_SINSRC2_Msk (0x3ul << EPWM_SYNC_SINSRC2_Pos) /*!< EPWM_T::SYNC: SINSRC2 Mask */
#define EPWM_SYNC_SINSRC4_Pos (12) /*!< EPWM_T::SYNC: SINSRC4 Position */
#define EPWM_SYNC_SINSRC4_Msk (0x3ul << EPWM_SYNC_SINSRC4_Pos) /*!< EPWM_T::SYNC: SINSRC4 Mask */
#define EPWM_SYNC_SNFLTEN_Pos (16) /*!< EPWM_T::SYNC: SNFLTEN Position */
#define EPWM_SYNC_SNFLTEN_Msk (0x1ul << EPWM_SYNC_SNFLTEN_Pos) /*!< EPWM_T::SYNC: SNFLTEN Mask */
#define EPWM_SYNC_SFLTCSEL_Pos (17) /*!< EPWM_T::SYNC: SFLTCSEL Position */
#define EPWM_SYNC_SFLTCSEL_Msk (0x7ul << EPWM_SYNC_SFLTCSEL_Pos) /*!< EPWM_T::SYNC: SFLTCSEL Mask */
#define EPWM_SYNC_SFLTCNT_Pos (20) /*!< EPWM_T::SYNC: SFLTCNT Position */
#define EPWM_SYNC_SFLTCNT_Msk (0x7ul << EPWM_SYNC_SFLTCNT_Pos) /*!< EPWM_T::SYNC: SFLTCNT Mask */
#define EPWM_SYNC_SINPINV_Pos (23) /*!< EPWM_T::SYNC: SINPINV Position */
#define EPWM_SYNC_SINPINV_Msk (0x1ul << EPWM_SYNC_SINPINV_Pos) /*!< EPWM_T::SYNC: SINPINV Mask */
#define EPWM_SYNC_PHSDIR0_Pos (24) /*!< EPWM_T::SYNC: PHSDIR0 Position */
#define EPWM_SYNC_PHSDIR0_Msk (0x1ul << EPWM_SYNC_PHSDIR0_Pos) /*!< EPWM_T::SYNC: PHSDIR0 Mask */
#define EPWM_SYNC_PHSDIR2_Pos (25) /*!< EPWM_T::SYNC: PHSDIR2 Position */
#define EPWM_SYNC_PHSDIR2_Msk (0x1ul << EPWM_SYNC_PHSDIR2_Pos) /*!< EPWM_T::SYNC: PHSDIR2 Mask */
#define EPWM_SYNC_PHSDIR4_Pos (26) /*!< EPWM_T::SYNC: PHSDIR4 Position */
#define EPWM_SYNC_PHSDIR4_Msk (0x1ul << EPWM_SYNC_PHSDIR4_Pos) /*!< EPWM_T::SYNC: PHSDIR4 Mask */
#define EPWM_SWSYNC_SWSYNC0_Pos (0) /*!< EPWM_T::SWSYNC: SWSYNC0 Position */
#define EPWM_SWSYNC_SWSYNC0_Msk (0x1ul << EPWM_SWSYNC_SWSYNC0_Pos) /*!< EPWM_T::SWSYNC: SWSYNC0 Mask */
#define EPWM_SWSYNC_SWSYNC2_Pos (1) /*!< EPWM_T::SWSYNC: SWSYNC2 Position */
#define EPWM_SWSYNC_SWSYNC2_Msk (0x1ul << EPWM_SWSYNC_SWSYNC2_Pos) /*!< EPWM_T::SWSYNC: SWSYNC2 Mask */
#define EPWM_SWSYNC_SWSYNC4_Pos (2) /*!< EPWM_T::SWSYNC: SWSYNC4 Position */
#define EPWM_SWSYNC_SWSYNC4_Msk (0x1ul << EPWM_SWSYNC_SWSYNC4_Pos) /*!< EPWM_T::SWSYNC: SWSYNC4 Mask */
#define EPWM_CLKSRC_ECLKSRC0_Pos (0) /*!< EPWM_T::CLKSRC: ECLKSRC0 Position */
#define EPWM_CLKSRC_ECLKSRC0_Msk (0x7ul << EPWM_CLKSRC_ECLKSRC0_Pos) /*!< EPWM_T::CLKSRC: ECLKSRC0 Mask */
#define EPWM_CLKSRC_ECLKSRC2_Pos (8) /*!< EPWM_T::CLKSRC: ECLKSRC2 Position */
#define EPWM_CLKSRC_ECLKSRC2_Msk (0x7ul << EPWM_CLKSRC_ECLKSRC2_Pos) /*!< EPWM_T::CLKSRC: ECLKSRC2 Mask */
#define EPWM_CLKSRC_ECLKSRC4_Pos (16) /*!< EPWM_T::CLKSRC: ECLKSRC4 Position */
#define EPWM_CLKSRC_ECLKSRC4_Msk (0x7ul << EPWM_CLKSRC_ECLKSRC4_Pos) /*!< EPWM_T::CLKSRC: ECLKSRC4 Mask */
#define EPWM_CLKPSC0_1_CLKPSC_Pos (0) /*!< EPWM_T::CLKPSC0_1: CLKPSC Position */
#define EPWM_CLKPSC0_1_CLKPSC_Msk (0xffful << EPWM_CLKPSC0_1_CLKPSC_Pos) /*!< EPWM_T::CLKPSC0_1: CLKPSC Mask */
#define EPWM_CLKPSC2_3_CLKPSC_Pos (0) /*!< EPWM_T::CLKPSC2_3: CLKPSC Position */
#define EPWM_CLKPSC2_3_CLKPSC_Msk (0xffful << EPWM_CLKPSC2_3_CLKPSC_Pos) /*!< EPWM_T::CLKPSC2_3: CLKPSC Mask */
#define EPWM_CLKPSC4_5_CLKPSC_Pos (0) /*!< EPWM_T::CLKPSC4_5: CLKPSC Position */
#define EPWM_CLKPSC4_5_CLKPSC_Msk (0xffful << EPWM_CLKPSC4_5_CLKPSC_Pos) /*!< EPWM_T::CLKPSC4_5: CLKPSC Mask */
#define EPWM_CNTEN_CNTEN0_Pos (0) /*!< EPWM_T::CNTEN: CNTEN0 Position */
#define EPWM_CNTEN_CNTEN0_Msk (0x1ul << EPWM_CNTEN_CNTEN0_Pos) /*!< EPWM_T::CNTEN: CNTEN0 Mask */
#define EPWM_CNTEN_CNTEN1_Pos (1) /*!< EPWM_T::CNTEN: CNTEN1 Position */
#define EPWM_CNTEN_CNTEN1_Msk (0x1ul << EPWM_CNTEN_CNTEN1_Pos) /*!< EPWM_T::CNTEN: CNTEN1 Mask */
#define EPWM_CNTEN_CNTEN2_Pos (2) /*!< EPWM_T::CNTEN: CNTEN2 Position */
#define EPWM_CNTEN_CNTEN2_Msk (0x1ul << EPWM_CNTEN_CNTEN2_Pos) /*!< EPWM_T::CNTEN: CNTEN2 Mask */
#define EPWM_CNTEN_CNTEN3_Pos (3) /*!< EPWM_T::CNTEN: CNTEN3 Position */
#define EPWM_CNTEN_CNTEN3_Msk (0x1ul << EPWM_CNTEN_CNTEN3_Pos) /*!< EPWM_T::CNTEN: CNTEN3 Mask */
#define EPWM_CNTEN_CNTEN4_Pos (4) /*!< EPWM_T::CNTEN: CNTEN4 Position */
#define EPWM_CNTEN_CNTEN4_Msk (0x1ul << EPWM_CNTEN_CNTEN4_Pos) /*!< EPWM_T::CNTEN: CNTEN4 Mask */
#define EPWM_CNTEN_CNTEN5_Pos (5) /*!< EPWM_T::CNTEN: CNTEN5 Position */
#define EPWM_CNTEN_CNTEN5_Msk (0x1ul << EPWM_CNTEN_CNTEN5_Pos) /*!< EPWM_T::CNTEN: CNTEN5 Mask */
#define EPWM_CNTCLR_CNTCLR0_Pos (0) /*!< EPWM_T::CNTCLR: CNTCLR0 Position */
#define EPWM_CNTCLR_CNTCLR0_Msk (0x1ul << EPWM_CNTCLR_CNTCLR0_Pos) /*!< EPWM_T::CNTCLR: CNTCLR0 Mask */
#define EPWM_CNTCLR_CNTCLR1_Pos (1) /*!< EPWM_T::CNTCLR: CNTCLR1 Position */
#define EPWM_CNTCLR_CNTCLR1_Msk (0x1ul << EPWM_CNTCLR_CNTCLR1_Pos) /*!< EPWM_T::CNTCLR: CNTCLR1 Mask */
#define EPWM_CNTCLR_CNTCLR2_Pos (2) /*!< EPWM_T::CNTCLR: CNTCLR2 Position */
#define EPWM_CNTCLR_CNTCLR2_Msk (0x1ul << EPWM_CNTCLR_CNTCLR2_Pos) /*!< EPWM_T::CNTCLR: CNTCLR2 Mask */
#define EPWM_CNTCLR_CNTCLR3_Pos (3) /*!< EPWM_T::CNTCLR: CNTCLR3 Position */
#define EPWM_CNTCLR_CNTCLR3_Msk (0x1ul << EPWM_CNTCLR_CNTCLR3_Pos) /*!< EPWM_T::CNTCLR: CNTCLR3 Mask */
#define EPWM_CNTCLR_CNTCLR4_Pos (4) /*!< EPWM_T::CNTCLR: CNTCLR4 Position */
#define EPWM_CNTCLR_CNTCLR4_Msk (0x1ul << EPWM_CNTCLR_CNTCLR4_Pos) /*!< EPWM_T::CNTCLR: CNTCLR4 Mask */
#define EPWM_CNTCLR_CNTCLR5_Pos (5) /*!< EPWM_T::CNTCLR: CNTCLR5 Position */
#define EPWM_CNTCLR_CNTCLR5_Msk (0x1ul << EPWM_CNTCLR_CNTCLR5_Pos) /*!< EPWM_T::CNTCLR: CNTCLR5 Mask */
#define EPWM_LOAD_LOAD0_Pos (0) /*!< EPWM_T::LOAD: LOAD0 Position */
#define EPWM_LOAD_LOAD0_Msk (0x1ul << EPWM_LOAD_LOAD0_Pos) /*!< EPWM_T::LOAD: LOAD0 Mask */
#define EPWM_LOAD_LOAD1_Pos (1) /*!< EPWM_T::LOAD: LOAD1 Position */
#define EPWM_LOAD_LOAD1_Msk (0x1ul << EPWM_LOAD_LOAD1_Pos) /*!< EPWM_T::LOAD: LOAD1 Mask */
#define EPWM_LOAD_LOAD2_Pos (2) /*!< EPWM_T::LOAD: LOAD2 Position */
#define EPWM_LOAD_LOAD2_Msk (0x1ul << EPWM_LOAD_LOAD2_Pos) /*!< EPWM_T::LOAD: LOAD2 Mask */
#define EPWM_LOAD_LOAD3_Pos (3) /*!< EPWM_T::LOAD: LOAD3 Position */
#define EPWM_LOAD_LOAD3_Msk (0x1ul << EPWM_LOAD_LOAD3_Pos) /*!< EPWM_T::LOAD: LOAD3 Mask */
#define EPWM_LOAD_LOAD4_Pos (4) /*!< EPWM_T::LOAD: LOAD4 Position */
#define EPWM_LOAD_LOAD4_Msk (0x1ul << EPWM_LOAD_LOAD4_Pos) /*!< EPWM_T::LOAD: LOAD4 Mask */
#define EPWM_LOAD_LOAD5_Pos (5) /*!< EPWM_T::LOAD: LOAD5 Position */
#define EPWM_LOAD_LOAD5_Msk (0x1ul << EPWM_LOAD_LOAD5_Pos) /*!< EPWM_T::LOAD: LOAD5 Mask */
#define EPWM_PERIOD0_PERIOD_Pos (0) /*!< EPWM_T::PERIOD0: PERIOD Position */
#define EPWM_PERIOD0_PERIOD_Msk (0xfffful << EPWM_PERIOD0_PERIOD_Pos) /*!< EPWM_T::PERIOD0: PERIOD Mask */
#define EPWM_PERIOD1_PERIOD_Pos (0) /*!< EPWM_T::PERIOD1: PERIOD Position */
#define EPWM_PERIOD1_PERIOD_Msk (0xfffful << EPWM_PERIOD1_PERIOD_Pos) /*!< EPWM_T::PERIOD1: PERIOD Mask */
#define EPWM_PERIOD2_PERIOD_Pos (0) /*!< EPWM_T::PERIOD2: PERIOD Position */
#define EPWM_PERIOD2_PERIOD_Msk (0xfffful << EPWM_PERIOD2_PERIOD_Pos) /*!< EPWM_T::PERIOD2: PERIOD Mask */
#define EPWM_PERIOD3_PERIOD_Pos (0) /*!< EPWM_T::PERIOD3: PERIOD Position */
#define EPWM_PERIOD3_PERIOD_Msk (0xfffful << EPWM_PERIOD3_PERIOD_Pos) /*!< EPWM_T::PERIOD3: PERIOD Mask */
#define EPWM_PERIOD4_PERIOD_Pos (0) /*!< EPWM_T::PERIOD4: PERIOD Position */
#define EPWM_PERIOD4_PERIOD_Msk (0xfffful << EPWM_PERIOD4_PERIOD_Pos) /*!< EPWM_T::PERIOD4: PERIOD Mask */
#define EPWM_PERIOD5_PERIOD_Pos (0) /*!< EPWM_T::PERIOD5: PERIOD Position */
#define EPWM_PERIOD5_PERIOD_Msk (0xfffful << EPWM_PERIOD5_PERIOD_Pos) /*!< EPWM_T::PERIOD5: PERIOD Mask */
#define EPWM_CMPDAT0_CMP_Pos (0) /*!< EPWM_T::CMPDAT0: CMP Position */
#define EPWM_CMPDAT0_CMP_Msk (0xfffful << EPWM_CMPDAT0_CMP_Pos) /*!< EPWM_T::CMPDAT0: CMP Mask */
#define EPWM_CMPDAT1_CMP_Pos (0) /*!< EPWM_T::CMPDAT1: CMP Position */
#define EPWM_CMPDAT1_CMP_Msk (0xfffful << EPWM_CMPDAT1_CMP_Pos) /*!< EPWM_T::CMPDAT1: CMP Mask */
#define EPWM_CMPDAT2_CMP_Pos (0) /*!< EPWM_T::CMPDAT2: CMP Position */
#define EPWM_CMPDAT2_CMP_Msk (0xfffful << EPWM_CMPDAT2_CMP_Pos) /*!< EPWM_T::CMPDAT2: CMP Mask */
#define EPWM_CMPDAT3_CMP_Pos (0) /*!< EPWM_T::CMPDAT3: CMP Position */
#define EPWM_CMPDAT3_CMP_Msk (0xfffful << EPWM_CMPDAT3_CMP_Pos) /*!< EPWM_T::CMPDAT3: CMP Mask */
#define EPWM_CMPDAT4_CMP_Pos (0) /*!< EPWM_T::CMPDAT4: CMP Position */
#define EPWM_CMPDAT4_CMP_Msk (0xfffful << EPWM_CMPDAT4_CMP_Pos) /*!< EPWM_T::CMPDAT4: CMP Mask */
#define EPWM_CMPDAT5_CMP_Pos (0) /*!< EPWM_T::CMPDAT5: CMP Position */
#define EPWM_CMPDAT5_CMP_Msk (0xfffful << EPWM_CMPDAT5_CMP_Pos) /*!< EPWM_T::CMPDAT5: CMP Mask */
#define EPWM_DTCTL0_1_DTCNT_Pos (0) /*!< EPWM_T::DTCTL0_1: DTCNT Position */
#define EPWM_DTCTL0_1_DTCNT_Msk (0xffful << EPWM_DTCTL0_1_DTCNT_Pos) /*!< EPWM_T::DTCTL0_1: DTCNT Mask */
#define EPWM_DTCTL0_1_DTEN_Pos (16) /*!< EPWM_T::DTCTL0_1: DTEN Position */
#define EPWM_DTCTL0_1_DTEN_Msk (0x1ul << EPWM_DTCTL0_1_DTEN_Pos) /*!< EPWM_T::DTCTL0_1: DTEN Mask */
#define EPWM_DTCTL0_1_DTCKSEL_Pos (24) /*!< EPWM_T::DTCTL0_1: DTCKSEL Position */
#define EPWM_DTCTL0_1_DTCKSEL_Msk (0x1ul << EPWM_DTCTL0_1_DTCKSEL_Pos) /*!< EPWM_T::DTCTL0_1: DTCKSEL Mask */
#define EPWM_DTCTL2_3_DTCNT_Pos (0) /*!< EPWM_T::DTCTL2_3: DTCNT Position */
#define EPWM_DTCTL2_3_DTCNT_Msk (0xffful << EPWM_DTCTL2_3_DTCNT_Pos) /*!< EPWM_T::DTCTL2_3: DTCNT Mask */
#define EPWM_DTCTL2_3_DTEN_Pos (16) /*!< EPWM_T::DTCTL2_3: DTEN Position */
#define EPWM_DTCTL2_3_DTEN_Msk (0x1ul << EPWM_DTCTL2_3_DTEN_Pos) /*!< EPWM_T::DTCTL2_3: DTEN Mask */
#define EPWM_DTCTL2_3_DTCKSEL_Pos (24) /*!< EPWM_T::DTCTL2_3: DTCKSEL Position */
#define EPWM_DTCTL2_3_DTCKSEL_Msk (0x1ul << EPWM_DTCTL2_3_DTCKSEL_Pos) /*!< EPWM_T::DTCTL2_3: DTCKSEL Mask */
#define EPWM_DTCTL4_5_DTCNT_Pos (0) /*!< EPWM_T::DTCTL4_5: DTCNT Position */
#define EPWM_DTCTL4_5_DTCNT_Msk (0xffful << EPWM_DTCTL4_5_DTCNT_Pos) /*!< EPWM_T::DTCTL4_5: DTCNT Mask */
#define EPWM_DTCTL4_5_DTEN_Pos (16) /*!< EPWM_T::DTCTL4_5: DTEN Position */
#define EPWM_DTCTL4_5_DTEN_Msk (0x1ul << EPWM_DTCTL4_5_DTEN_Pos) /*!< EPWM_T::DTCTL4_5: DTEN Mask */
#define EPWM_DTCTL4_5_DTCKSEL_Pos (24) /*!< EPWM_T::DTCTL4_5: DTCKSEL Position */
#define EPWM_DTCTL4_5_DTCKSEL_Msk (0x1ul << EPWM_DTCTL4_5_DTCKSEL_Pos) /*!< EPWM_T::DTCTL4_5: DTCKSEL Mask */
#define EPWM_PHS0_1_PHS_Pos (0) /*!< EPWM_T::PHS0_1: PHS Position */
#define EPWM_PHS0_1_PHS_Msk (0xfffful << EPWM_PHS0_1_PHS_Pos) /*!< EPWM_T::PHS0_1: PHS Mask */
#define EPWM_PHS2_3_PHS_Pos (0) /*!< EPWM_T::PHS2_3: PHS Position */
#define EPWM_PHS2_3_PHS_Msk (0xfffful << EPWM_PHS2_3_PHS_Pos) /*!< EPWM_T::PHS2_3: PHS Mask */
#define EPWM_PHS4_5_PHS_Pos (0) /*!< EPWM_T::PHS4_5: PHS Position */
#define EPWM_PHS4_5_PHS_Msk (0xfffful << EPWM_PHS4_5_PHS_Pos) /*!< EPWM_T::PHS4_5: PHS Mask */
#define EPWM_CNT0_CNT_Pos (0) /*!< EPWM_T::CNT0: CNT Position */
#define EPWM_CNT0_CNT_Msk (0xfffful << EPWM_CNT0_CNT_Pos) /*!< EPWM_T::CNT0: CNT Mask */
#define EPWM_CNT0_DIRF_Pos (16) /*!< EPWM_T::CNT0: DIRF Position */
#define EPWM_CNT0_DIRF_Msk (0x1ul << EPWM_CNT0_DIRF_Pos) /*!< EPWM_T::CNT0: DIRF Mask */
#define EPWM_CNT1_CNT_Pos (0) /*!< EPWM_T::CNT1: CNT Position */
#define EPWM_CNT1_CNT_Msk (0xfffful << EPWM_CNT1_CNT_Pos) /*!< EPWM_T::CNT1: CNT Mask */
#define EPWM_CNT1_DIRF_Pos (16) /*!< EPWM_T::CNT1: DIRF Position */
#define EPWM_CNT1_DIRF_Msk (0x1ul << EPWM_CNT1_DIRF_Pos) /*!< EPWM_T::CNT1: DIRF Mask */
#define EPWM_CNT2_CNT_Pos (0) /*!< EPWM_T::CNT2: CNT Position */
#define EPWM_CNT2_CNT_Msk (0xfffful << EPWM_CNT2_CNT_Pos) /*!< EPWM_T::CNT2: CNT Mask */
#define EPWM_CNT2_DIRF_Pos (16) /*!< EPWM_T::CNT2: DIRF Position */
#define EPWM_CNT2_DIRF_Msk (0x1ul << EPWM_CNT2_DIRF_Pos) /*!< EPWM_T::CNT2: DIRF Mask */
#define EPWM_CNT3_CNT_Pos (0) /*!< EPWM_T::CNT3: CNT Position */
#define EPWM_CNT3_CNT_Msk (0xfffful << EPWM_CNT3_CNT_Pos) /*!< EPWM_T::CNT3: CNT Mask */
#define EPWM_CNT3_DIRF_Pos (16) /*!< EPWM_T::CNT3: DIRF Position */
#define EPWM_CNT3_DIRF_Msk (0x1ul << EPWM_CNT3_DIRF_Pos) /*!< EPWM_T::CNT3: DIRF Mask */
#define EPWM_CNT4_CNT_Pos (0) /*!< EPWM_T::CNT4: CNT Position */
#define EPWM_CNT4_CNT_Msk (0xfffful << EPWM_CNT4_CNT_Pos) /*!< EPWM_T::CNT4: CNT Mask */
#define EPWM_CNT4_DIRF_Pos (16) /*!< EPWM_T::CNT4: DIRF Position */
#define EPWM_CNT4_DIRF_Msk (0x1ul << EPWM_CNT4_DIRF_Pos) /*!< EPWM_T::CNT4: DIRF Mask */
#define EPWM_CNT5_CNT_Pos (0) /*!< EPWM_T::CNT5: CNT Position */
#define EPWM_CNT5_CNT_Msk (0xfffful << EPWM_CNT5_CNT_Pos) /*!< EPWM_T::CNT5: CNT Mask */
#define EPWM_CNT5_DIRF_Pos (16) /*!< EPWM_T::CNT5: DIRF Position */
#define EPWM_CNT5_DIRF_Msk (0x1ul << EPWM_CNT5_DIRF_Pos) /*!< EPWM_T::CNT5: DIRF Mask */
#define EPWM_WGCTL0_ZPCTL0_Pos (0) /*!< EPWM_T::WGCTL0: ZPCTL0 Position */
#define EPWM_WGCTL0_ZPCTL0_Msk (0x3ul << EPWM_WGCTL0_ZPCTL0_Pos) /*!< EPWM_T::WGCTL0: ZPCTL0 Mask */
#define EPWM_WGCTL0_ZPCTL1_Pos (2) /*!< EPWM_T::WGCTL0: ZPCTL1 Position */
#define EPWM_WGCTL0_ZPCTL1_Msk (0x3ul << EPWM_WGCTL0_ZPCTL1_Pos) /*!< EPWM_T::WGCTL0: ZPCTL1 Mask */
#define EPWM_WGCTL0_ZPCTL2_Pos (4) /*!< EPWM_T::WGCTL0: ZPCTL2 Position */
#define EPWM_WGCTL0_ZPCTL2_Msk (0x3ul << EPWM_WGCTL0_ZPCTL2_Pos) /*!< EPWM_T::WGCTL0: ZPCTL2 Mask */
#define EPWM_WGCTL0_ZPCTL3_Pos (6) /*!< EPWM_T::WGCTL0: ZPCTL3 Position */
#define EPWM_WGCTL0_ZPCTL3_Msk (0x3ul << EPWM_WGCTL0_ZPCTL3_Pos) /*!< EPWM_T::WGCTL0: ZPCTL3 Mask */
#define EPWM_WGCTL0_ZPCTL4_Pos (8) /*!< EPWM_T::WGCTL0: ZPCTL4 Position */
#define EPWM_WGCTL0_ZPCTL4_Msk (0x3ul << EPWM_WGCTL0_ZPCTL4_Pos) /*!< EPWM_T::WGCTL0: ZPCTL4 Mask */
#define EPWM_WGCTL0_ZPCTL5_Pos (10) /*!< EPWM_T::WGCTL0: ZPCTL5 Position */
#define EPWM_WGCTL0_ZPCTL5_Msk (0x3ul << EPWM_WGCTL0_ZPCTL5_Pos) /*!< EPWM_T::WGCTL0: ZPCTL5 Mask */
#define EPWM_WGCTL0_PRDPCTL0_Pos (16) /*!< EPWM_T::WGCTL0: PRDPCTL0 Position */
#define EPWM_WGCTL0_PRDPCTL0_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL0_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL0 Mask */
#define EPWM_WGCTL0_PRDPCTL1_Pos (18) /*!< EPWM_T::WGCTL0: PRDPCTL1 Position */
#define EPWM_WGCTL0_PRDPCTL1_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL1_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL1 Mask */
#define EPWM_WGCTL0_PRDPCTL2_Pos (20) /*!< EPWM_T::WGCTL0: PRDPCTL2 Position */
#define EPWM_WGCTL0_PRDPCTL2_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL2_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL2 Mask */
#define EPWM_WGCTL0_PRDPCTL3_Pos (22) /*!< EPWM_T::WGCTL0: PRDPCTL3 Position */
#define EPWM_WGCTL0_PRDPCTL3_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL3_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL3 Mask */
#define EPWM_WGCTL0_PRDPCTL4_Pos (24) /*!< EPWM_T::WGCTL0: PRDPCTL4 Position */
#define EPWM_WGCTL0_PRDPCTL4_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL4_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL4 Mask */
#define EPWM_WGCTL0_PRDPCTL5_Pos (26) /*!< EPWM_T::WGCTL0: PRDPCTL5 Position */
#define EPWM_WGCTL0_PRDPCTL5_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL5_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL5 Mask */
#define EPWM_WGCTL1_CMPUCTL0_Pos (0) /*!< EPWM_T::WGCTL1: CMPUCTL0 Position */
#define EPWM_WGCTL1_CMPUCTL0_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL0_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL0 Mask */
#define EPWM_WGCTL1_CMPUCTL1_Pos (2) /*!< EPWM_T::WGCTL1: CMPUCTL1 Position */
#define EPWM_WGCTL1_CMPUCTL1_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL1_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL1 Mask */
#define EPWM_WGCTL1_CMPUCTL2_Pos (4) /*!< EPWM_T::WGCTL1: CMPUCTL2 Position */
#define EPWM_WGCTL1_CMPUCTL2_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL2_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL2 Mask */
#define EPWM_WGCTL1_CMPUCTL3_Pos (6) /*!< EPWM_T::WGCTL1: CMPUCTL3 Position */
#define EPWM_WGCTL1_CMPUCTL3_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL3_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL3 Mask */
#define EPWM_WGCTL1_CMPUCTL4_Pos (8) /*!< EPWM_T::WGCTL1: CMPUCTL4 Position */
#define EPWM_WGCTL1_CMPUCTL4_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL4_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL4 Mask */
#define EPWM_WGCTL1_CMPUCTL5_Pos (10) /*!< EPWM_T::WGCTL1: CMPUCTL5 Position */
#define EPWM_WGCTL1_CMPUCTL5_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL5_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL5 Mask */
#define EPWM_WGCTL1_CMPDCTL0_Pos (16) /*!< EPWM_T::WGCTL1: CMPDCTL0 Position */
#define EPWM_WGCTL1_CMPDCTL0_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL0_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL0 Mask */
#define EPWM_WGCTL1_CMPDCTL1_Pos (18) /*!< EPWM_T::WGCTL1: CMPDCTL1 Position */
#define EPWM_WGCTL1_CMPDCTL1_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL1_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL1 Mask */
#define EPWM_WGCTL1_CMPDCTL2_Pos (20) /*!< EPWM_T::WGCTL1: CMPDCTL2 Position */
#define EPWM_WGCTL1_CMPDCTL2_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL2_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL2 Mask */
#define EPWM_WGCTL1_CMPDCTL3_Pos (22) /*!< EPWM_T::WGCTL1: CMPDCTL3 Position */
#define EPWM_WGCTL1_CMPDCTL3_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL3_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL3 Mask */
#define EPWM_WGCTL1_CMPDCTL4_Pos (24) /*!< EPWM_T::WGCTL1: CMPDCTL4 Position */
#define EPWM_WGCTL1_CMPDCTL4_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL4_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL4 Mask */
#define EPWM_WGCTL1_CMPDCTL5_Pos (26) /*!< EPWM_T::WGCTL1: CMPDCTL5 Position */
#define EPWM_WGCTL1_CMPDCTL5_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL5_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL5 Mask */
#define EPWM_MSKEN_MSKEN0_Pos (0) /*!< EPWM_T::MSKEN: MSKEN0 Position */
#define EPWM_MSKEN_MSKEN0_Msk (0x1ul << EPWM_MSKEN_MSKEN0_Pos) /*!< EPWM_T::MSKEN: MSKEN0 Mask */
#define EPWM_MSKEN_MSKEN1_Pos (1) /*!< EPWM_T::MSKEN: MSKEN1 Position */
#define EPWM_MSKEN_MSKEN1_Msk (0x1ul << EPWM_MSKEN_MSKEN1_Pos) /*!< EPWM_T::MSKEN: MSKEN1 Mask */
#define EPWM_MSKEN_MSKEN2_Pos (2) /*!< EPWM_T::MSKEN: MSKEN2 Position */
#define EPWM_MSKEN_MSKEN2_Msk (0x1ul << EPWM_MSKEN_MSKEN2_Pos) /*!< EPWM_T::MSKEN: MSKEN2 Mask */
#define EPWM_MSKEN_MSKEN3_Pos (3) /*!< EPWM_T::MSKEN: MSKEN3 Position */
#define EPWM_MSKEN_MSKEN3_Msk (0x1ul << EPWM_MSKEN_MSKEN3_Pos) /*!< EPWM_T::MSKEN: MSKEN3 Mask */
#define EPWM_MSKEN_MSKEN4_Pos (4) /*!< EPWM_T::MSKEN: MSKEN4 Position */
#define EPWM_MSKEN_MSKEN4_Msk (0x1ul << EPWM_MSKEN_MSKEN4_Pos) /*!< EPWM_T::MSKEN: MSKEN4 Mask */
#define EPWM_MSKEN_MSKEN5_Pos (5) /*!< EPWM_T::MSKEN: MSKEN5 Position */
#define EPWM_MSKEN_MSKEN5_Msk (0x1ul << EPWM_MSKEN_MSKEN5_Pos) /*!< EPWM_T::MSKEN: MSKEN5 Mask */
#define EPWM_MSK_MSKDAT0_Pos (0) /*!< EPWM_T::MSK: MSKDAT0 Position */
#define EPWM_MSK_MSKDAT0_Msk (0x1ul << EPWM_MSK_MSKDAT0_Pos) /*!< EPWM_T::MSK: MSKDAT0 Mask */
#define EPWM_MSK_MSKDAT1_Pos (1) /*!< EPWM_T::MSK: MSKDAT1 Position */
#define EPWM_MSK_MSKDAT1_Msk (0x1ul << EPWM_MSK_MSKDAT1_Pos) /*!< EPWM_T::MSK: MSKDAT1 Mask */
#define EPWM_MSK_MSKDAT2_Pos (2) /*!< EPWM_T::MSK: MSKDAT2 Position */
#define EPWM_MSK_MSKDAT2_Msk (0x1ul << EPWM_MSK_MSKDAT2_Pos) /*!< EPWM_T::MSK: MSKDAT2 Mask */
#define EPWM_MSK_MSKDAT3_Pos (3) /*!< EPWM_T::MSK: MSKDAT3 Position */
#define EPWM_MSK_MSKDAT3_Msk (0x1ul << EPWM_MSK_MSKDAT3_Pos) /*!< EPWM_T::MSK: MSKDAT3 Mask */
#define EPWM_MSK_MSKDAT4_Pos (4) /*!< EPWM_T::MSK: MSKDAT4 Position */
#define EPWM_MSK_MSKDAT4_Msk (0x1ul << EPWM_MSK_MSKDAT4_Pos) /*!< EPWM_T::MSK: MSKDAT4 Mask */
#define EPWM_MSK_MSKDAT5_Pos (5) /*!< EPWM_T::MSK: MSKDAT5 Position */
#define EPWM_MSK_MSKDAT5_Msk (0x1ul << EPWM_MSK_MSKDAT5_Pos) /*!< EPWM_T::MSK: MSKDAT5 Mask */
#define EPWM_BNF_BRK0NFEN_Pos (0) /*!< EPWM_T::BNF: BRK0NFEN Position */
#define EPWM_BNF_BRK0NFEN_Msk (0x1ul << EPWM_BNF_BRK0NFEN_Pos) /*!< EPWM_T::BNF: BRK0NFEN Mask */
#define EPWM_BNF_BRK0NFSEL_Pos (1) /*!< EPWM_T::BNF: BRK0NFSEL Position */
#define EPWM_BNF_BRK0NFSEL_Msk (0x7ul << EPWM_BNF_BRK0NFSEL_Pos) /*!< EPWM_T::BNF: BRK0NFSEL Mask */
#define EPWM_BNF_BRK0FCNT_Pos (4) /*!< EPWM_T::BNF: BRK0FCNT Position */
#define EPWM_BNF_BRK0FCNT_Msk (0x7ul << EPWM_BNF_BRK0FCNT_Pos) /*!< EPWM_T::BNF: BRK0FCNT Mask */
#define EPWM_BNF_BRK0PINV_Pos (7) /*!< EPWM_T::BNF: BRK0PINV Position */
#define EPWM_BNF_BRK0PINV_Msk (0x1ul << EPWM_BNF_BRK0PINV_Pos) /*!< EPWM_T::BNF: BRK0PINV Mask */
#define EPWM_BNF_BRK1NFEN_Pos (8) /*!< EPWM_T::BNF: BRK1NFEN Position */
#define EPWM_BNF_BRK1NFEN_Msk (0x1ul << EPWM_BNF_BRK1NFEN_Pos) /*!< EPWM_T::BNF: BRK1NFEN Mask */
#define EPWM_BNF_BRK1NFSEL_Pos (9) /*!< EPWM_T::BNF: BRK1NFSEL Position */
#define EPWM_BNF_BRK1NFSEL_Msk (0x7ul << EPWM_BNF_BRK1NFSEL_Pos) /*!< EPWM_T::BNF: BRK1NFSEL Mask */
#define EPWM_BNF_BRK1FCNT_Pos (12) /*!< EPWM_T::BNF: BRK1FCNT Position */
#define EPWM_BNF_BRK1FCNT_Msk (0x7ul << EPWM_BNF_BRK1FCNT_Pos) /*!< EPWM_T::BNF: BRK1FCNT Mask */
#define EPWM_BNF_BRK1PINV_Pos (15) /*!< EPWM_T::BNF: BRK1PINV Position */
#define EPWM_BNF_BRK1PINV_Msk (0x1ul << EPWM_BNF_BRK1PINV_Pos) /*!< EPWM_T::BNF: BRK1PINV Mask */
#define EPWM_BNF_BK0SRC_Pos (16) /*!< EPWM_T::BNF: BK0SRC Position */
#define EPWM_BNF_BK0SRC_Msk (0x1ul << EPWM_BNF_BK0SRC_Pos) /*!< EPWM_T::BNF: BK0SRC Mask */
#define EPWM_BNF_BK1SRC_Pos (24) /*!< EPWM_T::BNF: BK1SRC Position */
#define EPWM_BNF_BK1SRC_Msk (0x1ul << EPWM_BNF_BK1SRC_Pos) /*!< EPWM_T::BNF: BK1SRC Mask */
#define EPWM_FAILBRK_CSSBRKEN_Pos (0) /*!< EPWM_T::FAILBRK: CSSBRKEN Position */
#define EPWM_FAILBRK_CSSBRKEN_Msk (0x1ul << EPWM_FAILBRK_CSSBRKEN_Pos) /*!< EPWM_T::FAILBRK: CSSBRKEN Mask */
#define EPWM_FAILBRK_BODBRKEN_Pos (1) /*!< EPWM_T::FAILBRK: BODBRKEN Position */
#define EPWM_FAILBRK_BODBRKEN_Msk (0x1ul << EPWM_FAILBRK_BODBRKEN_Pos) /*!< EPWM_T::FAILBRK: BODBRKEN Mask */
#define EPWM_FAILBRK_RAMBRKEN_Pos (2) /*!< EPWM_T::FAILBRK: RAMBRKEN Position */
#define EPWM_FAILBRK_RAMBRKEN_Msk (0x1ul << EPWM_FAILBRK_RAMBRKEN_Pos) /*!< EPWM_T::FAILBRK: RAMBRKEN Mask */
#define EPWM_FAILBRK_CORBRKEN_Pos (3) /*!< EPWM_T::FAILBRK: CORBRKEN Position */
#define EPWM_FAILBRK_CORBRKEN_Msk (0x1ul << EPWM_FAILBRK_CORBRKEN_Pos) /*!< EPWM_T::FAILBRK: CORBRKEN Mask */
#define EPWM_BRKCTL0_1_CPO0EBEN_Pos (0) /*!< EPWM_T::BRKCTL0_1: CPO0EBEN Position */
#define EPWM_BRKCTL0_1_CPO0EBEN_Msk (0x1ul << EPWM_BRKCTL0_1_CPO0EBEN_Pos) /*!< EPWM_T::BRKCTL0_1: CPO0EBEN Mask */
#define EPWM_BRKCTL0_1_CPO1EBEN_Pos (1) /*!< EPWM_T::BRKCTL0_1: CPO1EBEN Position */
#define EPWM_BRKCTL0_1_CPO1EBEN_Msk (0x1ul << EPWM_BRKCTL0_1_CPO1EBEN_Pos) /*!< EPWM_T::BRKCTL0_1: CPO1EBEN Mask */
#define EPWM_BRKCTL0_1_BRKP0EEN_Pos (4) /*!< EPWM_T::BRKCTL0_1: BRKP0EEN Position */
#define EPWM_BRKCTL0_1_BRKP0EEN_Msk (0x1ul << EPWM_BRKCTL0_1_BRKP0EEN_Pos) /*!< EPWM_T::BRKCTL0_1: BRKP0EEN Mask */
#define EPWM_BRKCTL0_1_BRKP1EEN_Pos (5) /*!< EPWM_T::BRKCTL0_1: BRKP1EEN Position */
#define EPWM_BRKCTL0_1_BRKP1EEN_Msk (0x1ul << EPWM_BRKCTL0_1_BRKP1EEN_Pos) /*!< EPWM_T::BRKCTL0_1: BRKP1EEN Mask */
#define EPWM_BRKCTL0_1_SYSEBEN_Pos (7) /*!< EPWM_T::BRKCTL0_1: SYSEBEN Position */
#define EPWM_BRKCTL0_1_SYSEBEN_Msk (0x1ul << EPWM_BRKCTL0_1_SYSEBEN_Pos) /*!< EPWM_T::BRKCTL0_1: SYSEBEN Mask */
#define EPWM_BRKCTL0_1_CPO0LBEN_Pos (8) /*!< EPWM_T::BRKCTL0_1: CPO0LBEN Position */
#define EPWM_BRKCTL0_1_CPO0LBEN_Msk (0x1ul << EPWM_BRKCTL0_1_CPO0LBEN_Pos) /*!< EPWM_T::BRKCTL0_1: CPO0LBEN Mask */
#define EPWM_BRKCTL0_1_CPO1LBEN_Pos (9) /*!< EPWM_T::BRKCTL0_1: CPO1LBEN Position */
#define EPWM_BRKCTL0_1_CPO1LBEN_Msk (0x1ul << EPWM_BRKCTL0_1_CPO1LBEN_Pos) /*!< EPWM_T::BRKCTL0_1: CPO1LBEN Mask */
#define EPWM_BRKCTL0_1_BRKP0LEN_Pos (12) /*!< EPWM_T::BRKCTL0_1: BRKP0LEN Position */
#define EPWM_BRKCTL0_1_BRKP0LEN_Msk (0x1ul << EPWM_BRKCTL0_1_BRKP0LEN_Pos) /*!< EPWM_T::BRKCTL0_1: BRKP0LEN Mask */
#define EPWM_BRKCTL0_1_BRKP1LEN_Pos (13) /*!< EPWM_T::BRKCTL0_1: BRKP1LEN Position */
#define EPWM_BRKCTL0_1_BRKP1LEN_Msk (0x1ul << EPWM_BRKCTL0_1_BRKP1LEN_Pos) /*!< EPWM_T::BRKCTL0_1: BRKP1LEN Mask */
#define EPWM_BRKCTL0_1_SYSLBEN_Pos (15) /*!< EPWM_T::BRKCTL0_1: SYSLBEN Position */
#define EPWM_BRKCTL0_1_SYSLBEN_Msk (0x1ul << EPWM_BRKCTL0_1_SYSLBEN_Pos) /*!< EPWM_T::BRKCTL0_1: SYSLBEN Mask */
#define EPWM_BRKCTL0_1_BRKAEVEN_Pos (16) /*!< EPWM_T::BRKCTL0_1: BRKAEVEN Position */
#define EPWM_BRKCTL0_1_BRKAEVEN_Msk (0x3ul << EPWM_BRKCTL0_1_BRKAEVEN_Pos) /*!< EPWM_T::BRKCTL0_1: BRKAEVEN Mask */
#define EPWM_BRKCTL0_1_BRKAODD_Pos (18) /*!< EPWM_T::BRKCTL0_1: BRKAODD Position */
#define EPWM_BRKCTL0_1_BRKAODD_Msk (0x3ul << EPWM_BRKCTL0_1_BRKAODD_Pos) /*!< EPWM_T::BRKCTL0_1: BRKAODD Mask */
#define EPWM_BRKCTL0_1_EADCEBEN_Pos (20) /*!< EPWM_T::BRKCTL0_1: EADCEBEN Position */
#define EPWM_BRKCTL0_1_EADCEBEN_Msk (0x1ul << EPWM_BRKCTL0_1_EADCEBEN_Pos) /*!< EPWM_T::BRKCTL0_1: EADCEBEN Mask */
#define EPWM_BRKCTL0_1_EADCLBEN_Pos (28) /*!< EPWM_T::BRKCTL0_1: EADCLBEN Position */
#define EPWM_BRKCTL0_1_EADCLBEN_Msk (0x1ul << EPWM_BRKCTL0_1_EADCLBEN_Pos) /*!< EPWM_T::BRKCTL0_1: EADCLBEN Mask */
#define EPWM_BRKCTL2_3_CPO0EBEN_Pos (0) /*!< EPWM_T::BRKCTL2_3: CPO0EBEN Position */
#define EPWM_BRKCTL2_3_CPO0EBEN_Msk (0x1ul << EPWM_BRKCTL2_3_CPO0EBEN_Pos) /*!< EPWM_T::BRKCTL2_3: CPO0EBEN Mask */
#define EPWM_BRKCTL2_3_CPO1EBEN_Pos (1) /*!< EPWM_T::BRKCTL2_3: CPO1EBEN Position */
#define EPWM_BRKCTL2_3_CPO1EBEN_Msk (0x1ul << EPWM_BRKCTL2_3_CPO1EBEN_Pos) /*!< EPWM_T::BRKCTL2_3: CPO1EBEN Mask */
#define EPWM_BRKCTL2_3_BRKP0EEN_Pos (4) /*!< EPWM_T::BRKCTL2_3: BRKP0EEN Position */
#define EPWM_BRKCTL2_3_BRKP0EEN_Msk (0x1ul << EPWM_BRKCTL2_3_BRKP0EEN_Pos) /*!< EPWM_T::BRKCTL2_3: BRKP0EEN Mask */
#define EPWM_BRKCTL2_3_BRKP1EEN_Pos (5) /*!< EPWM_T::BRKCTL2_3: BRKP1EEN Position */
#define EPWM_BRKCTL2_3_BRKP1EEN_Msk (0x1ul << EPWM_BRKCTL2_3_BRKP1EEN_Pos) /*!< EPWM_T::BRKCTL2_3: BRKP1EEN Mask */
#define EPWM_BRKCTL2_3_SYSEBEN_Pos (7) /*!< EPWM_T::BRKCTL2_3: SYSEBEN Position */
#define EPWM_BRKCTL2_3_SYSEBEN_Msk (0x1ul << EPWM_BRKCTL2_3_SYSEBEN_Pos) /*!< EPWM_T::BRKCTL2_3: SYSEBEN Mask */
#define EPWM_BRKCTL2_3_CPO0LBEN_Pos (8) /*!< EPWM_T::BRKCTL2_3: CPO0LBEN Position */
#define EPWM_BRKCTL2_3_CPO0LBEN_Msk (0x1ul << EPWM_BRKCTL2_3_CPO0LBEN_Pos) /*!< EPWM_T::BRKCTL2_3: CPO0LBEN Mask */
#define EPWM_BRKCTL2_3_CPO1LBEN_Pos (9) /*!< EPWM_T::BRKCTL2_3: CPO1LBEN Position */
#define EPWM_BRKCTL2_3_CPO1LBEN_Msk (0x1ul << EPWM_BRKCTL2_3_CPO1LBEN_Pos) /*!< EPWM_T::BRKCTL2_3: CPO1LBEN Mask */
#define EPWM_BRKCTL2_3_BRKP0LEN_Pos (12) /*!< EPWM_T::BRKCTL2_3: BRKP0LEN Position */
#define EPWM_BRKCTL2_3_BRKP0LEN_Msk (0x1ul << EPWM_BRKCTL2_3_BRKP0LEN_Pos) /*!< EPWM_T::BRKCTL2_3: BRKP0LEN Mask */
#define EPWM_BRKCTL2_3_BRKP1LEN_Pos (13) /*!< EPWM_T::BRKCTL2_3: BRKP1LEN Position */
#define EPWM_BRKCTL2_3_BRKP1LEN_Msk (0x1ul << EPWM_BRKCTL2_3_BRKP1LEN_Pos) /*!< EPWM_T::BRKCTL2_3: BRKP1LEN Mask */
#define EPWM_BRKCTL2_3_SYSLBEN_Pos (15) /*!< EPWM_T::BRKCTL2_3: SYSLBEN Position */
#define EPWM_BRKCTL2_3_SYSLBEN_Msk (0x1ul << EPWM_BRKCTL2_3_SYSLBEN_Pos) /*!< EPWM_T::BRKCTL2_3: SYSLBEN Mask */
#define EPWM_BRKCTL2_3_BRKAEVEN_Pos (16) /*!< EPWM_T::BRKCTL2_3: BRKAEVEN Position */
#define EPWM_BRKCTL2_3_BRKAEVEN_Msk (0x3ul << EPWM_BRKCTL2_3_BRKAEVEN_Pos) /*!< EPWM_T::BRKCTL2_3: BRKAEVEN Mask */
#define EPWM_BRKCTL2_3_BRKAODD_Pos (18) /*!< EPWM_T::BRKCTL2_3: BRKAODD Position */
#define EPWM_BRKCTL2_3_BRKAODD_Msk (0x3ul << EPWM_BRKCTL2_3_BRKAODD_Pos) /*!< EPWM_T::BRKCTL2_3: BRKAODD Mask */
#define EPWM_BRKCTL2_3_EADCEBEN_Pos (20) /*!< EPWM_T::BRKCTL2_3: EADCEBEN Position */
#define EPWM_BRKCTL2_3_EADCEBEN_Msk (0x1ul << EPWM_BRKCTL2_3_EADCEBEN_Pos) /*!< EPWM_T::BRKCTL2_3: EADCEBEN Mask */
#define EPWM_BRKCTL2_3_EADCLBEN_Pos (28) /*!< EPWM_T::BRKCTL2_3: EADCLBEN Position */
#define EPWM_BRKCTL2_3_EADCLBEN_Msk (0x1ul << EPWM_BRKCTL2_3_EADCLBEN_Pos) /*!< EPWM_T::BRKCTL2_3: EADCLBEN Mask */
#define EPWM_BRKCTL4_5_CPO0EBEN_Pos (0) /*!< EPWM_T::BRKCTL4_5: CPO0EBEN Position */
#define EPWM_BRKCTL4_5_CPO0EBEN_Msk (0x1ul << EPWM_BRKCTL4_5_CPO0EBEN_Pos) /*!< EPWM_T::BRKCTL4_5: CPO0EBEN Mask */
#define EPWM_BRKCTL4_5_CPO1EBEN_Pos (1) /*!< EPWM_T::BRKCTL4_5: CPO1EBEN Position */
#define EPWM_BRKCTL4_5_CPO1EBEN_Msk (0x1ul << EPWM_BRKCTL4_5_CPO1EBEN_Pos) /*!< EPWM_T::BRKCTL4_5: CPO1EBEN Mask */
#define EPWM_BRKCTL4_5_BRKP0EEN_Pos (4) /*!< EPWM_T::BRKCTL4_5: BRKP0EEN Position */
#define EPWM_BRKCTL4_5_BRKP0EEN_Msk (0x1ul << EPWM_BRKCTL4_5_BRKP0EEN_Pos) /*!< EPWM_T::BRKCTL4_5: BRKP0EEN Mask */
#define EPWM_BRKCTL4_5_BRKP1EEN_Pos (5) /*!< EPWM_T::BRKCTL4_5: BRKP1EEN Position */
#define EPWM_BRKCTL4_5_BRKP1EEN_Msk (0x1ul << EPWM_BRKCTL4_5_BRKP1EEN_Pos) /*!< EPWM_T::BRKCTL4_5: BRKP1EEN Mask */
#define EPWM_BRKCTL4_5_SYSEBEN_Pos (7) /*!< EPWM_T::BRKCTL4_5: SYSEBEN Position */
#define EPWM_BRKCTL4_5_SYSEBEN_Msk (0x1ul << EPWM_BRKCTL4_5_SYSEBEN_Pos) /*!< EPWM_T::BRKCTL4_5: SYSEBEN Mask */
#define EPWM_BRKCTL4_5_CPO0LBEN_Pos (8) /*!< EPWM_T::BRKCTL4_5: CPO0LBEN Position */
#define EPWM_BRKCTL4_5_CPO0LBEN_Msk (0x1ul << EPWM_BRKCTL4_5_CPO0LBEN_Pos) /*!< EPWM_T::BRKCTL4_5: CPO0LBEN Mask */
#define EPWM_BRKCTL4_5_CPO1LBEN_Pos (9) /*!< EPWM_T::BRKCTL4_5: CPO1LBEN Position */
#define EPWM_BRKCTL4_5_CPO1LBEN_Msk (0x1ul << EPWM_BRKCTL4_5_CPO1LBEN_Pos) /*!< EPWM_T::BRKCTL4_5: CPO1LBEN Mask */
#define EPWM_BRKCTL4_5_BRKP0LEN_Pos (12) /*!< EPWM_T::BRKCTL4_5: BRKP0LEN Position */
#define EPWM_BRKCTL4_5_BRKP0LEN_Msk (0x1ul << EPWM_BRKCTL4_5_BRKP0LEN_Pos) /*!< EPWM_T::BRKCTL4_5: BRKP0LEN Mask */
#define EPWM_BRKCTL4_5_BRKP1LEN_Pos (13) /*!< EPWM_T::BRKCTL4_5: BRKP1LEN Position */
#define EPWM_BRKCTL4_5_BRKP1LEN_Msk (0x1ul << EPWM_BRKCTL4_5_BRKP1LEN_Pos) /*!< EPWM_T::BRKCTL4_5: BRKP1LEN Mask */
#define EPWM_BRKCTL4_5_SYSLBEN_Pos (15) /*!< EPWM_T::BRKCTL4_5: SYSLBEN Position */
#define EPWM_BRKCTL4_5_SYSLBEN_Msk (0x1ul << EPWM_BRKCTL4_5_SYSLBEN_Pos) /*!< EPWM_T::BRKCTL4_5: SYSLBEN Mask */
#define EPWM_BRKCTL4_5_BRKAEVEN_Pos (16) /*!< EPWM_T::BRKCTL4_5: BRKAEVEN Position */
#define EPWM_BRKCTL4_5_BRKAEVEN_Msk (0x3ul << EPWM_BRKCTL4_5_BRKAEVEN_Pos) /*!< EPWM_T::BRKCTL4_5: BRKAEVEN Mask */
#define EPWM_BRKCTL4_5_BRKAODD_Pos (18) /*!< EPWM_T::BRKCTL4_5: BRKAODD Position */
#define EPWM_BRKCTL4_5_BRKAODD_Msk (0x3ul << EPWM_BRKCTL4_5_BRKAODD_Pos) /*!< EPWM_T::BRKCTL4_5: BRKAODD Mask */
#define EPWM_BRKCTL4_5_EADCEBEN_Pos (20) /*!< EPWM_T::BRKCTL4_5: EADCEBEN Position */
#define EPWM_BRKCTL4_5_EADCEBEN_Msk (0x1ul << EPWM_BRKCTL4_5_EADCEBEN_Pos) /*!< EPWM_T::BRKCTL4_5: EADCEBEN Mask */
#define EPWM_BRKCTL4_5_EADCLBEN_Pos (28) /*!< EPWM_T::BRKCTL4_5: EADCLBEN Position */
#define EPWM_BRKCTL4_5_EADCLBEN_Msk (0x1ul << EPWM_BRKCTL4_5_EADCLBEN_Pos) /*!< EPWM_T::BRKCTL4_5: EADCLBEN Mask */
#define EPWM_POLCTL_PINV0_Pos (0) /*!< EPWM_T::POLCTL: PINV0 Position */
#define EPWM_POLCTL_PINV0_Msk (0x1ul << EPWM_POLCTL_PINV0_Pos) /*!< EPWM_T::POLCTL: PINV0 Mask */
#define EPWM_POLCTL_PINV1_Pos (1) /*!< EPWM_T::POLCTL: PINV1 Position */
#define EPWM_POLCTL_PINV1_Msk (0x1ul << EPWM_POLCTL_PINV1_Pos) /*!< EPWM_T::POLCTL: PINV1 Mask */
#define EPWM_POLCTL_PINV2_Pos (2) /*!< EPWM_T::POLCTL: PINV2 Position */
#define EPWM_POLCTL_PINV2_Msk (0x1ul << EPWM_POLCTL_PINV2_Pos) /*!< EPWM_T::POLCTL: PINV2 Mask */
#define EPWM_POLCTL_PINV3_Pos (3) /*!< EPWM_T::POLCTL: PINV3 Position */
#define EPWM_POLCTL_PINV3_Msk (0x1ul << EPWM_POLCTL_PINV3_Pos) /*!< EPWM_T::POLCTL: PINV3 Mask */
#define EPWM_POLCTL_PINV4_Pos (4) /*!< EPWM_T::POLCTL: PINV4 Position */
#define EPWM_POLCTL_PINV4_Msk (0x1ul << EPWM_POLCTL_PINV4_Pos) /*!< EPWM_T::POLCTL: PINV4 Mask */
#define EPWM_POLCTL_PINV5_Pos (5) /*!< EPWM_T::POLCTL: PINV5 Position */
#define EPWM_POLCTL_PINV5_Msk (0x1ul << EPWM_POLCTL_PINV5_Pos) /*!< EPWM_T::POLCTL: PINV5 Mask */
#define EPWM_POEN_POEN0_Pos (0) /*!< EPWM_T::POEN: POEN0 Position */
#define EPWM_POEN_POEN0_Msk (0x1ul << EPWM_POEN_POEN0_Pos) /*!< EPWM_T::POEN: POEN0 Mask */
#define EPWM_POEN_POEN1_Pos (1) /*!< EPWM_T::POEN: POEN1 Position */
#define EPWM_POEN_POEN1_Msk (0x1ul << EPWM_POEN_POEN1_Pos) /*!< EPWM_T::POEN: POEN1 Mask */
#define EPWM_POEN_POEN2_Pos (2) /*!< EPWM_T::POEN: POEN2 Position */
#define EPWM_POEN_POEN2_Msk (0x1ul << EPWM_POEN_POEN2_Pos) /*!< EPWM_T::POEN: POEN2 Mask */
#define EPWM_POEN_POEN3_Pos (3) /*!< EPWM_T::POEN: POEN3 Position */
#define EPWM_POEN_POEN3_Msk (0x1ul << EPWM_POEN_POEN3_Pos) /*!< EPWM_T::POEN: POEN3 Mask */
#define EPWM_POEN_POEN4_Pos (4) /*!< EPWM_T::POEN: POEN4 Position */
#define EPWM_POEN_POEN4_Msk (0x1ul << EPWM_POEN_POEN4_Pos) /*!< EPWM_T::POEN: POEN4 Mask */
#define EPWM_POEN_POEN5_Pos (5) /*!< EPWM_T::POEN: POEN5 Position */
#define EPWM_POEN_POEN5_Msk (0x1ul << EPWM_POEN_POEN5_Pos) /*!< EPWM_T::POEN: POEN5 Mask */
#define EPWM_SWBRK_BRKETRG0_Pos (0) /*!< EPWM_T::SWBRK: BRKETRG0 Position */
#define EPWM_SWBRK_BRKETRG0_Msk (0x1ul << EPWM_SWBRK_BRKETRG0_Pos) /*!< EPWM_T::SWBRK: BRKETRG0 Mask */
#define EPWM_SWBRK_BRKETRG2_Pos (1) /*!< EPWM_T::SWBRK: BRKETRG2 Position */
#define EPWM_SWBRK_BRKETRG2_Msk (0x1ul << EPWM_SWBRK_BRKETRG2_Pos) /*!< EPWM_T::SWBRK: BRKETRG2 Mask */
#define EPWM_SWBRK_BRKETRG4_Pos (2) /*!< EPWM_T::SWBRK: BRKETRG4 Position */
#define EPWM_SWBRK_BRKETRG4_Msk (0x1ul << EPWM_SWBRK_BRKETRG4_Pos) /*!< EPWM_T::SWBRK: BRKETRG4 Mask */
#define EPWM_SWBRK_BRKLTRG0_Pos (8) /*!< EPWM_T::SWBRK: BRKLTRG0 Position */
#define EPWM_SWBRK_BRKLTRG0_Msk (0x1ul << EPWM_SWBRK_BRKLTRG0_Pos) /*!< EPWM_T::SWBRK: BRKLTRG0 Mask */
#define EPWM_SWBRK_BRKLTRG2_Pos (9) /*!< EPWM_T::SWBRK: BRKLTRG2 Position */
#define EPWM_SWBRK_BRKLTRG2_Msk (0x1ul << EPWM_SWBRK_BRKLTRG2_Pos) /*!< EPWM_T::SWBRK: BRKLTRG2 Mask */
#define EPWM_SWBRK_BRKLTRG4_Pos (10) /*!< EPWM_T::SWBRK: BRKLTRG4 Position */
#define EPWM_SWBRK_BRKLTRG4_Msk (0x1ul << EPWM_SWBRK_BRKLTRG4_Pos) /*!< EPWM_T::SWBRK: BRKLTRG4 Mask */
#define EPWM_INTEN0_ZIEN0_Pos (0) /*!< EPWM_T::INTEN0: ZIEN0 Position */
#define EPWM_INTEN0_ZIEN0_Msk (0x1ul << EPWM_INTEN0_ZIEN0_Pos) /*!< EPWM_T::INTEN0: ZIEN0 Mask */
#define EPWM_INTEN0_ZIEN1_Pos (1) /*!< EPWM_T::INTEN0: ZIEN1 Position */
#define EPWM_INTEN0_ZIEN1_Msk (0x1ul << EPWM_INTEN0_ZIEN1_Pos) /*!< EPWM_T::INTEN0: ZIEN1 Mask */
#define EPWM_INTEN0_ZIEN2_Pos (2) /*!< EPWM_T::INTEN0: ZIEN2 Position */
#define EPWM_INTEN0_ZIEN2_Msk (0x1ul << EPWM_INTEN0_ZIEN2_Pos) /*!< EPWM_T::INTEN0: ZIEN2 Mask */
#define EPWM_INTEN0_ZIEN3_Pos (3) /*!< EPWM_T::INTEN0: ZIEN3 Position */
#define EPWM_INTEN0_ZIEN3_Msk (0x1ul << EPWM_INTEN0_ZIEN3_Pos) /*!< EPWM_T::INTEN0: ZIEN3 Mask */
#define EPWM_INTEN0_ZIEN4_Pos (4) /*!< EPWM_T::INTEN0: ZIEN4 Position */
#define EPWM_INTEN0_ZIEN4_Msk (0x1ul << EPWM_INTEN0_ZIEN4_Pos) /*!< EPWM_T::INTEN0: ZIEN4 Mask */
#define EPWM_INTEN0_ZIEN5_Pos (5) /*!< EPWM_T::INTEN0: ZIEN5 Position */
#define EPWM_INTEN0_ZIEN5_Msk (0x1ul << EPWM_INTEN0_ZIEN5_Pos) /*!< EPWM_T::INTEN0: ZIEN5 Mask */
#define EPWM_INTEN0_PIEN0_Pos (8) /*!< EPWM_T::INTEN0: PIEN0 Position */
#define EPWM_INTEN0_PIEN0_Msk (0x1ul << EPWM_INTEN0_PIEN0_Pos) /*!< EPWM_T::INTEN0: PIEN0 Mask */
#define EPWM_INTEN0_PIEN1_Pos (9) /*!< EPWM_T::INTEN0: PIEN1 Position */
#define EPWM_INTEN0_PIEN1_Msk (0x1ul << EPWM_INTEN0_PIEN1_Pos) /*!< EPWM_T::INTEN0: PIEN1 Mask */
#define EPWM_INTEN0_PIEN2_Pos (10) /*!< EPWM_T::INTEN0: PIEN2 Position */
#define EPWM_INTEN0_PIEN2_Msk (0x1ul << EPWM_INTEN0_PIEN2_Pos) /*!< EPWM_T::INTEN0: PIEN2 Mask */
#define EPWM_INTEN0_PIEN3_Pos (11) /*!< EPWM_T::INTEN0: PIEN3 Position */
#define EPWM_INTEN0_PIEN3_Msk (0x1ul << EPWM_INTEN0_PIEN3_Pos) /*!< EPWM_T::INTEN0: PIEN3 Mask */
#define EPWM_INTEN0_PIEN4_Pos (12) /*!< EPWM_T::INTEN0: PIEN4 Position */
#define EPWM_INTEN0_PIEN4_Msk (0x1ul << EPWM_INTEN0_PIEN4_Pos) /*!< EPWM_T::INTEN0: PIEN4 Mask */
#define EPWM_INTEN0_PIEN5_Pos (13) /*!< EPWM_T::INTEN0: PIEN5 Position */
#define EPWM_INTEN0_PIEN5_Msk (0x1ul << EPWM_INTEN0_PIEN5_Pos) /*!< EPWM_T::INTEN0: PIEN5 Mask */
#define EPWM_INTEN0_CMPUIEN0_Pos (16) /*!< EPWM_T::INTEN0: CMPUIEN0 Position */
#define EPWM_INTEN0_CMPUIEN0_Msk (0x1ul << EPWM_INTEN0_CMPUIEN0_Pos) /*!< EPWM_T::INTEN0: CMPUIEN0 Mask */
#define EPWM_INTEN0_CMPUIEN1_Pos (17) /*!< EPWM_T::INTEN0: CMPUIEN1 Position */
#define EPWM_INTEN0_CMPUIEN1_Msk (0x1ul << EPWM_INTEN0_CMPUIEN1_Pos) /*!< EPWM_T::INTEN0: CMPUIEN1 Mask */
#define EPWM_INTEN0_CMPUIEN2_Pos (18) /*!< EPWM_T::INTEN0: CMPUIEN2 Position */
#define EPWM_INTEN0_CMPUIEN2_Msk (0x1ul << EPWM_INTEN0_CMPUIEN2_Pos) /*!< EPWM_T::INTEN0: CMPUIEN2 Mask */
#define EPWM_INTEN0_CMPUIEN3_Pos (19) /*!< EPWM_T::INTEN0: CMPUIEN3 Position */
#define EPWM_INTEN0_CMPUIEN3_Msk (0x1ul << EPWM_INTEN0_CMPUIEN3_Pos) /*!< EPWM_T::INTEN0: CMPUIEN3 Mask */
#define EPWM_INTEN0_CMPUIEN4_Pos (20) /*!< EPWM_T::INTEN0: CMPUIEN4 Position */
#define EPWM_INTEN0_CMPUIEN4_Msk (0x1ul << EPWM_INTEN0_CMPUIEN4_Pos) /*!< EPWM_T::INTEN0: CMPUIEN4 Mask */
#define EPWM_INTEN0_CMPUIEN5_Pos (21) /*!< EPWM_T::INTEN0: CMPUIEN5 Position */
#define EPWM_INTEN0_CMPUIEN5_Msk (0x1ul << EPWM_INTEN0_CMPUIEN5_Pos) /*!< EPWM_T::INTEN0: CMPUIEN5 Mask */
#define EPWM_INTEN0_CMPDIEN0_Pos (24) /*!< EPWM_T::INTEN0: CMPDIEN0 Position */
#define EPWM_INTEN0_CMPDIEN0_Msk (0x1ul << EPWM_INTEN0_CMPDIEN0_Pos) /*!< EPWM_T::INTEN0: CMPDIEN0 Mask */
#define EPWM_INTEN0_CMPDIEN1_Pos (25) /*!< EPWM_T::INTEN0: CMPDIEN1 Position */
#define EPWM_INTEN0_CMPDIEN1_Msk (0x1ul << EPWM_INTEN0_CMPDIEN1_Pos) /*!< EPWM_T::INTEN0: CMPDIEN1 Mask */
#define EPWM_INTEN0_CMPDIEN2_Pos (26) /*!< EPWM_T::INTEN0: CMPDIEN2 Position */
#define EPWM_INTEN0_CMPDIEN2_Msk (0x1ul << EPWM_INTEN0_CMPDIEN2_Pos) /*!< EPWM_T::INTEN0: CMPDIEN2 Mask */
#define EPWM_INTEN0_CMPDIEN3_Pos (27) /*!< EPWM_T::INTEN0: CMPDIEN3 Position */
#define EPWM_INTEN0_CMPDIEN3_Msk (0x1ul << EPWM_INTEN0_CMPDIEN3_Pos) /*!< EPWM_T::INTEN0: CMPDIEN3 Mask */
#define EPWM_INTEN0_CMPDIEN4_Pos (28) /*!< EPWM_T::INTEN0: CMPDIEN4 Position */
#define EPWM_INTEN0_CMPDIEN4_Msk (0x1ul << EPWM_INTEN0_CMPDIEN4_Pos) /*!< EPWM_T::INTEN0: CMPDIEN4 Mask */
#define EPWM_INTEN0_CMPDIEN5_Pos (29) /*!< EPWM_T::INTEN0: CMPDIEN5 Position */
#define EPWM_INTEN0_CMPDIEN5_Msk (0x1ul << EPWM_INTEN0_CMPDIEN5_Pos) /*!< EPWM_T::INTEN0: CMPDIEN5 Mask */
#define EPWM_INTEN1_BRKEIEN0_1_Pos (0) /*!< EPWM_T::INTEN1: BRKEIEN0_1 Position */
#define EPWM_INTEN1_BRKEIEN0_1_Msk (0x1ul << EPWM_INTEN1_BRKEIEN0_1_Pos) /*!< EPWM_T::INTEN1: BRKEIEN0_1 Mask */
#define EPWM_INTEN1_BRKEIEN2_3_Pos (1) /*!< EPWM_T::INTEN1: BRKEIEN2_3 Position */
#define EPWM_INTEN1_BRKEIEN2_3_Msk (0x1ul << EPWM_INTEN1_BRKEIEN2_3_Pos) /*!< EPWM_T::INTEN1: BRKEIEN2_3 Mask */
#define EPWM_INTEN1_BRKEIEN4_5_Pos (2) /*!< EPWM_T::INTEN1: BRKEIEN4_5 Position */
#define EPWM_INTEN1_BRKEIEN4_5_Msk (0x1ul << EPWM_INTEN1_BRKEIEN4_5_Pos) /*!< EPWM_T::INTEN1: BRKEIEN4_5 Mask */
#define EPWM_INTEN1_BRKLIEN0_1_Pos (8) /*!< EPWM_T::INTEN1: BRKLIEN0_1 Position */
#define EPWM_INTEN1_BRKLIEN0_1_Msk (0x1ul << EPWM_INTEN1_BRKLIEN0_1_Pos) /*!< EPWM_T::INTEN1: BRKLIEN0_1 Mask */
#define EPWM_INTEN1_BRKLIEN2_3_Pos (9) /*!< EPWM_T::INTEN1: BRKLIEN2_3 Position */
#define EPWM_INTEN1_BRKLIEN2_3_Msk (0x1ul << EPWM_INTEN1_BRKLIEN2_3_Pos) /*!< EPWM_T::INTEN1: BRKLIEN2_3 Mask */
#define EPWM_INTEN1_BRKLIEN4_5_Pos (10) /*!< EPWM_T::INTEN1: BRKLIEN4_5 Position */
#define EPWM_INTEN1_BRKLIEN4_5_Msk (0x1ul << EPWM_INTEN1_BRKLIEN4_5_Pos) /*!< EPWM_T::INTEN1: BRKLIEN4_5 Mask */
#define EPWM_INTSTS0_ZIF0_Pos (0) /*!< EPWM_T::INTSTS0: ZIF0 Position */
#define EPWM_INTSTS0_ZIF0_Msk (0x1ul << EPWM_INTSTS0_ZIF0_Pos) /*!< EPWM_T::INTSTS0: ZIF0 Mask */
#define EPWM_INTSTS0_ZIF1_Pos (1) /*!< EPWM_T::INTSTS0: ZIF1 Position */
#define EPWM_INTSTS0_ZIF1_Msk (0x1ul << EPWM_INTSTS0_ZIF1_Pos) /*!< EPWM_T::INTSTS0: ZIF1 Mask */
#define EPWM_INTSTS0_ZIF2_Pos (2) /*!< EPWM_T::INTSTS0: ZIF2 Position */
#define EPWM_INTSTS0_ZIF2_Msk (0x1ul << EPWM_INTSTS0_ZIF2_Pos) /*!< EPWM_T::INTSTS0: ZIF2 Mask */
#define EPWM_INTSTS0_ZIF3_Pos (3) /*!< EPWM_T::INTSTS0: ZIF3 Position */
#define EPWM_INTSTS0_ZIF3_Msk (0x1ul << EPWM_INTSTS0_ZIF3_Pos) /*!< EPWM_T::INTSTS0: ZIF3 Mask */
#define EPWM_INTSTS0_ZIF4_Pos (4) /*!< EPWM_T::INTSTS0: ZIF4 Position */
#define EPWM_INTSTS0_ZIF4_Msk (0x1ul << EPWM_INTSTS0_ZIF4_Pos) /*!< EPWM_T::INTSTS0: ZIF4 Mask */
#define EPWM_INTSTS0_ZIF5_Pos (5) /*!< EPWM_T::INTSTS0: ZIF5 Position */
#define EPWM_INTSTS0_ZIF5_Msk (0x1ul << EPWM_INTSTS0_ZIF5_Pos) /*!< EPWM_T::INTSTS0: ZIF5 Mask */
#define EPWM_INTSTS0_PIF0_Pos (8) /*!< EPWM_T::INTSTS0: PIF0 Position */
#define EPWM_INTSTS0_PIF0_Msk (0x1ul << EPWM_INTSTS0_PIF0_Pos) /*!< EPWM_T::INTSTS0: PIF0 Mask */
#define EPWM_INTSTS0_PIF1_Pos (9) /*!< EPWM_T::INTSTS0: PIF1 Position */
#define EPWM_INTSTS0_PIF1_Msk (0x1ul << EPWM_INTSTS0_PIF1_Pos) /*!< EPWM_T::INTSTS0: PIF1 Mask */
#define EPWM_INTSTS0_PIF2_Pos (10) /*!< EPWM_T::INTSTS0: PIF2 Position */
#define EPWM_INTSTS0_PIF2_Msk (0x1ul << EPWM_INTSTS0_PIF2_Pos) /*!< EPWM_T::INTSTS0: PIF2 Mask */
#define EPWM_INTSTS0_PIF3_Pos (11) /*!< EPWM_T::INTSTS0: PIF3 Position */
#define EPWM_INTSTS0_PIF3_Msk (0x1ul << EPWM_INTSTS0_PIF3_Pos) /*!< EPWM_T::INTSTS0: PIF3 Mask */
#define EPWM_INTSTS0_PIF4_Pos (12) /*!< EPWM_T::INTSTS0: PIF4 Position */
#define EPWM_INTSTS0_PIF4_Msk (0x1ul << EPWM_INTSTS0_PIF4_Pos) /*!< EPWM_T::INTSTS0: PIF4 Mask */
#define EPWM_INTSTS0_PIF5_Pos (13) /*!< EPWM_T::INTSTS0: PIF5 Position */
#define EPWM_INTSTS0_PIF5_Msk (0x1ul << EPWM_INTSTS0_PIF5_Pos) /*!< EPWM_T::INTSTS0: PIF5 Mask */
#define EPWM_INTSTS0_CMPUIF0_Pos (16) /*!< EPWM_T::INTSTS0: CMPUIF0 Position */
#define EPWM_INTSTS0_CMPUIF0_Msk (0x1ul << EPWM_INTSTS0_CMPUIF0_Pos) /*!< EPWM_T::INTSTS0: CMPUIF0 Mask */
#define EPWM_INTSTS0_CMPUIF1_Pos (17) /*!< EPWM_T::INTSTS0: CMPUIF1 Position */
#define EPWM_INTSTS0_CMPUIF1_Msk (0x1ul << EPWM_INTSTS0_CMPUIF1_Pos) /*!< EPWM_T::INTSTS0: CMPUIF1 Mask */
#define EPWM_INTSTS0_CMPUIF2_Pos (18) /*!< EPWM_T::INTSTS0: CMPUIF2 Position */
#define EPWM_INTSTS0_CMPUIF2_Msk (0x1ul << EPWM_INTSTS0_CMPUIF2_Pos) /*!< EPWM_T::INTSTS0: CMPUIF2 Mask */
#define EPWM_INTSTS0_CMPUIF3_Pos (19) /*!< EPWM_T::INTSTS0: CMPUIF3 Position */
#define EPWM_INTSTS0_CMPUIF3_Msk (0x1ul << EPWM_INTSTS0_CMPUIF3_Pos) /*!< EPWM_T::INTSTS0: CMPUIF3 Mask */
#define EPWM_INTSTS0_CMPUIF4_Pos (20) /*!< EPWM_T::INTSTS0: CMPUIF4 Position */
#define EPWM_INTSTS0_CMPUIF4_Msk (0x1ul << EPWM_INTSTS0_CMPUIF4_Pos) /*!< EPWM_T::INTSTS0: CMPUIF4 Mask */
#define EPWM_INTSTS0_CMPUIF5_Pos (21) /*!< EPWM_T::INTSTS0: CMPUIF5 Position */
#define EPWM_INTSTS0_CMPUIF5_Msk (0x1ul << EPWM_INTSTS0_CMPUIF5_Pos) /*!< EPWM_T::INTSTS0: CMPUIF5 Mask */
#define EPWM_INTSTS0_CMPDIF0_Pos (24) /*!< EPWM_T::INTSTS0: CMPDIF0 Position */
#define EPWM_INTSTS0_CMPDIF0_Msk (0x1ul << EPWM_INTSTS0_CMPDIF0_Pos) /*!< EPWM_T::INTSTS0: CMPDIF0 Mask */
#define EPWM_INTSTS0_CMPDIF1_Pos (25) /*!< EPWM_T::INTSTS0: CMPDIF1 Position */
#define EPWM_INTSTS0_CMPDIF1_Msk (0x1ul << EPWM_INTSTS0_CMPDIF1_Pos) /*!< EPWM_T::INTSTS0: CMPDIF1 Mask */
#define EPWM_INTSTS0_CMPDIF2_Pos (26) /*!< EPWM_T::INTSTS0: CMPDIF2 Position */
#define EPWM_INTSTS0_CMPDIF2_Msk (0x1ul << EPWM_INTSTS0_CMPDIF2_Pos) /*!< EPWM_T::INTSTS0: CMPDIF2 Mask */
#define EPWM_INTSTS0_CMPDIF3_Pos (27) /*!< EPWM_T::INTSTS0: CMPDIF3 Position */
#define EPWM_INTSTS0_CMPDIF3_Msk (0x1ul << EPWM_INTSTS0_CMPDIF3_Pos) /*!< EPWM_T::INTSTS0: CMPDIF3 Mask */
#define EPWM_INTSTS0_CMPDIF4_Pos (28) /*!< EPWM_T::INTSTS0: CMPDIF4 Position */
#define EPWM_INTSTS0_CMPDIF4_Msk (0x1ul << EPWM_INTSTS0_CMPDIF4_Pos) /*!< EPWM_T::INTSTS0: CMPDIF4 Mask */
#define EPWM_INTSTS0_CMPDIF5_Pos (29) /*!< EPWM_T::INTSTS0: CMPDIF5 Position */
#define EPWM_INTSTS0_CMPDIF5_Msk (0x1ul << EPWM_INTSTS0_CMPDIF5_Pos) /*!< EPWM_T::INTSTS0: CMPDIF5 Mask */
#define EPWM_INTSTS1_BRKEIF0_Pos (0) /*!< EPWM_T::INTSTS1: BRKEIF0 Position */
#define EPWM_INTSTS1_BRKEIF0_Msk (0x1ul << EPWM_INTSTS1_BRKEIF0_Pos) /*!< EPWM_T::INTSTS1: BRKEIF0 Mask */
#define EPWM_INTSTS1_BRKEIF1_Pos (1) /*!< EPWM_T::INTSTS1: BRKEIF1 Position */
#define EPWM_INTSTS1_BRKEIF1_Msk (0x1ul << EPWM_INTSTS1_BRKEIF1_Pos) /*!< EPWM_T::INTSTS1: BRKEIF1 Mask */
#define EPWM_INTSTS1_BRKEIF2_Pos (2) /*!< EPWM_T::INTSTS1: BRKEIF2 Position */
#define EPWM_INTSTS1_BRKEIF2_Msk (0x1ul << EPWM_INTSTS1_BRKEIF2_Pos) /*!< EPWM_T::INTSTS1: BRKEIF2 Mask */
#define EPWM_INTSTS1_BRKEIF3_Pos (3) /*!< EPWM_T::INTSTS1: BRKEIF3 Position */
#define EPWM_INTSTS1_BRKEIF3_Msk (0x1ul << EPWM_INTSTS1_BRKEIF3_Pos) /*!< EPWM_T::INTSTS1: BRKEIF3 Mask */
#define EPWM_INTSTS1_BRKEIF4_Pos (4) /*!< EPWM_T::INTSTS1: BRKEIF4 Position */
#define EPWM_INTSTS1_BRKEIF4_Msk (0x1ul << EPWM_INTSTS1_BRKEIF4_Pos) /*!< EPWM_T::INTSTS1: BRKEIF4 Mask */
#define EPWM_INTSTS1_BRKEIF5_Pos (5) /*!< EPWM_T::INTSTS1: BRKEIF5 Position */
#define EPWM_INTSTS1_BRKEIF5_Msk (0x1ul << EPWM_INTSTS1_BRKEIF5_Pos) /*!< EPWM_T::INTSTS1: BRKEIF5 Mask */
#define EPWM_INTSTS1_BRKLIF0_Pos (8) /*!< EPWM_T::INTSTS1: BRKLIF0 Position */
#define EPWM_INTSTS1_BRKLIF0_Msk (0x1ul << EPWM_INTSTS1_BRKLIF0_Pos) /*!< EPWM_T::INTSTS1: BRKLIF0 Mask */
#define EPWM_INTSTS1_BRKLIF1_Pos (9) /*!< EPWM_T::INTSTS1: BRKLIF1 Position */
#define EPWM_INTSTS1_BRKLIF1_Msk (0x1ul << EPWM_INTSTS1_BRKLIF1_Pos) /*!< EPWM_T::INTSTS1: BRKLIF1 Mask */
#define EPWM_INTSTS1_BRKLIF2_Pos (10) /*!< EPWM_T::INTSTS1: BRKLIF2 Position */
#define EPWM_INTSTS1_BRKLIF2_Msk (0x1ul << EPWM_INTSTS1_BRKLIF2_Pos) /*!< EPWM_T::INTSTS1: BRKLIF2 Mask */
#define EPWM_INTSTS1_BRKLIF3_Pos (11) /*!< EPWM_T::INTSTS1: BRKLIF3 Position */
#define EPWM_INTSTS1_BRKLIF3_Msk (0x1ul << EPWM_INTSTS1_BRKLIF3_Pos) /*!< EPWM_T::INTSTS1: BRKLIF3 Mask */
#define EPWM_INTSTS1_BRKLIF4_Pos (12) /*!< EPWM_T::INTSTS1: BRKLIF4 Position */
#define EPWM_INTSTS1_BRKLIF4_Msk (0x1ul << EPWM_INTSTS1_BRKLIF4_Pos) /*!< EPWM_T::INTSTS1: BRKLIF4 Mask */
#define EPWM_INTSTS1_BRKLIF5_Pos (13) /*!< EPWM_T::INTSTS1: BRKLIF5 Position */
#define EPWM_INTSTS1_BRKLIF5_Msk (0x1ul << EPWM_INTSTS1_BRKLIF5_Pos) /*!< EPWM_T::INTSTS1: BRKLIF5 Mask */
#define EPWM_INTSTS1_BRKESTS0_Pos (16) /*!< EPWM_T::INTSTS1: BRKESTS0 Position */
#define EPWM_INTSTS1_BRKESTS0_Msk (0x1ul << EPWM_INTSTS1_BRKESTS0_Pos) /*!< EPWM_T::INTSTS1: BRKESTS0 Mask */
#define EPWM_INTSTS1_BRKESTS1_Pos (17) /*!< EPWM_T::INTSTS1: BRKESTS1 Position */
#define EPWM_INTSTS1_BRKESTS1_Msk (0x1ul << EPWM_INTSTS1_BRKESTS1_Pos) /*!< EPWM_T::INTSTS1: BRKESTS1 Mask */
#define EPWM_INTSTS1_BRKESTS2_Pos (18) /*!< EPWM_T::INTSTS1: BRKESTS2 Position */
#define EPWM_INTSTS1_BRKESTS2_Msk (0x1ul << EPWM_INTSTS1_BRKESTS2_Pos) /*!< EPWM_T::INTSTS1: BRKESTS2 Mask */
#define EPWM_INTSTS1_BRKESTS3_Pos (19) /*!< EPWM_T::INTSTS1: BRKESTS3 Position */
#define EPWM_INTSTS1_BRKESTS3_Msk (0x1ul << EPWM_INTSTS1_BRKESTS3_Pos) /*!< EPWM_T::INTSTS1: BRKESTS3 Mask */
#define EPWM_INTSTS1_BRKESTS4_Pos (20) /*!< EPWM_T::INTSTS1: BRKESTS4 Position */
#define EPWM_INTSTS1_BRKESTS4_Msk (0x1ul << EPWM_INTSTS1_BRKESTS4_Pos) /*!< EPWM_T::INTSTS1: BRKESTS4 Mask */
#define EPWM_INTSTS1_BRKESTS5_Pos (21) /*!< EPWM_T::INTSTS1: BRKESTS5 Position */
#define EPWM_INTSTS1_BRKESTS5_Msk (0x1ul << EPWM_INTSTS1_BRKESTS5_Pos) /*!< EPWM_T::INTSTS1: BRKESTS5 Mask */
#define EPWM_INTSTS1_BRKLSTS0_Pos (24) /*!< EPWM_T::INTSTS1: BRKLSTS0 Position */
#define EPWM_INTSTS1_BRKLSTS0_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS0_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS0 Mask */
#define EPWM_INTSTS1_BRKLSTS1_Pos (25) /*!< EPWM_T::INTSTS1: BRKLSTS1 Position */
#define EPWM_INTSTS1_BRKLSTS1_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS1_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS1 Mask */
#define EPWM_INTSTS1_BRKLSTS2_Pos (26) /*!< EPWM_T::INTSTS1: BRKLSTS2 Position */
#define EPWM_INTSTS1_BRKLSTS2_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS2_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS2 Mask */
#define EPWM_INTSTS1_BRKLSTS3_Pos (27) /*!< EPWM_T::INTSTS1: BRKLSTS3 Position */
#define EPWM_INTSTS1_BRKLSTS3_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS3_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS3 Mask */
#define EPWM_INTSTS1_BRKLSTS4_Pos (28) /*!< EPWM_T::INTSTS1: BRKLSTS4 Position */
#define EPWM_INTSTS1_BRKLSTS4_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS4_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS4 Mask */
#define EPWM_INTSTS1_BRKLSTS5_Pos (29) /*!< EPWM_T::INTSTS1: BRKLSTS5 Position */
#define EPWM_INTSTS1_BRKLSTS5_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS5_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS5 Mask */
#define EPWM_DACTRGEN_ZTE0_Pos (0) /*!< EPWM_T::DACTRGEN: ZTE0 Position */
#define EPWM_DACTRGEN_ZTE0_Msk (0x1ul << EPWM_DACTRGEN_ZTE0_Pos) /*!< EPWM_T::DACTRGEN: ZTE0 Mask */
#define EPWM_DACTRGEN_ZTE1_Pos (1) /*!< EPWM_T::DACTRGEN: ZTE1 Position */
#define EPWM_DACTRGEN_ZTE1_Msk (0x1ul << EPWM_DACTRGEN_ZTE1_Pos) /*!< EPWM_T::DACTRGEN: ZTE1 Mask */
#define EPWM_DACTRGEN_ZTE2_Pos (2) /*!< EPWM_T::DACTRGEN: ZTE2 Position */
#define EPWM_DACTRGEN_ZTE2_Msk (0x1ul << EPWM_DACTRGEN_ZTE2_Pos) /*!< EPWM_T::DACTRGEN: ZTE2 Mask */
#define EPWM_DACTRGEN_ZTE3_Pos (3) /*!< EPWM_T::DACTRGEN: ZTE3 Position */
#define EPWM_DACTRGEN_ZTE3_Msk (0x1ul << EPWM_DACTRGEN_ZTE3_Pos) /*!< EPWM_T::DACTRGEN: ZTE3 Mask */
#define EPWM_DACTRGEN_ZTE4_Pos (4) /*!< EPWM_T::DACTRGEN: ZTE4 Position */
#define EPWM_DACTRGEN_ZTE4_Msk (0x1ul << EPWM_DACTRGEN_ZTE4_Pos) /*!< EPWM_T::DACTRGEN: ZTE4 Mask */
#define EPWM_DACTRGEN_ZTE5_Pos (5) /*!< EPWM_T::DACTRGEN: ZTE5 Position */
#define EPWM_DACTRGEN_ZTE5_Msk (0x1ul << EPWM_DACTRGEN_ZTE5_Pos) /*!< EPWM_T::DACTRGEN: ZTE5 Mask */
#define EPWM_DACTRGEN_PTE0_Pos (8) /*!< EPWM_T::DACTRGEN: PTE0 Position */
#define EPWM_DACTRGEN_PTE0_Msk (0x1ul << EPWM_DACTRGEN_PTE0_Pos) /*!< EPWM_T::DACTRGEN: PTE0 Mask */
#define EPWM_DACTRGEN_PTE1_Pos (9) /*!< EPWM_T::DACTRGEN: PTE1 Position */
#define EPWM_DACTRGEN_PTE1_Msk (0x1ul << EPWM_DACTRGEN_PTE1_Pos) /*!< EPWM_T::DACTRGEN: PTE1 Mask */
#define EPWM_DACTRGEN_PTE2_Pos (10) /*!< EPWM_T::DACTRGEN: PTE2 Position */
#define EPWM_DACTRGEN_PTE2_Msk (0x1ul << EPWM_DACTRGEN_PTE2_Pos) /*!< EPWM_T::DACTRGEN: PTE2 Mask */
#define EPWM_DACTRGEN_PTE3_Pos (11) /*!< EPWM_T::DACTRGEN: PTE3 Position */
#define EPWM_DACTRGEN_PTE3_Msk (0x1ul << EPWM_DACTRGEN_PTE3_Pos) /*!< EPWM_T::DACTRGEN: PTE3 Mask */
#define EPWM_DACTRGEN_PTE4_Pos (12) /*!< EPWM_T::DACTRGEN: PTE4 Position */
#define EPWM_DACTRGEN_PTE4_Msk (0x1ul << EPWM_DACTRGEN_PTE4_Pos) /*!< EPWM_T::DACTRGEN: PTE4 Mask */
#define EPWM_DACTRGEN_PTE5_Pos (13) /*!< EPWM_T::DACTRGEN: PTE5 Position */
#define EPWM_DACTRGEN_PTE5_Msk (0x1ul << EPWM_DACTRGEN_PTE5_Pos) /*!< EPWM_T::DACTRGEN: PTE5 Mask */
#define EPWM_DACTRGEN_CUTRGE0_Pos (16) /*!< EPWM_T::DACTRGEN: CUTRGE0 Position */
#define EPWM_DACTRGEN_CUTRGE0_Msk (0x1ul << EPWM_DACTRGEN_CUTRGE0_Pos) /*!< EPWM_T::DACTRGEN: CUTRGE0 Mask */
#define EPWM_DACTRGEN_CUTRGE1_Pos (17) /*!< EPWM_T::DACTRGEN: CUTRGE1 Position */
#define EPWM_DACTRGEN_CUTRGE1_Msk (0x1ul << EPWM_DACTRGEN_CUTRGE1_Pos) /*!< EPWM_T::DACTRGEN: CUTRGE1 Mask */
#define EPWM_DACTRGEN_CUTRGE2_Pos (18) /*!< EPWM_T::DACTRGEN: CUTRGE2 Position */
#define EPWM_DACTRGEN_CUTRGE2_Msk (0x1ul << EPWM_DACTRGEN_CUTRGE2_Pos) /*!< EPWM_T::DACTRGEN: CUTRGE2 Mask */
#define EPWM_DACTRGEN_CUTRGE3_Pos (19) /*!< EPWM_T::DACTRGEN: CUTRGE3 Position */
#define EPWM_DACTRGEN_CUTRGE3_Msk (0x1ul << EPWM_DACTRGEN_CUTRGE3_Pos) /*!< EPWM_T::DACTRGEN: CUTRGE3 Mask */
#define EPWM_DACTRGEN_CUTRGE4_Pos (20) /*!< EPWM_T::DACTRGEN: CUTRGE4 Position */
#define EPWM_DACTRGEN_CUTRGE4_Msk (0x1ul << EPWM_DACTRGEN_CUTRGE4_Pos) /*!< EPWM_T::DACTRGEN: CUTRGE4 Mask */
#define EPWM_DACTRGEN_CUTRGE5_Pos (21) /*!< EPWM_T::DACTRGEN: CUTRGE5 Position */
#define EPWM_DACTRGEN_CUTRGE5_Msk (0x1ul << EPWM_DACTRGEN_CUTRGE5_Pos) /*!< EPWM_T::DACTRGEN: CUTRGE5 Mask */
#define EPWM_DACTRGEN_CDTRGE0_Pos (24) /*!< EPWM_T::DACTRGEN: CDTRGE0 Position */
#define EPWM_DACTRGEN_CDTRGE0_Msk (0x1ul << EPWM_DACTRGEN_CDTRGE0_Pos) /*!< EPWM_T::DACTRGEN: CDTRGE0 Mask */
#define EPWM_DACTRGEN_CDTRGE1_Pos (25) /*!< EPWM_T::DACTRGEN: CDTRGE1 Position */
#define EPWM_DACTRGEN_CDTRGE1_Msk (0x1ul << EPWM_DACTRGEN_CDTRGE1_Pos) /*!< EPWM_T::DACTRGEN: CDTRGE1 Mask */
#define EPWM_DACTRGEN_CDTRGE2_Pos (26) /*!< EPWM_T::DACTRGEN: CDTRGE2 Position */
#define EPWM_DACTRGEN_CDTRGE2_Msk (0x1ul << EPWM_DACTRGEN_CDTRGE2_Pos) /*!< EPWM_T::DACTRGEN: CDTRGE2 Mask */
#define EPWM_DACTRGEN_CDTRGE3_Pos (27) /*!< EPWM_T::DACTRGEN: CDTRGE3 Position */
#define EPWM_DACTRGEN_CDTRGE3_Msk (0x1ul << EPWM_DACTRGEN_CDTRGE3_Pos) /*!< EPWM_T::DACTRGEN: CDTRGE3 Mask */
#define EPWM_DACTRGEN_CDTRGE4_Pos (28) /*!< EPWM_T::DACTRGEN: CDTRGE4 Position */
#define EPWM_DACTRGEN_CDTRGE4_Msk (0x1ul << EPWM_DACTRGEN_CDTRGE4_Pos) /*!< EPWM_T::DACTRGEN: CDTRGE4 Mask */
#define EPWM_DACTRGEN_CDTRGE5_Pos (29) /*!< EPWM_T::DACTRGEN: CDTRGE5 Position */
#define EPWM_DACTRGEN_CDTRGE5_Msk (0x1ul << EPWM_DACTRGEN_CDTRGE5_Pos) /*!< EPWM_T::DACTRGEN: CDTRGE5 Mask */
#define EPWM_EADCTS0_TRGSEL0_Pos (0) /*!< EPWM_T::EADCTS0: TRGSEL0 Position */
#define EPWM_EADCTS0_TRGSEL0_Msk (0xful << EPWM_EADCTS0_TRGSEL0_Pos) /*!< EPWM_T::EADCTS0: TRGSEL0 Mask */
#define EPWM_EADCTS0_TRGEN0_Pos (7) /*!< EPWM_T::EADCTS0: TRGEN0 Position */
#define EPWM_EADCTS0_TRGEN0_Msk (0x1ul << EPWM_EADCTS0_TRGEN0_Pos) /*!< EPWM_T::EADCTS0: TRGEN0 Mask */
#define EPWM_EADCTS0_TRGSEL1_Pos (8) /*!< EPWM_T::EADCTS0: TRGSEL1 Position */
#define EPWM_EADCTS0_TRGSEL1_Msk (0xful << EPWM_EADCTS0_TRGSEL1_Pos) /*!< EPWM_T::EADCTS0: TRGSEL1 Mask */
#define EPWM_EADCTS0_TRGEN1_Pos (15) /*!< EPWM_T::EADCTS0: TRGEN1 Position */
#define EPWM_EADCTS0_TRGEN1_Msk (0x1ul << EPWM_EADCTS0_TRGEN1_Pos) /*!< EPWM_T::EADCTS0: TRGEN1 Mask */
#define EPWM_EADCTS0_TRGSEL2_Pos (16) /*!< EPWM_T::EADCTS0: TRGSEL2 Position */
#define EPWM_EADCTS0_TRGSEL2_Msk (0xful << EPWM_EADCTS0_TRGSEL2_Pos) /*!< EPWM_T::EADCTS0: TRGSEL2 Mask */
#define EPWM_EADCTS0_TRGEN2_Pos (23) /*!< EPWM_T::EADCTS0: TRGEN2 Position */
#define EPWM_EADCTS0_TRGEN2_Msk (0x1ul << EPWM_EADCTS0_TRGEN2_Pos) /*!< EPWM_T::EADCTS0: TRGEN2 Mask */
#define EPWM_EADCTS0_TRGSEL3_Pos (24) /*!< EPWM_T::EADCTS0: TRGSEL3 Position */
#define EPWM_EADCTS0_TRGSEL3_Msk (0xful << EPWM_EADCTS0_TRGSEL3_Pos) /*!< EPWM_T::EADCTS0: TRGSEL3 Mask */
#define EPWM_EADCTS0_TRGEN3_Pos (31) /*!< EPWM_T::EADCTS0: TRGEN3 Position */
#define EPWM_EADCTS0_TRGEN3_Msk (0x1ul << EPWM_EADCTS0_TRGEN3_Pos) /*!< EPWM_T::EADCTS0: TRGEN3 Mask */
#define EPWM_EADCTS1_TRGSEL4_Pos (0) /*!< EPWM_T::EADCTS1: TRGSEL4 Position */
#define EPWM_EADCTS1_TRGSEL4_Msk (0xful << EPWM_EADCTS1_TRGSEL4_Pos) /*!< EPWM_T::EADCTS1: TRGSEL4 Mask */
#define EPWM_EADCTS1_TRGEN4_Pos (7) /*!< EPWM_T::EADCTS1: TRGEN4 Position */
#define EPWM_EADCTS1_TRGEN4_Msk (0x1ul << EPWM_EADCTS1_TRGEN4_Pos) /*!< EPWM_T::EADCTS1: TRGEN4 Mask */
#define EPWM_EADCTS1_TRGSEL5_Pos (8) /*!< EPWM_T::EADCTS1: TRGSEL5 Position */
#define EPWM_EADCTS1_TRGSEL5_Msk (0xful << EPWM_EADCTS1_TRGSEL5_Pos) /*!< EPWM_T::EADCTS1: TRGSEL5 Mask */
#define EPWM_EADCTS1_TRGEN5_Pos (15) /*!< EPWM_T::EADCTS1: TRGEN5 Position */
#define EPWM_EADCTS1_TRGEN5_Msk (0x1ul << EPWM_EADCTS1_TRGEN5_Pos) /*!< EPWM_T::EADCTS1: TRGEN5 Mask */
#define EPWM_FTCMPDAT0_1_FTCMP_Pos (0) /*!< EPWM_T::FTCMPDAT0_1: FTCMP Position */
#define EPWM_FTCMPDAT0_1_FTCMP_Msk (0xfffful << EPWM_FTCMPDAT0_1_FTCMP_Pos) /*!< EPWM_T::FTCMPDAT0_1: FTCMP Mask */
#define EPWM_FTCMPDAT2_3_FTCMP_Pos (0) /*!< EPWM_T::FTCMPDAT2_3: FTCMP Position */
#define EPWM_FTCMPDAT2_3_FTCMP_Msk (0xfffful << EPWM_FTCMPDAT2_3_FTCMP_Pos) /*!< EPWM_T::FTCMPDAT2_3: FTCMP Mask */
#define EPWM_FTCMPDAT4_5_FTCMP_Pos (0) /*!< EPWM_T::FTCMPDAT4_5: FTCMP Position */
#define EPWM_FTCMPDAT4_5_FTCMP_Msk (0xfffful << EPWM_FTCMPDAT4_5_FTCMP_Pos) /*!< EPWM_T::FTCMPDAT4_5: FTCMP Mask */
#define EPWM_SSCTL_SSEN0_Pos (0) /*!< EPWM_T::SSCTL: SSEN0 Position */
#define EPWM_SSCTL_SSEN0_Msk (0x1ul << EPWM_SSCTL_SSEN0_Pos) /*!< EPWM_T::SSCTL: SSEN0 Mask */
#define EPWM_SSCTL_SSEN1_Pos (1) /*!< EPWM_T::SSCTL: SSEN1 Position */
#define EPWM_SSCTL_SSEN1_Msk (0x1ul << EPWM_SSCTL_SSEN1_Pos) /*!< EPWM_T::SSCTL: SSEN1 Mask */
#define EPWM_SSCTL_SSEN2_Pos (2) /*!< EPWM_T::SSCTL: SSEN2 Position */
#define EPWM_SSCTL_SSEN2_Msk (0x1ul << EPWM_SSCTL_SSEN2_Pos) /*!< EPWM_T::SSCTL: SSEN2 Mask */
#define EPWM_SSCTL_SSEN3_Pos (3) /*!< EPWM_T::SSCTL: SSEN3 Position */
#define EPWM_SSCTL_SSEN3_Msk (0x1ul << EPWM_SSCTL_SSEN3_Pos) /*!< EPWM_T::SSCTL: SSEN3 Mask */
#define EPWM_SSCTL_SSEN4_Pos (4) /*!< EPWM_T::SSCTL: SSEN4 Position */
#define EPWM_SSCTL_SSEN4_Msk (0x1ul << EPWM_SSCTL_SSEN4_Pos) /*!< EPWM_T::SSCTL: SSEN4 Mask */
#define EPWM_SSCTL_SSEN5_Pos (5) /*!< EPWM_T::SSCTL: SSEN5 Position */
#define EPWM_SSCTL_SSEN5_Msk (0x1ul << EPWM_SSCTL_SSEN5_Pos) /*!< EPWM_T::SSCTL: SSEN5 Mask */
#define EPWM_SSCTL_SSRC_Pos (8) /*!< EPWM_T::SSCTL: SSRC Position */
#define EPWM_SSCTL_SSRC_Msk (0x3ul << EPWM_SSCTL_SSRC_Pos) /*!< EPWM_T::SSCTL: SSRC Mask */
#define EPWM_SSTRG_CNTSEN_Pos (0) /*!< EPWM_T::SSTRG: CNTSEN Position */
#define EPWM_SSTRG_CNTSEN_Msk (0x1ul << EPWM_SSTRG_CNTSEN_Pos) /*!< EPWM_T::SSTRG: CNTSEN Mask */
#define EPWM_LEBCTL_LEBEN_Pos (0) /*!< EPWM_T::LEBCTL: LEBEN Position */
#define EPWM_LEBCTL_LEBEN_Msk (0x1ul << EPWM_LEBCTL_LEBEN_Pos) /*!< EPWM_T::LEBCTL: LEBEN Mask */
#define EPWM_LEBCTL_SRCEN0_Pos (8) /*!< EPWM_T::LEBCTL: SRCEN0 Position */
#define EPWM_LEBCTL_SRCEN0_Msk (0x1ul << EPWM_LEBCTL_SRCEN0_Pos) /*!< EPWM_T::LEBCTL: SRCEN0 Mask */
#define EPWM_LEBCTL_SRCEN2_Pos (9) /*!< EPWM_T::LEBCTL: SRCEN2 Position */
#define EPWM_LEBCTL_SRCEN2_Msk (0x1ul << EPWM_LEBCTL_SRCEN2_Pos) /*!< EPWM_T::LEBCTL: SRCEN2 Mask */
#define EPWM_LEBCTL_SRCEN4_Pos (10) /*!< EPWM_T::LEBCTL: SRCEN4 Position */
#define EPWM_LEBCTL_SRCEN4_Msk (0x1ul << EPWM_LEBCTL_SRCEN4_Pos) /*!< EPWM_T::LEBCTL: SRCEN4 Mask */
#define EPWM_LEBCTL_TRGTYPE_Pos (16) /*!< EPWM_T::LEBCTL: TRGTYPE Position */
#define EPWM_LEBCTL_TRGTYPE_Msk (0x3ul << EPWM_LEBCTL_TRGTYPE_Pos) /*!< EPWM_T::LEBCTL: TRGTYPE Mask */
#define EPWM_LEBCNT_LEBCNT_Pos (0) /*!< EPWM_T::LEBCNT: LEBCNT Position */
#define EPWM_LEBCNT_LEBCNT_Msk (0x1fful << EPWM_LEBCNT_LEBCNT_Pos) /*!< EPWM_T::LEBCNT: LEBCNT Mask */
#define EPWM_STATUS_CNTMAXF0_Pos (0) /*!< EPWM_T::STATUS: CNTMAXF0 Position */
#define EPWM_STATUS_CNTMAXF0_Msk (0x1ul << EPWM_STATUS_CNTMAXF0_Pos) /*!< EPWM_T::STATUS: CNTMAXF0 Mask */
#define EPWM_STATUS_CNTMAXF1_Pos (1) /*!< EPWM_T::STATUS: CNTMAXF1 Position */
#define EPWM_STATUS_CNTMAXF1_Msk (0x1ul << EPWM_STATUS_CNTMAXF1_Pos) /*!< EPWM_T::STATUS: CNTMAXF1 Mask */
#define EPWM_STATUS_CNTMAXF2_Pos (2) /*!< EPWM_T::STATUS: CNTMAXF2 Position */
#define EPWM_STATUS_CNTMAXF2_Msk (0x1ul << EPWM_STATUS_CNTMAXF2_Pos) /*!< EPWM_T::STATUS: CNTMAXF2 Mask */
#define EPWM_STATUS_CNTMAXF3_Pos (3) /*!< EPWM_T::STATUS: CNTMAXF3 Position */
#define EPWM_STATUS_CNTMAXF3_Msk (0x1ul << EPWM_STATUS_CNTMAXF3_Pos) /*!< EPWM_T::STATUS: CNTMAXF3 Mask */
#define EPWM_STATUS_CNTMAXF4_Pos (4) /*!< EPWM_T::STATUS: CNTMAXF4 Position */
#define EPWM_STATUS_CNTMAXF4_Msk (0x1ul << EPWM_STATUS_CNTMAXF4_Pos) /*!< EPWM_T::STATUS: CNTMAXF4 Mask */
#define EPWM_STATUS_CNTMAXF5_Pos (5) /*!< EPWM_T::STATUS: CNTMAXF5 Position */
#define EPWM_STATUS_CNTMAXF5_Msk (0x1ul << EPWM_STATUS_CNTMAXF5_Pos) /*!< EPWM_T::STATUS: CNTMAXF5 Mask */
#define EPWM_STATUS_SYNCINF0_Pos (8) /*!< EPWM_T::STATUS: SYNCINF0 Position */
#define EPWM_STATUS_SYNCINF0_Msk (0x1ul << EPWM_STATUS_SYNCINF0_Pos) /*!< EPWM_T::STATUS: SYNCINF0 Mask */
#define EPWM_STATUS_SYNCINF2_Pos (9) /*!< EPWM_T::STATUS: SYNCINF2 Position */
#define EPWM_STATUS_SYNCINF2_Msk (0x1ul << EPWM_STATUS_SYNCINF2_Pos) /*!< EPWM_T::STATUS: SYNCINF2 Mask */
#define EPWM_STATUS_SYNCINF4_Pos (10) /*!< EPWM_T::STATUS: SYNCINF4 Position */
#define EPWM_STATUS_SYNCINF4_Msk (0x1ul << EPWM_STATUS_SYNCINF4_Pos) /*!< EPWM_T::STATUS: SYNCINF4 Mask */
#define EPWM_STATUS_EADCTRGF0_Pos (16) /*!< EPWM_T::STATUS: EADCTRGF0 Position */
#define EPWM_STATUS_EADCTRGF0_Msk (0x1ul << EPWM_STATUS_EADCTRGF0_Pos) /*!< EPWM_T::STATUS: EADCTRGF0 Mask */
#define EPWM_STATUS_EADCTRGF1_Pos (17) /*!< EPWM_T::STATUS: EADCTRGF1 Position */
#define EPWM_STATUS_EADCTRGF1_Msk (0x1ul << EPWM_STATUS_EADCTRGF1_Pos) /*!< EPWM_T::STATUS: EADCTRGF1 Mask */
#define EPWM_STATUS_EADCTRGF2_Pos (18) /*!< EPWM_T::STATUS: EADCTRGF2 Position */
#define EPWM_STATUS_EADCTRGF2_Msk (0x1ul << EPWM_STATUS_EADCTRGF2_Pos) /*!< EPWM_T::STATUS: EADCTRGF2 Mask */
#define EPWM_STATUS_EADCTRGF3_Pos (19) /*!< EPWM_T::STATUS: EADCTRGF3 Position */
#define EPWM_STATUS_EADCTRGF3_Msk (0x1ul << EPWM_STATUS_EADCTRGF3_Pos) /*!< EPWM_T::STATUS: EADCTRGF3 Mask */
#define EPWM_STATUS_EADCTRGF4_Pos (20) /*!< EPWM_T::STATUS: EADCTRGF4 Position */
#define EPWM_STATUS_EADCTRGF4_Msk (0x1ul << EPWM_STATUS_EADCTRGF4_Pos) /*!< EPWM_T::STATUS: EADCTRGF4 Mask */
#define EPWM_STATUS_EADCTRGF5_Pos (21) /*!< EPWM_T::STATUS: EADCTRGF5 Position */
#define EPWM_STATUS_EADCTRGF5_Msk (0x1ul << EPWM_STATUS_EADCTRGF5_Pos) /*!< EPWM_T::STATUS: EADCTRGF5 Mask */
#define EPWM_STATUS_DACTRGF_Pos (24) /*!< EPWM_T::STATUS: DACTRGF Position */
#define EPWM_STATUS_DACTRGF_Msk (0x1ul << EPWM_STATUS_DACTRGF_Pos) /*!< EPWM_T::STATUS: DACTRGF Mask */
#define EPWM_IFA0_IFACNT_Pos (0) /*!< EPWM_T::IFA0: IFACNT Position */
#define EPWM_IFA0_IFACNT_Msk (0xfffful << EPWM_IFA0_IFACNT_Pos) /*!< EPWM_T::IFA0: IFACNT Mask */
#define EPWM_IFA0_IFASEL_Pos (28) /*!< EPWM_T::IFA0: IFASEL Position */
#define EPWM_IFA0_IFASEL_Msk (0x3ul << EPWM_IFA0_IFASEL_Pos) /*!< EPWM_T::IFA0: IFASEL Mask */
#define EPWM_IFA0_IFAEN_Pos (31) /*!< EPWM_T::IFA0: IFAEN Position */
#define EPWM_IFA0_IFAEN_Msk (0x1ul << EPWM_IFA0_IFAEN_Pos) /*!< EPWM_T::IFA0: IFAEN Mask */
#define EPWM_IFA1_IFACNT_Pos (0) /*!< EPWM_T::IFA1: IFACNT Position */
#define EPWM_IFA1_IFACNT_Msk (0xfffful << EPWM_IFA1_IFACNT_Pos) /*!< EPWM_T::IFA1: IFACNT Mask */
#define EPWM_IFA1_IFASEL_Pos (28) /*!< EPWM_T::IFA1: IFASEL Position */
#define EPWM_IFA1_IFASEL_Msk (0x3ul << EPWM_IFA1_IFASEL_Pos) /*!< EPWM_T::IFA1: IFASEL Mask */
#define EPWM_IFA1_IFAEN_Pos (31) /*!< EPWM_T::IFA1: IFAEN Position */
#define EPWM_IFA1_IFAEN_Msk (0x1ul << EPWM_IFA1_IFAEN_Pos) /*!< EPWM_T::IFA1: IFAEN Mask */
#define EPWM_IFA2_IFACNT_Pos (0) /*!< EPWM_T::IFA2: IFACNT Position */
#define EPWM_IFA2_IFACNT_Msk (0xfffful << EPWM_IFA2_IFACNT_Pos) /*!< EPWM_T::IFA2: IFACNT Mask */
#define EPWM_IFA2_IFASEL_Pos (28) /*!< EPWM_T::IFA2: IFASEL Position */
#define EPWM_IFA2_IFASEL_Msk (0x3ul << EPWM_IFA2_IFASEL_Pos) /*!< EPWM_T::IFA2: IFASEL Mask */
#define EPWM_IFA2_IFAEN_Pos (31) /*!< EPWM_T::IFA2: IFAEN Position */
#define EPWM_IFA2_IFAEN_Msk (0x1ul << EPWM_IFA2_IFAEN_Pos) /*!< EPWM_T::IFA2: IFAEN Mask */
#define EPWM_IFA3_IFACNT_Pos (0) /*!< EPWM_T::IFA3: IFACNT Position */
#define EPWM_IFA3_IFACNT_Msk (0xfffful << EPWM_IFA3_IFACNT_Pos) /*!< EPWM_T::IFA3: IFACNT Mask */
#define EPWM_IFA3_IFASEL_Pos (28) /*!< EPWM_T::IFA3: IFASEL Position */
#define EPWM_IFA3_IFASEL_Msk (0x3ul << EPWM_IFA3_IFASEL_Pos) /*!< EPWM_T::IFA3: IFASEL Mask */
#define EPWM_IFA3_IFAEN_Pos (31) /*!< EPWM_T::IFA3: IFAEN Position */
#define EPWM_IFA3_IFAEN_Msk (0x1ul << EPWM_IFA3_IFAEN_Pos) /*!< EPWM_T::IFA3: IFAEN Mask */
#define EPWM_IFA4_IFACNT_Pos (0) /*!< EPWM_T::IFA4: IFACNT Position */
#define EPWM_IFA4_IFACNT_Msk (0xfffful << EPWM_IFA4_IFACNT_Pos) /*!< EPWM_T::IFA4: IFACNT Mask */
#define EPWM_IFA4_IFASEL_Pos (28) /*!< EPWM_T::IFA4: IFASEL Position */
#define EPWM_IFA4_IFASEL_Msk (0x3ul << EPWM_IFA4_IFASEL_Pos) /*!< EPWM_T::IFA4: IFASEL Mask */
#define EPWM_IFA4_IFAEN_Pos (31) /*!< EPWM_T::IFA4: IFAEN Position */
#define EPWM_IFA4_IFAEN_Msk (0x1ul << EPWM_IFA4_IFAEN_Pos) /*!< EPWM_T::IFA4: IFAEN Mask */
#define EPWM_IFA5_IFACNT_Pos (0) /*!< EPWM_T::IFA5: IFACNT Position */
#define EPWM_IFA5_IFACNT_Msk (0xfffful << EPWM_IFA5_IFACNT_Pos) /*!< EPWM_T::IFA5: IFACNT Mask */
#define EPWM_IFA5_IFASEL_Pos (28) /*!< EPWM_T::IFA5: IFASEL Position */
#define EPWM_IFA5_IFASEL_Msk (0x3ul << EPWM_IFA5_IFASEL_Pos) /*!< EPWM_T::IFA5: IFASEL Mask */
#define EPWM_IFA5_IFAEN_Pos (31) /*!< EPWM_T::IFA5: IFAEN Position */
#define EPWM_IFA5_IFAEN_Msk (0x1ul << EPWM_IFA5_IFAEN_Pos) /*!< EPWM_T::IFA5: IFAEN Mask */
#define EPWM_AINTSTS_IFAIF0_Pos (0) /*!< EPWM_T::AINTSTS: IFAIF0 Position */
#define EPWM_AINTSTS_IFAIF0_Msk (0x1ul << EPWM_AINTSTS_IFAIF0_Pos) /*!< EPWM_T::AINTSTS: IFAIF0 Mask */
#define EPWM_AINTSTS_IFAIF1_Pos (1) /*!< EPWM_T::AINTSTS: IFAIF1 Position */
#define EPWM_AINTSTS_IFAIF1_Msk (0x1ul << EPWM_AINTSTS_IFAIF1_Pos) /*!< EPWM_T::AINTSTS: IFAIF1 Mask */
#define EPWM_AINTSTS_IFAIF2_Pos (2) /*!< EPWM_T::AINTSTS: IFAIF2 Position */
#define EPWM_AINTSTS_IFAIF2_Msk (0x1ul << EPWM_AINTSTS_IFAIF2_Pos) /*!< EPWM_T::AINTSTS: IFAIF2 Mask */
#define EPWM_AINTSTS_IFAIF3_Pos (3) /*!< EPWM_T::AINTSTS: IFAIF3 Position */
#define EPWM_AINTSTS_IFAIF3_Msk (0x1ul << EPWM_AINTSTS_IFAIF3_Pos) /*!< EPWM_T::AINTSTS: IFAIF3 Mask */
#define EPWM_AINTSTS_IFAIF4_Pos (4) /*!< EPWM_T::AINTSTS: IFAIF4 Position */
#define EPWM_AINTSTS_IFAIF4_Msk (0x1ul << EPWM_AINTSTS_IFAIF4_Pos) /*!< EPWM_T::AINTSTS: IFAIF4 Mask */
#define EPWM_AINTSTS_IFAIF5_Pos (5) /*!< EPWM_T::AINTSTS: IFAIF5 Position */
#define EPWM_AINTSTS_IFAIF5_Msk (0x1ul << EPWM_AINTSTS_IFAIF5_Pos) /*!< EPWM_T::AINTSTS: IFAIF5 Mask */
#define EPWM_AINTEN_IFAIEN0_Pos (0) /*!< EPWM_T::AINTEN: IFAIEN0 Position */
#define EPWM_AINTEN_IFAIEN0_Msk (0x1ul << EPWM_AINTEN_IFAIEN0_Pos) /*!< EPWM_T::AINTEN: IFAIEN0 Mask */
#define EPWM_AINTEN_IFAIEN1_Pos (1) /*!< EPWM_T::AINTEN: IFAIEN1 Position */
#define EPWM_AINTEN_IFAIEN1_Msk (0x1ul << EPWM_AINTEN_IFAIEN1_Pos) /*!< EPWM_T::AINTEN: IFAIEN1 Mask */
#define EPWM_AINTEN_IFAIEN2_Pos (2) /*!< EPWM_T::AINTEN: IFAIEN2 Position */
#define EPWM_AINTEN_IFAIEN2_Msk (0x1ul << EPWM_AINTEN_IFAIEN2_Pos) /*!< EPWM_T::AINTEN: IFAIEN2 Mask */
#define EPWM_AINTEN_IFAIEN3_Pos (3) /*!< EPWM_T::AINTEN: IFAIEN3 Position */
#define EPWM_AINTEN_IFAIEN3_Msk (0x1ul << EPWM_AINTEN_IFAIEN3_Pos) /*!< EPWM_T::AINTEN: IFAIEN3 Mask */
#define EPWM_AINTEN_IFAIEN4_Pos (4) /*!< EPWM_T::AINTEN: IFAIEN4 Position */
#define EPWM_AINTEN_IFAIEN4_Msk (0x1ul << EPWM_AINTEN_IFAIEN4_Pos) /*!< EPWM_T::AINTEN: IFAIEN4 Mask */
#define EPWM_AINTEN_IFAIEN5_Pos (5) /*!< EPWM_T::AINTEN: IFAIEN5 Position */
#define EPWM_AINTEN_IFAIEN5_Msk (0x1ul << EPWM_AINTEN_IFAIEN5_Pos) /*!< EPWM_T::AINTEN: IFAIEN5 Mask */
#define EPWM_APDMACTL_APDMAEN0_Pos (0) /*!< EPWM_T::APDMACTL: APDMAEN0 Position */
#define EPWM_APDMACTL_APDMAEN0_Msk (0x1ul << EPWM_APDMACTL_APDMAEN0_Pos) /*!< EPWM_T::APDMACTL: APDMAEN0 Mask */
#define EPWM_APDMACTL_APDMAEN1_Pos (1) /*!< EPWM_T::APDMACTL: APDMAEN1 Position */
#define EPWM_APDMACTL_APDMAEN1_Msk (0x1ul << EPWM_APDMACTL_APDMAEN1_Pos) /*!< EPWM_T::APDMACTL: APDMAEN1 Mask */
#define EPWM_APDMACTL_APDMAEN2_Pos (2) /*!< EPWM_T::APDMACTL: APDMAEN2 Position */
#define EPWM_APDMACTL_APDMAEN2_Msk (0x1ul << EPWM_APDMACTL_APDMAEN2_Pos) /*!< EPWM_T::APDMACTL: APDMAEN2 Mask */
#define EPWM_APDMACTL_APDMAEN3_Pos (3) /*!< EPWM_T::APDMACTL: APDMAEN3 Position */
#define EPWM_APDMACTL_APDMAEN3_Msk (0x1ul << EPWM_APDMACTL_APDMAEN3_Pos) /*!< EPWM_T::APDMACTL: APDMAEN3 Mask */
#define EPWM_APDMACTL_APDMAEN4_Pos (4) /*!< EPWM_T::APDMACTL: APDMAEN4 Position */
#define EPWM_APDMACTL_APDMAEN4_Msk (0x1ul << EPWM_APDMACTL_APDMAEN4_Pos) /*!< EPWM_T::APDMACTL: APDMAEN4 Mask */
#define EPWM_APDMACTL_APDMAEN5_Pos (5) /*!< EPWM_T::APDMACTL: APDMAEN5 Position */
#define EPWM_APDMACTL_APDMAEN5_Msk (0x1ul << EPWM_APDMACTL_APDMAEN5_Pos) /*!< EPWM_T::APDMACTL: APDMAEN5 Mask */
#define EPWM_CAPINEN_CAPINEN0_Pos (0) /*!< EPWM_T::CAPINEN: CAPINEN0 Position */
#define EPWM_CAPINEN_CAPINEN0_Msk (0x1ul << EPWM_CAPINEN_CAPINEN0_Pos) /*!< EPWM_T::CAPINEN: CAPINEN0 Mask */
#define EPWM_CAPINEN_CAPINEN1_Pos (1) /*!< EPWM_T::CAPINEN: CAPINEN1 Position */
#define EPWM_CAPINEN_CAPINEN1_Msk (0x1ul << EPWM_CAPINEN_CAPINEN1_Pos) /*!< EPWM_T::CAPINEN: CAPINEN1 Mask */
#define EPWM_CAPINEN_CAPINEN2_Pos (2) /*!< EPWM_T::CAPINEN: CAPINEN2 Position */
#define EPWM_CAPINEN_CAPINEN2_Msk (0x1ul << EPWM_CAPINEN_CAPINEN2_Pos) /*!< EPWM_T::CAPINEN: CAPINEN2 Mask */
#define EPWM_CAPINEN_CAPINEN3_Pos (3) /*!< EPWM_T::CAPINEN: CAPINEN3 Position */
#define EPWM_CAPINEN_CAPINEN3_Msk (0x1ul << EPWM_CAPINEN_CAPINEN3_Pos) /*!< EPWM_T::CAPINEN: CAPINEN3 Mask */
#define EPWM_CAPINEN_CAPINEN4_Pos (4) /*!< EPWM_T::CAPINEN: CAPINEN4 Position */
#define EPWM_CAPINEN_CAPINEN4_Msk (0x1ul << EPWM_CAPINEN_CAPINEN4_Pos) /*!< EPWM_T::CAPINEN: CAPINEN4 Mask */
#define EPWM_CAPINEN_CAPINEN5_Pos (5) /*!< EPWM_T::CAPINEN: CAPINEN5 Position */
#define EPWM_CAPINEN_CAPINEN5_Msk (0x1ul << EPWM_CAPINEN_CAPINEN5_Pos) /*!< EPWM_T::CAPINEN: CAPINEN5 Mask */
#define EPWM_CAPCTL_CAPEN0_Pos (0) /*!< EPWM_T::CAPCTL: CAPEN0 Position */
#define EPWM_CAPCTL_CAPEN0_Msk (0x1ul << EPWM_CAPCTL_CAPEN0_Pos) /*!< EPWM_T::CAPCTL: CAPEN0 Mask */
#define EPWM_CAPCTL_CAPEN1_Pos (1) /*!< EPWM_T::CAPCTL: CAPEN1 Position */
#define EPWM_CAPCTL_CAPEN1_Msk (0x1ul << EPWM_CAPCTL_CAPEN1_Pos) /*!< EPWM_T::CAPCTL: CAPEN1 Mask */
#define EPWM_CAPCTL_CAPEN2_Pos (2) /*!< EPWM_T::CAPCTL: CAPEN2 Position */
#define EPWM_CAPCTL_CAPEN2_Msk (0x1ul << EPWM_CAPCTL_CAPEN2_Pos) /*!< EPWM_T::CAPCTL: CAPEN2 Mask */
#define EPWM_CAPCTL_CAPEN3_Pos (3) /*!< EPWM_T::CAPCTL: CAPEN3 Position */
#define EPWM_CAPCTL_CAPEN3_Msk (0x1ul << EPWM_CAPCTL_CAPEN3_Pos) /*!< EPWM_T::CAPCTL: CAPEN3 Mask */
#define EPWM_CAPCTL_CAPEN4_Pos (4) /*!< EPWM_T::CAPCTL: CAPEN4 Position */
#define EPWM_CAPCTL_CAPEN4_Msk (0x1ul << EPWM_CAPCTL_CAPEN4_Pos) /*!< EPWM_T::CAPCTL: CAPEN4 Mask */
#define EPWM_CAPCTL_CAPEN5_Pos (5) /*!< EPWM_T::CAPCTL: CAPEN5 Position */
#define EPWM_CAPCTL_CAPEN5_Msk (0x1ul << EPWM_CAPCTL_CAPEN5_Pos) /*!< EPWM_T::CAPCTL: CAPEN5 Mask */
#define EPWM_CAPCTL_CAPINV0_Pos (8) /*!< EPWM_T::CAPCTL: CAPINV0 Position */
#define EPWM_CAPCTL_CAPINV0_Msk (0x1ul << EPWM_CAPCTL_CAPINV0_Pos) /*!< EPWM_T::CAPCTL: CAPINV0 Mask */
#define EPWM_CAPCTL_CAPINV1_Pos (9) /*!< EPWM_T::CAPCTL: CAPINV1 Position */
#define EPWM_CAPCTL_CAPINV1_Msk (0x1ul << EPWM_CAPCTL_CAPINV1_Pos) /*!< EPWM_T::CAPCTL: CAPINV1 Mask */
#define EPWM_CAPCTL_CAPINV2_Pos (10) /*!< EPWM_T::CAPCTL: CAPINV2 Position */
#define EPWM_CAPCTL_CAPINV2_Msk (0x1ul << EPWM_CAPCTL_CAPINV2_Pos) /*!< EPWM_T::CAPCTL: CAPINV2 Mask */
#define EPWM_CAPCTL_CAPINV3_Pos (11) /*!< EPWM_T::CAPCTL: CAPINV3 Position */
#define EPWM_CAPCTL_CAPINV3_Msk (0x1ul << EPWM_CAPCTL_CAPINV3_Pos) /*!< EPWM_T::CAPCTL: CAPINV3 Mask */
#define EPWM_CAPCTL_CAPINV4_Pos (12) /*!< EPWM_T::CAPCTL: CAPINV4 Position */
#define EPWM_CAPCTL_CAPINV4_Msk (0x1ul << EPWM_CAPCTL_CAPINV4_Pos) /*!< EPWM_T::CAPCTL: CAPINV4 Mask */
#define EPWM_CAPCTL_CAPINV5_Pos (13) /*!< EPWM_T::CAPCTL: CAPINV5 Position */
#define EPWM_CAPCTL_CAPINV5_Msk (0x1ul << EPWM_CAPCTL_CAPINV5_Pos) /*!< EPWM_T::CAPCTL: CAPINV5 Mask */
#define EPWM_CAPCTL_RCRLDEN0_Pos (16) /*!< EPWM_T::CAPCTL: RCRLDEN0 Position */
#define EPWM_CAPCTL_RCRLDEN0_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN0_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN0 Mask */
#define EPWM_CAPCTL_RCRLDEN1_Pos (17) /*!< EPWM_T::CAPCTL: RCRLDEN1 Position */
#define EPWM_CAPCTL_RCRLDEN1_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN1_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN1 Mask */
#define EPWM_CAPCTL_RCRLDEN2_Pos (18) /*!< EPWM_T::CAPCTL: RCRLDEN2 Position */
#define EPWM_CAPCTL_RCRLDEN2_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN2_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN2 Mask */
#define EPWM_CAPCTL_RCRLDEN3_Pos (19) /*!< EPWM_T::CAPCTL: RCRLDEN3 Position */
#define EPWM_CAPCTL_RCRLDEN3_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN3_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN3 Mask */
#define EPWM_CAPCTL_RCRLDEN4_Pos (20) /*!< EPWM_T::CAPCTL: RCRLDEN4 Position */
#define EPWM_CAPCTL_RCRLDEN4_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN4_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN4 Mask */
#define EPWM_CAPCTL_RCRLDEN5_Pos (21) /*!< EPWM_T::CAPCTL: RCRLDEN5 Position */
#define EPWM_CAPCTL_RCRLDEN5_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN5_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN5 Mask */
#define EPWM_CAPCTL_FCRLDEN0_Pos (24) /*!< EPWM_T::CAPCTL: FCRLDEN0 Position */
#define EPWM_CAPCTL_FCRLDEN0_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN0_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN0 Mask */
#define EPWM_CAPCTL_FCRLDEN1_Pos (25) /*!< EPWM_T::CAPCTL: FCRLDEN1 Position */
#define EPWM_CAPCTL_FCRLDEN1_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN1_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN1 Mask */
#define EPWM_CAPCTL_FCRLDEN2_Pos (26) /*!< EPWM_T::CAPCTL: FCRLDEN2 Position */
#define EPWM_CAPCTL_FCRLDEN2_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN2_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN2 Mask */
#define EPWM_CAPCTL_FCRLDEN3_Pos (27) /*!< EPWM_T::CAPCTL: FCRLDEN3 Position */
#define EPWM_CAPCTL_FCRLDEN3_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN3_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN3 Mask */
#define EPWM_CAPCTL_FCRLDEN4_Pos (28) /*!< EPWM_T::CAPCTL: FCRLDEN4 Position */
#define EPWM_CAPCTL_FCRLDEN4_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN4_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN4 Mask */
#define EPWM_CAPCTL_FCRLDEN5_Pos (29) /*!< EPWM_T::CAPCTL: FCRLDEN5 Position */
#define EPWM_CAPCTL_FCRLDEN5_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN5_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN5 Mask */
#define EPWM_CAPSTS_CRLIFOV0_Pos (0) /*!< EPWM_T::CAPSTS: CRLIFOV0 Position */
#define EPWM_CAPSTS_CRLIFOV0_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV0_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV0 Mask */
#define EPWM_CAPSTS_CRLIFOV1_Pos (1) /*!< EPWM_T::CAPSTS: CRLIFOV1 Position */
#define EPWM_CAPSTS_CRLIFOV1_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV1_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV1 Mask */
#define EPWM_CAPSTS_CRLIFOV2_Pos (2) /*!< EPWM_T::CAPSTS: CRLIFOV2 Position */
#define EPWM_CAPSTS_CRLIFOV2_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV2_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV2 Mask */
#define EPWM_CAPSTS_CRLIFOV3_Pos (3) /*!< EPWM_T::CAPSTS: CRLIFOV3 Position */
#define EPWM_CAPSTS_CRLIFOV3_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV3_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV3 Mask */
#define EPWM_CAPSTS_CRLIFOV4_Pos (4) /*!< EPWM_T::CAPSTS: CRLIFOV4 Position */
#define EPWM_CAPSTS_CRLIFOV4_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV4_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV4 Mask */
#define EPWM_CAPSTS_CRLIFOV5_Pos (5) /*!< EPWM_T::CAPSTS: CRLIFOV5 Position */
#define EPWM_CAPSTS_CRLIFOV5_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV5_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV5 Mask */
#define EPWM_CAPSTS_CFLIFOV0_Pos (8) /*!< EPWM_T::CAPSTS: CFLIFOV0 Position */
#define EPWM_CAPSTS_CFLIFOV0_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV0_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV0 Mask */
#define EPWM_CAPSTS_CFLIFOV1_Pos (9) /*!< EPWM_T::CAPSTS: CFLIFOV1 Position */
#define EPWM_CAPSTS_CFLIFOV1_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV1_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV1 Mask */
#define EPWM_CAPSTS_CFLIFOV2_Pos (10) /*!< EPWM_T::CAPSTS: CFLIFOV2 Position */
#define EPWM_CAPSTS_CFLIFOV2_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV2_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV2 Mask */
#define EPWM_CAPSTS_CFLIFOV3_Pos (11) /*!< EPWM_T::CAPSTS: CFLIFOV3 Position */
#define EPWM_CAPSTS_CFLIFOV3_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV3_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV3 Mask */
#define EPWM_CAPSTS_CFLIFOV4_Pos (12) /*!< EPWM_T::CAPSTS: CFLIFOV4 Position */
#define EPWM_CAPSTS_CFLIFOV4_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV4_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV4 Mask */
#define EPWM_CAPSTS_CFLIFOV5_Pos (13) /*!< EPWM_T::CAPSTS: CFLIFOV5 Position */
#define EPWM_CAPSTS_CFLIFOV5_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV5_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV5 Mask */
#define EPWM_RCAPDAT0_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT0: RCAPDAT Position */
#define EPWM_RCAPDAT0_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT0_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT0: RCAPDAT Mask */
#define EPWM_FCAPDAT0_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT0: FCAPDAT Position */
#define EPWM_FCAPDAT0_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT0_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT0: FCAPDAT Mask */
#define EPWM_RCAPDAT1_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT1: RCAPDAT Position */
#define EPWM_RCAPDAT1_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT1_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT1: RCAPDAT Mask */
#define EPWM_FCAPDAT1_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT1: FCAPDAT Position */
#define EPWM_FCAPDAT1_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT1_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT1: FCAPDAT Mask */
#define EPWM_RCAPDAT2_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT2: RCAPDAT Position */
#define EPWM_RCAPDAT2_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT2_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT2: RCAPDAT Mask */
#define EPWM_FCAPDAT2_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT2: FCAPDAT Position */
#define EPWM_FCAPDAT2_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT2_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT2: FCAPDAT Mask */
#define EPWM_RCAPDAT3_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT3: RCAPDAT Position */
#define EPWM_RCAPDAT3_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT3_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT3: RCAPDAT Mask */
#define EPWM_FCAPDAT3_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT3: FCAPDAT Position */
#define EPWM_FCAPDAT3_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT3_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT3: FCAPDAT Mask */
#define EPWM_RCAPDAT4_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT4: RCAPDAT Position */
#define EPWM_RCAPDAT4_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT4_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT4: RCAPDAT Mask */
#define EPWM_FCAPDAT4_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT4: FCAPDAT Position */
#define EPWM_FCAPDAT4_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT4_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT4: FCAPDAT Mask */
#define EPWM_RCAPDAT5_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT5: RCAPDAT Position */
#define EPWM_RCAPDAT5_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT5_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT5: RCAPDAT Mask */
#define EPWM_FCAPDAT5_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT5: FCAPDAT Position */
#define EPWM_FCAPDAT5_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT5_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT5: FCAPDAT Mask */
#define EPWM_PDMACTL_CHEN0_1_Pos (0) /*!< EPWM_T::PDMACTL: CHEN0_1 Position */
#define EPWM_PDMACTL_CHEN0_1_Msk (0x1ul << EPWM_PDMACTL_CHEN0_1_Pos) /*!< EPWM_T::PDMACTL: CHEN0_1 Mask */
#define EPWM_PDMACTL_CAPMOD0_1_Pos (1) /*!< EPWM_T::PDMACTL: CAPMOD0_1 Position */
#define EPWM_PDMACTL_CAPMOD0_1_Msk (0x3ul << EPWM_PDMACTL_CAPMOD0_1_Pos) /*!< EPWM_T::PDMACTL: CAPMOD0_1 Mask */
#define EPWM_PDMACTL_CAPORD0_1_Pos (3) /*!< EPWM_T::PDMACTL: CAPORD0_1 Position */
#define EPWM_PDMACTL_CAPORD0_1_Msk (0x1ul << EPWM_PDMACTL_CAPORD0_1_Pos) /*!< EPWM_T::PDMACTL: CAPORD0_1 Mask */
#define EPWM_PDMACTL_CHSEL0_1_Pos (4) /*!< EPWM_T::PDMACTL: CHSEL0_1 Position */
#define EPWM_PDMACTL_CHSEL0_1_Msk (0x1ul << EPWM_PDMACTL_CHSEL0_1_Pos) /*!< EPWM_T::PDMACTL: CHSEL0_1 Mask */
#define EPWM_PDMACTL_CHEN2_3_Pos (8) /*!< EPWM_T::PDMACTL: CHEN2_3 Position */
#define EPWM_PDMACTL_CHEN2_3_Msk (0x1ul << EPWM_PDMACTL_CHEN2_3_Pos) /*!< EPWM_T::PDMACTL: CHEN2_3 Mask */
#define EPWM_PDMACTL_CAPMOD2_3_Pos (9) /*!< EPWM_T::PDMACTL: CAPMOD2_3 Position */
#define EPWM_PDMACTL_CAPMOD2_3_Msk (0x3ul << EPWM_PDMACTL_CAPMOD2_3_Pos) /*!< EPWM_T::PDMACTL: CAPMOD2_3 Mask */
#define EPWM_PDMACTL_CAPORD2_3_Pos (11) /*!< EPWM_T::PDMACTL: CAPORD2_3 Position */
#define EPWM_PDMACTL_CAPORD2_3_Msk (0x1ul << EPWM_PDMACTL_CAPORD2_3_Pos) /*!< EPWM_T::PDMACTL: CAPORD2_3 Mask */
#define EPWM_PDMACTL_CHSEL2_3_Pos (12) /*!< EPWM_T::PDMACTL: CHSEL2_3 Position */
#define EPWM_PDMACTL_CHSEL2_3_Msk (0x1ul << EPWM_PDMACTL_CHSEL2_3_Pos) /*!< EPWM_T::PDMACTL: CHSEL2_3 Mask */
#define EPWM_PDMACTL_CHEN4_5_Pos (16) /*!< EPWM_T::PDMACTL: CHEN4_5 Position */
#define EPWM_PDMACTL_CHEN4_5_Msk (0x1ul << EPWM_PDMACTL_CHEN4_5_Pos) /*!< EPWM_T::PDMACTL: CHEN4_5 Mask */
#define EPWM_PDMACTL_CAPMOD4_5_Pos (17) /*!< EPWM_T::PDMACTL: CAPMOD4_5 Position */
#define EPWM_PDMACTL_CAPMOD4_5_Msk (0x3ul << EPWM_PDMACTL_CAPMOD4_5_Pos) /*!< EPWM_T::PDMACTL: CAPMOD4_5 Mask */
#define EPWM_PDMACTL_CAPORD4_5_Pos (19) /*!< EPWM_T::PDMACTL: CAPORD4_5 Position */
#define EPWM_PDMACTL_CAPORD4_5_Msk (0x1ul << EPWM_PDMACTL_CAPORD4_5_Pos) /*!< EPWM_T::PDMACTL: CAPORD4_5 Mask */
#define EPWM_PDMACTL_CHSEL4_5_Pos (20) /*!< EPWM_T::PDMACTL: CHSEL4_5 Position */
#define EPWM_PDMACTL_CHSEL4_5_Msk (0x1ul << EPWM_PDMACTL_CHSEL4_5_Pos) /*!< EPWM_T::PDMACTL: CHSEL4_5 Mask */
#define EPWM_PDMACAP0_1_CAPBUF_Pos (0) /*!< EPWM_T::PDMACAP0_1: CAPBUF Position */
#define EPWM_PDMACAP0_1_CAPBUF_Msk (0xfffful << EPWM_PDMACAP0_1_CAPBUF_Pos) /*!< EPWM_T::PDMACAP0_1: CAPBUF Mask */
#define EPWM_PDMACAP2_3_CAPBUF_Pos (0) /*!< EPWM_T::PDMACAP2_3: CAPBUF Position */
#define EPWM_PDMACAP2_3_CAPBUF_Msk (0xfffful << EPWM_PDMACAP2_3_CAPBUF_Pos) /*!< EPWM_T::PDMACAP2_3: CAPBUF Mask */
#define EPWM_PDMACAP4_5_CAPBUF_Pos (0) /*!< EPWM_T::PDMACAP4_5: CAPBUF Position */
#define EPWM_PDMACAP4_5_CAPBUF_Msk (0xfffful << EPWM_PDMACAP4_5_CAPBUF_Pos) /*!< EPWM_T::PDMACAP4_5: CAPBUF Mask */
#define EPWM_CAPIEN_CAPRIEN0_Pos (0) /*!< EPWM_T::CAPIEN: CAPRIEN0 Position */
#define EPWM_CAPIEN_CAPRIEN0_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN0_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN0 Mask */
#define EPWM_CAPIEN_CAPRIEN1_Pos (1) /*!< EPWM_T::CAPIEN: CAPRIEN1 Position */
#define EPWM_CAPIEN_CAPRIEN1_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN1_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN1 Mask */
#define EPWM_CAPIEN_CAPRIEN2_Pos (2) /*!< EPWM_T::CAPIEN: CAPRIEN2 Position */
#define EPWM_CAPIEN_CAPRIEN2_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN2_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN2 Mask */
#define EPWM_CAPIEN_CAPRIEN3_Pos (3) /*!< EPWM_T::CAPIEN: CAPRIEN3 Position */
#define EPWM_CAPIEN_CAPRIEN3_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN3_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN3 Mask */
#define EPWM_CAPIEN_CAPRIEN4_Pos (4) /*!< EPWM_T::CAPIEN: CAPRIEN4 Position */
#define EPWM_CAPIEN_CAPRIEN4_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN4_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN4 Mask */
#define EPWM_CAPIEN_CAPRIEN5_Pos (5) /*!< EPWM_T::CAPIEN: CAPRIEN5 Position */
#define EPWM_CAPIEN_CAPRIEN5_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN5_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN5 Mask */
#define EPWM_CAPIEN_CAPFIEN0_Pos (8) /*!< EPWM_T::CAPIEN: CAPFIEN0 Position */
#define EPWM_CAPIEN_CAPFIEN0_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN0_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN0 Mask */
#define EPWM_CAPIEN_CAPFIEN1_Pos (9) /*!< EPWM_T::CAPIEN: CAPFIEN1 Position */
#define EPWM_CAPIEN_CAPFIEN1_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN1_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN1 Mask */
#define EPWM_CAPIEN_CAPFIEN2_Pos (10) /*!< EPWM_T::CAPIEN: CAPFIEN2 Position */
#define EPWM_CAPIEN_CAPFIEN2_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN2_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN2 Mask */
#define EPWM_CAPIEN_CAPFIEN3_Pos (11) /*!< EPWM_T::CAPIEN: CAPFIEN3 Position */
#define EPWM_CAPIEN_CAPFIEN3_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN3_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN3 Mask */
#define EPWM_CAPIEN_CAPFIEN4_Pos (12) /*!< EPWM_T::CAPIEN: CAPFIEN4 Position */
#define EPWM_CAPIEN_CAPFIEN4_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN4_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN4 Mask */
#define EPWM_CAPIEN_CAPFIEN5_Pos (13) /*!< EPWM_T::CAPIEN: CAPFIEN5 Position */
#define EPWM_CAPIEN_CAPFIEN5_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN5_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN5 Mask */
#define EPWM_CAPIF_CRLIF0_Pos (0) /*!< EPWM_T::CAPIF: CRLIF0 Position */
#define EPWM_CAPIF_CRLIF0_Msk (0x1ul << EPWM_CAPIF_CRLIF0_Pos) /*!< EPWM_T::CAPIF: CRLIF0 Mask */
#define EPWM_CAPIF_CRLIF1_Pos (1) /*!< EPWM_T::CAPIF: CRLIF1 Position */
#define EPWM_CAPIF_CRLIF1_Msk (0x1ul << EPWM_CAPIF_CRLIF1_Pos) /*!< EPWM_T::CAPIF: CRLIF1 Mask */
#define EPWM_CAPIF_CRLIF2_Pos (2) /*!< EPWM_T::CAPIF: CRLIF2 Position */
#define EPWM_CAPIF_CRLIF2_Msk (0x1ul << EPWM_CAPIF_CRLIF2_Pos) /*!< EPWM_T::CAPIF: CRLIF2 Mask */
#define EPWM_CAPIF_CRLIF3_Pos (3) /*!< EPWM_T::CAPIF: CRLIF3 Position */
#define EPWM_CAPIF_CRLIF3_Msk (0x1ul << EPWM_CAPIF_CRLIF3_Pos) /*!< EPWM_T::CAPIF: CRLIF3 Mask */
#define EPWM_CAPIF_CRLIF4_Pos (4) /*!< EPWM_T::CAPIF: CRLIF4 Position */
#define EPWM_CAPIF_CRLIF4_Msk (0x1ul << EPWM_CAPIF_CRLIF4_Pos) /*!< EPWM_T::CAPIF: CRLIF4 Mask */
#define EPWM_CAPIF_CRLIF5_Pos (5) /*!< EPWM_T::CAPIF: CRLIF5 Position */
#define EPWM_CAPIF_CRLIF5_Msk (0x1ul << EPWM_CAPIF_CRLIF5_Pos) /*!< EPWM_T::CAPIF: CRLIF5 Mask */
#define EPWM_CAPIF_CFLIF0_Pos (8) /*!< EPWM_T::CAPIF: CFLIF0 Position */
#define EPWM_CAPIF_CFLIF0_Msk (0x1ul << EPWM_CAPIF_CFLIF0_Pos) /*!< EPWM_T::CAPIF: CFLIF0 Mask */
#define EPWM_CAPIF_CFLIF1_Pos (9) /*!< EPWM_T::CAPIF: CFLIF1 Position */
#define EPWM_CAPIF_CFLIF1_Msk (0x1ul << EPWM_CAPIF_CFLIF1_Pos) /*!< EPWM_T::CAPIF: CFLIF1 Mask */
#define EPWM_CAPIF_CFLIF2_Pos (10) /*!< EPWM_T::CAPIF: CFLIF2 Position */
#define EPWM_CAPIF_CFLIF2_Msk (0x1ul << EPWM_CAPIF_CFLIF2_Pos) /*!< EPWM_T::CAPIF: CFLIF2 Mask */
#define EPWM_CAPIF_CFLIF3_Pos (11) /*!< EPWM_T::CAPIF: CFLIF3 Position */
#define EPWM_CAPIF_CFLIF3_Msk (0x1ul << EPWM_CAPIF_CFLIF3_Pos) /*!< EPWM_T::CAPIF: CFLIF3 Mask */
#define EPWM_CAPIF_CFLIF4_Pos (12) /*!< EPWM_T::CAPIF: CFLIF4 Position */
#define EPWM_CAPIF_CFLIF4_Msk (0x1ul << EPWM_CAPIF_CFLIF4_Pos) /*!< EPWM_T::CAPIF: CFLIF4 Mask */
#define EPWM_CAPIF_CFLIF5_Pos (13) /*!< EPWM_T::CAPIF: CFLIF5 Position */
#define EPWM_CAPIF_CFLIF5_Msk (0x1ul << EPWM_CAPIF_CFLIF5_Pos) /*!< EPWM_T::CAPIF: CFLIF5 Mask */
#define EPWM_PBUF0_PBUF_Pos (0) /*!< EPWM_T::PBUF0: PBUF Position */
#define EPWM_PBUF0_PBUF_Msk (0xfffful << EPWM_PBUF0_PBUF_Pos) /*!< EPWM_T::PBUF0: PBUF Mask */
#define EPWM_PBUF1_PBUF_Pos (0) /*!< EPWM_T::PBUF1: PBUF Position */
#define EPWM_PBUF1_PBUF_Msk (0xfffful << EPWM_PBUF1_PBUF_Pos) /*!< EPWM_T::PBUF1: PBUF Mask */
#define EPWM_PBUF2_PBUF_Pos (0) /*!< EPWM_T::PBUF2: PBUF Position */
#define EPWM_PBUF2_PBUF_Msk (0xfffful << EPWM_PBUF2_PBUF_Pos) /*!< EPWM_T::PBUF2: PBUF Mask */
#define EPWM_PBUF3_PBUF_Pos (0) /*!< EPWM_T::PBUF3: PBUF Position */
#define EPWM_PBUF3_PBUF_Msk (0xfffful << EPWM_PBUF3_PBUF_Pos) /*!< EPWM_T::PBUF3: PBUF Mask */
#define EPWM_PBUF4_PBUF_Pos (0) /*!< EPWM_T::PBUF4: PBUF Position */
#define EPWM_PBUF4_PBUF_Msk (0xfffful << EPWM_PBUF4_PBUF_Pos) /*!< EPWM_T::PBUF4: PBUF Mask */
#define EPWM_PBUF5_PBUF_Pos (0) /*!< EPWM_T::PBUF5: PBUF Position */
#define EPWM_PBUF5_PBUF_Msk (0xfffful << EPWM_PBUF5_PBUF_Pos) /*!< EPWM_T::PBUF5: PBUF Mask */
#define EPWM_CMPBUF0_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF0: CMPBUF Position */
#define EPWM_CMPBUF0_CMPBUF_Msk (0xfffful << EPWM_CMPBUF0_CMPBUF_Pos) /*!< EPWM_T::CMPBUF0: CMPBUF Mask */
#define EPWM_CMPBUF1_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF1: CMPBUF Position */
#define EPWM_CMPBUF1_CMPBUF_Msk (0xfffful << EPWM_CMPBUF1_CMPBUF_Pos) /*!< EPWM_T::CMPBUF1: CMPBUF Mask */
#define EPWM_CMPBUF2_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF2: CMPBUF Position */
#define EPWM_CMPBUF2_CMPBUF_Msk (0xfffful << EPWM_CMPBUF2_CMPBUF_Pos) /*!< EPWM_T::CMPBUF2: CMPBUF Mask */
#define EPWM_CMPBUF3_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF3: CMPBUF Position */
#define EPWM_CMPBUF3_CMPBUF_Msk (0xfffful << EPWM_CMPBUF3_CMPBUF_Pos) /*!< EPWM_T::CMPBUF3: CMPBUF Mask */
#define EPWM_CMPBUF4_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF4: CMPBUF Position */
#define EPWM_CMPBUF4_CMPBUF_Msk (0xfffful << EPWM_CMPBUF4_CMPBUF_Pos) /*!< EPWM_T::CMPBUF4: CMPBUF Mask */
#define EPWM_CMPBUF5_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF5: CMPBUF Position */
#define EPWM_CMPBUF5_CMPBUF_Msk (0xfffful << EPWM_CMPBUF5_CMPBUF_Pos) /*!< EPWM_T::CMPBUF5: CMPBUF Mask */
#define EPWM_CPSCBUF0_1_CPSCBUF_Pos (0) /*!< EPWM_T::CPSCBUF0_1: CPSCBUF Position */
#define EPWM_CPSCBUF0_1_CPSCBUF_Msk (0xffful << EPWM_CPSCBUF0_1_CPSCBUF_Pos) /*!< EPWM_T::CPSCBUF0_1: CPSCBUF Mask */
#define EPWM_CPSCBUF2_3_CPSCBUF_Pos (0) /*!< EPWM_T::CPSCBUF2_3: CPSCBUF Position */
#define EPWM_CPSCBUF2_3_CPSCBUF_Msk (0xffful << EPWM_CPSCBUF2_3_CPSCBUF_Pos) /*!< EPWM_T::CPSCBUF2_3: CPSCBUF Mask */
#define EPWM_CPSCBUF4_5_CPSCBUF_Pos (0) /*!< EPWM_T::CPSCBUF4_5: CPSCBUF Position */
#define EPWM_CPSCBUF4_5_CPSCBUF_Msk (0xffful << EPWM_CPSCBUF4_5_CPSCBUF_Pos) /*!< EPWM_T::CPSCBUF4_5: CPSCBUF Mask */
#define EPWM_FTCBUF0_1_FTCMPBUF_Pos (0) /*!< EPWM_T::FTCBUF0_1: FTCMPBUF Position */
#define EPWM_FTCBUF0_1_FTCMPBUF_Msk (0xfffful << EPWM_FTCBUF0_1_FTCMPBUF_Pos) /*!< EPWM_T::FTCBUF0_1: FTCMPBUF Mask */
#define EPWM_FTCBUF2_3_FTCMPBUF_Pos (0) /*!< EPWM_T::FTCBUF2_3: FTCMPBUF Position */
#define EPWM_FTCBUF2_3_FTCMPBUF_Msk (0xfffful << EPWM_FTCBUF2_3_FTCMPBUF_Pos) /*!< EPWM_T::FTCBUF2_3: FTCMPBUF Mask */
#define EPWM_FTCBUF4_5_FTCMPBUF_Pos (0) /*!< EPWM_T::FTCBUF4_5: FTCMPBUF Position */
#define EPWM_FTCBUF4_5_FTCMPBUF_Msk (0xfffful << EPWM_FTCBUF4_5_FTCMPBUF_Pos) /*!< EPWM_T::FTCBUF4_5: FTCMPBUF Mask */
#define EPWM_FTCI_FTCMU0_Pos (0) /*!< EPWM_T::FTCI: FTCMU0 Position */
#define EPWM_FTCI_FTCMU0_Msk (0x1ul << EPWM_FTCI_FTCMU0_Pos) /*!< EPWM_T::FTCI: FTCMU0 Mask */
#define EPWM_FTCI_FTCMU2_Pos (1) /*!< EPWM_T::FTCI: FTCMU2 Position */
#define EPWM_FTCI_FTCMU2_Msk (0x1ul << EPWM_FTCI_FTCMU2_Pos) /*!< EPWM_T::FTCI: FTCMU2 Mask */
#define EPWM_FTCI_FTCMU4_Pos (2) /*!< EPWM_T::FTCI: FTCMU4 Position */
#define EPWM_FTCI_FTCMU4_Msk (0x1ul << EPWM_FTCI_FTCMU4_Pos) /*!< EPWM_T::FTCI: FTCMU4 Mask */
#define EPWM_FTCI_FTCMD0_Pos (8) /*!< EPWM_T::FTCI: FTCMD0 Position */
#define EPWM_FTCI_FTCMD0_Msk (0x1ul << EPWM_FTCI_FTCMD0_Pos) /*!< EPWM_T::FTCI: FTCMD0 Mask */
#define EPWM_FTCI_FTCMD2_Pos (9) /*!< EPWM_T::FTCI: FTCMD2 Position */
#define EPWM_FTCI_FTCMD2_Msk (0x1ul << EPWM_FTCI_FTCMD2_Pos) /*!< EPWM_T::FTCI: FTCMD2 Mask */
#define EPWM_FTCI_FTCMD4_Pos (10) /*!< EPWM_T::FTCI: FTCMD4 Position */
#define EPWM_FTCI_FTCMD4_Msk (0x1ul << EPWM_FTCI_FTCMD4_Pos) /*!< EPWM_T::FTCI: FTCMD4 Mask */
/**@}*/ /* EPWM_CONST */
/**@}*/ /* end of EPWM register group */
/*---------------------- Basic Pulse Width Modulation Controller -------------------------*/
/**
@addtogroup BPWM Basic Pulse Width Modulation Controller(BPWM)
Memory Mapped Structure for BPWM Controller
@{ */
typedef struct {
/**
* @var BPWM_T::CTL0
* Offset: 0x00 BPWM Control Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CTRLD0 |Center Re-load
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period
* | | |CMPDAT will load to CMPBUF at the center point of a period
* |[1] |CTRLD1 |Center Re-load
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period
* | | |CMPDAT will load to CMPBUF at the center point of a period
* |[2] |CTRLD2 |Center Re-load
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period
* | | |CMPDAT will load to CMPBUF at the center point of a period
* |[3] |CTRLD3 |Center Re-load
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period
* | | |CMPDAT will load to CMPBUF at the center point of a period
* |[4] |CTRLD4 |Center Re-load
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period
* | | |CMPDAT will load to CMPBUF at the center point of a period
* |[5] |CTRLD5 |Center Re-load
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period
* | | |CMPDAT will load to CMPBUF at the center point of a period
* |[16] |IMMLDEN0 |Immediately Load Enable Bit(S)
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |0 = PERIOD will load to PBUF at the end point of each period
* | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
* | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT.
* | | |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid.
* |[17] |IMMLDEN1 |Immediately Load Enable Bit(S)
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |0 = PERIOD will load to PBUF at the end point of each period
* | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
* | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT.
* | | |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid.
* |[18] |IMMLDEN2 |Immediately Load Enable Bit(S)
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |0 = PERIOD will load to PBUF at the end point of each period
* | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
* | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT.
* | | |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid.
* |[19] |IMMLDEN3 |Immediately Load Enable Bit(S)
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |0 = PERIOD will load to PBUF at the end point of each period
* | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
* | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT.
* | | |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid.
* |[20] |IMMLDEN4 |Immediately Load Enable Bit(S)
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |0 = PERIOD will load to PBUF at the end point of each period
* | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
* | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT.
* | | |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid.
* |[21] |IMMLDEN5 |Immediately Load Enable Bit(S)
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |0 = PERIOD will load to PBUF at the end point of each period
* | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
* | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT.
* | | |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid.
* |[30] |DBGHALT |ICE Debug Mode Counter Halt (Write Protect)
* | | |If counter halt is enabled, BPWM all counters will keep current value until exit ICE debug mode.
* | | |0 = ICE debug mode counter halt Disabled.
* | | |1 = ICE debug mode counter halt Enabled.
* | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
* |[31] |DBGTRIOFF |ICE Debug Mode Acknowledge Disable (Write Protect)
* | | |0 = ICE debug mode acknowledgement effects BPWM output.
* | | |BPWM pin will be forced as tri-state while ICE debug mode acknowledged.
* | | |1 = ICE debug mode acknowledgement Disabled.
* | | |BPWM pin will keep output no matter ICE debug mode acknowledged or not.
* | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
* @var BPWM_T::CTL1
* Offset: 0x04 BPWM Control Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1:0] |CNTTYPE0 |BPWM Counter Behavior Type 0
* | | |Each bit n controls corresponding BPWM channel n.
* | | |00 = Up counter type (supports in capture mode).
* | | |01 = Down count type (supports in capture mode).
* | | |10 = Up-down counter type.
* | | |11 = Reserved.
* @var BPWM_T::CLKSRC
* Offset: 0x10 BPWM Clock Source Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[2:0] |ECLKSRC0 |BPWM_CH01 External Clock Source Select
* | | |000 = BPWMx_CLK, x denotes 0 or 1.
* | | |001 = TIMER0 overflow.
* | | |010 = TIMER1 overflow.
* | | |011 = TIMER2 overflow.
* | | |100 = TIMER3 overflow.
* | | |Others = Reserved.
* @var BPWM_T::CLKPSC
* Offset: 0x14 BPWM Clock Prescale Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[11:0] |CLKPSC |BPWM Counter Clock Prescale
* | | |The clock of BPWM counter is decided by clock prescaler
* | | |Each BPWM pair share one BPWM counter clock prescaler
* | | |The clock of BPWM counter is divided by (CLKPSC+ 1)
* @var BPWM_T::CNTEN
* Offset: 0x20 BPWM Counter Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CNTEN0 |BPWM Counter 0 Enable Bit
* | | |0 = BPWM Counter and clock prescaler stop running.
* | | |1 = BPWM Counter and clock prescaler start running.
* @var BPWM_T::CNTCLR
* Offset: 0x24 BPWM Clear Counter Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CNTCLR0 |Clear BPWM Counter Control Bit 0
* | | |It is automatically cleared by hardware.
* | | |0 = No effect.
* | | |1 = Clear 16-bit BPWM counter to 0000H.
* @var BPWM_T::PERIOD
* Offset: 0x30 BPWM Period Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |PERIOD |BPWM Period Register
* | | |Up-Count mode: In this mode, BPWM counter counts from 0 to PERIOD, and restarts from 0.
* | | |Down-Count mode: In this mode, BPWM counter counts from PERIOD to 0, and restarts from PERIOD.
* | | |BPWM period time = (PERIOD+1) * BPWM_CLK period.
* | | |Up-Down-Count mode: In this mode, BPWM counter counts from 0 to PERIOD, then decrements to 0 and repeats again.
* | | |BPWM period time = 2 * PERIOD * BPWM_CLK period.
* @var BPWM_T::CMPDAT[6]
* Offset: 0x50 BPWM Comparator Register 0~5
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |CMPDAT |BPWM Comparator Register
* | | |CMPDAT use to compare with CNTR to generate BPWM waveform, interrupt and trigger EADC.
* | | |In independent mode, CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point.
* @var BPWM_T::CNT
* Offset: 0x90 BPWM Counter Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |CNT |BPWM Data Register (Read Only)
* | | |User can monitor CNTR to know the current value in 16-bit period counter.
* |[16] |DIRF |BPWM Direction Indicator Flag (Read Only)
* | | |0 = Counter is Down count.
* | | |1 = Counter is UP count.
* @var BPWM_T::WGCTL0
* Offset: 0xB0 BPWM Generation Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1:0] |ZPCTL0 |BPWM Zero Point Control
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |00 = Do nothing.
* | | |01 = BPWM zero point output Low.
* | | |10 = BPWM zero point output High.
* | | |11 = BPWM zero point output Toggle.
* | | |BPWM can control output level when BPWM counter count to zero.
* |[3:2] |ZPCTL1 |BPWM Zero Point Control
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |00 = Do nothing.
* | | |01 = BPWM zero point output Low.
* | | |10 = BPWM zero point output High.
* | | |11 = BPWM zero point output Toggle.
* | | |BPWM can control output level when BPWM counter count to zero.
* |[5:4] |ZPCTL2 |BPWM Zero Point Control
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |00 = Do nothing.
* | | |01 = BPWM zero point output Low.
* | | |10 = BPWM zero point output High.
* | | |11 = BPWM zero point output Toggle.
* | | |BPWM can control output level when BPWM counter count to zero.
* |[7:6] |ZPCTL3 |BPWM Zero Point Control
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |00 = Do nothing.
* | | |01 = BPWM zero point output Low.
* | | |10 = BPWM zero point output High.
* | | |11 = BPWM zero point output Toggle.
* | | |BPWM can control output level when BPWM counter count to zero.
* |[9:8] |ZPCTL4 |BPWM Zero Point Control
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |00 = Do nothing.
* | | |01 = BPWM zero point output Low.
* | | |10 = BPWM zero point output High.
* | | |11 = BPWM zero point output Toggle.
* | | |BPWM can control output level when BPWM counter count to zero.
* |[11:10] |ZPCTL5 |BPWM Zero Point Control
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |00 = Do nothing.
* | | |01 = BPWM zero point output Low.
* | | |10 = BPWM zero point output High.
* | | |11 = BPWM zero point output Toggle.
* | | |BPWM can control output level when BPWM counter count to zero.
* |[17:16] |PRDPCTL0 |BPWM Period (Center) Point Control
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |00 = Do nothing.
* | | |01 = BPWM period (center) point output Low.
* | | |10 = BPWM period (center) point output High.
* | | |11 = BPWM period (center) point output Toggle.
* | | |BPWM can control output level when BPWM counter count to (PERIOD+1).
* | | |Note: This bit is center point control when BPWM counter operating in up-down counter type.
* |[19:18] |PRDPCTL1 |BPWM Period (Center) Point Control
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |00 = Do nothing.
* | | |01 = BPWM period (center) point output Low.
* | | |10 = BPWM period (center) point output High.
* | | |11 = BPWM period (center) point output Toggle.
* | | |BPWM can control output level when BPWM counter count to (PERIOD+1).
* | | |Note: This bit is center point control when BPWM counter operating in up-down counter type.
* |[21:20] |PRDPCTL2 |BPWM Period (Center) Point Control
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |00 = Do nothing.
* | | |01 = BPWM period (center) point output Low.
* | | |10 = BPWM period (center) point output High.
* | | |11 = BPWM period (center) point output Toggle.
* | | |BPWM can control output level when BPWM counter count to (PERIOD+1).
* | | |Note: This bit is center point control when BPWM counter operating in up-down counter type.
* |[23:22] |PRDPCTL3 |BPWM Period (Center) Point Control
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |00 = Do nothing.
* | | |01 = BPWM period (center) point output Low.
* | | |10 = BPWM period (center) point output High.
* | | |11 = BPWM period (center) point output Toggle.
* | | |BPWM can control output level when BPWM counter count to (PERIOD+1).
* | | |Note: This bit is center point control when BPWM counter operating in up-down counter type.
* |[25:24] |PRDPCTL4 |BPWM Period (Center) Point Control
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |00 = Do nothing.
* | | |01 = BPWM period (center) point output Low.
* | | |10 = BPWM period (center) point output High.
* | | |11 = BPWM period (center) point output Toggle.
* | | |BPWM can control output level when BPWM counter count to (PERIOD+1).
* | | |Note: This bit is center point control when BPWM counter operating in up-down counter type.
* |[27:26] |PRDPCTL5 |BPWM Period (Center) Point Control
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |00 = Do nothing.
* | | |01 = BPWM period (center) point output Low.
* | | |10 = BPWM period (center) point output High.
* | | |11 = BPWM period (center) point output Toggle.
* | | |BPWM can control output level when BPWM counter count to (PERIOD+1).
* | | |Note: This bit is center point control when BPWM counter operating in up-down counter type.
* @var BPWM_T::WGCTL1
* Offset: 0xB4 BPWM Generation Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1:0] |CMPUCTL0 |BPWM Compare Up Point Control
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |00 = Do nothing.
* | | |01 = BPWM compare up point output Low.
* | | |10 = BPWM compare up point output High.
* | | |11 = BPWM compare up point output Toggle.
* | | |BPWM can control output level when BPWM counter up count to CMPDAT.
* |[3:2] |CMPUCTL1 |BPWM Compare Up Point Control
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |00 = Do nothing.
* | | |01 = BPWM compare up point output Low.
* | | |10 = BPWM compare up point output High.
* | | |11 = BPWM compare up point output Toggle.
* | | |BPWM can control output level when BPWM counter up count to CMPDAT.
* |[5:4] |CMPUCTL2 |BPWM Compare Up Point Control
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |00 = Do nothing.
* | | |01 = BPWM compare up point output Low.
* | | |10 = BPWM compare up point output High.
* | | |11 = BPWM compare up point output Toggle.
* | | |BPWM can control output level when BPWM counter up count to CMPDAT.
* |[7:6] |CMPUCTL3 |BPWM Compare Up Point Control
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |00 = Do nothing.
* | | |01 = BPWM compare up point output Low.
* | | |10 = BPWM compare up point output High.
* | | |11 = BPWM compare up point output Toggle.
* | | |BPWM can control output level when BPWM counter up count to CMPDAT.
* |[9:8] |CMPUCTL4 |BPWM Compare Up Point Control
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |00 = Do nothing.
* | | |01 = BPWM compare up point output Low.
* | | |10 = BPWM compare up point output High.
* | | |11 = BPWM compare up point output Toggle.
* | | |BPWM can control output level when BPWM counter up count to CMPDAT.
* |[11:10] |CMPUCTL5 |BPWM Compare Up Point Control
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |00 = Do nothing.
* | | |01 = BPWM compare up point output Low.
* | | |10 = BPWM compare up point output High.
* | | |11 = BPWM compare up point output Toggle.
* | | |BPWM can control output level when BPWM counter up count to CMPDAT.
* |[17:16] |CMPDCTL0 |BPWM Compare Down Point Control
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |00 = Do nothing.
* | | |01 = BPWM compare down point output Low.
* | | |10 = BPWM compare down point output High.
* | | |11 = BPWM compare down point output Toggle.
* | | |BPWM can control output level when BPWM counter down count to CMPDAT.
* |[19:18] |CMPDCTL1 |BPWM Compare Down Point Control
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |00 = Do nothing.
* | | |01 = BPWM compare down point output Low.
* | | |10 = BPWM compare down point output High.
* | | |11 = BPWM compare down point output Toggle.
* | | |BPWM can control output level when BPWM counter down count to CMPDAT.
* |[21:20] |CMPDCTL2 |BPWM Compare Down Point Control
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |00 = Do nothing.
* | | |01 = BPWM compare down point output Low.
* | | |10 = BPWM compare down point output High.
* | | |11 = BPWM compare down point output Toggle.
* | | |BPWM can control output level when BPWM counter down count to CMPDAT.
* |[23:22] |CMPDCTL3 |BPWM Compare Down Point Control
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |00 = Do nothing.
* | | |01 = BPWM compare down point output Low.
* | | |10 = BPWM compare down point output High.
* | | |11 = BPWM compare down point output Toggle.
* | | |BPWM can control output level when BPWM counter down count to CMPDAT.
* |[25:24] |CMPDCTL4 |BPWM Compare Down Point Control
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |00 = Do nothing.
* | | |01 = BPWM compare down point output Low.
* | | |10 = BPWM compare down point output High.
* | | |11 = BPWM compare down point output Toggle.
* | | |BPWM can control output level when BPWM counter down count to CMPDAT.
* |[27:26] |CMPDCTL5 |BPWM Compare Down Point Control
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |00 = Do nothing.
* | | |01 = BPWM compare down point output Low.
* | | |10 = BPWM compare down point output High.
* | | |11 = BPWM compare down point output Toggle.
* | | |BPWM can control output level when BPWM counter down count to CMPDAT.
* @var BPWM_T::MSKEN
* Offset: 0xB8 BPWM Mask Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |MSKEN0 |BPWM Mask Enable Bits
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |The BPWM output signal will be masked when this bit is enabled
* | | |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
* | | |0 = BPWM output signal is non-masked.
* | | |1 = BPWM output signal is masked and output MSKDATn data.
* |[1] |MSKEN1 |BPWM Mask Enable Bits
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |The BPWM output signal will be masked when this bit is enabled
* | | |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
* | | |0 = BPWM output signal is non-masked.
* | | |1 = BPWM output signal is masked and output MSKDATn data.
* |[2] |MSKEN2 |BPWM Mask Enable Bits
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |The BPWM output signal will be masked when this bit is enabled
* | | |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
* | | |0 = BPWM output signal is non-masked.
* | | |1 = BPWM output signal is masked and output MSKDATn data.
* |[3] |MSKEN3 |BPWM Mask Enable Bits
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |The BPWM output signal will be masked when this bit is enabled
* | | |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
* | | |0 = BPWM output signal is non-masked.
* | | |1 = BPWM output signal is masked and output MSKDATn data.
* |[4] |MSKEN4 |BPWM Mask Enable Bits
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |The BPWM output signal will be masked when this bit is enabled
* | | |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
* | | |0 = BPWM output signal is non-masked.
* | | |1 = BPWM output signal is masked and output MSKDATn data.
* |[5] |MSKEN5 |BPWM Mask Enable Bits
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |The BPWM output signal will be masked when this bit is enabled
* | | |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
* | | |0 = BPWM output signal is non-masked.
* | | |1 = BPWM output signal is masked and output MSKDATn data.
* @var BPWM_T::MSK
* Offset: 0xBC BPWM Mask Data Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |MSKDAT0 |BPWM Mask Data Bit
* | | |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |0 = Output logic low to BPWMn.
* | | |1 = Output logic high to BPWMn.
* |[1] |MSKDAT1 |BPWM Mask Data Bit
* | | |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |0 = Output logic low to BPWMn.
* | | |1 = Output logic high to BPWMn.
* |[2] |MSKDAT2 |BPWM Mask Data Bit
* | | |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |0 = Output logic low to BPWMn.
* | | |1 = Output logic high to BPWMn.
* |[3] |MSKDAT3 |BPWM Mask Data Bit
* | | |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |0 = Output logic low to BPWMn.
* | | |1 = Output logic high to BPWMn.
* |[4] |MSKDAT4 |BPWM Mask Data Bit
* | | |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |0 = Output logic low to BPWMn.
* | | |1 = Output logic high to BPWMn.
* |[5] |MSKDAT5 |BPWM Mask Data Bit
* | | |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |0 = Output logic low to BPWMn.
* | | |1 = Output logic high to BPWMn.
* @var BPWM_T::POLCTL
* Offset: 0xD4 BPWM Pin Polar Inverse Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |PINV0 |BPWM PIN Polar Inverse Control
* | | |The register controls polarity state of BPWM output
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |0 = BPWM output polar inverse Disabled.
* | | |1 = BPWM output polar inverse Enabled.
* |[1] |PINV1 |BPWM PIN Polar Inverse Control
* | | |The register controls polarity state of BPWM output
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |0 = BPWM output polar inverse Disabled.
* | | |1 = BPWM output polar inverse Enabled.
* |[2] |PINV2 |BPWM PIN Polar Inverse Control
* | | |The register controls polarity state of BPWM output
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |0 = BPWM output polar inverse Disabled.
* | | |1 = BPWM output polar inverse Enabled.
* |[3] |PINV3 |BPWM PIN Polar Inverse Control
* | | |The register controls polarity state of BPWM output
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |0 = BPWM output polar inverse Disabled.
* | | |1 = BPWM output polar inverse Enabled.
* |[4] |PINV4 |BPWM PIN Polar Inverse Control
* | | |The register controls polarity state of BPWM output
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |0 = BPWM output polar inverse Disabled.
* | | |1 = BPWM output polar inverse Enabled.
* |[5] |PINV5 |BPWM PIN Polar Inverse Control
* | | |The register controls polarity state of BPWM output
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |0 = BPWM output polar inverse Disabled.
* | | |1 = BPWM output polar inverse Enabled.
* @var BPWM_T::POEN
* Offset: 0xD8 BPWM Output Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |POEN0 |BPWM Pin Output Enable Bits
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |0 = BPWM pin at tri-state.
* | | |1 = BPWM pin in output mode.
* |[1] |POEN1 |BPWM Pin Output Enable Bits
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |0 = BPWM pin at tri-state.
* | | |1 = BPWM pin in output mode.
* |[2] |POEN2 |BPWM Pin Output Enable Bits
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |0 = BPWM pin at tri-state.
* | | |1 = BPWM pin in output mode.
* |[3] |POEN3 |BPWM Pin Output Enable Bits
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |0 = BPWM pin at tri-state.
* | | |1 = BPWM pin in output mode.
* |[4] |POEN4 |BPWM Pin Output Enable Bits
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |0 = BPWM pin at tri-state.
* | | |1 = BPWM pin in output mode.
* |[5] |POEN5 |BPWM Pin Output Enable Bits
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |0 = BPWM pin at tri-state.
* | | |1 = BPWM pin in output mode.
* @var BPWM_T::INTEN
* Offset: 0xE0 BPWM Interrupt Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ZIEN0 |BPWM Zero Point Interrupt 0 Enable Bit
* | | |0 = Zero point interrupt Disabled.
* | | |1 = Zero point interrupt Enabled.
* |[8] |PIEN0 |BPWM Period Point Interrupt 0 Enable Bit
* | | |0 = Period point interrupt Disabled.
* | | |1 = Period point interrupt Enabled.
* | | |Note: When up-down counter type period point means center point.
* |[16] |CMPUIEN0 |BPWM Compare Up Count Interrupt Enable Bits
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |0 = Compare up count interrupt Disabled.
* | | |1 = Compare up count interrupt Enabled.
* |[17] |CMPUIEN1 |BPWM Compare Up Count Interrupt Enable Bits
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |0 = Compare up count interrupt Disabled.
* | | |1 = Compare up count interrupt Enabled.
* |[18] |CMPUIEN2 |BPWM Compare Up Count Interrupt Enable Bits
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |0 = Compare up count interrupt Disabled.
* | | |1 = Compare up count interrupt Enabled.
* |[19] |CMPUIEN3 |BPWM Compare Up Count Interrupt Enable Bits
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |0 = Compare up count interrupt Disabled.
* | | |1 = Compare up count interrupt Enabled.
* |[20] |CMPUIEN4 |BPWM Compare Up Count Interrupt Enable Bits
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |0 = Compare up count interrupt Disabled.
* | | |1 = Compare up count interrupt Enabled.
* |[21] |CMPUIEN5 |BPWM Compare Up Count Interrupt Enable Bits
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |0 = Compare up count interrupt Disabled.
* | | |1 = Compare up count interrupt Enabled.
* |[24] |CMPDIEN0 |BPWM Compare Down Count Interrupt Enable Bits
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |0 = Compare down count interrupt Disabled.
* | | |1 = Compare down count interrupt Enabled.
* |[25] |CMPDIEN1 |BPWM Compare Down Count Interrupt Enable Bits
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |0 = Compare down count interrupt Disabled.
* | | |1 = Compare down count interrupt Enabled.
* |[26] |CMPDIEN2 |BPWM Compare Down Count Interrupt Enable Bits
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |0 = Compare down count interrupt Disabled.
* | | |1 = Compare down count interrupt Enabled.
* |[27] |CMPDIEN3 |BPWM Compare Down Count Interrupt Enable Bits
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |0 = Compare down count interrupt Disabled.
* | | |1 = Compare down count interrupt Enabled.
* |[28] |CMPDIEN4 |BPWM Compare Down Count Interrupt Enable Bits
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |0 = Compare down count interrupt Disabled.
* | | |1 = Compare down count interrupt Enabled.
* |[29] |CMPDIEN5 |BPWM Compare Down Count Interrupt Enable Bits
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |0 = Compare down count interrupt Disabled.
* | | |1 = Compare down count interrupt Enabled.
* @var BPWM_T::INTSTS
* Offset: 0xE8 BPWM Interrupt Flag Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ZIF0 |BPWM Zero Point Interrupt Flag 0
* | | |This bit is set by hardware when BPWM_CH0 counter reaches zero, software can write 1 to clear this bit to zero.
* |[8] |PIF0 |BPWM Period Point Interrupt Flag 0
* | | |This bit is set by hardware when BPWM_CH0 counter reaches BPWM_PERIOD0, software can write 1 to clear this bit to zero.
* |[16] |CMPUIF0 |BPWM Compare Up Count Interrupt Flag
* | | |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
* |[17] |CMPUIF1 |BPWM Compare Up Count Interrupt Flag
* | | |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
* |[18] |CMPUIF2 |BPWM Compare Up Count Interrupt Flag
* | | |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
* |[19] |CMPUIF3 |BPWM Compare Up Count Interrupt Flag
* | | |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
* |[20] |CMPUIF4 |BPWM Compare Up Count Interrupt Flag
* | | |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
* |[21] |CMPUIF5 |BPWM Compare Up Count Interrupt Flag
* | | |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
* |[24] |CMPDIF0 |BPWM Compare Down Count Interrupt Flag
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.
* | | |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
* |[25] |CMPDIF1 |BPWM Compare Down Count Interrupt Flag
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.
* | | |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
* |[26] |CMPDIF2 |BPWM Compare Down Count Interrupt Flag
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.
* | | |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
* |[27] |CMPDIF3 |BPWM Compare Down Count Interrupt Flag
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.
* | | |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
* |[28] |CMPDIF4 |BPWM Compare Down Count Interrupt Flag
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.
* | | |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
* |[29] |CMPDIF5 |BPWM Compare Down Count Interrupt Flag
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.
* | | |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
* @var BPWM_T::EADCTS0
* Offset: 0xF8 BPWM Trigger EADC Source Select Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |TRGSEL0 |BPWM_CH0 Trigger EADC Source Select
* | | |0000 = BPWM_CH0 zero point.
* | | |0001 = BPWM_CH0 period point.
* | | |0010 = BPWM_CH0 zero or period point.
* | | |0011 = BPWM_CH0 up-count CMPDAT point.
* | | |0100 = BPWM_CH0 down-count CMPDAT point.
* | | |0101 = Reserved.
* | | |0110 = Reserved.
* | | |0111 = Reserved.
* | | |1000 = BPWM_CH1 up-count CMPDAT point.
* | | |1001 = BPWM_CH1 down-count CMPDAT point.
* | | |Others reserved
* |[7] |TRGEN0 |BPWM_CH0 Trigger EADC Enable Bit
* |[11:8] |TRGSEL1 |BPWM_CH1 Trigger EADC Source Select
* | | |0000 = BPWM_CH0 zero point.
* | | |0001 = BPWM_CH0 period point.
* | | |0010 = BPWM_CH0 zero or period point.
* | | |0011 = BPWM_CH0 up-count CMPDAT point.
* | | |0100 = BPWM_CH0 down-count CMPDAT point.
* | | |0101 = Reserved.
* | | |0110 = Reserved.
* | | |0111 = Reserved.
* | | |1000 = BPWM_CH1 up-count CMPDAT point.
* | | |1001 = BPWM_CH1 down-count CMPDAT point.
* | | |Others reserved
* |[15] |TRGEN1 |BPWM_CH1 Trigger EADC Enable Bit
* |[19:16] |TRGSEL2 |BPWM_CH2 Trigger EADC Source Select
* | | |0000 = BPWM_CH2 zero point.
* | | |0001 = BPWM_CH2 period point.
* | | |0010 = BPWM_CH2 zero or period point.
* | | |0011 = BPWM_CH2 up-count CMPDAT point.
* | | |0100 = BPWM_CH2 down-count CMPDAT point.
* | | |0101 = Reserved.
* | | |0110 = Reserved.
* | | |0111 = Reserved.
* | | |1000 = BPWM_CH3 up-count CMPDAT point.
* | | |1001 = BPWM_CH3 down-count CMPDAT point.
* | | |Others reserved
* |[23] |TRGEN2 |BPWM_CH2 Trigger EADC Enable Bit
* |[27:24] |TRGSEL3 |BPWM_CH3 Trigger EADC Source Select
* | | |0000 = BPWM_CH2 zero point.
* | | |0001 = BPWM_CH2 period point.
* | | |0010 = BPWM_CH2 zero or period point.
* | | |0011 = BPWM_CH2 up-count CMPDAT point.
* | | |0100 = BPWM_CH2 down-count CMPDAT point.
* | | |0101 = Reserved.
* | | |0110 = Reserved.
* | | |0111 = Reserved.
* | | |1000 = BPWM_CH3 up-count CMPDAT point.
* | | |1001 = BPWM_CH3 down-count CMPDAT point.
* | | |Others reserved.
* |[31] |TRGEN3 |BPWM_CH3 Trigger EADC Enable Bit
* @var BPWM_T::EADCTS1
* Offset: 0xFC BPWM Trigger EADC Source Select Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |TRGSEL4 |BPWM_CH4 Trigger EADC Source Select
* | | |0000 = BPWM_CH4 zero point.
* | | |0001 = BPWM_CH4 period point.
* | | |0010 = BPWM_CH4 zero or period point.
* | | |0011 = BPWM_CH4 up-count CMPDAT point.
* | | |0100 = BPWM_CH4 down-count CMPDAT point.
* | | |0101 = Reserved.
* | | |0110 = Reserved.
* | | |0111 = Reserved.
* | | |1000 = BPWM_CH5 up-count CMPDAT point.
* | | |1001 = BPWM_CH5 down-count CMPDAT point.
* | | |Others reserved
* |[7] |TRGEN4 |BPWM_CH4 Trigger EADC Enable Bit
* |[11:8] |TRGSEL5 |BPWM_CH5 Trigger EADC Source Select
* | | |0000 = BPWM_CH4 zero point.
* | | |0001 = BPWM_CH4 period point.
* | | |0010 = BPWM_CH4 zero or period point.
* | | |0011 = BPWM_CH4 up-count CMPDAT point.
* | | |0100 = BPWM_CH4 down-count CMPDAT point.
* | | |0101 = Reserved.
* | | |0110 = Reserved.
* | | |0111 = Reserved.
* | | |1000 = BPWM_CH5 up-count CMPDAT point.
* | | |1001 = BPWM_CH5 down-count CMPDAT point.
* | | |Others reserved
* |[15] |TRGEN5 |BPWM_CH5 Trigger EADC Enable Bit
* @var BPWM_T::SSCTL
* Offset: 0x110 BPWM Synchronous Start Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SSEN0 |BPWM Synchronous Start Function 0 Enable Bit
* | | |When synchronous start function is enabled, the BPWM_CH0 counter enable bit (CNTEN0) can be enabled by writing BPWM synchronous start trigger bit (CNTSEN).
* | | |0 = BPWM synchronous start function Disabled.
* | | |1 = BPWM synchronous start function Enabled.
* |[9:8] |SSRC |BPWM Synchronous Start Source Select
* | | |00 = Synchronous start source come from PWM0.
* | | |01 = Synchronous start source come from PWM1.
* | | |10 = Synchronous start source come from BPWM0.
* | | |11 = Synchronous start source come from BPWM1.
* @var BPWM_T::SSTRG
* Offset: 0x114 BPWM Synchronous Start Trigger Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CNTSEN |BPWM Counter Synchronous Start Enable Bit(Write Only)
* | | |BPMW counter synchronous enable function is used to make PWM or BPWM channels start counting at the same time.
* | | |Writing this bit to 1 will also set the counter enable bit if correlated BPWM channel counter synchronous start function is enabled.
* @var BPWM_T::STATUS
* Offset: 0x120 BPWM Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CNTMAX0 |Time-base Counter 0 Equal to 0xFFFF Latched Status
* | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF.
* | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit.
* |[16] |EADCTRG0 |EADC Start of Conversion Status
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |0 = Indicates no EADC start of conversion trigger event has occurred.
* | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.
* |[17] |EADCTRG1 |EADC Start of Conversion Status
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |0 = Indicates no EADC start of conversion trigger event has occurred.
* | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.
* |[18] |EADCTRG2 |EADC Start of Conversion Status
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |0 = Indicates no EADC start of conversion trigger event has occurred.
* | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.
* |[19] |EADCTRG3 |EADC Start of Conversion Status
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |0 = Indicates no EADC start of conversion trigger event has occurred.
* | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.
* |[20] |EADCTRG4 |EADC Start of Conversion Status
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |0 = Indicates no EADC start of conversion trigger event has occurred.
* | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.
* |[21] |EADCTRG5 |EADC Start of Conversion Status
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |0 = Indicates no EADC start of conversion trigger event has occurred.
* | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.
* @var BPWM_T::CAPINEN
* Offset: 0x200 BPWM Capture Input Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CAPINEN0 |Capture Input Enable Bits
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |0 = BPWM Channel capture input path Disabled
* | | |The input of BPWM channel capture function is always regarded as 0.
* | | |1 = BPWM Channel capture input path Enabled
* | | |The input of BPWM channel capture function comes from correlative multifunction pin.
* |[1] |CAPINEN1 |Capture Input Enable Bits
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |0 = BPWM Channel capture input path Disabled
* | | |The input of BPWM channel capture function is always regarded as 0.
* | | |1 = BPWM Channel capture input path Enabled
* | | |The input of BPWM channel capture function comes from correlative multifunction pin.
* |[2] |CAPINEN2 |Capture Input Enable Bits
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |0 = BPWM Channel capture input path Disabled
* | | |The input of BPWM channel capture function is always regarded as 0.
* | | |1 = BPWM Channel capture input path Enabled
* | | |The input of BPWM channel capture function comes from correlative multifunction pin.
* |[3] |CAPINEN3 |Capture Input Enable Bits
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |0 = BPWM Channel capture input path Disabled
* | | |The input of BPWM channel capture function is always regarded as 0.
* | | |1 = BPWM Channel capture input path Enabled
* | | |The input of BPWM channel capture function comes from correlative multifunction pin.
* |[4] |CAPINEN4 |Capture Input Enable Bits
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |0 = BPWM Channel capture input path Disabled
* | | |The input of BPWM channel capture function is always regarded as 0.
* | | |1 = BPWM Channel capture input path Enabled
* | | |The input of BPWM channel capture function comes from correlative multifunction pin.
* |[5] |CAPINEN5 |Capture Input Enable Bits
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |0 = BPWM Channel capture input path Disabled
* | | |The input of BPWM channel capture function is always regarded as 0.
* | | |1 = BPWM Channel capture input path Enabled
* | | |The input of BPWM channel capture function comes from correlative multifunction pin.
* @var BPWM_T::CAPCTL
* Offset: 0x204 BPWM Capture Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CAPEN0 |Capture Function Enable Bits
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.
* | | |1 = Capture function Enabled
* | | |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
* |[1] |CAPEN1 |Capture Function Enable Bits
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.
* | | |1 = Capture function Enabled
* | | |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
* |[2] |CAPEN2 |Capture Function Enable Bits
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.
* | | |1 = Capture function Enabled
* | | |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
* |[3] |CAPEN3 |Capture Function Enable Bits
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.
* | | |1 = Capture function Enabled
* | | |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
* |[4] |CAPEN4 |Capture Function Enable Bits
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.
* | | |1 = Capture function Enabled
* | | |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
* |[5] |CAPEN5 |Capture Function Enable Bits
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.
* | | |1 = Capture function Enabled
* | | |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
* |[8] |CAPINV0 |Capture Inverter Enable Bits
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |0 = Capture source inverter Disabled.
* | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
* |[9] |CAPINV1 |Capture Inverter Enable Bits
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |0 = Capture source inverter Disabled.
* | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
* |[10] |CAPINV2 |Capture Inverter Enable Bits
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |0 = Capture source inverter Disabled.
* | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
* |[11] |CAPINV3 |Capture Inverter Enable Bits
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |0 = Capture source inverter Disabled.
* | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
* |[12] |CAPINV4 |Capture Inverter Enable Bits
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |0 = Capture source inverter Disabled.
* | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
* |[13] |CAPINV5 |Capture Inverter Enable Bits
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |0 = Capture source inverter Disabled.
* | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
* |[16] |RCRLDEN0 |Rising Capture Reload Enable Bits
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |0 = Rising capture reload counter Disabled.
* | | |1 = Rising capture reload counter Enabled.
* |[17] |RCRLDEN1 |Rising Capture Reload Enable Bits
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |0 = Rising capture reload counter Disabled.
* | | |1 = Rising capture reload counter Enabled.
* |[18] |RCRLDEN2 |Rising Capture Reload Enable Bits
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |0 = Rising capture reload counter Disabled.
* | | |1 = Rising capture reload counter Enabled.
* |[19] |RCRLDEN3 |Rising Capture Reload Enable Bits
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |0 = Rising capture reload counter Disabled.
* | | |1 = Rising capture reload counter Enabled.
* |[20] |RCRLDEN4 |Rising Capture Reload Enable Bits
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |0 = Rising capture reload counter Disabled.
* | | |1 = Rising capture reload counter Enabled.
* |[21] |RCRLDEN5 |Rising Capture Reload Enable Bits
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |0 = Rising capture reload counter Disabled.
* | | |1 = Rising capture reload counter Enabled.
* |[24] |FCRLDEN0 |Falling Capture Reload Enable Bits
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |0 = Falling capture reload counter Disabled.
* | | |1 = Falling capture reload counter Enabled.
* |[25] |FCRLDEN1 |Falling Capture Reload Enable Bits
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |0 = Falling capture reload counter Disabled.
* | | |1 = Falling capture reload counter Enabled.
* |[26] |FCRLDEN2 |Falling Capture Reload Enable Bits
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |0 = Falling capture reload counter Disabled.
* | | |1 = Falling capture reload counter Enabled.
* |[27] |FCRLDEN3 |Falling Capture Reload Enable Bits
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |0 = Falling capture reload counter Disabled.
* | | |1 = Falling capture reload counter Enabled.
* |[28] |FCRLDEN4 |Falling Capture Reload Enable Bits
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |0 = Falling capture reload counter Disabled.
* | | |1 = Falling capture reload counter Enabled.
* |[29] |FCRLDEN5 |Falling Capture Reload Enable Bits
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |0 = Falling capture reload counter Disabled.
* | | |1 = Falling capture reload counter Enabled.
* @var BPWM_T::CAPSTS
* Offset: 0x208 BPWM Capture Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CRIFOV0 |Capture Rising Interrupt Flag Overrun Status (Read Only)
* | | |This flag indicates if rising latch happened when the corresponding CAPRIF is 1
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |Note: This bit will be cleared automatically when user clear corresponding CAPRIF.
* |[1] |CRIFOV1 |Capture Rising Interrupt Flag Overrun Status (Read Only)
* | | |This flag indicates if rising latch happened when the corresponding CAPRIF is 1
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |Note: This bit will be cleared automatically when user clear corresponding CAPRIF.
* |[2] |CRIFOV2 |Capture Rising Interrupt Flag Overrun Status (Read Only)
* | | |This flag indicates if rising latch happened when the corresponding CAPRIF is 1
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |Note: This bit will be cleared automatically when user clear corresponding CAPRIF.
* |[3] |CRIFOV3 |Capture Rising Interrupt Flag Overrun Status (Read Only)
* | | |This flag indicates if rising latch happened when the corresponding CAPRIF is 1
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |Note: This bit will be cleared automatically when user clear corresponding CAPRIF.
* |[4] |CRIFOV4 |Capture Rising Interrupt Flag Overrun Status (Read Only)
* | | |This flag indicates if rising latch happened when the corresponding CAPRIF is 1
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |Note: This bit will be cleared automatically when user clear corresponding CAPRIF.
* |[5] |CRIFOV5 |Capture Rising Interrupt Flag Overrun Status (Read Only)
* | | |This flag indicates if rising latch happened when the corresponding CAPRIF is 1
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |Note: This bit will be cleared automatically when user clear corresponding CAPRIF.
* |[8] |CFIFOV0 |Capture Falling Interrupt Flag Overrun Status (Read Only)
* | | |This flag indicates if falling latch happened when the corresponding CAPFIF is 1
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |Note: This bit will be cleared automatically when user clear corresponding CAPFIF.
* |[9] |CFIFOV1 |Capture Falling Interrupt Flag Overrun Status (Read Only)
* | | |This flag indicates if falling latch happened when the corresponding CAPFIF is 1
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |Note: This bit will be cleared automatically when user clear corresponding CAPFIF.
* |[10] |CFIFOV2 |Capture Falling Interrupt Flag Overrun Status (Read Only)
* | | |This flag indicates if falling latch happened when the corresponding CAPFIF is 1
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |Note: This bit will be cleared automatically when user clear corresponding CAPFIF.
* |[11] |CFIFOV3 |Capture Falling Interrupt Flag Overrun Status (Read Only)
* | | |This flag indicates if falling latch happened when the corresponding CAPFIF is 1
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |Note: This bit will be cleared automatically when user clear corresponding CAPFIF.
* |[12] |CFIFOV4 |Capture Falling Interrupt Flag Overrun Status (Read Only)
* | | |This flag indicates if falling latch happened when the corresponding CAPFIF is 1
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |Note: This bit will be cleared automatically when user clear corresponding CAPFIF.
* |[13] |CFIFOV5 |Capture Falling Interrupt Flag Overrun Status (Read Only)
* | | |This flag indicates if falling latch happened when the corresponding CAPFIF is 1
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |Note: This bit will be cleared automatically when user clear corresponding CAPFIF.
* @var BPWM_T::RCAPDAT0
* Offset: 0x20C BPWM Rising Capture Data Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |RCAPDAT |BPWM Rising Capture Data (Read Only)
* | | |When rising capture condition happened, the BPWM counter value will be saved in this register.
* @var BPWM_T::FCAPDAT0
* Offset: 0x210 BPWM Falling Capture Data Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |FCAPDAT |BPWM Falling Capture Data (Read Only)
* | | |When falling capture condition happened, the BPWM counter value will be saved in this register.
* @var BPWM_T::RCAPDAT1
* Offset: 0x214 BPWM Rising Capture Data Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |RCAPDAT |BPWM Rising Capture Data (Read Only)
* | | |When rising capture condition happened, the BPWM counter value will be saved in this register.
* @var BPWM_T::FCAPDAT1
* Offset: 0x218 BPWM Falling Capture Data Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |FCAPDAT |BPWM Falling Capture Data (Read Only)
* | | |When falling capture condition happened, the BPWM counter value will be saved in this register.
* @var BPWM_T::RCAPDAT2
* Offset: 0x21C BPWM Rising Capture Data Register 2
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |RCAPDAT |BPWM Rising Capture Data (Read Only)
* | | |When rising capture condition happened, the BPWM counter value will be saved in this register.
* @var BPWM_T::FCAPDAT2
* Offset: 0x220 BPWM Falling Capture Data Register 2
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |FCAPDAT |BPWM Falling Capture Data (Read Only)
* | | |When falling capture condition happened, the BPWM counter value will be saved in this register.
* @var BPWM_T::RCAPDAT3
* Offset: 0x224 BPWM Rising Capture Data Register 3
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |RCAPDAT |BPWM Rising Capture Data (Read Only)
* | | |When rising capture condition happened, the BPWM counter value will be saved in this register.
* @var BPWM_T::FCAPDAT3
* Offset: 0x228 BPWM Falling Capture Data Register 3
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |FCAPDAT |BPWM Falling Capture Data (Read Only)
* | | |When falling capture condition happened, the BPWM counter value will be saved in this register.
* @var BPWM_T::RCAPDAT4
* Offset: 0x22C BPWM Rising Capture Data Register 4
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |RCAPDAT |BPWM Rising Capture Data (Read Only)
* | | |When rising capture condition happened, the BPWM counter value will be saved in this register.
* @var BPWM_T::FCAPDAT4
* Offset: 0x230 BPWM Falling Capture Data Register 4
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |FCAPDAT |BPWM Falling Capture Data (Read Only)
* | | |When falling capture condition happened, the BPWM counter value will be saved in this register.
* @var BPWM_T::RCAPDAT5
* Offset: 0x234 BPWM Rising Capture Data Register 5
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |RCAPDAT |BPWM Rising Capture Data (Read Only)
* | | |When rising capture condition happened, the BPWM counter value will be saved in this register.
* @var BPWM_T::FCAPDAT5
* Offset: 0x238 BPWM Falling Capture Data Register 5
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |FCAPDAT |BPWM Falling Capture Data (Read Only)
* | | |When falling capture condition happened, the BPWM counter value will be saved in this register.
* @var BPWM_T::CAPIEN
* Offset: 0x250 BPWM Capture Interrupt Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[5:0] |CAPRIENn |BPWM Capture Rising Latch Interrupt Enable Bits
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |0 = Capture rising edge latch interrupt Disabled.
* | | |1 = Capture rising edge latch interrupt Enabled.
* |[13:8] |CAPFIENn |BPWM Capture Falling Latch Interrupt Enable Bits
* | | |Each bit n controls the corresponding BPWM channel n.
* | | |0 = Capture falling edge latch interrupt Disabled.
* | | |1 = Capture falling edge latch interrupt Enabled.
* @var BPWM_T::CAPIF
* Offset: 0x254 BPWM Capture Interrupt Flag Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CAPRIF0 |BPWM Capture Rising Latch Interrupt Flag
* | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.
* | | |0 = No capture rising latch condition happened.
* | | |1 = Capture rising latch condition happened, this flag will be set to high.
* |[1] |CAPRIF1 |BPWM Capture Rising Latch Interrupt Flag
* | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.
* | | |0 = No capture rising latch condition happened.
* | | |1 = Capture rising latch condition happened, this flag will be set to high.
* |[2] |CAPRIF2 |BPWM Capture Rising Latch Interrupt Flag
* | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.
* | | |0 = No capture rising latch condition happened.
* | | |1 = Capture rising latch condition happened, this flag will be set to high.
* |[3] |CAPRIF3 |BPWM Capture Rising Latch Interrupt Flag
* | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.
* | | |0 = No capture rising latch condition happened.
* | | |1 = Capture rising latch condition happened, this flag will be set to high.
* |[4] |CAPRIF4 |BPWM Capture Rising Latch Interrupt Flag
* | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.
* | | |0 = No capture rising latch condition happened.
* | | |1 = Capture rising latch condition happened, this flag will be set to high.
* |[5] |CAPRIF5 |BPWM Capture Rising Latch Interrupt Flag
* | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.
* | | |0 = No capture rising latch condition happened.
* | | |1 = Capture rising latch condition happened, this flag will be set to high.
* |[8] |CAPFIF0 |BPWM Capture Falling Latch Interrupt Flag
* | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.
* | | |0 = No capture falling latch condition happened.
* | | |1 = Capture falling latch condition happened, this flag will be set to high.
* |[9] |CAPFIF1 |BPWM Capture Falling Latch Interrupt Flag
* | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.
* | | |0 = No capture falling latch condition happened.
* | | |1 = Capture falling latch condition happened, this flag will be set to high.
* |[10] |CAPFIF2 |BPWM Capture Falling Latch Interrupt Flag
* | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.
* | | |0 = No capture falling latch condition happened.
* | | |1 = Capture falling latch condition happened, this flag will be set to high.
* |[11] |CAPFIF3 |BPWM Capture Falling Latch Interrupt Flag
* | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.
* | | |0 = No capture falling latch condition happened.
* | | |1 = Capture falling latch condition happened, this flag will be set to high.
* |[12] |CAPFIF4 |BPWM Capture Falling Latch Interrupt Flag
* | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.
* | | |0 = No capture falling latch condition happened.
* | | |1 = Capture falling latch condition happened, this flag will be set to high.
* |[13] |CAPFIF5 |BPWM Capture Falling Latch Interrupt Flag
* | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.
* | | |0 = No capture falling latch condition happened.
* | | |1 = Capture falling latch condition happened, this flag will be set to high.
* @var BPWM_T::PBUF
* Offset: 0x304 BPWM PERIOD Buffer
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |PBUF |BPWM Period Buffer (Read Only)
* | | |Used as PERIOD active register.
* @var BPWM_T::CMPBUF[6]
* Offset: 0x31C BPWM CMPDAT 0~5 Buffer
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |CMPBUF |BPWM Comparator Buffer (Read Only)
* | | |Used as CMP active register.
*/
__IO uint32_t CTL0; /*!< [0x0000] BPWM Control Register 0 */
__IO uint32_t CTL1; /*!< [0x0004] BPWM Control Register 1 */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE0[2];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t CLKSRC; /*!< [0x0010] BPWM Clock Source Register */
__IO uint32_t CLKPSC; /*!< [0x0014] BPWM Clock Prescale Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE1[2];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t CNTEN; /*!< [0x0020] BPWM Counter Enable Register */
__IO uint32_t CNTCLR; /*!< [0x0024] BPWM Clear Counter Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE2[2];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t PERIOD; /*!< [0x0030] BPWM Period Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE3[7];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t CMPDAT[6]; /*!< [0x0050] BPWM Comparator Register 0~5 */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE4[10];
/// @endcond //HIDDEN_SYMBOLS
__I uint32_t CNT; /*!< [0x0090] BPWM Counter Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE5[7];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t WGCTL0; /*!< [0x00b0] BPWM Generation Register 0 */
__IO uint32_t WGCTL1; /*!< [0x00b4] BPWM Generation Register 1 */
__IO uint32_t MSKEN; /*!< [0x00b8] BPWM Mask Enable Register */
__IO uint32_t MSK; /*!< [0x00bc] BPWM Mask Data Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE6[5];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t POLCTL; /*!< [0x00d4] BPWM Pin Polar Inverse Register */
__IO uint32_t POEN; /*!< [0x00d8] BPWM Output Enable Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE7[1];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t INTEN; /*!< [0x00e0] BPWM Interrupt Enable Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE8[1];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t INTSTS; /*!< [0x00e8] BPWM Interrupt Flag Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE9[3];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t EADCTS0; /*!< [0x00f8] BPWM Trigger EADC Source Select Register 0 */
__IO uint32_t EADCTS1; /*!< [0x00fc] BPWM Trigger EADC Source Select Register 1 */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE10[4];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t SSCTL; /*!< [0x0110] BPWM Synchronous Start Control Register */
__O uint32_t SSTRG; /*!< [0x0114] BPWM Synchronous Start Trigger Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE11[2];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t STATUS; /*!< [0x0120] BPWM Status Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE12[55];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t CAPINEN; /*!< [0x0200] BPWM Capture Input Enable Register */
__IO uint32_t CAPCTL; /*!< [0x0204] BPWM Capture Control Register */
__I uint32_t CAPSTS; /*!< [0x0208] BPWM Capture Status Register */
__I uint32_t RCAPDAT0; /*!< [0x020c] BPWM Rising Capture Data Register 0 */
__I uint32_t FCAPDAT0; /*!< [0x0210] BPWM Falling Capture Data Register 0 */
__I uint32_t RCAPDAT1; /*!< [0x0214] BPWM Rising Capture Data Register 1 */
__I uint32_t FCAPDAT1; /*!< [0x0218] BPWM Falling Capture Data Register 1 */
__I uint32_t RCAPDAT2; /*!< [0x021c] BPWM Rising Capture Data Register 2 */
__I uint32_t FCAPDAT2; /*!< [0x0220] BPWM Falling Capture Data Register 2 */
__I uint32_t RCAPDAT3; /*!< [0x0224] BPWM Rising Capture Data Register 3 */
__I uint32_t FCAPDAT3; /*!< [0x0228] BPWM Falling Capture Data Register 3 */
__I uint32_t RCAPDAT4; /*!< [0x022c] BPWM Rising Capture Data Register 4 */
__I uint32_t FCAPDAT4; /*!< [0x0230] BPWM Falling Capture Data Register 4 */
__I uint32_t RCAPDAT5; /*!< [0x0234] BPWM Rising Capture Data Register 5 */
__I uint32_t FCAPDAT5; /*!< [0x0238] BPWM Falling Capture Data Register 5 */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE13[5];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t CAPIEN; /*!< [0x0250] BPWM Capture Interrupt Enable Register */
__IO uint32_t CAPIF; /*!< [0x0254] BPWM Capture Interrupt Flag Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE14[43];
/// @endcond //HIDDEN_SYMBOLS
__I uint32_t PBUF; /*!< [0x0304] BPWM PERIOD Buffer */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE15[5];
/// @endcond //HIDDEN_SYMBOLS
__I uint32_t CMPBUF[6]; /*!< [0x031c] BPWM CMPDAT 0~5 Buffer */
} BPWM_T;
/**
@addtogroup BPWM_CONST BPWM Bit Field Definition
Constant Definitions for BPWM Controller
@{ */
#define BPWM_CTL0_CTRLD0_Pos (0) /*!< BPWM_T::CTL0: CTRLD0 Position */
#define BPWM_CTL0_CTRLD0_Msk (0x1ul << BPWM_CTL0_CTRLD0_Pos) /*!< BPWM_T::CTL0: CTRLD0 Mask */
#define BPWM_CTL0_CTRLD1_Pos (1) /*!< BPWM_T::CTL0: CTRLD1 Position */
#define BPWM_CTL0_CTRLD1_Msk (0x1ul << BPWM_CTL0_CTRLD1_Pos) /*!< BPWM_T::CTL0: CTRLD1 Mask */
#define BPWM_CTL0_CTRLD2_Pos (2) /*!< BPWM_T::CTL0: CTRLD2 Position */
#define BPWM_CTL0_CTRLD2_Msk (0x1ul << BPWM_CTL0_CTRLD2_Pos) /*!< BPWM_T::CTL0: CTRLD2 Mask */
#define BPWM_CTL0_CTRLD3_Pos (3) /*!< BPWM_T::CTL0: CTRLD3 Position */
#define BPWM_CTL0_CTRLD3_Msk (0x1ul << BPWM_CTL0_CTRLD3_Pos) /*!< BPWM_T::CTL0: CTRLD3 Mask */
#define BPWM_CTL0_CTRLD4_Pos (4) /*!< BPWM_T::CTL0: CTRLD4 Position */
#define BPWM_CTL0_CTRLD4_Msk (0x1ul << BPWM_CTL0_CTRLD4_Pos) /*!< BPWM_T::CTL0: CTRLD4 Mask */
#define BPWM_CTL0_CTRLD5_Pos (5) /*!< BPWM_T::CTL0: CTRLD5 Position */
#define BPWM_CTL0_CTRLD5_Msk (0x1ul << BPWM_CTL0_CTRLD5_Pos) /*!< BPWM_T::CTL0: CTRLD5 Mask */
#define BPWM_CTL0_IMMLDEN0_Pos (16) /*!< BPWM_T::CTL0: IMMLDEN0 Position */
#define BPWM_CTL0_IMMLDEN0_Msk (0x1ul << BPWM_CTL0_IMMLDEN0_Pos) /*!< BPWM_T::CTL0: IMMLDEN0 Mask */
#define BPWM_CTL0_IMMLDEN1_Pos (17) /*!< BPWM_T::CTL0: IMMLDEN1 Position */
#define BPWM_CTL0_IMMLDEN1_Msk (0x1ul << BPWM_CTL0_IMMLDEN1_Pos) /*!< BPWM_T::CTL0: IMMLDEN1 Mask */
#define BPWM_CTL0_IMMLDEN2_Pos (18) /*!< BPWM_T::CTL0: IMMLDEN2 Position */
#define BPWM_CTL0_IMMLDEN2_Msk (0x1ul << BPWM_CTL0_IMMLDEN2_Pos) /*!< BPWM_T::CTL0: IMMLDEN2 Mask */
#define BPWM_CTL0_IMMLDEN3_Pos (19) /*!< BPWM_T::CTL0: IMMLDEN3 Position */
#define BPWM_CTL0_IMMLDEN3_Msk (0x1ul << BPWM_CTL0_IMMLDEN3_Pos) /*!< BPWM_T::CTL0: IMMLDEN3 Mask */
#define BPWM_CTL0_IMMLDEN4_Pos (20) /*!< BPWM_T::CTL0: IMMLDEN4 Position */
#define BPWM_CTL0_IMMLDEN4_Msk (0x1ul << BPWM_CTL0_IMMLDEN4_Pos) /*!< BPWM_T::CTL0: IMMLDEN4 Mask */
#define BPWM_CTL0_IMMLDEN5_Pos (21) /*!< BPWM_T::CTL0: IMMLDEN5 Position */
#define BPWM_CTL0_IMMLDEN5_Msk (0x1ul << BPWM_CTL0_IMMLDEN5_Pos) /*!< BPWM_T::CTL0: IMMLDEN5 Mask */
#define BPWM_CTL0_DBGHALT_Pos (30) /*!< BPWM_T::CTL0: DBGHALT Position */
#define BPWM_CTL0_DBGHALT_Msk (0x1ul << BPWM_CTL0_DBGHALT_Pos) /*!< BPWM_T::CTL0: DBGHALT Mask */
#define BPWM_CTL0_DBGTRIOFF_Pos (31) /*!< BPWM_T::CTL0: DBGTRIOFF Position */
#define BPWM_CTL0_DBGTRIOFF_Msk (0x1ul << BPWM_CTL0_DBGTRIOFF_Pos) /*!< BPWM_T::CTL0: DBGTRIOFF Mask */
#define BPWM_CTL1_CNTTYPE0_Pos (0) /*!< BPWM_T::CTL1: CNTTYPE0 Position */
#define BPWM_CTL1_CNTTYPE0_Msk (0x3ul << BPWM_CTL1_CNTTYPE0_Pos) /*!< BPWM_T::CTL1: CNTTYPE0 Mask */
#define BPWM_CLKSRC_ECLKSRC0_Pos (0) /*!< BPWM_T::CLKSRC: ECLKSRC0 Position */
#define BPWM_CLKSRC_ECLKSRC0_Msk (0x7ul << BPWM_CLKSRC_ECLKSRC0_Pos) /*!< BPWM_T::CLKSRC: ECLKSRC0 Mask */
#define BPWM_CLKPSC_CLKPSC_Pos (0) /*!< BPWM_T::CLKPSC: CLKPSC Position */
#define BPWM_CLKPSC_CLKPSC_Msk (0xffful << BPWM_CLKPSC_CLKPSC_Pos) /*!< BPWM_T::CLKPSC: CLKPSC Mask */
#define BPWM_CNTEN_CNTEN0_Pos (0) /*!< BPWM_T::CNTEN: CNTEN0 Position */
#define BPWM_CNTEN_CNTEN0_Msk (0x1ul << BPWM_CNTEN_CNTEN0_Pos) /*!< BPWM_T::CNTEN: CNTEN0 Mask */
#define BPWM_CNTCLR_CNTCLR0_Pos (0) /*!< BPWM_T::CNTCLR: CNTCLR0 Position */
#define BPWM_CNTCLR_CNTCLR0_Msk (0x1ul << BPWM_CNTCLR_CNTCLR0_Pos) /*!< BPWM_T::CNTCLR: CNTCLR0 Mask */
#define BPWM_PERIOD_PERIOD_Pos (0) /*!< BPWM_T::PERIOD: PERIOD Position */
#define BPWM_PERIOD_PERIOD_Msk (0xfffful << BPWM_PERIOD_PERIOD_Pos) /*!< BPWM_T::PERIOD: PERIOD Mask */
#define BPWM_CMPDAT0_CMPDAT_Pos (0) /*!< BPWM_T::CMPDAT0: CMPDAT Position */
#define BPWM_CMPDAT0_CMPDAT_Msk (0xfffful << BPWM_CMPDAT0_CMPDAT_Pos) /*!< BPWM_T::CMPDAT0: CMPDAT Mask */
#define BPWM_CMPDAT1_CMPDAT_Pos (0) /*!< BPWM_T::CMPDAT1: CMPDAT Position */
#define BPWM_CMPDAT1_CMPDAT_Msk (0xfffful << BPWM_CMPDAT1_CMPDAT_Pos) /*!< BPWM_T::CMPDAT1: CMPDAT Mask */
#define BPWM_CMPDAT2_CMPDAT_Pos (0) /*!< BPWM_T::CMPDAT2: CMPDAT Position */
#define BPWM_CMPDAT2_CMPDAT_Msk (0xfffful << BPWM_CMPDAT2_CMPDAT_Pos) /*!< BPWM_T::CMPDAT2: CMPDAT Mask */
#define BPWM_CMPDAT3_CMPDAT_Pos (0) /*!< BPWM_T::CMPDAT3: CMPDAT Position */
#define BPWM_CMPDAT3_CMPDAT_Msk (0xfffful << BPWM_CMPDAT3_CMPDAT_Pos) /*!< BPWM_T::CMPDAT3: CMPDAT Mask */
#define BPWM_CMPDAT4_CMPDAT_Pos (0) /*!< BPWM_T::CMPDAT4: CMPDAT Position */
#define BPWM_CMPDAT4_CMPDAT_Msk (0xfffful << BPWM_CMPDAT4_CMPDAT_Pos) /*!< BPWM_T::CMPDAT4: CMPDAT Mask */
#define BPWM_CMPDAT5_CMPDAT_Pos (0) /*!< BPWM_T::CMPDAT5: CMPDAT Position */
#define BPWM_CMPDAT5_CMPDAT_Msk (0xfffful << BPWM_CMPDAT5_CMPDAT_Pos) /*!< BPWM_T::CMPDAT5: CMPDAT Mask */
#define BPWM_CNT_CNT_Pos (0) /*!< BPWM_T::CNT: CNT Position */
#define BPWM_CNT_CNT_Msk (0xfffful << BPWM_CNT_CNT_Pos) /*!< BPWM_T::CNT: CNT Mask */
#define BPWM_CNT_DIRF_Pos (16) /*!< BPWM_T::CNT: DIRF Position */
#define BPWM_CNT_DIRF_Msk (0x1ul << BPWM_CNT_DIRF_Pos) /*!< BPWM_T::CNT: DIRF Mask */
#define BPWM_WGCTL0_ZPCTL0_Pos (0) /*!< BPWM_T::WGCTL0: ZPCTL0 Position */
#define BPWM_WGCTL0_ZPCTL0_Msk (0x3ul << BPWM_WGCTL0_ZPCTL0_Pos) /*!< BPWM_T::WGCTL0: ZPCTL0 Mask */
#define BPWM_WGCTL0_ZPCTL1_Pos (2) /*!< BPWM_T::WGCTL0: ZPCTL1 Position */
#define BPWM_WGCTL0_ZPCTL1_Msk (0x3ul << BPWM_WGCTL0_ZPCTL1_Pos) /*!< BPWM_T::WGCTL0: ZPCTL1 Mask */
#define BPWM_WGCTL0_ZPCTL2_Pos (4) /*!< BPWM_T::WGCTL0: ZPCTL2 Position */
#define BPWM_WGCTL0_ZPCTL2_Msk (0x3ul << BPWM_WGCTL0_ZPCTL2_Pos) /*!< BPWM_T::WGCTL0: ZPCTL2 Mask */
#define BPWM_WGCTL0_ZPCTL3_Pos (6) /*!< BPWM_T::WGCTL0: ZPCTL3 Position */
#define BPWM_WGCTL0_ZPCTL3_Msk (0x3ul << BPWM_WGCTL0_ZPCTL3_Pos) /*!< BPWM_T::WGCTL0: ZPCTL3 Mask */
#define BPWM_WGCTL0_ZPCTL4_Pos (8) /*!< BPWM_T::WGCTL0: ZPCTL4 Position */
#define BPWM_WGCTL0_ZPCTL4_Msk (0x3ul << BPWM_WGCTL0_ZPCTL4_Pos) /*!< BPWM_T::WGCTL0: ZPCTL4 Mask */
#define BPWM_WGCTL0_ZPCTL5_Pos (10) /*!< BPWM_T::WGCTL0: ZPCTL5 Position */
#define BPWM_WGCTL0_ZPCTL5_Msk (0x3ul << BPWM_WGCTL0_ZPCTL5_Pos) /*!< BPWM_T::WGCTL0: ZPCTL5 Mask */
#define BPWM_WGCTL0_ZPCTLn_Pos (0) /*!< BPWM_T::WGCTL0: ZPCTLn Position */
#define BPWM_WGCTL0_ZPCTLn_Msk (0xffful << BPWM_WGCTL0_ZPCTLn_Pos) /*!< BPWM_T::WGCTL0: ZPCTLn Mask */
#define BPWM_WGCTL0_PRDPCTL0_Pos (16) /*!< BPWM_T::WGCTL0: PRDPCTL0 Position */
#define BPWM_WGCTL0_PRDPCTL0_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL0_Pos) /*!< BPWM_T::WGCTL0: PRDPCTL0 Mask */
#define BPWM_WGCTL0_PRDPCTL1_Pos (18) /*!< BPWM_T::WGCTL0: PRDPCTL1 Position */
#define BPWM_WGCTL0_PRDPCTL1_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL1_Pos) /*!< BPWM_T::WGCTL0: PRDPCTL1 Mask */
#define BPWM_WGCTL0_PRDPCTL2_Pos (20) /*!< BPWM_T::WGCTL0: PRDPCTL2 Position */
#define BPWM_WGCTL0_PRDPCTL2_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL2_Pos) /*!< BPWM_T::WGCTL0: PRDPCTL2 Mask */
#define BPWM_WGCTL0_PRDPCTL3_Pos (22) /*!< BPWM_T::WGCTL0: PRDPCTL3 Position */
#define BPWM_WGCTL0_PRDPCTL3_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL3_Pos) /*!< BPWM_T::WGCTL0: PRDPCTL3 Mask */
#define BPWM_WGCTL0_PRDPCTL4_Pos (24) /*!< BPWM_T::WGCTL0: PRDPCTL4 Position */
#define BPWM_WGCTL0_PRDPCTL4_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL4_Pos) /*!< BPWM_T::WGCTL0: PRDPCTL4 Mask */
#define BPWM_WGCTL0_PRDPCTL5_Pos (26) /*!< BPWM_T::WGCTL0: PRDPCTL5 Position */
#define BPWM_WGCTL0_PRDPCTL5_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL5_Pos) /*!< BPWM_T::WGCTL0: PRDPCTL5 Mask */
#define BPWM_WGCTL0_PRDPCTLn_Pos (16) /*!< BPWM_T::WGCTL0: PRDPCTLn Position */
#define BPWM_WGCTL0_PRDPCTLn_Msk (0xffful << BPWM_WGCTL0_PRDPCTLn_Pos) /*!< BPWM_T::WGCTL0: PRDPCTLn Mask */
#define BPWM_WGCTL1_CMPUCTL0_Pos (0) /*!< BPWM_T::WGCTL1: CMPUCTL0 Position */
#define BPWM_WGCTL1_CMPUCTL0_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL0_Pos) /*!< BPWM_T::WGCTL1: CMPUCTL0 Mask */
#define BPWM_WGCTL1_CMPUCTL1_Pos (2) /*!< BPWM_T::WGCTL1: CMPUCTL1 Position */
#define BPWM_WGCTL1_CMPUCTL1_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL1_Pos) /*!< BPWM_T::WGCTL1: CMPUCTL1 Mask */
#define BPWM_WGCTL1_CMPUCTL2_Pos (4) /*!< BPWM_T::WGCTL1: CMPUCTL2 Position */
#define BPWM_WGCTL1_CMPUCTL2_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL2_Pos) /*!< BPWM_T::WGCTL1: CMPUCTL2 Mask */
#define BPWM_WGCTL1_CMPUCTL3_Pos (6) /*!< BPWM_T::WGCTL1: CMPUCTL3 Position */
#define BPWM_WGCTL1_CMPUCTL3_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL3_Pos) /*!< BPWM_T::WGCTL1: CMPUCTL3 Mask */
#define BPWM_WGCTL1_CMPUCTL4_Pos (8) /*!< BPWM_T::WGCTL1: CMPUCTL4 Position */
#define BPWM_WGCTL1_CMPUCTL4_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL4_Pos) /*!< BPWM_T::WGCTL1: CMPUCTL4 Mask */
#define BPWM_WGCTL1_CMPUCTL5_Pos (10) /*!< BPWM_T::WGCTL1: CMPUCTL5 Position */
#define BPWM_WGCTL1_CMPUCTL5_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL5_Pos) /*!< BPWM_T::WGCTL1: CMPUCTL5 Mask */
#define BPWM_WGCTL1_CMPUCTLn_Pos (0) /*!< BPWM_T::WGCTL1: CMPUCTLn Position */
#define BPWM_WGCTL1_CMPUCTLn_Msk (0xffful << BPWM_WGCTL1_CMPUCTLn_Pos) /*!< BPWM_T::WGCTL1: CMPUCTLn Mask */
#define BPWM_WGCTL1_CMPDCTL0_Pos (16) /*!< BPWM_T::WGCTL1: CMPDCTL0 Position */
#define BPWM_WGCTL1_CMPDCTL0_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL0_Pos) /*!< BPWM_T::WGCTL1: CMPDCTL0 Mask */
#define BPWM_WGCTL1_CMPDCTL1_Pos (18) /*!< BPWM_T::WGCTL1: CMPDCTL1 Position */
#define BPWM_WGCTL1_CMPDCTL1_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL1_Pos) /*!< BPWM_T::WGCTL1: CMPDCTL1 Mask */
#define BPWM_WGCTL1_CMPDCTL2_Pos (20) /*!< BPWM_T::WGCTL1: CMPDCTL2 Position */
#define BPWM_WGCTL1_CMPDCTL2_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL2_Pos) /*!< BPWM_T::WGCTL1: CMPDCTL2 Mask */
#define BPWM_WGCTL1_CMPDCTL3_Pos (22) /*!< BPWM_T::WGCTL1: CMPDCTL3 Position */
#define BPWM_WGCTL1_CMPDCTL3_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL3_Pos) /*!< BPWM_T::WGCTL1: CMPDCTL3 Mask */
#define BPWM_WGCTL1_CMPDCTL4_Pos (24) /*!< BPWM_T::WGCTL1: CMPDCTL4 Position */
#define BPWM_WGCTL1_CMPDCTL4_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL4_Pos) /*!< BPWM_T::WGCTL1: CMPDCTL4 Mask */
#define BPWM_WGCTL1_CMPDCTL5_Pos (26) /*!< BPWM_T::WGCTL1: CMPDCTL5 Position */
#define BPWM_WGCTL1_CMPDCTL5_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL5_Pos) /*!< BPWM_T::WGCTL1: CMPDCTL5 Mask */
#define BPWM_WGCTL1_CMPDCTLn_Pos (16) /*!< BPWM_T::WGCTL1: CMPDCTLn Position */
#define BPWM_WGCTL1_CMPDCTLn_Msk (0xffful << BPWM_WGCTL1_CMPDCTLn_Pos) /*!< BPWM_T::WGCTL1: CMPDCTLn Mask */
#define BPWM_MSKEN_MSKEN0_Pos (0) /*!< BPWM_T::MSKEN: MSKEN0 Position */
#define BPWM_MSKEN_MSKEN0_Msk (0x1ul << BPWM_MSKEN_MSKEN0_Pos) /*!< BPWM_T::MSKEN: MSKEN0 Mask */
#define BPWM_MSKEN_MSKEN1_Pos (1) /*!< BPWM_T::MSKEN: MSKEN1 Position */
#define BPWM_MSKEN_MSKEN1_Msk (0x1ul << BPWM_MSKEN_MSKEN1_Pos) /*!< BPWM_T::MSKEN: MSKEN1 Mask */
#define BPWM_MSKEN_MSKEN2_Pos (2) /*!< BPWM_T::MSKEN: MSKEN2 Position */
#define BPWM_MSKEN_MSKEN2_Msk (0x1ul << BPWM_MSKEN_MSKEN2_Pos) /*!< BPWM_T::MSKEN: MSKEN2 Mask */
#define BPWM_MSKEN_MSKEN3_Pos (3) /*!< BPWM_T::MSKEN: MSKEN3 Position */
#define BPWM_MSKEN_MSKEN3_Msk (0x1ul << BPWM_MSKEN_MSKEN3_Pos) /*!< BPWM_T::MSKEN: MSKEN3 Mask */
#define BPWM_MSKEN_MSKEN4_Pos (4) /*!< BPWM_T::MSKEN: MSKEN4 Position */
#define BPWM_MSKEN_MSKEN4_Msk (0x1ul << BPWM_MSKEN_MSKEN4_Pos) /*!< BPWM_T::MSKEN: MSKEN4 Mask */
#define BPWM_MSKEN_MSKEN5_Pos (5) /*!< BPWM_T::MSKEN: MSKEN5 Position */
#define BPWM_MSKEN_MSKEN5_Msk (0x1ul << BPWM_MSKEN_MSKEN5_Pos) /*!< BPWM_T::MSKEN: MSKEN5 Mask */
#define BPWM_MSKEN_MSKENn_Pos (0) /*!< BPWM_T::MSKEN: MSKENn Position */
#define BPWM_MSKEN_MSKENn_Msk (0x3ful << BPWM_MSKEN_MSKENn_Pos) /*!< BPWM_T::MSKEN: MSKENn Mask */
#define BPWM_MSK_MSKDAT0_Pos (0) /*!< BPWM_T::MSK: MSKDAT0 Position */
#define BPWM_MSK_MSKDAT0_Msk (0x1ul << BPWM_MSK_MSKDAT0_Pos) /*!< BPWM_T::MSK: MSKDAT0 Mask */
#define BPWM_MSK_MSKDAT1_Pos (1) /*!< BPWM_T::MSK: MSKDAT1 Position */
#define BPWM_MSK_MSKDAT1_Msk (0x1ul << BPWM_MSK_MSKDAT1_Pos) /*!< BPWM_T::MSK: MSKDAT1 Mask */
#define BPWM_MSK_MSKDAT2_Pos (2) /*!< BPWM_T::MSK: MSKDAT2 Position */
#define BPWM_MSK_MSKDAT2_Msk (0x1ul << BPWM_MSK_MSKDAT2_Pos) /*!< BPWM_T::MSK: MSKDAT2 Mask */
#define BPWM_MSK_MSKDAT3_Pos (3) /*!< BPWM_T::MSK: MSKDAT3 Position */
#define BPWM_MSK_MSKDAT3_Msk (0x1ul << BPWM_MSK_MSKDAT3_Pos) /*!< BPWM_T::MSK: MSKDAT3 Mask */
#define BPWM_MSK_MSKDAT4_Pos (4) /*!< BPWM_T::MSK: MSKDAT4 Position */
#define BPWM_MSK_MSKDAT4_Msk (0x1ul << BPWM_MSK_MSKDAT4_Pos) /*!< BPWM_T::MSK: MSKDAT4 Mask */
#define BPWM_MSK_MSKDAT5_Pos (5) /*!< BPWM_T::MSK: MSKDAT5 Position */
#define BPWM_MSK_MSKDAT5_Msk (0x1ul << BPWM_MSK_MSKDAT5_Pos) /*!< BPWM_T::MSK: MSKDAT5 Mask */
#define BPWM_MSK_MSKDATn_Pos (0) /*!< BPWM_T::MSK: MSKDATn Position */
#define BPWM_MSK_MSKDATn_Msk (0x3ful << BPWM_MSK_MSKDATn_Pos) /*!< BPWM_T::MSK: MSKDATn Mask */
#define BPWM_POLCTL_PINV0_Pos (0) /*!< BPWM_T::POLCTL: PINV0 Position */
#define BPWM_POLCTL_PINV0_Msk (0x1ul << BPWM_POLCTL_PINV0_Pos) /*!< BPWM_T::POLCTL: PINV0 Mask */
#define BPWM_POLCTL_PINV1_Pos (1) /*!< BPWM_T::POLCTL: PINV1 Position */
#define BPWM_POLCTL_PINV1_Msk (0x1ul << BPWM_POLCTL_PINV1_Pos) /*!< BPWM_T::POLCTL: PINV1 Mask */
#define BPWM_POLCTL_PINV2_Pos (2) /*!< BPWM_T::POLCTL: PINV2 Position */
#define BPWM_POLCTL_PINV2_Msk (0x1ul << BPWM_POLCTL_PINV2_Pos) /*!< BPWM_T::POLCTL: PINV2 Mask */
#define BPWM_POLCTL_PINV3_Pos (3) /*!< BPWM_T::POLCTL: PINV3 Position */
#define BPWM_POLCTL_PINV3_Msk (0x1ul << BPWM_POLCTL_PINV3_Pos) /*!< BPWM_T::POLCTL: PINV3 Mask */
#define BPWM_POLCTL_PINV4_Pos (4) /*!< BPWM_T::POLCTL: PINV4 Position */
#define BPWM_POLCTL_PINV4_Msk (0x1ul << BPWM_POLCTL_PINV4_Pos) /*!< BPWM_T::POLCTL: PINV4 Mask */
#define BPWM_POLCTL_PINV5_Pos (5) /*!< BPWM_T::POLCTL: PINV5 Position */
#define BPWM_POLCTL_PINV5_Msk (0x1ul << BPWM_POLCTL_PINV5_Pos) /*!< BPWM_T::POLCTL: PINV5 Mask */
#define BPWM_POLCTL_PINVn_Pos (0) /*!< BPWM_T::POLCTL: PINVn Position */
#define BPWM_POLCTL_PINVn_Msk (0x3ful << BPWM_POLCTL_PINVn_Pos) /*!< BPWM_T::POLCTL: PINVn Mask */
#define BPWM_POEN_POEN0_Pos (0) /*!< BPWM_T::POEN: POEN0 Position */
#define BPWM_POEN_POEN0_Msk (0x1ul << BPWM_POEN_POEN0_Pos) /*!< BPWM_T::POEN: POEN0 Mask */
#define BPWM_POEN_POEN1_Pos (1) /*!< BPWM_T::POEN: POEN1 Position */
#define BPWM_POEN_POEN1_Msk (0x1ul << BPWM_POEN_POEN1_Pos) /*!< BPWM_T::POEN: POEN1 Mask */
#define BPWM_POEN_POEN2_Pos (2) /*!< BPWM_T::POEN: POEN2 Position */
#define BPWM_POEN_POEN2_Msk (0x1ul << BPWM_POEN_POEN2_Pos) /*!< BPWM_T::POEN: POEN2 Mask */
#define BPWM_POEN_POEN3_Pos (3) /*!< BPWM_T::POEN: POEN3 Position */
#define BPWM_POEN_POEN3_Msk (0x1ul << BPWM_POEN_POEN3_Pos) /*!< BPWM_T::POEN: POEN3 Mask */
#define BPWM_POEN_POEN4_Pos (4) /*!< BPWM_T::POEN: POEN4 Position */
#define BPWM_POEN_POEN4_Msk (0x1ul << BPWM_POEN_POEN4_Pos) /*!< BPWM_T::POEN: POEN4 Mask */
#define BPWM_POEN_POEN5_Pos (5) /*!< BPWM_T::POEN: POEN5 Position */
#define BPWM_POEN_POEN5_Msk (0x1ul << BPWM_POEN_POEN5_Pos) /*!< BPWM_T::POEN: POEN5 Mask */
#define BPWM_POEN_POENn_Pos (0) /*!< BPWM_T::POEN: POENn Position */
#define BPWM_POEN_POENn_Msk (0x3ful << BPWM_POEN_POENn_Pos) /*!< BPWM_T::POEN: POENn Mask */
#define BPWM_INTEN_ZIEN0_Pos (0) /*!< BPWM_T::INTEN: ZIEN0 Position */
#define BPWM_INTEN_ZIEN0_Msk (0x1ul << BPWM_INTEN_ZIEN0_Pos) /*!< BPWM_T::INTEN: ZIEN0 Mask */
#define BPWM_INTEN_PIEN0_Pos (8) /*!< BPWM_T::INTEN: PIEN0 Position */
#define BPWM_INTEN_PIEN0_Msk (0x1ul << BPWM_INTEN_PIEN0_Pos) /*!< BPWM_T::INTEN: PIEN0 Mask */
#define BPWM_INTEN_CMPUIEN0_Pos (16) /*!< BPWM_T::INTEN: CMPUIEN0 Position */
#define BPWM_INTEN_CMPUIEN0_Msk (0x1ul << BPWM_INTEN_CMPUIEN0_Pos) /*!< BPWM_T::INTEN: CMPUIEN0 Mask */
#define BPWM_INTEN_CMPUIEN1_Pos (17) /*!< BPWM_T::INTEN: CMPUIEN1 Position */
#define BPWM_INTEN_CMPUIEN1_Msk (0x1ul << BPWM_INTEN_CMPUIEN1_Pos) /*!< BPWM_T::INTEN: CMPUIEN1 Mask */
#define BPWM_INTEN_CMPUIEN2_Pos (18) /*!< BPWM_T::INTEN: CMPUIEN2 Position */
#define BPWM_INTEN_CMPUIEN2_Msk (0x1ul << BPWM_INTEN_CMPUIEN2_Pos) /*!< BPWM_T::INTEN: CMPUIEN2 Mask */
#define BPWM_INTEN_CMPUIEN3_Pos (19) /*!< BPWM_T::INTEN: CMPUIEN3 Position */
#define BPWM_INTEN_CMPUIEN3_Msk (0x1ul << BPWM_INTEN_CMPUIEN3_Pos) /*!< BPWM_T::INTEN: CMPUIEN3 Mask */
#define BPWM_INTEN_CMPUIEN4_Pos (20) /*!< BPWM_T::INTEN: CMPUIEN4 Position */
#define BPWM_INTEN_CMPUIEN4_Msk (0x1ul << BPWM_INTEN_CMPUIEN4_Pos) /*!< BPWM_T::INTEN: CMPUIEN4 Mask */
#define BPWM_INTEN_CMPUIEN5_Pos (21) /*!< BPWM_T::INTEN: CMPUIEN5 Position */
#define BPWM_INTEN_CMPUIEN5_Msk (0x1ul << BPWM_INTEN_CMPUIEN5_Pos) /*!< BPWM_T::INTEN: CMPUIEN5 Mask */
#define BPWM_INTEN_CMPUIENn_Pos (16) /*!< BPWM_T::INTEN: CMPUIENn Position */
#define BPWM_INTEN_CMPUIENn_Msk (0x3ful << BPWM_INTEN_CMPUIENn_Pos) /*!< BPWM_T::INTEN: CMPUIENn Mask */
#define BPWM_INTEN_CMPDIEN0_Pos (24) /*!< BPWM_T::INTEN: CMPDIEN0 Position */
#define BPWM_INTEN_CMPDIEN0_Msk (0x1ul << BPWM_INTEN_CMPDIEN0_Pos) /*!< BPWM_T::INTEN: CMPDIEN0 Mask */
#define BPWM_INTEN_CMPDIEN1_Pos (25) /*!< BPWM_T::INTEN: CMPDIEN1 Position */
#define BPWM_INTEN_CMPDIEN1_Msk (0x1ul << BPWM_INTEN_CMPDIEN1_Pos) /*!< BPWM_T::INTEN: CMPDIEN1 Mask */
#define BPWM_INTEN_CMPDIEN2_Pos (26) /*!< BPWM_T::INTEN: CMPDIEN2 Position */
#define BPWM_INTEN_CMPDIEN2_Msk (0x1ul << BPWM_INTEN_CMPDIEN2_Pos) /*!< BPWM_T::INTEN: CMPDIEN2 Mask */
#define BPWM_INTEN_CMPDIEN3_Pos (27) /*!< BPWM_T::INTEN: CMPDIEN3 Position */
#define BPWM_INTEN_CMPDIEN3_Msk (0x1ul << BPWM_INTEN_CMPDIEN3_Pos) /*!< BPWM_T::INTEN: CMPDIEN3 Mask */
#define BPWM_INTEN_CMPDIEN4_Pos (28) /*!< BPWM_T::INTEN: CMPDIEN4 Position */
#define BPWM_INTEN_CMPDIEN4_Msk (0x1ul << BPWM_INTEN_CMPDIEN4_Pos) /*!< BPWM_T::INTEN: CMPDIEN4 Mask */
#define BPWM_INTEN_CMPDIEN5_Pos (29) /*!< BPWM_T::INTEN: CMPDIEN5 Position */
#define BPWM_INTEN_CMPDIEN5_Msk (0x1ul << BPWM_INTEN_CMPDIEN5_Pos) /*!< BPWM_T::INTEN: CMPDIEN5 Mask */
#define BPWM_INTEN_CMPDIENn_Pos (24) /*!< BPWM_T::INTEN: CMPDIENn Position */
#define BPWM_INTEN_CMPDIENn_Msk (0x3ful << BPWM_INTEN_CMPDIENn_Pos) /*!< BPWM_T::INTEN: CMPDIENn Mask */
#define BPWM_INTSTS_ZIF0_Pos (0) /*!< BPWM_T::INTSTS: ZIF0 Position */
#define BPWM_INTSTS_ZIF0_Msk (0x1ul << BPWM_INTSTS_ZIF0_Pos) /*!< BPWM_T::INTSTS: ZIF0 Mask */
#define BPWM_INTSTS_PIF0_Pos (8) /*!< BPWM_T::INTSTS: PIF0 Position */
#define BPWM_INTSTS_PIF0_Msk (0x1ul << BPWM_INTSTS_PIF0_Pos) /*!< BPWM_T::INTSTS: PIF0 Mask */
#define BPWM_INTSTS_CMPUIF0_Pos (16) /*!< BPWM_T::INTSTS: CMPUIF0 Position */
#define BPWM_INTSTS_CMPUIF0_Msk (0x1ul << BPWM_INTSTS_CMPUIF0_Pos) /*!< BPWM_T::INTSTS: CMPUIF0 Mask */
#define BPWM_INTSTS_CMPUIF1_Pos (17) /*!< BPWM_T::INTSTS: CMPUIF1 Position */
#define BPWM_INTSTS_CMPUIF1_Msk (0x1ul << BPWM_INTSTS_CMPUIF1_Pos) /*!< BPWM_T::INTSTS: CMPUIF1 Mask */
#define BPWM_INTSTS_CMPUIF2_Pos (18) /*!< BPWM_T::INTSTS: CMPUIF2 Position */
#define BPWM_INTSTS_CMPUIF2_Msk (0x1ul << BPWM_INTSTS_CMPUIF2_Pos) /*!< BPWM_T::INTSTS: CMPUIF2 Mask */
#define BPWM_INTSTS_CMPUIF3_Pos (19) /*!< BPWM_T::INTSTS: CMPUIF3 Position */
#define BPWM_INTSTS_CMPUIF3_Msk (0x1ul << BPWM_INTSTS_CMPUIF3_Pos) /*!< BPWM_T::INTSTS: CMPUIF3 Mask */
#define BPWM_INTSTS_CMPUIF4_Pos (20) /*!< BPWM_T::INTSTS: CMPUIF4 Position */
#define BPWM_INTSTS_CMPUIF4_Msk (0x1ul << BPWM_INTSTS_CMPUIF4_Pos) /*!< BPWM_T::INTSTS: CMPUIF4 Mask */
#define BPWM_INTSTS_CMPUIF5_Pos (21) /*!< BPWM_T::INTSTS: CMPUIF5 Position */
#define BPWM_INTSTS_CMPUIF5_Msk (0x1ul << BPWM_INTSTS_CMPUIF5_Pos) /*!< BPWM_T::INTSTS: CMPUIF5 Mask */
#define BPWM_INTSTS_CMPUIFn_Pos (16) /*!< BPWM_T::INTSTS: CMPUIFn Position */
#define BPWM_INTSTS_CMPUIFn_Msk (0x3ful << BPWM_INTSTS_CMPUIFn_Pos) /*!< BPWM_T::INTSTS: CMPUIFn Mask */
#define BPWM_INTSTS_CMPDIF0_Pos (24) /*!< BPWM_T::INTSTS: CMPDIF0 Position */
#define BPWM_INTSTS_CMPDIF0_Msk (0x1ul << BPWM_INTSTS_CMPDIF0_Pos) /*!< BPWM_T::INTSTS: CMPDIF0 Mask */
#define BPWM_INTSTS_CMPDIF1_Pos (25) /*!< BPWM_T::INTSTS: CMPDIF1 Position */
#define BPWM_INTSTS_CMPDIF1_Msk (0x1ul << BPWM_INTSTS_CMPDIF1_Pos) /*!< BPWM_T::INTSTS: CMPDIF1 Mask */
#define BPWM_INTSTS_CMPDIF2_Pos (26) /*!< BPWM_T::INTSTS: CMPDIF2 Position */
#define BPWM_INTSTS_CMPDIF2_Msk (0x1ul << BPWM_INTSTS_CMPDIF2_Pos) /*!< BPWM_T::INTSTS: CMPDIF2 Mask */
#define BPWM_INTSTS_CMPDIF3_Pos (27) /*!< BPWM_T::INTSTS: CMPDIF3 Position */
#define BPWM_INTSTS_CMPDIF3_Msk (0x1ul << BPWM_INTSTS_CMPDIF3_Pos) /*!< BPWM_T::INTSTS: CMPDIF3 Mask */
#define BPWM_INTSTS_CMPDIF4_Pos (28) /*!< BPWM_T::INTSTS: CMPDIF4 Position */
#define BPWM_INTSTS_CMPDIF4_Msk (0x1ul << BPWM_INTSTS_CMPDIF4_Pos) /*!< BPWM_T::INTSTS: CMPDIF4 Mask */
#define BPWM_INTSTS_CMPDIF5_Pos (29) /*!< BPWM_T::INTSTS: CMPDIF5 Position */
#define BPWM_INTSTS_CMPDIF5_Msk (0x1ul << BPWM_INTSTS_CMPDIF5_Pos) /*!< BPWM_T::INTSTS: CMPDIF5 Mask */
#define BPWM_INTSTS_CMPDIFn_Pos (24) /*!< BPWM_T::INTSTS: CMPDIFn Position */
#define BPWM_INTSTS_CMPDIFn_Msk (0x3ful << BPWM_INTSTS_CMPDIFn_Pos) /*!< BPWM_T::INTSTS: CMPDIFn Mask */
#define BPWM_EADCTS0_TRGSEL0_Pos (0) /*!< BPWM_T::EADCTS0: TRGSEL0 Position */
#define BPWM_EADCTS0_TRGSEL0_Msk (0xful << BPWM_EADCTS0_TRGSEL0_Pos) /*!< BPWM_T::EADCTS0: TRGSEL0 Mask */
#define BPWM_EADCTS0_TRGEN0_Pos (7) /*!< BPWM_T::EADCTS0: TRGEN0 Position */
#define BPWM_EADCTS0_TRGEN0_Msk (0x1ul << BPWM_EADCTS0_TRGEN0_Pos) /*!< BPWM_T::EADCTS0: TRGEN0 Mask */
#define BPWM_EADCTS0_TRGSEL1_Pos (8) /*!< BPWM_T::EADCTS0: TRGSEL1 Position */
#define BPWM_EADCTS0_TRGSEL1_Msk (0xful << BPWM_EADCTS0_TRGSEL1_Pos) /*!< BPWM_T::EADCTS0: TRGSEL1 Mask */
#define BPWM_EADCTS0_TRGEN1_Pos (15) /*!< BPWM_T::EADCTS0: TRGEN1 Position */
#define BPWM_EADCTS0_TRGEN1_Msk (0x1ul << BPWM_EADCTS0_TRGEN1_Pos) /*!< BPWM_T::EADCTS0: TRGEN1 Mask */
#define BPWM_EADCTS0_TRGSEL2_Pos (16) /*!< BPWM_T::EADCTS0: TRGSEL2 Position */
#define BPWM_EADCTS0_TRGSEL2_Msk (0xful << BPWM_EADCTS0_TRGSEL2_Pos) /*!< BPWM_T::EADCTS0: TRGSEL2 Mask */
#define BPWM_EADCTS0_TRGEN2_Pos (23) /*!< BPWM_T::EADCTS0: TRGEN2 Position */
#define BPWM_EADCTS0_TRGEN2_Msk (0x1ul << BPWM_EADCTS0_TRGEN2_Pos) /*!< BPWM_T::EADCTS0: TRGEN2 Mask */
#define BPWM_EADCTS0_TRGSEL3_Pos (24) /*!< BPWM_T::EADCTS0: TRGSEL3 Position */
#define BPWM_EADCTS0_TRGSEL3_Msk (0xful << BPWM_EADCTS0_TRGSEL3_Pos) /*!< BPWM_T::EADCTS0: TRGSEL3 Mask */
#define BPWM_EADCTS0_TRGEN3_Pos (31) /*!< BPWM_T::EADCTS0: TRGEN3 Position */
#define BPWM_EADCTS0_TRGEN3_Msk (0x1ul << BPWM_EADCTS0_TRGEN3_Pos) /*!< BPWM_T::EADCTS0: TRGEN3 Mask */
#define BPWM_EADCTS1_TRGSEL4_Pos (0) /*!< BPWM_T::EADCTS1: TRGSEL4 Position */
#define BPWM_EADCTS1_TRGSEL4_Msk (0xful << BPWM_EADCTS1_TRGSEL4_Pos) /*!< BPWM_T::EADCTS1: TRGSEL4 Mask */
#define BPWM_EADCTS1_TRGEN4_Pos (7) /*!< BPWM_T::EADCTS1: TRGEN4 Position */
#define BPWM_EADCTS1_TRGEN4_Msk (0x1ul << BPWM_EADCTS1_TRGEN4_Pos) /*!< BPWM_T::EADCTS1: TRGEN4 Mask */
#define BPWM_EADCTS1_TRGSEL5_Pos (8) /*!< BPWM_T::EADCTS1: TRGSEL5 Position */
#define BPWM_EADCTS1_TRGSEL5_Msk (0xful << BPWM_EADCTS1_TRGSEL5_Pos) /*!< BPWM_T::EADCTS1: TRGSEL5 Mask */
#define BPWM_EADCTS1_TRGEN5_Pos (15) /*!< BPWM_T::EADCTS1: TRGEN5 Position */
#define BPWM_EADCTS1_TRGEN5_Msk (0x1ul << BPWM_EADCTS1_TRGEN5_Pos) /*!< BPWM_T::EADCTS1: TRGEN5 Mask */
#define BPWM_SSCTL_SSEN0_Pos (0) /*!< BPWM_T::SSCTL: SSEN0 Position */
#define BPWM_SSCTL_SSEN0_Msk (0x1ul << BPWM_SSCTL_SSEN0_Pos) /*!< BPWM_T::SSCTL: SSEN0 Mask */
#define BPWM_SSCTL_SSRC_Pos (8) /*!< BPWM_T::SSCTL: SSRC Position */
#define BPWM_SSCTL_SSRC_Msk (0x3ul << BPWM_SSCTL_SSRC_Pos) /*!< BPWM_T::SSCTL: SSRC Mask */
#define BPWM_SSTRG_CNTSEN_Pos (0) /*!< BPWM_T::SSTRG: CNTSEN Position */
#define BPWM_SSTRG_CNTSEN_Msk (0x1ul << BPWM_SSTRG_CNTSEN_Pos) /*!< BPWM_T::SSTRG: CNTSEN Mask */
#define BPWM_STATUS_CNTMAX0_Pos (0) /*!< BPWM_T::STATUS: CNTMAX0 Position */
#define BPWM_STATUS_CNTMAX0_Msk (0x1ul << BPWM_STATUS_CNTMAX0_Pos) /*!< BPWM_T::STATUS: CNTMAX0 Mask */
#define BPWM_STATUS_EADCTRG0_Pos (16) /*!< BPWM_T::STATUS: EADCTRG0 Position */
#define BPWM_STATUS_EADCTRG0_Msk (0x1ul << BPWM_STATUS_EADCTRG0_Pos) /*!< BPWM_T::STATUS: EADCTRG0 Mask */
#define BPWM_STATUS_EADCTRG1_Pos (17) /*!< BPWM_T::STATUS: EADCTRG1 Position */
#define BPWM_STATUS_EADCTRG1_Msk (0x1ul << BPWM_STATUS_EADCTRG1_Pos) /*!< BPWM_T::STATUS: EADCTRG1 Mask */
#define BPWM_STATUS_EADCTRG2_Pos (18) /*!< BPWM_T::STATUS: EADCTRG2 Position */
#define BPWM_STATUS_EADCTRG2_Msk (0x1ul << BPWM_STATUS_EADCTRG2_Pos) /*!< BPWM_T::STATUS: EADCTRG2 Mask */
#define BPWM_STATUS_EADCTRG3_Pos (19) /*!< BPWM_T::STATUS: EADCTRG3 Position */
#define BPWM_STATUS_EADCTRG3_Msk (0x1ul << BPWM_STATUS_EADCTRG3_Pos) /*!< BPWM_T::STATUS: EADCTRG3 Mask */
#define BPWM_STATUS_EADCTRG4_Pos (20) /*!< BPWM_T::STATUS: EADCTRG4 Position */
#define BPWM_STATUS_EADCTRG4_Msk (0x1ul << BPWM_STATUS_EADCTRG4_Pos) /*!< BPWM_T::STATUS: EADCTRG4 Mask */
#define BPWM_STATUS_EADCTRG5_Pos (21) /*!< BPWM_T::STATUS: EADCTRG5 Position */
#define BPWM_STATUS_EADCTRG5_Msk (0x1ul << BPWM_STATUS_EADCTRG5_Pos) /*!< BPWM_T::STATUS: EADCTRG5 Mask */
#define BPWM_STATUS_EADCTRGn_Pos (16) /*!< BPWM_T::STATUS: EADCTRGn Position */
#define BPWM_STATUS_EADCTRGn_Msk (0x3ful << BPWM_STATUS_EADCTRGn_Pos) /*!< BPWM_T::STATUS: EADCTRGn Mask */
#define BPWM_CAPINEN_CAPINEN0_Pos (0) /*!< BPWM_T::CAPINEN: CAPINEN0 Position */
#define BPWM_CAPINEN_CAPINEN0_Msk (0x1ul << BPWM_CAPINEN_CAPINEN0_Pos) /*!< BPWM_T::CAPINEN: CAPINEN0 Mask */
#define BPWM_CAPINEN_CAPINEN1_Pos (1) /*!< BPWM_T::CAPINEN: CAPINEN1 Position */
#define BPWM_CAPINEN_CAPINEN1_Msk (0x1ul << BPWM_CAPINEN_CAPINEN1_Pos) /*!< BPWM_T::CAPINEN: CAPINEN1 Mask */
#define BPWM_CAPINEN_CAPINEN2_Pos (2) /*!< BPWM_T::CAPINEN: CAPINEN2 Position */
#define BPWM_CAPINEN_CAPINEN2_Msk (0x1ul << BPWM_CAPINEN_CAPINEN2_Pos) /*!< BPWM_T::CAPINEN: CAPINEN2 Mask */
#define BPWM_CAPINEN_CAPINEN3_Pos (3) /*!< BPWM_T::CAPINEN: CAPINEN3 Position */
#define BPWM_CAPINEN_CAPINEN3_Msk (0x1ul << BPWM_CAPINEN_CAPINEN3_Pos) /*!< BPWM_T::CAPINEN: CAPINEN3 Mask */
#define BPWM_CAPINEN_CAPINEN4_Pos (4) /*!< BPWM_T::CAPINEN: CAPINEN4 Position */
#define BPWM_CAPINEN_CAPINEN4_Msk (0x1ul << BPWM_CAPINEN_CAPINEN4_Pos) /*!< BPWM_T::CAPINEN: CAPINEN4 Mask */
#define BPWM_CAPINEN_CAPINEN5_Pos (5) /*!< BPWM_T::CAPINEN: CAPINEN5 Position */
#define BPWM_CAPINEN_CAPINEN5_Msk (0x1ul << BPWM_CAPINEN_CAPINEN5_Pos) /*!< BPWM_T::CAPINEN: CAPINEN5 Mask */
#define BPWM_CAPINEN_CAPINENn_Pos (0) /*!< BPWM_T::CAPINEN: CAPINENn Position */
#define BPWM_CAPINEN_CAPINENn_Msk (0x3ful << BPWM_CAPINEN_CAPINENn_Pos) /*!< BPWM_T::CAPINEN: CAPINENn Mask */
#define BPWM_CAPCTL_CAPEN0_Pos (0) /*!< BPWM_T::CAPCTL: CAPEN0 Position */
#define BPWM_CAPCTL_CAPEN0_Msk (0x1ul << BPWM_CAPCTL_CAPEN0_Pos) /*!< BPWM_T::CAPCTL: CAPEN0 Mask */
#define BPWM_CAPCTL_CAPEN1_Pos (1) /*!< BPWM_T::CAPCTL: CAPEN1 Position */
#define BPWM_CAPCTL_CAPEN1_Msk (0x1ul << BPWM_CAPCTL_CAPEN1_Pos) /*!< BPWM_T::CAPCTL: CAPEN1 Mask */
#define BPWM_CAPCTL_CAPEN2_Pos (2) /*!< BPWM_T::CAPCTL: CAPEN2 Position */
#define BPWM_CAPCTL_CAPEN2_Msk (0x1ul << BPWM_CAPCTL_CAPEN2_Pos) /*!< BPWM_T::CAPCTL: CAPEN2 Mask */
#define BPWM_CAPCTL_CAPEN3_Pos (3) /*!< BPWM_T::CAPCTL: CAPEN3 Position */
#define BPWM_CAPCTL_CAPEN3_Msk (0x1ul << BPWM_CAPCTL_CAPEN3_Pos) /*!< BPWM_T::CAPCTL: CAPEN3 Mask */
#define BPWM_CAPCTL_CAPEN4_Pos (4) /*!< BPWM_T::CAPCTL: CAPEN4 Position */
#define BPWM_CAPCTL_CAPEN4_Msk (0x1ul << BPWM_CAPCTL_CAPEN4_Pos) /*!< BPWM_T::CAPCTL: CAPEN4 Mask */
#define BPWM_CAPCTL_CAPEN5_Pos (5) /*!< BPWM_T::CAPCTL: CAPEN5 Position */
#define BPWM_CAPCTL_CAPEN5_Msk (0x1ul << BPWM_CAPCTL_CAPEN5_Pos) /*!< BPWM_T::CAPCTL: CAPEN5 Mask */
#define BPWM_CAPCTL_CAPENn_Pos (0) /*!< BPWM_T::CAPCTL: CAPENn Position */
#define BPWM_CAPCTL_CAPENn_Msk (0x3ful << BPWM_CAPCTL_CAPENn_Pos) /*!< BPWM_T::CAPCTL: CAPENn Mask */
#define BPWM_CAPCTL_CAPINV0_Pos (8) /*!< BPWM_T::CAPCTL: CAPINV0 Position */
#define BPWM_CAPCTL_CAPINV0_Msk (0x1ul << BPWM_CAPCTL_CAPINV0_Pos) /*!< BPWM_T::CAPCTL: CAPINV0 Mask */
#define BPWM_CAPCTL_CAPINV1_Pos (9) /*!< BPWM_T::CAPCTL: CAPINV1 Position */
#define BPWM_CAPCTL_CAPINV1_Msk (0x1ul << BPWM_CAPCTL_CAPINV1_Pos) /*!< BPWM_T::CAPCTL: CAPINV1 Mask */
#define BPWM_CAPCTL_CAPINV2_Pos (10) /*!< BPWM_T::CAPCTL: CAPINV2 Position */
#define BPWM_CAPCTL_CAPINV2_Msk (0x1ul << BPWM_CAPCTL_CAPINV2_Pos) /*!< BPWM_T::CAPCTL: CAPINV2 Mask */
#define BPWM_CAPCTL_CAPINV3_Pos (11) /*!< BPWM_T::CAPCTL: CAPINV3 Position */
#define BPWM_CAPCTL_CAPINV3_Msk (0x1ul << BPWM_CAPCTL_CAPINV3_Pos) /*!< BPWM_T::CAPCTL: CAPINV3 Mask */
#define BPWM_CAPCTL_CAPINV4_Pos (12) /*!< BPWM_T::CAPCTL: CAPINV4 Position */
#define BPWM_CAPCTL_CAPINV4_Msk (0x1ul << BPWM_CAPCTL_CAPINV4_Pos) /*!< BPWM_T::CAPCTL: CAPINV4 Mask */
#define BPWM_CAPCTL_CAPINV5_Pos (13) /*!< BPWM_T::CAPCTL: CAPINV5 Position */
#define BPWM_CAPCTL_CAPINV5_Msk (0x1ul << BPWM_CAPCTL_CAPINV5_Pos) /*!< BPWM_T::CAPCTL: CAPINV5 Mask */
#define BPWM_CAPCTL_CAPINVn_Pos (8) /*!< BPWM_T::CAPCTL: CAPINVn Position */
#define BPWM_CAPCTL_CAPINVn_Msk (0x3ful << BPWM_CAPCTL_CAPINVn_Pos) /*!< BPWM_T::CAPCTL: CAPINVn Mask */
#define BPWM_CAPCTL_RCRLDEN0_Pos (16) /*!< BPWM_T::CAPCTL: RCRLDEN0 Position */
#define BPWM_CAPCTL_RCRLDEN0_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN0_Pos) /*!< BPWM_T::CAPCTL: RCRLDEN0 Mask */
#define BPWM_CAPCTL_RCRLDEN1_Pos (17) /*!< BPWM_T::CAPCTL: RCRLDEN1 Position */
#define BPWM_CAPCTL_RCRLDEN1_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN1_Pos) /*!< BPWM_T::CAPCTL: RCRLDEN1 Mask */
#define BPWM_CAPCTL_RCRLDEN2_Pos (18) /*!< BPWM_T::CAPCTL: RCRLDEN2 Position */
#define BPWM_CAPCTL_RCRLDEN2_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN2_Pos) /*!< BPWM_T::CAPCTL: RCRLDEN2 Mask */
#define BPWM_CAPCTL_RCRLDEN3_Pos (19) /*!< BPWM_T::CAPCTL: RCRLDEN3 Position */
#define BPWM_CAPCTL_RCRLDEN3_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN3_Pos) /*!< BPWM_T::CAPCTL: RCRLDEN3 Mask */
#define BPWM_CAPCTL_RCRLDEN4_Pos (20) /*!< BPWM_T::CAPCTL: RCRLDEN4 Position */
#define BPWM_CAPCTL_RCRLDEN4_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN4_Pos) /*!< BPWM_T::CAPCTL: RCRLDEN4 Mask */
#define BPWM_CAPCTL_RCRLDEN5_Pos (21) /*!< BPWM_T::CAPCTL: RCRLDEN5 Position */
#define BPWM_CAPCTL_RCRLDEN5_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN5_Pos) /*!< BPWM_T::CAPCTL: RCRLDEN5 Mask */
#define BPWM_CAPCTL_RCRLDENn_Pos (16) /*!< BPWM_T::CAPCTL: RCRLDENn Position */
#define BPWM_CAPCTL_RCRLDENn_Msk (0x3ful << BPWM_CAPCTL_RCRLDENn_Pos) /*!< BPWM_T::CAPCTL: RCRLDENn Mask */
#define BPWM_CAPCTL_FCRLDEN0_Pos (24) /*!< BPWM_T::CAPCTL: FCRLDEN0 Position */
#define BPWM_CAPCTL_FCRLDEN0_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN0_Pos) /*!< BPWM_T::CAPCTL: FCRLDEN0 Mask */
#define BPWM_CAPCTL_FCRLDEN1_Pos (25) /*!< BPWM_T::CAPCTL: FCRLDEN1 Position */
#define BPWM_CAPCTL_FCRLDEN1_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN1_Pos) /*!< BPWM_T::CAPCTL: FCRLDEN1 Mask */
#define BPWM_CAPCTL_FCRLDEN2_Pos (26) /*!< BPWM_T::CAPCTL: FCRLDEN2 Position */
#define BPWM_CAPCTL_FCRLDEN2_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN2_Pos) /*!< BPWM_T::CAPCTL: FCRLDEN2 Mask */
#define BPWM_CAPCTL_FCRLDEN3_Pos (27) /*!< BPWM_T::CAPCTL: FCRLDEN3 Position */
#define BPWM_CAPCTL_FCRLDEN3_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN3_Pos) /*!< BPWM_T::CAPCTL: FCRLDEN3 Mask */
#define BPWM_CAPCTL_FCRLDEN4_Pos (28) /*!< BPWM_T::CAPCTL: FCRLDEN4 Position */
#define BPWM_CAPCTL_FCRLDEN4_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN4_Pos) /*!< BPWM_T::CAPCTL: FCRLDEN4 Mask */
#define BPWM_CAPCTL_FCRLDEN5_Pos (29) /*!< BPWM_T::CAPCTL: FCRLDEN5 Position */
#define BPWM_CAPCTL_FCRLDEN5_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN5_Pos) /*!< BPWM_T::CAPCTL: FCRLDEN5 Mask */
#define BPWM_CAPCTL_FCRLDENn_Pos (24) /*!< BPWM_T::CAPCTL: FCRLDENn Position */
#define BPWM_CAPCTL_FCRLDENn_Msk (0x3ful << BPWM_CAPCTL_FCRLDENn_Pos) /*!< BPWM_T::CAPCTL: FCRLDENn Mask */
#define BPWM_CAPSTS_CRIFOV0_Pos (0) /*!< BPWM_T::CAPSTS: CRIFOV0 Position */
#define BPWM_CAPSTS_CRIFOV0_Msk (0x1ul << BPWM_CAPSTS_CRIFOV0_Pos) /*!< BPWM_T::CAPSTS: CRIFOV0 Mask */
#define BPWM_CAPSTS_CRIFOV1_Pos (1) /*!< BPWM_T::CAPSTS: CRIFOV1 Position */
#define BPWM_CAPSTS_CRIFOV1_Msk (0x1ul << BPWM_CAPSTS_CRIFOV1_Pos) /*!< BPWM_T::CAPSTS: CRIFOV1 Mask */
#define BPWM_CAPSTS_CRIFOV2_Pos (2) /*!< BPWM_T::CAPSTS: CRIFOV2 Position */
#define BPWM_CAPSTS_CRIFOV2_Msk (0x1ul << BPWM_CAPSTS_CRIFOV2_Pos) /*!< BPWM_T::CAPSTS: CRIFOV2 Mask */
#define BPWM_CAPSTS_CRIFOV3_Pos (3) /*!< BPWM_T::CAPSTS: CRIFOV3 Position */
#define BPWM_CAPSTS_CRIFOV3_Msk (0x1ul << BPWM_CAPSTS_CRIFOV3_Pos) /*!< BPWM_T::CAPSTS: CRIFOV3 Mask */
#define BPWM_CAPSTS_CRIFOV4_Pos (4) /*!< BPWM_T::CAPSTS: CRIFOV4 Position */
#define BPWM_CAPSTS_CRIFOV4_Msk (0x1ul << BPWM_CAPSTS_CRIFOV4_Pos) /*!< BPWM_T::CAPSTS: CRIFOV4 Mask */
#define BPWM_CAPSTS_CRIFOV5_Pos (5) /*!< BPWM_T::CAPSTS: CRIFOV5 Position */
#define BPWM_CAPSTS_CRIFOV5_Msk (0x1ul << BPWM_CAPSTS_CRIFOV5_Pos) /*!< BPWM_T::CAPSTS: CRIFOV5 Mask */
#define BPWM_CAPSTS_CRIFOVn_Pos (0) /*!< BPWM_T::CAPSTS: CRIFOVn Position */
#define BPWM_CAPSTS_CRIFOVn_Msk (0x3ful << BPWM_CAPSTS_CRIFOVn_Pos) /*!< BPWM_T::CAPSTS: CRIFOVn Mask */
#define BPWM_CAPSTS_CFIFOV0_Pos (8) /*!< BPWM_T::CAPSTS: CFIFOV0 Position */
#define BPWM_CAPSTS_CFIFOV0_Msk (0x1ul << BPWM_CAPSTS_CFIFOV0_Pos) /*!< BPWM_T::CAPSTS: CFIFOV0 Mask */
#define BPWM_CAPSTS_CFIFOV1_Pos (9) /*!< BPWM_T::CAPSTS: CFIFOV1 Position */
#define BPWM_CAPSTS_CFIFOV1_Msk (0x1ul << BPWM_CAPSTS_CFIFOV1_Pos) /*!< BPWM_T::CAPSTS: CFIFOV1 Mask */
#define BPWM_CAPSTS_CFIFOV2_Pos (10) /*!< BPWM_T::CAPSTS: CFIFOV2 Position */
#define BPWM_CAPSTS_CFIFOV2_Msk (0x1ul << BPWM_CAPSTS_CFIFOV2_Pos) /*!< BPWM_T::CAPSTS: CFIFOV2 Mask */
#define BPWM_CAPSTS_CFIFOV3_Pos (11) /*!< BPWM_T::CAPSTS: CFIFOV3 Position */
#define BPWM_CAPSTS_CFIFOV3_Msk (0x1ul << BPWM_CAPSTS_CFIFOV3_Pos) /*!< BPWM_T::CAPSTS: CFIFOV3 Mask */
#define BPWM_CAPSTS_CFIFOV4_Pos (12) /*!< BPWM_T::CAPSTS: CFIFOV4 Position */
#define BPWM_CAPSTS_CFIFOV4_Msk (0x1ul << BPWM_CAPSTS_CFIFOV4_Pos) /*!< BPWM_T::CAPSTS: CFIFOV4 Mask */
#define BPWM_CAPSTS_CFIFOV5_Pos (13) /*!< BPWM_T::CAPSTS: CFIFOV5 Position */
#define BPWM_CAPSTS_CFIFOV5_Msk (0x1ul << BPWM_CAPSTS_CFIFOV5_Pos) /*!< BPWM_T::CAPSTS: CFIFOV5 Mask */
#define BPWM_CAPSTS_CFIFOVn_Pos (8) /*!< BPWM_T::CAPSTS: CFIFOVn Position */
#define BPWM_CAPSTS_CFIFOVn_Msk (0x3ful << BPWM_CAPSTS_CFIFOVn_Pos) /*!< BPWM_T::CAPSTS: CFIFOVn Mask */
#define BPWM_RCAPDAT0_RCAPDAT_Pos (0) /*!< BPWM_T::RCAPDAT0: RCAPDAT Position */
#define BPWM_RCAPDAT0_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT0_RCAPDAT_Pos) /*!< BPWM_T::RCAPDAT0: RCAPDAT Mask */
#define BPWM_FCAPDAT0_FCAPDAT_Pos (0) /*!< BPWM_T::FCAPDAT0: FCAPDAT Position */
#define BPWM_FCAPDAT0_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT0_FCAPDAT_Pos) /*!< BPWM_T::FCAPDAT0: FCAPDAT Mask */
#define BPWM_RCAPDAT1_RCAPDAT_Pos (0) /*!< BPWM_T::RCAPDAT1: RCAPDAT Position */
#define BPWM_RCAPDAT1_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT1_RCAPDAT_Pos) /*!< BPWM_T::RCAPDAT1: RCAPDAT Mask */
#define BPWM_FCAPDAT1_FCAPDAT_Pos (0) /*!< BPWM_T::FCAPDAT1: FCAPDAT Position */
#define BPWM_FCAPDAT1_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT1_FCAPDAT_Pos) /*!< BPWM_T::FCAPDAT1: FCAPDAT Mask */
#define BPWM_RCAPDAT2_RCAPDAT_Pos (0) /*!< BPWM_T::RCAPDAT2: RCAPDAT Position */
#define BPWM_RCAPDAT2_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT2_RCAPDAT_Pos) /*!< BPWM_T::RCAPDAT2: RCAPDAT Mask */
#define BPWM_FCAPDAT2_FCAPDAT_Pos (0) /*!< BPWM_T::FCAPDAT2: FCAPDAT Position */
#define BPWM_FCAPDAT2_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT2_FCAPDAT_Pos) /*!< BPWM_T::FCAPDAT2: FCAPDAT Mask */
#define BPWM_RCAPDAT3_RCAPDAT_Pos (0) /*!< BPWM_T::RCAPDAT3: RCAPDAT Position */
#define BPWM_RCAPDAT3_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT3_RCAPDAT_Pos) /*!< BPWM_T::RCAPDAT3: RCAPDAT Mask */
#define BPWM_FCAPDAT3_FCAPDAT_Pos (0) /*!< BPWM_T::FCAPDAT3: FCAPDAT Position */
#define BPWM_FCAPDAT3_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT3_FCAPDAT_Pos) /*!< BPWM_T::FCAPDAT3: FCAPDAT Mask */
#define BPWM_RCAPDAT4_RCAPDAT_Pos (0) /*!< BPWM_T::RCAPDAT4: RCAPDAT Position */
#define BPWM_RCAPDAT4_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT4_RCAPDAT_Pos) /*!< BPWM_T::RCAPDAT4: RCAPDAT Mask */
#define BPWM_FCAPDAT4_FCAPDAT_Pos (0) /*!< BPWM_T::FCAPDAT4: FCAPDAT Position */
#define BPWM_FCAPDAT4_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT4_FCAPDAT_Pos) /*!< BPWM_T::FCAPDAT4: FCAPDAT Mask */
#define BPWM_RCAPDAT5_RCAPDAT_Pos (0) /*!< BPWM_T::RCAPDAT5: RCAPDAT Position */
#define BPWM_RCAPDAT5_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT5_RCAPDAT_Pos) /*!< BPWM_T::RCAPDAT5: RCAPDAT Mask */
#define BPWM_FCAPDAT5_FCAPDAT_Pos (0) /*!< BPWM_T::FCAPDAT5: FCAPDAT Position */
#define BPWM_FCAPDAT5_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT5_FCAPDAT_Pos) /*!< BPWM_T::FCAPDAT5: FCAPDAT Mask */
#define BPWM_CAPIEN_CAPRIENn_Pos (0) /*!< BPWM_T::CAPIEN: CAPRIENn Position */
#define BPWM_CAPIEN_CAPRIENn_Msk (0x3ful << BPWM_CAPIEN_CAPRIENn_Pos) /*!< BPWM_T::CAPIEN: CAPRIENn Mask */
#define BPWM_CAPIEN_CAPFIENn_Pos (8) /*!< BPWM_T::CAPIEN: CAPFIENn Position */
#define BPWM_CAPIEN_CAPFIENn_Msk (0x3ful << BPWM_CAPIEN_CAPFIENn_Pos) /*!< BPWM_T::CAPIEN: CAPFIENn Mask */
#define BPWM_CAPIF_CAPRIF0_Pos (0) /*!< BPWM_T::CAPIF: CAPRIF0 Position */
#define BPWM_CAPIF_CAPRIF0_Msk (0x1ul << BPWM_CAPIF_CAPRIF0_Pos) /*!< BPWM_T::CAPIF: CAPRIF0 Mask */
#define BPWM_CAPIF_CAPRIF1_Pos (1) /*!< BPWM_T::CAPIF: CAPRIF1 Position */
#define BPWM_CAPIF_CAPRIF1_Msk (0x1ul << BPWM_CAPIF_CAPRIF1_Pos) /*!< BPWM_T::CAPIF: CAPRIF1 Mask */
#define BPWM_CAPIF_CAPRIF2_Pos (2) /*!< BPWM_T::CAPIF: CAPRIF2 Position */
#define BPWM_CAPIF_CAPRIF2_Msk (0x1ul << BPWM_CAPIF_CAPRIF2_Pos) /*!< BPWM_T::CAPIF: CAPRIF2 Mask */
#define BPWM_CAPIF_CAPRIF3_Pos (3) /*!< BPWM_T::CAPIF: CAPRIF3 Position */
#define BPWM_CAPIF_CAPRIF3_Msk (0x1ul << BPWM_CAPIF_CAPRIF3_Pos) /*!< BPWM_T::CAPIF: CAPRIF3 Mask */
#define BPWM_CAPIF_CAPRIF4_Pos (4) /*!< BPWM_T::CAPIF: CAPRIF4 Position */
#define BPWM_CAPIF_CAPRIF4_Msk (0x1ul << BPWM_CAPIF_CAPRIF4_Pos) /*!< BPWM_T::CAPIF: CAPRIF4 Mask */
#define BPWM_CAPIF_CAPRIF5_Pos (5) /*!< BPWM_T::CAPIF: CAPRIF5 Position */
#define BPWM_CAPIF_CAPRIF5_Msk (0x1ul << BPWM_CAPIF_CAPRIF5_Pos) /*!< BPWM_T::CAPIF: CAPRIF5 Mask */
#define BPWM_CAPIF_CAPRIFn_Pos (0) /*!< BPWM_T::CAPIF: CAPRIFn Position */
#define BPWM_CAPIF_CAPRIFn_Msk (0x3ful << BPWM_CAPIF_CAPRIFn_Pos) /*!< BPWM_T::CAPIF: CAPRIFn Mask */
#define BPWM_CAPIF_CAPFIF0_Pos (8) /*!< BPWM_T::CAPIF: CAPFIF0 Position */
#define BPWM_CAPIF_CAPFIF0_Msk (0x1ul << BPWM_CAPIF_CAPFIF0_Pos) /*!< BPWM_T::CAPIF: CAPFIF0 Mask */
#define BPWM_CAPIF_CAPFIF1_Pos (9) /*!< BPWM_T::CAPIF: CAPFIF1 Position */
#define BPWM_CAPIF_CAPFIF1_Msk (0x1ul << BPWM_CAPIF_CAPFIF1_Pos) /*!< BPWM_T::CAPIF: CAPFIF1 Mask */
#define BPWM_CAPIF_CAPFIF2_Pos (10) /*!< BPWM_T::CAPIF: CAPFIF2 Position */
#define BPWM_CAPIF_CAPFIF2_Msk (0x1ul << BPWM_CAPIF_CAPFIF2_Pos) /*!< BPWM_T::CAPIF: CAPFIF2 Mask */
#define BPWM_CAPIF_CAPFIF3_Pos (11) /*!< BPWM_T::CAPIF: CAPFIF3 Position */
#define BPWM_CAPIF_CAPFIF3_Msk (0x1ul << BPWM_CAPIF_CAPFIF3_Pos) /*!< BPWM_T::CAPIF: CAPFIF3 Mask */
#define BPWM_CAPIF_CAPFIF4_Pos (12) /*!< BPWM_T::CAPIF: CAPFIF4 Position */
#define BPWM_CAPIF_CAPFIF4_Msk (0x1ul << BPWM_CAPIF_CAPFIF4_Pos) /*!< BPWM_T::CAPIF: CAPFIF4 Mask */
#define BPWM_CAPIF_CAPFIF5_Pos (13) /*!< BPWM_T::CAPIF: CAPFIF5 Position */
#define BPWM_CAPIF_CAPFIF5_Msk (0x1ul << BPWM_CAPIF_CAPFIF5_Pos) /*!< BPWM_T::CAPIF: CAPFIF5 Mask */
#define BPWM_CAPIF_CAPFIFn_Pos (8) /*!< BPWM_T::CAPIF: CAPFIFn Position */
#define BPWM_CAPIF_CAPFIFn_Msk (0x3ful << BPWM_CAPIF_CAPFIFn_Pos) /*!< BPWM_T::CAPIF: CAPFIFn Mask */
#define BPWM_PBUF_PBUF_Pos (0) /*!< BPWM_T::PBUF: PBUF Position */
#define BPWM_PBUF_PBUF_Msk (0xfffful << BPWM_PBUF_PBUF_Pos) /*!< BPWM_T::PBUF: PBUF Mask */
#define BPWM_CMPBUF0_CMPBUF_Pos (0) /*!< BPWM_T::CMPBUF0: CMPBUF Position */
#define BPWM_CMPBUF0_CMPBUF_Msk (0xfffful << BPWM_CMPBUF0_CMPBUF_Pos) /*!< BPWM_T::CMPBUF0: CMPBUF Mask */
#define BPWM_CMPBUF1_CMPBUF_Pos (0) /*!< BPWM_T::CMPBUF1: CMPBUF Position */
#define BPWM_CMPBUF1_CMPBUF_Msk (0xfffful << BPWM_CMPBUF1_CMPBUF_Pos) /*!< BPWM_T::CMPBUF1: CMPBUF Mask */
#define BPWM_CMPBUF2_CMPBUF_Pos (0) /*!< BPWM_T::CMPBUF2: CMPBUF Position */
#define BPWM_CMPBUF2_CMPBUF_Msk (0xfffful << BPWM_CMPBUF2_CMPBUF_Pos) /*!< BPWM_T::CMPBUF2: CMPBUF Mask */
#define BPWM_CMPBUF3_CMPBUF_Pos (0) /*!< BPWM_T::CMPBUF3: CMPBUF Position */
#define BPWM_CMPBUF3_CMPBUF_Msk (0xfffful << BPWM_CMPBUF3_CMPBUF_Pos) /*!< BPWM_T::CMPBUF3: CMPBUF Mask */
#define BPWM_CMPBUF4_CMPBUF_Pos (0) /*!< BPWM_T::CMPBUF4: CMPBUF Position */
#define BPWM_CMPBUF4_CMPBUF_Msk (0xfffful << BPWM_CMPBUF4_CMPBUF_Pos) /*!< BPWM_T::CMPBUF4: CMPBUF Mask */
#define BPWM_CMPBUF5_CMPBUF_Pos (0) /*!< BPWM_T::CMPBUF5: CMPBUF Position */
#define BPWM_CMPBUF5_CMPBUF_Msk (0xfffful << BPWM_CMPBUF5_CMPBUF_Pos) /*!< BPWM_T::CMPBUF5: CMPBUF Mask */
/**@}*/ /* BPWM_CONST */
/**@}*/ /* end of BPWM register group */
/*---------------------- Quadrature Encoder Interface -------------------------*/
/**
@addtogroup QEI Quadrature Encoder Interface(QEI)
Memory Mapped Structure for QEI Controller
@{ */
typedef struct {
/**
* @var QEI_T::CNT
* Offset: 0x00 QEI Counter Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |CNT |Quadrature Encoder Interface Counter
* | | |A 32-bit up/down counter
* | | |When an effective phase pulse is detected, this counter is increased by one if the bit DIRF (QEI_STATUS[8]) is one or decreased by one if the bit DIRF(QEI_STATUS[8]) is zero
* | | |This register performs an integrator which count value is proportional to the encoder position
* | | |The pulse counter may be initialized to a predetermined value by one of three events occurs:
* | | |1. Software is written if QEIEN (QEI_CTL[29]) = 0.
* | | |2. Compare-match event if QEIEN(QEI_CTL[29])=1 and QEI is in compare-counting mode.
* | | |3. Index signal change if QEIEN(QEI_CTL[29])=1 and IDXRLDEN (QEI_CTL[27])=1.
* @var QEI_T::CNTHOLD
* Offset: 0x04 QEI Counter Hold Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |CNTHOLD |Quadrature Encoder Interface Counter Hold
* | | |When bit HOLDCNT (QEI_CTL[24]) goes from low to high, the CNT(QEI_CNT[31:0]) is copied into CNTHOLD (QEI_CNTHOLD[31:0]) register.
* @var QEI_T::CNTLATCH
* Offset: 0x08 QEI Counter Index Latch Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |CNTLATCH |Quadrature Encoder Interface Counter Index Latch
* | | |When the IDXF (QEI_STATUS[0]) bit is set, the CNT(QEI_CNT[31:0]) is copied into CNTLATCH (QEI_CNTLATCH[31:0]) register.
* @var QEI_T::CNTCMP
* Offset: 0x0C QEI Counter Compare Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |CNTCMP |Quadrature Encoder Interface Counter Compare
* | | |If the QEI controller is in the compare-counting mode CMPEN (QEI_CTL[28]) =1, when the value of CNT(QEI_CNT[31:0]) matches CNTCMP(QEI_CNTCMP[31:0]), CMPF will be set
* | | |This register is software writable.
* @var QEI_T::CNTMAX
* Offset: 0x14 QEI Pre-set Maximum Count Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |CNTMAX |Quadrature Encoder Interface Preset Maximum Count
* | | |This register value determined by user stores the maximum value which may be the number of the QEI counter for the QEI controller compare-counting mode
* @var QEI_T::CTL
* Offset: 0x18 QEI Controller Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[2:0] |NFCLKSEL |Noise Filter Clock Pre-divide Selection
* | | |To determine the sampling frequency of the Noise Filter clock .
* | | |000 = QEI_CLK.
* | | |001 = QEI_CLK/2.
* | | |010 = QEI_CLK/4.
* | | |011 = QEI_CLK/16.
* | | |100 = QEI_CLK/32.
* | | |101 = QEI_CLK/64.
* |[3] |NFDIS |QEI Controller Input Noise Filter Disable Bit
* | | |0 = The noise filter of QEI controller Enabled.
* | | |1 = The noise filter of QEI controller Disabled.
* |[4] |CHAEN |QEA Input to QEI Controller Enable Bit
* | | |0 = QEA input to QEI Controller Disabled.
* | | |1 = QEA input to QEI Controller Enabled.
* |[5] |CHBEN |QEB Input to QEI Controller Enable Bit
* | | |0 = QEB input to QEI Controller Disabled.
* | | |1 = QEB input to QEI Controller Enabled.
* |[6] |IDXEN |IDX Input to QEI Controller Enable Bit
* | | |0 = IDX input to QEI Controller Disabled.
* | | |1 = IDX input to QEI Controller Enabled.
* |[9:8] |MODE |QEI Counting Mode Selection
* | | |There are four quadrature encoder pulse counter operation modes.
* | | |00 = X4 Free-counting Mode.
* | | |01 = X2 Free-counting Mode.
* | | |10 = X4 Compare-counting Mode.
* | | |11 = X2 Compare-counting Mode.
* |[12] |CHAINV |Inverse QEA Input Polarity
* | | |0 = Not inverse QEA input polarity.
* | | |1 = QEA input polarity is inversed to QEI controller.
* |[13] |CHBINV |Inverse QEB Input Polarity
* | | |0 = Not inverse QEB input polarity.
* | | |1 = QEB input polarity is inversed to QEI controller.
* |[14] |IDXINV |Inverse IDX Input Polarity
* | | |0 = Not inverse IDX input polarity.
* | | |1 = IDX input polarity is inversed to QEI controller.
* |[16] |OVUNIEN |OVUNF Trigger QEI Interrupt Enable Bit
* | | |0 = OVUNF can trigger QEI controller interrupt Disabled.
* | | |1 = OVUNF can trigger QEI controller interrupt Enabled.
* |[17] |DIRIEN |DIRCHGF Trigger QEI Interrupt Enable Bit
* | | |0 = DIRCHGF can trigger QEI controller interrupt Disabled.
* | | |1 = DIRCHGF can trigger QEI controller interrupt Enabled.
* |[18] |CMPIEN |CMPF Trigger QEI Interrupt Enable Bit
* | | |0 = CMPF can trigger QEI controller interrupt Disabled.
* | | |1 = CMPF can trigger QEI controller interrupt Enabled.
* |[19] |IDXIEN |IDXF Trigger QEI Interrupt Enable Bit
* | | |0 = The IDXF can trigger QEI interrupt Disabled.
* | | |1 = The IDXF can trigger QEI interrupt Enabled.
* |[20] |HOLDTMR0 |Hold QEI_CNT by Timer 0
* | | |0 = TIF (TIMER0_INTSTS[0]) has no effect on HOLDCNT.
* | | |1 = A rising edge of bit TIF(TIMER0_INTSTS[0]) in timer 0 sets HOLDCNT to 1.
* |[21] |HOLDTMR1 |Hold QEI_CNT by Timer 1
* | | |0 = TIF(TIMER1_INTSTS[0]) has no effect on HOLDCNT.
* | | |1 = A rising edge of bit TIF (TIMER1_INTSTS[0]) in timer 1 sets HOLDCNT to 1.
* |[22] |HOLDTMR2 |Hold QEI_CNT by Timer 2
* | | |0 = TIF(TIMER2_INTSTS[0]) has no effect on HOLDCNT.
* | | |1 = A rising edge of bit TIF(TIMER2_INTSTS[0]) in timer 2 sets HOLDCNT to 1.
* |[23] |HOLDTMR3 |Hold QEI_CNT by Timer 3
* | | |0 = TIF (TIMER3_INTSTS[0]) has no effect on HOLDCNT.
* | | |1 = A rising edge of bit TIF(TIMER3_INTSTS[0]) in timer 3 sets HOLDCNT to 1.
* |[24] |HOLDCNT |Hold QEI_CNT Control
* | | |When this bit is set from low to high, the CNT(QEI_CNT[31:0]) is copied into CNTHOLD(QEI_CNTHOLD[31:0])
* | | |This bit may be set by writing 1 to it or Timer0~Timer3 interrupt flag TIF (TIMERx_INTSTS[0]).
* | | |0 = No operation.
* | | |1 = QEI_CNT content is captured and stored in CNTHOLD(QEI_CNTHOLD[31:0]).
* | | |Note: This bit is automatically cleared after QEI_CNTHOLD holds QEI_CNT value.
* |[25] |IDXLATEN |Index Latch QEI_CNT Enable Bit
* | | |If this bit is set to high, the CNT(QEI_CNT[31:0]) content will be latched into CNTLATCH (QEI_CNTLATCH[31:0]) at every rising on signal CHX.
* | | |0 = The index signal latch QEI counter function Disabled.
* | | |1 = The index signal latch QEI counter function Enabled.
* |[27] |IDXRLDEN |Index Trigger QEI_CNT Reload Enable Bit
* | | |When this bit is high and a rising edge comes on signal CHX, the CNT(QEI_CNT[31:0]) will be reset to zero if the counter is in up-counting type (DIRF(QEI_STATUS[8]) = 1); while the CNT(QEI_CNT[31:0]) will be reloaded with CNTMAX (QEI_CNTMAX[31:0]) content if the counter is in down-counting type (DIRF(QEI_STATUS[8]) = 0).
* | | |0 = Reload function Disabled.
* | | |1 = QEI_CNT re-initialized by Index signal Enabled.
* |[28] |CMPEN |The Compare Function Enable Bit
* | | |The compare function in QEI controller is to compare the dynamic counting QEI_CNT with the compare register CNTCMP( QEI_CNTCMP[31:0]), if CNT(QEI_CNT[31:0]) reaches CNTCMP( QEI_CNTCMP[31:0]), the flag CMPF will be set.
* | | |0 = Compare function Disabled.
* | | |1 = Compare function Enabled.
* |[29] |QEIEN |Quadrature Encoder Interface Controller Enable Bit
* | | |0 = QEI controller function Disabled.
* | | |1 = QEI controller function Enabled.
* @var QEI_T::STATUS
* Offset: 0x2C QEI Controller Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |IDXF |IDX Detected Flag
* | | |When the QEI controller detects a rising edge on signal CHX it will set flag IDXF to high.
* | | |0 = No rising edge detected on signal CHX.
* | | |1 = A rising edge occurs on signal CHX.
* | | |Note: This bit is only cleared by writing 1 to it.
* |[1] |CMPF |Compare-match Flag
* | | |If the QEI compare function is enabled, the flag is set by hardware while QEI counter up or down counts and reach to the CNTCMP(QEI_CNTCMP[31:0]).
* | | |0 = QEI counter does not match with CNTCMP(QEI_CNTCMP[31:0]).
* | | |1 = QEI counter counts to the same as CNTCMP(QEI_CNTCMP[31:0]).
* | | |Note: This bit is only cleared by writing 1 to it.
* |[2] |OVUNF |QEI Counter Overflow or Underflow Flag
* | | |Flag is set by hardware while CNT(QEI_CNT[31:0]) overflows from 0xFFFF_FFFF to zero in free-counting mode or from the CNTMAX (QEI_CNTMAX[31:0]) to zero in compare-counting mode
* | | |Similarly, the flag is set while QEI counter underflows from zero to 0xFFFF_FFFF or CNTMAX (QEI_CNTMAX[31:0]).
* | | |0 = No overflow or underflow occurs in QEI counter.
* | | |1 = QEI counter occurs counting overflow or underflow.
* | | |Note: This bit is only cleared by writing 1 to it.
* |[3] |DIRCHGF |Direction Change Flag
* | | |Flag is set by hardware while QEI counter counting direction is changed.
* | | |Software can clear this bit by writing 1 to it.
* | | |0 = No change in QEI counter counting direction.
* | | |1 = QEI counter counting direction is changed.
* | | |Note: This bit is only cleared by writing 1 to it.
* |[8] |DIRF |QEI Counter Counting Direction Indication
* | | |0 = QEI Counter is in down-counting.
* | | |1 = QEI Counter is in up-counting.
* | | |Note: This bit is set/reset by hardware according to the phase detection between CHA and CHB.
*/
__IO uint32_t CNT; /*!< [0x0000] QEI Counter Register */
__IO uint32_t CNTHOLD; /*!< [0x0004] QEI Counter Hold Register */
__IO uint32_t CNTLATCH; /*!< [0x0008] QEI Counter Index Latch Register */
__IO uint32_t CNTCMP; /*!< [0x000c] QEI Counter Compare Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE0[1];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t CNTMAX; /*!< [0x0014] QEI Pre-set Maximum Count Register */
__IO uint32_t CTL; /*!< [0x0018] QEI Controller Control Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE1[4];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t STATUS; /*!< [0x002c] QEI Controller Status Register */
} QEI_T;
/**
@addtogroup QEI_CONST QEI Bit Field Definition
Constant Definitions for QEI Controller
@{ */
#define QEI_CNT_CNT_Pos (0) /*!< QEI_T::CNT: CNT Position */
#define QEI_CNT_CNT_Msk (0xfffffffful << QEI_CNT_CNT_Pos) /*!< QEI_T::CNT: CNT Mask */
#define QEI_CNTHOLD_CNTHOLD_Pos (0) /*!< QEI_T::CNTHOLD: CNTHOLD Position */
#define QEI_CNTHOLD_CNTHOLD_Msk (0xfffffffful << QEI_CNTHOLD_CNTHOLD_Pos) /*!< QEI_T::CNTHOLD: CNTHOLD Mask */
#define QEI_CNTLATCH_CNTLATCH_Pos (0) /*!< QEI_T::CNTLATCH: CNTLATCH Position */
#define QEI_CNTLATCH_CNTLATCH_Msk (0xfffffffful << QEI_CNTLATCH_CNTLATCH_Pos) /*!< QEI_T::CNTLATCH: CNTLATCH Mask */
#define QEI_CNTCMP_CNTCMP_Pos (0) /*!< QEI_T::CNTCMP: CNTCMP Position */
#define QEI_CNTCMP_CNTCMP_Msk (0xfffffffful << QEI_CNTCMP_CNTCMP_Pos) /*!< QEI_T::CNTCMP: CNTCMP Mask */
#define QEI_CNTMAX_CNTMAX_Pos (0) /*!< QEI_T::CNTMAX: CNTMAX Position */
#define QEI_CNTMAX_CNTMAX_Msk (0xfffffffful << QEI_CNTMAX_CNTMAX_Pos) /*!< QEI_T::CNTMAX: CNTMAX Mask */
#define QEI_CTL_NFCLKSEL_Pos (0) /*!< QEI_T::CTL: NFCLKSEL Position */
#define QEI_CTL_NFCLKSEL_Msk (0x7ul << QEI_CTL_NFCLKSEL_Pos) /*!< QEI_T::CTL: NFCLKSEL Mask */
#define QEI_CTL_NFDIS_Pos (3) /*!< QEI_T::CTL: NFDIS Position */
#define QEI_CTL_NFDIS_Msk (0x1ul << QEI_CTL_NFDIS_Pos) /*!< QEI_T::CTL: NFDIS Mask */
#define QEI_CTL_CHAEN_Pos (4) /*!< QEI_T::CTL: CHAEN Position */
#define QEI_CTL_CHAEN_Msk (0x1ul << QEI_CTL_CHAEN_Pos) /*!< QEI_T::CTL: CHAEN Mask */
#define QEI_CTL_CHBEN_Pos (5) /*!< QEI_T::CTL: CHBEN Position */
#define QEI_CTL_CHBEN_Msk (0x1ul << QEI_CTL_CHBEN_Pos) /*!< QEI_T::CTL: CHBEN Mask */
#define QEI_CTL_IDXEN_Pos (6) /*!< QEI_T::CTL: IDXEN Position */
#define QEI_CTL_IDXEN_Msk (0x1ul << QEI_CTL_IDXEN_Pos) /*!< QEI_T::CTL: IDXEN Mask */
#define QEI_CTL_MODE_Pos (8) /*!< QEI_T::CTL: MODE Position */
#define QEI_CTL_MODE_Msk (0x3ul << QEI_CTL_MODE_Pos) /*!< QEI_T::CTL: MODE Mask */
#define QEI_CTL_CHAINV_Pos (12) /*!< QEI_T::CTL: CHAINV Position */
#define QEI_CTL_CHAINV_Msk (0x1ul << QEI_CTL_CHAINV_Pos) /*!< QEI_T::CTL: CHAINV Mask */
#define QEI_CTL_CHBINV_Pos (13) /*!< QEI_T::CTL: CHBINV Position */
#define QEI_CTL_CHBINV_Msk (0x1ul << QEI_CTL_CHBINV_Pos) /*!< QEI_T::CTL: CHBINV Mask */
#define QEI_CTL_IDXINV_Pos (14) /*!< QEI_T::CTL: IDXINV Position */
#define QEI_CTL_IDXINV_Msk (0x1ul << QEI_CTL_IDXINV_Pos) /*!< QEI_T::CTL: IDXINV Mask */
#define QEI_CTL_OVUNIEN_Pos (16) /*!< QEI_T::CTL: OVUNIEN Position */
#define QEI_CTL_OVUNIEN_Msk (0x1ul << QEI_CTL_OVUNIEN_Pos) /*!< QEI_T::CTL: OVUNIEN Mask */
#define QEI_CTL_DIRIEN_Pos (17) /*!< QEI_T::CTL: DIRIEN Position */
#define QEI_CTL_DIRIEN_Msk (0x1ul << QEI_CTL_DIRIEN_Pos) /*!< QEI_T::CTL: DIRIEN Mask */
#define QEI_CTL_CMPIEN_Pos (18) /*!< QEI_T::CTL: CMPIEN Position */
#define QEI_CTL_CMPIEN_Msk (0x1ul << QEI_CTL_CMPIEN_Pos) /*!< QEI_T::CTL: CMPIEN Mask */
#define QEI_CTL_IDXIEN_Pos (19) /*!< QEI_T::CTL: IDXIEN Position */
#define QEI_CTL_IDXIEN_Msk (0x1ul << QEI_CTL_IDXIEN_Pos) /*!< QEI_T::CTL: IDXIEN Mask */
#define QEI_CTL_HOLDTMR0_Pos (20) /*!< QEI_T::CTL: HOLDTMR0 Position */
#define QEI_CTL_HOLDTMR0_Msk (0x1ul << QEI_CTL_HOLDTMR0_Pos) /*!< QEI_T::CTL: HOLDTMR0 Mask */
#define QEI_CTL_HOLDTMR1_Pos (21) /*!< QEI_T::CTL: HOLDTMR1 Position */
#define QEI_CTL_HOLDTMR1_Msk (0x1ul << QEI_CTL_HOLDTMR1_Pos) /*!< QEI_T::CTL: HOLDTMR1 Mask */
#define QEI_CTL_HOLDTMR2_Pos (22) /*!< QEI_T::CTL: HOLDTMR2 Position */
#define QEI_CTL_HOLDTMR2_Msk (0x1ul << QEI_CTL_HOLDTMR2_Pos) /*!< QEI_T::CTL: HOLDTMR2 Mask */
#define QEI_CTL_HOLDTMR3_Pos (23) /*!< QEI_T::CTL: HOLDTMR3 Position */
#define QEI_CTL_HOLDTMR3_Msk (0x1ul << QEI_CTL_HOLDTMR3_Pos) /*!< QEI_T::CTL: HOLDTMR3 Mask */
#define QEI_CTL_HOLDCNT_Pos (24) /*!< QEI_T::CTL: HOLDCNT Position */
#define QEI_CTL_HOLDCNT_Msk (0x1ul << QEI_CTL_HOLDCNT_Pos) /*!< QEI_T::CTL: HOLDCNT Mask */
#define QEI_CTL_IDXLATEN_Pos (25) /*!< QEI_T::CTL: IDXLATEN Position */
#define QEI_CTL_IDXLATEN_Msk (0x1ul << QEI_CTL_IDXLATEN_Pos) /*!< QEI_T::CTL: IDXLATEN Mask */
#define QEI_CTL_IDXRLDEN_Pos (27) /*!< QEI_T::CTL: IDXRLDEN Position */
#define QEI_CTL_IDXRLDEN_Msk (0x1ul << QEI_CTL_IDXRLDEN_Pos) /*!< QEI_T::CTL: IDXRLDEN Mask */
#define QEI_CTL_CMPEN_Pos (28) /*!< QEI_T::CTL: CMPEN Position */
#define QEI_CTL_CMPEN_Msk (0x1ul << QEI_CTL_CMPEN_Pos) /*!< QEI_T::CTL: CMPEN Mask */
#define QEI_CTL_QEIEN_Pos (29) /*!< QEI_T::CTL: QEIEN Position */
#define QEI_CTL_QEIEN_Msk (0x1ul << QEI_CTL_QEIEN_Pos) /*!< QEI_T::CTL: QEIEN Mask */
#define QEI_STATUS_IDXF_Pos (0) /*!< QEI_T::STATUS: IDXF Position */
#define QEI_STATUS_IDXF_Msk (0x1ul << QEI_STATUS_IDXF_Pos) /*!< QEI_T::STATUS: IDXF Mask */
#define QEI_STATUS_CMPF_Pos (1) /*!< QEI_T::STATUS: CMPF Position */
#define QEI_STATUS_CMPF_Msk (0x1ul << QEI_STATUS_CMPF_Pos) /*!< QEI_T::STATUS: CMPF Mask */
#define QEI_STATUS_OVUNF_Pos (2) /*!< QEI_T::STATUS: OVUNF Position */
#define QEI_STATUS_OVUNF_Msk (0x1ul << QEI_STATUS_OVUNF_Pos) /*!< QEI_T::STATUS: OVUNF Mask */
#define QEI_STATUS_DIRCHGF_Pos (3) /*!< QEI_T::STATUS: DIRCHGF Position */
#define QEI_STATUS_DIRCHGF_Msk (0x1ul << QEI_STATUS_DIRCHGF_Pos) /*!< QEI_T::STATUS: DIRCHGF Mask */
#define QEI_STATUS_DIRF_Pos (8) /*!< QEI_T::STATUS: DIRF Position */
#define QEI_STATUS_DIRF_Msk (0x1ul << QEI_STATUS_DIRF_Pos) /*!< QEI_T::STATUS: DIRF Mask */
/**@}*/ /* QEI_CONST */
/**@}*/ /* end of QEI register group */
/*---------------------- Enhanced Input Capture Timer -------------------------*/
/**
@addtogroup ECAP Enhanced Input Capture Timer(ECAP)
Memory Mapped Structure for ECAP Controller
@{ */
typedef struct {
/**
* @var ECAP_T::CNT
* Offset: 0x00 Input Capture Counter (24-bit up counter)
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[23:0] |CNT |Input Capture Timer/Counter
* | | |The input Capture Timer/Counter is a 24-bit up-counting counter
* | | |The clock source for the counter is from the clock divider
* @var ECAP_T::HLD0
* Offset: 0x04 Input Capture Hold Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[23:0] |HOLD |Input Capture Counter Hold Register
* | | |When an active input capture channel detects a valid edge signal change, the ECAPCNT value is latched into the corresponding holding register
* | | |Each input channel has its own holding register named by ECAP_HLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively.
* @var ECAP_T::HLD1
* Offset: 0x08 Input Capture Hold Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[23:0] |HOLD |Input Capture Counter Hold Register
* | | |When an active input capture channel detects a valid edge signal change, the ECAPCNT value is latched into the corresponding holding register
* | | |Each input channel has its own holding register named by ECAP_HLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively.
* @var ECAP_T::HLD2
* Offset: 0x0C Input Capture Hold Register 2
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[23:0] |HOLD |Input Capture Counter Hold Register
* | | |When an active input capture channel detects a valid edge signal change, the ECAPCNT value is latched into the corresponding holding register
* | | |Each input channel has its own holding register named by ECAP_HLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively.
* @var ECAP_T::CNTCMP
* Offset: 0x10 Input Capture Compare Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[23:0] |CNTCMP |Input Capture Counter Compare Register
* | | |If the compare function is enabled (CMPEN = 1), this register (ECAP_CNTCMP) is used to compare with the capture counter (ECAP_CNT).
* | | |If the reload control is enabled (RLDEN[n] = 1, n=0~3), an overflow event or capture events will trigger the hardware to load the value of this register (ECAP_CNTCMP) into ECAP_CNT.
* @var ECAP_T::CTL0
* Offset: 0x14 Input Capture Control Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[2:0] |NFCLKSEL |Noise Filter Clock Pre-divide Selection
* | | |To determine the sampling frequency of the Noise Filter clock
* | | |000 = CAP_CLK.
* | | |001 = CAP_CLK/2.
* | | |010 = CAP_CLK/4.
* | | |011 = CAP_CLK/16.
* | | |100 = CAP_CLK/32.
* | | |101 = CAP_CLK/64.
* |[3] |CAPNFDIS |Input Capture Noise Filter Disable Control
* | | |0 = Noise filter of Input Capture Enabled.
* | | |1 = Noise filter of Input Capture Disabled (Bypass).
* |[4] |IC0EN |Port Pin IC0 Input to Input Capture Unit Enable Control
* | | |0 = IC0 input to Input Capture Unit Disabled.
* | | |1 = IC0 input to Input Capture Unit Enabled.
* |[5] |IC1EN |Port Pin IC1 Input to Input Capture Unit Enable Control
* | | |0 = IC1 input to Input Capture Unit Disabled.
* | | |1 = IC1 input to Input Capture Unit Enabled.
* |[6] |IC2EN |Port Pin IC2 Input to Input Capture Unit Enable Control
* | | |0 = IC2 input to Input Capture Unit Disabled.
* | | |1 = IC2 input to Input Capture Unit Enabled.
* |[9:8] |CAPSEL0 |CAP0 Input Source Selection
* | | |00 = CAP0 input is from port pin ICAP0.
* | | |01 = Reserved.
* | | |10 = CAP0 input is from signal CHA of QEI controller unit n.
* | | |11 = Reserved.
* | | |Note: Input capture unit n matches QEIn, where n = 0~1.
* |[11:10] |CAPSEL1 |CAP1 Input Source Selection
* | | |00 = CAP1 input is from port pin ICAP1.
* | | |01 = Reserved.
* | | |10 = CAP1 input is from signal CHB of QEI controller unit n.
* | | |11 = Reserved.
* | | |Note: Input capture unit n matches QEIn, where n = 0~1.
* |[13:12] |CAPSEL2 |CAP2 Input Source Selection
* | | |00 = CAP2 input is from port pin ICAP2.
* | | |01 = Reserved.
* | | |10 = CAP2 input is from signal CHX of QEI controller unit n.
* | | |11 = Reserved.
* | | |Note: Input capture unit n matches QEIn, where n = 0~1.
* |[16] |CAPIEN0 |Input Capture Channel 0 Interrupt Enable Control
* | | |0 = The flag CAPTF0 can trigger Input Capture interrupt Disabled.
* | | |1 = The flag CAPTF0 can trigger Input Capture interrupt Enabled.
* |[17] |CAPIEN1 |Input Capture Channel 1 Interrupt Enable Control
* | | |0 = The flag CAPTF1 can trigger Input Capture interrupt Disabled.
* | | |1 = The flag CAPTF1 can trigger Input Capture interrupt Enabled.
* |[18] |CAPIEN2 |Input Capture Channel 2 Interrupt Enable Control
* | | |0 = The flag CAPTF2 can trigger Input Capture interrupt Disabled.
* | | |1 = The flag CAPTF2 can trigger Input Capture interrupt Enabled.
* |[20] |OVIEN |CAPOVF Trigger Input Capture Interrupt Enable Control
* | | |0 = The flag CAPOVF can trigger Input Capture interrupt Disabled.
* | | |1 = The flag CAPOVF can trigger Input Capture interrupt Enabled.
* |[21] |CMPIEN |CAPCMPF Trigger Input Capture Interrupt Enable Control
* | | |0 = The flag CAPCMPF can trigger Input Capture interrupt Disabled.
* | | |1 = The flag CAPCMPF can trigger Input Capture interrupt Enabled.
* |[24] |CNTEN |Input Capture Counter Start Counting Control
* | | |Setting this bit to 1, the capture counter (ECAP_CNT) starts up-counting synchronously with the clock from the .
* | | |0 = ECAP_CNT stop counting.
* | | |1 = ECAP_CNT starts up-counting.
* |[25] |CMPCLREN |Input Capture Counter Cleared by Compare-match Control
* | | |If this bit is set to 1, the capture counter (ECAP_CNT) will be cleared to 0 when the compare-match event (CAPCMPF = 1) occurs.
* | | |0 = Compare-match event (CAPCMPF) can clear capture counter (ECAP_CNT) Disabled.
* | | |1 = Compare-match event (CAPCMPF) can clear capture counter (ECAP_CNT) Enabled.
* |[28] |CMPEN |Compare Function Enable Control
* | | |The compare function in input capture timer/counter is to compare the dynamic counting ECAP_CNT with the compare register ECAP_CNTCMP, if ECAP_CNT value reaches ECAP_CNTCMP, the flag CAPCMPF will be set.
* | | |0 = The compare function Disabled.
* | | |1 = The compare function Enabled.
* |[29] |CAPEN |Input Capture Timer/Counter Enable Control
* | | |0 = Input Capture function Disabled.
* | | |1 = Input Capture function Enabled.
* @var ECAP_T::CTL1
* Offset: 0x18 Input Capture Control Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1:0] |EDGESEL0 |Channel 0 Captured Edge Selection
* | | |Input capture0 can detect falling edge change only, rising edge change only or both edge change
* | | |00 = Detect rising edge only.
* | | |01 = Detect falling edge only.
* | | |1x = Detect both rising and falling edge.
* |[3:2] |EDGESEL1 |Channel 1 Captured Edge Selection
* | | |Input capture1 can detect falling edge change only, rising edge change only or both edge change
* | | |00 = Detect rising edge only.
* | | |01 = Detect falling edge only.
* | | |1x = Detect both rising and falling edge.
* |[5:4] |EDGESEL2 |Channel 2 Captured Edge Selection
* | | |Input capture2 can detect falling edge change only, rising edge change only or both edge changes
* | | |00 = Detect rising edge only.
* | | |01 = Detect falling edge only.
* | | |1x = Detect both rising and falling edge.
* |[8] |CAP0RLDEN |Capture Counteru2019s Reload Function Triggered by Event CAPTE0 Enable Bit
* | | |0 = The reload triggered by Event CAPTE0 Disabled.
* | | |1 = The reload triggered by Event CAPTE0 Enabled.
* |[9] |CAP1RLDEN |Capture Counteru2019s Reload Function Triggered by Event CAPTE1 Enable Bit
* | | |0 = The reload triggered by Event CAPTE1 Disabled.
* | | |1 = The reload triggered by Event CAPTE1 Enabled.
* |[10] |CAP2RLDEN |Capture Counteru2019s Reload Function Triggered by Event CAPTE2 Enable Bit
* | | |0 = The reload triggered by Event CAPTE2 Disabled.
* | | |1 = The reload triggered by Event CAPTE2 Enabled.
* |[11] |OVRLDEN |Capture Counteru2019s Reload Function Triggered by Overflow Enable Bit
* | | |0 = The reload triggered by CAPOV Disabled.
* | | |1 = The reload triggered by CAPOV Enabled.
* |[14:12] |CLKSEL |Capture Timer Clock Divide Selection
* | | |The capture timer clock has a pre-divider with eight divided options controlled by CLKSEL[2:0].
* | | |000 = CAP_CLK/1.
* | | |001 = CAP_CLK/4.
* | | |010 = CAP_CLK/16.
* | | |011 = CAP_CLK/32.
* | | |100 = CAP_CLK/64.
* | | |101 = CAP_CLK/96.
* | | |110 = CAP_CLK/112.
* | | |111 = CAP_CLK/128.
* |[17:16] |CNTSRCSEL |Capture Timer/Counter Clock Source Selection
* | | |Select the capture timer/counter clock source.
* | | |00 = CAP_CLK (default).
* | | |01 = CAP0.
* | | |10 = CAP1.
* | | |11 = CAP2.
* |[20] |CAP0CLREN |Capture Counter Cleared by Capture Event0 Control
* | | |0 = Event CAPTE0 can clear capture counter (ECAP_CNT) Disabled.
* | | |1 = Event CAPTE0 can clear capture counter (ECAP_CNT) Enabled.
* |[21] |CAP1CLREN |Capture Counter Cleared by Capture Event1 Control
* | | |0 = Event CAPTE1 can clear capture counter (ECAP_CNT) Disabled.
* | | |1 = Event CAPTE1 can clear capture counter (ECAP_CNT) Enabled.
* |[22] |CAP2CLREN |Capture Counter Cleared by Capture Event2 Control
* | | |0 = Event CAPTE2 can clear capture counter (ECAP_CNT) Disabled.
* | | |1 = Event CAPTE2 can clear capture counter (ECAP_CNT) Enabled.
* @var ECAP_T::STATUS
* Offset: 0x1C Input Capture Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CAPTF0 |Input Capture Channel 0 Triggered Flag
* | | |When the input capture channel 0 detects a valid edge change at CAP0 input, it will set flag CAPTF0 to high.
* | | |0 = No valid edge change has been detected at CAP0 input since last clear.
* | | |1 = At least a valid edge change has been detected at CAP0 input since last clear.
* | | |Note: This bit is only cleared by writing 1 to it.
* |[1] |CAPTF1 |Input Capture Channel 1 Triggered Flag
* | | |When the input capture channel 1 detects a valid edge change at CAP1 input, it will set flag CAPTF1 to high.
* | | |0 = No valid edge change has been detected at CAP1 input since last clear.
* | | |1 = At least a valid edge change has been detected at CAP1 input since last clear.
* | | |Note: This bit is only cleared by writing 1 to it.
* |[2] |CAPTF2 |Input Capture Channel 2 Triggered Flag
* | | |When the input capture channel 2 detects a valid edge change at CAP2 input, it will set flag CAPTF2 to high.
* | | |0 = No valid edge change has been detected at CAP2 input since last clear.
* | | |1 = At least a valid edge change has been detected at CAP2 input since last clear.
* | | |Note: This bit is only cleared by writing 1 to it.
* |[4] |CAPCMPF |Input Capture Compare-match Flag
* | | |If the input capture compare function is enabled, the flag is set by hardware when capture counter (ECAP_CNT) up counts and reaches the ECAP_CNTCMP value.
* | | |0 = ECAP_CNT has not matched ECAP_CNTCMP value since last clear.
* | | |1 = ECAP_CNT has matched ECAP_CNTCMP value at least once since last clear.
* | | |Note: This bit is only cleared by writing 1 to it.
* |[5] |CAPOVF |Input Capture Counter Overflow Flag
* | | |Flag is set by hardware when counter (ECAP_CNT) overflows from 0x00FF_FFFF to zero.
* | | |0 = No overflow event has occurred since last clear.
* | | |1 = Overflow event(s) has/have occurred since last clear.
* | | |Note: This bit is only cleared by writing 1 to it.
* |[6] |CAP0 |Value of Input Channel 0, CAP0 (Read Only)
* | | |Reflecting the value of input channel 0, CAP0
* | | |(The bit is read only and write is ignored)
* |[7] |CAP1 |Value of Input Channel 1, CAP1 (Read Only)
* | | |Reflecting the value of input channel 1, CAP1
* | | |(The bit is read only and write is ignored)
* |[8] |CAP2 |Value of Input Channel 2, CAP2 (Read Only)
* | | |Reflecting the value of input channel 2, CAP2.
* | | |(The bit is read only and write is ignored)
*/
__IO uint32_t CNT; /*!< [0x0000] Input Capture Counter */
__IO uint32_t HLD0; /*!< [0x0004] Input Capture Hold Register 0 */
__IO uint32_t HLD1; /*!< [0x0008] Input Capture Hold Register 1 */
__IO uint32_t HLD2; /*!< [0x000c] Input Capture Hold Register 2 */
__IO uint32_t CNTCMP; /*!< [0x0010] Input Capture Compare Register */
__IO uint32_t CTL0; /*!< [0x0014] Input Capture Control Register 0 */
__IO uint32_t CTL1; /*!< [0x0018] Input Capture Control Register 1 */
__IO uint32_t STATUS; /*!< [0x001c] Input Capture Status Register */
} ECAP_T;
/**
@addtogroup ECAP_CONST ECAP Bit Field Definition
Constant Definitions for ECAP Controller
@{ */
#define ECAP_CNT_CNT_Pos (0) /*!< ECAP_T::CNT: CNT Position */
#define ECAP_CNT_CNT_Msk (0xfffffful << ECAP_CNT_CNT_Pos) /*!< ECAP_T::CNT: CNT Mask */
#define ECAP_HLD0_HOLD_Pos (0) /*!< ECAP_T::HLD0: HOLD Position */
#define ECAP_HLD0_HOLD_Msk (0xfffffful << ECAP_HLD0_HOLD_Pos) /*!< ECAP_T::HLD0: HOLD Mask */
#define ECAP_HLD1_HOLD_Pos (0) /*!< ECAP_T::HLD1: HOLD Position */
#define ECAP_HLD1_HOLD_Msk (0xfffffful << ECAP_HLD1_HOLD_Pos) /*!< ECAP_T::HLD1: HOLD Mask */
#define ECAP_HLD2_HOLD_Pos (0) /*!< ECAP_T::HLD2: HOLD Position */
#define ECAP_HLD2_HOLD_Msk (0xfffffful << ECAP_HLD2_HOLD_Pos) /*!< ECAP_T::HLD2: HOLD Mask */
#define ECAP_CNTCMP_CNTCMP_Pos (0) /*!< ECAP_T::CNTCMP: CNTCMP Position */
#define ECAP_CNTCMP_CNTCMP_Msk (0xfffffful << ECAP_CNTCMP_CNTCMP_Pos) /*!< ECAP_T::CNTCMP: CNTCMP Mask */
#define ECAP_CTL0_NFCLKSEL_Pos (0) /*!< ECAP_T::CTL0: NFCLKSEL Position */
#define ECAP_CTL0_NFCLKSEL_Msk (0x7ul << ECAP_CTL0_NFCLKSEL_Pos) /*!< ECAP_T::CTL0: NFCLKSEL Mask */
#define ECAP_CTL0_CAPNFDIS_Pos (3) /*!< ECAP_T::CTL0: CAPNFDIS Position */
#define ECAP_CTL0_CAPNFDIS_Msk (0x1ul << ECAP_CTL0_CAPNFDIS_Pos) /*!< ECAP_T::CTL0: CAPNFDIS Mask */
#define ECAP_CTL0_IC0EN_Pos (4) /*!< ECAP_T::CTL0: IC0EN Position */
#define ECAP_CTL0_IC0EN_Msk (0x1ul << ECAP_CTL0_IC0EN_Pos) /*!< ECAP_T::CTL0: IC0EN Mask */
#define ECAP_CTL0_IC1EN_Pos (5) /*!< ECAP_T::CTL0: IC1EN Position */
#define ECAP_CTL0_IC1EN_Msk (0x1ul << ECAP_CTL0_IC1EN_Pos) /*!< ECAP_T::CTL0: IC1EN Mask */
#define ECAP_CTL0_IC2EN_Pos (6) /*!< ECAP_T::CTL0: IC2EN Position */
#define ECAP_CTL0_IC2EN_Msk (0x1ul << ECAP_CTL0_IC2EN_Pos) /*!< ECAP_T::CTL0: IC2EN Mask */
#define ECAP_CTL0_CAPSEL0_Pos (8) /*!< ECAP_T::CTL0: CAPSEL0 Position */
#define ECAP_CTL0_CAPSEL0_Msk (0x3ul << ECAP_CTL0_CAPSEL0_Pos) /*!< ECAP_T::CTL0: CAPSEL0 Mask */
#define ECAP_CTL0_CAPSEL1_Pos (10) /*!< ECAP_T::CTL0: CAPSEL1 Position */
#define ECAP_CTL0_CAPSEL1_Msk (0x3ul << ECAP_CTL0_CAPSEL1_Pos) /*!< ECAP_T::CTL0: CAPSEL1 Mask */
#define ECAP_CTL0_CAPSEL2_Pos (12) /*!< ECAP_T::CTL0: CAPSEL2 Position */
#define ECAP_CTL0_CAPSEL2_Msk (0x3ul << ECAP_CTL0_CAPSEL2_Pos) /*!< ECAP_T::CTL0: CAPSEL2 Mask */
#define ECAP_CTL0_CAPIEN0_Pos (16) /*!< ECAP_T::CTL0: CAPIEN0 Position */
#define ECAP_CTL0_CAPIEN0_Msk (0x1ul << ECAP_CTL0_CAPIEN0_Pos) /*!< ECAP_T::CTL0: CAPIEN0 Mask */
#define ECAP_CTL0_CAPIEN1_Pos (17) /*!< ECAP_T::CTL0: CAPIEN1 Position */
#define ECAP_CTL0_CAPIEN1_Msk (0x1ul << ECAP_CTL0_CAPIEN1_Pos) /*!< ECAP_T::CTL0: CAPIEN1 Mask */
#define ECAP_CTL0_CAPIEN2_Pos (18) /*!< ECAP_T::CTL0: CAPIEN2 Position */
#define ECAP_CTL0_CAPIEN2_Msk (0x1ul << ECAP_CTL0_CAPIEN2_Pos) /*!< ECAP_T::CTL0: CAPIEN2 Mask */
#define ECAP_CTL0_OVIEN_Pos (20) /*!< ECAP_T::CTL0: OVIEN Position */
#define ECAP_CTL0_OVIEN_Msk (0x1ul << ECAP_CTL0_OVIEN_Pos) /*!< ECAP_T::CTL0: OVIEN Mask */
#define ECAP_CTL0_CMPIEN_Pos (21) /*!< ECAP_T::CTL0: CMPIEN Position */
#define ECAP_CTL0_CMPIEN_Msk (0x1ul << ECAP_CTL0_CMPIEN_Pos) /*!< ECAP_T::CTL0: CMPIEN Mask */
#define ECAP_CTL0_CNTEN_Pos (24) /*!< ECAP_T::CTL0: CNTEN Position */
#define ECAP_CTL0_CNTEN_Msk (0x1ul << ECAP_CTL0_CNTEN_Pos) /*!< ECAP_T::CTL0: CNTEN Mask */
#define ECAP_CTL0_CMPCLREN_Pos (25) /*!< ECAP_T::CTL0: CMPCLREN Position */
#define ECAP_CTL0_CMPCLREN_Msk (0x1ul << ECAP_CTL0_CMPCLREN_Pos) /*!< ECAP_T::CTL0: CMPCLREN Mask */
#define ECAP_CTL0_CMPEN_Pos (28) /*!< ECAP_T::CTL0: CMPEN Position */
#define ECAP_CTL0_CMPEN_Msk (0x1ul << ECAP_CTL0_CMPEN_Pos) /*!< ECAP_T::CTL0: CMPEN Mask */
#define ECAP_CTL0_CAPEN_Pos (29) /*!< ECAP_T::CTL0: CAPEN Position */
#define ECAP_CTL0_CAPEN_Msk (0x1ul << ECAP_CTL0_CAPEN_Pos) /*!< ECAP_T::CTL0: CAPEN Mask */
#define ECAP_CTL1_EDGESEL0_Pos (0) /*!< ECAP_T::CTL1: EDGESEL0 Position */
#define ECAP_CTL1_EDGESEL0_Msk (0x3ul << ECAP_CTL1_EDGESEL0_Pos) /*!< ECAP_T::CTL1: EDGESEL0 Mask */
#define ECAP_CTL1_EDGESEL1_Pos (2) /*!< ECAP_T::CTL1: EDGESEL1 Position */
#define ECAP_CTL1_EDGESEL1_Msk (0x3ul << ECAP_CTL1_EDGESEL1_Pos) /*!< ECAP_T::CTL1: EDGESEL1 Mask */
#define ECAP_CTL1_EDGESEL2_Pos (4) /*!< ECAP_T::CTL1: EDGESEL2 Position */
#define ECAP_CTL1_EDGESEL2_Msk (0x3ul << ECAP_CTL1_EDGESEL2_Pos) /*!< ECAP_T::CTL1: EDGESEL2 Mask */
#define ECAP_CTL1_CAP0RLDEN_Pos (8) /*!< ECAP_T::CTL1: CAP0RLDEN Position */
#define ECAP_CTL1_CAP0RLDEN_Msk (0x1ul << ECAP_CTL1_CAP0RLDEN_Pos) /*!< ECAP_T::CTL1: CAP0RLDEN Mask */
#define ECAP_CTL1_CAP1RLDEN_Pos (9) /*!< ECAP_T::CTL1: CAP1RLDEN Position */
#define ECAP_CTL1_CAP1RLDEN_Msk (0x1ul << ECAP_CTL1_CAP1RLDEN_Pos) /*!< ECAP_T::CTL1: CAP1RLDEN Mask */
#define ECAP_CTL1_CAP2RLDEN_Pos (10) /*!< ECAP_T::CTL1: CAP2RLDEN Position */
#define ECAP_CTL1_CAP2RLDEN_Msk (0x1ul << ECAP_CTL1_CAP2RLDEN_Pos) /*!< ECAP_T::CTL1: CAP2RLDEN Mask */
#define ECAP_CTL1_OVRLDEN_Pos (11) /*!< ECAP_T::CTL1: OVRLDEN Position */
#define ECAP_CTL1_OVRLDEN_Msk (0x1ul << ECAP_CTL1_OVRLDEN_Pos) /*!< ECAP_T::CTL1: OVRLDEN Mask */
#define ECAP_CTL1_CLKSEL_Pos (12) /*!< ECAP_T::CTL1: CLKSEL Position */
#define ECAP_CTL1_CLKSEL_Msk (0x7ul << ECAP_CTL1_CLKSEL_Pos) /*!< ECAP_T::CTL1: CLKSEL Mask */
#define ECAP_CTL1_CNTSRCSEL_Pos (16) /*!< ECAP_T::CTL1: CNTSRCSEL Position */
#define ECAP_CTL1_CNTSRCSEL_Msk (0x3ul << ECAP_CTL1_CNTSRCSEL_Pos) /*!< ECAP_T::CTL1: CNTSRCSEL Mask */
#define ECAP_CTL1_CAP0CLREN_Pos (20) /*!< ECAP_T::CTL1: CAP0CLREN Position */
#define ECAP_CTL1_CAP0CLREN_Msk (0x1ul << ECAP_CTL1_CAP0CLREN_Pos) /*!< ECAP_T::CTL1: CAP0CLREN Mask */
#define ECAP_CTL1_CAP1CLREN_Pos (21) /*!< ECAP_T::CTL1: CAP1CLREN Position */
#define ECAP_CTL1_CAP1CLREN_Msk (0x1ul << ECAP_CTL1_CAP1CLREN_Pos) /*!< ECAP_T::CTL1: CAP1CLREN Mask */
#define ECAP_CTL1_CAP2CLREN_Pos (22) /*!< ECAP_T::CTL1: CAP2CLREN Position */
#define ECAP_CTL1_CAP2CLREN_Msk (0x1ul << ECAP_CTL1_CAP2CLREN_Pos) /*!< ECAP_T::CTL1: CAP2CLREN Mask */
#define ECAP_STATUS_CAPTF0_Pos (0) /*!< ECAP_T::STATUS: CAPTF0 Position */
#define ECAP_STATUS_CAPTF0_Msk (0x1ul << ECAP_STATUS_CAPTF0_Pos) /*!< ECAP_T::STATUS: CAPTF0 Mask */
#define ECAP_STATUS_CAPTF1_Pos (1) /*!< ECAP_T::STATUS: CAPTF1 Position */
#define ECAP_STATUS_CAPTF1_Msk (0x1ul << ECAP_STATUS_CAPTF1_Pos) /*!< ECAP_T::STATUS: CAPTF1 Mask */
#define ECAP_STATUS_CAPTF2_Pos (2) /*!< ECAP_T::STATUS: CAPTF2 Position */
#define ECAP_STATUS_CAPTF2_Msk (0x1ul << ECAP_STATUS_CAPTF2_Pos) /*!< ECAP_T::STATUS: CAPTF2 Mask */
#define ECAP_STATUS_CAPCMPF_Pos (4) /*!< ECAP_T::STATUS: CAPCMPF Position */
#define ECAP_STATUS_CAPCMPF_Msk (0x1ul << ECAP_STATUS_CAPCMPF_Pos) /*!< ECAP_T::STATUS: CAPCMPF Mask */
#define ECAP_STATUS_CAPOVF_Pos (5) /*!< ECAP_T::STATUS: CAPOVF Position */
#define ECAP_STATUS_CAPOVF_Msk (0x1ul << ECAP_STATUS_CAPOVF_Pos) /*!< ECAP_T::STATUS: CAPOVF Mask */
#define ECAP_STATUS_CAP0_Pos (6) /*!< ECAP_T::STATUS: CAP0 Position */
#define ECAP_STATUS_CAP0_Msk (0x1ul << ECAP_STATUS_CAP0_Pos) /*!< ECAP_T::STATUS: CAP0 Mask */
#define ECAP_STATUS_CAP1_Pos (7) /*!< ECAP_T::STATUS: CAP1 Position */
#define ECAP_STATUS_CAP1_Msk (0x1ul << ECAP_STATUS_CAP1_Pos) /*!< ECAP_T::STATUS: CAP1 Mask */
#define ECAP_STATUS_CAP2_Pos (8) /*!< ECAP_T::STATUS: CAP2 Position */
#define ECAP_STATUS_CAP2_Msk (0x1ul << ECAP_STATUS_CAP2_Pos) /*!< ECAP_T::STATUS: CAP2 Mask */
/**@}*/ /* ECAP_CONST */
/**@}*/ /* end of ECAP register group */
/*---------------------- Universal Asynchronous Receiver/Transmitter Controller -------------------------*/
/**
@addtogroup UART Universal Asynchronous Receiver/Transmitter Controller(UART)
Memory Mapped Structure for UART Controller
@{ */
typedef struct {
/**
* @var UART_T::DAT
* Offset: 0x00 UART Receive/Transmit Buffer Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |DAT |Data Receive/Transmit Buffer
* | | |Write Operation:
* | | |By writing one byte to this register, the data byte will be stored in transmitter FIFO
* | | |The UART controller will send out the data stored in transmitter FIFO top location through the UART_TXD.
* | | |Read Operation:
* | | |By reading this register, the UART controller will return an 8-bit data received from receiver FIFO.
* |[8] |PARITY |Parity Bit Receive/Transmit Buffer
* | | |Write Operation:
* | | |By writing to this bit, the parity bit will be stored in transmitter FIFO
* | | |If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set,
* | | |the UART controller will send out this bit follow the DAT (UART_DAT[7:0]) through the UART_TXD.
* | | |Read Operation:
* | | |If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are enabled, the parity bit can be read by this bit.
* | | |Note: This bit has effect only when PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set.
* @var UART_T::INTEN
* Offset: 0x04 UART Interrupt Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |RDAIEN |Receive Data Available Interrupt Enable Bit
* | | |0 = Receive data available interrupt Disabled.
* | | |1 = Receive data available interrupt Enabled.
* |[1] |THREIEN |Transmit Holding Register Empty Interrupt Enable Bit
* | | |0 = Transmit holding register empty interrupt Disabled.
* | | |1 = Transmit holding register empty interrupt Enabled.
* |[2] |RLSIEN |Receive Line Status Interrupt Enable Bit
* | | |0 = Receive Line Status interrupt Disabled.
* | | |1 = Receive Line Status interrupt Enabled.
* |[3] |MODEMIEN |Modem Status Interrupt Enable Bit
* | | |0 = Modem status interrupt Disabled.
* | | |1 = Modem status interrupt Enabled.
* |[4] |RXTOIEN |RX Time-out Interrupt Enable Bit
* | | |0 = RX time-out interrupt Disabled.
* | | |1 = RX time-out interrupt Enabled.
* |[5] |BUFERRIEN |Buffer Error Interrupt Enable Bit
* | | |0 = Buffer error interrupt Disabled.
* | | |1 = Buffer error interrupt Enabled.
* |[6] |WKIEN |Wake-up Interrupt Enable Bit
* | | |0 = Wake-up Interrupt Disabled.
* | | |1 = Wake-up Interrupt Enabled.
* |[8] |LINIEN |LIN Bus Interrupt Enable Bit
* | | |0 = LIN bus interrupt Disabled.
* | | |1 = LIN bus interrupt Enabled.
* | | |Note: This bit is used for LIN function mode.
* |[11] |TOCNTEN |Receive Buffer Time-out Counter Enable Bit
* | | |0 = Receive Buffer Time-out counter Disabled.
* | | |1 = Receive Buffer Time-out counter Enabled.
* |[12] |ATORTSEN |nRTS Auto-flow Control Enable Bit
* | | |0 = nRTS auto-flow control Disabled.
* | | |1 = nRTS auto-flow control Enabled.
* | | |Note: When nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]), the UART will de-assert nRTS signal.
* |[13] |ATOCTSEN |nCTS Auto-flow Control Enable Bit
* | | |0 = nCTS auto-flow control Disabled.
* | | |1 = nCTS auto-flow control Enabled.
* | | |Note: When nCTS auto-flow is enabled, the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted).
* |[14] |TXPDMAEN |TX PDMA Enable Bit
* | | |This bit can enable or disable TX PDMA service.
* | | |0 = TX PDMA Disabled.
* | | |1 = TX PDMA Enabled.
* | | |Note: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused
* | | |If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]) , UART PDMA transmit request operation is stop
* | | |Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA transmit request operation continue.
* |[15] |RXPDMAEN |RX PDMA Enable Bit
* | | |This bit can enable or disable RX PDMA service.
* | | |0 = RX PDMA Disabled.
* | | |1 = RX PDMA Enabled.
* | | |Note: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused
* | | |If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]) , UART PDMA receive request operation is stop
* | | |Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA receive request operation continue.
* |[18] |ABRIEN |Auto-baud Rate Interrupt Enable Bit
* | | |0 = Auto-baud rate interrupt Disabled.
* | | |1 = Auto-baud rate interrupt Enabled.
* |[22] |TXENDIEN |Transmitter Empty Interrupt Enable Bit
* | | |If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted).
* | | |0 = Transmitter empty interrupt Disabled.
* | | |1 = Transmitter empty interrupt Enabled.
* @var UART_T::FIFO
* Offset: 0x08 UART FIFO Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1] |RXRST |RX Field Software Reset
* | | |When RXRST (UART_FIFO[1]) is set, all the byte in the receiver FIFO and RX internal state machine are cleared.
* | | |0 = No effect.
* | | |1 = Reset the RX internal state machine and pointers.
* | | |Note1: This bit will automatically clear at least 3 UART peripheral clock cycles.
* | | |Note2: Before setting this bit, it should wait for the RXIDLE (UART_FIFOSTS[29]) be set.
* |[2] |TXRST |TX Field Software Reset
* | | |When TXRST (UART_FIFO[2]) is set, all the byte in the transmit FIFO and TX internal state machine are cleared.
* | | |0 = No effect.
* | | |1 = Reset the TX internal state machine and pointers.
* | | |Note1: This bit will automatically clear at least 3 UART peripheral clock cycles.
* | | |Note2: Before setting this bit, it should wait for the TXEMPTYF (UART_FIFOSTS[28]) be set.
* |[7:4] |RFITL |RX FIFO Interrupt Trigger Level
* | | |When the number of bytes in the receive FIFO equals the RFITL, the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled, and an interrupt will be generated).
* | | |0000 = RX FIFO Interrupt Trigger Level is 1 byte.
* | | |0001 = RX FIFO Interrupt Trigger Level is 4 bytes.
* | | |0010 = RX FIFO Interrupt Trigger Level is 8 bytes.
* | | |0011 = RX FIFO Interrupt Trigger Level is 14 bytes.
* | | |Others = Reserved.
* |[8] |RXOFF |Receiver Disable Bit
* | | |The receiver is disabled or not (set 1 to disable receiver).
* | | |0 = Receiver Enabled.
* | | |1 = Receiver Disabled.
* | | |Note: This bit is used for RS-485 Normal Multi-drop mode
* | | |It should be programmed before RS485NMM (UART_ALTCTL [8]) is programmed.
* |[19:16] |RTSTRGLV |nRTS Trigger Level for Auto-flow Control Use
* | | |0000 = nRTS Trigger Level is 1 byte.
* | | |0001 = nRTS Trigger Level is 4 bytes.
* | | |0010 = nRTS Trigger Level is 8 bytes.
* | | |0011 = nRTS Trigger Level is 14 bytes.
* | | |Others = Reserved.
* | | |Note: This field is used for auto nRTS flow control.
* @var UART_T::LINE
* Offset: 0x0C UART Line Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1:0] |WLS |Word Length Selection
* | | |This field sets UART word length.
* | | |00 = 5 bits.
* | | |01 = 6 bits.
* | | |10 = 7 bits.
* | | |11 = 8 bits.
* |[2] |NSB |Number of 'STOP Bit'
* | | |0 = One 'STOP bit' is generated in the transmitted data.
* | | |1 = When select 5-bit word length, 1.5 'STOP bit' is generated in the transmitted data
* | | |When select 6-, 7- and 8-bit word length, 2 'STOP bit' is generated in the transmitted data.
* |[3] |PBE |Parity Bit Enable Bit
* | | |0 = Parity bit generated Disabled.
* | | |1 = Parity bit generated Enabled.
* | | |Note: Parity bit is generated on each outgoing character and is checked on each incoming data.
* |[4] |EPE |Even Parity Enable Bit
* | | |0 = Odd number of logic '1's is transmitted and checked in each word.
* | | |1 = Even number of logic '1's is transmitted and checked in each word.
* | | |Note: This bit has effect only when PBE (UART_LINE[3]) is set.
* |[5] |SPE |Stick Parity Enable Bit
* | | |0 = Stick parity Disabled.
* | | |1 = Stick parity Enabled.
* | | |Note: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1, the parity bit is transmitted and checked as logic 0
* | | |If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the parity bit is transmitted and checked as 1.
* |[6] |BCB |Break Control Bit
* | | |0 = Break Control Disabled.
* | | |1 = Break Control Enabled.
* | | |Note: When this bit is set to logic 1, the transmitted serial data output (TX) is forced to the Spacing State (logic 0)
* | | |This bit acts only on TX line and has no effect on the transmitter logic.
* |[7] |PSS |Parity Bit Source Selection
* | | |The parity bit can be selected to be generated and checked automatically or by software.
* | | |0 = Parity bit is generated by EPE (UART_LINE[4]) and SPE (UART_LINE[5]) setting and checked automatically.
* | | |1 = Parity bit generated and checked by software.
* | | |Note1: This bit has effect only when PBE (UART_LINE[3]) is set.
* | | |Note2: If PSS is 0, the parity bit is transmitted and checked automatically
* | | |If PSS is 1, the transmitted parity bit value can be determined by writing PARITY (UART_DAT[8]) and the parity bit can be read by reading PARITY (UART_DAT[8]).
* |[8] |TXDINV |TX Data Inverted
* | | |0 = Transmitted data signal inverted Disabled.
* | | |1 = Transmitted data signal inverted Enabled.
* | | |Note1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared
* | | |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
* | | |Note2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select UART, LIN or RS485 function.
* |[9] |RXDINV |RX Data Inverted
* | | |0 = Received data signal inverted Disabled.
* | | |1 = Received data signal inverted Enabled.
* | | |Note1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared
* | | |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
* | | |Note2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select UART, LIN or RS485 function.
* @var UART_T::MODEM
* Offset: 0x10 UART Modem Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1] |RTS |nRTS (Request-to-send) Signal Control
* | | |This bit is direct control internal nRTS signal active or not, and then drive the nRTS pin output with RTSACTLV bit configuration.
* | | |0 = nRTS signal is active.
* | | |1 = nRTS signal is inactive.
* | | |Note1: This nRTS signal control bit is not effective when nRTS auto-flow control is enabled in UART function mode.
* | | |Note2: This nRTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode.
* |[9] |RTSACTLV |nRTS Pin Active Level
* | | |This bit defines the active level state of nRTS pin output.
* | | |0 = nRTS pin output is high level active.
* | | |1 = nRTS pin output is low level active. (Default)
* | | |Note1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared
* | | |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
* |[13] |RTSSTS |nRTS Pin Status (Read Only)
* | | |This bit mirror from nRTS pin output of voltage logic status.
* | | |0 = nRTS pin output is low level voltage logic state.
* | | |1 = nRTS pin output is high level voltage logic state.
* @var UART_T::MODEMSTS
* Offset: 0x14 UART Modem Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CTSDETF |Detect nCTS State Change Flag
* | | |This bit is set whenever nCTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.
* | | |0 = nCTS input has not change state.
* | | |1 = nCTS input has change state.
* | | |Note: This bit can be cleared by writing '1' to it.
* |[4] |CTSSTS |nCTS Pin Status (Read Only)
* | | |This bit mirror from nCTS pin input of voltage logic status.
* | | |0 = nCTS pin input is low level voltage logic state.
* | | |1 = nCTS pin input is high level voltage logic state.
* | | |Note: This bit echoes when UART controller peripheral clock is enabled, and nCTS multi-function port is selected.
* |[8] |CTSACTLV |nCTS Pin Active Level
* | | |This bit defines the active level state of nCTS pin input.
* | | |0 = nCTS pin input is high level active.
* | | |1 = nCTS pin input is low level active. (Default)
* | | |Note: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared
* | | |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
* @var UART_T::FIFOSTS
* Offset: 0x18 UART FIFO Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |RXOVIF |RX Overflow Error Interrupt Flag
* | | |This bit is set when RX FIFO overflow.
* | | |If the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes, this bit will be set.
* | | |0 = RX FIFO is not overflow.
* | | |1 = RX FIFO is overflow.
* | | |Note: This bit can be cleared by writing '1' to it.
* |[1] |ABRDIF |Auto-baud Rate Detect Interrupt Flag
* | | |This bit is set to logic '1' when auto-baud rate detect function is finished.
* | | |0 = Auto-baud rate detect function is not finished.
* | | |1 = Auto-baud rate detect function is finished.
* | | |Note: This bit can be cleared by writing '1' to it.
* |[2] |ABRDTOIF |Auto-baud Rate Detect Time-out Interrupt Flag
* | | |This bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.
* | | |0 = Auto-baud rate counter is underflow.
* | | |1 = Auto-baud rate counter is overflow.
* | | |Note: This bit can be cleared by writing '1' to it.
* |[3] |ADDRDETF |RS-485 Address Byte Detect Flag
* | | |0 = Receiver detects a data that is not an address bit (bit 9 ='0').
* | | |1 = Receiver detects a data that is an address bit (bit 9 ='1').
* | | |Note1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode.
* | | |Note2: This bit can be cleared by writing '1' to it.
* |[4] |PEF |Parity Error Flag
* | | |This bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.
* | | |0 = No parity error is generated.
* | | |1 = Parity error is generated.
* | | |Note: This bit can be cleared by writing '1' to it.
* |[5] |FEF |Framing Error Flag
* | | |This bit is set to logic 1 whenever the received character does not have a valid 'stop bit'
* | | |(that is, the stop bit following the last data bit or parity bit is detected as logic 0).
* | | |0 = No framing error is generated.
* | | |1 = Framing error is generated.
* | | |Note: This bit can be cleared by writing '1' to it.
* |[6] |BIF |Break Interrupt Flag
* | | |This bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0)
* | | |for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits).
* | | |0 = No Break interrupt is generated.
* | | |1 = Break interrupt is generated.
* | | |Note: This bit can be cleared by writing '1' to it.
* |[13:8] |RXPTR |RX FIFO Pointer (Read Only)
* | | |This field indicates the RX FIFO Buffer Pointer
* | | |When UART receives one byte from external device, RXPTR increases one
* | | |When one byte of RX FIFO is read by CPU, RXPTR decreases one.
* | | |The Maximum value shown in RXPTR is 15
* | | |When the using level of RX FIFO Buffer equal to 16, the RXFULL bit is set to 1 and RXPTR will show 0
* | | |As one byte of RX FIFO is read by CPU, the RXFULL bit is cleared to 0 and RXPTR will show 15
* |[14] |RXEMPTY |Receiver FIFO Empty (Read Only)
* | | |This bit initiate RX FIFO empty or not.
* | | |0 = RX FIFO is not empty.
* | | |1 = RX FIFO is empty.
* | | |Note: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high
* | | |It will be cleared when UART receives any new data.
* |[15] |RXFULL |Receiver FIFO Full (Read Only)
* | | |This bit initiates RX FIFO full or not.
* | | |0 = RX FIFO is not full.
* | | |1 = RX FIFO is full.
* | | |Note: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise it is cleared by hardware.
* |[21:16] |TXPTR |TX FIFO Pointer (Read Only)
* | | |This field indicates the TX FIFO Buffer Pointer
* | | |When CPU writes one byte into UART_DAT, TXPTR increases one
* | | |When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one.
* | | |The Maximum value shown in TXPTR is 15
* | | |When the using level of TX FIFO Buffer equal to 16, the TXFULL bit is set to 1 and TXPTR will show 0
* | | |As one byte of TX FIFO is transferred to Transmitter Shift Register, the TXFULL bit is cleared to 0 and TXPTR will show 15
* |[22] |TXEMPTY |Transmitter FIFO Empty (Read Only)
* | | |This bit indicates TX FIFO empty or not.
* | | |0 = TX FIFO is not empty.
* | | |1 = TX FIFO is empty.
* | | |Note: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high
* | | |It will be cleared when writing data into UART_DAT (TX FIFO not empty).
* |[23] |TXFULL |Transmitter FIFO Full (Read Only)
* | | |This bit indicates TX FIFO full or not.
* | | |0 = TX FIFO is not full.
* | | |1 = TX FIFO is full.
* | | |Note: This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise it is cleared by hardware.
* |[24] |TXOVIF |TX Overflow Error Interrupt Flag
* | | |If TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1.
* | | |0 = TX FIFO is not overflow.
* | | |1 = TX FIFO is overflow.
* | | |Note: This bit can be cleared by writing '1' to it.
* |[28] |TXEMPTYF |Transmitter Empty Flag (Read Only)
* | | |This bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.
* | | |0 = TX FIFO is not empty or the STOP bit of the last byte has been not transmitted.
* | | |1 = TX FIFO is empty and the STOP bit of the last byte has been transmitted.
* | | |Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
* |[29] |RXIDLE |RX Idle Status (Read Only)
* | | |This bit is set by hardware when RX is idle.
* | | |0 = RX is busy.
* | | |1 = RX is idle. (Default)
* |[31] |TXRXACT |TX and RX Active Status (Read Only)
* | | |This bit indicates TX and RX are active or inactive.
* | | |0 = TX and RX are inactive.
* | | |1 = TX and RX are active. (Default)
* | | |Note: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state, this bit is cleared
* | | |The UART controller can not transmit or receive data at this moment
* | | |Otherwise this bit is set.
* @var UART_T::INTSTS
* Offset: 0x1C UART Interrupt Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |RDAIF |Receive Data Available Interrupt Flag
* | | |When the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set
* | | |If RDAIEN (UART_INTEN [0]) is enabled, the RDA interrupt will be generated.
* | | |0 = No RDA interrupt flag is generated.
* | | |1 = RDA interrupt flag is generated.
* | | |Note: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL(UART_FIFO[7:4]).
* |[1] |THREIF |Transmit Holding Register Empty Interrupt Flag
* | | |This bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register
* | | |If THREIEN (UART_INTEN[1]) is enabled, the THRE interrupt will be generated.
* | | |0 = No THRE interrupt flag is generated.
* | | |1 = THRE interrupt flag is generated.
* | | |Note: This bit is read only and it will be cleared when writing data into UART_DAT (TX FIFO not empty).
* |[2] |RLSIF |Receive Line Interrupt Flag (Read Only)
* | | |This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]), is set)
* | | |If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.
* | | |0 = No RLS interrupt flag is generated.
* | | |1 = RLS interrupt flag is generated.
* | | |Note1: In RS-485 function mode, this field is set include "receiver detect and received address byte character (bit9 = '1') bit"
* | | |At the same time, the bit of ADDRDETF (UART_FIFOSTS[3]) is also set.
* | | |Note2: This bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared.
* | | |Note3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]) , FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared.
* |[3] |MODEMIF |MODEM Interrupt Flag (Read Only)
* | | |This bit is set when the nCTS pin has state change (CTSDETF (UART_MODEMSTS[0]) = 1)
* | | |If MODEMIEN (UART_INTEN [3]) is enabled, the Modem interrupt will be generated.
* | | |0 = No Modem interrupt flag is generated.
* | | |1 = Modem interrupt flag is generated.
* | | |Note: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0]).
* |[4] |RXTOIF |RX Time-out Interrupt Flag (Read Only)
* | | |This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0])
* | | |If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated.
* | | |0 = No RX time-out interrupt flag is generated.
* | | |1 = RX time-out interrupt flag is generated.
* | | |Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
* |[5] |BUFERRIF |Buffer Error Interrupt Flag (Read Only)
* | | |This bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set)
* | | |When BUFERRIF (UART_INTSTS[5]) is set, the transfer is not correct
* | | |If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.
* | | |0 = No buffer error interrupt flag is generated.
* | | |1 = Buffer error interrupt flag is generated.
* | | |Note: This bit is cleared if both of RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]) are cleared to 0 by writing 1 to RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]).
* |[6] |WKIF |UART Wake-up Interrupt Flag (Read Only)
* | | |This bit is set when TOUTWKF (UART_WKSTS[4]), RS485WKF (UART_WKSTS[3]), RFRTWKF (UART_WKSTS[2]), DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.
* | | |0 = No UART wake-up interrupt flag is generated.
* | | |1 = UART wake-up interrupt flag is generated.
* | | |Note: This bit is cleared if all of TOUTWKF, RS485WKF, RFRTWKF, DATWKF and CTSWKF are cleared to 0 by writing 1 to the corresponding interrupt flag.
* |[7] |LINIF |LIN Bus Interrupt Flag
* | | |This bit is set when LIN slave header detect (SLVHDETF (UART_LINSTS[0] = 1)), LIN break detect (BRKDETF(UART_LINSTS[8]=1)), bit error detect (BITEF(UART_LINSTS[9]=1)), LIN slave ID parity error (SLVIDPEF(UART_LINSTS[2] = 1)) or LIN slave header error detect (SLVHEF (UART_LINSTS[1]))
* | | |If LINIEN (UART_INTEN [8]) is enabled the LIN interrupt will be generated.
* | | |0 = None of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated.
* | | |1 = At least one of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated.
* | | |Note: This bit is cleared when SLVHDETF(UART_LINSTS[0]), BRKDETF(UART_LINSTS[8]), BITEF(UART_LINSTS[9]), SLVIDPEF (UART_LINSTS[2]) and SLVHEF(UART_LINSTS[1]) all are cleared and software writing '1' to LINIF(UART_INTSTS[7]).
* |[8] |RDAINT |Receive Data Available Interrupt Indicator (Read Only)
* | | |This bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1.
* | | |0 = No RDA interrupt is generated.
* | | |1 = RDA interrupt is generated.
* |[9] |THREINT |Transmit Holding Register Empty Interrupt Indicator (Read Only)
* | | |This bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1.
* | | |0 = No THRE interrupt is generated.
* | | |1 = THRE interrupt is generated.
* |[10] |RLSINT |Receive Line Status Interrupt Indicator (Read Only)
* | | |This bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1.
* | | |0 = No RLS interrupt is generated.
* | | |1 = RLS interrupt is generated.
* |[11] |MODEMINT |MODEM Status Interrupt Indicator (Read Only)
* | | |This bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1
* | | |0 = No Modem interrupt is generated.
* | | |1 = Modem interrupt is generated.
* |[12] |RXTOINT |RX Time-out Interrupt Indicator (Read Only)
* | | |This bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1.
* | | |0 = No RX time-out interrupt is generated.
* | | |1 = RX time-out interrupt is generated.
* |[13] |BUFERRINT |Buffer Error Interrupt Indicator (Read Only)
* | | |This bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1.
* | | |0 = No buffer error interrupt is generated.
* | | |1 = Buffer error interrupt is generated.
* |[14] |WKINT |UART Wake-up Interrupt Indicator (Read Only)
* | | |This bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1.
* | | |0 = No UART wake-up interrupt is generated.
* | | |1 = UART wake-up interrupt is generated.
* |[15] |LININT |LIN Bus Interrupt Indicator (Read Only)
* | | |This bit is set if LINIEN (UART_INTEN[8]) and LINIF(UART_INTSTS[7]) are both set to 1.
* | | |0 = No LIN Bus interrupt is generated.
* | | |1 = The LIN Bus interrupt is generated.
* |[18] |HWRLSIF |PDMA Mode Receive Line Status Flag (Read Only)
* | | |This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set)
* | | |If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.
* | | |0 = No RLS interrupt flag is generated in PDMA mode.
* | | |1 = RLS interrupt flag is generated in PDMA mode.
* | | |Note1: In RS-485 function mode, this field include "receiver detect any address byte received address byte character (bit9 = '1') bit".
* | | |Note2: In UART function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]) , FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared.
* | | |Note3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared
* |[19] |HWMODIF |PDMA Mode MODEM Interrupt Flag (Read Only)
* | | |This bit is set when the nCTS pin has state change (CTSDETF (UART_MODEMSTS [0] =1))
* | | |If MODEMIEN (UART_INTEN [3]) is enabled, the Modem interrupt will be generated.
* | | |0 = No Modem interrupt flag is generated in PDMA mode.
* | | |1 = Modem interrupt flag is generated in PDMA mode.
* | | |Note: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS [0]).
* |[20] |HWTOIF |PDMA Mode RX Time-out Interrupt Flag (Read Only)
* | | |This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0])
* | | |If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated .
* | | |0 = No RX time-out interrupt flag is generated in PDMA mode.
* | | |1 = RX time-out interrupt flag is generated in PDMA mode.
* | | |Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
* |[21] |HWBUFEIF |PDMA Mode Buffer Error Interrupt Flag (Read Only)
* | | |This bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set)
* | | |When BUFERRIF (UART_INTSTS[5]) is set, the transfer maybe is not correct
* | | |If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.
* | | |0 = No buffer error interrupt flag is generated in PDMA mode.
* | | |1 = Buffer error interrupt flag is generated in PDMA mode.
* | | |Note: This bit is cleared when both TXOVIF (UART_FIFOSTS[24]]) and RXOVIF (UART_FIFOSTS[0]) are cleared.
* |[22] |TXENDIF |Transmitter Empty Interrupt Flag
* | | |This bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set)
* | | |If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt will be generated.
* | | |0 = No transmitter empty interrupt flag is generated.
* | | |1 = Transmitter empty interrupt flag is generated.
* | | |Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
* |[26] |HWRLSINT |PDMA Mode Receive Line Status Interrupt Indicator (Read Only)
* | | |This bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1.
* | | |0 = No RLS interrupt is generated in PDMA mode.
* | | |1 = RLS interrupt is generated in PDMA mode.
* |[27] |HWMODINT |PDMA Mode MODEM Status Interrupt Indicator (Read Only)
* | | |This bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1.
* | | |0 = No Modem interrupt is generated in PDMA mode.
* | | |1 = Modem interrupt is generated in PDMA mode.
* |[28] |HWTOINT |PDMA Mode RX Time-out Interrupt Indicator (Read Only)
* | | |This bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1.
* | | |0 = No RX time-out interrupt is generated in PDMA mode.
* | | |1 = RX time-out interrupt is generated in PDMA mode.
* |[29] |HWBUFEINT |PDMA Mode Buffer Error Interrupt Indicator (Read Only)
* | | |This bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1.
* | | |0 = No buffer error interrupt is generated in PDMA mode.
* | | |1 = Buffer error interrupt is generated in PDMA mode.
* |[30] |TXENDINT |Transmitter Empty Interrupt Indicator (Read Only)
* | | |This bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1.
* | | |0 = No Transmitter Empty interrupt is generated.
* | | |1 = Transmitter Empty interrupt is generated.
* |[31] |ABRINT |Auto-baud Rate Interrupt Indicator (Read Only)
* | | |This bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1.
* | | |0 = No Auto-baud Rate interrupt is generated.
* | | |1 = The Auto-baud Rate interrupt is generated.
* @var UART_T::TOUT
* Offset: 0x20 UART Time-out Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |TOIC |Time-out Interrupt Comparator
* | | |The time-out counter resets and starts counting (the counting clock = baud rate) whenever the RX FIFO receives a new data word if time out counter is enabled by setting TOCNTEN (UART_INTEN[11])
* | | |Once the content of time-out counter is equal to that of time-out interrupt comparator (TOIC (UART_TOUT[7:0])), a receiver time-out interrupt (RXTOINT(UART_INTSTS[12])) is generated if RXTOIEN (UART_INTEN [4]) enabled
* | | |A new incoming data word or RX FIFO empty will clear RXTOIF (UART_INTSTS[4])
* | | |In order to avoid receiver time-out interrupt generation immediately during one character is being received, TOIC value should be set between 40 and 255
* | | |So, for example, if TOIC is set with 40, the time-out interrupt is generated after four characters are not received when 1 stop bit and no parity check is set for UART transfer.
* |[15:8] |DLY |TX Delay Time Value
* | | |This field is used to programming the transfer delay time between the last stop bit and next start bit
* | | |The unit is bit time.
* @var UART_T::BAUD
* Offset: 0x24 UART Baud Rate Divider Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |BRD |Baud Rate Divider
* | | |The field indicates the baud rate divider
* | | |This filed is used in baud rate calculation
* | | |The detail description is shown in Table 7.15-4.
* |[27:24] |EDIVM1 |Extra Divider for BAUD Rate Mode 1
* | | |This field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2
* | | |The detail description is shown in Table 7.15-4
* |[28] |BAUDM0 |BAUD Rate Mode Selection Bit 0
* | | |This bit is baud rate mode selection bit 0
* | | |UART provides three baud rate calculation modes
* | | |This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode
* | | |The detail description is shown in Table 7.15-4.
* |[29] |BAUDM1 |BAUD Rate Mode Selection Bit 1
* | | |This bit is baud rate mode selection bit 1
* | | |UART provides three baud rate calculation modes
* | | |This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode
* | | |The detail description is shown in Table 7.15-4.
* | | |Note: In IrDA mode must be operated in mode 0.
* @var UART_T::IRDA
* Offset: 0x28 UART IrDA Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1] |TXEN |IrDA Receiver/Transmitter Selection Enable Bit
* | | |0 = IrDA Transmitter Disabled and Receiver Enabled. (Default)
* | | |1 = IrDA Transmitter Enabled and Receiver Disabled.
* |[5] |TXINV |IrDA Inverse Transmitting Output Signal
* | | |0 = None inverse transmitting signal. (Default).
* | | |1 = Inverse transmitting output signal.
* | | |Note1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared
* | | |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
* | | |Note2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select IrDA function.
* |[6] |RXINV |IrDA Inverse Receive Input Signal
* | | |0 = None inverse receiving input signal.
* | | |1 = Inverse receiving input signal. (Default)
* | | |Note1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared
* | | |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
* | | |Note2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select IrDA function.
* @var UART_T::ALTCTL
* Offset: 0x2C UART Alternate Control/Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |BRKFL |UART LIN Break Field Length
* | | |This field indicates a 4-bit LIN TX break field count.
* | | |Note1: This break field length is BRKFL + 1.
* | | |Note2: According to LIN spec, the reset value is 0xC (break field length = 13).
* |[6] |LINRXEN |LIN RX Enable Bit
* | | |0 = LIN RX mode Disabled.
* | | |1 = LIN RX mode Enabled.
* |[7] |LINTXEN |LIN TX Break Mode Enable Bit
* | | |0 = LIN TX Break mode Disabled.
* | | |1 = LIN TX Break mode Enabled.
* | | |Note: When TX break field transfer operation finished, this bit will be cleared automatically.
* |[8] |RS485NMM |RS-485 Normal Multi-drop Operation Mode (NMM)
* | | |0 = RS-485 Normal Multi-drop Operation mode (NMM) Disabled.
* | | |1 = RS-485 Normal Multi-drop Operation mode (NMM) Enabled.
* | | |Note: It cannot be active with RS-485_AAD operation mode.
* |[9] |RS485AAD |RS-485 Auto Address Detection Operation Mode (AAD)
* | | |0 = RS-485 Auto Address Detection Operation mode (AAD) Disabled.
* | | |1 = RS-485 Auto Address Detection Operation mode (AAD) Enabled.
* | | |Note: It cannot be active with RS-485_NMM operation mode.
* |[10] |RS485AUD |RS-485 Auto Direction Function (AUD)
* | | |0 = RS-485 Auto Direction Operation function (AUD) Disabled.
* | | |1 = RS-485 Auto Direction Operation function (AUD) Enabled.
* | | |Note: It can be active with RS-485_AAD or RS-485_NMM operation mode.
* |[15] |ADDRDEN |RS-485 Address Detection Enable Bit
* | | |This bit is used to enable RS-485 Address Detection mode.
* | | |0 = Address detection mode Disabled.
* | | |1 = Address detection mode Enabled.
* | | |Note: This bit is used for RS-485 any operation mode.
* |[17] |ABRIF |Auto-baud Rate Interrupt Flag (Read Only)
* | | |This bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated.
* | | |0 = No auto-baud rate interrupt flag is generated.
* | | |1 = Auto-baud rate interrupt flag is generated.
* | | |Note: This bit is read only, but it can be cleared by writing '1' to ABRDTOIF (UART_FIFOSTS[2]) and ABRDIF(UART_FIFOSTS[1])
* |[18] |ABRDEN |Auto-baud Rate Detect Enable Bit
* | | |0 = Auto-baud rate detect function Disabled.
* | | |1 = Auto-baud rate detect function Enabled.
* | | |Note : This bit is cleared automatically after auto-baud detection is finished.
* |[20:19] |ABRDBITS |Auto-baud Rate Detect Bit Length
* | | |00 = 1-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x01.
* | | |01 = 2-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x02.
* | | |10 = 4-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x08.
* | | |11 = 8-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x80.
* | | |Note : The calculation of bit number includes the START bit.
* |[31:24] |ADDRMV |Address Match Value
* | | |This field contains the RS-485 address match values.
* | | |Note: This field is used for RS-485 auto address detection mode.
* @var UART_T::FUNCSEL
* Offset: 0x30 UART Function Select Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1:0] |FUNCSEL |Function Select
* | | |00 = UART function.
* | | |01 = LIN function.
* | | |10 = IrDA function.
* | | |11 = RS-485 function.
* |[3] |TXRXDIS |TX and RX Disable Bit
* | | |Setting this bit can disable TX and RX.
* | | |0 = TX and RX Enabled.
* | | |1 = TX and RX Disabled.
* | | |Note: The TX and RX will not disable immediately when this bit is set
* | | |The TX and RX complete current task before disable TX and RX
* | | |When TX and RX disable, the TXRXACT (UART_FIFOSTS[31]) is cleared.
* @var UART_T::LINCTL
* Offset: 0x34 UART LIN Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SLVEN |LIN Slave Mode Enable Bit
* | | |0 = LIN slave mode Disabled.
* | | |1 = LIN slave mode Enabled.
* |[1] |SLVHDEN |LIN Slave Header Detection Enable Bit
* | | |0 = LIN slave header detection Disabled.
* | | |1 = LIN slave header detection Enabled.
* | | |Note1: This bit only valid when in LIN slave mode (SLVEN (UART_LINCTL[0]) = 1).
* | | |Note2: In LIN function mode, when detect header field (break + sync + frame ID), SLVHDETF (UART_LINSTS [0]) flag will be asserted
* | | |If the LINIEN (UART_INTEN[8]) = 1, an interrupt will be generated.
* |[2] |SLVAREN |LIN Slave Automatic Resynchronization Mode Enable Bit
* | | |0 = LIN automatic resynchronization Disabled.
* | | |1 = LIN automatic resynchronization Enabled.
* | | |Note1: This bit only valid when in LIN slave mode (SLVEN (UART_LINCTL[0]) = 1).
* | | |Note2: When operation in Automatic Resynchronization mode, the baud rate setting must be mode2 (BAUDM1 (UART_BAUD [29]) and BAUDM0 (UART_BAUD [28]) must be 1).
* | | |Note3: The control and interactions of this field are explained in 7.15.5.9 (Slave mode with automatic resynchronization).
* |[3] |SLVDUEN |LIN Slave Divider Update Method Enable Bit
* | | |0 = UART_BAUD updated is written by software (if no automatic resynchronization update occurs at the same time).
* | | |1 = UART_BAUD is updated at the next received character
* | | |User must set the bit before checksum reception.
* | | |Note1: This bit only valid when in LIN slave mode (SLVEN (UART_LINCTL[0]) = 1).
* | | |Note2: This bit used for LIN Slave Automatic Resynchronization mode
* | | |(for Non-Automatic Resynchronization mode, this bit should be kept cleared)
* | | |Note3: The control and interactions of this field are explained in 7.15.5.9 (Slave mode with automatic resynchronization).
* |[4] |MUTE |LIN Mute Mode Enable Bit
* | | |0 = LIN mute mode Disabled.
* | | |1 = LIN mute mode Enabled.
* | | |Note: The exit from mute mode condition and each control and interactions of this field are explained in 7.15.5.9 (LIN slave mode).
* |[8] |SENDH |LIN TX Send Header Enable Bit
* | | |The LIN TX header can be break field or 'break and sync field' or 'break, sync and frame ID field', it is depend on setting HSEL (UART_LINCTL[23:22]).
* | | |0 = Send LIN TX header Disabled.
* | | |1 = Send LIN TX header Enabled.
* | | |Note1: This bit is shadow bit of LINTXEN (UART_ALTCTL [7]); user can read/write it by setting LINTXEN (UART_ALTCTL [7]) or SENDH (UART_LINCTL [8]).
* | | |Note2: When transmitter header field (it may be 'break' or 'break + sync' or 'break + sync + frame ID' selected by HSEL (UART_LINCTL[23:22]) field) transfer operation finished, this bit will be cleared automatically.
* |[9] |IDPEN |LIN ID Parity Enable Bit
* | | |0 = LIN frame ID parity Disabled.
* | | |1 = LIN frame ID parity Enabled.
* | | |Note1: This bit can be used for LIN master to sending header field (SENDH (UART_LINCTL[8])) = 1 and HSEL (UART_LINCTL[23:22]) = 10 or be used for enable LIN slave received frame ID parity checked.
* | | |Note2: This bit is only used when the operation header transmitter is in HSEL (UART_LINCTL[23:22]) = 10
* |[10] |BRKDETEN |LIN Break Detection Enable Bit
* | | |When detect consecutive dominant greater than 11 bits, and are followed by a delimiter character, the BRKDETF (UART_LINSTS[8]) flag is set at the end of break field
* | | |If the LINIEN (UART_INTEN [8])=1, an interrupt will be generated.
* | | |0 = LIN break detection Disabled .
* | | |1 = LIN break detection Enabled.
* |[11] |LINRXOFF |LIN Receiver Disable Bit
* | | |If the receiver is enabled (LINRXOFF (UART_LINCTL[11] ) = 0), all received byte data will be accepted and stored in the RX FIFO, and if the receiver is disabled (LINRXOFF (UART_LINCTL[11] = 1), all received byte data will be ignore.
* | | |0 = LIN receiver Enabled.
* | | |1 = LIN receiver Disabled.
* | | |Note: This bit is only valid when operating in LIN function mode (FUNCSEL (UART_FUNCSEL[1:0]) = 01).
* |[12] |BITERREN |Bit Error Detect Enable Bit
* | | |0 = Bit error detection function Disabled.
* | | |1 = Bit error detection function Enabled.
* | | |Note: In LIN function mode, when occur bit error, the BITEF (UART_LINSTS[9]) flag will be asserted
* | | |If the LINIEN (UART_INTEN[8]) = 1, an interrupt will be generated.
* |[19:16] |BRKFL |LIN Break Field Length
* | | |This field indicates a 4-bit LIN TX break field count.
* | | |Note1: These registers are shadow registers of BRKFL (UART_ALTCTL[3:0]), User can read/write it by setting BRKFL (UART_ALTCTL[3:0]) or BRKFL (UART_LINCTL[19:16]).
* | | |Note2: This break field length is BRKFL + 1.
* | | |Note3: According to LIN spec, the reset value is 12 (break field length = 13).
* |[21:20] |BSL |LIN Break/Sync Delimiter Length
* | | |00 = The LIN break/sync delimiter length is 1-bit time.
* | | |01 = The LIN break/sync delimiter length is 2-bit time.
* | | |10 = The LIN break/sync delimiter length is 3-bit time.
* | | |11 = The LIN break/sync delimiter length is 4-bit time.
* | | |Note: This bit used for LIN master to sending header field.
* |[23:22] |HSEL |LIN Header Select
* | | |00 = The LIN header includes 'break field'.
* | | |01 = The LIN header includes 'break field' and 'sync field'.
* | | |10 = The LIN header includes 'break field', 'sync field' and 'frame ID field'.
* | | |11 = Reserved.
* | | |Note: This bit is used to master mode for LIN to send header field (SENDH (UART_LINCTL [8]) = 1) or used to slave to indicates exit from mute mode condition (MUTE (UART_LINCTL[4] = 1).
* |[31:24] |PID |LIN PID Bits
* | | |This field contains the LIN frame ID value when in LIN function mode, the frame ID parity can be generated by software or hardware depends on IDPEN (UART_LINCTL[9]) = 1.
* | | |If the parity generated by hardware, user fill ID0~ID5 (PID [29:24] ), hardware will calculate P0 (PID[30]) and P1 (PID[31]), otherwise user must filled frame ID and parity in this field.
* | | |Note1: User can fill any 8-bit value to this field and the bit 24 indicates ID0 (LSB first).
* | | |Note2: This field can be used for LIN master mode or slave mode.
* @var UART_T::LINSTS
* Offset: 0x38 UART LIN Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SLVHDETF |LIN Slave Header Detection Flag
* | | |This bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it.
* | | |0 = LIN header not detected.
* | | |1 = LIN header detected (break + sync + frame ID).
* | | |Note1: This bit can be cleared by writing 1 to it.
* | | |Note2: This bit is only valid when in LIN slave mode (SLVEN (UART_LINCTL [0]) = 1) and enable LIN slave header detection function (SLVHDEN (UART_LINCTL [1])).
* | | |Note3: When enable ID parity check IDPEN (UART_LINCTL [9]), if hardware detect complete header ('break + sync + frame ID'), the SLVHDETF will be set whether the frame ID correct or not.
* |[1] |SLVHEF |LIN Slave Header Error Flag
* | | |This bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it
* | | |The header errors include 'break delimiter is too short (less than 0.5 bit time)', 'frame error in sync field or Identifier field',
* | | |'sync field data is not 0x55 in Non-Automatic Resynchronization mode', 'sync field deviation error with Automatic Resynchronization mode',
* | | |'sync field measure time-out with Automatic Resynchronization mode' and 'LIN header reception time-out'.
* | | |0 = LIN header error not detected.
* | | |1 = LIN header error detected.
* | | |Note1: This bit can be cleared by writing 1 to it.
* | | |Note2: This bit is only valid when UART is operated in LIN slave mode (SLVEN (UART_LINCTL [0]) = 1) and
* | | |enables LIN slave header detection function (SLVHDEN (UART_LINCTL [1])).
* |[2] |SLVIDPEF |LIN Slave ID Parity Error Flag
* | | |This bit is set by hardware when receipted frame ID parity is not correct.
* | | |0 = No active.
* | | |1 = Receipted frame ID parity is not correct.
* | | |Note1: This bit can be cleared by writing 1 to it.
* | | |Note2: This bit is only valid when in LIN slave mode (SLVEN (UART_LINCTL [0])= 1) and enable LIN frame ID parity check function IDPEN (UART_LINCTL [9]).
* |[3] |SLVSYNCF |LIN Slave Sync Field
* | | |This bit indicates that the LIN sync field is being analyzed in Automatic Resynchronization mode
* | | |When the receiver header have some error been detect, user must reset the internal circuit to re-search new frame header by writing 1 to this bit.
* | | |0 = The current character is not at LIN sync state.
* | | |1 = The current character is at LIN sync state.
* | | |Note1: This bit is only valid when in LIN Slave mode (SLVEN(UART_LINCTL[0]) = 1).
* | | |Note2: This bit can be cleared by writing 1 to it.
* | | |Note3: When writing 1 to it, hardware will reload the initial baud rate and re-search a new frame header.
* |[8] |BRKDETF |LIN Break Detection Flag
* | | |This bit is set by hardware when a break is detected and be cleared by writing 1 to it through software.
* | | |0 = LIN break not detected.
* | | |1 = LIN break detected.
* | | |Note1: This bit can be cleared by writing 1 to it.
* | | |Note2: This bit is only valid when LIN break detection function is enabled (BRKDETEN (UART_LINCTL[10]) =1).
* |[9] |BITEF |Bit Error Detect Status Flag
* | | |At TX transfer state, hardware will monitor the bus state, if the input pin (UART_RXD) state not equals to the output pin (UART_TXD) state, BITEF (UART_LINSTS[9]) will be set.
* | | |When occur bit error, if the LINIEN (UART_INTEN[8]) = 1, an interrupt will be generated.
* | | |0 = Bit error not detected.
* | | |1 = Bit error detected.
* | | |Note1: This bit can be cleared by writing 1 to it.
* | | |Note2: This bit is only valid when enable bit error detection function (BITERREN (UART_LINCTL [12]) = 1).
* @var UART_T::BRCOMP
* Offset: 0x3C UART Baud Rate Compensation Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[8:0] |BRCOMP |Baud Rate Compensation Patten
* | | |These 9-bits are used to define the relative bit is compensated or not.
* | | |BRCOMP[7:0] is used to define the compensation of UART_DAT[7:0] and BRCOM[8] is used to define the parity bit.
* |[31] |BRCOMPDEC |Baud Rate Compensation Decrease
* | | |0 = Positive (increase one module clock) compensation for each compensated bit.
* | | |1 = Negative (decrease one module clock) compensation for each compensated bit.
* @var UART_T::WKCTL
* Offset: 0x40 UART Wake-up Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |WKCTSEN |nCTS Wake-up Enable Bit
* | | |0 = nCTS Wake-up system function Disabled.
* | | |1 = nCTS Wake-up system function Enabled, when the system is in Power-down mode, an external.
* | | |nCTS change will wake-up system from Power-down mode.
* |[1] |WKDATEN |Incoming Data Wake-up Enable Bit
* | | |0 = Incoming data wake-up system function Disabled.
* | | |1 = Incoming data wake-up system function Enabled, when the system is in Power-down mode,.
* | | |incoming data will wake-up system from Power-down mode.
* |[2] |WKRFRTEN |Received Data FIFO Reached Threshold Wake-up Enable Bit
* | | |0 = Received Data FIFO reached threshold wake-up system function Disabled.
* | | |1 = Received Data FIFO reached threshold wake-up system function Enabled, when the system is.
* | | |in Power-down mode, Received Data FIFO reached threshold will wake-up system from
* | | |Power-down mode.
* |[3] |WKRS485EN |RS-485 Address Match (AAD Mode) Wake-up Enable Bit
* | | |0 = RS-485 Address Match (AAD mode) wake-up system function Disabled.
* | | |1 = RS-485 Address Match (AAD mode) wake-up system function Enabled, when the system is in.
* | | |Power-down mode, RS-485 Address Match will wake-up system from Power-down mode.
* | | |Note: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485 function mode
* | | |and ADDRDEN (UART_ALTCTL[15]) is set to 1.
* |[4] |WKTOUTEN |Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit
* | | |0 = Received Data FIFO reached threshold time-out wake-up system function Disabled.
* | | |1 = Received Data FIFO reached threshold time-out wake-up system function Enabled, when the.
* | | |system is in Power-down mode, Received Data FIFO reached threshold time-out will wake-up
* | | |system from Power-down mode.
* | | |Note: It is suggest the function is enabled when the WKRFRTEN (UART_WKCTL[2]) is set to 1.
* @var UART_T::WKSTS
* Offset: 0x44 UART Wake-up Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CTSWKF |nCTS Wake-up Flag
* | | |This bit is set if chip wake-up from power-down state by nCTS wake-up.
* | | |0 = Chip stays in power-down state.
* | | |1 = Chip wake-up from power-down state by nCTS wake-up.
* | | |Note1: If WKCTSEN (UART_WKCTL[0]) is enabled, the nCTS wake-up cause this bit is set to '1'.
* | | |Note2: This bit can be cleared by writing '1' to it.
* |[1] |DATWKF |Incoming Data Wake-up Flag
* | | |This bit is set if chip wake-up from power-down state by data wake-up.
* | | |0 = Chip stays in power-down state.
* | | |1 = Chip wake-up from power-down state by Incoming Data wake-up.
* | | |Note1: If WKDATEN (UART_WKCTL[1]) is enabled, the Incoming Data wake-up cause this bit is set to '1'.
* | | |Note2: This bit can be cleared by writing '1' to it.
* |[2] |RFRTWKF |Received Data FIFO Reached Threshold Wake-up Flag
* | | |This bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold
* | | |wake-up .
* | | |0 = Chip stays in power-down state.
* | | |1 = Chip wake-up from power-down state by Received Data FIFO Reached Threshold wake-up.
* | | |Note1: If WKRFRTEN (UART_WKCTL[2]) is enabled, the Received Data FIFO Reached Threshold wake-up cause this bit is set to '1'.
* | | |Note2: This bit can be cleared by writing '1' to it.
* |[3] |RS485WKF |RS-485 Address Match (AAD Mode) Wake-up Flag
* | | |This bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).
* | | |0 = Chip stays in power-down state.
* | | |1 = Chip wake-up from power-down state by RS-485 Address Match (AAD mode) wake-up.
* | | |Note1: If WKRS485EN (UART_WKCTL[3]) is enabled, the RS-485 Address Match (AAD mode) wake-up cause this bit is set to '1'.
* | | |Note2: This bit can be cleared by writing '1' to it.
* |[4] |TOUTWKF |Received Data FIFO Threshold Time-out Wake-up Flag
* | | |This bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out
* | | |wake-up.
* | | |0 = Chip stays in power-down state.
* | | |1 = Chip wake-up from power-down state by Received Data FIFO reached threshold time-out.
* | | |wake-up.
* | | |Note1: If WKTOUTEN (UART_WKCTL[4]) is enabled, the Received Data FIFO reached threshold time-out wake-up cause this bit is set to '1'.
* | | |Note2: This bit can be cleared by writing '1' to it.
* @var UART_T::DWKCOMP
* Offset: 0x48 UART Incoming Data Wake-up Compensation Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |STCOMP |Start Bit Compensation Value
* | | |These bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (start bit) when the device is wake-up from power-down mode.
* | | |Note: It is valid only when WKDATEN (UART_WKCTL[1]) is set.
*/
__IO uint32_t DAT; /*!< [0x0000] UART Receive/Transmit Buffer Register */
__IO uint32_t INTEN; /*!< [0x0004] UART Interrupt Enable Register */
__IO uint32_t FIFO; /*!< [0x0008] UART FIFO Control Register */
__IO uint32_t LINE; /*!< [0x000c] UART Line Control Register */
__IO uint32_t MODEM; /*!< [0x0010] UART Modem Control Register */
__IO uint32_t MODEMSTS; /*!< [0x0014] UART Modem Status Register */
__IO uint32_t FIFOSTS; /*!< [0x0018] UART FIFO Status Register */
__IO uint32_t INTSTS; /*!< [0x001c] UART Interrupt Status Register */
__IO uint32_t TOUT; /*!< [0x0020] UART Time-out Register */
__IO uint32_t BAUD; /*!< [0x0024] UART Baud Rate Divider Register */
__IO uint32_t IRDA; /*!< [0x0028] UART IrDA Control Register */
__IO uint32_t ALTCTL; /*!< [0x002c] UART Alternate Control/Status Register */
__IO uint32_t FUNCSEL; /*!< [0x0030] UART Function Select Register */
__IO uint32_t LINCTL; /*!< [0x0034] UART LIN Control Register */
__IO uint32_t LINSTS; /*!< [0x0038] UART LIN Status Register */
__IO uint32_t BRCOMP; /*!< [0x003c] UART Baud Rate Compensation Register */
__IO uint32_t WKCTL; /*!< [0x0040] UART Wake-up Control Register */
__IO uint32_t WKSTS; /*!< [0x0044] UART Wake-up Status Register */
__IO uint32_t DWKCOMP; /*!< [0x0048] UART Incoming Data Wake-up Compensation Register */
} UART_T;
/**
@addtogroup UART_CONST UART Bit Field Definition
Constant Definitions for UART Controller
@{ */
#define UART_DAT_DAT_Pos (0) /*!< UART_T::DAT: DAT Position */
#define UART_DAT_DAT_Msk (0xfful << UART_DAT_DAT_Pos) /*!< UART_T::DAT: DAT Mask */
#define UART_DAT_PARITY_Pos (8) /*!< UART_T::DAT: PARITY Position */
#define UART_DAT_PARITY_Msk (0x1ul << UART_DAT_PARITY_Pos) /*!< UART_T::DAT: PARITY Mask */
#define UART_INTEN_RDAIEN_Pos (0) /*!< UART_T::INTEN: RDAIEN Position */
#define UART_INTEN_RDAIEN_Msk (0x1ul << UART_INTEN_RDAIEN_Pos) /*!< UART_T::INTEN: RDAIEN Mask */
#define UART_INTEN_THREIEN_Pos (1) /*!< UART_T::INTEN: THREIEN Position */
#define UART_INTEN_THREIEN_Msk (0x1ul << UART_INTEN_THREIEN_Pos) /*!< UART_T::INTEN: THREIEN Mask */
#define UART_INTEN_RLSIEN_Pos (2) /*!< UART_T::INTEN: RLSIEN Position */
#define UART_INTEN_RLSIEN_Msk (0x1ul << UART_INTEN_RLSIEN_Pos) /*!< UART_T::INTEN: RLSIEN Mask */
#define UART_INTEN_MODEMIEN_Pos (3) /*!< UART_T::INTEN: MODEMIEN Position */
#define UART_INTEN_MODEMIEN_Msk (0x1ul << UART_INTEN_MODEMIEN_Pos) /*!< UART_T::INTEN: MODEMIEN Mask */
#define UART_INTEN_RXTOIEN_Pos (4) /*!< UART_T::INTEN: RXTOIEN Position */
#define UART_INTEN_RXTOIEN_Msk (0x1ul << UART_INTEN_RXTOIEN_Pos) /*!< UART_T::INTEN: RXTOIEN Mask */
#define UART_INTEN_BUFERRIEN_Pos (5) /*!< UART_T::INTEN: BUFERRIEN Position */
#define UART_INTEN_BUFERRIEN_Msk (0x1ul << UART_INTEN_BUFERRIEN_Pos) /*!< UART_T::INTEN: BUFERRIEN Mask */
#define UART_INTEN_WKIEN_Pos (6) /*!< UART_T::INTEN: WKIEN Position */
#define UART_INTEN_WKIEN_Msk (0x1ul << UART_INTEN_WKIEN_Pos) /*!< UART_T::INTEN: WKIEN Mask */
#define UART_INTEN_LINIEN_Pos (8) /*!< UART_T::INTEN: LINIEN Position */
#define UART_INTEN_LINIEN_Msk (0x1ul << UART_INTEN_LINIEN_Pos) /*!< UART_T::INTEN: LINIEN Mask */
#define UART_INTEN_TOCNTEN_Pos (11) /*!< UART_T::INTEN: TOCNTEN Position */
#define UART_INTEN_TOCNTEN_Msk (0x1ul << UART_INTEN_TOCNTEN_Pos) /*!< UART_T::INTEN: TOCNTEN Mask */
#define UART_INTEN_ATORTSEN_Pos (12) /*!< UART_T::INTEN: ATORTSEN Position */
#define UART_INTEN_ATORTSEN_Msk (0x1ul << UART_INTEN_ATORTSEN_Pos) /*!< UART_T::INTEN: ATORTSEN Mask */
#define UART_INTEN_ATOCTSEN_Pos (13) /*!< UART_T::INTEN: ATOCTSEN Position */
#define UART_INTEN_ATOCTSEN_Msk (0x1ul << UART_INTEN_ATOCTSEN_Pos) /*!< UART_T::INTEN: ATOCTSEN Mask */
#define UART_INTEN_TXPDMAEN_Pos (14) /*!< UART_T::INTEN: TXPDMAEN Position */
#define UART_INTEN_TXPDMAEN_Msk (0x1ul << UART_INTEN_TXPDMAEN_Pos) /*!< UART_T::INTEN: TXPDMAEN Mask */
#define UART_INTEN_RXPDMAEN_Pos (15) /*!< UART_T::INTEN: RXPDMAEN Position */
#define UART_INTEN_RXPDMAEN_Msk (0x1ul << UART_INTEN_RXPDMAEN_Pos) /*!< UART_T::INTEN: RXPDMAEN Mask */
#define UART_INTEN_ABRIEN_Pos (18) /*!< UART_T::INTEN: ABRIEN Position */
#define UART_INTEN_ABRIEN_Msk (0x1ul << UART_INTEN_ABRIEN_Pos) /*!< UART_T::INTEN: ABRIEN Mask */
#define UART_INTEN_TXENDIEN_Pos (22) /*!< UART_T::INTEN: TXENDIEN Position */
#define UART_INTEN_TXENDIEN_Msk (0x1ul << UART_INTEN_TXENDIEN_Pos) /*!< UART_T::INTEN: TXENDIEN Mask */
#define UART_FIFO_RXRST_Pos (1) /*!< UART_T::FIFO: RXRST Position */
#define UART_FIFO_RXRST_Msk (0x1ul << UART_FIFO_RXRST_Pos) /*!< UART_T::FIFO: RXRST Mask */
#define UART_FIFO_TXRST_Pos (2) /*!< UART_T::FIFO: TXRST Position */
#define UART_FIFO_TXRST_Msk (0x1ul << UART_FIFO_TXRST_Pos) /*!< UART_T::FIFO: TXRST Mask */
#define UART_FIFO_RFITL_Pos (4) /*!< UART_T::FIFO: RFITL Position */
#define UART_FIFO_RFITL_Msk (0xful << UART_FIFO_RFITL_Pos) /*!< UART_T::FIFO: RFITL Mask */
#define UART_FIFO_RXOFF_Pos (8) /*!< UART_T::FIFO: RXOFF Position */
#define UART_FIFO_RXOFF_Msk (0x1ul << UART_FIFO_RXOFF_Pos) /*!< UART_T::FIFO: RXOFF Mask */
#define UART_FIFO_RTSTRGLV_Pos (16) /*!< UART_T::FIFO: RTSTRGLV Position */
#define UART_FIFO_RTSTRGLV_Msk (0xful << UART_FIFO_RTSTRGLV_Pos) /*!< UART_T::FIFO: RTSTRGLV Mask */
#define UART_LINE_WLS_Pos (0) /*!< UART_T::LINE: WLS Position */
#define UART_LINE_WLS_Msk (0x3ul << UART_LINE_WLS_Pos) /*!< UART_T::LINE: WLS Mask */
#define UART_LINE_NSB_Pos (2) /*!< UART_T::LINE: NSB Position */
#define UART_LINE_NSB_Msk (0x1ul << UART_LINE_NSB_Pos) /*!< UART_T::LINE: NSB Mask */
#define UART_LINE_PBE_Pos (3) /*!< UART_T::LINE: PBE Position */
#define UART_LINE_PBE_Msk (0x1ul << UART_LINE_PBE_Pos) /*!< UART_T::LINE: PBE Mask */
#define UART_LINE_EPE_Pos (4) /*!< UART_T::LINE: EPE Position */
#define UART_LINE_EPE_Msk (0x1ul << UART_LINE_EPE_Pos) /*!< UART_T::LINE: EPE Mask */
#define UART_LINE_SPE_Pos (5) /*!< UART_T::LINE: SPE Position */
#define UART_LINE_SPE_Msk (0x1ul << UART_LINE_SPE_Pos) /*!< UART_T::LINE: SPE Mask */
#define UART_LINE_BCB_Pos (6) /*!< UART_T::LINE: BCB Position */
#define UART_LINE_BCB_Msk (0x1ul << UART_LINE_BCB_Pos) /*!< UART_T::LINE: BCB Mask */
#define UART_LINE_PSS_Pos (7) /*!< UART_T::LINE: PSS Position */
#define UART_LINE_PSS_Msk (0x1ul << UART_LINE_PSS_Pos) /*!< UART_T::LINE: PSS Mask */
#define UART_LINE_TXDINV_Pos (8) /*!< UART_T::LINE: TXDINV Position */
#define UART_LINE_TXDINV_Msk (0x1ul << UART_LINE_TXDINV_Pos) /*!< UART_T::LINE: TXDINV Mask */
#define UART_LINE_RXDINV_Pos (9) /*!< UART_T::LINE: RXDINV Position */
#define UART_LINE_RXDINV_Msk (0x1ul << UART_LINE_RXDINV_Pos) /*!< UART_T::LINE: RXDINV Mask */
#define UART_MODEM_RTS_Pos (1) /*!< UART_T::MODEM: RTS Position */
#define UART_MODEM_RTS_Msk (0x1ul << UART_MODEM_RTS_Pos) /*!< UART_T::MODEM: RTS Mask */
#define UART_MODEM_RTSACTLV_Pos (9) /*!< UART_T::MODEM: RTSACTLV Position */
#define UART_MODEM_RTSACTLV_Msk (0x1ul << UART_MODEM_RTSACTLV_Pos) /*!< UART_T::MODEM: RTSACTLV Mask */
#define UART_MODEM_RTSSTS_Pos (13) /*!< UART_T::MODEM: RTSSTS Position */
#define UART_MODEM_RTSSTS_Msk (0x1ul << UART_MODEM_RTSSTS_Pos) /*!< UART_T::MODEM: RTSSTS Mask */
#define UART_MODEMSTS_CTSDETF_Pos (0) /*!< UART_T::MODEMSTS: CTSDETF Position */
#define UART_MODEMSTS_CTSDETF_Msk (0x1ul << UART_MODEMSTS_CTSDETF_Pos) /*!< UART_T::MODEMSTS: CTSDETF Mask */
#define UART_MODEMSTS_CTSSTS_Pos (4) /*!< UART_T::MODEMSTS: CTSSTS Position */
#define UART_MODEMSTS_CTSSTS_Msk (0x1ul << UART_MODEMSTS_CTSSTS_Pos) /*!< UART_T::MODEMSTS: CTSSTS Mask */
#define UART_MODEMSTS_CTSACTLV_Pos (8) /*!< UART_T::MODEMSTS: CTSACTLV Position */
#define UART_MODEMSTS_CTSACTLV_Msk (0x1ul << UART_MODEMSTS_CTSACTLV_Pos) /*!< UART_T::MODEMSTS: CTSACTLV Mask */
#define UART_FIFOSTS_RXOVIF_Pos (0) /*!< UART_T::FIFOSTS: RXOVIF Position */
#define UART_FIFOSTS_RXOVIF_Msk (0x1ul << UART_FIFOSTS_RXOVIF_Pos) /*!< UART_T::FIFOSTS: RXOVIF Mask */
#define UART_FIFOSTS_ABRDIF_Pos (1) /*!< UART_T::FIFOSTS: ABRDIF Position */
#define UART_FIFOSTS_ABRDIF_Msk (0x1ul << UART_FIFOSTS_ABRDIF_Pos) /*!< UART_T::FIFOSTS: ABRDIF Mask */
#define UART_FIFOSTS_ABRDTOIF_Pos (2) /*!< UART_T::FIFOSTS: ABRDTOIF Position */
#define UART_FIFOSTS_ABRDTOIF_Msk (0x1ul << UART_FIFOSTS_ABRDTOIF_Pos) /*!< UART_T::FIFOSTS: ABRDTOIF Mask */
#define UART_FIFOSTS_ADDRDETF_Pos (3) /*!< UART_T::FIFOSTS: ADDRDETF Position */
#define UART_FIFOSTS_ADDRDETF_Msk (0x1ul << UART_FIFOSTS_ADDRDETF_Pos) /*!< UART_T::FIFOSTS: ADDRDETF Mask */
#define UART_FIFOSTS_PEF_Pos (4) /*!< UART_T::FIFOSTS: PEF Position */
#define UART_FIFOSTS_PEF_Msk (0x1ul << UART_FIFOSTS_PEF_Pos) /*!< UART_T::FIFOSTS: PEF Mask */
#define UART_FIFOSTS_FEF_Pos (5) /*!< UART_T::FIFOSTS: FEF Position */
#define UART_FIFOSTS_FEF_Msk (0x1ul << UART_FIFOSTS_FEF_Pos) /*!< UART_T::FIFOSTS: FEF Mask */
#define UART_FIFOSTS_BIF_Pos (6) /*!< UART_T::FIFOSTS: BIF Position */
#define UART_FIFOSTS_BIF_Msk (0x1ul << UART_FIFOSTS_BIF_Pos) /*!< UART_T::FIFOSTS: BIF Mask */
#define UART_FIFOSTS_RXPTR_Pos (8) /*!< UART_T::FIFOSTS: RXPTR Position */
#define UART_FIFOSTS_RXPTR_Msk (0x3ful << UART_FIFOSTS_RXPTR_Pos) /*!< UART_T::FIFOSTS: RXPTR Mask */
#define UART_FIFOSTS_RXEMPTY_Pos (14) /*!< UART_T::FIFOSTS: RXEMPTY Position */
#define UART_FIFOSTS_RXEMPTY_Msk (0x1ul << UART_FIFOSTS_RXEMPTY_Pos) /*!< UART_T::FIFOSTS: RXEMPTY Mask */
#define UART_FIFOSTS_RXFULL_Pos (15) /*!< UART_T::FIFOSTS: RXFULL Position */
#define UART_FIFOSTS_RXFULL_Msk (0x1ul << UART_FIFOSTS_RXFULL_Pos) /*!< UART_T::FIFOSTS: RXFULL Mask */
#define UART_FIFOSTS_TXPTR_Pos (16) /*!< UART_T::FIFOSTS: TXPTR Position */
#define UART_FIFOSTS_TXPTR_Msk (0x3ful << UART_FIFOSTS_TXPTR_Pos) /*!< UART_T::FIFOSTS: TXPTR Mask */
#define UART_FIFOSTS_TXEMPTY_Pos (22) /*!< UART_T::FIFOSTS: TXEMPTY Position */
#define UART_FIFOSTS_TXEMPTY_Msk (0x1ul << UART_FIFOSTS_TXEMPTY_Pos) /*!< UART_T::FIFOSTS: TXEMPTY Mask */
#define UART_FIFOSTS_TXFULL_Pos (23) /*!< UART_T::FIFOSTS: TXFULL Position */
#define UART_FIFOSTS_TXFULL_Msk (0x1ul << UART_FIFOSTS_TXFULL_Pos) /*!< UART_T::FIFOSTS: TXFULL Mask */
#define UART_FIFOSTS_TXOVIF_Pos (24) /*!< UART_T::FIFOSTS: TXOVIF Position */
#define UART_FIFOSTS_TXOVIF_Msk (0x1ul << UART_FIFOSTS_TXOVIF_Pos) /*!< UART_T::FIFOSTS: TXOVIF Mask */
#define UART_FIFOSTS_TXEMPTYF_Pos (28) /*!< UART_T::FIFOSTS: TXEMPTYF Position */
#define UART_FIFOSTS_TXEMPTYF_Msk (0x1ul << UART_FIFOSTS_TXEMPTYF_Pos) /*!< UART_T::FIFOSTS: TXEMPTYF Mask */
#define UART_FIFOSTS_RXIDLE_Pos (29) /*!< UART_T::FIFOSTS: RXIDLE Position */
#define UART_FIFOSTS_RXIDLE_Msk (0x1ul << UART_FIFOSTS_RXIDLE_Pos) /*!< UART_T::FIFOSTS: RXIDLE Mask */
#define UART_FIFOSTS_TXRXACT_Pos (31) /*!< UART_T::FIFOSTS: TXRXACT Position */
#define UART_FIFOSTS_TXRXACT_Msk (0x1ul << UART_FIFOSTS_TXRXACT_Pos) /*!< UART_T::FIFOSTS: TXRXACT Mask */
#define UART_INTSTS_RDAIF_Pos (0) /*!< UART_T::INTSTS: RDAIF Position */
#define UART_INTSTS_RDAIF_Msk (0x1ul << UART_INTSTS_RDAIF_Pos) /*!< UART_T::INTSTS: RDAIF Mask */
#define UART_INTSTS_THREIF_Pos (1) /*!< UART_T::INTSTS: THREIF Position */
#define UART_INTSTS_THREIF_Msk (0x1ul << UART_INTSTS_THREIF_Pos) /*!< UART_T::INTSTS: THREIF Mask */
#define UART_INTSTS_RLSIF_Pos (2) /*!< UART_T::INTSTS: RLSIF Position */
#define UART_INTSTS_RLSIF_Msk (0x1ul << UART_INTSTS_RLSIF_Pos) /*!< UART_T::INTSTS: RLSIF Mask */
#define UART_INTSTS_MODEMIF_Pos (3) /*!< UART_T::INTSTS: MODEMIF Position */
#define UART_INTSTS_MODEMIF_Msk (0x1ul << UART_INTSTS_MODEMIF_Pos) /*!< UART_T::INTSTS: MODEMIF Mask */
#define UART_INTSTS_RXTOIF_Pos (4) /*!< UART_T::INTSTS: RXTOIF Position */
#define UART_INTSTS_RXTOIF_Msk (0x1ul << UART_INTSTS_RXTOIF_Pos) /*!< UART_T::INTSTS: RXTOIF Mask */
#define UART_INTSTS_BUFERRIF_Pos (5) /*!< UART_T::INTSTS: BUFERRIF Position */
#define UART_INTSTS_BUFERRIF_Msk (0x1ul << UART_INTSTS_BUFERRIF_Pos) /*!< UART_T::INTSTS: BUFERRIF Mask */
#define UART_INTSTS_WKIF_Pos (6) /*!< UART_T::INTSTS: WKIF Position */
#define UART_INTSTS_WKIF_Msk (0x1ul << UART_INTSTS_WKIF_Pos) /*!< UART_T::INTSTS: WKIF Mask */
#define UART_INTSTS_LINIF_Pos (7) /*!< UART_T::INTSTS: LINIF Position */
#define UART_INTSTS_LINIF_Msk (0x1ul << UART_INTSTS_LINIF_Pos) /*!< UART_T::INTSTS: LINIF Mask */
#define UART_INTSTS_RDAINT_Pos (8) /*!< UART_T::INTSTS: RDAINT Position */
#define UART_INTSTS_RDAINT_Msk (0x1ul << UART_INTSTS_RDAINT_Pos) /*!< UART_T::INTSTS: RDAINT Mask */
#define UART_INTSTS_THREINT_Pos (9) /*!< UART_T::INTSTS: THREINT Position */
#define UART_INTSTS_THREINT_Msk (0x1ul << UART_INTSTS_THREINT_Pos) /*!< UART_T::INTSTS: THREINT Mask */
#define UART_INTSTS_RLSINT_Pos (10) /*!< UART_T::INTSTS: RLSINT Position */
#define UART_INTSTS_RLSINT_Msk (0x1ul << UART_INTSTS_RLSINT_Pos) /*!< UART_T::INTSTS: RLSINT Mask */
#define UART_INTSTS_MODEMINT_Pos (11) /*!< UART_T::INTSTS: MODEMINT Position */
#define UART_INTSTS_MODEMINT_Msk (0x1ul << UART_INTSTS_MODEMINT_Pos) /*!< UART_T::INTSTS: MODEMINT Mask */
#define UART_INTSTS_RXTOINT_Pos (12) /*!< UART_T::INTSTS: RXTOINT Position */
#define UART_INTSTS_RXTOINT_Msk (0x1ul << UART_INTSTS_RXTOINT_Pos) /*!< UART_T::INTSTS: RXTOINT Mask */
#define UART_INTSTS_BUFERRINT_Pos (13) /*!< UART_T::INTSTS: BUFERRINT Position */
#define UART_INTSTS_BUFERRINT_Msk (0x1ul << UART_INTSTS_BUFERRINT_Pos) /*!< UART_T::INTSTS: BUFERRINT Mask */
#define UART_INTSTS_WKINT_Pos (14) /*!< UART_T::INTSTS: WKINT Position */
#define UART_INTSTS_WKINT_Msk (0x1ul << UART_INTSTS_WKINT_Pos) /*!< UART_T::INTSTS: WKINT Mask */
#define UART_INTSTS_LININT_Pos (15) /*!< UART_T::INTSTS: LININT Position */
#define UART_INTSTS_LININT_Msk (0x1ul << UART_INTSTS_LININT_Pos) /*!< UART_T::INTSTS: LININT Mask */
#define UART_INTSTS_HWRLSIF_Pos (18) /*!< UART_T::INTSTS: HWRLSIF Position */
#define UART_INTSTS_HWRLSIF_Msk (0x1ul << UART_INTSTS_HWRLSIF_Pos) /*!< UART_T::INTSTS: HWRLSIF Mask */
#define UART_INTSTS_HWMODIF_Pos (19) /*!< UART_T::INTSTS: HWMODIF Position */
#define UART_INTSTS_HWMODIF_Msk (0x1ul << UART_INTSTS_HWMODIF_Pos) /*!< UART_T::INTSTS: HWMODIF Mask */
#define UART_INTSTS_HWTOIF_Pos (20) /*!< UART_T::INTSTS: HWTOIF Position */
#define UART_INTSTS_HWTOIF_Msk (0x1ul << UART_INTSTS_HWTOIF_Pos) /*!< UART_T::INTSTS: HWTOIF Mask */
#define UART_INTSTS_HWBUFEIF_Pos (21) /*!< UART_T::INTSTS: HWBUFEIF Position */
#define UART_INTSTS_HWBUFEIF_Msk (0x1ul << UART_INTSTS_HWBUFEIF_Pos) /*!< UART_T::INTSTS: HWBUFEIF Mask */
#define UART_INTSTS_TXENDIF_Pos (22) /*!< UART_T::INTSTS: TXENDIF Position */
#define UART_INTSTS_TXENDIF_Msk (0x1ul << UART_INTSTS_TXENDIF_Pos) /*!< UART_T::INTSTS: TXENDIF Mask */
#define UART_INTSTS_HWRLSINT_Pos (26) /*!< UART_T::INTSTS: HWRLSINT Position */
#define UART_INTSTS_HWRLSINT_Msk (0x1ul << UART_INTSTS_HWRLSINT_Pos) /*!< UART_T::INTSTS: HWRLSINT Mask */
#define UART_INTSTS_HWMODINT_Pos (27) /*!< UART_T::INTSTS: HWMODINT Position */
#define UART_INTSTS_HWMODINT_Msk (0x1ul << UART_INTSTS_HWMODINT_Pos) /*!< UART_T::INTSTS: HWMODINT Mask */
#define UART_INTSTS_HWTOINT_Pos (28) /*!< UART_T::INTSTS: HWTOINT Position */
#define UART_INTSTS_HWTOINT_Msk (0x1ul << UART_INTSTS_HWTOINT_Pos) /*!< UART_T::INTSTS: HWTOINT Mask */
#define UART_INTSTS_HWBUFEINT_Pos (29) /*!< UART_T::INTSTS: HWBUFEINT Position */
#define UART_INTSTS_HWBUFEINT_Msk (0x1ul << UART_INTSTS_HWBUFEINT_Pos) /*!< UART_T::INTSTS: HWBUFEINT Mask */
#define UART_INTSTS_TXENDINT_Pos (30) /*!< UART_T::INTSTS: TXENDINT Position */
#define UART_INTSTS_TXENDINT_Msk (0x1ul << UART_INTSTS_TXENDINT_Pos) /*!< UART_T::INTSTS: TXENDINT Mask */
#define UART_INTSTS_ABRINT_Pos (31) /*!< UART_T::INTSTS: ABRINT Position */
#define UART_INTSTS_ABRINT_Msk (0x1ul << UART_INTSTS_ABRINT_Pos) /*!< UART_T::INTSTS: ABRINT Mask */
#define UART_TOUT_TOIC_Pos (0) /*!< UART_T::TOUT: TOIC Position */
#define UART_TOUT_TOIC_Msk (0xfful << UART_TOUT_TOIC_Pos) /*!< UART_T::TOUT: TOIC Mask */
#define UART_TOUT_DLY_Pos (8) /*!< UART_T::TOUT: DLY Position */
#define UART_TOUT_DLY_Msk (0xfful << UART_TOUT_DLY_Pos) /*!< UART_T::TOUT: DLY Mask */
#define UART_BAUD_BRD_Pos (0) /*!< UART_T::BAUD: BRD Position */
#define UART_BAUD_BRD_Msk (0xfffful << UART_BAUD_BRD_Pos) /*!< UART_T::BAUD: BRD Mask */
#define UART_BAUD_EDIVM1_Pos (24) /*!< UART_T::BAUD: EDIVM1 Position */
#define UART_BAUD_EDIVM1_Msk (0xful << UART_BAUD_EDIVM1_Pos) /*!< UART_T::BAUD: EDIVM1 Mask */
#define UART_BAUD_BAUDM0_Pos (28) /*!< UART_T::BAUD: BAUDM0 Position */
#define UART_BAUD_BAUDM0_Msk (0x1ul << UART_BAUD_BAUDM0_Pos) /*!< UART_T::BAUD: BAUDM0 Mask */
#define UART_BAUD_BAUDM1_Pos (29) /*!< UART_T::BAUD: BAUDM1 Position */
#define UART_BAUD_BAUDM1_Msk (0x1ul << UART_BAUD_BAUDM1_Pos) /*!< UART_T::BAUD: BAUDM1 Mask */
#define UART_IRDA_TXEN_Pos (1) /*!< UART_T::IRDA: TXEN Position */
#define UART_IRDA_TXEN_Msk (0x1ul << UART_IRDA_TXEN_Pos) /*!< UART_T::IRDA: TXEN Mask */
#define UART_IRDA_TXINV_Pos (5) /*!< UART_T::IRDA: TXINV Position */
#define UART_IRDA_TXINV_Msk (0x1ul << UART_IRDA_TXINV_Pos) /*!< UART_T::IRDA: TXINV Mask */
#define UART_IRDA_RXINV_Pos (6) /*!< UART_T::IRDA: RXINV Position */
#define UART_IRDA_RXINV_Msk (0x1ul << UART_IRDA_RXINV_Pos) /*!< UART_T::IRDA: RXINV Mask */
#define UART_ALTCTL_BRKFL_Pos (0) /*!< UART_T::ALTCTL: BRKFL Position */
#define UART_ALTCTL_BRKFL_Msk (0xful << UART_ALTCTL_BRKFL_Pos) /*!< UART_T::ALTCTL: BRKFL Mask */
#define UART_ALTCTL_LINRXEN_Pos (6) /*!< UART_T::ALTCTL: LINRXEN Position */
#define UART_ALTCTL_LINRXEN_Msk (0x1ul << UART_ALTCTL_LINRXEN_Pos) /*!< UART_T::ALTCTL: LINRXEN Mask */
#define UART_ALTCTL_LINTXEN_Pos (7) /*!< UART_T::ALTCTL: LINTXEN Position */
#define UART_ALTCTL_LINTXEN_Msk (0x1ul << UART_ALTCTL_LINTXEN_Pos) /*!< UART_T::ALTCTL: LINTXEN Mask */
#define UART_ALTCTL_RS485NMM_Pos (8) /*!< UART_T::ALTCTL: RS485NMM Position */
#define UART_ALTCTL_RS485NMM_Msk (0x1ul << UART_ALTCTL_RS485NMM_Pos) /*!< UART_T::ALTCTL: RS485NMM Mask */
#define UART_ALTCTL_RS485AAD_Pos (9) /*!< UART_T::ALTCTL: RS485AAD Position */
#define UART_ALTCTL_RS485AAD_Msk (0x1ul << UART_ALTCTL_RS485AAD_Pos) /*!< UART_T::ALTCTL: RS485AAD Mask */
#define UART_ALTCTL_RS485AUD_Pos (10) /*!< UART_T::ALTCTL: RS485AUD Position */
#define UART_ALTCTL_RS485AUD_Msk (0x1ul << UART_ALTCTL_RS485AUD_Pos) /*!< UART_T::ALTCTL: RS485AUD Mask */
#define UART_ALTCTL_ADDRDEN_Pos (15) /*!< UART_T::ALTCTL: ADDRDEN Position */
#define UART_ALTCTL_ADDRDEN_Msk (0x1ul << UART_ALTCTL_ADDRDEN_Pos) /*!< UART_T::ALTCTL: ADDRDEN Mask */
#define UART_ALTCTL_ABRIF_Pos (17) /*!< UART_T::ALTCTL: ABRIF Position */
#define UART_ALTCTL_ABRIF_Msk (0x1ul << UART_ALTCTL_ABRIF_Pos) /*!< UART_T::ALTCTL: ABRIF Mask */
#define UART_ALTCTL_ABRDEN_Pos (18) /*!< UART_T::ALTCTL: ABRDEN Position */
#define UART_ALTCTL_ABRDEN_Msk (0x1ul << UART_ALTCTL_ABRDEN_Pos) /*!< UART_T::ALTCTL: ABRDEN Mask */
#define UART_ALTCTL_ABRDBITS_Pos (19) /*!< UART_T::ALTCTL: ABRDBITS Position */
#define UART_ALTCTL_ABRDBITS_Msk (0x3ul << UART_ALTCTL_ABRDBITS_Pos) /*!< UART_T::ALTCTL: ABRDBITS Mask */
#define UART_ALTCTL_ADDRMV_Pos (24) /*!< UART_T::ALTCTL: ADDRMV Position */
#define UART_ALTCTL_ADDRMV_Msk (0xfful << UART_ALTCTL_ADDRMV_Pos) /*!< UART_T::ALTCTL: ADDRMV Mask */
#define UART_FUNCSEL_FUNCSEL_Pos (0) /*!< UART_T::FUNCSEL: FUNCSEL Position */
#define UART_FUNCSEL_FUNCSEL_Msk (0x3ul << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_T::FUNCSEL: FUNCSEL Mask */
#define UART_FUNCSEL_TXRXDIS_Pos (3) /*!< UART_T::FUNCSEL: TXRXDIS Position */
#define UART_FUNCSEL_TXRXDIS_Msk (0x1ul << UART_FUNCSEL_TXRXDIS_Pos) /*!< UART_T::FUNCSEL: TXRXDIS Mask */
#define UART_LINCTL_SLVEN_Pos (0) /*!< UART_T::LINCTL: SLVEN Position */
#define UART_LINCTL_SLVEN_Msk (0x1ul << UART_LINCTL_SLVEN_Pos) /*!< UART_T::LINCTL: SLVEN Mask */
#define UART_LINCTL_SLVHDEN_Pos (1) /*!< UART_T::LINCTL: SLVHDEN Position */
#define UART_LINCTL_SLVHDEN_Msk (0x1ul << UART_LINCTL_SLVHDEN_Pos) /*!< UART_T::LINCTL: SLVHDEN Mask */
#define UART_LINCTL_SLVAREN_Pos (2) /*!< UART_T::LINCTL: SLVAREN Position */
#define UART_LINCTL_SLVAREN_Msk (0x1ul << UART_LINCTL_SLVAREN_Pos) /*!< UART_T::LINCTL: SLVAREN Mask */
#define UART_LINCTL_SLVDUEN_Pos (3) /*!< UART_T::LINCTL: SLVDUEN Position */
#define UART_LINCTL_SLVDUEN_Msk (0x1ul << UART_LINCTL_SLVDUEN_Pos) /*!< UART_T::LINCTL: SLVDUEN Mask */
#define UART_LINCTL_MUTE_Pos (4) /*!< UART_T::LINCTL: MUTE Position */
#define UART_LINCTL_MUTE_Msk (0x1ul << UART_LINCTL_MUTE_Pos) /*!< UART_T::LINCTL: MUTE Mask */
#define UART_LINCTL_SENDH_Pos (8) /*!< UART_T::LINCTL: SENDH Position */
#define UART_LINCTL_SENDH_Msk (0x1ul << UART_LINCTL_SENDH_Pos) /*!< UART_T::LINCTL: SENDH Mask */
#define UART_LINCTL_IDPEN_Pos (9) /*!< UART_T::LINCTL: IDPEN Position */
#define UART_LINCTL_IDPEN_Msk (0x1ul << UART_LINCTL_IDPEN_Pos) /*!< UART_T::LINCTL: IDPEN Mask */
#define UART_LINCTL_BRKDETEN_Pos (10) /*!< UART_T::LINCTL: BRKDETEN Position */
#define UART_LINCTL_BRKDETEN_Msk (0x1ul << UART_LINCTL_BRKDETEN_Pos) /*!< UART_T::LINCTL: BRKDETEN Mask */
#define UART_LINCTL_LINRXOFF_Pos (11) /*!< UART_T::LINCTL: LINRXOFF Position */
#define UART_LINCTL_LINRXOFF_Msk (0x1ul << UART_LINCTL_LINRXOFF_Pos) /*!< UART_T::LINCTL: LINRXOFF Mask */
#define UART_LINCTL_BITERREN_Pos (12) /*!< UART_T::LINCTL: BITERREN Position */
#define UART_LINCTL_BITERREN_Msk (0x1ul << UART_LINCTL_BITERREN_Pos) /*!< UART_T::LINCTL: BITERREN Mask */
#define UART_LINCTL_BRKFL_Pos (16) /*!< UART_T::LINCTL: BRKFL Position */
#define UART_LINCTL_BRKFL_Msk (0xful << UART_LINCTL_BRKFL_Pos) /*!< UART_T::LINCTL: BRKFL Mask */
#define UART_LINCTL_BSL_Pos (20) /*!< UART_T::LINCTL: BSL Position */
#define UART_LINCTL_BSL_Msk (0x3ul << UART_LINCTL_BSL_Pos) /*!< UART_T::LINCTL: BSL Mask */
#define UART_LINCTL_HSEL_Pos (22) /*!< UART_T::LINCTL: HSEL Position */
#define UART_LINCTL_HSEL_Msk (0x3ul << UART_LINCTL_HSEL_Pos) /*!< UART_T::LINCTL: HSEL Mask */
#define UART_LINCTL_PID_Pos (24) /*!< UART_T::LINCTL: PID Position */
#define UART_LINCTL_PID_Msk (0xfful << UART_LINCTL_PID_Pos) /*!< UART_T::LINCTL: PID Mask */
#define UART_LINSTS_SLVHDETF_Pos (0) /*!< UART_T::LINSTS: SLVHDETF Position */
#define UART_LINSTS_SLVHDETF_Msk (0x1ul << UART_LINSTS_SLVHDETF_Pos) /*!< UART_T::LINSTS: SLVHDETF Mask */
#define UART_LINSTS_SLVHEF_Pos (1) /*!< UART_T::LINSTS: SLVHEF Position */
#define UART_LINSTS_SLVHEF_Msk (0x1ul << UART_LINSTS_SLVHEF_Pos) /*!< UART_T::LINSTS: SLVHEF Mask */
#define UART_LINSTS_SLVIDPEF_Pos (2) /*!< UART_T::LINSTS: SLVIDPEF Position */
#define UART_LINSTS_SLVIDPEF_Msk (0x1ul << UART_LINSTS_SLVIDPEF_Pos) /*!< UART_T::LINSTS: SLVIDPEF Mask */
#define UART_LINSTS_SLVSYNCF_Pos (3) /*!< UART_T::LINSTS: SLVSYNCF Position */
#define UART_LINSTS_SLVSYNCF_Msk (0x1ul << UART_LINSTS_SLVSYNCF_Pos) /*!< UART_T::LINSTS: SLVSYNCF Mask */
#define UART_LINSTS_BRKDETF_Pos (8) /*!< UART_T::LINSTS: BRKDETF Position */
#define UART_LINSTS_BRKDETF_Msk (0x1ul << UART_LINSTS_BRKDETF_Pos) /*!< UART_T::LINSTS: BRKDETF Mask */
#define UART_LINSTS_BITEF_Pos (9) /*!< UART_T::LINSTS: BITEF Position */
#define UART_LINSTS_BITEF_Msk (0x1ul << UART_LINSTS_BITEF_Pos) /*!< UART_T::LINSTS: BITEF Mask */
#define UART_BRCOMP_BRCOMP_Pos (0) /*!< UART_T::BRCOMP: BRCOMP Position */
#define UART_BRCOMP_BRCOMP_Msk (0x1fful << UART_BRCOMP_BRCOMP_Pos) /*!< UART_T::BRCOMP: BRCOMP Mask */
#define UART_BRCOMP_BRCOMPDEC_Pos (31) /*!< UART_T::BRCOMP: BRCOMPDEC Position */
#define UART_BRCOMP_BRCOMPDEC_Msk (0x1ul << UART_BRCOMP_BRCOMPDEC_Pos) /*!< UART_T::BRCOMP: BRCOMPDEC Mask */
#define UART_WKCTL_WKCTSEN_Pos (0) /*!< UART_T::WKCTL: WKCTSEN Position */
#define UART_WKCTL_WKCTSEN_Msk (0x1ul << UART_WKCTL_WKCTSEN_Pos) /*!< UART_T::WKCTL: WKCTSEN Mask */
#define UART_WKCTL_WKDATEN_Pos (1) /*!< UART_T::WKCTL: WKDATEN Position */
#define UART_WKCTL_WKDATEN_Msk (0x1ul << UART_WKCTL_WKDATEN_Pos) /*!< UART_T::WKCTL: WKDATEN Mask */
#define UART_WKCTL_WKRFRTEN_Pos (2) /*!< UART_T::WKCTL: WKRFRTEN Position */
#define UART_WKCTL_WKRFRTEN_Msk (0x1ul << UART_WKCTL_WKRFRTEN_Pos) /*!< UART_T::WKCTL: WKRFRTEN Mask */
#define UART_WKCTL_WKRS485EN_Pos (3) /*!< UART_T::WKCTL: WKRS485EN Position */
#define UART_WKCTL_WKRS485EN_Msk (0x1ul << UART_WKCTL_WKRS485EN_Pos) /*!< UART_T::WKCTL: WKRS485EN Mask */
#define UART_WKCTL_WKTOUTEN_Pos (4) /*!< UART_T::WKCTL: WKTOUTEN Position */
#define UART_WKCTL_WKTOUTEN_Msk (0x1ul << UART_WKCTL_WKTOUTEN_Pos) /*!< UART_T::WKCTL: WKTOUTEN Mask */
#define UART_WKSTS_CTSWKF_Pos (0) /*!< UART_T::WKSTS: CTSWKF Position */
#define UART_WKSTS_CTSWKF_Msk (0x1ul << UART_WKSTS_CTSWKF_Pos) /*!< UART_T::WKSTS: CTSWKF Mask */
#define UART_WKSTS_DATWKF_Pos (1) /*!< UART_T::WKSTS: DATWKF Position */
#define UART_WKSTS_DATWKF_Msk (0x1ul << UART_WKSTS_DATWKF_Pos) /*!< UART_T::WKSTS: DATWKF Mask */
#define UART_WKSTS_RFRTWKF_Pos (2) /*!< UART_T::WKSTS: RFRTWKF Position */
#define UART_WKSTS_RFRTWKF_Msk (0x1ul << UART_WKSTS_RFRTWKF_Pos) /*!< UART_T::WKSTS: RFRTWKF Mask */
#define UART_WKSTS_RS485WKF_Pos (3) /*!< UART_T::WKSTS: RS485WKF Position */
#define UART_WKSTS_RS485WKF_Msk (0x1ul << UART_WKSTS_RS485WKF_Pos) /*!< UART_T::WKSTS: RS485WKF Mask */
#define UART_WKSTS_TOUTWKF_Pos (4) /*!< UART_T::WKSTS: TOUTWKF Position */
#define UART_WKSTS_TOUTWKF_Msk (0x1ul << UART_WKSTS_TOUTWKF_Pos) /*!< UART_T::WKSTS: TOUTWKF Mask */
#define UART_DWKCOMP_STCOMP_Pos (0) /*!< UART_T::DWKCOMP: STCOMP Position */
#define UART_DWKCOMP_STCOMP_Msk (0xfffful << UART_DWKCOMP_STCOMP_Pos) /*!< UART_T::DWKCOMP: STCOMP Mask */
/**@}*/ /* UART_CONST */
/**@}*/ /* end of UART register group */
/*---------------------- Ethernet MAC Controller -------------------------*/
/**
@addtogroup EMAC Ethernet MAC Controller(EMAC)
Memory Mapped Structure for EMAC Controller
@{ */
typedef struct {
/**
* @var EMAC_T::CAMCTL
* Offset: 0x00 CAM Comparison Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |AUP |Accept Unicast Packet
* | | |The AUP controls the unicast packet reception
* | | |If AUP is enabled, EMAC receives all incoming packet its destination MAC address is a unicast address.
* | | |0 = EMAC receives packet depends on the CAM comparison result.
* | | |1 = EMAC receives all unicast packets.
* |[1] |AMP |Accept Multicast Packet
* | | |The AMP controls the multicast packet reception
* | | |If AMP is enabled, EMAC receives all incoming packet its destination MAC address is a multicast address.
* | | |0 = EMAC receives packet depends on the CAM comparison result.
* | | |1 = EMAC receives all multicast packets.
* |[2] |ABP |Accept Broadcast Packet
* | | |The ABP controls the broadcast packet reception
* | | |If ABP is enabled, EMAC receives all incoming packet its destination MAC address is a broadcast address.
* | | |0 = EMAC receives packet depends on the CAM comparison result.
* | | |1 = EMAC receives all broadcast packets.
* |[3] |COMPEN |Complement CAM Comparison Enable Bit
* | | |The COMPEN controls the complement of the CAM comparison result
* | | |If the CMPEN and COMPEN are both enabled, the incoming packet with specific destination MAC address
* | | |configured in CAM entry will be dropped
* | | |And the incoming packet with destination MAC address does not configured in any CAM entry will be received.
* | | |0 = Complement CAM comparison result Disabled.
* | | |1 = Complement CAM comparison result Enabled.
* |[4] |CMPEN |CAM Compare Enable Bit
* | | |The CMPEN controls the enable of CAM comparison function for destination MAC address recognition
* | | |If software wants to receive a packet with specific destination MAC address, configures the MAC address
* | | |into CAM 12~0, then enables that CAM entry and set CMPEN to 1.
* | | |0 = CAM comparison function for destination MAC address recognition Disabled.
* | | |1 = CAM comparison function for destination MAC address recognition Enabled.
* @var EMAC_T::CAMEN
* Offset: 0x04 CAM Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CAMxEN |CAM Entry X Enable Bit
* | | |The CAMxEN controls the validation of CAM entry x.
* | | |The CAM entry 13, 14 and 15 are for PAUSE control frame transmission
* | | |If software wants to transmit a PAUSE control frame out to network, the enable bits of these three CAM
* | | |entries all must be enabled first.
* | | |0 = CAM entry x Disabled.
* | | |1 = CAM entry x Enabled.
* @var EMAC_T::CAM0M
* Offset: 0x08 CAM0 Most Significant Word Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |MACADDR2 |MAC Address Byte 2
* |[15:8] |MACADDR3 |MAC Address Byte 3
* |[23:16] |MACADDR4 |MAC Address Byte 4
* |[31:24] |MACADDR5 |MAC Address Byte 5
* | | |The CAMxM keeps the bit 47~16 of MAC address
* | | |The x can be the 0~14
* | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
* | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
* | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
* @var EMAC_T::CAM0L
* Offset: 0x0C CAM0 Least Significant Word Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[23:16] |MACADDR0 |MAC Address Byte 0
* |[31:24] |MACADDR1 |MAC Address Byte 1
* | | |The CAMxL keeps the bit 15~0 of MAC address
* | | |The x can be the 0~14
* | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
* | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
* | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
* @var EMAC_T::CAM1M
* Offset: 0x10 CAM1 Most Significant Word Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |MACADDR2 |MAC Address Byte 2
* |[15:8] |MACADDR3 |MAC Address Byte 3
* |[23:16] |MACADDR4 |MAC Address Byte 4
* |[31:24] |MACADDR5 |MAC Address Byte 5
* | | |The CAMxM keeps the bit 47~16 of MAC address
* | | |The x can be the 0~14
* | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
* | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
* | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
* @var EMAC_T::CAM1L
* Offset: 0x14 CAM1 Least Significant Word Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[23:16] |MACADDR0 |MAC Address Byte 0
* |[31:24] |MACADDR1 |MAC Address Byte 1
* | | |The CAMxL keeps the bit 15~0 of MAC address
* | | |The x can be the 0~14
* | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
* | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
* | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
* @var EMAC_T::CAM2M
* Offset: 0x18 CAM2 Most Significant Word Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |MACADDR2 |MAC Address Byte 2
* |[15:8] |MACADDR3 |MAC Address Byte 3
* |[23:16] |MACADDR4 |MAC Address Byte 4
* |[31:24] |MACADDR5 |MAC Address Byte 5
* | | |The CAMxM keeps the bit 47~16 of MAC address
* | | |The x can be the 0~14
* | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
* | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
* | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
* @var EMAC_T::CAM2L
* Offset: 0x1C CAM2 Least Significant Word Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[23:16] |MACADDR0 |MAC Address Byte 0
* |[31:24] |MACADDR1 |MAC Address Byte 1
* | | |The CAMxL keeps the bit 15~0 of MAC address
* | | |The x can be the 0~14
* | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
* | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
* | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
* @var EMAC_T::CAM3M
* Offset: 0x20 CAM3 Most Significant Word Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |MACADDR2 |MAC Address Byte 2
* |[15:8] |MACADDR3 |MAC Address Byte 3
* |[23:16] |MACADDR4 |MAC Address Byte 4
* |[31:24] |MACADDR5 |MAC Address Byte 5
* | | |The CAMxM keeps the bit 47~16 of MAC address
* | | |The x can be the 0~14
* | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
* | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
* | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
* @var EMAC_T::CAM3L
* Offset: 0x24 CAM3 Least Significant Word Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[23:16] |MACADDR0 |MAC Address Byte 0
* |[31:24] |MACADDR1 |MAC Address Byte 1
* | | |The CAMxL keeps the bit 15~0 of MAC address
* | | |The x can be the 0~14
* | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
* | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
* | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
* @var EMAC_T::CAM4M
* Offset: 0x28 CAM4 Most Significant Word Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |MACADDR2 |MAC Address Byte 2
* |[15:8] |MACADDR3 |MAC Address Byte 3
* |[23:16] |MACADDR4 |MAC Address Byte 4
* |[31:24] |MACADDR5 |MAC Address Byte 5
* | | |The CAMxM keeps the bit 47~16 of MAC address
* | | |The x can be the 0~14
* | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
* | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
* | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
* @var EMAC_T::CAM4L
* Offset: 0x2C CAM4 Least Significant Word Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[23:16] |MACADDR0 |MAC Address Byte 0
* |[31:24] |MACADDR1 |MAC Address Byte 1
* | | |The CAMxL keeps the bit 15~0 of MAC address
* | | |The x can be the 0~14
* | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
* | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
* | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
* @var EMAC_T::CAM5M
* Offset: 0x30 CAM5 Most Significant Word Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |MACADDR2 |MAC Address Byte 2
* |[15:8] |MACADDR3 |MAC Address Byte 3
* |[23:16] |MACADDR4 |MAC Address Byte 4
* |[31:24] |MACADDR5 |MAC Address Byte 5
* | | |The CAMxM keeps the bit 47~16 of MAC address
* | | |The x can be the 0~14
* | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
* | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
* | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
* @var EMAC_T::CAM5L
* Offset: 0x34 CAM5 Least Significant Word Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[23:16] |MACADDR0 |MAC Address Byte 0
* |[31:24] |MACADDR1 |MAC Address Byte 1
* | | |The CAMxL keeps the bit 15~0 of MAC address
* | | |The x can be the 0~14
* | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
* | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
* | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
* @var EMAC_T::CAM6M
* Offset: 0x38 CAM6 Most Significant Word Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |MACADDR2 |MAC Address Byte 2
* |[15:8] |MACADDR3 |MAC Address Byte 3
* |[23:16] |MACADDR4 |MAC Address Byte 4
* |[31:24] |MACADDR5 |MAC Address Byte 5
* | | |The CAMxM keeps the bit 47~16 of MAC address
* | | |The x can be the 0~14
* | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
* | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
* | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
* @var EMAC_T::CAM6L
* Offset: 0x3C CAM6 Least Significant Word Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[23:16] |MACADDR0 |MAC Address Byte 0
* |[31:24] |MACADDR1 |MAC Address Byte 1
* | | |The CAMxL keeps the bit 15~0 of MAC address
* | | |The x can be the 0~14
* | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
* | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
* | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
* @var EMAC_T::CAM7M
* Offset: 0x40 CAM7 Most Significant Word Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |MACADDR2 |MAC Address Byte 2
* |[15:8] |MACADDR3 |MAC Address Byte 3
* |[23:16] |MACADDR4 |MAC Address Byte 4
* |[31:24] |MACADDR5 |MAC Address Byte 5
* | | |The CAMxM keeps the bit 47~16 of MAC address
* | | |The x can be the 0~14
* | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
* | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
* | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
* @var EMAC_T::CAM7L
* Offset: 0x44 CAM7 Least Significant Word Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[23:16] |MACADDR0 |MAC Address Byte 0
* |[31:24] |MACADDR1 |MAC Address Byte 1
* | | |The CAMxL keeps the bit 15~0 of MAC address
* | | |The x can be the 0~14
* | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
* | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
* | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
* @var EMAC_T::CAM8M
* Offset: 0x48 CAM8 Most Significant Word Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |MACADDR2 |MAC Address Byte 2
* |[15:8] |MACADDR3 |MAC Address Byte 3
* |[23:16] |MACADDR4 |MAC Address Byte 4
* |[31:24] |MACADDR5 |MAC Address Byte 5
* | | |The CAMxM keeps the bit 47~16 of MAC address
* | | |The x can be the 0~14
* | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
* | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
* | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
* @var EMAC_T::CAM8L
* Offset: 0x4C CAM8 Least Significant Word Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[23:16] |MACADDR0 |MAC Address Byte 0
* |[31:24] |MACADDR1 |MAC Address Byte 1
* | | |The CAMxL keeps the bit 15~0 of MAC address
* | | |The x can be the 0~14
* | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
* | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
* | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
* @var EMAC_T::CAM9M
* Offset: 0x50 CAM9 Most Significant Word Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |MACADDR2 |MAC Address Byte 2
* |[15:8] |MACADDR3 |MAC Address Byte 3
* |[23:16] |MACADDR4 |MAC Address Byte 4
* |[31:24] |MACADDR5 |MAC Address Byte 5
* | | |The CAMxM keeps the bit 47~16 of MAC address
* | | |The x can be the 0~14
* | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
* | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
* | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
* @var EMAC_T::CAM9L
* Offset: 0x54 CAM9 Least Significant Word Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[23:16] |MACADDR0 |MAC Address Byte 0
* |[31:24] |MACADDR1 |MAC Address Byte 1
* | | |The CAMxL keeps the bit 15~0 of MAC address
* | | |The x can be the 0~14
* | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
* | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
* | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
* @var EMAC_T::CAM10M
* Offset: 0x58 CAM10 Most Significant Word Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |MACADDR2 |MAC Address Byte 2
* |[15:8] |MACADDR3 |MAC Address Byte 3
* |[23:16] |MACADDR4 |MAC Address Byte 4
* |[31:24] |MACADDR5 |MAC Address Byte 5
* | | |The CAMxM keeps the bit 47~16 of MAC address
* | | |The x can be the 0~14
* | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
* | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
* | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
* @var EMAC_T::CAM10L
* Offset: 0x5C CAM10 Least Significant Word Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[23:16] |MACADDR0 |MAC Address Byte 0
* |[31:24] |MACADDR1 |MAC Address Byte 1
* | | |The CAMxL keeps the bit 15~0 of MAC address
* | | |The x can be the 0~14
* | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
* | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
* | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
* @var EMAC_T::CAM11M
* Offset: 0x60 CAM11 Most Significant Word Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |MACADDR2 |MAC Address Byte 2
* |[15:8] |MACADDR3 |MAC Address Byte 3
* |[23:16] |MACADDR4 |MAC Address Byte 4
* |[31:24] |MACADDR5 |MAC Address Byte 5
* | | |The CAMxM keeps the bit 47~16 of MAC address
* | | |The x can be the 0~14
* | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
* | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
* | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
* @var EMAC_T::CAM11L
* Offset: 0x64 CAM11 Least Significant Word Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[23:16] |MACADDR0 |MAC Address Byte 0
* |[31:24] |MACADDR1 |MAC Address Byte 1
* | | |The CAMxL keeps the bit 15~0 of MAC address
* | | |The x can be the 0~14
* | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
* | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
* | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
* @var EMAC_T::CAM12M
* Offset: 0x68 CAM12 Most Significant Word Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |MACADDR2 |MAC Address Byte 2
* |[15:8] |MACADDR3 |MAC Address Byte 3
* |[23:16] |MACADDR4 |MAC Address Byte 4
* |[31:24] |MACADDR5 |MAC Address Byte 5
* | | |The CAMxM keeps the bit 47~16 of MAC address
* | | |The x can be the 0~14
* | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
* | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
* | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
* @var EMAC_T::CAM12L
* Offset: 0x6C CAM12 Least Significant Word Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[23:16] |MACADDR0 |MAC Address Byte 0
* |[31:24] |MACADDR1 |MAC Address Byte 1
* | | |The CAMxL keeps the bit 15~0 of MAC address
* | | |The x can be the 0~14
* | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
* | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
* | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
* @var EMAC_T::CAM13M
* Offset: 0x70 CAM13 Most Significant Word Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |MACADDR2 |MAC Address Byte 2
* |[15:8] |MACADDR3 |MAC Address Byte 3
* |[23:16] |MACADDR4 |MAC Address Byte 4
* |[31:24] |MACADDR5 |MAC Address Byte 5
* | | |The CAMxM keeps the bit 47~16 of MAC address
* | | |The x can be the 0~14
* | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
* | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
* | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
* @var EMAC_T::CAM13L
* Offset: 0x74 CAM13 Least Significant Word Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[23:16] |MACADDR0 |MAC Address Byte 0
* |[31:24] |MACADDR1 |MAC Address Byte 1
* | | |The CAMxL keeps the bit 15~0 of MAC address
* | | |The x can be the 0~14
* | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
* | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
* | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
* @var EMAC_T::CAM14M
* Offset: 0x78 CAM14 Most Significant Word Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |MACADDR2 |MAC Address Byte 2
* |[15:8] |MACADDR3 |MAC Address Byte 3
* |[23:16] |MACADDR4 |MAC Address Byte 4
* |[31:24] |MACADDR5 |MAC Address Byte 5
* | | |The CAMxM keeps the bit 47~16 of MAC address
* | | |The x can be the 0~14
* | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
* | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
* | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
* @var EMAC_T::CAM14L
* Offset: 0x7C CAM14 Least Significant Word Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[23:16] |MACADDR0 |MAC Address Byte 0
* |[31:24] |MACADDR1 |MAC Address Byte 1
* | | |The CAMxL keeps the bit 15~0 of MAC address
* | | |The x can be the 0~14
* | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
* | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
* | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
* @var EMAC_T::CAM15MSB
* Offset: 0x80 CAM15 Most Significant Word Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |OPCODE |OP Code Field of PAUSE Control Frame
* | | |In the PAUSE control frame, an op code field defined and is 0x0001.
* |[31:16] |LENGTH |LENGTH Field of PAUSE Control Frame
* | | |In the PAUSE control frame, a LENGTH field defined and is 0x8808.
* @var EMAC_T::CAM15LSB
* Offset: 0x84 CAM15 Least Significant Word Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:24] |OPERAND |Pause Parameter
* | | |In the PAUSE control frame, an OPERAND field defined and controls how much time the destination
* | | |Ethernet MAC Controller paused
* | | |The unit of the OPERAND is a slot time, the 512-bit time.
* @var EMAC_T::TXDSA
* Offset: 0x88 Transmit Descriptor Link List Start Address Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |TXDSA |Transmit Descriptor Link-list Start Address
* | | |The TXDSA keeps the start address of transmit descriptor link-list
* | | |If the software enables the bit TXON (EMAC_CTL[8]), the content of TXDSA will be loaded into the
* | | |current transmit descriptor start address register (EMAC_CTXDSA)
* | | |The TXDSA does not be updated by EMAC
* | | |During the operation, EMAC will ignore the bits [1:0] of TXDSA
* | | |This means that TX descriptors must locate at word boundary memory address.
* @var EMAC_T::RXDSA
* Offset: 0x8C Receive Descriptor Link List Start Address Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |RXDSA |Receive Descriptor Link-list Start Address
* | | |The RXDSA keeps the start address of receive descriptor link-list
* | | |If the S/W enables the bit RXON (EMAC_CTL[0]), the content of RXDSA will be loaded into the current
* | | |receive descriptor start address register (EMAC_CRXDSA)
* | | |The RXDSA does not be updated by EMAC
* | | |During the operation, EMAC will ignore the bits [1:0] of RXDSA
* | | |This means that RX descriptors must locate at word boundary memory address.
* @var EMAC_T::CTL
* Offset: 0x90 MAC Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |RXON |Frame Reception ON
* | | |The RXON controls the normal packet reception of EMAC
* | | |If the RXON is set to high, the EMAC starts the packet reception process, including the RX
* | | |descriptor fetching, packet reception and RX descriptor modification.
* | | |It is necessary to finish EMAC initial sequence before enable RXON
* | | |Otherwise, the EMAC operation is undefined.
* | | |If the RXON is disabled during EMAC is receiving an incoming packet, the EMAC stops the packet
* | | |reception process after the current packet reception finished.
* | | |0 = Packet reception process stopped.
* | | |1 = Packet reception process started.
* |[1] |ALP |Accept Long Packet
* | | |The ALP controls the long packet, which packet length is greater than 1518 bytes, reception
* | | |If the ALP is set to high, the EMAC will accept the long packet.
* | | |Otherwise, the long packet will be dropped.
* | | |0 = Ethernet MAC controller dropped the long packet.
* | | |1 = Ethernet MAC controller received the long packet.
* |[2] |ARP |Accept Runt Packet
* | | |The ARP controls the runt packet, which length is less than 64 bytes, reception
* | | |If the ARP is set to high, the EMAC will accept the runt packet.
* | | |Otherwise, the runt packet will be dropped.
* | | |0 = Ethernet MAC controller dropped the runt packet.
* | | |1 = Ethernet MAC controller received the runt packet.
* |[3] |ACP |Accept Control Packet
* | | |The ACP controls the control frame reception
* | | |If the ACP is set to high, the EMAC will accept the control frame
* | | |Otherwise, the control frame will be dropped
* | | |It is recommended that S/W only enable ACP while EMAC is operating on full duplex mode.
* | | |0 = Ethernet MAC controller dropped the control frame.
* | | |1 = Ethernet MAC controller received the control frame.
* |[4] |AEP |Accept CRC Error Packet
* | | |The AEP controls the EMAC accepts or drops the CRC error packet
* | | |If the AEP is set to high, the incoming packet with CRC error will be received by EMAC as a good packet.
* | | |0 = Ethernet MAC controller dropped the CRC error packet.
* | | |1 = Ethernet MAC controller received the CRC error packet.
* |[5] |STRIPCRC |Strip CRC Checksum
* | | |The STRIPCRC controls if the length of incoming packet is calculated with 4 bytes CRC checksum
* | | |If the STRIPCRC is set to high, 4 bytes CRC checksum is excluded from length calculation of incoming packet.
* | | |0 = The 4 bytes CRC checksum is included in packet length calculation.
* | | |1 = The 4 bytes CRC checksum is excluded in packet length calculation.
* |[6] |WOLEN |Wake on LAN Enable Bit
* | | |The WOLEN high enables the functionality that Ethernet MAC controller checked if the incoming packet
* | | |is Magic Packet and wakeup system from Power-down mode.
* | | |If incoming packet was a Magic Packet and the system was in Power-down, the Ethernet MAC controller
* | | |would generate a wakeup event to wake system up from Power-down mode.
* | | |0 = Wake-up by Magic Packet function Disabled.
* | | |1 = Wake-up by Magic Packet function Enabled.
* |[8] |TXON |Frame Transmission ON
* | | |The TXON controls the normal packet transmission of EMAC
* | | |If the TXON is set to high, the EMAC starts the packet transmission process, including the TX
* | | |descriptor fetching, packet transmission and TX descriptor modification.
* | | |It is must to finish EMAC initial sequence before enable TXON
* | | |Otherwise, the EMAC operation is undefined.
* | | |If the TXON is disabled during EMAC is transmitting a packet out, the EMAC stops the packet
* | | |transmission process after the current packet transmission finished.
* | | |0 = Packet transmission process stopped.
* | | |1 = Packet transmission process started.
* |[9] |NODEF |No Deferral
* | | |The NODEF controls the enable of deferral exceed counter
* | | |If NODEF is set to high, the deferral exceed counter is disabled
* | | |The NODEF is only useful while EMAC is operating on half duplex mode.
* | | |0 = The deferral exceed counter Enabled.
* | | |1 = The deferral exceed counter Disabled.
* |[16] |SDPZ |Send PAUSE Frame
* | | |The SDPZ controls the PAUSE control frame transmission.
* | | |If S/W wants to send a PAUSE control frame out, the CAM entry 13, 14 and 15 must be configured
* | | |first and the corresponding CAM enable bit of CAMEN register also must be set.
* | | |Then, set SDPZ to 1 enables the PAUSE control frame transmission.
* | | |The SDPZ is a self-clear bit
* | | |This means after the PAUSE control frame transmission has completed, the SDPZ will be cleared automatically.
* | | |It is recommended that only enabling SNDPAUSE while EMAC is operating in Full Duplex mode.
* | | |0 = PAUSE control frame transmission completed.
* | | |1 = PAUSE control frame transmission Enabled.
* |[17] |SQECHKEN |SQE Checking Enable Bit
* | | |The SQECHKEN controls the enable of SQE checking
* | | |The SQE checking is only available while EMAC is operating on 10M bps and half duplex mode
* | | |In other words, the SQECHKEN cannot affect EMAC operation, if the EMAC is operating on 100Mbps
* | | |or full duplex mode.
* | | |0 = SQE checking Disabled while EMAC is operating in 10Mbps and Half Duplex mode.
* | | |1 = SQE checking Enabled while EMAC is operating in 10Mbps and Half Duplex mode.
* |[18] |FUDUP |Full Duplex Mode Selection
* | | |The FUDUP controls that if EMAC is operating on full or half duplex mode.
* | | |0 = EMAC operates in half duplex mode.
* | | |1 = EMAC operates in full duplex mode.
* |[19] |RMIIRXCTL |RMII RX Control
* | | |The RMIIRXCTL control the receive data sample in RMII mode
* | | |It's necessary to set this bit high when RMIIEN (EMAC_CTL[ [22]) is high.
* | | |0 = RMII RX control disabled.
* | | |1 = RMII RX control enabled.
* |[20] |OPMODE |Operation Mode Selection
* | | |The OPMODE defines that if the EMAC is operating on 10M or 100M bps mode
* | | |The RST (EMAC_CTL[24]) would not affect OPMODE value.
* | | |0 = EMAC operates in 10Mbps mode.
* | | |1 = EMAC operates in 100Mbps mode.
* |[22] |RMIIEN |RMII Mode Enable Bit
* | | |This bit controls if Ethernet MAC controller connected with off-chip Ethernet PHY by MII
* | | |interface or RMII interface
* | | |The RST (EMAC_CTL[24]) would not affect RMIIEN value.
* | | |0 = Ethernet MAC controller RMII mode Disabled.
* | | |1 = Ethernet MAC controller RMII mode Enabled.
* | | |NOTE: This field must keep 1.
* |[24] |RST |Software Reset
* | | |The RST implements a reset function to make the EMAC return default state
* | | |The RST is a self-clear bit
* | | |This means after the software reset finished, the RST will be cleared automatically
* | | |Enable RST can also reset all control and status registers, exclusive of the control bits
* | | |RMIIEN (EMAC_CTL[22]), and OPMODE (EMAC_CTL[20]).
* | | |The EMAC re-initial is necessary after the software reset completed.
* | | |0 = Software reset completed.
* | | |1 = Software reset Enabled.
* @var EMAC_T::MIIMDAT
* Offset: 0x94 MII Management Data Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |DATA |MII Management Data
* | | |The DATA is the 16 bits data that will be written into the registers of external PHY for MII
* | | |Management write command or the data from the registers of external PHY for MII Management read command.
* @var EMAC_T::MIIMCTL
* Offset: 0x98 MII Management Control and Address Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[4:0] |PHYREG |PHY Register Address
* | | |The PHYREG keeps the address to indicate which register of external PHY is the target of the
* | | |MII management command.
* |[12:8] |PHYADDR |PHY Address
* | | |The PHYADDR keeps the address to differentiate which external PHY is the target of the MII management command.
* |[16] |WRITE |Write Command
* | | |The Write defines the MII management command is a read or write.
* | | |0 = MII management command is a read command.
* | | |1 = MII management command is a write command.
* |[17] |BUSY |Busy Bit
* | | |The BUSY controls the enable of the MII management frame generation
* | | |If S/W wants to access registers of external PHY, it set BUSY to high and EMAC generates
* | | |the MII management frame to external PHY through MII Management I/F
* | | |The BUSY is a self-clear bit
* | | |This means the BUSY will be cleared automatically after the MII management command finished.
* | | |0 = MII management command generation finished.
* | | |1 = MII management command generation Enabled.
* |[18] |PREAMSP |Preamble Suppress
* | | |The PREAMSP controls the preamble field generation of MII management frame
* | | |If the PREAMSP is set to high, the preamble field generation of MII management frame is skipped.
* | | |0 = Preamble field generation of MII management frame not skipped.
* | | |1 = Preamble field generation of MII management frame skipped.
* |[19] |MDCON |MDC Clock ON
* | | |The MDC controls the MDC clock generation. If the MDCON is set to high, the MDC clock is turned on.
* | | |0 = MDC clock off.
* | | |1 = MDC clock on.
* @var EMAC_T::FIFOCTL
* Offset: 0x9C FIFO Threshold Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1:0] |RXFIFOTH |RXFIFO Low Threshold
* | | |The RXFIFOTH controls when RXDMA requests internal arbiter for data transfer between RXFIFO
* | | |and system memory
* | | |The RXFIFOTH defines not only the high threshold of RXFIFO, but also the low threshold
* | | |The low threshold is the half of high threshold always
* | | |During the packet reception, if the RXFIFO reaches the high threshold, the RXDMA starts to
* | | |transfer frame data from RXFIFO to system memory
* | | |If the frame data in RXFIFO is less than low threshold, RXDMA stops to transfer the frame
* | | |data to system memory.
* | | |00 = Depend on the burst length setting
* | | |If the burst length is 8 words, high threshold is 8 words, too.
* | | |01 = RXFIFO high threshold is 64B and low threshold is 32B.
* | | |10 = RXFIFO high threshold is 128B and low threshold is 64B.
* | | |11 = RXFIFO high threshold is 192B and low threshold is 96B.
* |[9:8] |TXFIFOTH |TXFIFO Low Threshold
* | | |The TXFIFOTH controls when TXDMA requests internal arbiter for data transfer between system
* | | |memory and TXFIFO
* | | |The TXFIFOTH defines not only the low threshold of TXFIFO, but also the high threshold
* | | |The high threshold is the twice of low threshold always
* | | |During the packet transmission, if the TXFIFO reaches the high threshold, the TXDMA stops
* | | |generate request to transfer frame data from system memory to TXFIFO
* | | |If the frame data in TXFIFO is less than low threshold, TXDMA starts to transfer frame data
* | | |from system memory to TXFIFO.
* | | |The TXFIFOTH also defines when the TXMAC starts to transmit frame out to network
* | | |The TXMAC starts to transmit the frame out while the TXFIFO first time reaches the high threshold
* | | |during the transmission of the frame
* | | |If the frame data length is less than TXFIFO high threshold, the TXMAC starts to transmit the frame
* | | |out after the frame data are all inside the TXFIFO.
* | | |00 = Undefined.
* | | |01 = TXFIFO low threshold is 64B and high threshold is 128B.
* | | |10 = TXFIFO low threshold is 80B and high threshold is 160B.
* | | |11 = TXFIFO low threshold is 96B and high threshold is 192B.
* |[21:20] |BURSTLEN |DMA Burst Length
* | | |This defines the burst length of AHB bus cycle while EMAC accesses system memory.
* | | |00 = 4 words.
* | | |01 = 8 words.
* | | |10 = 16 words.
* | | |11 = 16 words.
* @var EMAC_T::TXST
* Offset: 0xA0 Transmit Start Demand Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |TXST |Transmit Start Demand
* | | |If the TX descriptor is not available for use of TXDMA after the TXON (EMAC_CTL[8]) is enabled,
* | | |the FSM (Finite State Machine) of TXDMA enters the Halt state and the frame transmission is halted
* | | |After the S/W has prepared the new TX descriptor for frame transmission, it must issue a write
* | | |command to EMAC_TXST register to make TXDMA to leave Halt state and continue the frame transmission.
* | | |The EMAC_TXST is a write only register and read from this register is undefined.
* | | |The write to EMAC_TXST register takes effect only when TXDMA stayed at Halt state.
* @var EMAC_T::RXST
* Offset: 0xA4 Receive Start Demand Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |RXST |Receive Start Demand
* | | |If the RX descriptor is not available for use of RXDMA after the RXON (EMAC_CTL[0]) is enabled,
* | | |the FSM (Finite State Machine) of RXDMA enters the Halt state and the frame reception is halted
* | | |After the S/W has prepared the new RX descriptor for frame reception, it must issue a write
* | | |command to EMAC_RXST register to make RXDMA to leave Halt state and continue the frame reception.
* | | |The EMAC_RXST is a write only register and read from this register is undefined.
* | | |The write to EMAC_RXST register take effect only when RXDMA stayed at Halt state.
* @var EMAC_T::MRFL
* Offset: 0xA8 Maximum Receive Frame Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |MRFL |Maximum Receive Frame Length
* | | |The MRFL defines the maximum frame length for received frame
* | | |If the frame length of received frame is greater than MRFL, and bit MFLEIEN (EMAC_INTEN[8])
* | | |is also enabled, the bit MFLEIF (EMAC_INTSTS[8]) is set and the RX interrupt is triggered.
* | | |It is recommended that only use MRFL to qualify the length of received frame while S/W wants to
* | | |receive a frame which length is greater than 1518 bytes.
* @var EMAC_T::INTEN
* Offset: 0xAC MAC Interrupt Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |RXIEN |Receive Interrupt Enable Bit
* | | |The RXIEN controls the RX interrupt generation.
* | | |If RXIEN is enabled and RXIF (EMAC_INTSTS[0]) is high, EMAC generates the RX interrupt to CPU
* | | |If RXIEN is disabled, no RX interrupt is generated to CPU even any status bit EMAC_INTSTS[15:1]
* | | |is set and the corresponding bit of EMAC_INTEN is enabled
* | | |In other words, if S/W wants to receive RX interrupt from EMAC, this bit must be enabled
* | | |And, if S/W doesn't want to receive any RX interrupt from EMAC, disables this bit.
* | | |0 = RXIF (EMAC_INTSTS[0]) is masked and RX interrupt generation Disabled.
* | | |1 = RXIF (EMAC_INTSTS[0]) is not masked and RX interrupt generation Enabled.
* |[1] |CRCEIEN |CRC Error Interrupt Enable Bit
* | | |The CRCEIEN controls the CRCEIF (EMAC_INTSTS[1]) interrupt generation
* | | |If CRCEIF (EMAC_INTSTS[1]) is set, and both CRCEIEN and RXIEN (EMAC_INTEN[0]) are enabled, the
* | | |EMAC generates the RX interrupt to CPU
* | | |If CRCEIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the
* | | |CRCEIF (EMAC_INTSTS[1]) is set.
* | | |0 = CRCEIF (EMAC_INTSTS[1]) trigger RX interrupt Disabled.
* | | |1 = CRCEIF (EMAC_INTSTS[1]) trigger RX interrupt Enabled.
* |[2] |RXOVIEN |Receive FIFO Overflow Interrupt Enable Bit
* | | |The RXOVIEN controls the RXOVIF (EMAC_INTSTS[2]) interrupt generation
* | | |If RXOVIF (EMAC_INTSTS[2]) is set, and both RXOVIEN and RXIEN (EMAC_INTEN[0]) are enabled, the
* | | |EMAC generates the RX interrupt to CPU
* | | |If RXOVIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the
* | | |RXOVIF (EMAC_INTSTS[2]) is set.
* | | |0 = RXOVIF (EMAC_INTSTS[2]) trigger RX interrupt Disabled.
* | | |1 = RXOVIF (EMAC_INTSTS[2]) trigger RX interrupt Enabled.
* |[3] |LPIEN |Long Packet Interrupt Enable Bit
* | | |The LPIEN controls the LPIF (EMAC_INTSTS[3]) interrupt generation
* | | |If LPIF (EMAC_INTSTS[3]) is set, and both LPIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC
* | | |generates the RX interrupt to CPU
* | | |If LPIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the LPIF
* | | |(EMAC_INTSTS[3]) is set.
* | | |0 = LPIF (EMAC_INTSTS[3]) trigger RX interrupt Disabled.
* | | |1 = LPIF (EMAC_INTSTS[3]) trigger RX interrupt Enabled.
* |[4] |RXGDIEN |Receive Good Interrupt Enable Bit
* | | |The RXGDIEN controls the RXGDIF (EMAC_INTSTS[4]) interrupt generation
* | | |If RXGDIF (EMAC_INTSTS[4]) is set, and both RXGDIEN and RXIEN (EMAC_INTEN[0]) are enabled, the
* | | |EMAC generates the RX interrupt to CPU
* | | |If RXGDIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the
* | | |RXGDIF (EMAC_INTSTS[4]) is set.
* | | |0 = RXGDIF (EMAC_INTSTS[4]) trigger RX interrupt Disabled.
* | | |1 = RXGDIF (EMAC_INTSTS[4]) trigger RX interrupt Enabled.
* |[5] |ALIEIEN |Alignment Error Interrupt Enable Bit
* | | |The ALIEIEN controls the ALIEIF (EMAC_INTSTS[5]) interrupt generation
* | | |If ALIEIF (EMAC_INTSTS[5]) is set, and both ALIEIEN and RXIEN (EMAC_INTEN[0]) are enabled, the
* | | |EMAC generates the RX interrupt to CPU
* | | |If ALIEIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the
* | | |ALIEIF (EMAC_INTSTS[5]) is set.
* | | |0 = ALIEIF (EMAC_INTSTS[5]) trigger RX interrupt Disabled.
* | | |1 = ALIEIF (EMAC_INTSTS[5]) trigger RX interrupt Enabled.
* |[6] |RPIEN |Runt Packet Interrupt Enable Bit
* | | |The RPIEN controls the RPIF (EMAC_INTSTS[6]) interrupt generation
* | | |If RPIF (EMAC_INTSTS[6]) is set, and both RPIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC
* | | |generates the RX interrupt to CPU
* | | |If RPIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the
* | | |RPIF (EMAC_INTSTS[6]) is set.
* | | |0 = RPIF (EMAC_INTSTS[6]) trigger RX interrupt Disabled.
* | | |1 = RPIF (EMAC_INTSTS[6]) trigger RX interrupt Enabled.
* |[7] |MPCOVIEN |Miss Packet Counter Overrun Interrupt Enable Bit
* | | |The MPCOVIEN controls the MPCOVIF (EMAC_INTSTS[7]) interrupt generation
* | | |If MPCOVIF (EMAC_INTSTS[7]) is set, and both MPCOVIEN and RXIEN (EMAC_INTEN[0]) are enabled,
* | | |the EMAC generates the RX interrupt to CPU
* | | |If MPCOVIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the
* | | |MPCOVIF (EMAC_INTSTS[7]) is set.
* | | |0 = MPCOVIF (EMAC_INTSTS[7]) trigger RX interrupt Disabled.
* | | |1 = MPCOVIF (EMAC_INTSTS[7]) trigger RX interrupt Enabled.
* |[8] |MFLEIEN |Maximum Frame Length Exceed Interrupt Enable Bit
* | | |The MFLEIEN controls the MFLEIF (EMAC_INTSTS[8]) interrupt generation
* | | |If MFLEIF (EMAC_INTSTS[8]) is set, and both MFLEIEN and RXIEN (EMAC_INTEN[0]) are enabled, the
* | | |EMAC generates the RX interrupt to CPU
* | | |If MFLEIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the
* | | |MFLEIF (EMAC_INTSTS[8]) is set.
* | | |0 = MFLEIF (EMAC_INTSTS[8]) trigger RX interrupt Disabled.
* | | |1 = MFLEIF (EMAC_INTSTS[8]) trigger RX interrupt Enabled.
* |[9] |DENIEN |DMA Early Notification Interrupt Enable Bit
* | | |The DENIEN controls the DENIF (EMAC_INTSTS[9]) interrupt generation
* | | |If DENIF (EMAC_INTSTS[9]) is set, and both DENIEN and RXIEN (EMAC_INTEN[0]) are enabled, the
* | | |EMAC generates the RX interrupt to CPU
* | | |If DENIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the
* | | |DENIF (EMAC_INTSTS[9]) is set.
* | | |0 = TDENIF (EMAC_INTSTS[9]) trigger RX interrupt Disabled.
* | | |1 = TDENIF (EMAC_INTSTS[9]) trigger RX interrupt Enabled.
* |[10] |RDUIEN |Receive Descriptor Unavailable Interrupt Enable Bit
* | | |The RDUIEN controls the RDUIF (EMAC_INTSTS[10]) interrupt generation
* | | |If RDUIF (EMAC_INTSTS[10]) is set, and both RDUIEN and RXIEN (EMAC_INTEN[0]) are enabled, the
* | | |EMAC generates the RX interrupt to CPU
* | | |If RDUIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the
* | | |RDUIF (EMAC_MIOSTA[10]) register is set.
* | | |0 = RDUIF (EMAC_INTSTS[10]) trigger RX interrupt Disabled.
* | | |1 = RDUIF (EMAC_INTSTS[10]) trigger RX interrupt Enabled.
* |[11] |RXBEIEN |Receive Bus Error Interrupt Enable Bit
* | | |The RXBEIEN controls the RXBEIF (EMAC_INTSTS[11]) interrupt generation
* | | |If RXBEIF (EMAC_INTSTS[11]) is set, and both RXBEIEN and RXIEN (EMAC_INTEN[0]) are enabled, the
* | | |EMAC generates the RX interrupt to CPU
* | | |If RXBEIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the
* | | |RXBEIF (EMAC_INTSTS[11]) is set.
* | | |0 = RXBEIF (EMAC_INTSTS[11]) trigger RX interrupt Disabled.
* | | |1 = RXBEIF (EMAC_INTSTS[11]) trigger RX interrupt Enabled.
* |[14] |CFRIEN |Control Frame Receive Interrupt Enable Bit
* | | |The CFRIEN controls the CFRIF (EMAC_INTSTS[14]) interrupt generation
* | | |If CFRIF (EMAC_INTSTS[14]) is set, and both CFRIEN and RXIEN (EMAC_INTEN[0]) are enabled, the
* | | |EMAC generates the RX interrupt to CPU
* | | |If CFRIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the
* | | |CFRIF (EMAC_INTSTS[14]) register is set.
* | | |0 = CFRIF (EMAC_INTSTS[14]) trigger RX interrupt Disabled.
* | | |1 = CFRIF (EMAC_INTSTS[14]) trigger RX interrupt Enabled.
* |[15] |WOLIEN |Wake on LAN Interrupt Enable Bit
* | | |The WOLIEN controls the WOLIF (EMAC_INTSTS[15]) interrupt generation
* | | |If WOLIF (EMAC_INTSTS[15]) is set, and both WOLIEN and RXIEN (EMAC_INTEN[0]) are enabled,
* | | |the EMAC generates the RX interrupt to CPU
* | | |If WOLIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the
* | | |WOLIF (EMAC_INTSTS[15]) is set.
* | | |0 = WOLIF (EMAC_INTSTS[15]) trigger RX interrupt Disabled.
* | | |1 = WOLIF (EMAC_INTSTS[15]) trigger RX interrupt Enabled.
* |[16] |TXIEN |Transmit Interrupt Enable Bit
* | | |The TXIEN controls the TX interrupt generation.
* | | |If TXIEN is enabled and TXIF (EMAC_INTSTS[16]) is high, EMAC generates the TX interrupt to CPU
* | | |If TXIEN is disabled, no TX interrupt is generated to CPU even any status bit of
* | | |EMAC_INTSTS[24:17] set and the corresponding bit of EMAC_INTEN is enabled
* | | |In other words, if S/W wants to receive TX interrupt from EMAC, this bit must be enabled
* | | |And, if S/W doesn't want to receive any TX interrupt from EMAC, disables this bit.
* | | |0 = TXIF (EMAC_INTSTS[16]) is masked and TX interrupt generation Disabled.
* | | |1 = TXIF (EMAC_INTSTS[16]) is not masked and TX interrupt generation Enabled.
* |[17] |TXUDIEN |Transmit FIFO Underflow Interrupt Enable Bit
* | | |The TXUDIEN controls the TXUDIF (EMAC_INTSTS[17]) interrupt generation
* | | |If TXUDIF (EMAC_INTSTS[17]) is set, and both TXUDIEN and TXIEN (EMAC_INTEN[16]) are enabled,
* | | |the EMAC generates the TX interrupt to CPU
* | | |If TXUDIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even
* | | |the TXUDIF (EMAC_INTSTS[17]) is set.
* | | |0 = TXUDIF (EMAC_INTSTS[17]) TX interrupt Disabled.
* | | |1 = TXUDIF (EMAC_INTSTS[17]) TX interrupt Enabled.
* |[18] |TXCPIEN |Transmit Completion Interrupt Enable Bit
* | | |The TXCPIEN controls the TXCPIF (EMAC_INTSTS[18]) interrupt generation
* | | |If TXCPIF (EMAC_INTSTS[18]) is set, and both TXCPIEN and TXIEN (EMAC_INTEN[16]) are enabled,
* | | |the EMAC generates the TX interrupt to CPU
* | | |If TXCPIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the
* | | |TXCPIF (EMAC_INTSTS[18]) is set.
* | | |0 = TXCPIF (EMAC_INTSTS[18]) trigger TX interrupt Disabled.
* | | |1 = TXCPIF (EMAC_INTSTS[18]) trigger TX interrupt Enabled.
* |[19] |EXDEFIEN |Defer Exceed Interrupt Enable Bit
* | | |The EXDEFIEN controls the EXDEFIF (EMAC_INTSTS[19]) interrupt generation
* | | |If EXDEFIF (EMAC_INTSTS[19]) is set, and both EXDEFIEN and TXIEN (EMAC_INTEN[16]) are enabled,
* | | |the EMAC generates the TX interrupt to CPU
* | | |If EXDEFIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the
* | | |EXDEFIF (EMAC_INTSTS[19]) is set.
* | | |0 = EXDEFIF (EMAC_INTSTS[19]) trigger TX interrupt Disabled.
* | | |1 = EXDEFIF (EMAC_INTSTS[19]) trigger TX interrupt Enabled.
* |[20] |NCSIEN |No Carrier Sense Interrupt Enable Bit
* | | |The NCSIEN controls the NCSIF (EMAC_INTSTS[20]) interrupt generation
* | | |If NCSIF (EMAC_INTSTS[20]) is set, and both NCSIEN and TXIEN (EMAC_INTEN[16]) are enabled, the
* | | |EMAC generates the TX interrupt to CPU
* | | |If NCSIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the
* | | |NCSIF (EMAC_INTSTS[20]) is set.
* | | |0 = NCSIF (EMAC_INTSTS[20]) trigger TX interrupt Disabled.
* | | |1 = NCSIF (EMAC_INTSTS[20]) trigger TX interrupt Enabled.
* |[21] |TXABTIEN |Transmit Abort Interrupt Enable Bit
* | | |The TXABTIEN controls the TXABTIF (EMAC_INTSTS[21]) interrupt generation
* | | |If TXABTIF (EMAC_INTSTS[21]) is set, and both TXABTIEN and TXIEN (EMAC_INTEN[16]) are enabled,
* | | |the EMAC generates the TX interrupt to CPU
* | | |If TXABTIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the
* | | |TXABTIF (EMAC_INTSTS[21]) is set.
* | | |0 = TXABTIF (EMAC_INTSTS[21]) trigger TX interrupt Disabled.
* | | |1 = TXABTIF (EMAC_INTSTS[21]) trigger TX interrupt Enabled.
* |[22] |LCIEN |Late Collision Interrupt Enable Bit
* | | |The LCIEN controls the LCIF (EMAC_INTSTS[22]) interrupt generation
* | | |If LCIF (EMAC_INTSTS[22]) is set, and both LCIEN and TXIEN (EMAC_INTEN[16]) are enabled, the
* | | |EMAC generates the TX interrupt to CPU
* | | |If LCIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the
* | | |LCIF (EMAC_INTSTS[22]) is set.
* | | |0 = LCIF (EMAC_INTSTS[22]) trigger TX interrupt Disabled.
* | | |1 = LCIF (EMAC_INTSTS[22]) trigger TX interrupt Enabled.
* |[23] |TDUIEN |Transmit Descriptor Unavailable Interrupt Enable Bit
* | | |The TDUIEN controls the TDUIF (EMAC_INTSTS[23]) interrupt generation
* | | |If TDUIF (EMAC_INTSTS[23]) is set, and both TDUIEN and TXIEN (EMAC_INTEN[16]) are enabled, the
* | | |EMAC generates the TX interrupt to CPU
* | | |If TDUIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the
* | | |TDUIF (EMAC_INTSTS[23]) is set.
* | | |0 = TDUIF (EMAC_INTSTS[23]) trigger TX interrupt Disabled.
* | | |1 = TDUIF (EMAC_INTSTS[23]) trigger TX interrupt Enabled.
* |[24] |TXBEIEN |Transmit Bus Error Interrupt Enable Bit
* | | |The TXBEIEN controls the TXBEIF (EMAC_INTSTS[24]) interrupt generation
* | | |If TXBEIF (EMAC_INTSTS[24]) is set, and both TXBEIEN and TXIEN (EMAC_INTEN[16]) are enabled, the
* | | |EMAC generates the TX interrupt to CPU
* | | |If TXBEIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the
* | | |TXBEIF (EMAC_INTSTS[24]) is set.
* | | |0 = TXBEIF (EMAC_INTSTS[24]) trigger TX interrupt Disabled.
* | | |1 = TXBEIF (EMAC_INTSTS[24]) trigger TX interrupt Enabled.
* |[28] |TSALMIEN |Time Stamp Alarm Interrupt Enable Bit
* | | |The TSALMIEN controls the TSALMIF (EMAC_INTSTS[28]) interrupt generation
* | | |If TSALMIF (EMAC_INTSTS[28]) is set, and both TSALMIEN and TXIEN (EMAC_INTEN[16]) enabled, the
* | | |EMAC generates the TX interrupt to CPU
* | | |If TSALMIEN or TXIEN (EMAC_INTEN[16]) disabled, no TX interrupt generated to CPU even the
* | | |TXTSALMIF (EMAC_INTEN[28]) is set.
* | | |0 = TXTSALMIF (EMAC_INTSTS[28]) trigger TX interrupt Disabled.
* | | |1 = TXTSALMIF (EMAC_INTSTS[28]) trigger TX interrupt Enabled.
* @var EMAC_T::INTSTS
* Offset: 0xB0 MAC Interrupt Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |RXIF |Receive Interrupt
* | | |The RXIF indicates the RX interrupt status.
* | | |If RXIF high and its corresponding enable bit, RXIEN (EMAC_INTEN[0]), is also high indicates
* | | |the EMAC generates RX interrupt to CPU
* | | |If RXIF is high but RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated.
* | | |The RXIF is logic OR result of bit logic AND result of EMAC_INTSTS[15:1] and EMAC_INTEN[15:1]
* | | |In other words, if any bit of EMAC_INTSTS[15:1] is high and its corresponding enable bit in
* | | |EMAC_INTEN[15:1] is also enabled, the RXIF will be high.
* | | |Because the RXIF is a logic OR result, clears EMAC_INTSTS[15:1] makes RXIF be cleared, too.
* | | |0 = No status bit in EMAC_INTSTS[15:1] is set or no enable bit in EMAC_INTEN[15:1] is enabled.
* | | |1 = At least one status in EMAC_INTSTS[15:1] is set and its corresponding enable bit in
* | | |EMAC_INTEN[15:1] is enabled, too.
* |[1] |CRCEIF |CRC Error Interrupt
* | | |The CRCEIF high indicates the incoming packet incurred the CRC error and the packet is dropped
* | | |If the AEP (EMAC_CTL[4]) is set, the CRC error packet will be regarded as a good packet and
* | | |CRCEIF will not be set.
* | | |If the CRCEIF is high and CRCEIEN (EMAC_INTEN[1]) is enabled, the RXIF will be high
* | | |Write 1 to this bit clears the CRCEIF status.
* | | |0 = The frame does not incur CRC error.
* | | |1 = The frame incurred CRC error.
* |[2] |RXOVIF |Receive FIFO Overflow Interrupt
* | | |The RXOVIF high indicates the RXFIFO overflow occurred during packet reception
* | | |While the RXFIFO overflow occurred, the EMAC drops the current receiving packer
* | | |If the RXFIFO overflow occurred often, it is recommended that modify RXFIFO threshold control,
* | | |the RXFIFOTH of FFTCR register, to higher level.
* | | |If the RXOVIF is high and RXOVIEN (EMAC_INTEN[2]) is enabled, the RXIF will be high
* | | |Write 1 to this bit clears the RXOVIF status.
* | | |0 = No RXFIFO overflow occurred during packet reception.
* | | |1 = RXFIFO overflow occurred during packet reception.
* |[3] |LPIF |Long Packet Interrupt Flag
* | | |The LPIF high indicates the length of the incoming packet is greater than 1518 bytes and the
* | | |incoming packet is dropped
* | | |If the ALP (EMAC_CTL[1]) is set, the long packet will be regarded as a good packet and LPIF will not be set.
* | | |If the LPIF is high and LPIEN (EMAC_INTEN[3]) is enabled, the RXIF will be high
* | | |Write 1 to this bit clears the LPIF status.
* | | |0 = The incoming frame is not a long frame or S/W wants to receive a long frame.
* | | |1 = The incoming frame is a long frame and dropped.
* |[4] |RXGDIF |Receive Good Interrupt
* | | |The RXGDIF high indicates the frame reception has completed.
* | | |If the RXGDIF is high and RXGDIEN (EAMC_MIEN[4]) is enabled, the RXIF will be high
* | | |Write 1 to this bit clears the RXGDIF status.
* | | |0 = The frame reception has not complete yet.
* | | |1 = The frame reception has completed.
* |[5] |ALIEIF |Alignment Error Interrupt
* | | |The ALIEIF high indicates the length of the incoming frame is not a multiple of byte
* | | |If the ALIEIF is high and ALIEIEN (EMAC_INTEN[5]) is enabled, the RXIF will be high
* | | |Write 1 to this bit clears the ALIEIF status.
* | | |0 = The frame length is a multiple of byte.
* | | |1 = The frame length is not a multiple of byte.
* |[6] |RPIF |Runt Packet Interrupt
* | | |The RPIF high indicates the length of the incoming packet is less than 64 bytes and the packet is dropped
* | | |If the ARP (EMAC_CTL[2]) is set, the short packet is regarded as a good packet and RPIF will not be set.
* | | |If the RPIF is high and RPIEN (EMAC_INTEN[6]) is enabled, the RXIF will be high
* | | |Write 1 to this bit clears the RPIF status.
* | | |0 = The incoming frame is not a short frame or S/W wants to receive a short frame.
* | | |1 = The incoming frame is a short frame and dropped.
* |[7] |MPCOVIF |Missed Packet Counter Overrun Interrupt Flag
* | | |The MPCOVIF high indicates the MPCNT, Missed Packet Count, has overflow
* | | |If the MPCOVIF is high and MPCOVIEN (EMAC_INTEN[7]) is enabled, the RXIF will be high
* | | |Write 1 to this bit clears the MPCOVIF status.
* | | |0 = The MPCNT has not rolled over yet.
* | | |1 = The MPCNT has rolled over yet.
* |[8] |MFLEIF |Maximum Frame Length Exceed Interrupt Flag
* | | |The MFLEIF high indicates the length of the incoming packet has exceeded the length limitation
* | | |configured in DMARFC register and the incoming packet is dropped
* | | |If the MFLEIF is high and MFLEIEN (EMAC_INTEN[8]) is enabled, the RXIF will be high
* | | |Write 1 to this bit clears the MFLEIF status.
* | | |0 = The length of the incoming packet does not exceed the length limitation configured in DMARFC.
* | | |1 = The length of the incoming packet has exceeded the length limitation configured in DMARFC.
* |[9] |DENIF |DMA Early Notification Interrupt
* | | |The DENIF high indicates the EMAC has received the LENGTH field of the incoming packet.
* | | |If the DENIF is high and DENIENI (EMAC_INTEN[9]) is enabled, the RXIF will be high
* | | |Write 1 to this bit clears the DENIF status.
* | | |0 = The LENGTH field of incoming packet has not received yet.
* | | |1 = The LENGTH field of incoming packet has received.
* |[10] |RDUIF |Receive Descriptor Unavailable Interrupt
* | | |The RDUIF high indicates that there is no available RX descriptor for packet reception and
* | | |RXDMA will stay at Halt state
* | | |Once, the RXDMA enters the Halt state, S/W must issues a write command to RSDR register to
* | | |make RXDMA leave Halt state while new RX descriptor is available.
* | | |If the RDUIF is high and RDUIEN (EMAC_INTEN[10]) is enabled, the RXIF will be high
* | | |Write 1 to this bit clears the RDUIF status.
* | | |0 = RX descriptor is available.
* | | |1 = RX descriptor is unavailable.
* |[11] |RXBEIF |Receive Bus Error Interrupt
* | | |The RXBEIF high indicates the memory controller replies ERROR response while EMAC access
* | | |system memory through RXDMA during packet reception process
* | | |Reset EMAC is recommended while RXBEIF status is high.
* | | |If the RXBEIF is high and RXBEIEN (EMAC_INTEN[11]) is enabled, the RXIF will be high
* | | |Write 1 to this bit clears the RXBEIF status.
* | | |0 = No ERROR response is received.
* | | |1 = ERROR response is received.
* |[14] |CFRIF |Control Frame Receive Interrupt
* | | |The CFRIF high indicates EMAC receives a flow control frame
* | | |The CFRIF only available while EMAC is operating on full duplex mode.
* | | |If the CFRIF is high and CFRIEN (EMAC_INTEN[14]) is enabled, the RXIF will be high
* | | |Write 1 to this bit clears the CFRIF status.
* | | |0 = The EMAC does not receive the flow control frame.
* | | |1 = The EMAC receives a flow control frame.
* |[15] |WOLIF |Wake on LAN Interrupt Flag
* | | |The WOLIF high indicates EMAC receives a Magic Packet
* | | |The CFRIF only available while system is in power down mode and WOLEN is set high.
* | | |If the WOLIF is high and WOLIEN (EMAC_INTEN[15]) is enabled, the RXIF will be high
* | | |Write 1 to this bit clears the WOLIF status.
* | | |0 = The EMAC does not receive the Magic Packet.
* | | |1 = The EMAC receives a Magic Packet.
* |[16] |TXIF |Transmit Interrupt
* | | |The TXIF indicates the TX interrupt status.
* | | |If TXIF high and its corresponding enable bit, TXIEN (EMAC_INTEN[16]), is also high indicates
* | | |the EMAC generates TX interrupt to CPU
* | | |If TXIF is high but TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated.
* | | |The TXIF is logic OR result of bit logic AND result of EMAC_INTSTS[28:17] and EMAC_INTEN[28:17]
* | | |In other words, if any bit of EMAC_INTSTS[28:17] is high and its corresponding enable bit
* | | |in EMAC_INTEN[28:17] is also enabled, the TXIF will be high
* | | |Because the TXIF is a logic OR result, clears EMAC_INTSTS[28:17] makes TXIF be cleared, too.
* | | |0 = No status bit in EMAC_INTSTS[28:17] is set or no enable bit in EMAC_INTEN[28:17] is enabled.
* | | |1 = At least one status in EMAC_INTSTS[28:17] is set and its corresponding enable bit
* | | |in EMAC_INTEN[28:17] is enabled, too.
* |[17] |TXUDIF |Transmit FIFO Underflow Interrupt
* | | |The TXUDIF high indicates the TXFIFO underflow occurred during packet transmission
* | | |While the TXFIFO underflow occurred, the EMAC will retransmit the packet automatically
* | | |without S/W intervention
* | | |If the TXFIFO underflow occurred often, it is recommended that modify TXFIFO threshold control,
* | | |the TXFIFOTH of FFTCR register, to higher level.
* | | |If the TXUDIF is high and TXUDIEN (EMAC_INTEN[17]) is enabled, the TXIF will be high
* | | |Write 1 to this bit clears the TXUDIF status.
* | | |0 = No TXFIFO underflow occurred during packet transmission.
* | | |1 = TXFIFO underflow occurred during packet transmission.
* |[18] |TXCPIF |Transmit Completion Interrupt
* | | |The TXCPIF indicates the packet transmission has completed correctly.
* | | |If the TXCPIF is high and TXCPIEN (EMAC_INTEN[18]) is enabled, the TXIF will be high
* | | |Write 1 to this bit clears the TXCPIF status.
* | | |0 = The packet transmission not completed.
* | | |1 = The packet transmission has completed.
* |[19] |EXDEFIF |Defer Exceed Interrupt
* | | |The EXDEFIF high indicates the frame waiting for transmission has deferred over 0.32768ms
* | | |on 100Mbps mode, or 3.2768ms on 10Mbps mode.
* | | |The deferral exceed check will only be done while bit NODEF of MCMDR is disabled, and EMAC
* | | |is operating on half-duplex mode.
* | | |If the EXDEFIF is high and EXDEFIEN (EMAC_INTEN[19]) is enabled, the TXIF will be high
* | | |Write 1 to this bit clears the EXDEFIF status.
* | | |0 = Frame waiting for transmission has not deferred over 0.32768ms (100Mbps) or 3.2768ms (10Mbps).
* | | |1 = Frame waiting for transmission has deferred over 0.32768ms (100Mbps) or 3.2768ms (10Mbps).
* |[20] |NCSIF |No Carrier Sense Interrupt
* | | |The NCSIF high indicates the MII I/F signal CRS does not active at the start of or during
* | | |the packet transmission
* | | |The NCSIF is only available while EMAC is operating on half-duplex mode
* | | |If the NCSIF is high and NCSIEN (EMAC_INTEN[20]) is enabled, the TXIF will be high.
* | | |Write 1 to this bit clears the NCSIF status.
* | | |0 = CRS signal actives correctly.
* | | |1 = CRS signal does not active at the start of or during the packet transmission.
* |[21] |TXABTIF |Transmit Abort Interrupt
* | | |The TXABTIF high indicates the packet incurred 16 consecutive collisions during transmission,
* | | |and then the transmission process for this packet is aborted
* | | |The transmission abort is only available while EMAC is operating on half-duplex mode.
* | | |If the TXABTIF is high and TXABTIEN (EMAC_INTEN[21]) is enabled, the TXIF will be high
* | | |Write 1 to this bit clears the TXABTIF status.
* | | |0 = Packet does not incur 16 consecutive collisions during transmission.
* | | |1 = Packet incurred 16 consecutive collisions during transmission.
* |[22] |LCIF |Late Collision Interrupt
* | | |The LCIF high indicates the collision occurred in the outside of 64 bytes collision window
* | | |This means after the 64 bytes of a frame has been transmitted out to the network, the collision
* | | |still occurred.
* | | |The late collision check will only be done while EMAC is operating on half-duplex mode
* | | |If the LCIF is high and LCIEN (EMAC_INTEN[22]) is enabled, the TXIF will be high.
* | | |Write 1 to this bit clears the LCIF status.
* | | |0 = No collision occurred in the outside of 64 bytes collision window.
* | | |1 = Collision occurred in the outside of 64 bytes collision window.
* |[23] |TDUIF |Transmit Descriptor Unavailable Interrupt
* | | |The TDUIF high indicates that there is no available TX descriptor for packet transmission and
* | | |TXDMA will stay at Halt state.
* | | |Once, the TXDMA enters the Halt state, S/W must issues a write command to TSDR register to make
* | | |TXDMA leave Halt state while new TX descriptor is available.
* | | |If the TDUIF is high and TDUIEN (EMAC_INTEN[23]) is enabled, the TXIF will be high.
* | | |Write 1 to this bit clears the TDUIF status.
* | | |0 = TX descriptor is available.
* | | |1 = TX descriptor is unavailable.
* |[24] |TXBEIF |Transmit Bus Error Interrupt
* | | |The TXBEIF high indicates the memory controller replies ERROR response while EMAC access system
* | | |memory through TXDMA during packet transmission process
* | | |Reset EMAC is recommended while TXBEIF status is high.
* | | |If the TXBEIF is high and TXBEIEN (EMAC_INTEN[24]) is enabled, the TXIF will be high.
* | | |Write 1 to this bit clears the TXBEIF status.
* | | |0 = No ERROR response is received.
* | | |1 = ERROR response is received.
* |[28] |TSALMIF |Time Stamp Alarm Interrupt
* | | |The TSALMIF high indicates the EMAC_TSSEC register value equals to EMAC_ALMSEC register and
* | | |EMAC_TSSUBSEC register value equals to register EMAC_ALMSUBLSR.
* | | |If TSALMIF is high and TSALMIEN (EMAC_INTEN[28]) enabled, the TXIF will be high.
* | | |Write 1 to this bit clears the TSALMIF status.
* | | |0 = EMAC_TSSEC did not equal EMAC_ALMSEC or EMAC_TSSUBSEC did not equal EMAC_ALMSUBSEC.
* | | |1 = EMAC_TSSEC equals EMAC_ALMSEC and EMAC_TSSUBSEC equals EMAC_ALMSUBSEC.
* @var EMAC_T::GENSTS
* Offset: 0xB4 MAC General Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CFR |Control Frame Received
* | | |The CFRIF high indicates EMAC receives a flow control frame
* | | |The CFRIF only available while EMAC is operating on full duplex mode.
* | | |0 = The EMAC does not receive the flow control frame.
* | | |1 = The EMAC receives a flow control frame.
* |[1] |RXHALT |Receive Halted
* | | |The RXHALT high indicates the next normal packet reception process will be halted because
* | | |the bit RXON of MCMDR is disabled be S/W.
* | | |0 = Next normal packet reception process will go on.
* | | |1 = Next normal packet reception process will be halted.
* |[2] |RXFFULL |RXFIFO Full
* | | |The RXFFULL indicates the RXFIFO is full due to four 64-byte packets are kept in RXFIFO
* | | |and the following incoming packet will be dropped.
* | | |0 = The RXFIFO is not full.
* | | |1 = The RXFIFO is full and the following incoming packet will be dropped.
* |[7:4] |COLCNT |Collision Count
* | | |The COLCNT indicates that how many collisions occurred consecutively during a packet transmission
* | | |If the packet incurred 16 consecutive collisions during transmission, the COLCNT will be
* | | |0 and bit TXABTIF will be set to 1.
* |[8] |DEF |Deferred Transmission
* | | |The DEF high indicates the packet transmission has deferred once
* | | |The DEF is only available while EMAC is operating on half-duplex mode.
* | | |0 = Packet transmission does not defer.
* | | |1 = Packet transmission has deferred once.
* |[9] |TXPAUSED |Transmission Paused
* | | |The TXPAUSED high indicates the next normal packet transmission process will be paused temporally
* | | |because EMAC received a PAUSE control frame.
* | | |0 = Next normal packet transmission process will go on.
* | | |1 = Next normal packet transmission process will be paused.
* |[10] |SQE |Signal Quality Error
* | | |The SQE high indicates the SQE error found at end of packet transmission on 10Mbps half-duplex mode
* | | |The SQE error check will only be done while both bit SQECHKEN (EMAC_CTL[17]) is enabled and EMAC
* | | |is operating on 10Mbps half-duplex mode.
* | | |0 = No SQE error found at end of packet transmission.
* | | |1 = SQE error found at end of packet transmission.
* |[11] |TXHALT |Transmission Halted
* | | |The TXHALT high indicates the next normal packet transmission process will be halted because
* | | |the bit TXON (EMAC_CTL[8]) is disabled be S/W.
* | | |0 = Next normal packet transmission process will go on.
* | | |1 = Next normal packet transmission process will be halted.
* |[12] |RPSTS |Remote Pause Status
* | | |The RPSTS indicates that remote pause counter down counting actives.
* | | |After Ethernet MAC controller sent PAUSE frame out successfully, it starts the remote pause
* | | |counter down counting
* | | |When this bit high, it's predictable that remote Ethernet MAC controller wouldn't start the packet
* | | |transmission until the down counting done.
* | | |0 = Remote pause counter down counting done.
* | | |1 = Remote pause counter down counting actives.
* @var EMAC_T::MPCNT
* Offset: 0xB8 Missed Packet Count Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |MPCNT |Miss Packet Count
* | | |The MPCNT indicates the number of packets that were dropped due to various types of receive errors
* | | |The following type of receiving error makes missed packet counter increase:
* | | |1. Incoming packet is incurred RXFIFO overflow.
* | | |2. Incoming packet is dropped due to RXON is disabled.
* | | |3. Incoming packet is incurred CRC error.
* @var EMAC_T::RPCNT
* Offset: 0xBC MAC Receive Pause Count Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |RPCNT |MAC Receive Pause Count
* | | |The RPCNT keeps the OPERAND field of the PAUSE control frame
* | | |It indicates how many slot time (512 bit time) the TX of EMAC will be paused.
* @var EMAC_T::FRSTS
* Offset: 0xC8 DMA Receive Frame Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |RXFLT |Receive Frame LENGTH
* | | |The RXFLT keeps the LENGTH field of each incoming Ethernet packet
* | | |If the bit DENIEN (EMAC_INTEN[9]) is enabled and the LENGTH field of incoming packet has
* | | |received, the bit DENIF (EMAC_INTSTS[9]) will be set and trigger interrupt.
* | | |And, the content of LENGTH field will be stored in RXFLT.
* @var EMAC_T::CTXDSA
* Offset: 0xCC Current Transmit Descriptor Start Address Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |CTXDSA |Current Transmit Descriptor Start Address
* | | |The CTXDSA keeps the start address of TX descriptor that is used by TXDMA currently
* | | |The CTXDSA is read only and write to this register has no effect.
* @var EMAC_T::CTXBSA
* Offset: 0xD0 Current Transmit Buffer Start Address Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |CTXBSA |Current Transmit Buffer Start Address
* | | |The CTXDSA keeps the start address of TX frame buffer that is used by TXDMA currently
* | | |The CTXBSA is read only and write to this register has no effect.
* @var EMAC_T::CRXDSA
* Offset: 0xD4 Current Receive Descriptor Start Address Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |CRXDSA |Current Receive Descriptor Start Address
* | | |The CRXDSA keeps the start address of RX descriptor that is used by RXDMA currently
* | | |The CRXDSA is read only and write to this register has no effect.
* @var EMAC_T::CRXBSA
* Offset: 0xD8 Current Receive Buffer Start Address Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |CRXBSA |Current Receive Buffer Start Address
* | | |The CRXBSA keeps the start address of RX frame buffer that is used by RXDMA currently
* | | |The CRXBSA is read only and write to this register has no effect.
* @var EMAC_T::TSCTL
* Offset: 0x100 Time Stamp Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |TSEN |Time Stamp Function Enable Bit
* | | |This bit controls if the IEEE 1588 PTP time stamp function is enabled or not.
* | | |Set this bit high to enable IEEE 1588 PTP time stamp function while set this bit low
* | | |to disable IEEE 1588 PTP time stamp function.
* | | |0 = I EEE 1588 PTP time stamp function Disabled.
* | | |1 = IEEE 1588 PTP time stamp function Enabled.
* |[1] |TSIEN |Time Stamp Counter Initialization Enable Bit
* | | |Set this bit high enables Ethernet MAC controller to load value of register EMAC_UPDSEC
* | | |and EMAC_UPDSUBSEC to PTP time stamp counter.
* | | |After the load operation finished, Ethernet MAC controller clear this bit to low automatically.
* | | |0 = Time stamp counter initialization done.
* | | |1 = Time stamp counter initialization Enabled.
* |[2] |TSMODE |Time Stamp Fine Update Enable Bit
* | | |This bit chooses the time stamp counter update mode.
* | | |0 = Time stamp counter is in coarse update mode.
* | | |1 = Time stamp counter is in fine update mode.
* |[3] |TSUPDATE |Time Stamp Counter Time Update Enable Bit
* | | |Set this bit high enables Ethernet MAC controller to add value of register EMAC_UPDSEC and
* | | |EMAC_UPDSUBSEC to PTP time stamp counter.
* | | |After the add operation finished, Ethernet MAC controller clear this bit to low automatically.
* | | |0 = No action.
* | | |1 = EMAC_UPDSEC updated to EMAC_TSSEC and EMAC_UPDSUBSEC updated to EMAC_TSSUBSEC.
* |[5] |TSALMEN |Time Stamp Alarm Enable Bit
* | | |Set this bit high enable Ethernet MAC controller to set TSALMIF (EMAC_INTSTS[28]) high when
* | | |EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to EMAC_ALMSUBSEC.
* | | |0 = Alarm disabled when EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to EMAC_ALMSUBSEC.
* | | |1 = Alarm enabled when EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to EMAC_ALMSUBSEC.
* @var EMAC_T::TSSEC
* Offset: 0x110 Time Stamp Counter Second Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |SEC |Time Stamp Counter Second
* | | |This register reflects the bit [63:32] value of 64-bit reference timing counter
* | | |This 32-bit value is used as the second part of time stamp when TSEN (EMAC_TSCTL[0]) is high.
* @var EMAC_T::TSSUBSEC
* Offset: 0x114 Time Stamp Counter Sub Second Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |SUBSEC |Time Stamp Counter Sub-second
* | | |This register reflects the bit [31:0] value of 64-bit reference timing counter
* | | |This 32-bit value is used as the sub-second part of time stamp when TSEN (EMAC_TSCTL[0]) is high.
* @var EMAC_T::TSINC
* Offset: 0x118 Time Stamp Increment Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |CNTINC |Time Stamp Counter Increment
* | | |Time stamp counter increment value.
* | | |If TSEN (EMAC_TSCTL[0]) is high, EMAC adds EMAC_TSSUBSEC with this 8-bit value every
* | | |time when it wants to increase the EMAC_TSSUBSEC value.
* @var EMAC_T::TSADDEND
* Offset: 0x11C Time Stamp Addend Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |ADDEND |Time Stamp Counter Addend
* | | |This register keeps a 32-bit value for accumulator to enable increment of EMAC_TSSUBSEC.
* | | |If TSEN (EMAC_TSCTL[0]) and TSMODE (EMAC_TSCTL[2]) are both high, EMAC increases accumulator
* | | |with this 32-bit value in each HCLK
* | | |Once the accumulator is overflow, it generates a enable to increase EMAC_TSSUBSEC with an 8-bit
* | | |value kept in register EMAC_TSINC.
* @var EMAC_T::UPDSEC
* Offset: 0x120 Time Stamp Update Second Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |SEC |Time Stamp Counter Second Update
* | | |When TSIEN (EMAC_TSCTL[1]) is high
* | | |EMAC loads this 32-bit value to EMAC_TSSEC directly
* | | |When TSUPDATE (EMAC_TSCTL[3]) is high, EMAC increases EMAC_TSSEC with this 32-bit value.
* @var EMAC_T::UPDSUBSEC
* Offset: 0x124 Time Stamp Update Sub Second Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |SUBSEC |Time Stamp Counter Sub-second Update
* | | |When TSIEN (EMAC_TSCTL[1]) is high
* | | |EMAC loads this 32-bit value to EMAC_TSSUBSEC directly
* | | |When TSUPDATE (EMAC_TSCTL[3]) is high, EMAC increases EMAC_TSSUBSEC with this 32-bit value.
* @var EMAC_T::ALMSEC
* Offset: 0x128 Time Stamp Alarm Second Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |SEC |Time Stamp Counter Second Alarm
* | | |Time stamp counter second part alarm value.
* | | |This value is only useful when ALMEN (EMAC_TSCTL[5]) high
* | | |If ALMEN (EMAC_TSCTL[5]) is high, EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to
* | | |EMAC_ALMSUBSEC, Ethernet MAC controller set TSALMIF (EMAC_INTSTS[28]) high.
* @var EMAC_T::ALMSUBSEC
* Offset: 0x12C Time Stamp Alarm Sub Second Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |SUBSEC |Time Stamp Counter Sub-second Alarm
* | | |Time stamp counter sub-second part alarm value.
* | | |This value is only useful when ALMEN (EMAC_TSCTL[5]) high
* | | |If ALMEN (EMAC_TSCTL[5]) is high, EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to
* | | |EMAC_ALMSUBSEC, Ethernet MAC controller set TSALMIF (EMAC_INTSTS[28]) high.
*/
__IO uint32_t CAMCTL; /*!< [0x0000] CAM Comparison Control Register */
__IO uint32_t CAMEN; /*!< [0x0004] CAM Enable Register */
__IO uint32_t CAM0M; /*!< [0x0008] CAM0 Most Significant Word Register */
__IO uint32_t CAM0L; /*!< [0x000c] CAM0 Least Significant Word Register */
__IO uint32_t CAM1M; /*!< [0x0010] CAM1 Most Significant Word Register */
__IO uint32_t CAM1L; /*!< [0x0014] CAM1 Least Significant Word Register */
__IO uint32_t CAM2M; /*!< [0x0018] CAM2 Most Significant Word Register */
__IO uint32_t CAM2L; /*!< [0x001c] CAM2 Least Significant Word Register */
__IO uint32_t CAM3M; /*!< [0x0020] CAM3 Most Significant Word Register */
__IO uint32_t CAM3L; /*!< [0x0024] CAM3 Least Significant Word Register */
__IO uint32_t CAM4M; /*!< [0x0028] CAM4 Most Significant Word Register */
__IO uint32_t CAM4L; /*!< [0x002c] CAM4 Least Significant Word Register */
__IO uint32_t CAM5M; /*!< [0x0030] CAM5 Most Significant Word Register */
__IO uint32_t CAM5L; /*!< [0x0034] CAM5 Least Significant Word Register */
__IO uint32_t CAM6M; /*!< [0x0038] CAM6 Most Significant Word Register */
__IO uint32_t CAM6L; /*!< [0x003c] CAM6 Least Significant Word Register */
__IO uint32_t CAM7M; /*!< [0x0040] CAM7 Most Significant Word Register */
__IO uint32_t CAM7L; /*!< [0x0044] CAM7 Least Significant Word Register */
__IO uint32_t CAM8M; /*!< [0x0048] CAM8 Most Significant Word Register */
__IO uint32_t CAM8L; /*!< [0x004c] CAM8 Least Significant Word Register */
__IO uint32_t CAM9M; /*!< [0x0050] CAM9 Most Significant Word Register */
__IO uint32_t CAM9L; /*!< [0x0054] CAM9 Least Significant Word Register */
__IO uint32_t CAM10M; /*!< [0x0058] CAM10 Most Significant Word Register */
__IO uint32_t CAM10L; /*!< [0x005c] CAM10 Least Significant Word Register */
__IO uint32_t CAM11M; /*!< [0x0060] CAM11 Most Significant Word Register */
__IO uint32_t CAM11L; /*!< [0x0064] CAM11 Least Significant Word Register */
__IO uint32_t CAM12M; /*!< [0x0068] CAM12 Most Significant Word Register */
__IO uint32_t CAM12L; /*!< [0x006c] CAM12 Least Significant Word Register */
__IO uint32_t CAM13M; /*!< [0x0070] CAM13 Most Significant Word Register */
__IO uint32_t CAM13L; /*!< [0x0074] CAM13 Least Significant Word Register */
__IO uint32_t CAM14M; /*!< [0x0078] CAM14 Most Significant Word Register */
__IO uint32_t CAM14L; /*!< [0x007c] CAM14 Least Significant Word Register */
__IO uint32_t CAM15MSB; /*!< [0x0080] CAM15 Most Significant Word Register */
__IO uint32_t CAM15LSB; /*!< [0x0084] CAM15 Least Significant Word Register */
__IO uint32_t TXDSA; /*!< [0x0088] Transmit Descriptor Link List Start Address Register */
__IO uint32_t RXDSA; /*!< [0x008c] Receive Descriptor Link List Start Address Register */
__IO uint32_t CTL; /*!< [0x0090] MAC Control Register */
__IO uint32_t MIIMDAT; /*!< [0x0094] MII Management Data Register */
__IO uint32_t MIIMCTL; /*!< [0x0098] MII Management Control and Address Register */
__IO uint32_t FIFOCTL; /*!< [0x009c] FIFO Threshold Control Register */
__O uint32_t TXST; /*!< [0x00a0] Transmit Start Demand Register */
__O uint32_t RXST; /*!< [0x00a4] Receive Start Demand Register */
__IO uint32_t MRFL; /*!< [0x00a8] Maximum Receive Frame Control Register */
__IO uint32_t INTEN; /*!< [0x00ac] MAC Interrupt Enable Register */
__IO uint32_t INTSTS; /*!< [0x00b0] MAC Interrupt Status Register */
__IO uint32_t GENSTS; /*!< [0x00b4] MAC General Status Register */
__IO uint32_t MPCNT; /*!< [0x00b8] Missed Packet Count Register */
__I uint32_t RPCNT; /*!< [0x00bc] MAC Receive Pause Count Register */
/** @cond HIDDEN_SYMBOLS */
__I uint32_t RESERVE0[2];
/** @endcond */
__IO uint32_t FRSTS; /*!< [0x00c8] DMA Receive Frame Status Register */
__I uint32_t CTXDSA; /*!< [0x00cc] Current Transmit Descriptor Start Address Register */
__I uint32_t CTXBSA; /*!< [0x00d0] Current Transmit Buffer Start Address Register */
__I uint32_t CRXDSA; /*!< [0x00d4] Current Receive Descriptor Start Address Register */
__I uint32_t CRXBSA; /*!< [0x00d8] Current Receive Buffer Start Address Register */
/** @cond HIDDEN_SYMBOLS */
__I uint32_t RESERVE1[9];
/** @endcond */
__IO uint32_t TSCTL; /*!< [0x0100] Time Stamp Control Register */
/** @cond HIDDEN_SYMBOLS */
__I uint32_t RESERVE2[3];
/** @endcond */
__I uint32_t TSSEC; /*!< [0x0110] Time Stamp Counter Second Register */
__I uint32_t TSSUBSEC; /*!< [0x0114] Time Stamp Counter Sub Second Register */
__IO uint32_t TSINC; /*!< [0x0118] Time Stamp Increment Register */
__IO uint32_t TSADDEND; /*!< [0x011c] Time Stamp Addend Register */
__IO uint32_t UPDSEC; /*!< [0x0120] Time Stamp Update Second Register */
__IO uint32_t UPDSUBSEC; /*!< [0x0124] Time Stamp Update Sub Second Register */
__IO uint32_t ALMSEC; /*!< [0x0128] Time Stamp Alarm Second Register */
__IO uint32_t ALMSUBSEC; /*!< [0x012c] Time Stamp Alarm Sub Second Register */
} EMAC_T;
/**
@addtogroup EMAC_CONST EMAC Bit Field Definition
Constant Definitions for EMAC Controller
@{ */
#define EMAC_CAMCTL_AUP_Pos (0) /*!< EMAC_T::CAMCTL: AUP Position */
#define EMAC_CAMCTL_AUP_Msk (0x1ul << EMAC_CAMCTL_AUP_Pos) /*!< EMAC_T::CAMCTL: AUP Mask */
#define EMAC_CAMCTL_AMP_Pos (1) /*!< EMAC_T::CAMCTL: AMP Position */
#define EMAC_CAMCTL_AMP_Msk (0x1ul << EMAC_CAMCTL_AMP_Pos) /*!< EMAC_T::CAMCTL: AMP Mask */
#define EMAC_CAMCTL_ABP_Pos (2) /*!< EMAC_T::CAMCTL: ABP Position */
#define EMAC_CAMCTL_ABP_Msk (0x1ul << EMAC_CAMCTL_ABP_Pos) /*!< EMAC_T::CAMCTL: ABP Mask */
#define EMAC_CAMCTL_COMPEN_Pos (3) /*!< EMAC_T::CAMCTL: COMPEN Position */
#define EMAC_CAMCTL_COMPEN_Msk (0x1ul << EMAC_CAMCTL_COMPEN_Pos) /*!< EMAC_T::CAMCTL: COMPEN Mask */
#define EMAC_CAMCTL_CMPEN_Pos (4) /*!< EMAC_T::CAMCTL: CMPEN Position */
#define EMAC_CAMCTL_CMPEN_Msk (0x1ul << EMAC_CAMCTL_CMPEN_Pos) /*!< EMAC_T::CAMCTL: CMPEN Mask */
#define EMAC_CAMEN_CAMxEN_Pos (0) /*!< EMAC_T::CAMEN: CAMxEN Position */
#define EMAC_CAMEN_CAMxEN_Msk (0x1ul << EMAC_CAMEN_CAMxEN_Pos) /*!< EMAC_T::CAMEN: CAMxEN Mask */
#define EMAC_CAM0M_MACADDR2_Pos (0) /*!< EMAC_T::CAM0M: MACADDR2 Position */
#define EMAC_CAM0M_MACADDR2_Msk (0xfful << EMAC_CAM0M_MACADDR2_Pos) /*!< EMAC_T::CAM0M: MACADDR2 Mask */
#define EMAC_CAM0M_MACADDR3_Pos (8) /*!< EMAC_T::CAM0M: MACADDR3 Position */
#define EMAC_CAM0M_MACADDR3_Msk (0xfful << EMAC_CAM0M_MACADDR3_Pos) /*!< EMAC_T::CAM0M: MACADDR3 Mask */
#define EMAC_CAM0M_MACADDR4_Pos (16) /*!< EMAC_T::CAM0M: MACADDR4 Position */
#define EMAC_CAM0M_MACADDR4_Msk (0xfful << EMAC_CAM0M_MACADDR4_Pos) /*!< EMAC_T::CAM0M: MACADDR4 Mask */
#define EMAC_CAM0M_MACADDR5_Pos (24) /*!< EMAC_T::CAM0M: MACADDR5 Position */
#define EMAC_CAM0M_MACADDR5_Msk (0xfful << EMAC_CAM0M_MACADDR5_Pos) /*!< EMAC_T::CAM0M: MACADDR5 Mask */
#define EMAC_CAM0L_MACADDR0_Pos (16) /*!< EMAC_T::CAM0L: MACADDR0 Position */
#define EMAC_CAM0L_MACADDR0_Msk (0xfful << EMAC_CAM0L_MACADDR0_Pos) /*!< EMAC_T::CAM0L: MACADDR0 Mask */
#define EMAC_CAM0L_MACADDR1_Pos (24) /*!< EMAC_T::CAM0L: MACADDR1 Position */
#define EMAC_CAM0L_MACADDR1_Msk (0xfful << EMAC_CAM0L_MACADDR1_Pos) /*!< EMAC_T::CAM0L: MACADDR1 Mask */
#define EMAC_CAM1M_MACADDR2_Pos (0) /*!< EMAC_T::CAM1M: MACADDR2 Position */
#define EMAC_CAM1M_MACADDR2_Msk (0xfful << EMAC_CAM1M_MACADDR2_Pos) /*!< EMAC_T::CAM1M: MACADDR2 Mask */
#define EMAC_CAM1M_MACADDR3_Pos (8) /*!< EMAC_T::CAM1M: MACADDR3 Position */
#define EMAC_CAM1M_MACADDR3_Msk (0xfful << EMAC_CAM1M_MACADDR3_Pos) /*!< EMAC_T::CAM1M: MACADDR3 Mask */
#define EMAC_CAM1M_MACADDR4_Pos (16) /*!< EMAC_T::CAM1M: MACADDR4 Position */
#define EMAC_CAM1M_MACADDR4_Msk (0xfful << EMAC_CAM1M_MACADDR4_Pos) /*!< EMAC_T::CAM1M: MACADDR4 Mask */
#define EMAC_CAM1M_MACADDR5_Pos (24) /*!< EMAC_T::CAM1M: MACADDR5 Position */
#define EMAC_CAM1M_MACADDR5_Msk (0xfful << EMAC_CAM1M_MACADDR5_Pos) /*!< EMAC_T::CAM1M: MACADDR5 Mask */
#define EMAC_CAM1L_MACADDR0_Pos (16) /*!< EMAC_T::CAM1L: MACADDR0 Position */
#define EMAC_CAM1L_MACADDR0_Msk (0xfful << EMAC_CAM1L_MACADDR0_Pos) /*!< EMAC_T::CAM1L: MACADDR0 Mask */
#define EMAC_CAM1L_MACADDR1_Pos (24) /*!< EMAC_T::CAM1L: MACADDR1 Position */
#define EMAC_CAM1L_MACADDR1_Msk (0xfful << EMAC_CAM1L_MACADDR1_Pos) /*!< EMAC_T::CAM1L: MACADDR1 Mask */
#define EMAC_CAM2M_MACADDR2_Pos (0) /*!< EMAC_T::CAM2M: MACADDR2 Position */
#define EMAC_CAM2M_MACADDR2_Msk (0xfful << EMAC_CAM2M_MACADDR2_Pos) /*!< EMAC_T::CAM2M: MACADDR2 Mask */
#define EMAC_CAM2M_MACADDR3_Pos (8) /*!< EMAC_T::CAM2M: MACADDR3 Position */
#define EMAC_CAM2M_MACADDR3_Msk (0xfful << EMAC_CAM2M_MACADDR3_Pos) /*!< EMAC_T::CAM2M: MACADDR3 Mask */
#define EMAC_CAM2M_MACADDR4_Pos (16) /*!< EMAC_T::CAM2M: MACADDR4 Position */
#define EMAC_CAM2M_MACADDR4_Msk (0xfful << EMAC_CAM2M_MACADDR4_Pos) /*!< EMAC_T::CAM2M: MACADDR4 Mask */
#define EMAC_CAM2M_MACADDR5_Pos (24) /*!< EMAC_T::CAM2M: MACADDR5 Position */
#define EMAC_CAM2M_MACADDR5_Msk (0xfful << EMAC_CAM2M_MACADDR5_Pos) /*!< EMAC_T::CAM2M: MACADDR5 Mask */
#define EMAC_CAM2L_MACADDR0_Pos (16) /*!< EMAC_T::CAM2L: MACADDR0 Position */
#define EMAC_CAM2L_MACADDR0_Msk (0xfful << EMAC_CAM2L_MACADDR0_Pos) /*!< EMAC_T::CAM2L: MACADDR0 Mask */
#define EMAC_CAM2L_MACADDR1_Pos (24) /*!< EMAC_T::CAM2L: MACADDR1 Position */
#define EMAC_CAM2L_MACADDR1_Msk (0xfful << EMAC_CAM2L_MACADDR1_Pos) /*!< EMAC_T::CAM2L: MACADDR1 Mask */
#define EMAC_CAM3M_MACADDR2_Pos (0) /*!< EMAC_T::CAM3M: MACADDR2 Position */
#define EMAC_CAM3M_MACADDR2_Msk (0xfful << EMAC_CAM3M_MACADDR2_Pos) /*!< EMAC_T::CAM3M: MACADDR2 Mask */
#define EMAC_CAM3M_MACADDR3_Pos (8) /*!< EMAC_T::CAM3M: MACADDR3 Position */
#define EMAC_CAM3M_MACADDR3_Msk (0xfful << EMAC_CAM3M_MACADDR3_Pos) /*!< EMAC_T::CAM3M: MACADDR3 Mask */
#define EMAC_CAM3M_MACADDR4_Pos (16) /*!< EMAC_T::CAM3M: MACADDR4 Position */
#define EMAC_CAM3M_MACADDR4_Msk (0xfful << EMAC_CAM3M_MACADDR4_Pos) /*!< EMAC_T::CAM3M: MACADDR4 Mask */
#define EMAC_CAM3M_MACADDR5_Pos (24) /*!< EMAC_T::CAM3M: MACADDR5 Position */
#define EMAC_CAM3M_MACADDR5_Msk (0xfful << EMAC_CAM3M_MACADDR5_Pos) /*!< EMAC_T::CAM3M: MACADDR5 Mask */
#define EMAC_CAM3L_MACADDR0_Pos (16) /*!< EMAC_T::CAM3L: MACADDR0 Position */
#define EMAC_CAM3L_MACADDR0_Msk (0xfful << EMAC_CAM3L_MACADDR0_Pos) /*!< EMAC_T::CAM3L: MACADDR0 Mask */
#define EMAC_CAM3L_MACADDR1_Pos (24) /*!< EMAC_T::CAM3L: MACADDR1 Position */
#define EMAC_CAM3L_MACADDR1_Msk (0xfful << EMAC_CAM3L_MACADDR1_Pos) /*!< EMAC_T::CAM3L: MACADDR1 Mask */
#define EMAC_CAM4M_MACADDR2_Pos (0) /*!< EMAC_T::CAM4M: MACADDR2 Position */
#define EMAC_CAM4M_MACADDR2_Msk (0xfful << EMAC_CAM4M_MACADDR2_Pos) /*!< EMAC_T::CAM4M: MACADDR2 Mask */
#define EMAC_CAM4M_MACADDR3_Pos (8) /*!< EMAC_T::CAM4M: MACADDR3 Position */
#define EMAC_CAM4M_MACADDR3_Msk (0xfful << EMAC_CAM4M_MACADDR3_Pos) /*!< EMAC_T::CAM4M: MACADDR3 Mask */
#define EMAC_CAM4M_MACADDR4_Pos (16) /*!< EMAC_T::CAM4M: MACADDR4 Position */
#define EMAC_CAM4M_MACADDR4_Msk (0xfful << EMAC_CAM4M_MACADDR4_Pos) /*!< EMAC_T::CAM4M: MACADDR4 Mask */
#define EMAC_CAM4M_MACADDR5_Pos (24) /*!< EMAC_T::CAM4M: MACADDR5 Position */
#define EMAC_CAM4M_MACADDR5_Msk (0xfful << EMAC_CAM4M_MACADDR5_Pos) /*!< EMAC_T::CAM4M: MACADDR5 Mask */
#define EMAC_CAM4L_MACADDR0_Pos (16) /*!< EMAC_T::CAM4L: MACADDR0 Position */
#define EMAC_CAM4L_MACADDR0_Msk (0xfful << EMAC_CAM4L_MACADDR0_Pos) /*!< EMAC_T::CAM4L: MACADDR0 Mask */
#define EMAC_CAM4L_MACADDR1_Pos (24) /*!< EMAC_T::CAM4L: MACADDR1 Position */
#define EMAC_CAM4L_MACADDR1_Msk (0xfful << EMAC_CAM4L_MACADDR1_Pos) /*!< EMAC_T::CAM4L: MACADDR1 Mask */
#define EMAC_CAM5M_MACADDR2_Pos (0) /*!< EMAC_T::CAM5M: MACADDR2 Position */
#define EMAC_CAM5M_MACADDR2_Msk (0xfful << EMAC_CAM5M_MACADDR2_Pos) /*!< EMAC_T::CAM5M: MACADDR2 Mask */
#define EMAC_CAM5M_MACADDR3_Pos (8) /*!< EMAC_T::CAM5M: MACADDR3 Position */
#define EMAC_CAM5M_MACADDR3_Msk (0xfful << EMAC_CAM5M_MACADDR3_Pos) /*!< EMAC_T::CAM5M: MACADDR3 Mask */
#define EMAC_CAM5M_MACADDR4_Pos (16) /*!< EMAC_T::CAM5M: MACADDR4 Position */
#define EMAC_CAM5M_MACADDR4_Msk (0xfful << EMAC_CAM5M_MACADDR4_Pos) /*!< EMAC_T::CAM5M: MACADDR4 Mask */
#define EMAC_CAM5M_MACADDR5_Pos (24) /*!< EMAC_T::CAM5M: MACADDR5 Position */
#define EMAC_CAM5M_MACADDR5_Msk (0xfful << EMAC_CAM5M_MACADDR5_Pos) /*!< EMAC_T::CAM5M: MACADDR5 Mask */
#define EMAC_CAM5L_MACADDR0_Pos (16) /*!< EMAC_T::CAM5L: MACADDR0 Position */
#define EMAC_CAM5L_MACADDR0_Msk (0xfful << EMAC_CAM5L_MACADDR0_Pos) /*!< EMAC_T::CAM5L: MACADDR0 Mask */
#define EMAC_CAM5L_MACADDR1_Pos (24) /*!< EMAC_T::CAM5L: MACADDR1 Position */
#define EMAC_CAM5L_MACADDR1_Msk (0xfful << EMAC_CAM5L_MACADDR1_Pos) /*!< EMAC_T::CAM5L: MACADDR1 Mask */
#define EMAC_CAM6M_MACADDR2_Pos (0) /*!< EMAC_T::CAM6M: MACADDR2 Position */
#define EMAC_CAM6M_MACADDR2_Msk (0xfful << EMAC_CAM6M_MACADDR2_Pos) /*!< EMAC_T::CAM6M: MACADDR2 Mask */
#define EMAC_CAM6M_MACADDR3_Pos (8) /*!< EMAC_T::CAM6M: MACADDR3 Position */
#define EMAC_CAM6M_MACADDR3_Msk (0xfful << EMAC_CAM6M_MACADDR3_Pos) /*!< EMAC_T::CAM6M: MACADDR3 Mask */
#define EMAC_CAM6M_MACADDR4_Pos (16) /*!< EMAC_T::CAM6M: MACADDR4 Position */
#define EMAC_CAM6M_MACADDR4_Msk (0xfful << EMAC_CAM6M_MACADDR4_Pos) /*!< EMAC_T::CAM6M: MACADDR4 Mask */
#define EMAC_CAM6M_MACADDR5_Pos (24) /*!< EMAC_T::CAM6M: MACADDR5 Position */
#define EMAC_CAM6M_MACADDR5_Msk (0xfful << EMAC_CAM6M_MACADDR5_Pos) /*!< EMAC_T::CAM6M: MACADDR5 Mask */
#define EMAC_CAM6L_MACADDR0_Pos (16) /*!< EMAC_T::CAM6L: MACADDR0 Position */
#define EMAC_CAM6L_MACADDR0_Msk (0xfful << EMAC_CAM6L_MACADDR0_Pos) /*!< EMAC_T::CAM6L: MACADDR0 Mask */
#define EMAC_CAM6L_MACADDR1_Pos (24) /*!< EMAC_T::CAM6L: MACADDR1 Position */
#define EMAC_CAM6L_MACADDR1_Msk (0xfful << EMAC_CAM6L_MACADDR1_Pos) /*!< EMAC_T::CAM6L: MACADDR1 Mask */
#define EMAC_CAM7M_MACADDR2_Pos (0) /*!< EMAC_T::CAM7M: MACADDR2 Position */
#define EMAC_CAM7M_MACADDR2_Msk (0xfful << EMAC_CAM7M_MACADDR2_Pos) /*!< EMAC_T::CAM7M: MACADDR2 Mask */
#define EMAC_CAM7M_MACADDR3_Pos (8) /*!< EMAC_T::CAM7M: MACADDR3 Position */
#define EMAC_CAM7M_MACADDR3_Msk (0xfful << EMAC_CAM7M_MACADDR3_Pos) /*!< EMAC_T::CAM7M: MACADDR3 Mask */
#define EMAC_CAM7M_MACADDR4_Pos (16) /*!< EMAC_T::CAM7M: MACADDR4 Position */
#define EMAC_CAM7M_MACADDR4_Msk (0xfful << EMAC_CAM7M_MACADDR4_Pos) /*!< EMAC_T::CAM7M: MACADDR4 Mask */
#define EMAC_CAM7M_MACADDR5_Pos (24) /*!< EMAC_T::CAM7M: MACADDR5 Position */
#define EMAC_CAM7M_MACADDR5_Msk (0xfful << EMAC_CAM7M_MACADDR5_Pos) /*!< EMAC_T::CAM7M: MACADDR5 Mask */
#define EMAC_CAM7L_MACADDR0_Pos (16) /*!< EMAC_T::CAM7L: MACADDR0 Position */
#define EMAC_CAM7L_MACADDR0_Msk (0xfful << EMAC_CAM7L_MACADDR0_Pos) /*!< EMAC_T::CAM7L: MACADDR0 Mask */
#define EMAC_CAM7L_MACADDR1_Pos (24) /*!< EMAC_T::CAM7L: MACADDR1 Position */
#define EMAC_CAM7L_MACADDR1_Msk (0xfful << EMAC_CAM7L_MACADDR1_Pos) /*!< EMAC_T::CAM7L: MACADDR1 Mask */
#define EMAC_CAM8M_MACADDR2_Pos (0) /*!< EMAC_T::CAM8M: MACADDR2 Position */
#define EMAC_CAM8M_MACADDR2_Msk (0xfful << EMAC_CAM8M_MACADDR2_Pos) /*!< EMAC_T::CAM8M: MACADDR2 Mask */
#define EMAC_CAM8M_MACADDR3_Pos (8) /*!< EMAC_T::CAM8M: MACADDR3 Position */
#define EMAC_CAM8M_MACADDR3_Msk (0xfful << EMAC_CAM8M_MACADDR3_Pos) /*!< EMAC_T::CAM8M: MACADDR3 Mask */
#define EMAC_CAM8M_MACADDR4_Pos (16) /*!< EMAC_T::CAM8M: MACADDR4 Position */
#define EMAC_CAM8M_MACADDR4_Msk (0xfful << EMAC_CAM8M_MACADDR4_Pos) /*!< EMAC_T::CAM8M: MACADDR4 Mask */
#define EMAC_CAM8M_MACADDR5_Pos (24) /*!< EMAC_T::CAM8M: MACADDR5 Position */
#define EMAC_CAM8M_MACADDR5_Msk (0xfful << EMAC_CAM8M_MACADDR5_Pos) /*!< EMAC_T::CAM8M: MACADDR5 Mask */
#define EMAC_CAM8L_MACADDR0_Pos (16) /*!< EMAC_T::CAM8L: MACADDR0 Position */
#define EMAC_CAM8L_MACADDR0_Msk (0xfful << EMAC_CAM8L_MACADDR0_Pos) /*!< EMAC_T::CAM8L: MACADDR0 Mask */
#define EMAC_CAM8L_MACADDR1_Pos (24) /*!< EMAC_T::CAM8L: MACADDR1 Position */
#define EMAC_CAM8L_MACADDR1_Msk (0xfful << EMAC_CAM8L_MACADDR1_Pos) /*!< EMAC_T::CAM8L: MACADDR1 Mask */
#define EMAC_CAM9M_MACADDR2_Pos (0) /*!< EMAC_T::CAM9M: MACADDR2 Position */
#define EMAC_CAM9M_MACADDR2_Msk (0xfful << EMAC_CAM9M_MACADDR2_Pos) /*!< EMAC_T::CAM9M: MACADDR2 Mask */
#define EMAC_CAM9M_MACADDR3_Pos (8) /*!< EMAC_T::CAM9M: MACADDR3 Position */
#define EMAC_CAM9M_MACADDR3_Msk (0xfful << EMAC_CAM9M_MACADDR3_Pos) /*!< EMAC_T::CAM9M: MACADDR3 Mask */
#define EMAC_CAM9M_MACADDR4_Pos (16) /*!< EMAC_T::CAM9M: MACADDR4 Position */
#define EMAC_CAM9M_MACADDR4_Msk (0xfful << EMAC_CAM9M_MACADDR4_Pos) /*!< EMAC_T::CAM9M: MACADDR4 Mask */
#define EMAC_CAM9M_MACADDR5_Pos (24) /*!< EMAC_T::CAM9M: MACADDR5 Position */
#define EMAC_CAM9M_MACADDR5_Msk (0xfful << EMAC_CAM9M_MACADDR5_Pos) /*!< EMAC_T::CAM9M: MACADDR5 Mask */
#define EMAC_CAM9L_MACADDR0_Pos (16) /*!< EMAC_T::CAM9L: MACADDR0 Position */
#define EMAC_CAM9L_MACADDR0_Msk (0xfful << EMAC_CAM9L_MACADDR0_Pos) /*!< EMAC_T::CAM9L: MACADDR0 Mask */
#define EMAC_CAM9L_MACADDR1_Pos (24) /*!< EMAC_T::CAM9L: MACADDR1 Position */
#define EMAC_CAM9L_MACADDR1_Msk (0xfful << EMAC_CAM9L_MACADDR1_Pos) /*!< EMAC_T::CAM9L: MACADDR1 Mask */
#define EMAC_CAM10M_MACADDR2_Pos (0) /*!< EMAC_T::CAM10M: MACADDR2 Position */
#define EMAC_CAM10M_MACADDR2_Msk (0xfful << EMAC_CAM10M_MACADDR2_Pos) /*!< EMAC_T::CAM10M: MACADDR2 Mask */
#define EMAC_CAM10M_MACADDR3_Pos (8) /*!< EMAC_T::CAM10M: MACADDR3 Position */
#define EMAC_CAM10M_MACADDR3_Msk (0xfful << EMAC_CAM10M_MACADDR3_Pos) /*!< EMAC_T::CAM10M: MACADDR3 Mask */
#define EMAC_CAM10M_MACADDR4_Pos (16) /*!< EMAC_T::CAM10M: MACADDR4 Position */
#define EMAC_CAM10M_MACADDR4_Msk (0xfful << EMAC_CAM10M_MACADDR4_Pos) /*!< EMAC_T::CAM10M: MACADDR4 Mask */
#define EMAC_CAM10M_MACADDR5_Pos (24) /*!< EMAC_T::CAM10M: MACADDR5 Position */
#define EMAC_CAM10M_MACADDR5_Msk (0xfful << EMAC_CAM10M_MACADDR5_Pos) /*!< EMAC_T::CAM10M: MACADDR5 Mask */
#define EMAC_CAM10L_MACADDR0_Pos (16) /*!< EMAC_T::CAM10L: MACADDR0 Position */
#define EMAC_CAM10L_MACADDR0_Msk (0xfful << EMAC_CAM10L_MACADDR0_Pos) /*!< EMAC_T::CAM10L: MACADDR0 Mask */
#define EMAC_CAM10L_MACADDR1_Pos (24) /*!< EMAC_T::CAM10L: MACADDR1 Position */
#define EMAC_CAM10L_MACADDR1_Msk (0xfful << EMAC_CAM10L_MACADDR1_Pos) /*!< EMAC_T::CAM10L: MACADDR1 Mask */
#define EMAC_CAM11M_MACADDR2_Pos (0) /*!< EMAC_T::CAM11M: MACADDR2 Position */
#define EMAC_CAM11M_MACADDR2_Msk (0xfful << EMAC_CAM11M_MACADDR2_Pos) /*!< EMAC_T::CAM11M: MACADDR2 Mask */
#define EMAC_CAM11M_MACADDR3_Pos (8) /*!< EMAC_T::CAM11M: MACADDR3 Position */
#define EMAC_CAM11M_MACADDR3_Msk (0xfful << EMAC_CAM11M_MACADDR3_Pos) /*!< EMAC_T::CAM11M: MACADDR3 Mask */
#define EMAC_CAM11M_MACADDR4_Pos (16) /*!< EMAC_T::CAM11M: MACADDR4 Position */
#define EMAC_CAM11M_MACADDR4_Msk (0xfful << EMAC_CAM11M_MACADDR4_Pos) /*!< EMAC_T::CAM11M: MACADDR4 Mask */
#define EMAC_CAM11M_MACADDR5_Pos (24) /*!< EMAC_T::CAM11M: MACADDR5 Position */
#define EMAC_CAM11M_MACADDR5_Msk (0xfful << EMAC_CAM11M_MACADDR5_Pos) /*!< EMAC_T::CAM11M: MACADDR5 Mask */
#define EMAC_CAM11L_MACADDR0_Pos (16) /*!< EMAC_T::CAM11L: MACADDR0 Position */
#define EMAC_CAM11L_MACADDR0_Msk (0xfful << EMAC_CAM11L_MACADDR0_Pos) /*!< EMAC_T::CAM11L: MACADDR0 Mask */
#define EMAC_CAM11L_MACADDR1_Pos (24) /*!< EMAC_T::CAM11L: MACADDR1 Position */
#define EMAC_CAM11L_MACADDR1_Msk (0xfful << EMAC_CAM11L_MACADDR1_Pos) /*!< EMAC_T::CAM11L: MACADDR1 Mask */
#define EMAC_CAM12M_MACADDR2_Pos (0) /*!< EMAC_T::CAM12M: MACADDR2 Position */
#define EMAC_CAM12M_MACADDR2_Msk (0xfful << EMAC_CAM12M_MACADDR2_Pos) /*!< EMAC_T::CAM12M: MACADDR2 Mask */
#define EMAC_CAM12M_MACADDR3_Pos (8) /*!< EMAC_T::CAM12M: MACADDR3 Position */
#define EMAC_CAM12M_MACADDR3_Msk (0xfful << EMAC_CAM12M_MACADDR3_Pos) /*!< EMAC_T::CAM12M: MACADDR3 Mask */
#define EMAC_CAM12M_MACADDR4_Pos (16) /*!< EMAC_T::CAM12M: MACADDR4 Position */
#define EMAC_CAM12M_MACADDR4_Msk (0xfful << EMAC_CAM12M_MACADDR4_Pos) /*!< EMAC_T::CAM12M: MACADDR4 Mask */
#define EMAC_CAM12M_MACADDR5_Pos (24) /*!< EMAC_T::CAM12M: MACADDR5 Position */
#define EMAC_CAM12M_MACADDR5_Msk (0xfful << EMAC_CAM12M_MACADDR5_Pos) /*!< EMAC_T::CAM12M: MACADDR5 Mask */
#define EMAC_CAM12L_MACADDR0_Pos (16) /*!< EMAC_T::CAM12L: MACADDR0 Position */
#define EMAC_CAM12L_MACADDR0_Msk (0xfful << EMAC_CAM12L_MACADDR0_Pos) /*!< EMAC_T::CAM12L: MACADDR0 Mask */
#define EMAC_CAM12L_MACADDR1_Pos (24) /*!< EMAC_T::CAM12L: MACADDR1 Position */
#define EMAC_CAM12L_MACADDR1_Msk (0xfful << EMAC_CAM12L_MACADDR1_Pos) /*!< EMAC_T::CAM12L: MACADDR1 Mask */
#define EMAC_CAM13M_MACADDR2_Pos (0) /*!< EMAC_T::CAM13M: MACADDR2 Position */
#define EMAC_CAM13M_MACADDR2_Msk (0xfful << EMAC_CAM13M_MACADDR2_Pos) /*!< EMAC_T::CAM13M: MACADDR2 Mask */
#define EMAC_CAM13M_MACADDR3_Pos (8) /*!< EMAC_T::CAM13M: MACADDR3 Position */
#define EMAC_CAM13M_MACADDR3_Msk (0xfful << EMAC_CAM13M_MACADDR3_Pos) /*!< EMAC_T::CAM13M: MACADDR3 Mask */
#define EMAC_CAM13M_MACADDR4_Pos (16) /*!< EMAC_T::CAM13M: MACADDR4 Position */
#define EMAC_CAM13M_MACADDR4_Msk (0xfful << EMAC_CAM13M_MACADDR4_Pos) /*!< EMAC_T::CAM13M: MACADDR4 Mask */
#define EMAC_CAM13M_MACADDR5_Pos (24) /*!< EMAC_T::CAM13M: MACADDR5 Position */
#define EMAC_CAM13M_MACADDR5_Msk (0xfful << EMAC_CAM13M_MACADDR5_Pos) /*!< EMAC_T::CAM13M: MACADDR5 Mask */
#define EMAC_CAM13L_MACADDR0_Pos (16) /*!< EMAC_T::CAM13L: MACADDR0 Position */
#define EMAC_CAM13L_MACADDR0_Msk (0xfful << EMAC_CAM13L_MACADDR0_Pos) /*!< EMAC_T::CAM13L: MACADDR0 Mask */
#define EMAC_CAM13L_MACADDR1_Pos (24) /*!< EMAC_T::CAM13L: MACADDR1 Position */
#define EMAC_CAM13L_MACADDR1_Msk (0xfful << EMAC_CAM13L_MACADDR1_Pos) /*!< EMAC_T::CAM13L: MACADDR1 Mask */
#define EMAC_CAM14M_MACADDR2_Pos (0) /*!< EMAC_T::CAM14M: MACADDR2 Position */
#define EMAC_CAM14M_MACADDR2_Msk (0xfful << EMAC_CAM14M_MACADDR2_Pos) /*!< EMAC_T::CAM14M: MACADDR2 Mask */
#define EMAC_CAM14M_MACADDR3_Pos (8) /*!< EMAC_T::CAM14M: MACADDR3 Position */
#define EMAC_CAM14M_MACADDR3_Msk (0xfful << EMAC_CAM14M_MACADDR3_Pos) /*!< EMAC_T::CAM14M: MACADDR3 Mask */
#define EMAC_CAM14M_MACADDR4_Pos (16) /*!< EMAC_T::CAM14M: MACADDR4 Position */
#define EMAC_CAM14M_MACADDR4_Msk (0xfful << EMAC_CAM14M_MACADDR4_Pos) /*!< EMAC_T::CAM14M: MACADDR4 Mask */
#define EMAC_CAM14M_MACADDR5_Pos (24) /*!< EMAC_T::CAM14M: MACADDR5 Position */
#define EMAC_CAM14M_MACADDR5_Msk (0xfful << EMAC_CAM14M_MACADDR5_Pos) /*!< EMAC_T::CAM14M: MACADDR5 Mask */
#define EMAC_CAM14L_MACADDR0_Pos (16) /*!< EMAC_T::CAM14L: MACADDR0 Position */
#define EMAC_CAM14L_MACADDR0_Msk (0xfful << EMAC_CAM14L_MACADDR0_Pos) /*!< EMAC_T::CAM14L: MACADDR0 Mask */
#define EMAC_CAM14L_MACADDR1_Pos (24) /*!< EMAC_T::CAM14L: MACADDR1 Position */
#define EMAC_CAM14L_MACADDR1_Msk (0xfful << EMAC_CAM14L_MACADDR1_Pos) /*!< EMAC_T::CAM14L: MACADDR1 Mask */
#define EMAC_CAM15MSB_OPCODE_Pos (0) /*!< EMAC_T::CAM15MSB: OPCODE Position */
#define EMAC_CAM15MSB_OPCODE_Msk (0xfffful << EMAC_CAM15MSB_OPCODE_Pos) /*!< EMAC_T::CAM15MSB: OPCODE Mask */
#define EMAC_CAM15MSB_LENGTH_Pos (16) /*!< EMAC_T::CAM15MSB: LENGTH Position */
#define EMAC_CAM15MSB_LENGTH_Msk (0xfffful << EMAC_CAM15MSB_LENGTH_Pos) /*!< EMAC_T::CAM15MSB: LENGTH Mask */
#define EMAC_CAM15LSB_OPERAND_Pos (24) /*!< EMAC_T::CAM15LSB: OPERAND Position */
#define EMAC_CAM15LSB_OPERAND_Msk (0xfful << EMAC_CAM15LSB_OPERAND_Pos) /*!< EMAC_T::CAM15LSB: OPERAND Mask */
#define EMAC_TXDSA_TXDSA_Pos (0) /*!< EMAC_T::TXDSA: TXDSA Position */
#define EMAC_TXDSA_TXDSA_Msk (0xfffffffful << EMAC_TXDSA_TXDSA_Pos) /*!< EMAC_T::TXDSA: TXDSA Mask */
#define EMAC_RXDSA_RXDSA_Pos (0) /*!< EMAC_T::RXDSA: RXDSA Position */
#define EMAC_RXDSA_RXDSA_Msk (0xfffffffful << EMAC_RXDSA_RXDSA_Pos) /*!< EMAC_T::RXDSA: RXDSA Mask */
#define EMAC_CTL_RXON_Pos (0) /*!< EMAC_T::CTL: RXON Position */
#define EMAC_CTL_RXON_Msk (0x1ul << EMAC_CTL_RXON_Pos) /*!< EMAC_T::CTL: RXON Mask */
#define EMAC_CTL_ALP_Pos (1) /*!< EMAC_T::CTL: ALP Position */
#define EMAC_CTL_ALP_Msk (0x1ul << EMAC_CTL_ALP_Pos) /*!< EMAC_T::CTL: ALP Mask */
#define EMAC_CTL_ARP_Pos (2) /*!< EMAC_T::CTL: ARP Position */
#define EMAC_CTL_ARP_Msk (0x1ul << EMAC_CTL_ARP_Pos) /*!< EMAC_T::CTL: ARP Mask */
#define EMAC_CTL_ACP_Pos (3) /*!< EMAC_T::CTL: ACP Position */
#define EMAC_CTL_ACP_Msk (0x1ul << EMAC_CTL_ACP_Pos) /*!< EMAC_T::CTL: ACP Mask */
#define EMAC_CTL_AEP_Pos (4) /*!< EMAC_T::CTL: AEP Position */
#define EMAC_CTL_AEP_Msk (0x1ul << EMAC_CTL_AEP_Pos) /*!< EMAC_T::CTL: AEP Mask */
#define EMAC_CTL_STRIPCRC_Pos (5) /*!< EMAC_T::CTL: STRIPCRC Position */
#define EMAC_CTL_STRIPCRC_Msk (0x1ul << EMAC_CTL_STRIPCRC_Pos) /*!< EMAC_T::CTL: STRIPCRC Mask */
#define EMAC_CTL_WOLEN_Pos (6) /*!< EMAC_T::CTL: WOLEN Position */
#define EMAC_CTL_WOLEN_Msk (0x1ul << EMAC_CTL_WOLEN_Pos) /*!< EMAC_T::CTL: WOLEN Mask */
#define EMAC_CTL_TXON_Pos (8) /*!< EMAC_T::CTL: TXON Position */
#define EMAC_CTL_TXON_Msk (0x1ul << EMAC_CTL_TXON_Pos) /*!< EMAC_T::CTL: TXON Mask */
#define EMAC_CTL_NODEF_Pos (9) /*!< EMAC_T::CTL: NODEF Position */
#define EMAC_CTL_NODEF_Msk (0x1ul << EMAC_CTL_NODEF_Pos) /*!< EMAC_T::CTL: NODEF Mask */
#define EMAC_CTL_SDPZ_Pos (16) /*!< EMAC_T::CTL: SDPZ Position */
#define EMAC_CTL_SDPZ_Msk (0x1ul << EMAC_CTL_SDPZ_Pos) /*!< EMAC_T::CTL: SDPZ Mask */
#define EMAC_CTL_SQECHKEN_Pos (17) /*!< EMAC_T::CTL: SQECHKEN Position */
#define EMAC_CTL_SQECHKEN_Msk (0x1ul << EMAC_CTL_SQECHKEN_Pos) /*!< EMAC_T::CTL: SQECHKEN Mask */
#define EMAC_CTL_FUDUP_Pos (18) /*!< EMAC_T::CTL: FUDUP Position */
#define EMAC_CTL_FUDUP_Msk (0x1ul << EMAC_CTL_FUDUP_Pos) /*!< EMAC_T::CTL: FUDUP Mask */
#define EMAC_CTL_RMIIRXCTL_Pos (19) /*!< EMAC_T::CTL: RMIIRXCTL Position */
#define EMAC_CTL_RMIIRXCTL_Msk (0x1ul << EMAC_CTL_RMIIRXCTL_Pos) /*!< EMAC_T::CTL: RMIIRXCTL Mask */
#define EMAC_CTL_OPMODE_Pos (20) /*!< EMAC_T::CTL: OPMODE Position */
#define EMAC_CTL_OPMODE_Msk (0x1ul << EMAC_CTL_OPMODE_Pos) /*!< EMAC_T::CTL: OPMODE Mask */
#define EMAC_CTL_RMIIEN_Pos (22) /*!< EMAC_T::CTL: RMIIEN Position */
#define EMAC_CTL_RMIIEN_Msk (0x1ul << EMAC_CTL_RMIIEN_Pos) /*!< EMAC_T::CTL: RMIIEN Mask */
#define EMAC_CTL_RST_Pos (24) /*!< EMAC_T::CTL: RST Position */
#define EMAC_CTL_RST_Msk (0x1ul << EMAC_CTL_RST_Pos) /*!< EMAC_T::CTL: RST Mask */
#define EMAC_MIIMDAT_DATA_Pos (0) /*!< EMAC_T::MIIMDAT: DATA Position */
#define EMAC_MIIMDAT_DATA_Msk (0xfffful << EMAC_MIIMDAT_DATA_Pos) /*!< EMAC_T::MIIMDAT: DATA Mask */
#define EMAC_MIIMCTL_PHYREG_Pos (0) /*!< EMAC_T::MIIMCTL: PHYREG Position */
#define EMAC_MIIMCTL_PHYREG_Msk (0x1ful << EMAC_MIIMCTL_PHYREG_Pos) /*!< EMAC_T::MIIMCTL: PHYREG Mask */
#define EMAC_MIIMCTL_PHYADDR_Pos (8) /*!< EMAC_T::MIIMCTL: PHYADDR Position */
#define EMAC_MIIMCTL_PHYADDR_Msk (0x1ful << EMAC_MIIMCTL_PHYADDR_Pos) /*!< EMAC_T::MIIMCTL: PHYADDR Mask */
#define EMAC_MIIMCTL_WRITE_Pos (16) /*!< EMAC_T::MIIMCTL: WRITE Position */
#define EMAC_MIIMCTL_WRITE_Msk (0x1ul << EMAC_MIIMCTL_WRITE_Pos) /*!< EMAC_T::MIIMCTL: WRITE Mask */
#define EMAC_MIIMCTL_BUSY_Pos (17) /*!< EMAC_T::MIIMCTL: BUSY Position */
#define EMAC_MIIMCTL_BUSY_Msk (0x1ul << EMAC_MIIMCTL_BUSY_Pos) /*!< EMAC_T::MIIMCTL: BUSY Mask */
#define EMAC_MIIMCTL_PREAMSP_Pos (18) /*!< EMAC_T::MIIMCTL: PREAMSP Position */
#define EMAC_MIIMCTL_PREAMSP_Msk (0x1ul << EMAC_MIIMCTL_PREAMSP_Pos) /*!< EMAC_T::MIIMCTL: PREAMSP Mask */
#define EMAC_MIIMCTL_MDCON_Pos (19) /*!< EMAC_T::MIIMCTL: MDCON Position */
#define EMAC_MIIMCTL_MDCON_Msk (0x1ul << EMAC_MIIMCTL_MDCON_Pos) /*!< EMAC_T::MIIMCTL: MDCON Mask */
#define EMAC_FIFOCTL_RXFIFOTH_Pos (0) /*!< EMAC_T::FIFOCTL: RXFIFOTH Position */
#define EMAC_FIFOCTL_RXFIFOTH_Msk (0x3ul << EMAC_FIFOCTL_RXFIFOTH_Pos) /*!< EMAC_T::FIFOCTL: RXFIFOTH Mask */
#define EMAC_FIFOCTL_TXFIFOTH_Pos (8) /*!< EMAC_T::FIFOCTL: TXFIFOTH Position */
#define EMAC_FIFOCTL_TXFIFOTH_Msk (0x3ul << EMAC_FIFOCTL_TXFIFOTH_Pos) /*!< EMAC_T::FIFOCTL: TXFIFOTH Mask */
#define EMAC_FIFOCTL_BURSTLEN_Pos (20) /*!< EMAC_T::FIFOCTL: BURSTLEN Position */
#define EMAC_FIFOCTL_BURSTLEN_Msk (0x3ul << EMAC_FIFOCTL_BURSTLEN_Pos) /*!< EMAC_T::FIFOCTL: BURSTLEN Mask */
#define EMAC_TXST_TXST_Pos (0) /*!< EMAC_T::TXST: TXST Position */
#define EMAC_TXST_TXST_Msk (0xfffffffful << EMAC_TXST_TXST_Pos) /*!< EMAC_T::TXST: TXST Mask */
#define EMAC_RXST_RXST_Pos (0) /*!< EMAC_T::RXST: RXST Position */
#define EMAC_RXST_RXST_Msk (0xfffffffful << EMAC_RXST_RXST_Pos) /*!< EMAC_T::RXST: RXST Mask */
#define EMAC_MRFL_MRFL_Pos (0) /*!< EMAC_T::MRFL: MRFL Position */
#define EMAC_MRFL_MRFL_Msk (0xfffful << EMAC_MRFL_MRFL_Pos) /*!< EMAC_T::MRFL: MRFL Mask */
#define EMAC_INTEN_RXIEN_Pos (0) /*!< EMAC_T::INTEN: RXIEN Position */
#define EMAC_INTEN_RXIEN_Msk (0x1ul << EMAC_INTEN_RXIEN_Pos) /*!< EMAC_T::INTEN: RXIEN Mask */
#define EMAC_INTEN_CRCEIEN_Pos (1) /*!< EMAC_T::INTEN: CRCEIEN Position */
#define EMAC_INTEN_CRCEIEN_Msk (0x1ul << EMAC_INTEN_CRCEIEN_Pos) /*!< EMAC_T::INTEN: CRCEIEN Mask */
#define EMAC_INTEN_RXOVIEN_Pos (2) /*!< EMAC_T::INTEN: RXOVIEN Position */
#define EMAC_INTEN_RXOVIEN_Msk (0x1ul << EMAC_INTEN_RXOVIEN_Pos) /*!< EMAC_T::INTEN: RXOVIEN Mask */
#define EMAC_INTEN_LPIEN_Pos (3) /*!< EMAC_T::INTEN: LPIEN Position */
#define EMAC_INTEN_LPIEN_Msk (0x1ul << EMAC_INTEN_LPIEN_Pos) /*!< EMAC_T::INTEN: LPIEN Mask */
#define EMAC_INTEN_RXGDIEN_Pos (4) /*!< EMAC_T::INTEN: RXGDIEN Position */
#define EMAC_INTEN_RXGDIEN_Msk (0x1ul << EMAC_INTEN_RXGDIEN_Pos) /*!< EMAC_T::INTEN: RXGDIEN Mask */
#define EMAC_INTEN_ALIEIEN_Pos (5) /*!< EMAC_T::INTEN: ALIEIEN Position */
#define EMAC_INTEN_ALIEIEN_Msk (0x1ul << EMAC_INTEN_ALIEIEN_Pos) /*!< EMAC_T::INTEN: ALIEIEN Mask */
#define EMAC_INTEN_RPIEN_Pos (6) /*!< EMAC_T::INTEN: RPIEN Position */
#define EMAC_INTEN_RPIEN_Msk (0x1ul << EMAC_INTEN_RPIEN_Pos) /*!< EMAC_T::INTEN: RPIEN Mask */
#define EMAC_INTEN_MPCOVIEN_Pos (7) /*!< EMAC_T::INTEN: MPCOVIEN Position */
#define EMAC_INTEN_MPCOVIEN_Msk (0x1ul << EMAC_INTEN_MPCOVIEN_Pos) /*!< EMAC_T::INTEN: MPCOVIEN Mask */
#define EMAC_INTEN_MFLEIEN_Pos (8) /*!< EMAC_T::INTEN: MFLEIEN Position */
#define EMAC_INTEN_MFLEIEN_Msk (0x1ul << EMAC_INTEN_MFLEIEN_Pos) /*!< EMAC_T::INTEN: MFLEIEN Mask */
#define EMAC_INTEN_DENIEN_Pos (9) /*!< EMAC_T::INTEN: DENIEN Position */
#define EMAC_INTEN_DENIEN_Msk (0x1ul << EMAC_INTEN_DENIEN_Pos) /*!< EMAC_T::INTEN: DENIEN Mask */
#define EMAC_INTEN_RDUIEN_Pos (10) /*!< EMAC_T::INTEN: RDUIEN Position */
#define EMAC_INTEN_RDUIEN_Msk (0x1ul << EMAC_INTEN_RDUIEN_Pos) /*!< EMAC_T::INTEN: RDUIEN Mask */
#define EMAC_INTEN_RXBEIEN_Pos (11) /*!< EMAC_T::INTEN: RXBEIEN Position */
#define EMAC_INTEN_RXBEIEN_Msk (0x1ul << EMAC_INTEN_RXBEIEN_Pos) /*!< EMAC_T::INTEN: RXBEIEN Mask */
#define EMAC_INTEN_CFRIEN_Pos (14) /*!< EMAC_T::INTEN: CFRIEN Position */
#define EMAC_INTEN_CFRIEN_Msk (0x1ul << EMAC_INTEN_CFRIEN_Pos) /*!< EMAC_T::INTEN: CFRIEN Mask */
#define EMAC_INTEN_WOLIEN_Pos (15) /*!< EMAC_T::INTEN: WOLIEN Position */
#define EMAC_INTEN_WOLIEN_Msk (0x1ul << EMAC_INTEN_WOLIEN_Pos) /*!< EMAC_T::INTEN: WOLIEN Mask */
#define EMAC_INTEN_TXIEN_Pos (16) /*!< EMAC_T::INTEN: TXIEN Position */
#define EMAC_INTEN_TXIEN_Msk (0x1ul << EMAC_INTEN_TXIEN_Pos) /*!< EMAC_T::INTEN: TXIEN Mask */
#define EMAC_INTEN_TXUDIEN_Pos (17) /*!< EMAC_T::INTEN: TXUDIEN Position */
#define EMAC_INTEN_TXUDIEN_Msk (0x1ul << EMAC_INTEN_TXUDIEN_Pos) /*!< EMAC_T::INTEN: TXUDIEN Mask */
#define EMAC_INTEN_TXCPIEN_Pos (18) /*!< EMAC_T::INTEN: TXCPIEN Position */
#define EMAC_INTEN_TXCPIEN_Msk (0x1ul << EMAC_INTEN_TXCPIEN_Pos) /*!< EMAC_T::INTEN: TXCPIEN Mask */
#define EMAC_INTEN_EXDEFIEN_Pos (19) /*!< EMAC_T::INTEN: EXDEFIEN Position */
#define EMAC_INTEN_EXDEFIEN_Msk (0x1ul << EMAC_INTEN_EXDEFIEN_Pos) /*!< EMAC_T::INTEN: EXDEFIEN Mask */
#define EMAC_INTEN_NCSIEN_Pos (20) /*!< EMAC_T::INTEN: NCSIEN Position */
#define EMAC_INTEN_NCSIEN_Msk (0x1ul << EMAC_INTEN_NCSIEN_Pos) /*!< EMAC_T::INTEN: NCSIEN Mask */
#define EMAC_INTEN_TXABTIEN_Pos (21) /*!< EMAC_T::INTEN: TXABTIEN Position */
#define EMAC_INTEN_TXABTIEN_Msk (0x1ul << EMAC_INTEN_TXABTIEN_Pos) /*!< EMAC_T::INTEN: TXABTIEN Mask */
#define EMAC_INTEN_LCIEN_Pos (22) /*!< EMAC_T::INTEN: LCIEN Position */
#define EMAC_INTEN_LCIEN_Msk (0x1ul << EMAC_INTEN_LCIEN_Pos) /*!< EMAC_T::INTEN: LCIEN Mask */
#define EMAC_INTEN_TDUIEN_Pos (23) /*!< EMAC_T::INTEN: TDUIEN Position */
#define EMAC_INTEN_TDUIEN_Msk (0x1ul << EMAC_INTEN_TDUIEN_Pos) /*!< EMAC_T::INTEN: TDUIEN Mask */
#define EMAC_INTEN_TXBEIEN_Pos (24) /*!< EMAC_T::INTEN: TXBEIEN Position */
#define EMAC_INTEN_TXBEIEN_Msk (0x1ul << EMAC_INTEN_TXBEIEN_Pos) /*!< EMAC_T::INTEN: TXBEIEN Mask */
#define EMAC_INTEN_TSALMIEN_Pos (28) /*!< EMAC_T::INTEN: TSALMIEN Position */
#define EMAC_INTEN_TSALMIEN_Msk (0x1ul << EMAC_INTEN_TSALMIEN_Pos) /*!< EMAC_T::INTEN: TSALMIEN Mask */
#define EMAC_INTSTS_RXIF_Pos (0) /*!< EMAC_T::INTSTS: RXIF Position */
#define EMAC_INTSTS_RXIF_Msk (0x1ul << EMAC_INTSTS_RXIF_Pos) /*!< EMAC_T::INTSTS: RXIF Mask */
#define EMAC_INTSTS_CRCEIF_Pos (1) /*!< EMAC_T::INTSTS: CRCEIF Position */
#define EMAC_INTSTS_CRCEIF_Msk (0x1ul << EMAC_INTSTS_CRCEIF_Pos) /*!< EMAC_T::INTSTS: CRCEIF Mask */
#define EMAC_INTSTS_RXOVIF_Pos (2) /*!< EMAC_T::INTSTS: RXOVIF Position */
#define EMAC_INTSTS_RXOVIF_Msk (0x1ul << EMAC_INTSTS_RXOVIF_Pos) /*!< EMAC_T::INTSTS: RXOVIF Mask */
#define EMAC_INTSTS_LPIF_Pos (3) /*!< EMAC_T::INTSTS: LPIF Position */
#define EMAC_INTSTS_LPIF_Msk (0x1ul << EMAC_INTSTS_LPIF_Pos) /*!< EMAC_T::INTSTS: LPIF Mask */
#define EMAC_INTSTS_RXGDIF_Pos (4) /*!< EMAC_T::INTSTS: RXGDIF Position */
#define EMAC_INTSTS_RXGDIF_Msk (0x1ul << EMAC_INTSTS_RXGDIF_Pos) /*!< EMAC_T::INTSTS: RXGDIF Mask */
#define EMAC_INTSTS_ALIEIF_Pos (5) /*!< EMAC_T::INTSTS: ALIEIF Position */
#define EMAC_INTSTS_ALIEIF_Msk (0x1ul << EMAC_INTSTS_ALIEIF_Pos) /*!< EMAC_T::INTSTS: ALIEIF Mask */
#define EMAC_INTSTS_RPIF_Pos (6) /*!< EMAC_T::INTSTS: RPIF Position */
#define EMAC_INTSTS_RPIF_Msk (0x1ul << EMAC_INTSTS_RPIF_Pos) /*!< EMAC_T::INTSTS: RPIF Mask */
#define EMAC_INTSTS_MPCOVIF_Pos (7) /*!< EMAC_T::INTSTS: MPCOVIF Position */
#define EMAC_INTSTS_MPCOVIF_Msk (0x1ul << EMAC_INTSTS_MPCOVIF_Pos) /*!< EMAC_T::INTSTS: MPCOVIF Mask */
#define EMAC_INTSTS_MFLEIF_Pos (8) /*!< EMAC_T::INTSTS: MFLEIF Position */
#define EMAC_INTSTS_MFLEIF_Msk (0x1ul << EMAC_INTSTS_MFLEIF_Pos) /*!< EMAC_T::INTSTS: MFLEIF Mask */
#define EMAC_INTSTS_DENIF_Pos (9) /*!< EMAC_T::INTSTS: DENIF Position */
#define EMAC_INTSTS_DENIF_Msk (0x1ul << EMAC_INTSTS_DENIF_Pos) /*!< EMAC_T::INTSTS: DENIF Mask */
#define EMAC_INTSTS_RDUIF_Pos (10) /*!< EMAC_T::INTSTS: RDUIF Position */
#define EMAC_INTSTS_RDUIF_Msk (0x1ul << EMAC_INTSTS_RDUIF_Pos) /*!< EMAC_T::INTSTS: RDUIF Mask */
#define EMAC_INTSTS_RXBEIF_Pos (11) /*!< EMAC_T::INTSTS: RXBEIF Position */
#define EMAC_INTSTS_RXBEIF_Msk (0x1ul << EMAC_INTSTS_RXBEIF_Pos) /*!< EMAC_T::INTSTS: RXBEIF Mask */
#define EMAC_INTSTS_CFRIF_Pos (14) /*!< EMAC_T::INTSTS: CFRIF Position */
#define EMAC_INTSTS_CFRIF_Msk (0x1ul << EMAC_INTSTS_CFRIF_Pos) /*!< EMAC_T::INTSTS: CFRIF Mask */
#define EMAC_INTSTS_WOLIF_Pos (15) /*!< EMAC_T::INTSTS: WOLIF Position */
#define EMAC_INTSTS_WOLIF_Msk (0x1ul << EMAC_INTSTS_WOLIF_Pos) /*!< EMAC_T::INTSTS: WOLIF Mask */
#define EMAC_INTSTS_TXIF_Pos (16) /*!< EMAC_T::INTSTS: TXIF Position */
#define EMAC_INTSTS_TXIF_Msk (0x1ul << EMAC_INTSTS_TXIF_Pos) /*!< EMAC_T::INTSTS: TXIF Mask */
#define EMAC_INTSTS_TXUDIF_Pos (17) /*!< EMAC_T::INTSTS: TXUDIF Position */
#define EMAC_INTSTS_TXUDIF_Msk (0x1ul << EMAC_INTSTS_TXUDIF_Pos) /*!< EMAC_T::INTSTS: TXUDIF Mask */
#define EMAC_INTSTS_TXCPIF_Pos (18) /*!< EMAC_T::INTSTS: TXCPIF Position */
#define EMAC_INTSTS_TXCPIF_Msk (0x1ul << EMAC_INTSTS_TXCPIF_Pos) /*!< EMAC_T::INTSTS: TXCPIF Mask */
#define EMAC_INTSTS_EXDEFIF_Pos (19) /*!< EMAC_T::INTSTS: EXDEFIF Position */
#define EMAC_INTSTS_EXDEFIF_Msk (0x1ul << EMAC_INTSTS_EXDEFIF_Pos) /*!< EMAC_T::INTSTS: EXDEFIF Mask */
#define EMAC_INTSTS_NCSIF_Pos (20) /*!< EMAC_T::INTSTS: NCSIF Position */
#define EMAC_INTSTS_NCSIF_Msk (0x1ul << EMAC_INTSTS_NCSIF_Pos) /*!< EMAC_T::INTSTS: NCSIF Mask */
#define EMAC_INTSTS_TXABTIF_Pos (21) /*!< EMAC_T::INTSTS: TXABTIF Position */
#define EMAC_INTSTS_TXABTIF_Msk (0x1ul << EMAC_INTSTS_TXABTIF_Pos) /*!< EMAC_T::INTSTS: TXABTIF Mask */
#define EMAC_INTSTS_LCIF_Pos (22) /*!< EMAC_T::INTSTS: LCIF Position */
#define EMAC_INTSTS_LCIF_Msk (0x1ul << EMAC_INTSTS_LCIF_Pos) /*!< EMAC_T::INTSTS: LCIF Mask */
#define EMAC_INTSTS_TDUIF_Pos (23) /*!< EMAC_T::INTSTS: TDUIF Position */
#define EMAC_INTSTS_TDUIF_Msk (0x1ul << EMAC_INTSTS_TDUIF_Pos) /*!< EMAC_T::INTSTS: TDUIF Mask */
#define EMAC_INTSTS_TXBEIF_Pos (24) /*!< EMAC_T::INTSTS: TXBEIF Position */
#define EMAC_INTSTS_TXBEIF_Msk (0x1ul << EMAC_INTSTS_TXBEIF_Pos) /*!< EMAC_T::INTSTS: TXBEIF Mask */
#define EMAC_INTSTS_TSALMIF_Pos (28) /*!< EMAC_T::INTSTS: TSALMIF Position */
#define EMAC_INTSTS_TSALMIF_Msk (0x1ul << EMAC_INTSTS_TSALMIF_Pos) /*!< EMAC_T::INTSTS: TSALMIF Mask */
#define EMAC_GENSTS_CFR_Pos (0) /*!< EMAC_T::GENSTS: CFR Position */
#define EMAC_GENSTS_CFR_Msk (0x1ul << EMAC_GENSTS_CFR_Pos) /*!< EMAC_T::GENSTS: CFR Mask */
#define EMAC_GENSTS_RXHALT_Pos (1) /*!< EMAC_T::GENSTS: RXHALT Position */
#define EMAC_GENSTS_RXHALT_Msk (0x1ul << EMAC_GENSTS_RXHALT_Pos) /*!< EMAC_T::GENSTS: RXHALT Mask */
#define EMAC_GENSTS_RXFFULL_Pos (2) /*!< EMAC_T::GENSTS: RXFFULL Position */
#define EMAC_GENSTS_RXFFULL_Msk (0x1ul << EMAC_GENSTS_RXFFULL_Pos) /*!< EMAC_T::GENSTS: RXFFULL Mask */
#define EMAC_GENSTS_COLCNT_Pos (4) /*!< EMAC_T::GENSTS: COLCNT Position */
#define EMAC_GENSTS_COLCNT_Msk (0xful << EMAC_GENSTS_COLCNT_Pos) /*!< EMAC_T::GENSTS: COLCNT Mask */
#define EMAC_GENSTS_DEF_Pos (8) /*!< EMAC_T::GENSTS: DEF Position */
#define EMAC_GENSTS_DEF_Msk (0x1ul << EMAC_GENSTS_DEF_Pos) /*!< EMAC_T::GENSTS: DEF Mask */
#define EMAC_GENSTS_TXPAUSED_Pos (9) /*!< EMAC_T::GENSTS: TXPAUSED Position */
#define EMAC_GENSTS_TXPAUSED_Msk (0x1ul << EMAC_GENSTS_TXPAUSED_Pos) /*!< EMAC_T::GENSTS: TXPAUSED Mask */
#define EMAC_GENSTS_SQE_Pos (10) /*!< EMAC_T::GENSTS: SQE Position */
#define EMAC_GENSTS_SQE_Msk (0x1ul << EMAC_GENSTS_SQE_Pos) /*!< EMAC_T::GENSTS: SQE Mask */
#define EMAC_GENSTS_TXHALT_Pos (11) /*!< EMAC_T::GENSTS: TXHALT Position */
#define EMAC_GENSTS_TXHALT_Msk (0x1ul << EMAC_GENSTS_TXHALT_Pos) /*!< EMAC_T::GENSTS: TXHALT Mask */
#define EMAC_GENSTS_RPSTS_Pos (12) /*!< EMAC_T::GENSTS: RPSTS Position */
#define EMAC_GENSTS_RPSTS_Msk (0x1ul << EMAC_GENSTS_RPSTS_Pos) /*!< EMAC_T::GENSTS: RPSTS Mask */
#define EMAC_MPCNT_MPCNT_Pos (0) /*!< EMAC_T::MPCNT: MPCNT Position */
#define EMAC_MPCNT_MPCNT_Msk (0xfffful << EMAC_MPCNT_MPCNT_Pos) /*!< EMAC_T::MPCNT: MPCNT Mask */
#define EMAC_RPCNT_RPCNT_Pos (0) /*!< EMAC_T::RPCNT: RPCNT Position */
#define EMAC_RPCNT_RPCNT_Msk (0xfffful << EMAC_RPCNT_RPCNT_Pos) /*!< EMAC_T::RPCNT: RPCNT Mask */
#define EMAC_FRSTS_RXFLT_Pos (0) /*!< EMAC_T::FRSTS: RXFLT Position */
#define EMAC_FRSTS_RXFLT_Msk (0xfffful << EMAC_FRSTS_RXFLT_Pos) /*!< EMAC_T::FRSTS: RXFLT Mask */
#define EMAC_CTXDSA_CTXDSA_Pos (0) /*!< EMAC_T::CTXDSA: CTXDSA Position */
#define EMAC_CTXDSA_CTXDSA_Msk (0xfffffffful << EMAC_CTXDSA_CTXDSA_Pos) /*!< EMAC_T::CTXDSA: CTXDSA Mask */
#define EMAC_CTXBSA_CTXBSA_Pos (0) /*!< EMAC_T::CTXBSA: CTXBSA Position */
#define EMAC_CTXBSA_CTXBSA_Msk (0xfffffffful << EMAC_CTXBSA_CTXBSA_Pos) /*!< EMAC_T::CTXBSA: CTXBSA Mask */
#define EMAC_CRXDSA_CRXDSA_Pos (0) /*!< EMAC_T::CRXDSA: CRXDSA Position */
#define EMAC_CRXDSA_CRXDSA_Msk (0xfffffffful << EMAC_CRXDSA_CRXDSA_Pos) /*!< EMAC_T::CRXDSA: CRXDSA Mask */
#define EMAC_CRXBSA_CRXBSA_Pos (0) /*!< EMAC_T::CRXBSA: CRXBSA Position */
#define EMAC_CRXBSA_CRXBSA_Msk (0xfffffffful << EMAC_CRXBSA_CRXBSA_Pos) /*!< EMAC_T::CRXBSA: CRXBSA Mask */
#define EMAC_TSCTL_TSEN_Pos (0) /*!< EMAC_T::TSCTL: TSEN Position */
#define EMAC_TSCTL_TSEN_Msk (0x1ul << EMAC_TSCTL_TSEN_Pos) /*!< EMAC_T::TSCTL: TSEN Mask */
#define EMAC_TSCTL_TSIEN_Pos (1) /*!< EMAC_T::TSCTL: TSIEN Position */
#define EMAC_TSCTL_TSIEN_Msk (0x1ul << EMAC_TSCTL_TSIEN_Pos) /*!< EMAC_T::TSCTL: TSIEN Mask */
#define EMAC_TSCTL_TSMODE_Pos (2) /*!< EMAC_T::TSCTL: TSMODE Position */
#define EMAC_TSCTL_TSMODE_Msk (0x1ul << EMAC_TSCTL_TSMODE_Pos) /*!< EMAC_T::TSCTL: TSMODE Mask */
#define EMAC_TSCTL_TSUPDATE_Pos (3) /*!< EMAC_T::TSCTL: TSUPDATE Position */
#define EMAC_TSCTL_TSUPDATE_Msk (0x1ul << EMAC_TSCTL_TSUPDATE_Pos) /*!< EMAC_T::TSCTL: TSUPDATE Mask */
#define EMAC_TSCTL_TSALMEN_Pos (5) /*!< EMAC_T::TSCTL: TSALMEN Position */
#define EMAC_TSCTL_TSALMEN_Msk (0x1ul << EMAC_TSCTL_TSALMEN_Pos) /*!< EMAC_T::TSCTL: TSALMEN Mask */
#define EMAC_TSSEC_SEC_Pos (0) /*!< EMAC_T::TSSEC: SEC Position */
#define EMAC_TSSEC_SEC_Msk (0xfffffffful << EMAC_TSSEC_SEC_Pos) /*!< EMAC_T::TSSEC: SEC Mask */
#define EMAC_TSSUBSEC_SUBSEC_Pos (0) /*!< EMAC_T::TSSUBSEC: SUBSEC Position */
#define EMAC_TSSUBSEC_SUBSEC_Msk (0xfffffffful << EMAC_TSSUBSEC_SUBSEC_Pos) /*!< EMAC_T::TSSUBSEC: SUBSEC Mask */
#define EMAC_TSINC_CNTINC_Pos (0) /*!< EMAC_T::TSINC: CNTINC Position */
#define EMAC_TSINC_CNTINC_Msk (0xfful << EMAC_TSINC_CNTINC_Pos) /*!< EMAC_T::TSINC: CNTINC Mask */
#define EMAC_TSADDEND_ADDEND_Pos (0) /*!< EMAC_T::TSADDEND: ADDEND Position */
#define EMAC_TSADDEND_ADDEND_Msk (0xfffffffful << EMAC_TSADDEND_ADDEND_Pos) /*!< EMAC_T::TSADDEND: ADDEND Mask */
#define EMAC_UPDSEC_SEC_Pos (0) /*!< EMAC_T::UPDSEC: SEC Position */
#define EMAC_UPDSEC_SEC_Msk (0xfffffffful << EMAC_UPDSEC_SEC_Pos) /*!< EMAC_T::UPDSEC: SEC Mask */
#define EMAC_UPDSUBSEC_SUBSEC_Pos (0) /*!< EMAC_T::UPDSUBSEC: SUBSEC Position */
#define EMAC_UPDSUBSEC_SUBSEC_Msk (0xfffffffful << EMAC_UPDSUBSEC_SUBSEC_Pos) /*!< EMAC_T::UPDSUBSEC: SUBSEC Mask */
#define EMAC_ALMSEC_SEC_Pos (0) /*!< EMAC_T::ALMSEC: SEC Position */
#define EMAC_ALMSEC_SEC_Msk (0xfffffffful << EMAC_ALMSEC_SEC_Pos) /*!< EMAC_T::ALMSEC: SEC Mask */
#define EMAC_ALMSUBSEC_SUBSEC_Pos (0) /*!< EMAC_T::ALMSUBSEC: SUBSEC Position */
#define EMAC_ALMSUBSEC_SUBSEC_Msk (0xfffffffful << EMAC_ALMSUBSEC_SUBSEC_Pos) /*!< EMAC_T::ALMSUBSEC: SUBSEC Mask */
/**@}*/ /* EMAC_CONST */
/**@}*/ /* end of EMAC register group */
/*---------------------- Smart Card Host Interface Controller -------------------------*/
/**
@addtogroup SC Smart Card Host Interface Controller(SC)
Memory Mapped Structure for SC Controller
@{ */
typedef struct {
/**
* @var SC_T::DAT
* Offset: 0x00 SC Receive/Transmit Holding Buffer Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |DAT |Receive/Transmit Holding Buffer
* | | |Write Operation:
* | | |By writing data to DAT, the SC will send out an 8-bit data.
* | | |Note: If SCEN (SCn_CTL[0]) is not enabled, DAT cannot be programmed.
* | | |Read Operation:
* | | |By reading DAT, the SC will return an 8-bit received data.
* @var SC_T::CTL
* Offset: 0x04 SC Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SCEN |SC Controller Enable Bit
* | | |Set this bit to 1 to enable SC operation. If this bit is cleared,
* | | |0 = SC will force all transition to IDLE state.
* | | |1 = SC controller is enabled and all function can work correctly.
* | | |Note1: SCEN must be set to 1 before filling in other SC registers, or smart card will not work properly.
* |[1] |RXOFF |RX Transition Disable Control Bit
* | | |This bit is used for disable Rx transition function.
* | | |0 = The receiver Enabled.
* | | |1 = The receiver Disabled.
* | | |Note1: If AUTOCEN (SCn_CTL[3]) is enabled, this field is ignored.
* |[2] |TXOFF |TX Transition Disable Control Bit
* | | |This bit is used for disable Tx transition function.
* | | |0 = The transceiver Enabled.
* | | |1 = The transceiver Disabled.
* |[3] |AUTOCEN |Auto Convention Enable Bit
* | | |This bit is used for enable auto convention function.
* | | |0 = Auto-convention Disabled.
* | | |1 = Auto-convention Enabled.
* | | |If user enables auto convention function, the setting step must be done before Answer to Reset (ATR)
* | | |state and the first data must be 0x3B or 0x3F.
* | | |After hardware received first data and stored it at buffer, hardware will decided the convention and
* | | |change the CONSEL (SCn_CTL[5:4]) bits automatically when received first data is 0x3B or 0x3F.
* | | |If received first byte is 0x3B, TS is direct convention, CONSEL (SCn_CTL[5:4]) will be set to 00
* | | |automatically, otherwise the TS is inverse convention, and CONSEL (SCn_CTL[5:4]) will be set to 11.
* | | |If the first data is not 0x3B or 0x3F, hardware will set ACERRIF (SCn_INTSTS[10]) and generate an
* | | |interrupt to CPU when ACERRIEN (SCn_INTEN[10]) is enabled.
* |[5:4] |CONSEL |Convention Selection
* | | |00 = Direct convention.
* | | |01 = Reserved.
* | | |10 = Reserved.
* | | |11 = Inverse convention.
* | | |Note: If AUTOCEN (SCn_CTL[3]) is enabled, this field is ignored.
* |[7:6] |RXTRGLV |Rx Buffer Trigger Level
* | | |When the number of bytes in the receiving buffer equals the RXTRGLV, the RDAIF will be set
* | | |If RDAIEN (SCn_INTEN[0]) is enabled, an interrupt will be generated to CPU.
* | | |00 = Rx Buffer Trigger Level with 01 bytes.
* | | |01 = Rx Buffer Trigger Level with 02 bytes.
* | | |10 = Rx Buffer Trigger Level with 03 bytes.
* | | |11 = Reserved.
* |[12:8] |BGT |Block Guard Time (BGT)
* | | |Block guard time means the minimum interval between the leading edges of two consecutive characters
* | | |between different transfer directions
* | | |This field indicates the counter for the bit length of block guard time
* | | |According to ISO 7816-3, in T = 0 mode, user must fill 15 (real block guard time = 16.5) to this
* | | |field; in T = 1 mode, user must fill 21 (real block guard time = 22.5) to it.
* | | |Note: The real block guard time is BGT + 1.
* |[14:13] |TMRSEL |Timer Channel Selection
* | | |00 = All internal timer function Disabled.
* | | |11 = Internal 24 bit timer and two 8 bit timers Enabled
* | | |User can configure them by setting SCn_TMRCTL0[23:0], SCn_TMRCTL1[7:0] and SCn_TMRCTL2[7:0].
* | | |Other configurations are reserved
* |[15] |NSB |Stop Bit Length
* | | |This field indicates the length of stop bit.
* | | |0 = The stop bit length is 2 ETU.
* | | |1= The stop bit length is 1 ETU.
* | | |Note1: The default stop bit length is 2. SC and UART adopts NSB to program the stop bit length.
* | | |Note2: In UART mode, RX can receive the data sequence in 1 stop bit or 2 stop bits with NSB is set to 0.
* |[18:16] |RXRTY |RX Error Retry Count Number
* | | |This field indicates the maximum number of receiver retries that are allowed when parity error has occurred.
* | | |Note1: The real retry number is RXRTY + 1, so 8 is the maximum retry number.
* | | |Note2: This field cannot be changed when RXRTYEN enabled
* | | |The change flow is to disable RXRTYEN first and then fill in new retry value.
* |[19] |RXRTYEN |RX Error Retry Enable Bit
* | | |This bit enables receiver retry function when parity error has occurred.
* | | |0 = RX error retry function Disabled.
* | | |1 = RX error retry function Enabled.
* | | |Note: User must fill in the RXRTY value before enabling this bit.
* |[22:20] |TXRTY |TX Error Retry Count Number
* | | |This field indicates the maximum number of transmitter retries that are allowed when parity
* | | |error has occurred.
* | | |Note1: The real retry number is TXRTY + 1, so 8 is the maximum retry number.
* | | |Note2: This field cannot be changed when TXRTYEN enabled
* | | |The change flow is to disable TXRTYEN first and then fill in new retry value.
* |[23] |TXRTYEN |TX Error Retry Enable Bit
* | | |This bit enables transmitter retry function when parity error has occurred.
* | | |0 = TX error retry function Disabled.
* | | |1 = TX error retry function Enabled.
* |[25:24] |CDDBSEL |Card Detect De-bounce Selection
* | | |This field indicates the card detect de-bounce selection.
* | | |00 = De-bounce sample card insert once per 384 (128 * 3) SC module clocks and de-bounce
* | | |sample card removal once per 128 SC module clocks.
* | | |Other configurations are reserved.
* |[26] |CDLV |Card Detect Level Selection
* | | |0 = When hardware detects the card detect pin (SCn_CD) from high to low, it indicates a card is detected.
* | | |1 = When hardware detects the card detect pin (SCn_CD) from low to high, it indicates a card is detected.
* | | |Note: User must select card detect level before Smart Card controller enabled.
* |[30] |SYNC |SYNC Flag Indicator (Read Only)
* | | |Due to synchronization, user should check this bit before writing a new value to RXRTY and TXRTY fields.
* | | |0 = Synchronizing is completion, user can write new data to RXRTY and TXRTY.
* | | |1 = Last value is synchronizing.
* @var SC_T::ALTCTL
* Offset: 0x08 SC Alternate Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |TXRST |TX Software Reset
* | | |When TXRST is set, all the bytes in the transmit buffer and TX internal state machine will be cleared.
* | | |0 = No effect.
* | | |1 = Reset the TX internal state machine and pointers.
* | | |Note: This bit will be auto cleared after reset is complete.
* |[1] |RXRST |Rx Software Reset
* | | |When RXRST is set, all the bytes in the receive buffer and Rx internal state machine will be cleared.
* | | |0 = No effect.
* | | |1 = Reset the Rx internal state machine and pointers.
* | | |Note: This bit will be auto cleared after reset is complete.
* |[2] |DACTEN |Deactivation Sequence Generator Enable Bit
* | | |This bit enables SC controller to initiate the card by deactivation sequence.
* | | |0 = No effect.
* | | |1 = Deactivation sequence generator Enabled.
* | | |Note1: When the deactivation sequence completed, this bit will be cleared automatically and
* | | |the INITIF (SCn_INTSTS[8]) will be set to 1.
* | | |Note2: This field will be cleared by TXRST (SCn_ALTCTL[0]) and RXRST (SCn_ALTCTL[1])
* | | |Thus, do not fill in this bit DACTEN, TXRST and RXRST at the same time.
* | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed.
* |[3] |ACTEN |Activation Sequence Generator Enable Bit
* | | |This bit enables SC controller to initiate the card by activation sequence.
* | | |0 = No effect.
* | | |1 = Activation sequence generator Enabled.
* | | |Note1: When the activation sequence completed, this bit will be cleared automatically and the
* | | |INITIF (SCn_INTSTS[8]) will be set to 1.
* | | |Note2: This field will be cleared by TXRST (SCn_ALTCTL[0]) and RXRST (SCn_ALTCTL[1])
* | | |Thus, do not fill in this bit ACTEN, TXRST and RXRST at the same time.
* | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed.
* | | |Note4: During the activation sequence, RX is disabled automatically and can not receive data
* | | |After the activation sequence completion, RXOFF (SCn_CTL[1]) keeps the state before hardware activation.
* |[4] |WARSTEN |Warm Reset Sequence Generator Enable Bit
* | | |This bit enables SC controller to initiate the card by warm reset sequence.
* | | |0 = No effect.
* | | |1 = Warm reset sequence generator Enabled.
* | | |Note1: When the warm reset sequence completed, this bit will be cleared automatically and the
* | | |INITIF (SCn_INTSTS[8]) will be set to 1.
* | | |Note2: This field will be cleared by TXRST (SCn_ALTCTL[0]) and RXRST (SCn_ALTCTL[1])
* | | |Thus, do not fill in this bit WARSTEN, TXRST and RXRST at the same time.
* | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed.
* | | |Note4: During the warm reset sequence, RX is disabled automatically and can not receive data
* | | |After the warm reset sequence completion, RXOFF (SCn_CTL[1]) keeps the state before perform
* | | |warm reset sequence.
* |[5] |CNTEN0 |Internal Timer0 Start Enable Bit
* | | |This bit enables Timer 0 to start counting
* | | |User can fill 0 to stop it and set 1 to reload and count
* | | |The counter unit is ETU base.
* | | |0 = Stops counting.
* | | |1 = Start counting.
* | | |Note1: This field is used for internal 24 bit timer when TMRSEL (SCn_CTL[14:13]) is 11 only.
* | | |Note2: If the operation mode is not in auto-reload mode (SCn_TMRCTL0[26] = 0), this bit will
* | | |be auto-cleared by hardware.
* | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed.
* |[6] |CNTEN1 |Internal Timer1 Start Enable Bit
* | | |This bit enables Timer 1 to start counting
* | | |User can fill 0 to stop it and set 1 to reload and count
* | | |The counter unit is ETU base.
* | | |0 = Stops counting.
* | | |1 = Start counting.
* | | |Note1: This field is used for internal 8 bit timer when TMRSEL(SCn_CTL[14:13]) is 11 only
* | | |Do not fill CNTEN1 when TMRSEL (SCn_CTL[14:13]) is not equal to 11.
* | | |Note2: If the operation mode is not in auto-reload mode (SCn_TMRCTL1[26] = 0), this bit will
* | | |be auto-cleared by hardware.
* | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed.
* |[7] |CNTEN2 |Internal Timer2 Start Enable Bit
* | | |This bit enables Timer 2 to start counting
* | | |User can fill 0 to stop it and set 1 to reload and count
* | | |The counter unit is ETU base.
* | | |0 = Stops counting.
* | | |1 = Start counting.
* | | |Note1: This field is used for internal 8 bit timer when TMRSEL (SCn_CTL[14:13]) is 11 only
* | | |Do not fill in CNTEN2 when TMRSEL (SCn_CTL[14:13]) is not equal to 11.
* | | |Note2: If the operation mode is not in auto-reload mode (SCn_TMRCTL2[26] = 0), this bit will
* | | |be auto-cleared by hardware.
* | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed.
* |[9:8] |INITSEL |Initial Timing Selection
* | | |This fields indicates the initial timing of hardware activation, warm-reset or deactivation.
* | | |The unit of initial timing is SC module clock.
* | | |Activation: refer to SC Activation Sequence in Figure 7.17-54.
* | | |Warm-reset: refer to Warm-Reset Sequence in Figure 7.17-5.
* | | |Deactivation: refer to Deactivation Sequence in Figure 7.17-56.
* | | |Note: When set activation and warm reset in Timer0 operation mode 0011, it may have deviation
* | | |at most 128 SC module clock cycles.
* |[11] |ADACEN |Auto Deactivation When Card Removal
* | | |This bit is used for enable hardware auto deactivation when smart card is removed.
* | | |0 = Auto deactivation Disabled.
* | | |1 = Auto deactivation Enabled.
* | | |Note: When the card is removed, hardware will stop any process and then do deactivation sequence
* | | |if this bit is set
* | | |If auto deactivation process completes, hardware will set INITIF (SCn_INTSTS[8]) also.
* |[12] |RXBGTEN |Receiver Block Guard Time Function Enable Bit
* | | |This bit enables the receiver block guard time function.
* | | |0 = Receiver block guard time function Disabled.
* | | |1 = Receiver block guard time function Enabled.
* |[13] |ACTSTS0 |Internal Timer0 Active Status (Read Only)
* | | |This bit indicates the timer counter status of timer0.
* | | |0 = Timer0 is not active.
* | | |1 = Timer0 is active.
* | | |Note: Timer0 is active does not always mean timer0 is counting the CNT (SCn_TMRCTL0[23:0]).
* |[14] |ACTSTS1 |Internal Timer1 Active Status (Read Only)
* | | |This bit indicates the timer counter status of timer1.
* | | |0 = Timer1 is not active.
* | | |1 = Timer1 is active.
* | | |Note: Timer1 is active does not always mean timer1 is counting the CNT (SCn_TMRCTL1[7:0]).
* |[15] |ACTSTS2 |Internal Timer2 Active Status (Read Only)
* | | |This bit indicates the timer counter status of timer2.
* | | |0 = Timer2 is not active.
* | | |1 = Timer2 is active.
* | | |Note: Timer2 is active does not always mean timer2 is counting the CNT (SCn_TMRCTL2[7:0]).
* |[31] |SYNC |SYNC Flag Indicator (Read Only)
* | | |Due to synchronization, user should check this bit when writing a new value to SCn_ALTCTL register.
* | | |0 = Synchronizing is completion, user can write new data to SCn_ALTCTL register.
* | | |1 = Last value is synchronizing.
* @var SC_T::EGT
* Offset: 0x0C SC Extra Guard Time Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |EGT |Extra Guard Time
* | | |This field indicates the extra guard time value.
* | | |Note: The extra guard time unit is ETU base.
* @var SC_T::RXTOUT
* Offset: 0x10 SC Receive Buffer Time-out Counter Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[8:0] |RFTM |SC Receiver FIFO Time-out Counter
* | | |The time-out down counter resets and starts counting whenever the RX buffer received a new data
* | | |Once the counter decrease to 1 and no new data is received or CPU does not read data by
* | | |reading SCn_DAT, a receiver time-out flag RBTOIF (SCn_INTSTS[9]) will be set, and hardware will
* | | |generate an interrupt to CPU when RBTOIEN (SCn_INTEN[9]) is enabled.
* | | |Note1: The counter unit is ETU based and the interval of time-out is RFTM + 0.5.
* | | |Note2: Filling in all 0 to this field indicates to disable this function.
* @var SC_T::ETUCTL
* Offset: 0x14 SC Element Time Unit Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[11:0] |ETURDIV |ETU Rate Divider
* | | |The field is used for ETU clock rate divider.
* | | |The real ETU is ETURDIV + 1.
* | | |Note: User can configure this field, but this field must be greater than 0x04.
* @var SC_T::INTEN
* Offset: 0x18 SC Interrupt Enable Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |RDAIEN |Receive Data Reach Interrupt Enable Bit
* | | |This field is used to enable received data reaching trigger level RXTRGLV (SCn_CTL[7:6]) interrupt.
* | | |0 = Receive data reach trigger level interrupt Disabled.
* | | |1 = Receive data reach trigger level interrupt Enabled.
* |[1] |TBEIEN |Transmit Buffer Empty Interrupt Enable Bit
* | | |This field is used to enable transmit buffer empty interrupt.
* | | |0 = Transmit buffer empty interrupt Disabled.
* | | |1 = Transmit buffer empty interrupt Enabled.
* |[2] |TERRIEN |Transfer Error Interrupt Enable Bit
* | | |This field is used to enable transfer error interrupt
* | | |The transfer error states is at SCn_STATUS register which includes receiver break error
* | | |BEF (SCn_STATUS[6]), frame error FEF (SCn_STATUS[5]), parity error PEF (SCn_STATUS[4]), receive
* | | |buffer overflow error RXOV (SCn_STATUS[0]), transmit buffer overflow error TXOV (SCn_STATUS[8]),
* | | |receiver retry over limit error RXOVERR (SCn_STATUS[22]) and transmitter retry over limit error
* | | |TXOVERR (SCn_STATUS[30]).
* | | |0 = Transfer error interrupt Disabled.
* | | |1 = Transfer error interrupt Enabled.
* |[3] |TMR0IEN |Timer0 Interrupt Enable Bit
* | | |This field is used to enable Timer0 interrupt function.
* | | |0 = Timer0 interrupt Disabled.
* | | |1 = Timer0 interrupt Enabled.
* |[4] |TMR1IEN |Timer1 Interrupt Enable Bit
* | | |This field is used to enable the Timer1 interrupt function.
* | | |0 = Timer1 interrupt Disabled.
* | | |1 = Timer1 interrupt Enabled.
* |[5] |TMR2IEN |Timer2 Interrupt Enable Bit
* | | |This field is used to enable Timer2 interrupt function.
* | | |0 = Timer2 interrupt Disabled.
* | | |1 = Timer2 interrupt Enabled.
* |[6] |BGTIEN |Block Guard Time Interrupt Enable Bit
* | | |This field is used to enable block guard time interrupt in receive direction.
* | | |0 = Block guard time interrupt Disabled.
* | | |1 = Block guard time interrupt Enabled.
* | | |Note: This bit is valid only for receive direction block guard time.
* |[7] |CDIEN |Card Detect Interrupt Enable Bit
* | | |This field is used to enable card detect interrupt
* | | |The card detect status is CDPINSTS (SCn_STATUS[13]).
* | | |0 = Card detect interrupt Disabled.
* | | |1 = Card detect interrupt Enabled.
* |[8] |INITIEN |Initial End Interrupt Enable Bit
* | | |This field is used to enable activation (ACTEN (SCn_ALTCTL[3] = 1)), deactivation
* | | |(DACTEN (SCn_ALTCTL[2] = 1)) and warm reset (WARSTEN (SCn_ALTCTL [4])) sequence complete interrupt.
* | | |0 = Initial end interrupt Disabled.
* | | |1 = Initial end interrupt Enabled.
* |[9] |RXTOIEN |Receiver Buffer Time-out Interrupt Enable Bit
* | | |This field is used to enable receiver buffer time-out interrupt.
* | | |0 = Receiver buffer time-out interrupt Disabled.
* | | |1 = Receiver buffer time-out interrupt Enabled.
* |[10] |ACERRIEN |Auto Convention Error Interrupt Enable Bit
* | | |This field is used to enable auto-convention error interrupt.
* | | |0 = Auto-convention error interrupt Disabled.
* | | |1 = Auto-convention error interrupt Enabled.
* @var SC_T::INTSTS
* Offset: 0x1C SC Interrupt Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |RDAIF |Receive Data Reach Interrupt Status Flag (Read Only)
* | | |This field is used for received data reaching trigger level RXTRGLV (SCn_CTL[7:6]) interrupt status flag.
* | | |0 = Number of receive buffer is less than RXTRGLV setting.
* | | |1 = Number of receive buffer data equals the RXTRGLV setting.
* | | |Note: This bit is read only
* | | |If user reads data from SCn_DAT and receiver buffer data byte number is less than RXTRGLV,
* | | |this bit will be cleared automatically.
* |[1] |TBEIF |Transmit Buffer Empty Interrupt Status Flag (Read Only)
* | | |This field is used for transmit buffer empty interrupt status flag.
* | | |0 = Transmit buffer is not empty.
* | | |1 = Transmit buffer is empty.
* | | |Note: This bit is read only
* | | |If user wants to clear this bit, user must write data to DAT (SCn_DAT[7:0]) and then this bit
* | | |will be cleared automatically.
* |[2] |TERRIF |Transfer Error Interrupt Status Flag
* | | |This field is used for transfer error interrupt status flag
* | | |The transfer error states is at SCn_STATUS register which includes receiver break error
* | | |BEF (SCn_STATUS[6]), frame error FEF (SCn_STATUS[5], parity error PEF (SCn_STATUS[4] and receive
* | | |buffer overflow error RXOV (SCn_STATUS[0]), transmit buffer overflow error TXOV (SCn_STATUS[8]),
* | | |receiver retry over limit error RXOVERR (SCn_STATUS[22] or transmitter retry over limit error
* | | |TXOVERR (SCn_STATUS[30]).
* | | |0 = Transfer error interrupt did not occur.
* | | |1 = Transfer error interrupt occurred.
* | | |Note1: This field is the status flag of BEF, FEF, PEF, RXOV, TXOV, RXOVERR or TXOVERR.
* | | |Note2: This bit can be cleared by writing 1 to it.
* |[3] |TMR0IF |Timer0 Interrupt Status Flag
* | | |This field is used for Timer0 interrupt status flag.
* | | |0 = Timer0 interrupt did not occur.
* | | |1 = Timer0 interrupt occurred.
* | | |Note: This bit can be cleared by writing 1 to it.
* |[4] |TMR1IF |Timer1 Interrupt Status Flag
* | | |This field is used for Timer1 interrupt status flag.
* | | |0 = Timer1 interrupt did not occur.
* | | |1 = Timer1 interrupt occurred.
* | | |Note: This bit can be cleared by writing 1 to it.
* |[5] |TMR2IF |Timer2 Interrupt Status Flag
* | | |This field is used for Timer2 interrupt status flag.
* | | |0 = Timer2 interrupt did not occur.
* | | |1 = Timer2 interrupt occurred.
* | | |Note: This bit can be cleared by writing 1 to it.
* |[6] |BGTIF |Block Guard Time Interrupt Status Flag
* | | |This field is used for indicate block guard time interrupt status flag in receive direction.
* | | |0 = Block guard time interrupt did not occur.
* | | |1 = Block guard time interrupt occurred.
* | | |Note1: This bit is valid only when RXBGTEN (SCn_ALTCTL[12]) is enabled.
* | | |Note2: This bit can be cleared by writing 1 to it.
* |[7] |CDIF |Card Detect Interrupt Status Flag (Read Only)
* | | |This field is used for card detect interrupt status flag
* | | |The card detect status is CINSERT (SCn_STATUS[12]) and CREMOVE (SCn_STATUS[11]).
* | | |0 = Card detect event did not occur.
* | | |1 = Card detect event occurred.
* | | |Note: This bit is read only, user must to clear CINSERT or CREMOVE status to clear it.
* |[8] |INITIF |Initial End Interrupt Status Flag
* | | |This field is used for activation (ACTEN (SCn_ALTCTL[3])), deactivation (DACTEN (SCn_ALTCTL[2]))
* | | |and warm reset (WARSTEN (SCn_ALTCTL[4])) sequence interrupt status flag.
* | | |0 = Initial sequence is not complete.
* | | |1 = Initial sequence is completed.
* | | |Note: This bit can be cleared by writing 1 to it.
* |[9] |RXTOIF |Receive Buffer Time-out Interrupt Status Flag (Read Only)
* | | |This field is used for indicate receive buffer time-out interrupt status flag.
* | | |0 = Receive buffer time-out interrupt did not occur.
* | | |1 = Receive buffer time-out interrupt occurred.
* | | |Note: This bit is read only, user must read all receive buffer remaining data by reading SCn_DAT
* | | |register to clear it.
* |[10] |ACERRIF |Auto Convention Error Interrupt Status Flag
* | | |This field indicates auto convention sequence error.
* | | |0 = Received TS at ATR state is 0x3B or 0x3F.
* | | |1 = Received TS at ATR state is neither 0x3B nor 0x3F.
* | | |Note: This bit can be cleared by writing 1 to it.
* @var SC_T::STATUS
* Offset: 0x20 SC Transfer Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |RXOV |Receive Overflow Error Status Flag
* | | |This bit is set when Rx buffer overflow.
* | | |0 = Rx buffer is not overflow.
* | | |1 = Rx buffer is overflow when the number of received bytes is greater than Rx buffer size (4 bytes).
* | | |Note: This bit can be cleared by writing 1 to it.
* |[1] |RXEMPTY |Receive Buffer Empty Status Flag (Read Only)
* | | |This bit indicates Rx buffer empty or not.
* | | |0 = Rx buffer is not empty.
* | | |1 = Rx buffer is empty, it means the last byte of Rx buffer has read from DAT (SCn_DAT[7:0]) by CPU.
* |[2] |RXFULL |Receive Buffer Full Status Flag (Read Only)
* | | |This bit indicates Rx buffer full or not.
* | | |0 = Rx buffer count is less than 4.
* | | |1 = Rx buffer count equals to 4.
* |[4] |PEF |Receiver Parity Error Status Flag
* | | |This bit is set to logic 1 whenever the received character does not have a valid parity bit.
* | | |0 = Receiver parity error flag did not occur.
* | | |1 = Receiver parity error flag occurred.
* | | |Note1: This bit can be cleared by writing 1 to it.
* | | |Note2: If CPU sets receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not
* | | |set this flag.
* |[5] |FEF |Receiver Frame Error Status Flag
* | | |This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is,
* | | |the stop bit following the last data bit or parity bit is detected as logic 0).
* | | |0 = Receiver frame error flag did not occur.
* | | |1 = Receiver frame error flag occurred.
* | | |Note1: This bit can be cleared by writing 1 to it.
* | | |Note2: If CPU sets receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not
* | | |set this flag.
* |[6] |BEF |Receiver Break Error Status Flag
* | | |This bit is set to logic 1 whenever the received data input (Rx) held in the spacing state
* | | |(logic 0) is longer than a full word transmission time (that is, the total time of start bit +
* | | |data bits + parity bit + stop bit).
* | | |0 = Receiver break error flag did not occur.
* | | |1 = Receiver break error flag occurred.
* | | |Note1: This bit can be cleared by writing 1 to it.
* | | |Note2: If CPU sets receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set
* | | |this flag.
* |[8] |TXOV |Transmit Overflow Error Interrupt Status Flag
* | | |This bit is set when Tx buffer overflow.
* | | |0 = Tx buffer is not overflow.
* | | |1 = Tx buffer is overflow when Tx buffer is full and an additional write operation to DAT (SCn_DAT[7:0]).
* | | |Note: This bit can be cleared by writing 1 to it.
* |[9] |TXEMPTY |Transmit Buffer Empty Status Flag (Read Only)
* | | |This bit indicates TX buffer empty or not.
* | | |0 = Tx buffer is not empty.
* | | |1 = Tx buffer is empty, it means the last byte of Tx buffer has been transferred to Transmitter
* | | |Shift Register.
* | | |Note: This bit will be cleared when writing data into DAT (SCn_DAT[7:0]).
* |[10] |TXFULL |Transmit Buffer Full Status Flag (Read Only)
* | | |This bit indicates Tx buffer full or not.
* | | |0 = Tx buffer count is less than 4.
* | | |1 = Tx buffer count equals to 4.
* |[11] |CREMOVE |Card Removal Status of SCn_CD Pin
* | | |This bit is set whenever card has been removal.
* | | |0 = No effect.
* | | |1 = Card removed.
* | | |Note1: This bit can be cleared by writing 1 to it.
* | | |Note2: Card detect function will start after SCEN (SCn_CTL[0]) set.
* |[12] |CINSERT |Card Insert Status of SCn_CD Pin
* | | |This bit is set whenever card has been inserted.
* | | |0 = No effect.
* | | |1 = Card insert.
* | | |Note1: This bit can be cleared by writing 1 to it.
* | | |Note2: The card detect function will start after SCEN (SCn_CTL[0]) set.
* |[13] |CDPINSTS |Card Detect Pin Status (Read Only)
* | | |This bit is the pin status of SCn_CD.
* | | |0 = The SCn_CD pin state at low.
* | | |1 = The SCn_CD pin state at high.
* |[18:16] |RXPOINT |Receive Buffer Pointer Status (Read Only)
* | | |This field indicates the Rx buffer pointer status
* | | |When SC controller receives one byte from external device, RXPOINT increases one
* | | |When one byte of Rx buffer is read by CPU, RXPOINT decreases one.
* |[21] |RXRERR |Receiver Retry Error
* | | |This bit is used for receiver error retry and set by hardware.
* | | |0 = No Rx retry transfer.
* | | |1 = Rx has any error and retries transfer.
* | | |Note1: This bit can be cleared by writing 1 to it.
* | | |Note2 This bit is a flag and cannot generate any interrupt to CPU.
* | | |Note3: If CPU enables receiver retries function by setting RXRTYEN (SCn_CTL[19]),
* | | |hardware will not set this flag.
* |[22] |RXOVERR |Receiver over Retry Error
* | | |This bit is used for receiver retry counts over than retry number limitation.
* | | |0 = Receiver retries counts is not over than RXRTY (SCn_CTL[18:16]) + 1.
* | | |1 = Receiver retries counts over than RXRTY (SCn_CTL[18:16]) + 1.
* | | |Note1: This bit can be cleared by writing 1 to it.
* | | |Note2: If CPU enables receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware
* | | |will not set this flag.
* |[23] |RXACT |Receiver in Active Status Flag (Read Only)
* | | |This bit indicates Rx transfer status.
* | | |0 = This bit is cleared automatically when Rx transfer is finished.
* | | |1 = This bit is set by hardware when Rx transfer is in active.
* | | |Note: This bit is read only.
* |[26:24] |TXPOINT |Transmit Buffer Pointer Status (Read Only)
* | | |This field indicates the Tx buffer pointer status
* | | |When CPU writes data into SCn_DAT, TXPOINT increases one
* | | |When one byte of Tx buffer is transferred to transmitter shift register, TXPOINT decreases one.
* |[29] |TXRERR |Transmitter Retry Error
* | | |This bit is used for indicate transmitter error retry and set by hardware.
* | | |0 = No Tx retry transfer.
* | | |1 = Tx has any error and retries transfer.
* | | |Note1: This bit can be cleared by writing 1 to it.
* | | |Note2: This bit is a flag and cannot generate any interrupt to CPU.
* |[30] |TXOVERR |Transmitter over Retry Error
* | | |This bit is used for transmitter retry counts over than retry number limitation.
* | | |0 = Transmitter retries counts is not over than TXRTY (SCn_CTL[22:20]) + 1.
* | | |1 = Transmitter retries counts over than TXRTY (SCn_CTL[22:20]) + 1.
* | | |Note: This bit can be cleared by writing 1 to it.
* |[31] |TXACT |Transmit in Active Status Flag (Read Only)
* | | |This bit indicates Tx transmit status.
* | | |0 = This bit is cleared automatically when Tx transfer is finished or the last byte transmission
* | | |has completed.
* | | |1 = Transmit is active and this bit is set by hardware when Tx transfer is in active and the STOP
* | | |bit of the last byte has not been transmitted.
* | | |Note: This bit is read only.
* @var SC_T::PINCTL
* Offset: 0x24 SC Pin Control State Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |PWREN |SCn_PWR Pin Signal
* | | |User can set PWRINV (SCn_PINCTL[11]) and PWREN (SCn_PINCTL[0]) to decide SCn_PWR pin is in high or low level.
* | | |Write this field to drive SCn_PWR pin
* | | |Refer PWRINV (SCn_PINCTL[11]) description for programming SCn_PWR pin voltage level.
* | | |Read this field to get SCn_PWR signal status.
* | | |0 = SCn_PWR signal status is low.
* | | |1 = SCn_PWR signal status is high.
* | | |Note: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically.
* | | |Thus, do not fill in this field when operating in these modes.
* |[1] |RSTEN |SCn_RST Pin Signal
* | | |User can set RSTEN (SCn_PINCTL[1]) to decide SCn_RST pin is in high or low level.
* | | |Write this field to drive SCn_RST pin.
* | | |0 = Drive SCn_RST pin to low.
* | | |1 = Drive SCn_RST pin to high.
* | | |Read this field to get SCn_RST signal status.
* | | |0 = SCn_RST signal status is low.
* | | |1 = SCn_RST signal status is high.
* | | |Note: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically.
* | | |Thus, do not fill in this field when operating in these modes.
* |[6] |CLKKEEP |SC Clock Enable Bit
* | | |0 = SC clock generation Disabled.
* | | |1 = SC clock always keeps free running.
* | | |Note: When operating in activation, warm reset or deactivation mode, this bit will be changed automatically.
* | | |Thus, do not fill in this field when operating in these modes.
* |[9] |SCDATA |SCn_DATA Pin Signal
* | | |This bit is the signal status of SCn_DATA but user can drive SCn_DATA pin to high or low by setting this bit.
* | | |0 = Drive SCn_DATA pin to low.
* | | |1 = Drive SCn_DATA pin to high.
* | | |Read this field to get SCn_DATA signal status.
* | | |0 = SCn_DATA signal status is low.
* | | |1 = SCn_DATA signal status is high.
* | | |Note: When SC is at activation, warm reset or deactivation mode, this bit will be changed automatically.
* | | |Thus, do not fill in this field when SC is in these modes.
* |[11] |PWRINV |SCn_PWR Pin Inverse
* | | |This bit is used for inverse the SCn_PWR pin.
* | | |There are four kinds of combination for SCn_PWR pin setting by PWRINV (SCn_PINCTL[11]) and PWREN (SCn_PINCTL[0]).
* | | |PWRINV is 0 and PWREN is 0, SCn_PWR pin is 0.
* | | |PWRINV is 0 and PWREN is 1, SCn_PWR pin is 1.
* | | |PWRINV is 1 and PWREN is 0, SCn_PWR pin is 1.
* | | |PWRINV is 1 and PWREN is 1, SCn_PWR pin is 0.
* | | |Note: User must select PWRINV (SCn_PINCTL[11]) before smart card is enabled by SCEN (SCn_CTL[0]).
* |[16] |DATASTS |SCn_DATA Pin Status (Read Only)
* | | |This bit is the pin status of SCn_DATA.
* | | |0 = The SCn_DATA pin status is low.
* | | |1 = The SCn_DATA pin status is high.
* |[17] |PWRSTS |SCn_PWR Pin Status (Read Only)
* | | |This bit is the pin status of SCn_PWR.
* | | |0 = SCn_PWR pin to low.
* | | |1 = SCn_PWR pin to high.
* |[18] |RSTSTS |SCn_RST Pin Status (Read Only)
* | | |This bit is the pin status of SCn_RST.
* | | |0 = SCn_RST pin is low.
* | | |1 = SCn_RST pin is high.
* |[30] |SYNC |SYNC Flag Indicator (Read Only)
* | | |Due to synchronization, user should check this bit when writing a new value to SCn_PINCTL register.
* | | |0 = Synchronizing is completion, user can write new data to SCn_PINCTL register.
* | | |1 = Last value is synchronizing.
* @var SC_T::TMRCTL0
* Offset: 0x28 SC Internal Timer0 Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[23:0] |CNT |Timer0 Counter Value
* | | |This field indicates the internal Timer0 counter values.
* | | |Note: Unit of Timer0 counter is ETU base.
* |[27:24] |OPMODE |Timer0 Operation Mode Selection
* | | |This field indicates the internal 24-bit Timer0 operation selection.
* | | |Refer to Table 7.17-3 for programming Timer0.
* |[31] |SYNC |SYNC Flag Indicator (Read Only)
* | | |Due to synchronization, user should check this bit when writing a new value to the SCn_TMRCTL0 register.
* | | |0 = Synchronizing is completion, user can write new data to SCn_TMRCTL0 register.
* | | |1 = Last value is synchronizing.
* @var SC_T::TMRCTL1
* Offset: 0x2C SC Internal Timer1 Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |CNT |Timer 1 Counter Value
* | | |This field indicates the internal Timer1 counter values.
* | | |Note: Unit of Timer1 counter is ETU base.
* |[27:24] |OPMODE |Timer 1 Operation Mode Selection
* | | |This field indicates the internal 8-bit Timer1 operation selection.
* | | |Refer to Table 7.17-3 for programming Timer1.
* |[31] |SYNC |SYNC Flag Indicator (Read Only)
* | | |Due to synchronization, software should check this bit when writing a new value to SCn_TMRCTL1 register.
* | | |0 = Synchronizing is completion, user can write new data to SCn_TMRCTL1 register.
* | | |1 = Last value is synchronizing.
* @var SC_T::TMRCTL2
* Offset: 0x30 SC Internal Timer2 Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |CNT |Timer 2 Counter Value
* | | |This field indicates the internal Timer2 counter values.
* | | |Note: Unit of Timer2 counter is ETU base.
* |[27:24] |OPMODE |Timer 2 Operation Mode Selection
* | | |This field indicates the internal 8-bit Timer2 operation selection
* | | |Refer to Table 7.17-3 for programming Timer2.
* |[31] |SYNC |SYNC Flag Indicator (Read Only)
* | | |Due to synchronization, user should check this bit when writing a new value to SCn_TMRCTL2 register.
* | | |0 = Synchronizing is completion, user can write new data to SCn_TMRCTL2 register.
* | | |1 = Last value is synchronizing.
* @var SC_T::UARTCTL
* Offset: 0x34 SC UART Mode Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |UARTEN |UART Mode Enable Bit
* | | |Sets this bit to enable UART mode function.
* | | |0 = Smart Card mode.
* | | |1 = UART mode.
* | | |Note1: When operating in UART mode, user must set CONSEL (SCn_CTL[5:4]) = 00 and AUTOCEN (SCn_CTL[3]) = 0.
* | | |Note2: When operating in Smart Card mode, user must set UARTEN (SCn_UARTCTL[0]) = 0.
* | | |Note3: When UART mode is enabled, hardware will generate a reset to reset FIFO and internal state machine.
* |[5:4] |WLS |Word Length Selection
* | | |This field is used for select UART data length.
* | | |00 = Word length is 8 bits.
* | | |01 = Word length is 7 bits.
* | | |10 = Word length is 6 bits.
* | | |11 = Word length is 5 bits.
* | | |Note: In smart card mode, this WLS must be '00'.
* |[6] |PBOFF |Parity Bit Disable Control
* | | |Sets this bit is used for disable parity check function.
* | | |0 = Parity bit is generated or checked between the last data word bit and stop bit of the serial data.
* | | |1 = Parity bit is not generated (transmitting data) or checked (receiving data) during transfer.
* | | |Note: In smart card mode, this field must be '0' (default setting is with parity bit).
* |[7] |OPE |Odd Parity Enable Bit
* | | |This is used for odd/even parity selection.
* | | |0 = Even number of logic 1's are transmitted or check the data word and parity bits in receiving mode.
* | | |1 = Odd number of logic 1's are transmitted or check the data word and parity bits in receiving mode.
* | | |Note: This bit has effect only when PBOFF bit is '0'.
* @var SC_T::ACTCTL
* Offset: 0x4C SC Activation Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[4:0] |T1EXT |T1 Extend Time of Hardware Activation
* | | |This field provide the configurable cycles to extend the activation time T1 period.
* | | |The cycle scaling factor is 2048.
* | | |Extend cycles = (filled value * 2048) cycles.
* | | |Refer to SC activation sequence in Figure 7.17-4.
* | | |For example,
* | | |SCLK = 4MHz, each cycle = 0.25us,.
* | | |Filled 20 to this field
* | | |Extend time = 20 * 2048 * 0.25us = 10.24 ms.
* | | |Note: Setting 0 to this field conforms to the protocol ISO/IEC 7816-3
*/
__IO uint32_t DAT; /*!< [0x0000] SC Receive/Transmit Holding Buffer Register */
__IO uint32_t CTL; /*!< [0x0004] SC Control Register */
__IO uint32_t ALTCTL; /*!< [0x0008] SC Alternate Control Register */
__IO uint32_t EGT; /*!< [0x000c] SC Extra Guard Time Register */
__IO uint32_t RXTOUT; /*!< [0x0010] SC Receive Buffer Time-out Counter Register */
__IO uint32_t ETUCTL; /*!< [0x0014] SC Element Time Unit Control Register */
__IO uint32_t INTEN; /*!< [0x0018] SC Interrupt Enable Control Register */
__IO uint32_t INTSTS; /*!< [0x001c] SC Interrupt Status Register */
__IO uint32_t STATUS; /*!< [0x0020] SC Transfer Status Register */
__IO uint32_t PINCTL; /*!< [0x0024] SC Pin Control State Register */
__IO uint32_t TMRCTL0; /*!< [0x0028] SC Internal Timer0 Control Register */
__IO uint32_t TMRCTL1; /*!< [0x002c] SC Internal Timer1 Control Register */
__IO uint32_t TMRCTL2; /*!< [0x0030] SC Internal Timer2 Control Register */
__IO uint32_t UARTCTL; /*!< [0x0034] SC UART Mode Control Register */
/** @cond HIDDEN_SYMBOLS */
__I uint32_t RESERVE0[5];
/** @endcond */
__IO uint32_t ACTCTL; /*!< [0x004c] SC Activation Control Register */
} SC_T;
/**
@addtogroup SC_CONST SC Bit Field Definition
Constant Definitions for SC Controller
@{ */
#define SC_DAT_DAT_Pos (0) /*!< SC_T::DAT: DAT Position */
#define SC_DAT_DAT_Msk (0xfful << SC_DAT_DAT_Pos) /*!< SC_T::DAT: DAT Mask */
#define SC_CTL_SCEN_Pos (0) /*!< SC_T::CTL: SCEN Position */
#define SC_CTL_SCEN_Msk (0x1ul << SC_CTL_SCEN_Pos) /*!< SC_T::CTL: SCEN Mask */
#define SC_CTL_RXOFF_Pos (1) /*!< SC_T::CTL: RXOFF Position */
#define SC_CTL_RXOFF_Msk (0x1ul << SC_CTL_RXOFF_Pos) /*!< SC_T::CTL: RXOFF Mask */
#define SC_CTL_TXOFF_Pos (2) /*!< SC_T::CTL: TXOFF Position */
#define SC_CTL_TXOFF_Msk (0x1ul << SC_CTL_TXOFF_Pos) /*!< SC_T::CTL: TXOFF Mask */
#define SC_CTL_AUTOCEN_Pos (3) /*!< SC_T::CTL: AUTOCEN Position */
#define SC_CTL_AUTOCEN_Msk (0x1ul << SC_CTL_AUTOCEN_Pos) /*!< SC_T::CTL: AUTOCEN Mask */
#define SC_CTL_CONSEL_Pos (4) /*!< SC_T::CTL: CONSEL Position */
#define SC_CTL_CONSEL_Msk (0x3ul << SC_CTL_CONSEL_Pos) /*!< SC_T::CTL: CONSEL Mask */
#define SC_CTL_RXTRGLV_Pos (6) /*!< SC_T::CTL: RXTRGLV Position */
#define SC_CTL_RXTRGLV_Msk (0x3ul << SC_CTL_RXTRGLV_Pos) /*!< SC_T::CTL: RXTRGLV Mask */
#define SC_CTL_BGT_Pos (8) /*!< SC_T::CTL: BGT Position */
#define SC_CTL_BGT_Msk (0x1ful << SC_CTL_BGT_Pos) /*!< SC_T::CTL: BGT Mask */
#define SC_CTL_TMRSEL_Pos (13) /*!< SC_T::CTL: TMRSEL Position */
#define SC_CTL_TMRSEL_Msk (0x3ul << SC_CTL_TMRSEL_Pos) /*!< SC_T::CTL: TMRSEL Mask */
#define SC_CTL_NSB_Pos (15) /*!< SC_T::CTL: NSB Position */
#define SC_CTL_NSB_Msk (0x1ul << SC_CTL_NSB_Pos) /*!< SC_T::CTL: NSB Mask */
#define SC_CTL_RXRTY_Pos (16) /*!< SC_T::CTL: RXRTY Position */
#define SC_CTL_RXRTY_Msk (0x7ul << SC_CTL_RXRTY_Pos) /*!< SC_T::CTL: RXRTY Mask */
#define SC_CTL_RXRTYEN_Pos (19) /*!< SC_T::CTL: RXRTYEN Position */
#define SC_CTL_RXRTYEN_Msk (0x1ul << SC_CTL_RXRTYEN_Pos) /*!< SC_T::CTL: RXRTYEN Mask */
#define SC_CTL_TXRTY_Pos (20) /*!< SC_T::CTL: TXRTY Position */
#define SC_CTL_TXRTY_Msk (0x7ul << SC_CTL_TXRTY_Pos) /*!< SC_T::CTL: TXRTY Mask */
#define SC_CTL_TXRTYEN_Pos (23) /*!< SC_T::CTL: TXRTYEN Position */
#define SC_CTL_TXRTYEN_Msk (0x1ul << SC_CTL_TXRTYEN_Pos) /*!< SC_T::CTL: TXRTYEN Mask */
#define SC_CTL_CDDBSEL_Pos (24) /*!< SC_T::CTL: CDDBSEL Position */
#define SC_CTL_CDDBSEL_Msk (0x3ul << SC_CTL_CDDBSEL_Pos) /*!< SC_T::CTL: CDDBSEL Mask */
#define SC_CTL_CDLV_Pos (26) /*!< SC_T::CTL: CDLV Position */
#define SC_CTL_CDLV_Msk (0x1ul << SC_CTL_CDLV_Pos) /*!< SC_T::CTL: CDLV Mask */
#define SC_CTL_SYNC_Pos (30) /*!< SC_T::CTL: SYNC Position */
#define SC_CTL_SYNC_Msk (0x1ul << SC_CTL_SYNC_Pos) /*!< SC_T::CTL: SYNC Mask */
#define SC_ALTCTL_TXRST_Pos (0) /*!< SC_T::ALTCTL: TXRST Position */
#define SC_ALTCTL_TXRST_Msk (0x1ul << SC_ALTCTL_TXRST_Pos) /*!< SC_T::ALTCTL: TXRST Mask */
#define SC_ALTCTL_RXRST_Pos (1) /*!< SC_T::ALTCTL: RXRST Position */
#define SC_ALTCTL_RXRST_Msk (0x1ul << SC_ALTCTL_RXRST_Pos) /*!< SC_T::ALTCTL: RXRST Mask */
#define SC_ALTCTL_DACTEN_Pos (2) /*!< SC_T::ALTCTL: DACTEN Position */
#define SC_ALTCTL_DACTEN_Msk (0x1ul << SC_ALTCTL_DACTEN_Pos) /*!< SC_T::ALTCTL: DACTEN Mask */
#define SC_ALTCTL_ACTEN_Pos (3) /*!< SC_T::ALTCTL: ACTEN Position */
#define SC_ALTCTL_ACTEN_Msk (0x1ul << SC_ALTCTL_ACTEN_Pos) /*!< SC_T::ALTCTL: ACTEN Mask */
#define SC_ALTCTL_WARSTEN_Pos (4) /*!< SC_T::ALTCTL: WARSTEN Position */
#define SC_ALTCTL_WARSTEN_Msk (0x1ul << SC_ALTCTL_WARSTEN_Pos) /*!< SC_T::ALTCTL: WARSTEN Mask */
#define SC_ALTCTL_CNTEN0_Pos (5) /*!< SC_T::ALTCTL: CNTEN0 Position */
#define SC_ALTCTL_CNTEN0_Msk (0x1ul << SC_ALTCTL_CNTEN0_Pos) /*!< SC_T::ALTCTL: CNTEN0 Mask */
#define SC_ALTCTL_CNTEN1_Pos (6) /*!< SC_T::ALTCTL: CNTEN1 Position */
#define SC_ALTCTL_CNTEN1_Msk (0x1ul << SC_ALTCTL_CNTEN1_Pos) /*!< SC_T::ALTCTL: CNTEN1 Mask */
#define SC_ALTCTL_CNTEN2_Pos (7) /*!< SC_T::ALTCTL: CNTEN2 Position */
#define SC_ALTCTL_CNTEN2_Msk (0x1ul << SC_ALTCTL_CNTEN2_Pos) /*!< SC_T::ALTCTL: CNTEN2 Mask */
#define SC_ALTCTL_INITSEL_Pos (8) /*!< SC_T::ALTCTL: INITSEL Position */
#define SC_ALTCTL_INITSEL_Msk (0x3ul << SC_ALTCTL_INITSEL_Pos) /*!< SC_T::ALTCTL: INITSEL Mask */
#define SC_ALTCTL_ADACEN_Pos (11) /*!< SC_T::ALTCTL: ADACEN Position */
#define SC_ALTCTL_ADACEN_Msk (0x1ul << SC_ALTCTL_ADACEN_Pos) /*!< SC_T::ALTCTL: ADACEN Mask */
#define SC_ALTCTL_RXBGTEN_Pos (12) /*!< SC_T::ALTCTL: RXBGTEN Position */
#define SC_ALTCTL_RXBGTEN_Msk (0x1ul << SC_ALTCTL_RXBGTEN_Pos) /*!< SC_T::ALTCTL: RXBGTEN Mask */
#define SC_ALTCTL_ACTSTS0_Pos (13) /*!< SC_T::ALTCTL: ACTSTS0 Position */
#define SC_ALTCTL_ACTSTS0_Msk (0x1ul << SC_ALTCTL_ACTSTS0_Pos) /*!< SC_T::ALTCTL: ACTSTS0 Mask */
#define SC_ALTCTL_ACTSTS1_Pos (14) /*!< SC_T::ALTCTL: ACTSTS1 Position */
#define SC_ALTCTL_ACTSTS1_Msk (0x1ul << SC_ALTCTL_ACTSTS1_Pos) /*!< SC_T::ALTCTL: ACTSTS1 Mask */
#define SC_ALTCTL_ACTSTS2_Pos (15) /*!< SC_T::ALTCTL: ACTSTS2 Position */
#define SC_ALTCTL_ACTSTS2_Msk (0x1ul << SC_ALTCTL_ACTSTS2_Pos) /*!< SC_T::ALTCTL: ACTSTS2 Mask */
#define SC_ALTCTL_SYNC_Pos (31) /*!< SC_T::ALTCTL: SYNC Position */
#define SC_ALTCTL_SYNC_Msk (0x1ul << SC_ALTCTL_SYNC_Pos) /*!< SC_T::ALTCTL: SYNC Mask */
#define SC_EGT_EGT_Pos (0) /*!< SC_T::EGT: EGT Position */
#define SC_EGT_EGT_Msk (0xfful << SC_EGT_EGT_Pos) /*!< SC_T::EGT: EGT Mask */
#define SC_RXTOUT_RFTM_Pos (0) /*!< SC_T::RXTOUT: RFTM Position */
#define SC_RXTOUT_RFTM_Msk (0x1fful << SC_RXTOUT_RFTM_Pos) /*!< SC_T::RXTOUT: RFTM Mask */
#define SC_ETUCTL_ETURDIV_Pos (0) /*!< SC_T::ETUCTL: ETURDIV Position */
#define SC_ETUCTL_ETURDIV_Msk (0xffful << SC_ETUCTL_ETURDIV_Pos) /*!< SC_T::ETUCTL: ETURDIV Mask */
#define SC_INTEN_RDAIEN_Pos (0) /*!< SC_T::INTEN: RDAIEN Position */
#define SC_INTEN_RDAIEN_Msk (0x1ul << SC_INTEN_RDAIEN_Pos) /*!< SC_T::INTEN: RDAIEN Mask */
#define SC_INTEN_TBEIEN_Pos (1) /*!< SC_T::INTEN: TBEIEN Position */
#define SC_INTEN_TBEIEN_Msk (0x1ul << SC_INTEN_TBEIEN_Pos) /*!< SC_T::INTEN: TBEIEN Mask */
#define SC_INTEN_TERRIEN_Pos (2) /*!< SC_T::INTEN: TERRIEN Position */
#define SC_INTEN_TERRIEN_Msk (0x1ul << SC_INTEN_TERRIEN_Pos) /*!< SC_T::INTEN: TERRIEN Mask */
#define SC_INTEN_TMR0IEN_Pos (3) /*!< SC_T::INTEN: TMR0IEN Position */
#define SC_INTEN_TMR0IEN_Msk (0x1ul << SC_INTEN_TMR0IEN_Pos) /*!< SC_T::INTEN: TMR0IEN Mask */
#define SC_INTEN_TMR1IEN_Pos (4) /*!< SC_T::INTEN: TMR1IEN Position */
#define SC_INTEN_TMR1IEN_Msk (0x1ul << SC_INTEN_TMR1IEN_Pos) /*!< SC_T::INTEN: TMR1IEN Mask */
#define SC_INTEN_TMR2IEN_Pos (5) /*!< SC_T::INTEN: TMR2IEN Position */
#define SC_INTEN_TMR2IEN_Msk (0x1ul << SC_INTEN_TMR2IEN_Pos) /*!< SC_T::INTEN: TMR2IEN Mask */
#define SC_INTEN_BGTIEN_Pos (6) /*!< SC_T::INTEN: BGTIEN Position */
#define SC_INTEN_BGTIEN_Msk (0x1ul << SC_INTEN_BGTIEN_Pos) /*!< SC_T::INTEN: BGTIEN Mask */
#define SC_INTEN_CDIEN_Pos (7) /*!< SC_T::INTEN: CDIEN Position */
#define SC_INTEN_CDIEN_Msk (0x1ul << SC_INTEN_CDIEN_Pos) /*!< SC_T::INTEN: CDIEN Mask */
#define SC_INTEN_INITIEN_Pos (8) /*!< SC_T::INTEN: INITIEN Position */
#define SC_INTEN_INITIEN_Msk (0x1ul << SC_INTEN_INITIEN_Pos) /*!< SC_T::INTEN: INITIEN Mask */
#define SC_INTEN_RXTOIEN_Pos (9) /*!< SC_T::INTEN: RXTOIEN Position */
#define SC_INTEN_RXTOIEN_Msk (0x1ul << SC_INTEN_RXTOIEN_Pos) /*!< SC_T::INTEN: RXTOIEN Mask */
#define SC_INTEN_ACERRIEN_Pos (10) /*!< SC_T::INTEN: ACERRIEN Position */
#define SC_INTEN_ACERRIEN_Msk (0x1ul << SC_INTEN_ACERRIEN_Pos) /*!< SC_T::INTEN: ACERRIEN Mask */
#define SC_INTSTS_RDAIF_Pos (0) /*!< SC_T::INTSTS: RDAIF Position */
#define SC_INTSTS_RDAIF_Msk (0x1ul << SC_INTSTS_RDAIF_Pos) /*!< SC_T::INTSTS: RDAIF Mask */
#define SC_INTSTS_TBEIF_Pos (1) /*!< SC_T::INTSTS: TBEIF Position */
#define SC_INTSTS_TBEIF_Msk (0x1ul << SC_INTSTS_TBEIF_Pos) /*!< SC_T::INTSTS: TBEIF Mask */
#define SC_INTSTS_TERRIF_Pos (2) /*!< SC_T::INTSTS: TERRIF Position */
#define SC_INTSTS_TERRIF_Msk (0x1ul << SC_INTSTS_TERRIF_Pos) /*!< SC_T::INTSTS: TERRIF Mask */
#define SC_INTSTS_TMR0IF_Pos (3) /*!< SC_T::INTSTS: TMR0IF Position */
#define SC_INTSTS_TMR0IF_Msk (0x1ul << SC_INTSTS_TMR0IF_Pos) /*!< SC_T::INTSTS: TMR0IF Mask */
#define SC_INTSTS_TMR1IF_Pos (4) /*!< SC_T::INTSTS: TMR1IF Position */
#define SC_INTSTS_TMR1IF_Msk (0x1ul << SC_INTSTS_TMR1IF_Pos) /*!< SC_T::INTSTS: TMR1IF Mask */
#define SC_INTSTS_TMR2IF_Pos (5) /*!< SC_T::INTSTS: TMR2IF Position */
#define SC_INTSTS_TMR2IF_Msk (0x1ul << SC_INTSTS_TMR2IF_Pos) /*!< SC_T::INTSTS: TMR2IF Mask */
#define SC_INTSTS_BGTIF_Pos (6) /*!< SC_T::INTSTS: BGTIF Position */
#define SC_INTSTS_BGTIF_Msk (0x1ul << SC_INTSTS_BGTIF_Pos) /*!< SC_T::INTSTS: BGTIF Mask */
#define SC_INTSTS_CDIF_Pos (7) /*!< SC_T::INTSTS: CDIF Position */
#define SC_INTSTS_CDIF_Msk (0x1ul << SC_INTSTS_CDIF_Pos) /*!< SC_T::INTSTS: CDIF Mask */
#define SC_INTSTS_INITIF_Pos (8) /*!< SC_T::INTSTS: INITIF Position */
#define SC_INTSTS_INITIF_Msk (0x1ul << SC_INTSTS_INITIF_Pos) /*!< SC_T::INTSTS: INITIF Mask */
#define SC_INTSTS_RXTOIF_Pos (9) /*!< SC_T::INTSTS: RXTOIF Position */
#define SC_INTSTS_RXTOIF_Msk (0x1ul << SC_INTSTS_RXTOIF_Pos) /*!< SC_T::INTSTS: RXTOIF Mask */
#define SC_INTSTS_ACERRIF_Pos (10) /*!< SC_T::INTSTS: ACERRIF Position */
#define SC_INTSTS_ACERRIF_Msk (0x1ul << SC_INTSTS_ACERRIF_Pos) /*!< SC_T::INTSTS: ACERRIF Mask */
#define SC_STATUS_RXOV_Pos (0) /*!< SC_T::STATUS: RXOV Position */
#define SC_STATUS_RXOV_Msk (0x1ul << SC_STATUS_RXOV_Pos) /*!< SC_T::STATUS: RXOV Mask */
#define SC_STATUS_RXEMPTY_Pos (1) /*!< SC_T::STATUS: RXEMPTY Position */
#define SC_STATUS_RXEMPTY_Msk (0x1ul << SC_STATUS_RXEMPTY_Pos) /*!< SC_T::STATUS: RXEMPTY Mask */
#define SC_STATUS_RXFULL_Pos (2) /*!< SC_T::STATUS: RXFULL Position */
#define SC_STATUS_RXFULL_Msk (0x1ul << SC_STATUS_RXFULL_Pos) /*!< SC_T::STATUS: RXFULL Mask */
#define SC_STATUS_PEF_Pos (4) /*!< SC_T::STATUS: PEF Position */
#define SC_STATUS_PEF_Msk (0x1ul << SC_STATUS_PEF_Pos) /*!< SC_T::STATUS: PEF Mask */
#define SC_STATUS_FEF_Pos (5) /*!< SC_T::STATUS: FEF Position */
#define SC_STATUS_FEF_Msk (0x1ul << SC_STATUS_FEF_Pos) /*!< SC_T::STATUS: FEF Mask */
#define SC_STATUS_BEF_Pos (6) /*!< SC_T::STATUS: BEF Position */
#define SC_STATUS_BEF_Msk (0x1ul << SC_STATUS_BEF_Pos) /*!< SC_T::STATUS: BEF Mask */
#define SC_STATUS_TXOV_Pos (8) /*!< SC_T::STATUS: TXOV Position */
#define SC_STATUS_TXOV_Msk (0x1ul << SC_STATUS_TXOV_Pos) /*!< SC_T::STATUS: TXOV Mask */
#define SC_STATUS_TXEMPTY_Pos (9) /*!< SC_T::STATUS: TXEMPTY Position */
#define SC_STATUS_TXEMPTY_Msk (0x1ul << SC_STATUS_TXEMPTY_Pos) /*!< SC_T::STATUS: TXEMPTY Mask */
#define SC_STATUS_TXFULL_Pos (10) /*!< SC_T::STATUS: TXFULL Position */
#define SC_STATUS_TXFULL_Msk (0x1ul << SC_STATUS_TXFULL_Pos) /*!< SC_T::STATUS: TXFULL Mask */
#define SC_STATUS_CREMOVE_Pos (11) /*!< SC_T::STATUS: CREMOVE Position */
#define SC_STATUS_CREMOVE_Msk (0x1ul << SC_STATUS_CREMOVE_Pos) /*!< SC_T::STATUS: CREMOVE Mask */
#define SC_STATUS_CINSERT_Pos (12) /*!< SC_T::STATUS: CINSERT Position */
#define SC_STATUS_CINSERT_Msk (0x1ul << SC_STATUS_CINSERT_Pos) /*!< SC_T::STATUS: CINSERT Mask */
#define SC_STATUS_CDPINSTS_Pos (13) /*!< SC_T::STATUS: CDPINSTS Position */
#define SC_STATUS_CDPINSTS_Msk (0x1ul << SC_STATUS_CDPINSTS_Pos) /*!< SC_T::STATUS: CDPINSTS Mask */
#define SC_STATUS_RXPOINT_Pos (16) /*!< SC_T::STATUS: RXPOINT Position */
#define SC_STATUS_RXPOINT_Msk (0x7ul << SC_STATUS_RXPOINT_Pos) /*!< SC_T::STATUS: RXPOINT Mask */
#define SC_STATUS_RXRERR_Pos (21) /*!< SC_T::STATUS: RXRERR Position */
#define SC_STATUS_RXRERR_Msk (0x1ul << SC_STATUS_RXRERR_Pos) /*!< SC_T::STATUS: RXRERR Mask */
#define SC_STATUS_RXOVERR_Pos (22) /*!< SC_T::STATUS: RXOVERR Position */
#define SC_STATUS_RXOVERR_Msk (0x1ul << SC_STATUS_RXOVERR_Pos) /*!< SC_T::STATUS: RXOVERR Mask */
#define SC_STATUS_RXACT_Pos (23) /*!< SC_T::STATUS: RXACT Position */
#define SC_STATUS_RXACT_Msk (0x1ul << SC_STATUS_RXACT_Pos) /*!< SC_T::STATUS: RXACT Mask */
#define SC_STATUS_TXPOINT_Pos (24) /*!< SC_T::STATUS: TXPOINT Position */
#define SC_STATUS_TXPOINT_Msk (0x7ul << SC_STATUS_TXPOINT_Pos) /*!< SC_T::STATUS: TXPOINT Mask */
#define SC_STATUS_TXRERR_Pos (29) /*!< SC_T::STATUS: TXRERR Position */
#define SC_STATUS_TXRERR_Msk (0x1ul << SC_STATUS_TXRERR_Pos) /*!< SC_T::STATUS: TXRERR Mask */
#define SC_STATUS_TXOVERR_Pos (30) /*!< SC_T::STATUS: TXOVERR Position */
#define SC_STATUS_TXOVERR_Msk (0x1ul << SC_STATUS_TXOVERR_Pos) /*!< SC_T::STATUS: TXOVERR Mask */
#define SC_STATUS_TXACT_Pos (31) /*!< SC_T::STATUS: TXACT Position */
#define SC_STATUS_TXACT_Msk (0x1ul << SC_STATUS_TXACT_Pos) /*!< SC_T::STATUS: TXACT Mask */
#define SC_PINCTL_PWREN_Pos (0) /*!< SC_T::PINCTL: PWREN Position */
#define SC_PINCTL_PWREN_Msk (0x1ul << SC_PINCTL_PWREN_Pos) /*!< SC_T::PINCTL: PWREN Mask */
#define SC_PINCTL_RSTEN_Pos (1) /*!< SC_T::PINCTL: RSTEN Position */
#define SC_PINCTL_RSTEN_Msk (0x1ul << SC_PINCTL_RSTEN_Pos) /*!< SC_T::PINCTL: RSTEN Mask */
#define SC_PINCTL_CLKKEEP_Pos (6) /*!< SC_T::PINCTL: CLKKEEP Position */
#define SC_PINCTL_CLKKEEP_Msk (0x1ul << SC_PINCTL_CLKKEEP_Pos) /*!< SC_T::PINCTL: CLKKEEP Mask */
#define SC_PINCTL_SCDATA_Pos (9) /*!< SC_T::PINCTL: SCDATA Position */
#define SC_PINCTL_SCDATA_Msk (0x1ul << SC_PINCTL_SCDATA_Pos) /*!< SC_T::PINCTL: SCDATA Mask */
#define SC_PINCTL_PWRINV_Pos (11) /*!< SC_T::PINCTL: PWRINV Position */
#define SC_PINCTL_PWRINV_Msk (0x1ul << SC_PINCTL_PWRINV_Pos) /*!< SC_T::PINCTL: PWRINV Mask */
#define SC_PINCTL_DATASTS_Pos (16) /*!< SC_T::PINCTL: DATASTS Position */
#define SC_PINCTL_DATASTS_Msk (0x1ul << SC_PINCTL_DATASTS_Pos) /*!< SC_T::PINCTL: DATASTS Mask */
#define SC_PINCTL_PWRSTS_Pos (17) /*!< SC_T::PINCTL: PWRSTS Position */
#define SC_PINCTL_PWRSTS_Msk (0x1ul << SC_PINCTL_PWRSTS_Pos) /*!< SC_T::PINCTL: PWRSTS Mask */
#define SC_PINCTL_RSTSTS_Pos (18) /*!< SC_T::PINCTL: RSTSTS Position */
#define SC_PINCTL_RSTSTS_Msk (0x1ul << SC_PINCTL_RSTSTS_Pos) /*!< SC_T::PINCTL: RSTSTS Mask */
#define SC_PINCTL_SYNC_Pos (30) /*!< SC_T::PINCTL: SYNC Position */
#define SC_PINCTL_SYNC_Msk (0x1ul << SC_PINCTL_SYNC_Pos) /*!< SC_T::PINCTL: SYNC Mask */
#define SC_TMRCTL0_CNT_Pos (0) /*!< SC_T::TMRCTL0: CNT Position */
#define SC_TMRCTL0_CNT_Msk (0xfffffful << SC_TMRCTL0_CNT_Pos) /*!< SC_T::TMRCTL0: CNT Mask */
#define SC_TMRCTL0_OPMODE_Pos (24) /*!< SC_T::TMRCTL0: OPMODE Position */
#define SC_TMRCTL0_OPMODE_Msk (0xful << SC_TMRCTL0_OPMODE_Pos) /*!< SC_T::TMRCTL0: OPMODE Mask */
#define SC_TMRCTL0_SYNC_Pos (31) /*!< SC_T::TMRCTL0: SYNC Position */
#define SC_TMRCTL0_SYNC_Msk (0x1ul << SC_TMRCTL0_SYNC_Pos) /*!< SC_T::TMRCTL0: SYNC Mask */
#define SC_TMRCTL1_CNT_Pos (0) /*!< SC_T::TMRCTL1: CNT Position */
#define SC_TMRCTL1_CNT_Msk (0xfful << SC_TMRCTL1_CNT_Pos) /*!< SC_T::TMRCTL1: CNT Mask */
#define SC_TMRCTL1_OPMODE_Pos (24) /*!< SC_T::TMRCTL1: OPMODE Position */
#define SC_TMRCTL1_OPMODE_Msk (0xful << SC_TMRCTL1_OPMODE_Pos) /*!< SC_T::TMRCTL1: OPMODE Mask */
#define SC_TMRCTL1_SYNC_Pos (31) /*!< SC_T::TMRCTL1: SYNC Position */
#define SC_TMRCTL1_SYNC_Msk (0x1ul << SC_TMRCTL1_SYNC_Pos) /*!< SC_T::TMRCTL1: SYNC Mask */
#define SC_TMRCTL2_CNT_Pos (0) /*!< SC_T::TMRCTL2: CNT Position */
#define SC_TMRCTL2_CNT_Msk (0xfful << SC_TMRCTL2_CNT_Pos) /*!< SC_T::TMRCTL2: CNT Mask */
#define SC_TMRCTL2_OPMODE_Pos (24) /*!< SC_T::TMRCTL2: OPMODE Position */
#define SC_TMRCTL2_OPMODE_Msk (0xful << SC_TMRCTL2_OPMODE_Pos) /*!< SC_T::TMRCTL2: OPMODE Mask */
#define SC_TMRCTL2_SYNC_Pos (31) /*!< SC_T::TMRCTL2: SYNC Position */
#define SC_TMRCTL2_SYNC_Msk (0x1ul << SC_TMRCTL2_SYNC_Pos) /*!< SC_T::TMRCTL2: SYNC Mask */
#define SC_UARTCTL_UARTEN_Pos (0) /*!< SC_T::UARTCTL: UARTEN Position */
#define SC_UARTCTL_UARTEN_Msk (0x1ul << SC_UARTCTL_UARTEN_Pos) /*!< SC_T::UARTCTL: UARTEN Mask */
#define SC_UARTCTL_WLS_Pos (4) /*!< SC_T::UARTCTL: WLS Position */
#define SC_UARTCTL_WLS_Msk (0x3ul << SC_UARTCTL_WLS_Pos) /*!< SC_T::UARTCTL: WLS Mask */
#define SC_UARTCTL_PBOFF_Pos (6) /*!< SC_T::UARTCTL: PBOFF Position */
#define SC_UARTCTL_PBOFF_Msk (0x1ul << SC_UARTCTL_PBOFF_Pos) /*!< SC_T::UARTCTL: PBOFF Mask */
#define SC_UARTCTL_OPE_Pos (7) /*!< SC_T::UARTCTL: OPE Position */
#define SC_UARTCTL_OPE_Msk (0x1ul << SC_UARTCTL_OPE_Pos) /*!< SC_T::UARTCTL: OPE Mask */
#define SC_ACTCTL_T1EXT_Pos (0) /*!< SC_T::ACTCTL: T1EXT Position */
#define SC_ACTCTL_T1EXT_Msk (0x1ful << SC_ACTCTL_T1EXT_Pos) /*!< SC_T::ACTCTL: T1EXT Mask */
/**@}*/ /* SC_CONST */
/**@}*/ /* end of SC register group */
/*---------------------- I2S Interface Controller -------------------------*/
/**
@addtogroup I2S I2S Interface Controller(I2S)
Memory Mapped Structure for I2S Controller
@{ */
typedef struct {
/**
* @var I2S_T::CTL0
* Offset: 0x00 I2S Control Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |I2SEN |I2S Controller Enable Control
* | | |0 = I2S controller Disabled.
* | | |1 = I2S controller Enabled.
* |[1] |TXEN |Transmit Enable Control
* | | |0 = Data transmission Disabled.
* | | |1 = Data transmission Enabled.
* |[2] |RXEN |Receive Enable Control
* | | |0 = Data receiving Disabled.
* | | |1 = Data receiving Enabled.
* |[3] |MUTE |Transmit Mute Enable Control
* | | |0 = Transmit data is shifted from buffer.
* | | |1 = Send zero on transmit channel.
* |[5:4] |DATWIDTH |Data Width
* | | |This bit field is used to define the bit-width of data word in each audio channel
* | | |00 = The bit-width of data word is 8-bit.
* | | |01 = The bit-width of data word is 16-bit.
* | | |10 = The bit-width of data word is 24-bit.
* | | |11 = The bit-width of data word is 32-bit.
* |[6] |MONO |Monaural Data Control
* | | |0 = Data is stereo format.
* | | |1 = Data is monaural format.
* | | |Note: when chip records data, RXLCH (I2S_CTL0[23]) indicates which channel data will be saved if monaural format is selected.
* |[7] |ORDER |Stereo Data Order in FIFO
* | | |In 8-bit/16-bit data width, this bit is used to select whether the even or odd channel data is stored in higher byte
* | | |In 24-bit data width, this is used to select the left/right alignment method of audio data which is stored in data memory consisted of 32-bit FIFO entries.
* | | |0 = Even channel data at high byte in 8-bit/16-bit data width.
* | | |LSB of 24-bit audio data in each channel is aligned to right side in 32-bit FIFO entries.
* | | |1 = Even channel data at low byte.
* | | | MSB of 24-bit audio data in each channel is aligned to left side in 32-bit FIFO entries.
* |[8] |SLAVE |Slave Mode Enable Control
* | | |0 = Master mode.
* | | |1 = Slave mode.
* | | |Note: I2S can operate as master or slave
* | | |For Master mode, I2S_BCLK and I2S_LRCLK pins are output mode and send out bit clock to Audio CODEC chip
* | | |In Slave mode, I2S_BCLK and I2S_LRCLK pins are input mode and I2S_BCLK and I2S_LRCLK signals are received from outer Audio CODEC chip.
* |[15] |MCLKEN |Master Clock Enable Control
* | | |If MCLKEN is set to 1, I2S controller will generate master clock on I2S_MCLK pin for external audio devices.
* | | |0 = Master clock Disabled.
* | | |1 = Master clock Enabled.
* |[18] |TXFBCLR |Transmit FIFO Buffer Clear
* | | |0 = No Effect.
* | | |1 = Clear TX FIFO.
* | | |Note1: Write 1 to clear transmit FIFO, internal pointer is reset to FIFO start point, and TXCNT (I2S_STATUS1[12:8]) returns 0 and transmit FIFO becomes empty but data in transmit FIFO is not changed.
* | | |Note2: This bit is clear by hardware automatically, read it return zero.
* |[19] |RXFBCLR |Receive FIFO Buffer Clear
* | | |0 = No Effect.
* | | |1 = Clear RX FIFO.
* | | |Note1: Write 1 to clear receive FIFO, internal pointer is reset to FIFO start point, and RXCNT (I2S_STATUS1[20:16]) returns 0 and receive FIFO becomes empty.
* | | |Note2: This bit is cleared by hardware automatically, read it return zero.
* |[20] |TXPDMAEN |Transmit PDMA Enable Control
* | | |0 = Transmit PDMA function Disabled.
* | | |1 = Transmit PDMA function Enabled.
* |[21] |RXPDMAEN |Receive PDMA Enable Control
* | | |0 = Receiver PDMA function Disabled.
* | | |1 = Receiver PDMA function Enabled.
* |[23] |RXLCH |Receive Left Channel Enable Control
* | | |When monaural format is selected (MONO = 1), I2S will receive channel1 data if RXLCH is set to 0, and receive channel0 data if RXLCH is set to 1.
* | | |0 = Receives channel1 data in MONO mode.
* | | |1 = Receives channel0 data in MONO mode.
* |[26:24] |FORMAT |Data Format Selection
* | | |000 = I2S standard data format.
* | | |001 = I2S with MSB justified.
* | | |010 = I2S with LSB justified.
* | | |011 = Reserved.
* | | |100 = PCM standard data format.
* | | |101 = PCM with MSB justified.
* | | |110 = PCM with LSB justified.
* | | |111 = Reserved.
* |[27] |PCMSYNC |PCM Synchronization Pulse Length Selection
* | | |This bit field is used to select the high pulse length of frame synchronization signal in PCM protocol
* | | |0 = One BCLK period.
* | | |1 = One channel period.
* | | |Note: This bit is only available in master mode
* |[29:28] |CHWIDTH |Channel Width
* | | |This bit fields are used to define the length of audio channel
* | | |If CHWIDTH < DATWIDTH, the hardware will set the real channel length as the bit-width of audio data which is defined by DATWIDTH.
* | | |00 = The bit-width of each audio channel is 8-bit.
* | | |01 = The bit-width of each audio channel is 16-bit.
* | | |10 = The bit-width of each audio channel is 24-bit.
* | | |11 = The bit-width of each audio channel is 32-bit.
* |[31:30] |TDMCHNUM |TDM Channel Number
* | | |This bit fields are used to define the TDM channel number in one audio frame while PCM mode (FORMAT[2] = 1).
* | | |00 = 2 channels in audio frame.
* | | |01 = 4 channels in audio frame.
* | | |10 = 6 channels in audio frame.
* | | |11 = 8 channels in audio frame.
* @var I2S_T::CLKDIV
* Offset: 0x04 I2S Clock Divider Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[5:0] |MCLKDIV |Master Clock Divider
* | | |If chip external crystal frequency is (2xMCLKDIV)*256fs then software can program these bits to generate 256fs clock frequency to audio codec chip
* | | |If MCLKDIV is set to 0, MCLK is the same as external clock input.
* | | |For example, sampling rate is 24 kHz and chip external crystal clock is 12.288 MHz, set MCLKDIV = 1.
* | | |F_MCLK = F_I2SCLK/(2x(MCLKDIV)) (When MCLKDIV is >= 1 ).
* | | |F_MCLK = F_I2SCLK (When MCLKDIV is set to 0 ).
* | | |Note: F_MCLK is the frequency of MCLK, and F_I2SCLK is the frequency of the I2S_CLK
* |[16:8] |BCLKDIV |Bit Clock Divider
* | | |The I2S controller will generate bit clock in Master mode
* | | |Software can program these bit fields to generate sampling rate clock frequency.
* | | |F_BCLK= F_I2SCLK / (2*(BCLKDIV + 1)).
* | | |Note: F_BCLK is the frequency of BCLK and F_I2SCLK is the frequency of I2S_CLK
* @var I2S_T::IEN
* Offset: 0x08 I2S Interrupt Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |RXUDFIEN |Receive FIFO Underflow Interrupt Enable Control
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* | | |Note: If software reads receive FIFO when it is empty then RXUDIF (I2S_STATUS0[8]) flag is set to 1.
* |[1] |RXOVFIEN |Receive FIFO Overflow Interrupt Enable Control
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* | | |Note: Interrupt occurs if this bit is set to 1 and RXOVIF (I2S_STATUS0[9]) flag is set to 1
* |[2] |RXTHIEN |Receive FIFO Threshold Level Interrupt Enable Control
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* | | |Note: When data word in receive FIFO is equal or higher than RXTH (I2S_CTL1[19:16]) and the RXTHIF (I2S_STATUS0[10]) bit is set to 1
* | | |If RXTHIEN bit is enabled, interrupt occur.
* |[8] |TXUDFIEN |Transmit FIFO Underflow Interrupt Enable Control
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* | | |Note: Interrupt occur if this bit is set to 1 and TXUDIF (I2S_STATUS0[16]) flag is set to 1.
* |[9] |TXOVFIEN |Transmit FIFO Overflow Interrupt Enable Control
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* | | |Note: Interrupt occurs if this bit is set to 1 and TXOVIF (I2S_STATUS0[17]) flag is set to 1
* |[10] |TXTHIEN |Transmit FIFO Threshold Level Interrupt Enable Control
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* | | |Note: Interrupt occurs if this bit is set to 1 and data words in transmit FIFO is less than TXTH (I2S_CTL1[11:8]).
* |[16] |CH0ZCIEN |Channel0 Zero-cross Interrupt Enable Control
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* | | |Note1: Interrupt occurs if this bit is set to 1 and channel0 zero-cross
* | | |Note2: Channel0 also means left audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode.
* |[17] |CH1ZCIEN |Channel1 Zero-cross Interrupt Enable Control
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* | | |Note1: Interrupt occurs if this bit is set to 1 and channel1 zero-cross
* | | |Note2: Channel1 also means right audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode.
* |[18] |CH2ZCIEN |Channel2 Zero-cross Interrupt Enable Control
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* | | |Note1: Interrupt occurs if this bit is set to 1 and channel2 zero-cross
* | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
* |[19] |CH3ZCIEN |Channel3 Zero-cross Interrupt Enable Control
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* | | |Note1: Interrupt occurs if this bit is set to 1 and channel3 zero-cross
* | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
* |[20] |CH4ZCIEN |Channel4 Zero-cross Interrupt Enable Control
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* | | |Note1: Interrupt occurs if this bit is set to 1 and channel4 zero-cross
* | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
* |[21] |CH5ZCIEN |Channel5 Zero-cross Interrupt Enable Control
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* | | |Note1: Interrupt occurs if this bit is set to 1 and channel5 zero-cross
* | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
* |[22] |CH6ZCIEN |Channel6 Zero-cross Interrupt Enable Control
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* | | |Note1: Interrupt occurs if this bit is set to 1 and channel6 zero-cross
* | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
* |[23] |CH7ZCIEN |Channel7 Zero-cross Interrupt Enable Control
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* | | |Note1: Interrupt occurs if this bit is set to 1 and channel7 zero-cross
* | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
* @var I2S_T::STATUS0
* Offset: 0x0C I2S Status Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |I2SINT |I2S Interrupt Flag (Read Only)
* | | |0 = No I2S interrupt.
* | | |1 = I2S interrupt.
* | | |Note: It is wire-OR of I2STXINT and I2SRXINT bits.
* |[1] |I2SRXINT |I2S Receive Interrupt (Read Only)
* | | |0 = No receive interrupt.
* | | |1 = Receive interrupt.
* |[2] |I2STXINT |I2S Transmit Interrupt (Read Only)
* | | |0 = No transmit interrupt.
* | | |1 = Transmit interrupt.
* |[5:3] |DATACH |Transmission Data Channel (Read Only)
* | | |This bit fields are used to indicate which audio channel is current transmit data belong.
* | | |000 = channel0 (means left channel while 2-channel I2S/PCM mode).
* | | |001 = channel1 (means right channel while 2-channel I2S/PCM mode).
* | | |010 = channel2 (available while 4-channel TDM PCM mode).
* | | |011 = channel3 (available while 4-channel TDM PCM mode).
* | | |100 = channel4 (available while 6-channel TDM PCM mode).
* | | |101 = channel5 (available while 6-channel TDM PCM mode).
* | | |110 = channel6 (available while 8-channel TDM PCM mode).
* | | |111 = channel7 (available while 8-channel TDM PCM mode).
* |[8] |RXUDIF |Receive FIFO Underflow Interrupt Flag
* | | |0 = No underflow occur.
* | | |1 = Underflow occur.
* | | |Note1: When receive FIFO is empty, and software reads the receive FIFO again
* | | |This bit will be set to 1, and it indicates underflow situation occurs.
* | | |Note2: Write 1 to clear this bit to zero
* |[9] |RXOVIF |Receive FIFO Overflow Interrupt Flag
* | | |0 = No overflow occur.
* | | |1 = Overflow occur.
* | | |Note1: When receive FIFO is full and receive hardware attempt to write data into receive FIFO then this bit is set to 1, data in 1st buffer is overwrote.
* | | |Note2: Write 1 to clear this bit to 0.
* |[10] |RXTHIF |Receive FIFO Threshold Interrupt Flag (Read Only)
* | | |0 = Data word(s) in FIFO is not higher than threshold level.
* | | |1 = Data word(s) in FIFO is higher than threshold level.
* | | |Note: When data word(s) in receive FIFO is higher than threshold value set in RXTH (I2S_CTL1[19:16]) the RXTHIF bit becomes to 1
* | | |It keeps at 1 till RXCNT (I2S_STATUS1[20:16]) is not higher than RXTH (I2S_CTL1[19:16]) after software read RXFIFO register.
* |[11] |RXFULL |Receive FIFO Full (Read Only)
* | | |0 = Not full.
* | | |1 = Full.
* | | |Note: This bit reflects data words number in receive FIFO is 16.
* |[12] |RXEMPTY |Receive FIFO Empty (Read Only)
* | | |0 = Not empty.
* | | |1 = Empty.
* | | |Note: This bit reflects data words number in receive FIFO is zero
* |[16] |TXUDIF |Transmit FIFO Underflow Interrupt Flag
* | | |0 = No underflow.
* | | |1 = Underflow.
* | | |Note1: This bit will be set to 1 when shift logic hardware read data from transmitting FIFO and the filling data level in transmitting FIFO is not enough for one audio frame.
* | | |Note2: Write 1 to clear this bit to 0.
* |[17] |TXOVIF |Transmit FIFO Overflow Interrupt Flag
* | | |0 = No overflow.
* | | |1 = Overflow.
* | | |Note1: Write data to transmit FIFO when it is full and this bit set to 1
* | | |Note2: Write 1 to clear this bit to 0.
* |[18] |TXTHIF |Transmit FIFO Threshold Interrupt Flag (Read Only)
* | | |0 = Data word(s) in FIFO is higher than threshold level.
* | | |1 = Data word(s) in FIFO is equal or lower than threshold level.
* | | |Note: When data word(s) in transmit FIFO is equal or lower than threshold value set in TXTH (I2S_CTL1[11:8]) the TXTHIF bit becomes to 1
* | | |It keeps at 1 till TXCNT (I2S_STATUS1[12:8]) is higher than TXTH (I2S_CTL1[11:8]) after software write TXFIFO register.
* |[19] |TXFULL |Transmit FIFO Full (Read Only)
* | | |This bit reflect data word number in transmit FIFO is 16
* | | |0 = Not full.
* | | |1 = Full.
* |[20] |TXEMPTY |Transmit FIFO Empty (Read Only)
* | | |This bit reflect data word number in transmit FIFO is zero
* | | |0 = Not empty.
* | | |1 = Empty.
* |[21] |TXBUSY |Transmit Busy (Read Only)
* | | |0 = Transmit shift buffer is empty.
* | | |1 = Transmit shift buffer is busy.
* | | |Note: This bit is cleared to 0 when all data in transmit FIFO and shift buffer is shifted out
* | | |And set to 1 when 1st data is load to shift buffer
* @var I2S_T::TXFIFO
* Offset: 0x10 I2S Transmit FIFO Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |TXFIFO |Transmit FIFO Bits
* | | |I2S contains 16 words (16x32 bit) data buffer for data transmit
* | | |Write data to this register to prepare data for transmit
* | | |The remaining word number is indicated by TXCNT (I2S_STATUS1[12:8]).
* @var I2S_T::RXFIFO
* Offset: 0x14 I2S Receive FIFO Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |RXFIFO |Receive FIFO Bits
* | | |I2S contains 16 words (16x32 bit) data buffer for data receive
* | | |Read this register to get data in FIFO
* | | |The remaining data word number is indicated by RXCNT (I2S_STATUS1[20:16]).
* @var I2S_T::CTL1
* Offset: 0x20 I2S Control Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CH0ZCEN |Channel0 Zero-cross Detection Enable Control
* | | |0 = channel0 zero-cross detect Disabled.
* | | |1 = channel0 zero-cross detect Enabled.
* | | |Note1: Channel0 also means left audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode.
* | | |Note2: If this bit is set to 1, when channel0 data sign bit change or next shift data bits are all zero then CH0ZCIF(I2S_STATUS1[0]) flag is set to 1.
* | | |Note3: If CH0ZCIF Flag is set to 1, the channel0 will be mute.
* |[1] |CH1ZCEN |Channel1 Zero-cross Detect Enable Control
* | | |0 = channel1 zero-cross detect Disabled.
* | | |1 = channel1 zero-cross detect Enabled.
* | | |Note1: Channel1 also means right audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode.
* | | |Note2: If this bit is set to 1, when channel1 data sign bit change or next shift data bits are all zero then CH1ZCIF(I2S_STATUS1[1]) flag is set to 1.
* | | |Note3: If CH1ZCIF Flag is set to 1, the channel1 will be mute.
* |[2] |CH2ZCEN |Channel2 Zero-cross Detect Enable Control
* | | |0 = channel2 zero-cross detect Disabled.
* | | |1 = channel2 zero-cross detect Enabled.
* | | |Note1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
* | | |Note2: If this bit is set to 1, when channel2 data sign bit change or next shift data bits are all zero then CH2ZCIF(I2S_STATUS1[2]) flag is set to 1.
* | | |Note3: If CH2ZCIF Flag is set to 1, the channel2 will be mute.
* |[3] |CH3ZCEN |Channel3 Zero-cross Detect Enable Control
* | | |0 = channel3 zero-cross detect Disabled.
* | | |1 = channel3 zero-cross detect Enabled.
* | | |Note1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
* | | |Note2: If this bit is set to 1, when channel3 data sign bit change or next shift data bits are all zero then CH3ZCIF(I2S_STATUS1[3]) flag is set to 1.
* | | |Note3: If CH3ZCIF Flag is set to 1, the channel3 will be mute.
* |[4] |CH4ZCEN |Channel4 Zero-cross Detect Enable Control
* | | |0 = channel4 zero-cross detect Disabled.
* | | |1 = channel4 zero-cross detect Enabled.
* | | |Note1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
* | | |Note2: If this bit is set to 1, when channel4 data sign bit change or next shift data bits are all zero then CH4ZCIF(I2S_STATUS1[4]) flag is set to 1.
* | | |Note3: If CH4ZCIF Flag is set to 1, the channel4 will be mute.
* |[5] |CH5ZCEN |Channel5 Zero-cross Detect Enable Control
* | | |0 = channel5 zero-cross detect Disabled.
* | | |1 = channel5 zero-cross detect Enabled.
* | | |Note1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
* | | |Note2: If this bit is set to 1, when channel5 data sign bit change or next shift data bits are all zero then CH5ZCIF(I2S_STATUS1[5]) flag is set to 1.
* | | |Note3: If CH5ZCIF Flag is set to 1, the channel5 will be mute.
* |[6] |CH6ZCEN |Channel6 Zero-cross Detect Enable Control
* | | |0 = channel6 zero-cross detect Disabled.
* | | |1 = channel6 zero-cross detect Enabled.
* | | |Note1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
* | | |Note2: If this bit is set to 1, when channel6 data sign bit change or next shift data bits are all zero then CH6ZCIF(I2S_STATUS1[6]) flag is set to 1.
* | | |Note3: If CH6ZCIF Flag is set to 1, the channel6 will be mute.
* |[7] |CH7ZCEN |Channel7 Zero-cross Detect Enable Control
* | | |0 = channel7 zero-cross detect Disabled.
* | | |1 = channel7 zero-cross detect Enabled.
* | | |Note1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
* | | |Note2: If this bit is set to 1, when channel7 data sign bit change or next shift data bits are all zero then CH7ZCIF (I2S_STATUS1[7]) flag is set to 1.
* | | |Note3: If CH7ZCIF Flag is set to 1, the channel7 will be mute.
* |[11:8] |TXTH |Transmit FIFO Threshold Level
* | | |0000 = 0 data word in transmit FIFO.
* | | |0001 = 1 data word in transmit FIFO.
* | | |0010 = 2 data words in transmit FIFO.
* | | |...
* | | |1110 = 14 data words in transmit FIFO.
* | | |1111 = 15 data words in transmit FIFO.
* | | |Note: If remain data word number in transmit FIFO is the same or less than threshold level then TXTHIF (I2S_STATUS0[18]) flag is set.
* |[19:16] |RXTH |Receive FIFO Threshold Level
* | | |0000 = 1 data word in receive FIFO.
* | | |0001 = 2 data words in receive FIFO.
* | | |0010 = 3 data words in receive FIFO.
* | | |...
* | | |1110 = 15 data words in receive FIFO.
* | | |1111 = 16 data words in receive FIFO.
* | | |Note: When received data word number in receive buffer is greater than threshold level then RXTHIF (I2S_STATUS0[10]) flag is set.
* |[24] |PBWIDTH |Peripheral Bus Data Width Selection
* | | |This bit is used to choice the available data width of APB bus
* | | |It must be set to 1 while PDMA function is enable and it is set to 16-bit transmission mode
* | | |0 = 32 bits data width.
* | | |1 = 16 bits data width.
* | | |Note1: If PBWIDTH=1, the low 16 bits of 32-bit data bus are available.
* | | |Note2: If PBWIDTH=1, the transmitting FIFO level will be increased after two FIFO write operations.
* | | |Note3: If PBWIDTH=1, the receiving FIFO level will be decreased after two FIFO read operations.
* |[25] |PB16ORD |FIFO Read/Write Order in 16-bit Width of Peripheral Bus
* | | |When PBWIDTH = 1, the data FIFO will be increased or decreased by two peripheral bus access
* | | |This bit is used to select the order of FIFO access operations to meet the 32-bit transmitting/receiving FIFO entries.
* | | |0 = Low 16-bit read/write access first.
* | | |1 = High 16-bit read/write access first.
* | | |Note: This bit is available while PBWIDTH = 1.
* @var I2S_T::STATUS1
* Offset: 0x24 I2S Status Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CH0ZCIF |Channel0 Zero-cross Interrupt Flag
* | | |It indicates channel0 next sample data sign bit is changed or all data bits are zero.
* | | |0 = No zero-cross in channel0.
* | | |1 = Channel0 zero-cross is detected.
* | | |Note1: Write 1 to clear this bit to 0.
* | | |Note2: Channel0 also means left audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode.
* |[1] |CH1ZCIF |Channel1 Zero-cross Interrupt Flag
* | | |It indicates channel1 next sample data sign bit is changed or all data bits are zero.
* | | |0 = No zero-cross in channel1.
* | | |1 = Channel1 zero-cross is detected.
* | | |Note1: Write 1 to clear this bit to 0.
* | | |Note2: Channel1 also means right audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode.
* |[2] |CH2ZCIF |Channel2 Zero-cross Interrupt Flag
* | | |It indicates channel2 next sample data sign bit is changed or all data bits are zero.
* | | |0 = No zero-cross in channel2.
* | | |1 = Channel2 zero-cross is detected.
* | | |Note1: Write 1 to clear this bit to 0.
* | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
* |[3] |CH3ZCIF |Channel3 Zero-cross Interrupt Flag
* | | |It indicates channel3 next sample data sign bit is changed or all data bits are zero.
* | | |0 = No zero-cross in channel3.
* | | |1 = Channel3 zero-cross is detected.
* | | |Note1: Write 1 to clear this bit to 0.
* | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
* |[4] |CH4ZCIF |Channel4 Zero-cross Interrupt Flag
* | | |It indicates channel4 next sample data sign bit is changed or all data bits are zero.
* | | |0 = No zero-cross in channel4.
* | | |1 = Channel4 zero-cross is detected.
* | | |Note1: Write 1 to clear this bit to 0.
* | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
* |[5] |CH5ZCIF |Channel5 Zero-cross Interrupt Flag
* | | |It indicates channel5 next sample data sign bit is changed or all data bits are zero.
* | | |0 = No zero-cross in channel5.
* | | |1 = Channel5 zero-cross is detected.
* | | |Note1: Write 1 to clear this bit to 0.
* | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
* |[6] |CH6ZCIF |Channel6 Zero-cross Interrupt Flag
* | | |It indicates channel6 next sample data sign bit is changed or all data bits are zero.
* | | |0 = No zero-cross in channel6.
* | | |1 = Channel6 zero-cross is detected.
* | | |Note1: Write 1 to clear this bit to 0.
* | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
* |[7] |CH7ZCIF |Channel7 Zero-cross Interrupt Flag
* | | |It indicates channel7 next sample data sign bit is changed or all data bits are zero.
* | | |0 = No zero-cross in channel7.
* | | |1 = Channel7 zero-cross is detected.
* | | |Note1: Write 1 to clear this bit to 0.
* | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
* |[12:8] |TXCNT |Transmit FIFO Level (Read Only)
* | | |These bits indicate the number of available entries in transmit FIFO
* | | |00000 = No data.
* | | |00001 = 1 word in transmit FIFO.
* | | |00010 = 2 words in transmit FIFO.
* | | |...
* | | |01110 = 14 words in transmit FIFO.
* | | |01111 = 15 words in transmit FIFO.
* | | |10000 = 16 words in transmit FIFO.
* | | |Others are reserved.
* |[20:16] |RXCNT |Receive FIFO Level (Read Only)
* | | |These bits indicate the number of available entries in receive FIFO
* | | |00000 = No data.
* | | |00001 = 1 word in receive FIFO.
* | | |00010 = 2 words in receive FIFO.
* | | |...
* | | |01110 = 14 words in receive FIFO.
* | | |01111 = 15 words in receive FIFO.
* | | |10000 = 16 words in receive FIFO.
* | | |Others are reserved.
*/
__IO uint32_t CTL0; /*!< [0x0000] I2S Control Register 0 */
__IO uint32_t CLKDIV; /*!< [0x0004] I2S Clock Divider Register */
__IO uint32_t IEN; /*!< [0x0008] I2S Interrupt Enable Register */
__IO uint32_t STATUS0; /*!< [0x000c] I2S Status Register 0 */
__O uint32_t TXFIFO; /*!< [0x0010] I2S Transmit FIFO Register */
__I uint32_t RXFIFO; /*!< [0x0014] I2S Receive FIFO Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE0[2];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t CTL1; /*!< [0x0020] I2S Control Register 1 */
__IO uint32_t STATUS1; /*!< [0x0024] I2S Status Register 1 */
} I2S_T;
/**
@addtogroup I2S_CONST I2S Bit Field Definition
Constant Definitions for I2S Controller
@{ */
#define I2S_CTL0_I2SEN_Pos (0) /*!< I2S_T::CTL0: I2SEN Position */
#define I2S_CTL0_I2SEN_Msk (0x1ul << I2S_CTL0_I2SEN_Pos) /*!< I2S_T::CTL0: I2SEN Mask */
#define I2S_CTL0_TXEN_Pos (1) /*!< I2S_T::CTL0: TXEN Position */
#define I2S_CTL0_TXEN_Msk (0x1ul << I2S_CTL0_TXEN_Pos) /*!< I2S_T::CTL0: TXEN Mask */
#define I2S_CTL0_RXEN_Pos (2) /*!< I2S_T::CTL0: RXEN Position */
#define I2S_CTL0_RXEN_Msk (0x1ul << I2S_CTL0_RXEN_Pos) /*!< I2S_T::CTL0: RXEN Mask */
#define I2S_CTL0_MUTE_Pos (3) /*!< I2S_T::CTL0: MUTE Position */
#define I2S_CTL0_MUTE_Msk (0x1ul << I2S_CTL0_MUTE_Pos) /*!< I2S_T::CTL0: MUTE Mask */
#define I2S_CTL0_DATWIDTH_Pos (4) /*!< I2S_T::CTL0: DATWIDTH Position */
#define I2S_CTL0_DATWIDTH_Msk (0x3ul << I2S_CTL0_DATWIDTH_Pos) /*!< I2S_T::CTL0: DATWIDTH Mask */
#define I2S_CTL0_MONO_Pos (6) /*!< I2S_T::CTL0: MONO Position */
#define I2S_CTL0_MONO_Msk (0x1ul << I2S_CTL0_MONO_Pos) /*!< I2S_T::CTL0: MONO Mask */
#define I2S_CTL0_ORDER_Pos (7) /*!< I2S_T::CTL0: ORDER Position */
#define I2S_CTL0_ORDER_Msk (0x1ul << I2S_CTL0_ORDER_Pos) /*!< I2S_T::CTL0: ORDER Mask */
#define I2S_CTL0_SLAVE_Pos (8) /*!< I2S_T::CTL0: SLAVE Position */
#define I2S_CTL0_SLAVE_Msk (0x1ul << I2S_CTL0_SLAVE_Pos) /*!< I2S_T::CTL0: SLAVE Mask */
#define I2S_CTL0_MCLKEN_Pos (15) /*!< I2S_T::CTL0: MCLKEN Position */
#define I2S_CTL0_MCLKEN_Msk (0x1ul << I2S_CTL0_MCLKEN_Pos) /*!< I2S_T::CTL0: MCLKEN Mask */
#define I2S_CTL0_TXFBCLR_Pos (18) /*!< I2S_T::CTL0: TXFBCLR Position */
#define I2S_CTL0_TXFBCLR_Msk (0x1ul << I2S_CTL0_TXFBCLR_Pos) /*!< I2S_T::CTL0: TXFBCLR Mask */
#define I2S_CTL0_RXFBCLR_Pos (19) /*!< I2S_T::CTL0: RXFBCLR Position */
#define I2S_CTL0_RXFBCLR_Msk (0x1ul << I2S_CTL0_RXFBCLR_Pos) /*!< I2S_T::CTL0: RXFBCLR Mask */
#define I2S_CTL0_TXPDMAEN_Pos (20) /*!< I2S_T::CTL0: TXPDMAEN Position */
#define I2S_CTL0_TXPDMAEN_Msk (0x1ul << I2S_CTL0_TXPDMAEN_Pos) /*!< I2S_T::CTL0: TXPDMAEN Mask */
#define I2S_CTL0_RXPDMAEN_Pos (21) /*!< I2S_T::CTL0: RXPDMAEN Position */
#define I2S_CTL0_RXPDMAEN_Msk (0x1ul << I2S_CTL0_RXPDMAEN_Pos) /*!< I2S_T::CTL0: RXPDMAEN Mask */
#define I2S_CTL0_RXLCH_Pos (23) /*!< I2S_T::CTL0: RXLCH Position */
#define I2S_CTL0_RXLCH_Msk (0x1ul << I2S_CTL0_RXLCH_Pos) /*!< I2S_T::CTL0: RXLCH Mask */
#define I2S_CTL0_FORMAT_Pos (24) /*!< I2S_T::CTL0: FORMAT Position */
#define I2S_CTL0_FORMAT_Msk (0x7ul << I2S_CTL0_FORMAT_Pos) /*!< I2S_T::CTL0: FORMAT Mask */
#define I2S_CTL0_PCMSYNC_Pos (27) /*!< I2S_T::CTL0: PCMSYNC Position */
#define I2S_CTL0_PCMSYNC_Msk (0x1ul << I2S_CTL0_PCMSYNC_Pos) /*!< I2S_T::CTL0: PCMSYNC Mask */
#define I2S_CTL0_CHWIDTH_Pos (28) /*!< I2S_T::CTL0: CHWIDTH Position */
#define I2S_CTL0_CHWIDTH_Msk (0x3ul << I2S_CTL0_CHWIDTH_Pos) /*!< I2S_T::CTL0: CHWIDTH Mask */
#define I2S_CTL0_TDMCHNUM_Pos (30) /*!< I2S_T::CTL0: TDMCHNUM Position */
#define I2S_CTL0_TDMCHNUM_Msk (0x3ul << I2S_CTL0_TDMCHNUM_Pos) /*!< I2S_T::CTL0: TDMCHNUM Mask */
#define I2S_CLKDIV_MCLKDIV_Pos (0) /*!< I2S_T::CLKDIV: MCLKDIV Position */
#define I2S_CLKDIV_MCLKDIV_Msk (0x3ful << I2S_CLKDIV_MCLKDIV_Pos) /*!< I2S_T::CLKDIV: MCLKDIV Mask */
#define I2S_CLKDIV_BCLKDIV_Pos (8) /*!< I2S_T::CLKDIV: BCLKDIV Position */
#define I2S_CLKDIV_BCLKDIV_Msk (0x1fful << I2S_CLKDIV_BCLKDIV_Pos) /*!< I2S_T::CLKDIV: BCLKDIV Mask */
#define I2S_IEN_RXUDFIEN_Pos (0) /*!< I2S_T::IEN: RXUDFIEN Position */
#define I2S_IEN_RXUDFIEN_Msk (0x1ul << I2S_IEN_RXUDFIEN_Pos) /*!< I2S_T::IEN: RXUDFIEN Mask */
#define I2S_IEN_RXOVFIEN_Pos (1) /*!< I2S_T::IEN: RXOVFIEN Position */
#define I2S_IEN_RXOVFIEN_Msk (0x1ul << I2S_IEN_RXOVFIEN_Pos) /*!< I2S_T::IEN: RXOVFIEN Mask */
#define I2S_IEN_RXTHIEN_Pos (2) /*!< I2S_T::IEN: RXTHIEN Position */
#define I2S_IEN_RXTHIEN_Msk (0x1ul << I2S_IEN_RXTHIEN_Pos) /*!< I2S_T::IEN: RXTHIEN Mask */
#define I2S_IEN_TXUDFIEN_Pos (8) /*!< I2S_T::IEN: TXUDFIEN Position */
#define I2S_IEN_TXUDFIEN_Msk (0x1ul << I2S_IEN_TXUDFIEN_Pos) /*!< I2S_T::IEN: TXUDFIEN Mask */
#define I2S_IEN_TXOVFIEN_Pos (9) /*!< I2S_T::IEN: TXOVFIEN Position */
#define I2S_IEN_TXOVFIEN_Msk (0x1ul << I2S_IEN_TXOVFIEN_Pos) /*!< I2S_T::IEN: TXOVFIEN Mask */
#define I2S_IEN_TXTHIEN_Pos (10) /*!< I2S_T::IEN: TXTHIEN Position */
#define I2S_IEN_TXTHIEN_Msk (0x1ul << I2S_IEN_TXTHIEN_Pos) /*!< I2S_T::IEN: TXTHIEN Mask */
#define I2S_IEN_CH0ZCIEN_Pos (16) /*!< I2S_T::IEN: CH0ZCIEN Position */
#define I2S_IEN_CH0ZCIEN_Msk (0x1ul << I2S_IEN_CH0ZCIEN_Pos) /*!< I2S_T::IEN: CH0ZCIEN Mask */
#define I2S_IEN_CH1ZCIEN_Pos (17) /*!< I2S_T::IEN: CH1ZCIEN Position */
#define I2S_IEN_CH1ZCIEN_Msk (0x1ul << I2S_IEN_CH1ZCIEN_Pos) /*!< I2S_T::IEN: CH1ZCIEN Mask */
#define I2S_IEN_CH2ZCIEN_Pos (18) /*!< I2S_T::IEN: CH2ZCIEN Position */
#define I2S_IEN_CH2ZCIEN_Msk (0x1ul << I2S_IEN_CH2ZCIEN_Pos) /*!< I2S_T::IEN: CH2ZCIEN Mask */
#define I2S_IEN_CH3ZCIEN_Pos (19) /*!< I2S_T::IEN: CH3ZCIEN Position */
#define I2S_IEN_CH3ZCIEN_Msk (0x1ul << I2S_IEN_CH3ZCIEN_Pos) /*!< I2S_T::IEN: CH3ZCIEN Mask */
#define I2S_IEN_CH4ZCIEN_Pos (20) /*!< I2S_T::IEN: CH4ZCIEN Position */
#define I2S_IEN_CH4ZCIEN_Msk (0x1ul << I2S_IEN_CH4ZCIEN_Pos) /*!< I2S_T::IEN: CH4ZCIEN Mask */
#define I2S_IEN_CH5ZCIEN_Pos (21) /*!< I2S_T::IEN: CH5ZCIEN Position */
#define I2S_IEN_CH5ZCIEN_Msk (0x1ul << I2S_IEN_CH5ZCIEN_Pos) /*!< I2S_T::IEN: CH5ZCIEN Mask */
#define I2S_IEN_CH6ZCIEN_Pos (22) /*!< I2S_T::IEN: CH6ZCIEN Position */
#define I2S_IEN_CH6ZCIEN_Msk (0x1ul << I2S_IEN_CH6ZCIEN_Pos) /*!< I2S_T::IEN: CH6ZCIEN Mask */
#define I2S_IEN_CH7ZCIEN_Pos (23) /*!< I2S_T::IEN: CH7ZCIEN Position */
#define I2S_IEN_CH7ZCIEN_Msk (0x1ul << I2S_IEN_CH7ZCIEN_Pos) /*!< I2S_T::IEN: CH7ZCIEN Mask */
#define I2S_STATUS0_I2SINT_Pos (0) /*!< I2S_T::STATUS0: I2SINT Position */
#define I2S_STATUS0_I2SINT_Msk (0x1ul << I2S_STATUS0_I2SINT_Pos) /*!< I2S_T::STATUS0: I2SINT Mask */
#define I2S_STATUS0_I2SRXINT_Pos (1) /*!< I2S_T::STATUS0: I2SRXINT Position */
#define I2S_STATUS0_I2SRXINT_Msk (0x1ul << I2S_STATUS0_I2SRXINT_Pos) /*!< I2S_T::STATUS0: I2SRXINT Mask */
#define I2S_STATUS0_I2STXINT_Pos (2) /*!< I2S_T::STATUS0: I2STXINT Position */
#define I2S_STATUS0_I2STXINT_Msk (0x1ul << I2S_STATUS0_I2STXINT_Pos) /*!< I2S_T::STATUS0: I2STXINT Mask */
#define I2S_STATUS0_DATACH_Pos (3) /*!< I2S_T::STATUS0: DATACH Position */
#define I2S_STATUS0_DATACH_Msk (0x7ul << I2S_STATUS0_DATACH_Pos) /*!< I2S_T::STATUS0: DATACH Mask */
#define I2S_STATUS0_RXUDIF_Pos (8) /*!< I2S_T::STATUS0: RXUDIF Position */
#define I2S_STATUS0_RXUDIF_Msk (0x1ul << I2S_STATUS0_RXUDIF_Pos) /*!< I2S_T::STATUS0: RXUDIF Mask */
#define I2S_STATUS0_RXOVIF_Pos (9) /*!< I2S_T::STATUS0: RXOVIF Position */
#define I2S_STATUS0_RXOVIF_Msk (0x1ul << I2S_STATUS0_RXOVIF_Pos) /*!< I2S_T::STATUS0: RXOVIF Mask */
#define I2S_STATUS0_RXTHIF_Pos (10) /*!< I2S_T::STATUS0: RXTHIF Position */
#define I2S_STATUS0_RXTHIF_Msk (0x1ul << I2S_STATUS0_RXTHIF_Pos) /*!< I2S_T::STATUS0: RXTHIF Mask */
#define I2S_STATUS0_RXFULL_Pos (11) /*!< I2S_T::STATUS0: RXFULL Position */
#define I2S_STATUS0_RXFULL_Msk (0x1ul << I2S_STATUS0_RXFULL_Pos) /*!< I2S_T::STATUS0: RXFULL Mask */
#define I2S_STATUS0_RXEMPTY_Pos (12) /*!< I2S_T::STATUS0: RXEMPTY Position */
#define I2S_STATUS0_RXEMPTY_Msk (0x1ul << I2S_STATUS0_RXEMPTY_Pos) /*!< I2S_T::STATUS0: RXEMPTY Mask */
#define I2S_STATUS0_TXUDIF_Pos (16) /*!< I2S_T::STATUS0: TXUDIF Position */
#define I2S_STATUS0_TXUDIF_Msk (0x1ul << I2S_STATUS0_TXUDIF_Pos) /*!< I2S_T::STATUS0: TXUDIF Mask */
#define I2S_STATUS0_TXOVIF_Pos (17) /*!< I2S_T::STATUS0: TXOVIF Position */
#define I2S_STATUS0_TXOVIF_Msk (0x1ul << I2S_STATUS0_TXOVIF_Pos) /*!< I2S_T::STATUS0: TXOVIF Mask */
#define I2S_STATUS0_TXTHIF_Pos (18) /*!< I2S_T::STATUS0: TXTHIF Position */
#define I2S_STATUS0_TXTHIF_Msk (0x1ul << I2S_STATUS0_TXTHIF_Pos) /*!< I2S_T::STATUS0: TXTHIF Mask */
#define I2S_STATUS0_TXFULL_Pos (19) /*!< I2S_T::STATUS0: TXFULL Position */
#define I2S_STATUS0_TXFULL_Msk (0x1ul << I2S_STATUS0_TXFULL_Pos) /*!< I2S_T::STATUS0: TXFULL Mask */
#define I2S_STATUS0_TXEMPTY_Pos (20) /*!< I2S_T::STATUS0: TXEMPTY Position */
#define I2S_STATUS0_TXEMPTY_Msk (0x1ul << I2S_STATUS0_TXEMPTY_Pos) /*!< I2S_T::STATUS0: TXEMPTY Mask */
#define I2S_STATUS0_TXBUSY_Pos (21) /*!< I2S_T::STATUS0: TXBUSY Position */
#define I2S_STATUS0_TXBUSY_Msk (0x1ul << I2S_STATUS0_TXBUSY_Pos) /*!< I2S_T::STATUS0: TXBUSY Mask */
#define I2S_TXFIFO_TXFIFO_Pos (0) /*!< I2S_T::TXFIFO: TXFIFO Position */
#define I2S_TXFIFO_TXFIFO_Msk (0xfffffffful << I2S_TXFIFO_TXFIFO_Pos) /*!< I2S_T::TXFIFO: TXFIFO Mask */
#define I2S_RXFIFO_RXFIFO_Pos (0) /*!< I2S_T::RXFIFO: RXFIFO Position */
#define I2S_RXFIFO_RXFIFO_Msk (0xfffffffful << I2S_RXFIFO_RXFIFO_Pos) /*!< I2S_T::RXFIFO: RXFIFO Mask */
#define I2S_CTL1_CH0ZCEN_Pos (0) /*!< I2S_T::CTL1: CH0ZCEN Position */
#define I2S_CTL1_CH0ZCEN_Msk (0x1ul << I2S_CTL1_CH0ZCEN_Pos) /*!< I2S_T::CTL1: CH0ZCEN Mask */
#define I2S_CTL1_CH1ZCEN_Pos (1) /*!< I2S_T::CTL1: CH1ZCEN Position */
#define I2S_CTL1_CH1ZCEN_Msk (0x1ul << I2S_CTL1_CH1ZCEN_Pos) /*!< I2S_T::CTL1: CH1ZCEN Mask */
#define I2S_CTL1_CH2ZCEN_Pos (2) /*!< I2S_T::CTL1: CH2ZCEN Position */
#define I2S_CTL1_CH2ZCEN_Msk (0x1ul << I2S_CTL1_CH2ZCEN_Pos) /*!< I2S_T::CTL1: CH2ZCEN Mask */
#define I2S_CTL1_CH3ZCEN_Pos (3) /*!< I2S_T::CTL1: CH3ZCEN Position */
#define I2S_CTL1_CH3ZCEN_Msk (0x1ul << I2S_CTL1_CH3ZCEN_Pos) /*!< I2S_T::CTL1: CH3ZCEN Mask */
#define I2S_CTL1_CH4ZCEN_Pos (4) /*!< I2S_T::CTL1: CH4ZCEN Position */
#define I2S_CTL1_CH4ZCEN_Msk (0x1ul << I2S_CTL1_CH4ZCEN_Pos) /*!< I2S_T::CTL1: CH4ZCEN Mask */
#define I2S_CTL1_CH5ZCEN_Pos (5) /*!< I2S_T::CTL1: CH5ZCEN Position */
#define I2S_CTL1_CH5ZCEN_Msk (0x1ul << I2S_CTL1_CH5ZCEN_Pos) /*!< I2S_T::CTL1: CH5ZCEN Mask */
#define I2S_CTL1_CH6ZCEN_Pos (6) /*!< I2S_T::CTL1: CH6ZCEN Position */
#define I2S_CTL1_CH6ZCEN_Msk (0x1ul << I2S_CTL1_CH6ZCEN_Pos) /*!< I2S_T::CTL1: CH6ZCEN Mask */
#define I2S_CTL1_CH7ZCEN_Pos (7) /*!< I2S_T::CTL1: CH7ZCEN Position */
#define I2S_CTL1_CH7ZCEN_Msk (0x1ul << I2S_CTL1_CH7ZCEN_Pos) /*!< I2S_T::CTL1: CH7ZCEN Mask */
#define I2S_CTL1_TXTH_Pos (8) /*!< I2S_T::CTL1: TXTH Position */
#define I2S_CTL1_TXTH_Msk (0xful << I2S_CTL1_TXTH_Pos) /*!< I2S_T::CTL1: TXTH Mask */
#define I2S_CTL1_RXTH_Pos (16) /*!< I2S_T::CTL1: RXTH Position */
#define I2S_CTL1_RXTH_Msk (0xful << I2S_CTL1_RXTH_Pos) /*!< I2S_T::CTL1: RXTH Mask */
#define I2S_CTL1_PBWIDTH_Pos (24) /*!< I2S_T::CTL1: PBWIDTH Position */
#define I2S_CTL1_PBWIDTH_Msk (0x1ul << I2S_CTL1_PBWIDTH_Pos) /*!< I2S_T::CTL1: PBWIDTH Mask */
#define I2S_CTL1_PB16ORD_Pos (25) /*!< I2S_T::CTL1: PB16ORD Position */
#define I2S_CTL1_PB16ORD_Msk (0x1ul << I2S_CTL1_PB16ORD_Pos) /*!< I2S_T::CTL1: PB16ORD Mask */
#define I2S_STATUS1_CH0ZCIF_Pos (0) /*!< I2S_T::STATUS1: CH0ZCIF Position */
#define I2S_STATUS1_CH0ZCIF_Msk (0x1ul << I2S_STATUS1_CH0ZCIF_Pos) /*!< I2S_T::STATUS1: CH0ZCIF Mask */
#define I2S_STATUS1_CH1ZCIF_Pos (1) /*!< I2S_T::STATUS1: CH1ZCIF Position */
#define I2S_STATUS1_CH1ZCIF_Msk (0x1ul << I2S_STATUS1_CH1ZCIF_Pos) /*!< I2S_T::STATUS1: CH1ZCIF Mask */
#define I2S_STATUS1_CH2ZCIF_Pos (2) /*!< I2S_T::STATUS1: CH2ZCIF Position */
#define I2S_STATUS1_CH2ZCIF_Msk (0x1ul << I2S_STATUS1_CH2ZCIF_Pos) /*!< I2S_T::STATUS1: CH2ZCIF Mask */
#define I2S_STATUS1_CH3ZCIF_Pos (3) /*!< I2S_T::STATUS1: CH3ZCIF Position */
#define I2S_STATUS1_CH3ZCIF_Msk (0x1ul << I2S_STATUS1_CH3ZCIF_Pos) /*!< I2S_T::STATUS1: CH3ZCIF Mask */
#define I2S_STATUS1_CH4ZCIF_Pos (4) /*!< I2S_T::STATUS1: CH4ZCIF Position */
#define I2S_STATUS1_CH4ZCIF_Msk (0x1ul << I2S_STATUS1_CH4ZCIF_Pos) /*!< I2S_T::STATUS1: CH4ZCIF Mask */
#define I2S_STATUS1_CH5ZCIF_Pos (5) /*!< I2S_T::STATUS1: CH5ZCIF Position */
#define I2S_STATUS1_CH5ZCIF_Msk (0x1ul << I2S_STATUS1_CH5ZCIF_Pos) /*!< I2S_T::STATUS1: CH5ZCIF Mask */
#define I2S_STATUS1_CH6ZCIF_Pos (6) /*!< I2S_T::STATUS1: CH6ZCIF Position */
#define I2S_STATUS1_CH6ZCIF_Msk (0x1ul << I2S_STATUS1_CH6ZCIF_Pos) /*!< I2S_T::STATUS1: CH6ZCIF Mask */
#define I2S_STATUS1_CH7ZCIF_Pos (7) /*!< I2S_T::STATUS1: CH7ZCIF Position */
#define I2S_STATUS1_CH7ZCIF_Msk (0x1ul << I2S_STATUS1_CH7ZCIF_Pos) /*!< I2S_T::STATUS1: CH7ZCIF Mask */
#define I2S_STATUS1_TXCNT_Pos (8) /*!< I2S_T::STATUS1: TXCNT Position */
#define I2S_STATUS1_TXCNT_Msk (0x1ful << I2S_STATUS1_TXCNT_Pos) /*!< I2S_T::STATUS1: TXCNT Mask */
#define I2S_STATUS1_RXCNT_Pos (16) /*!< I2S_T::STATUS1: RXCNT Position */
#define I2S_STATUS1_RXCNT_Msk (0x1ful << I2S_STATUS1_RXCNT_Pos) /*!< I2S_T::STATUS1: RXCNT Mask */
/**@}*/ /* I2S_CONST */
/**@}*/ /* end of I2S register group */
/*---------------------- Serial Peripheral Interface Controller -------------------------*/
/**
@addtogroup SPI Serial Peripheral Interface Controller(SPI)
Memory Mapped Structure for SPI Controller
@{ */
typedef struct {
/**
* @var SPI_T::CTL
* Offset: 0x00 SPI Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SPIEN |SPI Transfer Control Enable Bit
* | | |In Master mode, the transfer will start when there is data in the FIFO buffer after this bit is set to 1
* | | |In Slave mode, this device is ready to receive data when this bit is set to 1.
* | | |0 = Transfer control Disabled.
* | | |1 = Transfer control Enabled.
* | | |Note: Before changing the configurations of SPIx_CTL, SPIx_CLKDIV, SPIx_SSCTL and SPIx_FIFOCTL registers, user shall clear the SPIEN (SPIx_CTL[0]) and confirm the SPIENSTS (SPIx_STATUS[15]) is 0.
* |[1] |RXNEG |Receive on Negative Edge
* | | |0 = Received data input signal is latched on the rising edge of SPI bus clock.
* | | |1 = Received data input signal is latched on the falling edge of SPI bus clock.
* |[2] |TXNEG |Transmit on Negative Edge
* | | |0 = Transmitted data output signal is changed on the rising edge of SPI bus clock.
* | | |1 = Transmitted data output signal is changed on the falling edge of SPI bus clock.
* |[3] |CLKPOL |Clock Polarity
* | | |0 = SPI bus clock is idle low.
* | | |1 = SPI bus clock is idle high.
* |[7:4] |SUSPITV |Suspend Interval (Master Only)
* | | |The four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer
* | | |The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word
* | | |The default value is 0x3
* | | |The period of the suspend interval is obtained according to the following equation.
* | | |(SUSPITV[3:0] + 0.5) * period of SPICLK clock cycle
* | | |Example:
* | | |SUSPITV = 0x0 .... 0.5 SPICLK clock cycle.
* | | |SUSPITV = 0x1 .... 1.5 SPICLK clock cycle.
* | | |.....
* | | |SUSPITV = 0xE .... 14.5 SPICLK clock cycle.
* | | |SUSPITV = 0xF .... 15.5 SPICLK clock cycle.
* |[12:8] |DWIDTH |Data Width
* | | |This field specifies how many bits can be transmitted / received in one transaction
* | | |The minimum bit length is 8 bits and can up to 32 bits.
* | | |DWIDTH = 0x08 .... 8 bits.
* | | |DWIDTH = 0x09 .... 9 bits.
* | | |.....
* | | |DWIDTH = 0x1F .... 31 bits.
* | | |DWIDTH = 0x00 .... 32 bits.
* | | |Note: For SPI1~SPI4, this bit field will decide the depth of TX/RX FIFO configuration in SPI mode
* | | |Therefore, changing this bit field will clear TX/RX FIFO by hardware automatically in SPI1~SPI4.
* |[13] |LSB |Send LSB First
* | | |0 = The MSB, which bit of transmit/receive register depends on the setting of DWIDTH, is transmitted/received first.
* | | |1 = The LSB, bit 0 of the SPI TX register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX).
* |[14] |HALFDPX |SPI Half-duplex Transfer Enable Bit
* | | |This bit is used to select full-duplex or half-duplex for SPI transfer
* | | |The bit field DATDIR (SPIx_CTL[20]) can be used to set the data direction in half-duplex transfer.
* | | |0 = SPI operates in full-duplex transfer.
* | | |1 = SPI operates in half-duplex transfer.
* |[15] |RXONLY |Receive-only Mode Enable Bit (Master Only)
* | | |This bit field is only available in Master mode
* | | |In receive-only mode, SPI Master will generate SPI bus clock continuously for receiving data bit from SPI slave device and assert the BUSY status.
* | | |0 = Receive-only mode Disabled.
* | | |1 = Receive-only mode Enabled.
* |[16] |TWOBIT |2-bit Transfer Mode Enable Bit (Only Supported in SPI0)
* | | |0 = 2-Bit Transfer mode Disabled.
* | | |1 = 2-Bit Transfer mode Enabled.
* | | |Note: When 2-Bit Transfer mode is enabled, the first serial transmitted bit data is from the first FIFO buffer data, and the 2nd serial transmitted bit data is from the second FIFO buffer data
* | | |As the same as transmitted function, the first received bit data is stored into the first FIFO buffer and the 2nd received bit data is stored into the second FIFO buffer at the same time.
* |[17] |UNITIEN |Unit Transfer Interrupt Enable Bit
* | | |0 = SPI unit transfer interrupt Disabled.
* | | |1 = SPI unit transfer interrupt Enabled.
* |[18] |SLAVE |Slave Mode Control
* | | |0 = Master mode.
* | | |1 = Slave mode.
* |[19] |REORDER |Byte Reorder Function Enable Bit
* | | |0 = Byte Reorder function Disabled.
* | | |1 = Byte Reorder function Enabled
* | | |A byte suspend interval will be inserted among each byte
* | | |The period of the byte suspend interval depends on the setting of SUSPITV.
* | | |Note: Byte Reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits.
* |[20] |DATDIR |Data Port Direction Control
* | | |This bit is used to select the data input/output direction in half-duplex transfer and Dual/Quad transfer
* | | |0 = SPI data is input direction.
* | | |1 = SPI data is output direction.
* |[21] |DUALIOEN |Dual I/O Mode Enable Bit (Only Supported in SPI0)
* | | |0 = Dual I/O mode Disabled.
* | | |1 = Dual I/O mode Enabled.
* |[22] |QUADIOEN |Quad I/O Mode Enable Bit (Only Supported in SPI0)
* | | |0 = Quad I/O mode Disabled.
* | | |1 = Quad I/O mode Enabled.
* @var SPI_T::CLKDIV
* Offset: 0x04 SPI Clock Divider Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[8:0] |DIVIDER |Clock Divider
* | | |The value in this field is the frequency divider for generating the peripheral clock, fspi_eclk, and the SPI bus clock of SPI Master
* | | |The frequency is obtained according to the following equation.
* | | |where
* | | |is the peripheral clock source, which is defined in the clock control register, CLK_CLKSEL2.
* | | |Note: Not supported in I2S mode.
* @var SPI_T::SSCTL
* Offset: 0x08 SPI Slave Select Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SS |Slave Selection Control (Master Only)
* | | |If AUTOSS bit is cleared to 0,
* | | |0 = set the SPIx_SS line to inactive state.
* | | |1 = set the SPIx_SS line to active state.
* | | |If the AUTOSS bit is set to 1,
* | | |0 = Keep the SPIx_SS line at inactive state.
* | | |1 = SPIx_SS line will be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time
* | | |The active state of SPIx_SS is specified in SSACTPOL (SPIx_SSCTL[2]).
* |[2] |SSACTPOL |Slave Selection Active Polarity
* | | |This bit defines the active polarity of slave selection signal (SPIx_SS).
* | | |0 = The slave selection signal SPIx_SS is active low.
* | | |1 = The slave selection signal SPIx_SS is active high.
* |[3] |AUTOSS |Automatic Slave Selection Function Enable Bit (Master Only)
* | | |0 = Automatic slave selection function Disabled
* | | |Slave selection signal will be asserted/de-asserted according to SS (SPIx_SSCTL[0]).
* | | |1 = Automatic slave selection function Enabled.
* |[4] |SLV3WIRE |Slave 3-wire Mode Enable Bit (Only Supported in SPI0)
* | | |Slave 3-wire mode is only available in SPI0
* | | |In Slave 3-wire mode, the SPI controller can work with 3-wire interface including SPI0_CLK, SPI0_MISO and SPI0_MOSI pins.
* | | |0 = 4-wire bi-direction interface.
* | | |1 = 3-wire bi-direction interface.
* |[5] |SLVTOIEN |Slave Mode Time-out Interrupt Enable Bit (Only Supported in SPI0)
* | | |0 = Slave mode time-out interrupt Disabled.
* | | |1 = Slave mode time-out interrupt Enabled.
* |[6] |SLVTORST |Slave Mode Time-out Reset Control (Only Supported in SPI0)
* | | |0 = When Slave mode time-out event occurs, the TX and RX control circuit will not be reset.
* | | |1 = When Slave mode time-out event occurs, the TX and RX control circuit will be reset by hardware.
* |[8] |SLVBEIEN |Slave Mode Bit Count Error Interrupt Enable Bit
* | | |0 = Slave mode bit count error interrupt Disabled.
* | | |1 = Slave mode bit count error interrupt Enabled.
* |[9] |SLVURIEN |Slave Mode TX Under Run Interrupt Enable Bit
* | | |0 = Slave mode TX under run interrupt Disabled.
* | | |1 = Slave mode TX under run interrupt Enabled.
* |[12] |SSACTIEN |Slave Select Active Interrupt Enable Bit
* | | |0 = Slave select active interrupt Disabled.
* | | |1 = Slave select active interrupt Enabled.
* |[13] |SSINAIEN |Slave Select Inactive Interrupt Enable Bit
* | | |0 = Slave select inactive interrupt Disabled.
* | | |1 = Slave select inactive interrupt Enabled.
* |[31:16] |SLVTOCNT |Slave Mode Time-out Period (Only Supported in SPI0)
* | | |In Slave mode, these bits indicate the time-out period when there is bus clock input during slave select active
* | | |The clock source of the time-out counter is Slave peripheral clock
* | | |If the value is 0, it indicates the slave mode time-out function is disabled.
* @var SPI_T::PDMACTL
* Offset: 0x0C SPI PDMA Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |TXPDMAEN |Transmit PDMA Enable Bit
* | | |0 = Transmit PDMA function Disabled.
* | | |1 = Transmit PDMA function Enabled.
* | | |Note: In SPI Master mode with full duplex transfer, if both TX and RX PDMA functions are enabled, RX PDMA function cannot be enabled prior to TX PDMA function
* | | |User can enable TX PDMA function firstly or enable both functions simultaneously.
* |[1] |RXPDMAEN |Receive PDMA Enable Bit
* | | |0 = Receive PDMA function Disabled.
* | | |1 = Receive PDMA function Enabled.
* |[2] |PDMARST |PDMA Reset
* | | |0 = No effect.
* | | |1 = Reset the PDMA control logic of the SPI controller. This bit will be automatically cleared to 0.
* @var SPI_T::FIFOCTL
* Offset: 0x10 SPI FIFO Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |RXRST |Receive Reset
* | | |0 = No effect.
* | | |1 = Reset receive FIFO pointer and receive circuit
* | | |The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1
* | | |This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1
* | | |User can read TXRXRST (SPIx_STATUS[23]) to check if reset is accomplished or not.
* |[1] |TXRST |Transmit Reset
* | | |0 = No effect.
* | | |1 = Reset transmit FIFO pointer and transmit circuit
* | | |The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1
* | | |This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1
* | | |User can read TXRXRST (SPIx_STATUS[23]) to check if reset is accomplished or not.
* | | |Note: If TX underflow event occurs in SPI Slave mode, this bit can be used to make SPI return to idle state.
* |[2] |RXTHIEN |Receive FIFO Threshold Interrupt Enable Bit
* | | |0 = RX FIFO threshold interrupt Disabled.
* | | |1 = RX FIFO threshold interrupt Enabled.
* |[3] |TXTHIEN |Transmit FIFO Threshold Interrupt Enable Bit
* | | |0 = TX FIFO threshold interrupt Disabled.
* | | |1 = TX FIFO threshold interrupt Enabled.
* |[4] |RXTOIEN |Slave Receive Time-out Interrupt Enable Bit
* | | |0 = Receive time-out interrupt Disabled.
* | | |1 = Receive time-out interrupt Enabled.
* |[5] |RXOVIEN |Receive FIFO Overrun Interrupt Enable Bit
* | | |0 = Receive FIFO overrun interrupt Disabled.
* | | |1 = Receive FIFO overrun interrupt Enabled.
* |[6] |TXUFPOL |TX Underflow Data Polarity
* | | |0 = The SPI data out is keep 0 if there is TX underflow event in Slave mode.
* | | |1 = The SPI data out is keep 1 if there is TX underflow event in Slave mode.
* | | |Note:
* | | |1. The TX underflow event occurs if there is no any data in TX FIFO when the slave selection signal is active.
* | | |2. This bit should be set as 0 in I2S mode.
* | | |3. When TX underflow event occurs, SPIx_MISO pin state will be determined by this setting even though TX FIFO is not empty afterward
* | | |Data stored in TX FIFO will be sent through SPIx_MISO pin in the next transfer frame.
* |[7] |TXUFIEN |TX Underflow Interrupt Enable Bit
* | | |When TX underflow event occurs in Slave mode, TXUFIF (SPIx_STATUS[19]) will be set to 1
* | | |This bit is used to enable the TX underflow interrupt.
* | | |0 = Slave TX underflow interrupt Disabled.
* | | |1 = Slave TX underflow interrupt Enabled.
* |[8] |RXFBCLR |Receive FIFO Buffer Clear
* | | |0 = No effect.
* | | |1 = Clear receive FIFO pointer
* | | |The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1
* | | |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1.
* | | |Note: The RX shift register will not be cleared.
* |[9] |TXFBCLR |Transmit FIFO Buffer Clear
* | | |0 = No effect.
* | | |1 = Clear transmit FIFO pointer
* | | |The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1
* | | |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1.
* | | |Note: The TX shift register will not be cleared.
* |[26:24] |RXTH |Receive FIFO Threshold
* | | |If the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0
* | | |For SPI1~SPI4, the MSB of this bit field is only meaningful while SPI mode 8~16 bits of data length.
* |[30:28] |TXTH |Transmit FIFO Threshold
* | | |If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0
* | | |For SPI1~SPI4, the MSB of this bit field is only meaningful while SPI mode 8~16 bits of data length
* @var SPI_T::STATUS
* Offset: 0x14 SPI Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |BUSY |Busy Status (Read Only)
* | | |0 = SPI controller is in idle state.
* | | |1 = SPI controller is in busy state.
* | | |The following listing are the bus busy conditions:
* | | |a. SPIx_CTL[0] = 1 and TXEMPTY = 0.
* | | |b
* | | |For SPI Master mode, SPIx_CTL[0] = 1 and TXEMPTY = 1 but the current transaction is not finished yet.
* | | |c. For SPI Master mode, SPIx_CTL[0] = 1 and RXONLY = 1.
* | | |d
* | | |For SPI Slave mode, the SPIx_CTL[0] = 1 and there is serial clock input into the SPI core logic when slave select is active.
* | | |For SPI Slave mode, the SPIx_CTL[0] = 1 and the transmit buffer or transmit shift register is not empty even if the slave select is inactive.
* |[1] |UNITIF |Unit Transfer Interrupt Flag
* | | |0 = No transaction has been finished since this bit was cleared to 0.
* | | |1 = SPI controller has finished one unit transfer.
* | | |Note: This bit will be cleared by writing 1 to it.
* |[2] |SSACTIF |Slave Select Active Interrupt Flag
* | | |0 = Slave select active interrupt was cleared or not occurred.
* | | |1 = Slave select active interrupt event occurred.
* | | |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it.
* |[3] |SSINAIF |Slave Select Inactive Interrupt Flag
* | | |0 = Slave select inactive interrupt was cleared or not occurred.
* | | |1 = Slave select inactive interrupt event occurred.
* | | |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it.
* |[4] |SSLINE |Slave Select Line Bus Status (Read Only)
* | | |0 = The slave select line status is 0.
* | | |1 = The slave select line status is 1.
* | | |Note: This bit is only available in Slave mode
* | | |If SSACTPOL (SPIx_SSCTL[2]) is set 0, and the SSLINE is 1, the SPI slave select is in inactive status.
* |[5] |SLVTOIF |Slave Time-out Interrupt Flag (Only Supported in SPI0)
* | | |When the slave select is active and the value of SLVTOCNT is not 0, as the bus clock is detected, the slave time-out counter in SPI controller logic will be started
* | | |When the value of time-out counter is greater than or equal to the value of SLVTOCNT (SPI_SSCTL[31:16]) before one transaction is done, the slave time-out interrupt event will be asserted.
* | | |0 = Slave time-out is not active.
* | | |1 = Slave time-out is active.
* | | |Note: This bit will be cleared by writing 1 to it.
* |[6] |SLVBEIF |Slave Mode Bit Count Error Interrupt Flag
* | | |In Slave mode, when the slave select line goes to inactive state, if bit counter is mismatch with DWIDTH, this interrupt flag will be set to 1.
* | | |0 = No Slave mode bit count error event.
* | | |1 = Slave mode bit count error event occurs.
* | | |Note: If the slave select active but there is no any bus clock input, the SLVBEIF also active when the slave select goes to inactive state
* | | |This bit will be cleared by writing 1 to it.
* |[7] |SLVURIF |Slave Mode TX Under Run Interrupt Flag
* | | |In Slave mode, if TX underflow event occurs and the slave select line goes to inactive state, this interrupt flag will be set to 1.
* | | |0 = No Slave TX under run event.
* | | |1 = Slave TX under run event occurs.
* | | |Note: This bit will be cleared by writing 1 to it.
* |[8] |RXEMPTY |Receive FIFO Buffer Empty Indicator (Read Only)
* | | |0 = Receive FIFO buffer is not empty.
* | | |1 = Receive FIFO buffer is empty.
* |[9] |RXFULL |Receive FIFO Buffer Full Indicator (Read Only)
* | | |0 = Receive FIFO buffer is not full.
* | | |1 = Receive FIFO buffer is full.
* |[10] |RXTHIF |Receive FIFO Threshold Interrupt Flag (Read Only)
* | | |0 = The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH.
* | | |1 = The valid data count within the receive FIFO buffer is larger than the setting value of RXTH.
* |[11] |RXOVIF |Receive FIFO Overrun Interrupt Flag
* | | |When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.
* | | |0 = No FIFO is overrun.
* | | |1 = Receive FIFO is overrun.
* | | |Note: This bit will be cleared by writing 1 to it.
* |[12] |RXTOIF |Receive Time-out Interrupt Flag
* | | |0 = No receive FIFO time-out event.
* | | |1 = Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI peripheral clock periods in Master mode or over 576 SPI peripheral clock periods in Slave mode
* | | |When the received FIFO buffer is read by software, the time-out status will be cleared automatically.
* | | |Note: This bit will be cleared by writing 1 to it.
* |[15] |SPIENSTS |SPI Enable Status (Read Only)
* | | |0 = The SPI controller is disabled.
* | | |1 = The SPI controller is enabled.
* | | |Note: The SPI peripheral clock is asynchronous with the system clock
* | | |In order to make sure the SPI control logic is disabled, this bit indicates the real status of SPI controller.
* |[16] |TXEMPTY |Transmit FIFO Buffer Empty Indicator (Read Only)
* | | |0 = Transmit FIFO buffer is not empty.
* | | |1 = Transmit FIFO buffer is empty.
* |[17] |TXFULL |Transmit FIFO Buffer Full Indicator (Read Only)
* | | |0 = Transmit FIFO buffer is not full.
* | | |1 = Transmit FIFO buffer is full.
* |[18] |TXTHIF |Transmit FIFO Threshold Interrupt Flag (Read Only)
* | | |0 = The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH.
* | | |1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH.
* |[19] |TXUFIF |TX Underflow Interrupt Flag
* | | |When the TX underflow event occurs, this bit will be set to 1, the state of data output pin depends on the setting of TXUFPOL.
* | | |0 = No effect.
* | | |1 = No data in Transmit FIFO and TX shift register when the slave selection signal is active.
* | | |Note 1: This bit will be cleared by writing 1 to it.
* | | |Note 2: If reset slave's transmission circuit when slave selection signal is active, this flag will be set to 1 after 2 peripheral clock cycles + 3 system clock cycles since the reset operation is done.
* |[23] |TXRXRST |TX or RX Reset Status (Read Only)
* | | |0 = The reset function of TXRST or RXRST is done.
* | | |1 = Doing the reset function of TXRST or RXRST.
* | | |Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles
* | | |User can check the status of this bit to monitor the reset function is doing or done.
* |[27:24] |RXCNT |Receive FIFO Data Count (Read Only)
* | | |This bit field indicates the valid data count of receive FIFO buffer.
* |[31:28] |TXCNT |Transmit FIFO Data Count (Read Only)
* | | |This bit field indicates the valid data count of transmit FIFO buffer.
* @var SPI_T::TX
* Offset: 0x20 SPI Data Transmit Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |TX |Data Transmit Register
* | | |The data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers
* | | |The number of valid bits depends on the setting of DWIDTH (SPIx_CTL[12:8]) in SPI mode or WDWIDTH (SPIx_I2SCTL[5:4]) in I2S mode.
* | | |In SPI mode, if DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted
* | | |If DWIDTH is set to 0x00 , the SPI controller will perform a 32-bit transfer.
* | | |In I2S mode, if WDWIDTH (SPIx_I2SCTL[5:4]) is set to 0x2, the data width of audio channel is 24-bit and corresponding to TX[23:0]
* | | |If WDWIDTH is set as 0x0, 0x1, or 0x3, all bits of this field are valid and referred to the data arrangement in I2S mode FIFO operation section
* | | |Note: In Master mode, SPI controller will start to transfer the SPI bus clock after 1 APB clock and 6 peripheral clock cycles after user writes to this register.
* @var SPI_T::RX
* Offset: 0x30 SPI Data Receive Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |RX |Data Receive Register
* | | |There are 4-level FIFO buffers in this controller
* | | |The data receive register holds the data received from SPI data input pin
* | | |If the RXEMPTY (SPIx_STATUS[8] or SPIx_I2SSTS[8]) is not set to 1, the receive FIFO buffers can be accessed through software by reading this register
* | | |This is a read only register.
* @var SPI_T::I2SCTL
* Offset: 0x60 I2S Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |I2SEN |I2S Controller Enable Bit
* | | |0 = Disabled I2S mode.
* | | |1 = Enabled I2S mode.
* | | |Note:
* | | |1. If enable this bit, I2Sx_BCLK will start to output in Master mode.
* | | |2
* | | |Before changing the configurations of SPIx_I2SCTL, SPIx_I2SCLK, and SPIx_FIFOCTL registers, user shall clear the I2SEN (SPIx_I2SCTL[0]) and confirm the I2SENSTS (SPIx_I2SSTS[15]) is 0.
* |[1] |TXEN |Transmit Enable Bit
* | | |0 = Data transmit Disabled.
* | | |1 = Data transmit Enabled.
* |[2] |RXEN |Receive Enable Bit
* | | |0 = Data receive Disabled.
* | | |1 = Data receive Enabled.
* |[3] |MUTE |Transmit Mute Enable Bit
* | | |0 = Transmit data is shifted from buffer.
* | | |1 = Transmit channel zero.
* |[5:4] |WDWIDTH |Word Width
* | | |00 = data size is 8-bit.
* | | |01 = data size is 16-bit.
* | | |10 = data size is 24-bit.
* | | |11 = data size is 32-bit.
* |[6] |MONO |Monaural Data
* | | |0 = Data is stereo format.
* | | |1 = Data is monaural format.
* |[7] |ORDER |Stereo Data Order in FIFO
* | | |0 = Left channel data at high byte.
* | | |1 = Left channel data at low byte.
* |[8] |SLAVE |Slave Mode
* | | |I2S can operate as master or slave
* | | |For Master mode, I2Sx_BCLK and I2Sx_LRCLK pins are output mode and send bit clock from NuMicro M480 series to audio CODEC chip
* | | |In Slave mode, I2Sx_BCLK and I2Sx_LRCLK pins are input mode and I2Sx_BCLK and I2Sx_LRCLK signals are received from outer audio CODEC chip.
* | | |0 = Master mode.
* | | |1 = Slave mode.
* |[15] |MCLKEN |Master Clock Enable Bit
* | | |If MCLKEN is set to 1, I2S controller will generate master clock on SPIx_I2SMCLK pin for external audio devices.
* | | |0 = Master clock Disabled.
* | | |1 = Master clock Enabled.
* |[16] |RZCEN |Right Channel Zero Cross Detection Enable Bit
* | | |If this bit is set to 1, when right channel data sign bit change or next shift data bits are all 0 then RZCIF flag in SPIx_I2SSTS register is set to 1
* | | |This function is only available in transmit operation.
* | | |0 = Right channel zero cross detection Disabled.
* | | |1 = Right channel zero cross detection Enabled.
* |[17] |LZCEN |Left Channel Zero Cross Detection Enable Bit
* | | |If this bit is set to 1, when left channel data sign bit changes or next shift data bits are all 0 then LZCIF flag in SPIx_I2SSTS register is set to 1
* | | |This function is only available in transmit operation.
* | | |0 = Left channel zero cross detection Disabled.
* | | |1 = Left channel zero cross detection Enabled.
* |[23] |RXLCH |Receive Left Channel Enable Bit
* | | |When monaural format is selected (MONO = 1), I2S controller will receive right channel data if RXLCH is set to 0, and receive left channel data if RXLCH is set to 1.
* | | |0 = Receive right channel data in Mono mode.
* | | |1 = Receive left channel data in Mono mode.
* |[24] |RZCIEN |Right Channel Zero Cross Interrupt Enable Bit
* | | |Interrupt occurs if this bit is set to 1 and right channel zero cross event occurs.
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* |[25] |LZCIEN |Left Channel Zero Cross Interrupt Enable Bit
* | | |Interrupt occurs if this bit is set to 1 and left channel zero cross event occurs.
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* |[29:28] |FORMAT |Data Format Selection
* | | |00 = I2S data format.
* | | |01 = MSB justified data format.
* | | |10 = PCM mode A.
* | | |11 = PCM mode B.
* @var SPI_T::I2SCLK
* Offset: 0x64 I2S Clock Divider Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[6:0] |MCLKDIV |Master Clock Divider
* | | |If MCLKEN is set to 1, I2S controller will generate master clock for external audio devices
* | | |The frequency of master clock, fMCLK, is determined by the following expressions:
* | | |If MCLKDIV >= 1,.
* | | |If MCLKDIV = 0,.
* | | |where
* | | |is the frequency of I2S peripheral clock source, which is defined in the clock control register CLK_CLKSEL2
* | | |In general, the master clock rate is 256 times sampling clock rate.
* |[17:8] |BCLKDIV |Bit Clock Divider
* | | |The I2S controller will generate bit clock in Master mode
* | | |The clock frequency of bit clock , fBCLK, is determined by the following expression:
* | | |where
* | | |is the frequency of I2S peripheral clock source, which is defined in the clock control register CLK_CLKSEL2.
* | | |In I2S Slave mode, this field is used to define the frequency of peripheral clock and it's determined by .
* | | |The peripheral clock frequency in I2S Slave mode must be equal to or faster than 6 times of input bit clock.
* @var SPI_T::I2SSTS
* Offset: 0x68 I2S Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[4] |RIGHT |Right Channel (Read Only)
* | | |This bit indicates the current transmit data is belong to which channel.
* | | |0 = Left channel.
* | | |1 = Right channel.
* |[8] |RXEMPTY |Receive FIFO Buffer Empty Indicator (Read Only)
* | | |0 = Receive FIFO buffer is not empty.
* | | |1 = Receive FIFO buffer is empty.
* |[9] |RXFULL |Receive FIFO Buffer Full Indicator (Read Only)
* | | |0 = Receive FIFO buffer is not full.
* | | |1 = Receive FIFO buffer is full.
* |[10] |RXTHIF |Receive FIFO Threshold Interrupt Flag (Read Only)
* | | |0 = The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH.
* | | |1 = The valid data count within the receive FIFO buffer is larger than the setting value of RXTH.
* | | |Note: If RXTHIEN = 1 and RXTHIF = 1, the SPI/I2S controller will generate a SPI interrupt request.
* |[11] |RXOVIF |Receive FIFO Overrun Interrupt Flag
* | | |When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.
* | | |Note: This bit will be cleared by writing 1 to it.
* |[12] |RXTOIF |Receive Time-out Interrupt Flag
* | | |0 = No receive FIFO time-out event.
* | | |1 = Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI peripheral clock period in Master mode or over 576 SPI peripheral clock period in Slave mode
* | | |When the received FIFO buffer is read by software, the time-out status will be cleared automatically.
* | | |Note: This bit will be cleared by writing 1 to it.
* |[15] |I2SENSTS |I2S Enable Status (Read Only)
* | | |0 = The SPI/I2S control logic is disabled.
* | | |1 = The SPI/I2S control logic is enabled.
* | | |Note: The SPI peripheral clock is asynchronous with the system clock
* | | |In order to make sure the SPI/I2S control logic is disabled, this bit indicates the real status of SPI/I2S control logic for user.
* |[16] |TXEMPTY |Transmit FIFO Buffer Empty Indicator (Read Only)
* | | |0 = Transmit FIFO buffer is not empty.
* | | |1 = Transmit FIFO buffer is empty.
* |[17] |TXFULL |Transmit FIFO Buffer Full Indicator (Read Only)
* | | |0 = Transmit FIFO buffer is not full.
* | | |1 = Transmit FIFO buffer is full.
* |[18] |TXTHIF |Transmit FIFO Threshold Interrupt Flag (Read Only)
* | | |0 = The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH.
* | | |1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH.
* | | |Note: If TXTHIEN = 1 and TXTHIF = 1, the SPI/I2S controller will generate a SPI interrupt request.
* |[19] |TXUFIF |Transmit FIFO Underflow Interrupt Flag
* | | |When the transmit FIFO buffer is empty and there is no datum written into the FIFO buffer, if there is more bus clock input, this bit will be set to 1.
* | | |Note: This bit will be cleared by writing 1 to it.
* |[20] |RZCIF |Right Channel Zero Cross Interrupt Flag
* | | |0 = No zero cross event occurred on right channel.
* | | |1 = Zero cross event occurred on right channel.
* |[21] |LZCIF |Left Channel Zero Cross Interrupt Flag
* | | |0 = No zero cross event occurred on left channel.
* | | |1 = Zero cross event occurred on left channel.
* |[23] |TXRXRST |TX or RX Reset Status (Read Only)
* | | |0 = The reset function of TXRST or RXRST is done.
* | | |1 = Doing the reset function of TXRST or RXRST.
* | | |Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles
* | | |User can check the status of this bit to monitor the reset function is doing or done.
* |[26:24] |RXCNT |Receive FIFO Data Count (Read Only)
* | | |This bit field indicates the valid data count of receive FIFO buffer.
* |[30:28] |TXCNT |Transmit FIFO Data Count (Read Only)
* | | |This bit field indicates the valid data count of transmit FIFO buffer.
*/
__IO uint32_t CTL; /*!< [0x0000] SPI Control Register */
__IO uint32_t CLKDIV; /*!< [0x0004] SPI Clock Divider Register */
__IO uint32_t SSCTL; /*!< [0x0008] SPI Slave Select Control Register */
__IO uint32_t PDMACTL; /*!< [0x000c] SPI PDMA Control Register */
__IO uint32_t FIFOCTL; /*!< [0x0010] SPI FIFO Control Register */
__IO uint32_t STATUS; /*!< [0x0014] SPI Status Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE0[2];
/// @endcond //HIDDEN_SYMBOLS
__O uint32_t TX; /*!< [0x0020] SPI Data Transmit Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE1[3];
/// @endcond //HIDDEN_SYMBOLS
__I uint32_t RX; /*!< [0x0030] SPI Data Receive Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE2[11];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t I2SCTL; /*!< [0x0060] I2S Control Register */
__IO uint32_t I2SCLK; /*!< [0x0064] I2S Clock Divider Control Register */
__IO uint32_t I2SSTS; /*!< [0x0068] I2S Status Register */
} SPI_T;
/**
@addtogroup SPI_CONST SPI Bit Field Definition
Constant Definitions for SPI Controller
@{ */
#define SPI_CTL_SPIEN_Pos (0) /*!< SPI_T::CTL: SPIEN Position */
#define SPI_CTL_SPIEN_Msk (0x1ul << SPI_CTL_SPIEN_Pos) /*!< SPI_T::CTL: SPIEN Mask */
#define SPI_CTL_RXNEG_Pos (1) /*!< SPI_T::CTL: RXNEG Position */
#define SPI_CTL_RXNEG_Msk (0x1ul << SPI_CTL_RXNEG_Pos) /*!< SPI_T::CTL: RXNEG Mask */
#define SPI_CTL_TXNEG_Pos (2) /*!< SPI_T::CTL: TXNEG Position */
#define SPI_CTL_TXNEG_Msk (0x1ul << SPI_CTL_TXNEG_Pos) /*!< SPI_T::CTL: TXNEG Mask */
#define SPI_CTL_CLKPOL_Pos (3) /*!< SPI_T::CTL: CLKPOL Position */
#define SPI_CTL_CLKPOL_Msk (0x1ul << SPI_CTL_CLKPOL_Pos) /*!< SPI_T::CTL: CLKPOL Mask */
#define SPI_CTL_SUSPITV_Pos (4) /*!< SPI_T::CTL: SUSPITV Position */
#define SPI_CTL_SUSPITV_Msk (0xful << SPI_CTL_SUSPITV_Pos) /*!< SPI_T::CTL: SUSPITV Mask */
#define SPI_CTL_DWIDTH_Pos (8) /*!< SPI_T::CTL: DWIDTH Position */
#define SPI_CTL_DWIDTH_Msk (0x1ful << SPI_CTL_DWIDTH_Pos) /*!< SPI_T::CTL: DWIDTH Mask */
#define SPI_CTL_LSB_Pos (13) /*!< SPI_T::CTL: LSB Position */
#define SPI_CTL_LSB_Msk (0x1ul << SPI_CTL_LSB_Pos) /*!< SPI_T::CTL: LSB Mask */
#define SPI_CTL_HALFDPX_Pos (14) /*!< SPI_T::CTL: HALFDPX Position */
#define SPI_CTL_HALFDPX_Msk (0x1ul << SPI_CTL_HALFDPX_Pos) /*!< SPI_T::CTL: HALFDPX Mask */
#define SPI_CTL_RXONLY_Pos (15) /*!< SPI_T::CTL: RXONLY Position */
#define SPI_CTL_RXONLY_Msk (0x1ul << SPI_CTL_RXONLY_Pos) /*!< SPI_T::CTL: RXONLY Mask */
#define SPI_CTL_TWOBIT_Pos (16) /*!< SPI_T::CTL: TWOBIT Position */
#define SPI_CTL_TWOBIT_Msk (0x1ul << SPI_CTL_TWOBIT_Pos) /*!< SPI_T::CTL: TWOBIT Mask */
#define SPI_CTL_UNITIEN_Pos (17) /*!< SPI_T::CTL: UNITIEN Position */
#define SPI_CTL_UNITIEN_Msk (0x1ul << SPI_CTL_UNITIEN_Pos) /*!< SPI_T::CTL: UNITIEN Mask */
#define SPI_CTL_SLAVE_Pos (18) /*!< SPI_T::CTL: SLAVE Position */
#define SPI_CTL_SLAVE_Msk (0x1ul << SPI_CTL_SLAVE_Pos) /*!< SPI_T::CTL: SLAVE Mask */
#define SPI_CTL_REORDER_Pos (19) /*!< SPI_T::CTL: REORDER Position */
#define SPI_CTL_REORDER_Msk (0x1ul << SPI_CTL_REORDER_Pos) /*!< SPI_T::CTL: REORDER Mask */
#define SPI_CTL_DATDIR_Pos (20) /*!< SPI_T::CTL: DATDIR Position */
#define SPI_CTL_DATDIR_Msk (0x1ul << SPI_CTL_DATDIR_Pos) /*!< SPI_T::CTL: DATDIR Mask */
#define SPI_CTL_DUALIOEN_Pos (21) /*!< SPI_T::CTL: DUALIOEN Position */
#define SPI_CTL_DUALIOEN_Msk (0x1ul << SPI_CTL_DUALIOEN_Pos) /*!< SPI_T::CTL: DUALIOEN Mask */
#define SPI_CTL_QUADIOEN_Pos (22) /*!< SPI_T::CTL: QUADIOEN Position */
#define SPI_CTL_QUADIOEN_Msk (0x1ul << SPI_CTL_QUADIOEN_Pos) /*!< SPI_T::CTL: QUADIOEN Mask */
#define SPI_CLKDIV_DIVIDER_Pos (0) /*!< SPI_T::CLKDIV: DIVIDER Position */
#define SPI_CLKDIV_DIVIDER_Msk (0x1fful << SPI_CLKDIV_DIVIDER_Pos) /*!< SPI_T::CLKDIV: DIVIDER Mask */
#define SPI_SSCTL_SS_Pos (0) /*!< SPI_T::SSCTL: SS Position */
#define SPI_SSCTL_SS_Msk (0x1ul << SPI_SSCTL_SS_Pos) /*!< SPI_T::SSCTL: SS Mask */
#define SPI_SSCTL_SSACTPOL_Pos (2) /*!< SPI_T::SSCTL: SSACTPOL Position */
#define SPI_SSCTL_SSACTPOL_Msk (0x1ul << SPI_SSCTL_SSACTPOL_Pos) /*!< SPI_T::SSCTL: SSACTPOL Mask */
#define SPI_SSCTL_AUTOSS_Pos (3) /*!< SPI_T::SSCTL: AUTOSS Position */
#define SPI_SSCTL_AUTOSS_Msk (0x1ul << SPI_SSCTL_AUTOSS_Pos) /*!< SPI_T::SSCTL: AUTOSS Mask */
#define SPI_SSCTL_SLV3WIRE_Pos (4) /*!< SPI_T::SSCTL: SLV3WIRE Position */
#define SPI_SSCTL_SLV3WIRE_Msk (0x1ul << SPI_SSCTL_SLV3WIRE_Pos) /*!< SPI_T::SSCTL: SLV3WIRE Mask */
#define SPI_SSCTL_SLVTOIEN_Pos (5) /*!< SPI_T::SSCTL: SLVTOIEN Position */
#define SPI_SSCTL_SLVTOIEN_Msk (0x1ul << SPI_SSCTL_SLVTOIEN_Pos) /*!< SPI_T::SSCTL: SLVTOIEN Mask */
#define SPI_SSCTL_SLVTORST_Pos (6) /*!< SPI_T::SSCTL: SLVTORST Position */
#define SPI_SSCTL_SLVTORST_Msk (0x1ul << SPI_SSCTL_SLVTORST_Pos) /*!< SPI_T::SSCTL: SLVTORST Mask */
#define SPI_SSCTL_SLVBEIEN_Pos (8) /*!< SPI_T::SSCTL: SLVBEIEN Position */
#define SPI_SSCTL_SLVBEIEN_Msk (0x1ul << SPI_SSCTL_SLVBEIEN_Pos) /*!< SPI_T::SSCTL: SLVBEIEN Mask */
#define SPI_SSCTL_SLVURIEN_Pos (9) /*!< SPI_T::SSCTL: SLVURIEN Position */
#define SPI_SSCTL_SLVURIEN_Msk (0x1ul << SPI_SSCTL_SLVURIEN_Pos) /*!< SPI_T::SSCTL: SLVURIEN Mask */
#define SPI_SSCTL_SSACTIEN_Pos (12) /*!< SPI_T::SSCTL: SSACTIEN Position */
#define SPI_SSCTL_SSACTIEN_Msk (0x1ul << SPI_SSCTL_SSACTIEN_Pos) /*!< SPI_T::SSCTL: SSACTIEN Mask */
#define SPI_SSCTL_SSINAIEN_Pos (13) /*!< SPI_T::SSCTL: SSINAIEN Position */
#define SPI_SSCTL_SSINAIEN_Msk (0x1ul << SPI_SSCTL_SSINAIEN_Pos) /*!< SPI_T::SSCTL: SSINAIEN Mask */
#define SPI_SSCTL_SLVTOCNT_Pos (16) /*!< SPI_T::SSCTL: SLVTOCNT Position */
#define SPI_SSCTL_SLVTOCNT_Msk (0xfffful << SPI_SSCTL_SLVTOCNT_Pos) /*!< SPI_T::SSCTL: SLVTOCNT Mask */
#define SPI_PDMACTL_TXPDMAEN_Pos (0) /*!< SPI_T::PDMACTL: TXPDMAEN Position */
#define SPI_PDMACTL_TXPDMAEN_Msk (0x1ul << SPI_PDMACTL_TXPDMAEN_Pos) /*!< SPI_T::PDMACTL: TXPDMAEN Mask */
#define SPI_PDMACTL_RXPDMAEN_Pos (1) /*!< SPI_T::PDMACTL: RXPDMAEN Position */
#define SPI_PDMACTL_RXPDMAEN_Msk (0x1ul << SPI_PDMACTL_RXPDMAEN_Pos) /*!< SPI_T::PDMACTL: RXPDMAEN Mask */
#define SPI_PDMACTL_PDMARST_Pos (2) /*!< SPI_T::PDMACTL: PDMARST Position */
#define SPI_PDMACTL_PDMARST_Msk (0x1ul << SPI_PDMACTL_PDMARST_Pos) /*!< SPI_T::PDMACTL: PDMARST Mask */
#define SPI_FIFOCTL_RXRST_Pos (0) /*!< SPI_T::FIFOCTL: RXRST Position */
#define SPI_FIFOCTL_RXRST_Msk (0x1ul << SPI_FIFOCTL_RXRST_Pos) /*!< SPI_T::FIFOCTL: RXRST Mask */
#define SPI_FIFOCTL_TXRST_Pos (1) /*!< SPI_T::FIFOCTL: TXRST Position */
#define SPI_FIFOCTL_TXRST_Msk (0x1ul << SPI_FIFOCTL_TXRST_Pos) /*!< SPI_T::FIFOCTL: TXRST Mask */
#define SPI_FIFOCTL_RXTHIEN_Pos (2) /*!< SPI_T::FIFOCTL: RXTHIEN Position */
#define SPI_FIFOCTL_RXTHIEN_Msk (0x1ul << SPI_FIFOCTL_RXTHIEN_Pos) /*!< SPI_T::FIFOCTL: RXTHIEN Mask */
#define SPI_FIFOCTL_TXTHIEN_Pos (3) /*!< SPI_T::FIFOCTL: TXTHIEN Position */
#define SPI_FIFOCTL_TXTHIEN_Msk (0x1ul << SPI_FIFOCTL_TXTHIEN_Pos) /*!< SPI_T::FIFOCTL: TXTHIEN Mask */
#define SPI_FIFOCTL_RXTOIEN_Pos (4) /*!< SPI_T::FIFOCTL: RXTOIEN Position */
#define SPI_FIFOCTL_RXTOIEN_Msk (0x1ul << SPI_FIFOCTL_RXTOIEN_Pos) /*!< SPI_T::FIFOCTL: RXTOIEN Mask */
#define SPI_FIFOCTL_RXOVIEN_Pos (5) /*!< SPI_T::FIFOCTL: RXOVIEN Position */
#define SPI_FIFOCTL_RXOVIEN_Msk (0x1ul << SPI_FIFOCTL_RXOVIEN_Pos) /*!< SPI_T::FIFOCTL: RXOVIEN Mask */
#define SPI_FIFOCTL_TXUFPOL_Pos (6) /*!< SPI_T::FIFOCTL: TXUFPOL Position */
#define SPI_FIFOCTL_TXUFPOL_Msk (0x1ul << SPI_FIFOCTL_TXUFPOL_Pos) /*!< SPI_T::FIFOCTL: TXUFPOL Mask */
#define SPI_FIFOCTL_TXUFIEN_Pos (7) /*!< SPI_T::FIFOCTL: TXUFIEN Position */
#define SPI_FIFOCTL_TXUFIEN_Msk (0x1ul << SPI_FIFOCTL_TXUFIEN_Pos) /*!< SPI_T::FIFOCTL: TXUFIEN Mask */
#define SPI_FIFOCTL_RXFBCLR_Pos (8) /*!< SPI_T::FIFOCTL: RXFBCLR Position */
#define SPI_FIFOCTL_RXFBCLR_Msk (0x1ul << SPI_FIFOCTL_RXFBCLR_Pos) /*!< SPI_T::FIFOCTL: RXFBCLR Mask */
#define SPI_FIFOCTL_TXFBCLR_Pos (9) /*!< SPI_T::FIFOCTL: TXFBCLR Position */
#define SPI_FIFOCTL_TXFBCLR_Msk (0x1ul << SPI_FIFOCTL_TXFBCLR_Pos) /*!< SPI_T::FIFOCTL: TXFBCLR Mask */
#define SPI_FIFOCTL_RXTH_Pos (24) /*!< SPI_T::FIFOCTL: RXTH Position */
#define SPI_FIFOCTL_RXTH_Msk (0x7ul << SPI_FIFOCTL_RXTH_Pos) /*!< SPI_T::FIFOCTL: RXTH Mask */
#define SPI_FIFOCTL_TXTH_Pos (28) /*!< SPI_T::FIFOCTL: TXTH Position */
#define SPI_FIFOCTL_TXTH_Msk (0x7ul << SPI_FIFOCTL_TXTH_Pos) /*!< SPI_T::FIFOCTL: TXTH Mask */
#define SPI_STATUS_BUSY_Pos (0) /*!< SPI_T::STATUS: BUSY Position */
#define SPI_STATUS_BUSY_Msk (0x1ul << SPI_STATUS_BUSY_Pos) /*!< SPI_T::STATUS: BUSY Mask */
#define SPI_STATUS_UNITIF_Pos (1) /*!< SPI_T::STATUS: UNITIF Position */
#define SPI_STATUS_UNITIF_Msk (0x1ul << SPI_STATUS_UNITIF_Pos) /*!< SPI_T::STATUS: UNITIF Mask */
#define SPI_STATUS_SSACTIF_Pos (2) /*!< SPI_T::STATUS: SSACTIF Position */
#define SPI_STATUS_SSACTIF_Msk (0x1ul << SPI_STATUS_SSACTIF_Pos) /*!< SPI_T::STATUS: SSACTIF Mask */
#define SPI_STATUS_SSINAIF_Pos (3) /*!< SPI_T::STATUS: SSINAIF Position */
#define SPI_STATUS_SSINAIF_Msk (0x1ul << SPI_STATUS_SSINAIF_Pos) /*!< SPI_T::STATUS: SSINAIF Mask */
#define SPI_STATUS_SSLINE_Pos (4) /*!< SPI_T::STATUS: SSLINE Position */
#define SPI_STATUS_SSLINE_Msk (0x1ul << SPI_STATUS_SSLINE_Pos) /*!< SPI_T::STATUS: SSLINE Mask */
#define SPI_STATUS_SLVTOIF_Pos (5) /*!< SPI_T::STATUS: SLVTOIF Position */
#define SPI_STATUS_SLVTOIF_Msk (0x1ul << SPI_STATUS_SLVTOIF_Pos) /*!< SPI_T::STATUS: SLVTOIF Mask */
#define SPI_STATUS_SLVBEIF_Pos (6) /*!< SPI_T::STATUS: SLVBEIF Position */
#define SPI_STATUS_SLVBEIF_Msk (0x1ul << SPI_STATUS_SLVBEIF_Pos) /*!< SPI_T::STATUS: SLVBEIF Mask */
#define SPI_STATUS_SLVURIF_Pos (7) /*!< SPI_T::STATUS: SLVURIF Position */
#define SPI_STATUS_SLVURIF_Msk (0x1ul << SPI_STATUS_SLVURIF_Pos) /*!< SPI_T::STATUS: SLVURIF Mask */
#define SPI_STATUS_RXEMPTY_Pos (8) /*!< SPI_T::STATUS: RXEMPTY Position */
#define SPI_STATUS_RXEMPTY_Msk (0x1ul << SPI_STATUS_RXEMPTY_Pos) /*!< SPI_T::STATUS: RXEMPTY Mask */
#define SPI_STATUS_RXFULL_Pos (9) /*!< SPI_T::STATUS: RXFULL Position */
#define SPI_STATUS_RXFULL_Msk (0x1ul << SPI_STATUS_RXFULL_Pos) /*!< SPI_T::STATUS: RXFULL Mask */
#define SPI_STATUS_RXTHIF_Pos (10) /*!< SPI_T::STATUS: RXTHIF Position */
#define SPI_STATUS_RXTHIF_Msk (0x1ul << SPI_STATUS_RXTHIF_Pos) /*!< SPI_T::STATUS: RXTHIF Mask */
#define SPI_STATUS_RXOVIF_Pos (11) /*!< SPI_T::STATUS: RXOVIF Position */
#define SPI_STATUS_RXOVIF_Msk (0x1ul << SPI_STATUS_RXOVIF_Pos) /*!< SPI_T::STATUS: RXOVIF Mask */
#define SPI_STATUS_RXTOIF_Pos (12) /*!< SPI_T::STATUS: RXTOIF Position */
#define SPI_STATUS_RXTOIF_Msk (0x1ul << SPI_STATUS_RXTOIF_Pos) /*!< SPI_T::STATUS: RXTOIF Mask */
#define SPI_STATUS_SPIENSTS_Pos (15) /*!< SPI_T::STATUS: SPIENSTS Position */
#define SPI_STATUS_SPIENSTS_Msk (0x1ul << SPI_STATUS_SPIENSTS_Pos) /*!< SPI_T::STATUS: SPIENSTS Mask */
#define SPI_STATUS_TXEMPTY_Pos (16) /*!< SPI_T::STATUS: TXEMPTY Position */
#define SPI_STATUS_TXEMPTY_Msk (0x1ul << SPI_STATUS_TXEMPTY_Pos) /*!< SPI_T::STATUS: TXEMPTY Mask */
#define SPI_STATUS_TXFULL_Pos (17) /*!< SPI_T::STATUS: TXFULL Position */
#define SPI_STATUS_TXFULL_Msk (0x1ul << SPI_STATUS_TXFULL_Pos) /*!< SPI_T::STATUS: TXFULL Mask */
#define SPI_STATUS_TXTHIF_Pos (18) /*!< SPI_T::STATUS: TXTHIF Position */
#define SPI_STATUS_TXTHIF_Msk (0x1ul << SPI_STATUS_TXTHIF_Pos) /*!< SPI_T::STATUS: TXTHIF Mask */
#define SPI_STATUS_TXUFIF_Pos (19) /*!< SPI_T::STATUS: TXUFIF Position */
#define SPI_STATUS_TXUFIF_Msk (0x1ul << SPI_STATUS_TXUFIF_Pos) /*!< SPI_T::STATUS: TXUFIF Mask */
#define SPI_STATUS_TXRXRST_Pos (23) /*!< SPI_T::STATUS: TXRXRST Position */
#define SPI_STATUS_TXRXRST_Msk (0x1ul << SPI_STATUS_TXRXRST_Pos) /*!< SPI_T::STATUS: TXRXRST Mask */
#define SPI_STATUS_RXCNT_Pos (24) /*!< SPI_T::STATUS: RXCNT Position */
#define SPI_STATUS_RXCNT_Msk (0xful << SPI_STATUS_RXCNT_Pos) /*!< SPI_T::STATUS: RXCNT Mask */
#define SPI_STATUS_TXCNT_Pos (28) /*!< SPI_T::STATUS: TXCNT Position */
#define SPI_STATUS_TXCNT_Msk (0xful << SPI_STATUS_TXCNT_Pos) /*!< SPI_T::STATUS: TXCNT Mask */
#define SPI_TX_TX_Pos (0) /*!< SPI_T::TX: TX Position */
#define SPI_TX_TX_Msk (0xfffffffful << SPI_TX_TX_Pos) /*!< SPI_T::TX: TX Mask */
#define SPI_RX_RX_Pos (0) /*!< SPI_T::RX: RX Position */
#define SPI_RX_RX_Msk (0xfffffffful << SPI_RX_RX_Pos) /*!< SPI_T::RX: RX Mask */
#define SPI_I2SCTL_I2SEN_Pos (0) /*!< SPI_T::I2SCTL: I2SEN Position */
#define SPI_I2SCTL_I2SEN_Msk (0x1ul << SPI_I2SCTL_I2SEN_Pos) /*!< SPI_T::I2SCTL: I2SEN Mask */
#define SPI_I2SCTL_TXEN_Pos (1) /*!< SPI_T::I2SCTL: TXEN Position */
#define SPI_I2SCTL_TXEN_Msk (0x1ul << SPI_I2SCTL_TXEN_Pos) /*!< SPI_T::I2SCTL: TXEN Mask */
#define SPI_I2SCTL_RXEN_Pos (2) /*!< SPI_T::I2SCTL: RXEN Position */
#define SPI_I2SCTL_RXEN_Msk (0x1ul << SPI_I2SCTL_RXEN_Pos) /*!< SPI_T::I2SCTL: RXEN Mask */
#define SPI_I2SCTL_MUTE_Pos (3) /*!< SPI_T::I2SCTL: MUTE Position */
#define SPI_I2SCTL_MUTE_Msk (0x1ul << SPI_I2SCTL_MUTE_Pos) /*!< SPI_T::I2SCTL: MUTE Mask */
#define SPI_I2SCTL_WDWIDTH_Pos (4) /*!< SPI_T::I2SCTL: WDWIDTH Position */
#define SPI_I2SCTL_WDWIDTH_Msk (0x3ul << SPI_I2SCTL_WDWIDTH_Pos) /*!< SPI_T::I2SCTL: WDWIDTH Mask */
#define SPI_I2SCTL_MONO_Pos (6) /*!< SPI_T::I2SCTL: MONO Position */
#define SPI_I2SCTL_MONO_Msk (0x1ul << SPI_I2SCTL_MONO_Pos) /*!< SPI_T::I2SCTL: MONO Mask */
#define SPI_I2SCTL_ORDER_Pos (7) /*!< SPI_T::I2SCTL: ORDER Position */
#define SPI_I2SCTL_ORDER_Msk (0x1ul << SPI_I2SCTL_ORDER_Pos) /*!< SPI_T::I2SCTL: ORDER Mask */
#define SPI_I2SCTL_SLAVE_Pos (8) /*!< SPI_T::I2SCTL: SLAVE Position */
#define SPI_I2SCTL_SLAVE_Msk (0x1ul << SPI_I2SCTL_SLAVE_Pos) /*!< SPI_T::I2SCTL: SLAVE Mask */
#define SPI_I2SCTL_MCLKEN_Pos (15) /*!< SPI_T::I2SCTL: MCLKEN Position */
#define SPI_I2SCTL_MCLKEN_Msk (0x1ul << SPI_I2SCTL_MCLKEN_Pos) /*!< SPI_T::I2SCTL: MCLKEN Mask */
#define SPI_I2SCTL_RZCEN_Pos (16) /*!< SPI_T::I2SCTL: RZCEN Position */
#define SPI_I2SCTL_RZCEN_Msk (0x1ul << SPI_I2SCTL_RZCEN_Pos) /*!< SPI_T::I2SCTL: RZCEN Mask */
#define SPI_I2SCTL_LZCEN_Pos (17) /*!< SPI_T::I2SCTL: LZCEN Position */
#define SPI_I2SCTL_LZCEN_Msk (0x1ul << SPI_I2SCTL_LZCEN_Pos) /*!< SPI_T::I2SCTL: LZCEN Mask */
#define SPI_I2SCTL_RXLCH_Pos (23) /*!< SPI_T::I2SCTL: RXLCH Position */
#define SPI_I2SCTL_RXLCH_Msk (0x1ul << SPI_I2SCTL_RXLCH_Pos) /*!< SPI_T::I2SCTL: RXLCH Mask */
#define SPI_I2SCTL_RZCIEN_Pos (24) /*!< SPI_T::I2SCTL: RZCIEN Position */
#define SPI_I2SCTL_RZCIEN_Msk (0x1ul << SPI_I2SCTL_RZCIEN_Pos) /*!< SPI_T::I2SCTL: RZCIEN Mask */
#define SPI_I2SCTL_LZCIEN_Pos (25) /*!< SPI_T::I2SCTL: LZCIEN Position */
#define SPI_I2SCTL_LZCIEN_Msk (0x1ul << SPI_I2SCTL_LZCIEN_Pos) /*!< SPI_T::I2SCTL: LZCIEN Mask */
#define SPI_I2SCTL_FORMAT_Pos (28) /*!< SPI_T::I2SCTL: FORMAT Position */
#define SPI_I2SCTL_FORMAT_Msk (0x3ul << SPI_I2SCTL_FORMAT_Pos) /*!< SPI_T::I2SCTL: FORMAT Mask */
#define SPI_I2SCLK_MCLKDIV_Pos (0) /*!< SPI_T::I2SCLK: MCLKDIV Position */
#define SPI_I2SCLK_MCLKDIV_Msk (0x7ful << SPI_I2SCLK_MCLKDIV_Pos) /*!< SPI_T::I2SCLK: MCLKDIV Mask */
#define SPI_I2SCLK_BCLKDIV_Pos (8) /*!< SPI_T::I2SCLK: BCLKDIV Position */
#define SPI_I2SCLK_BCLKDIV_Msk (0x3fful << SPI_I2SCLK_BCLKDIV_Pos) /*!< SPI_T::I2SCLK: BCLKDIV Mask */
#define SPI_I2SSTS_RIGHT_Pos (4) /*!< SPI_T::I2SSTS: RIGHT Position */
#define SPI_I2SSTS_RIGHT_Msk (0x1ul << SPI_I2SSTS_RIGHT_Pos) /*!< SPI_T::I2SSTS: RIGHT Mask */
#define SPI_I2SSTS_RXEMPTY_Pos (8) /*!< SPI_T::I2SSTS: RXEMPTY Position */
#define SPI_I2SSTS_RXEMPTY_Msk (0x1ul << SPI_I2SSTS_RXEMPTY_Pos) /*!< SPI_T::I2SSTS: RXEMPTY Mask */
#define SPI_I2SSTS_RXFULL_Pos (9) /*!< SPI_T::I2SSTS: RXFULL Position */
#define SPI_I2SSTS_RXFULL_Msk (0x1ul << SPI_I2SSTS_RXFULL_Pos) /*!< SPI_T::I2SSTS: RXFULL Mask */
#define SPI_I2SSTS_RXTHIF_Pos (10) /*!< SPI_T::I2SSTS: RXTHIF Position */
#define SPI_I2SSTS_RXTHIF_Msk (0x1ul << SPI_I2SSTS_RXTHIF_Pos) /*!< SPI_T::I2SSTS: RXTHIF Mask */
#define SPI_I2SSTS_RXOVIF_Pos (11) /*!< SPI_T::I2SSTS: RXOVIF Position */
#define SPI_I2SSTS_RXOVIF_Msk (0x1ul << SPI_I2SSTS_RXOVIF_Pos) /*!< SPI_T::I2SSTS: RXOVIF Mask */
#define SPI_I2SSTS_RXTOIF_Pos (12) /*!< SPI_T::I2SSTS: RXTOIF Position */
#define SPI_I2SSTS_RXTOIF_Msk (0x1ul << SPI_I2SSTS_RXTOIF_Pos) /*!< SPI_T::I2SSTS: RXTOIF Mask */
#define SPI_I2SSTS_I2SENSTS_Pos (15) /*!< SPI_T::I2SSTS: I2SENSTS Position */
#define SPI_I2SSTS_I2SENSTS_Msk (0x1ul << SPI_I2SSTS_I2SENSTS_Pos) /*!< SPI_T::I2SSTS: I2SENSTS Mask */
#define SPI_I2SSTS_TXEMPTY_Pos (16) /*!< SPI_T::I2SSTS: TXEMPTY Position */
#define SPI_I2SSTS_TXEMPTY_Msk (0x1ul << SPI_I2SSTS_TXEMPTY_Pos) /*!< SPI_T::I2SSTS: TXEMPTY Mask */
#define SPI_I2SSTS_TXFULL_Pos (17) /*!< SPI_T::I2SSTS: TXFULL Position */
#define SPI_I2SSTS_TXFULL_Msk (0x1ul << SPI_I2SSTS_TXFULL_Pos) /*!< SPI_T::I2SSTS: TXFULL Mask */
#define SPI_I2SSTS_TXTHIF_Pos (18) /*!< SPI_T::I2SSTS: TXTHIF Position */
#define SPI_I2SSTS_TXTHIF_Msk (0x1ul << SPI_I2SSTS_TXTHIF_Pos) /*!< SPI_T::I2SSTS: TXTHIF Mask */
#define SPI_I2SSTS_TXUFIF_Pos (19) /*!< SPI_T::I2SSTS: TXUFIF Position */
#define SPI_I2SSTS_TXUFIF_Msk (0x1ul << SPI_I2SSTS_TXUFIF_Pos) /*!< SPI_T::I2SSTS: TXUFIF Mask */
#define SPI_I2SSTS_RZCIF_Pos (20) /*!< SPI_T::I2SSTS: RZCIF Position */
#define SPI_I2SSTS_RZCIF_Msk (0x1ul << SPI_I2SSTS_RZCIF_Pos) /*!< SPI_T::I2SSTS: RZCIF Mask */
#define SPI_I2SSTS_LZCIF_Pos (21) /*!< SPI_T::I2SSTS: LZCIF Position */
#define SPI_I2SSTS_LZCIF_Msk (0x1ul << SPI_I2SSTS_LZCIF_Pos) /*!< SPI_T::I2SSTS: LZCIF Mask */
#define SPI_I2SSTS_TXRXRST_Pos (23) /*!< SPI_T::I2SSTS: TXRXRST Position */
#define SPI_I2SSTS_TXRXRST_Msk (0x1ul << SPI_I2SSTS_TXRXRST_Pos) /*!< SPI_T::I2SSTS: TXRXRST Mask */
#define SPI_I2SSTS_RXCNT_Pos (24) /*!< SPI_T::I2SSTS: RXCNT Position */
#define SPI_I2SSTS_RXCNT_Msk (0x7ul << SPI_I2SSTS_RXCNT_Pos) /*!< SPI_T::I2SSTS: RXCNT Mask */
#define SPI_I2SSTS_TXCNT_Pos (28) /*!< SPI_T::I2SSTS: TXCNT Position */
#define SPI_I2SSTS_TXCNT_Msk (0x7ul << SPI_I2SSTS_TXCNT_Pos) /*!< SPI_T::I2SSTS: TXCNT Mask */
/**@}*/ /* SPI_CONST */
/**@}*/ /* end of SPI register group */
/*---------------------- SPIM Serial Interface Controller Master Mode (SPIM) -------------------------*/
/**
@addtogroup SPIM Serial Interface Controller Master Mode (SPIM)
Memory Mapped Structure for SPIM Controller
@{ */
typedef struct {
/**
* @var SPIM_T::CTL0
* Offset: 0x00 Control and Status Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CIPHOFF |Cipher Disable Control
* | | |0 = Cipher function Enabled.
* | | |1 = Cipher function Disabled.
* | | |Note1: If there is not any KEY1(SPIM_KEY1[31:0]) or KEY2(SPIM_KEY2[31:0]) (KEY1 is 0x0000_0000 or KEY2 is 0x0000_0000), the cipher function will be disabled automatically.
* | | |Note2: When CIPHOFF(SPIM_CTL0[0]) is 0, both of KEY1(SPIM_KEY1[31:0]) and KEY2(SPIM_KEY2[31:0]) do not equal to 0x0000_0000 (i.e.
* | | |KEY1 != 0x0000_0000 and KEY2 != 0x0000_0000), cipher encryption/decryption is enabled.
* | | |Note3 : When cipher encryption/decryption is enabled, please set DESELTIM (SPIM_DMMCTL[20:16]) >= 0x10.
* | | |When cipher encryption/decryption is disabled, please set DESELTIM(SPIM_DMMCTL[20:16]) >= 0x8.
* |[2] |BALEN |Balance the AHB Control Time Between Cipher Enable and Disable Control
* | | |When cipher is enabled, the AHB control signal will delay some time caused by the encoding or decoding calculation
* | | |Therefore, if set BALEN to 1, it will make the AHB signal processing time with cipher disabled be equal to that with cipher enabled.
* | | |Note: Only useful when cipher is disabled.
* |[5] |B4ADDREN |4-byte Address Mode Enable Control
* | | |0 = 4-byte address mode is disabled, and 3-byte address mode is enabled.
* | | |1 = 4-byte address mode is enabled.
* | | |Note: Used for DMA write mode, DMA read mode, and DMM mode.
* |[6] |IEN |Interrupt Enable Control
* | | |0 = SPIM Interrupt Disabled.
* | | |1 = SPIM Interrupt Enabled.
* |[7] |IF |Interrupt Flag
* | | |(1) Write Operation :
* | | |0 = No effect.
* | | |1 = Write 1 to clear.
* | | |(2) Read Operation :
* | | |0 = The transfer has not finished yet.
* | | |1 = The transfer has done.
* |[12:8] |DWIDTH |Transmit/Receive Bit Length
* | | |This specifies how many bits are transmitted/received in one transmit/receive transaction.
* | | |0x7 = 8 bits.
* | | |0xF = 16 bits.
* | | |0x17 = 24 bits.
* | | |0x1F = 32 bits.
* | | |Others = Incorrect transfer result.
* | | |Note1: Only used for normal I/O mode.
* | | |Note2: Only 8, 16, 24, and 32 bits are allowed. Other bit length will result in incorrect transfer.
* |[14:13] |BURSTNUM |Transmit/Receive Burst Number
* | | |This field specifies how many transmit/receive transactions should be executed continuously in one transfer.
* | | |0x0 = Only one transmit/receive transaction will be executed in one transfer.
* | | |0x1 = Two successive transmit/receive transactions will be executed in one transfer.
* | | |0x2 = Three successive transmit/receive transactions will be executed in one transfer.
* | | |0x3 = Four successive transmit/receive transactions will be executed in one transfer.
* | | |Note: Only used for normal I/O Mode.
* |[15] |QDIODIR |SPI Interface Direction Select for Quad/Dual Mode
* | | |0 = Interface signals are input.
* | | |1 = Interface signals are output.
* | | |Note: Only used for normal I/O mode.
* |[19:16] |SUSPITV |Suspend Interval
* | | |These four bits provide the configuration of suspend interval between two successive transmit/receive transactions in a transfer
* | | |The default value is 0x00
* | | |When BURSTNUM = 00, setting this field has no effect on transfer
* | | |The desired interval is obtained according to the following equation (from the last falling edge of current SPI clock to the first rising edge of next SPI clock):
* | | | (SUSPITV+2)*period of AHB clock
* | | | 0x0 = 2 AHB clock cycles.
* | | | 0x1 = 3 AHB clock cycles.
* | | | ......
* | | | 0xE = 16 AHB clock cycles.
* | | | 0xF = 17 AHB clock cycles.
* | | | Note: Only used for normal I/O mode.
* |[21:20] |BITMODE |SPI Interface Bit Mode
* | | |0x0 = Standard mode.
* | | |0x1 = Dual mode.
* | | |0x2 = Quad mode.
* | | |0x3 = Reserved.
* | | |Note: Only used for normal I/O mode.
* |[23:22] |OPMODE |SPI Function Operation Mode
* | | |0x0 = Normal I/O mode. (Note1) (Note3)
* | | |0x1 = DMA write mode. (Note2) (Note3)
* | | |0x2 = DMA read mode. (Note3)
* | | |0x3 = Direct Memory Mapping mode (DMM mode) (Default). (Note4)
* | | |Note1 : After user uses Normal I/O mode of SPI flash controller to program the content of external SPI flash, please set CDINVAL(SPIM_CTL1[3]) to 0x1 (Set all cache data to be invalid).
* | | |Note2 : In DMA write mode, hardware will send just one page program command per operation
* | | |Users must take care of cross-page cases
* | | |After user uses DMA write mode of SPI flash controller to program the content of external SPI flash, please set CDINVAL(SPIM_CTL1[3]) to 0x1 (Set all cache data to be invalid).
* | | |Note3 : For external SPI flash with 32 MB, access address range of external SPI flash address is from 0x00000000 to 0x01FFFFFF when user uses Normal I/O mode, DMA write mode, and DMA read mode to write/read external SPI flash data
* | | |Please user check size of used SPI flash component to know access address range of external SPI flash.
* | | |Note4 : For external SPI flash with 32 MB, access address range of external SPI flash address is from 0x08000000 to 0x09FFFFFF when user uses Direct Memory mapping mode (DMM mode) to read external SPI flash data
* | | |Please user check size of used SPI flash component to know access address range of external SPI flash.
* |[31:24] |CMDCODE |Page Program Command Code (Note4)
* | | |(1) 0x02 = Page program (Used for DMA Write mode).
* | | |(2) 0x32 = Quad page program with TYPE_1 program flow (Used for DMA Write mode). (Note3)
* | | |(3) 0x38 = Quad page program with TYPE_2 program flow (Used for DMA Write mode). (Note3)
* | | |(4) 0x40 = Quad page program with TYPE_3 program flow (Used for DMA Write mode). (Note3)
* | | |The Others = Reserved.
* | | |Read Command Code :
* | | |(1) 0x03 = Standard Read (Used for DMA Read/DMM mode).
* | | |(2) 0x0B = Fast Read (Used for DMA Read/DMM mode).
* | | |The fast read command code "0x0B" is similar to command code of standard read "0x03" except it can operate at highest possible frequency
* | | |(Note2)
* | | |(3) 0x3B = Fast Read Dual Output (Used for DMA Read/DMM mode).
* | | |(4) 0xBB = Fast Read Dual I/O (Used for DMA Read/DMM mode).
* | | |The fast read dual I/O command code "0xBB" is similar to command code of fast read dual output "0x3B" but with capability to input the address bits two bits per clock
* | | |(Note2)
* | | |(5) 0xEB = Fast quad read (Used for DMA Read/DMM mode).
* | | |(6) 0xE7 = Word quad read (Used for DMA Read/DMM mode).
* | | |The command code of word quad read "0xE7" is similar to command code of fast quad read "0xEB" except that the lowest address bit must equal to 0 and the number of dummy cycles is less than fast quad read
* | | |(Note2)
* | | |(7) 0x0D = DTR/DDR Fast read (Used for DMA Read/DMM mode).
* | | |(8) 0xBD = DTR/DDR dual read (Used for DMA Read/DMM mode).
* | | |(9) 0xED = DTR/DDR quad read (Used for DMA Read/DMM mode).
* | | |The Others command codes are Reserved.
* | | |The DTR/DDR read commands "0x0D,0xBD,0xED" improves throughput by transferring address and data on both the falling and rising edge of SPI flash clock (SPIM_CLK)
* | | |It is similar to those commands "0x0B, 0xBB, 0xEB" but allows transfer of address and data on rising edge and falling edge of SPI flash output clock
* | | |(Note2)
* | | |Note1: Quad mode of SPI Flash must be enabled first by normal I/O mode before using quad page program/quad read commands.
* | | |Note2: See SPI flash specifications for support items.
* | | |Note3: For TYPE_1, TYPE_2, and TYPE_3 of page program command code, refer to Figure 7.19-3, Figure 7.19-4, and Figure 7.19-5.
* | | |Note4: Please disable "continuous read mode" and "burst wrap mode" before DMA write mode of SPI flash controller is used to program data of external SPI flash
* | | |After user uses DMA write mode of SPI flash controller to program the content of external SPI flash, please set CDINVAL(SPIM_CTL1[3]) to 0x1 (Set all cache data to be invalid).
* @var SPIM_T::CTL1
* Offset: 0x04 Control Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SPIMEN |Go and Busy Status
* | | |(1) Write Operation :
* | | |0 = No effect.
* | | |1 = Start the transfer
* | | |This bit remains set during the transfer and is automatically cleared after transfer finished.
* | | |(2) Read Operation :
* | | |0 = The transfer has done.
* | | |1 = The transfer has not finished yet.
* | | |Note: All registers should be set before writing 1 to the SPIMEN bit
* | | |When a transfer is in progress, you should not write to any register of this peripheral.
* |[1] |CACHEOFF |Cache Memory Function Disable Control
* | | |0 = Cache memory function enable. (Default value)
* | | |1 = Cache memory function disable.
* | | |Note: When CCM mode is enabled, the cache function will be disable by hardware automatically
* | | |When CCM mode is disabled, the cache function can be enable or disable by user.
* |[2] |CCMEN |CCM (Core Coupled Memory) Mode Enable Control
* | | |0 = CCM mode disable. (Default value)
* | | |1 = CCM mode enable.
* | | |Note1: When CCM mode is enabled, the cache function will be disable by hardware automatically
* | | |When CCM mode is disabled, the cache function can be enabled or disabled by user.
* | | |Note2: When CCM mode is disabled, user accesses the core coupled memory by bus master
* | | |In this case, the SPI flash controller will send error response via HRESP bus signal to bus master.
* | | |Note3: When CCM mode needs to be enabled, user sets CCMEN to 1 and needs to read this register to show the current hardware status
* | | |When reading data of CCMEN is 1, MCU can start to read data from CCM memory space or write data to CCM memory space.
* |[3] |CDINVAL |Cache Data Invalid Enable Control
* | | |(1) Write Operation:
* | | |0 = No effect.
* | | |1 = Set all cache data to be invalid. This bit is cleared by hardware automatically.
* | | |(2) Read Operation : No effect
* | | |Note: When SPI flash memory is page erasing or whole flash erasing, please set CDINVAL to 0x1
* | | |After user uses normal I/O mode or DMA write mode of SPI flash controller to program or erase the content of external SPI flash, please set CDINVAL to 0x1.
* |[4] |SS |Slave Select Active Enable Control
* | | |0 = SPIM_SS is in active level.
* | | |1 = SPIM_SS is in inactive level (Default).
* | | |Note: This interface can only drive one device/slave at a given time
* | | |Therefore, the slave selects of the selected device must be set to its active level before starting any read or write transfer
* | | |Functional description of SSACTPOL(SPIM_CTL1[5]) and SS is shown in Table 2.
* |[5] |SSACTPOL |Slave Select Active Level
* | | |It defines the active level of device/slave select signal (SPIM_SS), and we show in Table 2.
* | | |0 = The SPIM_SS slave select signal is active low.
* | | |1 = The SPIM_SS slave select signal is active high.
* |[11:8] |IDLETIME |Idle Time Interval
* | | |In DMM mode, IDLETIME is set to control the minimum idle time between two SPI Flash accesses.
* | | |Minimum idle time = (IDLETIME + 1) * AHB clock cycle time.
* | | |Note1: Only used for DMM mode.
* | | |Note2 : AHB clock cycle time = 1/AHB clock frequency.
* |[31:16] |DIVIDER |Clock Divider Register
* | | |The value in this field is the frequency divider of the AHB clock (HCLK) to generate the serial SPI output clock "SCLK" on the output SPIM_CLK pin
* | | |The desired frequency is obtained according to the following equation:
* | | |Note1: When set DIVIDER to zero, the frequency of SPIM_CLK will be equal to the frequency of HCLK.
* | | |Note2: SCLK is serial SPI output clock.
* | | |Note3: Please check the specification of the used SPI flash component to decide the frequency of SPI flash clock.
* | | |Note4: For DTR/DDR read commands "0x0D, 0xBD, 0xED", the setting values of DIVIDER are only 1,2,4,8,16,32,..., where n = 0,1,2,3,4, ...
* @var SPIM_T::RXCLKDLY
* Offset: 0x0C RX Clock Delay Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |DWDELSEL |SPI flash deselect time interval of DMA write mode
* | | |For DMA write mode only
* | | |This register sets the deselect time interval of SPI flash (i.e.
* | | |time interval of inactive level of SPIM_SS) when SPI flash controller operates on DMA write mode
* | | |(Note1)
* | | |Deselect time interval of DMA write mode = (DWDELSEL + 1) * AHB clock cycle time (Note2).
* | | |Note1: Please user check the used external SPI flash component to set this register value
* | | |In general case, the deselect time interval of SPI flash is greater than 50 ns when SPI flash performs the program operation.
* | | |Note2: AHB clock cycle time = 1/AHB clock frequency.
* |[18:16] |RDDLYSEL |Sampling Clock Delay Selection for Received Data
* | | |For Normal I/O mode, DMA read mode, DMA write mode, and direct memory mapping mode
* | | |Determine the number of inserted delay cycles
* | | |Used to adjust the sampling clock of received data to latch the correct data.
* | | |0x0 : No delay. (Default Value)
* | | |0x1 : Delay 1 SPI flash clock.
* | | |0x2 : Delay 2 SPI flash clocks.
* | | |0x3 : Delay 3 SPI flash clocks.
* | | |...
* | | |0x7 : Delay 7 SPI flash clocks
* | | |Note : We can use manufacturer id or device id of external SPI flash component to determine the correct setting value of RDDLYSEL, and we give example as follows.
* | | |For example, manufacturer id and device id of external SPI flash for some vendor are 0xEF and 0x1234 separately
* | | |Firstly, we set RDDLYSEL to 0x0, and use read manufacturer id/device id command to read the manufacturer id of external SPI flash by using normal I/O mode (the manufacturer id is 0xEF (1110_1111) in this example).
* | | |If manufacturer id which reads from external SPI flash is 0xF7 (1111_0111), it denotes that manufacturer id is shifted the right by 1 bit and most significant bit (MSB) of manufacturer id is assigned to 1
* | | |According to manufacturer id reads from external SPI flash, we need to set RDDLYSEL to 0x1 to receive SPI flash data correctly.
* |[20] |RDEDGE |Sampling Clock Edge Selection for Received Data
* | | |For Normal I/O mode, DMA read mode, DMA write mode, and direct memory mapping mode
* | | |0 : Use SPI input clock rising edge to sample received data. (Default Value)
* | | |1 : Use SPI input clock falling edge to sample received data.
* @var SPIM_T::RX[4]
* Offset: 0x10 ~ 0x1C Data Receive Register 0 ~ 3
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |RXDAT |Data Receive Register
* | | |The Data Receive Registers hold the received data of the last executed transfer.
* | | |Number of valid RX registers is specified in SPIM_CTL0[BURSTNUM]
* | | |If BURSTNUM > 0, received data are held in the most significant RXDAT register first.
* | | |Number of valid-bit is specified in SPIM_CTL0[DWIDTH]
* | | |If DWIDTH is 16, 24, or 32, received data are held in the least significant byte of RXDAT register first.
* | | |In a byte, received data are held in the most significant bit of RXDAT register first.
* | | |Example 1: If SPIM_CTL0[BURSTNUM] = 0x3 and SPIM_CTL1[DWIDTH] = 0x17, received data will be held in the order SPIM_RX3[23:0], SPIM_RX2[23:0], SPIM_RX1[23:0], SPIM_RX0[23:0].
* | | |Example 2: If SPIM_CTL0[BURSTNUM = 0x0 and SPIM_CTL0[DWIDTH] = 0x17, received data will be held in the order SPIM_RX0[7:0], SPIM_RX0[15:8], SPIM_RX0[23:16].
* | | |Example 3: If SPIM_CTL0[BURSTNUM = 0x0 and SPIM_CTL0[DWIDTH] = 0x07, received data will be held in the order SPIM_RX0[7], SPIM_RX0[6], ...,
* | | |SPIM_RX0[0].
* @var SPIM_T::TX[4]
* Offset: 0x20 ~ 0x2C Data Transmit Register 0 ~ 3
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |TXDAT |Data Transmit Register
* | | |The Data Transmit Registers hold the data to be transmitted in next transfer.
* | | |Number of valid TXDAT registers is specified in SPIM_CTL0[BURSTNUM]
* | | |If BURSTNUM > 0, data are transmitted in the most significant TXDAT register first.
* | | |Number of valid-bit is specified in SPIM_CTL0[DWIDTH]
* | | |If DWIDTH is 16, 24, or 32, data are transmitted in the least significant byte of TXDAT register first.
* | | |In a byte, data are transmitted in the most significant bit of TXDAT register first.
* | | |Example 1: If SPIM_CTL0[BURSTNUM] = 0x3 and SPIM_CTL1[DWIDTH] = 0x17, data will be transmitted in the order SPIM_TX3[23:0], SPIM_TX2[23:0], SPIM_TX1[23:0], SPIM_TX0[23:0] in next transfer.
* | | |Example 2: If SPIM_CTL0[BURSTNUM] = 0x0 and SPIM_CTL0[DWIDTH] = 0x17, data will be transmitted in the order SPIM_TX0[7:0], SPIM_TX0[15:8], SPIM_TX0[23:16] in next transfer.
* | | |Example 3: If SPIM_CTL0[BURSTNUM] = 0x0 and SPIM_CTL0[DWIDTH] = 0x07, data will be transmitted in the order SPIM_TX0[7], SPIM_TX0[6], ...,
* | | |SPIM_TX0[0] in next transfer.
* @var SPIM_T::SRAMADDR
* Offset: 0x30 SRAM Memory Address Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |ADDR |SRAM Memory Address
* | | |For DMA Read mode, this is the destination address for DMA transfer.
* | | |For DMA Write mode, this is the source address for DMA transfer.
* | | |Note: This address must be word-aligned.
* @var SPIM_T::DMACNT
* Offset: 0x34 DMA Transfer Byte Count Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[23:0] |DMACNT |DMA Transfer Byte Count Register
* | | |It indicates the transfer length for DMA process.
* | | |Note1: The unit for counting is byte.
* | | |Note2: The number must be the multiple of 4.
* | | |Note3: Please check specification of used SPI flash to know maximum byte length of page program.
* @var SPIM_T::FADDR
* Offset: 0x38 SPI Flash Address Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |ADDR |SPI Flash Address Register
* | | |For DMA Read mode, this is the source address for DMA transfer.
* | | |For DMA Write mode, this is the destination address for DMA transfer.
* | | |Note 1 : This address must be word-aligned.
* | | |Note 2 : For external SPI flash with 32 MB, the value of this SPI flash address register "ADDR" is from 0x00000000 to 0x01FFFFFF when user uses DMA write mode and DMA read mode to write/read external SPI flash data
* | | |Please user check size of used SPI flash component to know access address range of external SPI flash.
* @var SPIM_T::KEY1
* Offset: 0x3C Cipher Key1 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |KEY1 |Cipher Key1 Register
* | | |This is the KEY1 data for cipher function.
* | | |Note1: If there is not any KEY1(SPIM_KEY1[31:0]) or KEY2(SPIM_KEY2[31:0]) (KEY1 is 0x0000_0000 or KEY2 is 0x0000_0000), the cipher function will be disabled automatically.
* | | |Note2: When CIPHOFF(SPIM_CTL0[0]) is 0, both of KEY1(SPIM_KEY1[31:0]) and KEY2(SPIM_KEY2[31:0]) do not equal to 0x0000_0000 (i.e.
* | | |KEY1 != 0x0000_0000 and KEY2 != 0x0000_0000), cipher encryption/decryption is enabled.
* @var SPIM_T::KEY2
* Offset: 0x40 Cipher Key2 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |KEY2 |Cipher Key2 Register
* | | |This is the KEY2 data for cipher function.
* | | |Note1: If there is not any KEY1(SPIM_KEY1[31:0]) or KEY2(SPIM_KEY2[31:0]) (KEY1 is 0x0000_0000 or KEY2 is 0x0000_0000), the cipher function will be disabled automatically.
* | | |Note2: When CIPHOFF(SPIM_CTL0[0]) is 0, both of KEY1(SPIM_KEY1[31:0]) and KEY2(SPIM_KEY2[31:0]) do not equal to 0x0000_0000 (i.e.
* | | |KEY1 != 0x0000_0000 and KEY2 != 0x0000_0000), cipher encryption/decryption is enabled.
* @var SPIM_T::DMMCTL
* Offset: 0x44 Direct Memory Mapping Mode Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:8] |CRMDAT |Mode bits data for Continuous Read Mode (or performance enhance mode) (Default value = 0)
* | | |Only for direct memory mapping mode
* | | |Set the mode bits data for continuous read mode (or performance enhance mode).
* | | |When we set this mode bits currently (Note1) and set CREN(SPIM_DMMCTL[25]), this reduces the command phase by eight clocks and allows the read address to be immediately entered after SPIM_SS asserted to active
* | | |(Note1)
* | | |Note1 : Please check the used SPI flash specification to know the setting value of this mode bits data, and different SPI flash vendor may use different setting values.
* | | |Note2 : CRMDAT needs to used with CREN(SPIM_DMMCTL[25]).
* |[20:16] |DESELTIM |SPI Flash Deselect Time
* | | |Only for direct memory mapping mode
* | | |Set the minimum time width of SPI flash deselect time (i.e.
* | | |Minimum SPIM_SS deselect time), and we show in Figure 7.19-8.
* | | |(1) Cache function disable :
* | | |Minimum time width of SPIM_SS deselect time = (DESELTIM + 1) * AHB clock cycle time.
* | | |(2) Cache function enable :
* | | |Minimum time width of SPIM_SS deselect time = (DESELTIM + 4) * AHB clock cycle time.
* | | |Note1 : AHB clock cycle time = 1/AHB clock frequency.
* | | |Note2 : When cipher encryption/decryption is enabled, please set this register value >= 0x10
* | | |When cipher encryption/decryption is disabled, please set this register value >= 0x8.
* | | |Note3 : Please check the used SPI flash specification to know the setting value of this register, and different SPI flash vendor may use different setting values.
* |[24] |BWEN |16 bytes Burst Wrap Mode Enable Control Register (Default value = 0)
* | | |Only for WINBOND SPI flash, direct memory mapping mode, Cache enable, and read command code "0xEB, and 0xE7"
* | | |0 = Burst Wrap Mode Disable. (Default)
* | | |1 = Burst Wrap Mode Enable.
* | | |In direct memory mapping mode, both of quad read commands "0xEB" and "0xE7" support burst wrap mode for cache application and performance enhance
* | | |For cache application, the burst wrap mode can be used to fill the cache line quickly (In this SPI flash controller, we use cache data line with 16 bytes size)
* | | |For performance enhance with direct memory mapping mode and cache enable, when cache data is miss, the burst wrap mode can let MCU get the required SPI flash data quickly.
* |[25] |CREN |Continuous Read Mode Enable Control
* | | |Only for direct memory mapping mode, read command codes 0xBB, 0xEB, 0xE7, 0x0D, 0xBD, 0xED (Note2)
* | | |0 = Continuous Read Mode Disable. (Default)
* | | |1 = Continuous Read Mode Enable.
* | | |For read operations of SPI flash, commands of fast read quad I/O (0xEB), word read quad I/O (0xE7 in Winbond SPI flash), fast read dual I/O (0xBB), DTR/DDR fast read (0x0D), DTR/DDR fast read dual I/O (0xBD), and DTR/DDR fast read quad I/O (0xED) can further reduce command overhead through setting the "continuous read mode" bits (8 bits) after the input address data.
* | | |Note: When user uses function of continuous read mode and sets USETEN (SPIM_CTL2[16]) to 1, CRMDAT(SPIM_DMMCTL[15:8]) must be set by used SPI flash specifications
* | | |When user uses function of continuous read mode and sets USETEN(SPIM_CTL2[16]) to 0, CRMDAT(SPIM_DMMCTL[15:8]) is set by default value of WINBOND SPI flash.
* |[26] |UACTSCLK |User Sets SPI Flash Active SCLK Time
* | | |Only for direct memory mapping mode, DMA write mode, and DMA read mode
* | | |0 = According to DIVIDER(SPIM_CTL1[31:16]), ACTSCLKT(SPIM_DMMCTL[31:28]) is set by hardware automatically
* | | |(Default value)
* | | |1 = Set ACTSCLKT(SPIM_DMMCTL[31:28]) by user manually.
* | | |When user wants to set ACTSCLKT(SPIM_DMMCTL[31:28]) manually, please set UACTSCLK to 1.
* |[31:28] |ACTSCLKT |SPI Flash Active SCLK Time
* | | |Only for direct memory mapping mode, DMA write mode, and DMA read mode
* | | |This register sets time interval between SPIM SS active edge and the position edge of the first serial SPI output clock, and we show in Figure 7.19-8.
* | | |(1) ACTSCLKT = 0 (function disable) :.
* | | |Time interval = 1 AHB clock cycle time.
* | | |(2) ACTSCLKT != 0 (function enable) :
* | | |Time interval = (ACTSCLKT + 3) * AHB clock cycle time.
* | | |Note1 : AHB clock cycle time = 1/AHB clock frequency.
* | | |Note2 : SCLK is SPI output clock
* | | |Note3 : Please check the used SPI flash specification to know the setting value of this register, and different SPI flash vendor may use different setting values.
* @var SPIM_T::CTL2
* Offset: 0x48 Control Register 2
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[16] |USETEN |User Set Value Enable Control
* | | |Only for direct memory mapping mode and DMA read mode with read commands 0x03,0x0B,0x3B,0xBB,0xEB,0xE7
* | | |0 = Hardware circuit of SPI flash controller will use the following default values of DCNUM(SPIM_CTL2[28:24]) and CRMDAT(SPIM_DMMCTL[15:8]) to configure SPI flash operations automatically.
* | | |Dummy cycle number (DCNUM) :
* | | |Dummy cycle number for read command 0x03 : 0x0
* | | |Dummy cycle number for read command 0x0B : 0x8
* | | |Dummy cycle number for read command 0x3B : 0x8
* | | |Dummy cycle number for read command 0xBB : 0x0
* | | |Dummy cycle number for read command 0xEB : 0x4
* | | |Dummy cycle number for read command 0xE7 : 0x2
* | | |Mode bits data for continuous read mode (CRMDAT) : 0x20
* | | |1 = If DCNUM(SPIM_CTL2[28:24]) and CRMDAT(SPIM_DMMCTL[15:8]) are not set as above default values, user must set USETEN to 0x1, DCNUM(SPIM_CTL2[28:24]) and CRMDAT(SPIM_DMMCTL[15:8]) to configure SPI flash operations manually.
* | | |For DTR/DDR command codes 0x0D, 0xBD, and 0xED, please set USETEN to 0x1.
* |[20] |DTRMPOFF |Mode Phase OFF for DTR/DDR Command Codes 0x0D, 0xBD, and 0xED
* | | |Only for direct memory mapping mode and DMA read mode (Note1)
* | | |0 = mode cycle number (or performance enhance cycle number) does not equal to 0x0 in DTR/DDR read command codes 0x0D, 0xBD, and 0xED.
* | | |1 = mode cycle number (or performance enhance cycle number) equals to 0x0 in DTR/DDR read command codes 0x0D, 0xBD, and 0xED.
* | | |Note1 : Please check the used SPI flash specification to know the mode cycle number (or performance enhance cycle number) for DTR/DDR command codes 0x0D, 0xBD, and 0xED.
* |[28:24] |DCNUM |Dummy Cycle Number
* | | |Only for direct memory mapping mode and DMA read mode (Note1)
* | | |Set number of dummy cycles
* | | |(1) For non-DTR/non-DDR command codes 0x03, 0x0B, 0x3B, 0xBB, 0xEB, and 0xE7 :
* | | |When read command code do not need any dummy cycles (i.e.
* | | |dummy cycle number = 0x0), user must set DCNUM to 0x0.
* | | |For command code 0xBB, if both mode cycle number (or performance enhance cycle number) and dummy cycle number do not equal to 0x0 simultaneously, user must set DCNUM to "mode cycle number + dummy cycle number" by used SPI flash specification.
* | | |For command code 0xBB, if there is only dummy cycle number (i.e.
* | | |dummy cycle number != 0x0 and mode cycle number = 0x0 (or performance enhance cycle number = 0x0)), user set DCNUM to dummy cycle number by used SPI flash specification.
* | | |For command codes 0x0B, 0x3B, 0xEB, and 0xE7, user only set DCNUM to dummy cycle number by used SPI flash specification.
* | | |(2) For DTR/DDR command codes 0x0D, 0xBD, and 0xED :
* | | |user sets DCNUM to dummy cycle number and DTRMPOFF(SPIM_CTL2[20]) by used SPI flash specification.
* | | |Note1 : Number of dummy cycles depends on the frequency of SPI output clock, SPI flash vendor, and read command types
* | | |Please check the used SPI flash specification to know the setting value of this number of dummy cycles.
* @var SPIM_T::VERSION
* Offset: 0x4C SPIM Version Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |MINOR |SPIM Design MINOR Version Number
* | | |Minor version number is dependent on ECO version control
* | | |0x0000: (current Minor Version Number)
* |[23:16] |SUB |SPIM Design SUB Version Number
* | | |Sub version number is relative to key feature
* | | |0x02: (current Sub Version Number)
* |[31:24] |MAJOR |SPIM Design MAJOR Version Number
* | | |Major version number is correlated to Product Line
* | | |0x02: (current Major Version Number)
*/
__IO uint32_t CTL0; /*!< [0x0000] Control and Status Register 0 */
__IO uint32_t CTL1; /*!< [0x0004] Control Register 1 */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE0[1];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t RXCLKDLY; /*!< [0x000c] RX Clock Delay Control Register */
__I uint32_t RX[4]; /*!< [0x0010] ~ [0x001C] Data Receive Register 0~3 */
__IO uint32_t TX[4]; /*!< [0x0020] ~ [0x002C] Data Transmit Register 0~3 */
__IO uint32_t SRAMADDR; /*!< [0x0030] SRAM Memory Address Register */
__IO uint32_t DMACNT; /*!< [0x0034] DMA Transfer Byte Count Register */
__IO uint32_t FADDR; /*!< [0x0038] SPI Flash Address Register */
__O uint32_t KEY1; /*!< [0x003c] Cipher Key1 Register */
__O uint32_t KEY2; /*!< [0x0040] Cipher Key2 Register */
__IO uint32_t DMMCTL; /*!< [0x0044] Direct Memory Mapping Mode Control Register */
__IO uint32_t CTL2; /*!< [0x0048] Control Register 2 */
__I uint32_t VERSION; /*!< [0x004c] SPIM Version Control Register */
} SPIM_T;
/**
@addtogroup SPIM_CONST SPIM Bit Field Definition
Constant Definitions for SPIM Controller
@{ */
#define SPIM_CTL0_CIPHOFF_Pos (0) /*!< SPIM_T::CTL0: CIPHOFF Position */
#define SPIM_CTL0_CIPHOFF_Msk (0x1ul << SPIM_CTL0_CIPHOFF_Pos) /*!< SPIM_T::CTL0: CIPHOFF Mask */
#define SPIM_CTL0_BALEN_Pos (2) /*!< SPIM_T::CTL0: BALEN Position */
#define SPIM_CTL0_BALEN_Msk (0x1ul << SPIM_CTL0_BALEN_Pos) /*!< SPIM_T::CTL0: BALEN Mask */
#define SPIM_CTL0_B4ADDREN_Pos (5) /*!< SPIM_T::CTL0: B4ADDREN Position */
#define SPIM_CTL0_B4ADDREN_Msk (0x1ul << SPIM_CTL0_B4ADDREN_Pos) /*!< SPIM_T::CTL0: B4ADDREN Mask */
#define SPIM_CTL0_IEN_Pos (6) /*!< SPIM_T::CTL0: IEN Position */
#define SPIM_CTL0_IEN_Msk (0x1ul << SPIM_CTL0_IEN_Pos) /*!< SPIM_T::CTL0: IEN Mask */
#define SPIM_CTL0_IF_Pos (7) /*!< SPIM_T::CTL0: IF Position */
#define SPIM_CTL0_IF_Msk (0x1ul << SPIM_CTL0_IF_Pos) /*!< SPIM_T::CTL0: IF Mask */
#define SPIM_CTL0_DWIDTH_Pos (8) /*!< SPIM_T::CTL0: DWIDTH Position */
#define SPIM_CTL0_DWIDTH_Msk (0x1ful << SPIM_CTL0_DWIDTH_Pos) /*!< SPIM_T::CTL0: DWIDTH Mask */
#define SPIM_CTL0_BURSTNUM_Pos (13) /*!< SPIM_T::CTL0: BURSTNUM Position */
#define SPIM_CTL0_BURSTNUM_Msk (0x3ul << SPIM_CTL0_BURSTNUM_Pos) /*!< SPIM_T::CTL0: BURSTNUM Mask */
#define SPIM_CTL0_QDIODIR_Pos (15) /*!< SPIM_T::CTL0: QDIODIR Position */
#define SPIM_CTL0_QDIODIR_Msk (0x1ul << SPIM_CTL0_QDIODIR_Pos) /*!< SPIM_T::CTL0: QDIODIR Mask */
#define SPIM_CTL0_SUSPITV_Pos (16) /*!< SPIM_T::CTL0: SUSPITV Position */
#define SPIM_CTL0_SUSPITV_Msk (0xful << SPIM_CTL0_SUSPITV_Pos) /*!< SPIM_T::CTL0: SUSPITV Mask */
#define SPIM_CTL0_BITMODE_Pos (20) /*!< SPIM_T::CTL0: BITMODE Position */
#define SPIM_CTL0_BITMODE_Msk (0x3ul << SPIM_CTL0_BITMODE_Pos) /*!< SPIM_T::CTL0: BITMODE Mask */
#define SPIM_CTL0_OPMODE_Pos (22) /*!< SPIM_T::CTL0: OPMODE Position */
#define SPIM_CTL0_OPMODE_Msk (0x3ul << SPIM_CTL0_OPMODE_Pos) /*!< SPIM_T::CTL0: OPMODE Mask */
#define SPIM_CTL0_CMDCODE_Pos (24) /*!< SPIM_T::CTL0: CMDCODE Position */
#define SPIM_CTL0_CMDCODE_Msk (0xfful << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_T::CTL0: CMDCODE Mask */
#define SPIM_CTL1_SPIMEN_Pos (0) /*!< SPIM_T::CTL1: SPIMEN Position */
#define SPIM_CTL1_SPIMEN_Msk (0x1ul << SPIM_CTL1_SPIMEN_Pos) /*!< SPIM_T::CTL1: SPIMEN Mask */
#define SPIM_CTL1_CACHEOFF_Pos (1) /*!< SPIM_T::CTL1: CACHEOFF Position */
#define SPIM_CTL1_CACHEOFF_Msk (0x1ul << SPIM_CTL1_CACHEOFF_Pos) /*!< SPIM_T::CTL1: CACHEOFF Mask */
#define SPIM_CTL1_CCMEN_Pos (2) /*!< SPIM_T::CTL1: CCMEN Position */
#define SPIM_CTL1_CCMEN_Msk (0x1ul << SPIM_CTL1_CCMEN_Pos) /*!< SPIM_T::CTL1: CCMEN Mask */
#define SPIM_CTL1_CDINVAL_Pos (3) /*!< SPIM_T::CTL1: CDINVAL Position */
#define SPIM_CTL1_CDINVAL_Msk (0x1ul << SPIM_CTL1_CDINVAL_Pos) /*!< SPIM_T::CTL1: CDINVAL Mask */
#define SPIM_CTL1_SS_Pos (4) /*!< SPIM_T::CTL1: SS Position */
#define SPIM_CTL1_SS_Msk (0x1ul << SPIM_CTL1_SS_Pos) /*!< SPIM_T::CTL1: SS Mask */
#define SPIM_CTL1_SSACTPOL_Pos (5) /*!< SPIM_T::CTL1: SSACTPOL Position */
#define SPIM_CTL1_SSACTPOL_Msk (0x1ul << SPIM_CTL1_SSACTPOL_Pos) /*!< SPIM_T::CTL1: SSACTPOL Mask */
#define SPIM_CTL1_IDLETIME_Pos (8) /*!< SPIM_T::CTL1: IDLETIME Position */
#define SPIM_CTL1_IDLETIME_Msk (0xful << SPIM_CTL1_IDLETIME_Pos) /*!< SPIM_T::CTL1: IDLETIME Mask */
#define SPIM_CTL1_DIVIDER_Pos (16) /*!< SPIM_T::CTL1: DIVIDER Position */
#define SPIM_CTL1_DIVIDER_Msk (0xfffful << SPIM_CTL1_DIVIDER_Pos) /*!< SPIM_T::CTL1: DIVIDER Mask */
#define SPIM_RXCLKDLY_DWDELSEL_Pos (0) /*!< SPIM_T::RXCLKDLY: DWDELSEL Position */
#define SPIM_RXCLKDLY_DWDELSEL_Msk (0xfful << SPIM_RXCLKDLY_DWDELSEL_Pos) /*!< SPIM_T::RXCLKDLY: DWDELSEL Mask */
#define SPIM_RXCLKDLY_RDDLYSEL_Pos (16) /*!< SPIM_T::RXCLKDLY: RDDLYSEL Position */
#define SPIM_RXCLKDLY_RDDLYSEL_Msk (0x7ul << SPIM_RXCLKDLY_RDDLYSEL_Pos) /*!< SPIM_T::RXCLKDLY: RDDLYSEL Mask */
#define SPIM_RXCLKDLY_RDEDGE_Pos (20) /*!< SPIM_T::RXCLKDLY: RDEDGE Position */
#define SPIM_RXCLKDLY_RDEDGE_Msk (0x1ul << SPIM_RXCLKDLY_RDEDGE_Pos) /*!< SPIM_T::RXCLKDLY: RDEDGE Mask */
#define SPIM_RX_RXDAT_Pos (0) /*!< SPIM_T::RX[4]: RXDAT Position */
#define SPIM_RX_RXDAT_Msk (0xfffffffful << SPIM_RX_RXDAT_Pos) /*!< SPIM_T::RX[4]: RXDAT Mask */
#define SPIM_TX_TXDAT_Pos (0) /*!< SPIM_T::TX[4]: TXDAT Position */
#define SPIM_TX_TXDAT_Msk (0xfffffffful << SPIM_TX_TXDAT_Pos) /*!< SPIM_T::TX[4]: TXDAT Mask */
#define SPIM_SRAMADDR_ADDR_Pos (0) /*!< SPIM_T::SRAMADDR: ADDR Position */
#define SPIM_SRAMADDR_ADDR_Msk (0xfffffffful << SPIM_SRAMADDR_ADDR_Pos) /*!< SPIM_T::SRAMADDR: ADDR Mask */
#define SPIM_DMACNT_DMACNT_Pos (0) /*!< SPIM_T::DMACNT: DMACNT Position */
#define SPIM_DMACNT_DMACNT_Msk (0xfffffful << SPIM_DMACNT_DMACNT_Pos) /*!< SPIM_T::DMACNT: DMACNT Mask */
#define SPIM_FADDR_ADDR_Pos (0) /*!< SPIM_T::FADDR: ADDR Position */
#define SPIM_FADDR_ADDR_Msk (0xfffffffful << SPIM_FADDR_ADDR_Pos) /*!< SPIM_T::FADDR: ADDR Mask */
#define SPIM_KEY1_KEY1_Pos (0) /*!< SPIM_T::KEY1: KEY1 Position */
#define SPIM_KEY1_KEY1_Msk (0xfffffffful << SPIM_KEY1_KEY1_Pos) /*!< SPIM_T::KEY1: KEY1 Mask */
#define SPIM_KEY2_KEY2_Pos (0) /*!< SPIM_T::KEY2: KEY2 Position */
#define SPIM_KEY2_KEY2_Msk (0xfffffffful << SPIM_KEY2_KEY2_Pos) /*!< SPIM_T::KEY2: KEY2 Mask */
#define SPIM_DMMCTL_CRMDAT_Pos (8) /*!< SPIM_T::DMMCTL: CRMDAT Position */
#define SPIM_DMMCTL_CRMDAT_Msk (0xfful << SPIM_DMMCTL_CRMDAT_Pos) /*!< SPIM_T::DMMCTL: CRMDAT Mask */
#define SPIM_DMMCTL_DESELTIM_Pos (16) /*!< SPIM_T::DMMCTL: DESELTIM Position */
#define SPIM_DMMCTL_DESELTIM_Msk (0x1ful << SPIM_DMMCTL_DESELTIM_Pos) /*!< SPIM_T::DMMCTL: DESELTIM Mask */
#define SPIM_DMMCTL_BWEN_Pos (24) /*!< SPIM_T::DMMCTL: BWEN Position */
#define SPIM_DMMCTL_BWEN_Msk (0x1ul << SPIM_DMMCTL_BWEN_Pos) /*!< SPIM_T::DMMCTL: BWEN Mask */
#define SPIM_DMMCTL_CREN_Pos (25) /*!< SPIM_T::DMMCTL: CREN Position */
#define SPIM_DMMCTL_CREN_Msk (0x1ul << SPIM_DMMCTL_CREN_Pos) /*!< SPIM_T::DMMCTL: CREN Mask */
#define SPIM_DMMCTL_UACTSCLK_Pos (26) /*!< SPIM_T::DMMCTL: UACTSCLK Position */
#define SPIM_DMMCTL_UACTSCLK_Msk (0x1ul << SPIM_DMMCTL_UACTSCLK_Pos) /*!< SPIM_T::DMMCTL: UACTSCLK Mask */
#define SPIM_DMMCTL_ACTSCLKT_Pos (28) /*!< SPIM_T::DMMCTL: ACTSCLKT Position */
#define SPIM_DMMCTL_ACTSCLKT_Msk (0xful << SPIM_DMMCTL_ACTSCLKT_Pos) /*!< SPIM_T::DMMCTL: ACTSCLKT Mask */
#define SPIM_CTL2_USETEN_Pos (16) /*!< SPIM_T::CTL2: USETEN Position */
#define SPIM_CTL2_USETEN_Msk (0x1ul << SPIM_CTL2_USETEN_Pos) /*!< SPIM_T::CTL2: USETEN Mask */
#define SPIM_CTL2_DTRMPOFF_Pos (20) /*!< SPIM_T::CTL2: DTRMPOFF Position */
#define SPIM_CTL2_DTRMPOFF_Msk (0x1ul << SPIM_CTL2_DTRMPOFF_Pos) /*!< SPIM_T::CTL2: DTRMPOFF Mask */
#define SPIM_CTL2_DCNUM_Pos (24) /*!< SPIM_T::CTL2: DCNUM Position */
#define SPIM_CTL2_DCNUM_Msk (0x1ful << SPIM_CTL2_DCNUM_Pos) /*!< SPIM_T::CTL2: DCNUM Mask */
#define SPIM_VERSION_MINOR_Pos (0) /*!< SPIM_T::VERSION: MINOR Position */
#define SPIM_VERSION_MINOR_Msk (0xfffful << SPIM_VERSION_MINOR_Pos) /*!< SPIM_T::VERSION: MINOR Mask */
#define SPIM_VERSION_SUB_Pos (16) /*!< SPIM_T::VERSION: SUB Position */
#define SPIM_VERSION_SUB_Msk (0xfful << SPIM_VERSION_SUB_Pos) /*!< SPIM_T::VERSION: SUB Mask */
#define SPIM_VERSION_MAJOR_Pos (24) /*!< SPIM_T::VERSION: MAJOR Position */
#define SPIM_VERSION_MAJOR_Msk (0xfful << SPIM_VERSION_MAJOR_Pos) /*!< SPIM_T::VERSION: MAJOR Mask */
/**@}*/ /* SPIM_CONST */
/**@}*/ /* end of SPIM register group */
/*---------------------- Inter-IC Bus Controller -------------------------*/
/**
@addtogroup I2C Inter-IC Bus Controller(I2C)
Memory Mapped Structure for I2C Controller
@{ */
typedef struct {
/**
* @var I2C_T::CTL0
* Offset: 0x00 I2C Control Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[2] |AA |Assert Acknowledge Control
* | | |When AA =1 prior to address or data is received, an acknowledged (low level to SDA) will be returned during the acknowledge clock pulse on the SCL line when 1.) A slave is acknowledging the address sent from master, 2.) The receiver devices are acknowledging the data sent by transmitter
* | | |When AA=0 prior to address or data received, a Not acknowledged (high level to SDA) will be returned during the acknowledge clock pulse on the SCL line
* |[3] |SI |I2C Interrupt Flag
* | | |When a new I2C state is present in the I2C_STATUS register, the SI flag is set by hardware
* | | |If bit INTEN (I2C_CTL [7]) is set, the I2C interrupt is requested
* | | |SI must be cleared by software
* | | |Clear SI by writing 1 to this bit.
* | | |For ACKMEN is set in slave read mode, the SI flag is set in 8th clock period for user to confirm the acknowledge bit and 9th clock period for user to read the data in the data buffer.
* |[4] |STO |I2C STOP Control
* | | |In Master mode, setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected
* | | |This bit will be cleared by hardware automatically.
* |[5] |STA |I2C START Control
* | | |Setting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free.
* |[6] |I2CEN |I2C Controller Enable Bit
* | | |Set to enable I2C serial function controller
* | | |When I2CEN=1 the I2C serial function enable
* | | |The multi-function pin function must set to SDA, and SCL of I2C function first.
* | | |0 = I2C controller Disabled.
* | | |1 = I2C controller Enabled.
* |[7] |INTEN |Enable Interrupt
* | | |0 = I2C interrupt Disabled.
* | | |1 = I2C interrupt Enabled.
* @var I2C_T::ADDR0
* Offset: 0x04 I2C Slave Address Register0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |GC |General Call Function
* | | |0 = General Call Function Disabled.
* | | |1 = General Call Function Enabled.
* |[10:1] |ADDR |I2C Address
* | | |The content of this register is irrelevant when I2C is in Master mode
* | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address
* | | |The I2C hardware will react if either of the address is matched.
* | | |Note: When software set 10'h000, the address can not be used.
* @var I2C_T::DAT
* Offset: 0x08 I2C Data Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |DAT |I2C Data
* | | |Bit [7:0] is located with the 8-bit transferred/received data of I2C serial port.
* @var I2C_T::STATUS0
* Offset: 0x0C I2C Status Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |STATUS |I2C Status
* | | |The three least significant bits are always 0
* | | |The five most significant bits contain the status code
* | | |There are 28 possible status codes
* | | |When the content of I2C_STATUS is F8H, no serial interrupt is requested
* | | |Others I2C_STATUS values correspond to defined I2C states
* | | |When each of these states is entered, a status interrupt is requested (SI = 1)
* | | |A valid status code is present in I2C_STATUS one cycle after SI is set by hardware and is still present one cycle after SI has been reset by software
* | | |In addition, states 00H stands for a Bus Error
* | | |A Bus Error occurs when a START or STOP condition is present at an illegal position in the formation frame
* | | |Example of illegal position are during the serial transfer of an address byte, a data byte or an acknowledge bit.
* @var I2C_T::CLKDIV
* Offset: 0x10 I2C Clock Divided Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[9:0] |DIVIDER |I2C Clock Divided
* | | |Indicates the I2C clock rate: Data Baud Rate of I2C = (system clock) / (4x (I2C_CLKDIV+1)).
* | | |Note: The minimum value of I2C_CLKDIV is 4.
* @var I2C_T::TOCTL
* Offset: 0x14 I2C Time-out Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |TOIF |Time-out Flag
* | | |This bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1.
* | | |Note: Software can write 1 to clear this bit.
* |[1] |TOCDIV4 |Time-out Counter Input Clock Divided by 4
* | | |When Enabled, The time-out period is extend 4 times.
* | | |0 = Time-out period is extend 4 times Disabled.
* | | |1 = Time-out period is extend 4 times Enabled.
* |[2] |TOCEN |Time-out Counter Enable Bit
* | | |When Enabled, the 14-bit time-out counter will start counting when SI is clear
* | | |Setting flag SI to '1' will reset counter and re-start up counting after SI is cleared.
* | | |0 = Time-out counter Disabled.
* | | |1 = Time-out counter Enabled.
* @var I2C_T::ADDR1
* Offset: 0x18 I2C Slave Address Register1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |GC |General Call Function
* | | |0 = General Call Function Disabled.
* | | |1 = General Call Function Enabled.
* |[10:1] |ADDR |I2C Address
* | | |The content of this register is irrelevant when I2C is in Master mode
* | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address
* | | |The I2C hardware will react if either of the address is matched.
* | | |Note: When software set 10'h000, the address can not be used.
* @var I2C_T::ADDR2
* Offset: 0x1C I2C Slave Address Register2
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |GC |General Call Function
* | | |0 = General Call Function Disabled.
* | | |1 = General Call Function Enabled.
* |[10:1] |ADDR |I2C Address
* | | |The content of this register is irrelevant when I2C is in Master mode
* | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address
* | | |The I2C hardware will react if either of the address is matched.
* | | |Note: When software set 10'h000, the address can not be used.
* @var I2C_T::ADDR3
* Offset: 0x20 I2C Slave Address Register3
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |GC |General Call Function
* | | |0 = General Call Function Disabled.
* | | |1 = General Call Function Enabled.
* |[10:1] |ADDR |I2C Address
* | | |The content of this register is irrelevant when I2C is in Master mode
* | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address
* | | |The I2C hardware will react if either of the address is matched.
* | | |Note: When software set 10'h000, the address can not be used.
* @var I2C_T::ADDRMSK0
* Offset: 0x24 I2C Slave Address Mask Register0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[10:1] |ADDRMSK |I2C Address Mask
* | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
* | | |1 = Mask Enabled (the received corresponding address bit is don't care.).
* | | |I2C bus controllers support multiple address recognition with four address mask register
* | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care
* | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
* | | |Note: The wake-up function can not use address mask.
* @var I2C_T::ADDRMSK1
* Offset: 0x28 I2C Slave Address Mask Register1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[10:1] |ADDRMSK |I2C Address Mask
* | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
* | | |1 = Mask Enabled (the received corresponding address bit is don't care.).
* | | |I2C bus controllers support multiple address recognition with four address mask register
* | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care
* | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
* | | |Note: The wake-up function can not use address mask.
* @var I2C_T::ADDRMSK2
* Offset: 0x2C I2C Slave Address Mask Register2
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[10:1] |ADDRMSK |I2C Address Mask
* | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
* | | |1 = Mask Enabled (the received corresponding address bit is don't care.).
* | | |I2C bus controllers support multiple address recognition with four address mask register
* | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care
* | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
* | | |Note: The wake-up function can not use address mask.
* @var I2C_T::ADDRMSK3
* Offset: 0x30 I2C Slave Address Mask Register3
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[10:1] |ADDRMSK |I2C Address Mask
* | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
* | | |1 = Mask Enabled (the received corresponding address bit is don't care.).
* | | |I2C bus controllers support multiple address recognition with four address mask register
* | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care
* | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
* | | |Note: The wake-up function can not use address mask.
* @var I2C_T::WKCTL
* Offset: 0x3C I2C Wake-up Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |WKEN |I2C Wake-up Enable Bit
* | | |0 = I2C wake-up function Disabled.
* | | |1 = I2C wake-up function Enabled.
* |[7] |NHDBUSEN |I2C No Hold BUS Enable Bit
* | | |0 = I2C hold bus after wake-up.
* | | |1 = I2C don't hold bus after wake-up.
* | | |Note: I2C controller could response when WKIF event is not clear, it may cause error data transmitted or received
* | | |If data transmitted or received when WKIF event is not clear, user must reset I2C controller and execute the original operation again.
* @var I2C_T::WKSTS
* Offset: 0x40 I2C Wake-up Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |WKIF |I2C Wake-up Flag
* | | |When chip is woken up from Power-down mode by I2C, this bit is set to 1
* | | |Software can write 1 to clear this bit.
* |[1] |WKAKDONE |Wakeup Address Frame Acknowledge Bit Done
* | | |0 = The ACK bit cycle of address match frame isn't done.
* | | |1 = The ACK bit cycle of address match frame is done in power-down.
* | | |Note: This bit can't release WKIF. Software can write 1 to clear this bit.
* |[2] |WRSTSWK |Read/Write Status Bit in Address Wakeup Frame
* | | |0 = Write command be record on the address match wakeup frame.
* | | |1 = Read command be record on the address match wakeup frame.
* | | |Note: This bit will be cleared when software can write 1 to WKAKDONE bit.
* @var I2C_T::CTL1
* Offset: 0x44 I2C Control Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |TXPDMAEN |PDMA Transmit Channel Available
* | | |0 = Transmit PDMA function disable.
* | | |1 = Transmit PDMA function enable.
* |[1] |RXPDMAEN |PDMA Receive Channel Available
* | | |0 = Receive PDMA function disable.
* | | |1 = Receive PDMA function enable.
* |[2] |PDMARST |PDMA Reset
* | | |0 = No effect.
* | | |1 = Reset the I2C request to PDMA.
* |[8] |PDMASTR |PDMA Stretch Bit
* | | |0 = I2C send STOP automatically after PDMA transfer done. (only master TX)
* | | |1 = I2C SCL bus is stretched by hardware after PDMA transfer done if the SI is not cleared
* | | |(only master TX)
* |[9] |ADDR10EN |Address 10-bit Function Enable
* | | |0 = Address match 10-bit function is disabled.
* | | |1 = Address match 10-bit function is enabled.
* @var I2C_T::STATUS1
* Offset: 0x48 I2C Status Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ADMAT0 |I2C Address 0 Match Status Register
* | | |When address 0 is matched, hardware will inform which address used
* | | |This bit will set to 1, and software can write 1 to clear this bit.
* |[1] |ADMAT1 |I2C Address 1 Match Status Register
* | | |When address 1 is matched, hardware will inform which address used
* | | |This bit will set to 1, and software can write 1 to clear this bit.
* |[2] |ADMAT2 |I2C Address 2 Match Status Register
* | | |When address 2 is matched, hardware will inform which address used
* | | |This bit will set to 1, and software can write 1 to clear this bit.
* |[3] |ADMAT3 |I2C Address 3 Match Status Register
* | | |When address 3 is matched, hardware will inform which address used
* | | |This bit will set to 1, and software can write 1 to clear this bit.
* |[8] |ONBUSY |On Bus Busy
* | | |Indicates that a communication is in progress on the bus
* | | |It is set by hardware when a START condition is detected
* | | |It is cleared by hardware when a STOP condition is detected.
* | | |0 = The bus is IDLE (both SCLK and SDA High).
* | | |1 = The bus is busy.
* | | |Note:This bit is read only.
* @var I2C_T::TMCTL
* Offset: 0x4C I2C Timing Configure Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[8:0] |STCTL |Setup Time Configure Control Register
* | | |This field is used to generate a delay timing between SDA falling edge and SCL rising edge in transmission mode.
* | | |The delay setup time is numbers of peripheral clock = STCTL x PCLK.
* | | |Note: Setup time setting should not make SCL output less than three PCLKs.
* |[24:16] |HTCTL |Hold Time Configure Control Register
* | | |This field is used to generate the delay timing between SCL falling edge and SDA rising edge in transmission mode.
* | | |The delay hold time is numbers of peripheral clock = HTCTL x PCLK.
* @var I2C_T::BUSCTL
* Offset: 0x50 I2C Bus Management Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ACKMEN |Acknowledge Control by Manual
* | | |In order to allow ACK control in slave reception including the command and data, slave byte control mode must be enabled by setting the ACKMEN bit.
* | | |0 = Slave byte control Disabled.
* | | |1 = Slave byte control Enabled
* | | |The 9th bit can response the ACK or NACK according the received data by user
* | | |When the byte is received, stretching the SCLK signal low between the 8th and 9th SCLK pulse.
* | | |Note: If the BMDEN=1 and this bit is enabled, the information of I2C_STATUS will be fixed as 0xF0 in slave receive condition.
* |[1] |PECEN |Packet Error Checking Calculation Enable Bit
* | | |0 = Packet Error Checking Calculation Disabled.
* | | |1 = Packet Error Checking Calculation Enabled.
* | | |Note: When I2C enter power down mode, the bit should be enabled after wake-up if needed PEC calculation.
* |[2] |BMDEN |Bus Management Device Default Address Enable Bit
* | | |0 = Device default address Disable
* | | |When the address 0'b1100001x coming and the both of BMDEN and ACKMEN are enabled, the device responses NACKed
* | | |1 = Device default address Enabled
* | | |When the address 0'b1100001x coming and the both of BMDEN and ACKMEN are enabled, the device responses ACKed.
* |[3] |BMHEN |Bus Management Host Enable Bit
* | | |0 = Host function Disabled.
* | | |1 = Host function Enabled.
* |[4] |ALERTEN |Bus Management Alert Enable Bit
* | | |Device Mode (BMHEN=0).
* | | |0 = Release the BM_ALERT pin high and Alert Response Header disabled: 0001100x followed by NACK if both of BMDEN and ACKMEN are enabled.
* | | |1 = Drive BM_ALERT pin low and Alert Response Address Header enables: 0001100x followed by ACK if both of BMDEN and ACKMEN are enabled.
* | | |Host Mode (BMHEN=1).
* | | |0 = BM_ALERT pin not supported.
* | | |1 = BM_ALERT pin supported.
* |[5] |SCTLOSTS |Suspend/Control Data Output Status
* | | |0 = The output of SUSCON pin is low.
* | | |1 = The output of SUSCON pin is high.
* |[6] |SCTLOEN |Suspend or Control Pin Output Enable Bit
* | | |0 = The SUSCON pin in input.
* | | |1 = The output enable is active on the SUSCON pin.
* |[7] |BUSEN |BUS Enable Bit
* | | |0 = The system management function is Disabled.
* | | |1 = The system management function is Enable.
* | | |Note: When the bit is enabled, the internal 14-bit counter is used to calculate the time out event of clock low condition.
* |[8] |PECTXEN |Packet Error Checking Byte Transmission/Reception
* | | |0 = No PEC transfer.
* | | |1 = PEC transmission is requested.
* | | |Note: This bit has no effect in slave mode when ACKMEN=0.
* |[9] |TIDLE |Timer Check in Idle State
* | | |The BUSTOUT is used to calculate the time-out of clock low in bus active and the idle period in bus Idle
* | | |This bit is used to define which condition is enabled.
* | | |0 = The BUSTOUT is used to calculate the clock low period in bus active.
* | | |1 = The BUSTOUT is used to calculate the IDLE period in bus Idle.
* | | |Note: The BUSY (I2C_BUSSTS[0]) indicate the current bus state.
* |[10] |PECCLR |PEC Clear at Repeat Start
* | | |The calculation of PEC starts when PECEN is set to 1 and it is clear when the STA or STO bit is detected
* | | |This PECCLR bit is used to enable the condition of REPEAT START can clear the PEC calculation.
* | | |0 = The PEC calculation is cleared by "Repeat Start" function is Disabled.
* | | |1 = The PEC calculation is cleared by "Repeat Start"" function is Enabled.
* |[11] |ACKM9SI |Acknowledge Manual Enable Extra SI Interrupt
* | | |0 = There is no SI interrupt in the 9th clock cycle when the BUSEN=1 and ACKMEN=1.
* | | |1 = There is SI interrupt in the 9th clock cycle when the BUSEN=1 and ACKMEN=1.
* |[12] |BCDIEN |Packet Error Checking Byte Count Done Interrupt Enable Bit
* | | |0 = Indicates the byte count done interrupt is Disabled.
* | | |1 = Indicates the byte count done interrupt is Enabled.
* | | |Note: This bit is used in PECEN=1.
* |[13] |PECDIEN |Packet Error Checking Byte Transfer Done Interrupt Enable Bit
* | | |0 = Indicates the PEC transfer done interrupt is Disabled.
* | | |1 = Indicates the PEC transfer done interrupt is Enabled.
* | | |Note: This bit is used in PECEN=1.
* @var I2C_T::BUSTCTL
* Offset: 0x54 I2C Bus Management Timer Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |BUSTOEN |Bus Time Out Enable Bit
* | | |0 = Indicates the bus clock low time-out detection is Disabled.
* | | |1 = Indicates the bus clock low time-out detection is Enabled (bus clock is low for more than TTime-out (in BIDLE=0) or high more than TTime-out(in BIDLE =1)
* |[1] |CLKTOEN |Cumulative Clock Low Time Out Enable Bit
* | | |0 = Indicates the cumulative clock low time-out detection is Disabled.
* | | |1 = Indicates the cumulative clock low time-out detection is Enabled.
* | | |For Master, it calculates the period from START to ACK
* | | |For Slave, it calculates the period from START to STOP
* |[2] |BUSTOIEN |Time-out Interrupt Enable Bit
* | | |BUSY =1.
* | | |0 = Indicates the SCLK low time-out interrupt is Disabled.
* | | |1 = Indicates the SCLK low time-out interrupt is Enabled.
* | | |BUSY =0.
* | | |0 = Indicates the bus IDLE time-out interrupt is Disabled.
* | | |1 = Indicates the bus IDLE time-out interrupt is Enabled.
* |[3] |CLKTOIEN |Extended Clock Time Out Interrupt Enable Bit
* | | |0 = Indicates the clock time out interrupt is Disabled.
* | | |1 = Indicates the clock time out interrupt is Enabled.
* |[4] |TORSTEN |Time Out Reset Enable Bit
* | | |0 = Indicates the I2C state machine reset is Disable.
* | | |1 = Indicates the I2C state machine reset is Enable. (The clock and data bus will be released to high)
* @var I2C_T::BUSSTS
* Offset: 0x58 I2C Bus Management Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |BUSY |Bus Busy
* | | |Indicates that a communication is in progress on the bus
* | | |It is set by hardware when a START condition is detected
* | | |It is cleared by hardware when a STOP condition is detected
* | | |0 = The bus is IDLE (both SCLK and SDA High).
* | | |1 = The bus is busy.
* |[1] |BCDONE |Byte Count Transmission/Receive Done
* | | |0 = Indicates the byte count transmission/ receive is not finished when the PECEN is set.
* | | |1 = Indicates the byte count transmission/ receive is finished when the PECEN is set.
* | | |Note: Software can write 1 to clear this bit.
* |[2] |PECERR |PEC Error in Reception
* | | |0 = Indicates the PEC value equal the received PEC data packet.
* | | |1 = Indicates the PEC value doesn't match the receive PEC data packet.
* | | |Note: Software can write 1 to clear this bit.
* |[3] |ALERT |SMBus Alert Status
* | | |Device Mode (BMHEN =0).
* | | |0 = Indicates SMBALERT pin state is low.
* | | |1 = Indicates SMBALERT pin state is high.
* | | |Host Mode (BMHEN =1).
* | | |0 = No SMBALERT event.
* | | |1 = Indicates there is SMBALERT event (falling edge) is detected in SMALERT pin when the BMHEN = 1 (SMBus host configuration) and the ALERTEN = 1.
* | | |Note:
* | | |1. The SMBALERT pin is an open-drain pin, the pull-high resistor is must in the system
* | | |2. Software can write 1 to clear this bit.
* |[4] |SCTLDIN |Bus Suspend or Control Signal Input Status
* | | |0 = The input status of SUSCON pin is 0.
* | | |1 = The input status of SUSCON pin is 1.
* |[5] |BUSTO |Bus Time-out Status
* | | |0 = Indicates that there is no any time-out or external clock time-out.
* | | |1 = Indicates that a time-out or external clock time-out occurred.
* | | |In bus busy, the bit indicates the total clock low time-out event occurred otherwise, it indicates the bus idle time-out event occurred.
* | | |Note: Software can write 1 to clear this bit.
* |[6] |CLKTO |Clock Low Cumulate Time-out Status
* | | |0 = Indicates that the cumulative clock low is no any time-out.
* | | |1 = Indicates that the cumulative clock low time-out occurred.
* | | |Note: Software can write 1 to clear this bit.
* |[7] |PECDONE |PEC Byte Transmission/Receive Done
* | | |0 = Indicates the PEC transmission/ receive is not finished when the PECEN is set.
* | | |1 = Indicates the PEC transmission/ receive is finished when the PECEN is set.
* | | |Note: Software can write 1 to clear this bit.
* @var I2C_T::PKTSIZE
* Offset: 0x5C I2C Packet Error Checking Byte Number Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[8:0] |PLDSIZE |Transfer Byte Number
* | | |The transmission or receive byte number in one transaction when the PECEN is set
* | | |The maximum transaction or receive byte is 256 Bytes.
* | | |Notice: The byte number counting includes address, command code, and data frame.
* @var I2C_T::PKTCRC
* Offset: 0x60 I2C Packet Error Checking Byte Value Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |PECCRC |Packet Error Checking Byte Value
* | | |This byte indicates the packet error checking content after transmission or receive byte count by using the C(x) = X8 + X2 + X + 1
* | | |It is read only.
* @var I2C_T::BUSTOUT
* Offset: 0x64 I2C Bus Management Timer Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |BUSTO |Bus Management Time-out Value
* | | |Indicate the bus time-out value in bus is IDLE or SCLK low.
* | | |Note: If the user wants to revise the value of BUSTOUT, the TORSTEN (I2C_BUSTCTL[4]) bit shall be set to 1 and clear to 0 first in the BUSEN(I2C_BUSCTL[7]) is set.
* @var I2C_T::CLKTOUT
* Offset: 0x68 I2C Bus Management Clock Low Timer Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |CLKTO |Bus Clock Low Timer
* | | |The field is used to configure the cumulative clock extension time-out.
* | | |Note: If the user wants to revise the value of CLKLTOUT, the TORSTEN bit shall be set to 1 and clear to 0 first in the BUSEN is set.
*/
__IO uint32_t CTL0; /*!< [0x0000] I2C Control Register 0 */
__IO uint32_t ADDR0; /*!< [0x0004] I2C Slave Address Register0 */
__IO uint32_t DAT; /*!< [0x0008] I2C Data Register */
__I uint32_t STATUS0; /*!< [0x000c] I2C Status Register 0 */
__IO uint32_t CLKDIV; /*!< [0x0010] I2C Clock Divided Register */
__IO uint32_t TOCTL; /*!< [0x0014] I2C Time-out Control Register */
__IO uint32_t ADDR1; /*!< [0x0018] I2C Slave Address Register1 */
__IO uint32_t ADDR2; /*!< [0x001c] I2C Slave Address Register2 */
__IO uint32_t ADDR3; /*!< [0x0020] I2C Slave Address Register3 */
__IO uint32_t ADDRMSK0; /*!< [0x0024] I2C Slave Address Mask Register0 */
__IO uint32_t ADDRMSK1; /*!< [0x0028] I2C Slave Address Mask Register1 */
__IO uint32_t ADDRMSK2; /*!< [0x002c] I2C Slave Address Mask Register2 */
__IO uint32_t ADDRMSK3; /*!< [0x0030] I2C Slave Address Mask Register3 */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE0[2];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t WKCTL; /*!< [0x003c] I2C Wake-up Control Register */
__IO uint32_t WKSTS; /*!< [0x0040] I2C Wake-up Status Register */
__IO uint32_t CTL1; /*!< [0x0044] I2C Control Register 1 */
__IO uint32_t STATUS1; /*!< [0x0048] I2C Status Register 1 */
__IO uint32_t TMCTL; /*!< [0x004c] I2C Timing Configure Control Register */
__IO uint32_t BUSCTL; /*!< [0x0050] I2C Bus Management Control Register */
__IO uint32_t BUSTCTL; /*!< [0x0054] I2C Bus Management Timer Control Register */
__IO uint32_t BUSSTS; /*!< [0x0058] I2C Bus Management Status Register */
__IO uint32_t PKTSIZE; /*!< [0x005c] I2C Packet Error Checking Byte Number Register */
__I uint32_t PKTCRC; /*!< [0x0060] I2C Packet Error Checking Byte Value Register */
__IO uint32_t BUSTOUT; /*!< [0x0064] I2C Bus Management Timer Register */
__IO uint32_t CLKTOUT; /*!< [0x0068] I2C Bus Management Clock Low Timer Register */
} I2C_T;
/**
@addtogroup I2C_CONST I2C Bit Field Definition
Constant Definitions for I2C Controller
@{ */
#define I2C_CTL0_AA_Pos (2) /*!< I2C_T::CTL: AA Position */
#define I2C_CTL0_AA_Msk (0x1ul << I2C_CTL0_AA_Pos) /*!< I2C_T::CTL: AA Mask */
#define I2C_CTL0_SI_Pos (3) /*!< I2C_T::CTL: SI Position */
#define I2C_CTL0_SI_Msk (0x1ul << I2C_CTL0_SI_Pos) /*!< I2C_T::CTL: SI Mask */
#define I2C_CTL0_STO_Pos (4) /*!< I2C_T::CTL: STO Position */
#define I2C_CTL0_STO_Msk (0x1ul << I2C_CTL0_STO_Pos) /*!< I2C_T::CTL: STO Mask */
#define I2C_CTL0_STA_Pos (5) /*!< I2C_T::CTL: STA Position */
#define I2C_CTL0_STA_Msk (0x1ul << I2C_CTL0_STA_Pos) /*!< I2C_T::CTL: STA Mask */
#define I2C_CTL0_I2CEN_Pos (6) /*!< I2C_T::CTL: I2CEN Position */
#define I2C_CTL0_I2CEN_Msk (0x1ul << I2C_CTL0_I2CEN_Pos) /*!< I2C_T::CTL: I2CEN Mask */
#define I2C_CTL0_INTEN_Pos (7) /*!< I2C_T::CTL: INTEN Position */
#define I2C_CTL0_INTEN_Msk (0x1ul << I2C_CTL0_INTEN_Pos) /*!< I2C_T::CTL: INTEN Mask */
#define I2C_ADDR0_GC_Pos (0) /*!< I2C_T::ADDR0: GC Position */
#define I2C_ADDR0_GC_Msk (0x1ul << I2C_ADDR0_GC_Pos) /*!< I2C_T::ADDR0: GC Mask */
#define I2C_ADDR0_ADDR_Pos (1) /*!< I2C_T::ADDR0: ADDR Position */
#define I2C_ADDR0_ADDR_Msk (0x3fful << I2C_ADDR0_ADDR_Pos) /*!< I2C_T::ADDR0: ADDR Mask */
#define I2C_DAT_DAT_Pos (0) /*!< I2C_T::DAT: DAT Position */
#define I2C_DAT_DAT_Msk (0xfful << I2C_DAT_DAT_Pos) /*!< I2C_T::DAT: DAT Mask */
#define I2C_STATUS0_STATUS_Pos (0) /*!< I2C_T::STATUS: STATUS Position */
#define I2C_STATUS0_STATUS_Msk (0xfful << I2C_STATUS_STATUS0_Pos) /*!< I2C_T::STATUS: STATUS Mask */
#define I2C_CLKDIV_DIVIDER_Pos (0) /*!< I2C_T::CLKDIV: DIVIDER Position */
#define I2C_CLKDIV_DIVIDER_Msk (0x3fful << I2C_CLKDIV_DIVIDER_Pos) /*!< I2C_T::CLKDIV: DIVIDER Mask */
#define I2C_TOCTL_TOIF_Pos (0) /*!< I2C_T::TOCTL: TOIF Position */
#define I2C_TOCTL_TOIF_Msk (0x1ul << I2C_TOCTL_TOIF_Pos) /*!< I2C_T::TOCTL: TOIF Mask */
#define I2C_TOCTL_TOCDIV4_Pos (1) /*!< I2C_T::TOCTL: TOCDIV4 Position */
#define I2C_TOCTL_TOCDIV4_Msk (0x1ul << I2C_TOCTL_TOCDIV4_Pos) /*!< I2C_T::TOCTL: TOCDIV4 Mask */
#define I2C_TOCTL_TOCEN_Pos (2) /*!< I2C_T::TOCTL: TOCEN Position */
#define I2C_TOCTL_TOCEN_Msk (0x1ul << I2C_TOCTL_TOCEN_Pos) /*!< I2C_T::TOCTL: TOCEN Mask */
#define I2C_ADDR1_GC_Pos (0) /*!< I2C_T::ADDR1: GC Position */
#define I2C_ADDR1_GC_Msk (0x1ul << I2C_ADDR1_GC_Pos) /*!< I2C_T::ADDR1: GC Mask */
#define I2C_ADDR1_ADDR_Pos (1) /*!< I2C_T::ADDR1: ADDR Position */
#define I2C_ADDR1_ADDR_Msk (0x3fful << I2C_ADDR1_ADDR_Pos) /*!< I2C_T::ADDR1: ADDR Mask */
#define I2C_ADDR2_GC_Pos (0) /*!< I2C_T::ADDR2: GC Position */
#define I2C_ADDR2_GC_Msk (0x1ul << I2C_ADDR2_GC_Pos) /*!< I2C_T::ADDR2: GC Mask */
#define I2C_ADDR2_ADDR_Pos (1) /*!< I2C_T::ADDR2: ADDR Position */
#define I2C_ADDR2_ADDR_Msk (0x3fful << I2C_ADDR2_ADDR_Pos) /*!< I2C_T::ADDR2: ADDR Mask */
#define I2C_ADDR3_GC_Pos (0) /*!< I2C_T::ADDR3: GC Position */
#define I2C_ADDR3_GC_Msk (0x1ul << I2C_ADDR3_GC_Pos) /*!< I2C_T::ADDR3: GC Mask */
#define I2C_ADDR3_ADDR_Pos (1) /*!< I2C_T::ADDR3: ADDR Position */
#define I2C_ADDR3_ADDR_Msk (0x3fful << I2C_ADDR3_ADDR_Pos) /*!< I2C_T::ADDR3: ADDR Mask */
#define I2C_ADDRMSK0_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK0: ADDRMSK Position */
#define I2C_ADDRMSK0_ADDRMSK_Msk (0x3fful << I2C_ADDRMSK0_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK0: ADDRMSK Mask */
#define I2C_ADDRMSK1_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK1: ADDRMSK Position */
#define I2C_ADDRMSK1_ADDRMSK_Msk (0x3fful << I2C_ADDRMSK1_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK1: ADDRMSK Mask */
#define I2C_ADDRMSK2_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK2: ADDRMSK Position */
#define I2C_ADDRMSK2_ADDRMSK_Msk (0x3fful << I2C_ADDRMSK2_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK2: ADDRMSK Mask */
#define I2C_ADDRMSK3_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK3: ADDRMSK Position */
#define I2C_ADDRMSK3_ADDRMSK_Msk (0x3fful << I2C_ADDRMSK3_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK3: ADDRMSK Mask */
#define I2C_WKCTL_WKEN_Pos (0) /*!< I2C_T::WKCTL: WKEN Position */
#define I2C_WKCTL_WKEN_Msk (0x1ul << I2C_WKCTL_WKEN_Pos) /*!< I2C_T::WKCTL: WKEN Mask */
#define I2C_WKCTL_NHDBUSEN_Pos (7) /*!< I2C_T::WKCTL: NHDBUSEN Position */
#define I2C_WKCTL_NHDBUSEN_Msk (0x1ul << I2C_WKCTL_NHDBUSEN_Pos) /*!< I2C_T::WKCTL: NHDBUSEN Mask */
#define I2C_WKSTS_WKIF_Pos (0) /*!< I2C_T::WKSTS: WKIF Position */
#define I2C_WKSTS_WKIF_Msk (0x1ul << I2C_WKSTS_WKIF_Pos) /*!< I2C_T::WKSTS: WKIF Mask */
#define I2C_WKSTS_WKAKDONE_Pos (1) /*!< I2C_T::WKSTS: WKAKDONE Position */
#define I2C_WKSTS_WKAKDONE_Msk (0x1ul << I2C_WKSTS_WKAKDONE_Pos) /*!< I2C_T::WKSTS: WKAKDONE Mask */
#define I2C_WKSTS_WRSTSWK_Pos (2) /*!< I2C_T::WKSTS: WRSTSWK Position */
#define I2C_WKSTS_WRSTSWK_Msk (0x1ul << I2C_WKSTS_WRSTSWK_Pos) /*!< I2C_T::WKSTS: WRSTSWK Mask */
#define I2C_CTL1_TXPDMAEN_Pos (0) /*!< I2C_T::CTL1: TXPDMAEN Position */
#define I2C_CTL1_TXPDMAEN_Msk (0x1ul << I2C_CTL1_TXPDMAEN_Pos) /*!< I2C_T::CTL1: TXPDMAEN Mask */
#define I2C_CTL1_RXPDMAEN_Pos (1) /*!< I2C_T::CTL1: RXPDMAEN Position */
#define I2C_CTL1_RXPDMAEN_Msk (0x1ul << I2C_CTL1_RXPDMAEN_Pos) /*!< I2C_T::CTL1: RXPDMAEN Mask */
#define I2C_CTL1_PDMARST_Pos (2) /*!< I2C_T::CTL1: PDMARST Position */
#define I2C_CTL1_PDMARST_Msk (0x1ul << I2C_CTL1_PDMARST_Pos) /*!< I2C_T::CTL1: PDMARST Mask */
#define I2C_CTL1_PDMASTR_Pos (8) /*!< I2C_T::CTL1: PDMASTR Position */
#define I2C_CTL1_PDMASTR_Msk (0x1ul << I2C_CTL1_PDMASTR_Pos) /*!< I2C_T::CTL1: PDMASTR Mask */
#define I2C_CTL1_ADDR10EN_Pos (9) /*!< I2C_T::CTL1: ADDR10EN Position */
#define I2C_CTL1_ADDR10EN_Msk (0x1ul << I2C_CTL1_ADDR10EN_Pos) /*!< I2C_T::CTL1: ADDR10EN Mask */
#define I2C_STATUS1_ADMAT0_Pos (0) /*!< I2C_T::STATUS1: ADMAT0 Position */
#define I2C_STATUS1_ADMAT0_Msk (0x1ul << I2C_STATUS1_ADMAT0_Pos) /*!< I2C_T::STATUS1: ADMAT0 Mask */
#define I2C_STATUS1_ADMAT1_Pos (1) /*!< I2C_T::STATUS1: ADMAT1 Position */
#define I2C_STATUS1_ADMAT1_Msk (0x1ul << I2C_STATUS1_ADMAT1_Pos) /*!< I2C_T::STATUS1: ADMAT1 Mask */
#define I2C_STATUS1_ADMAT2_Pos (2) /*!< I2C_T::STATUS1: ADMAT2 Position */
#define I2C_STATUS1_ADMAT2_Msk (0x1ul << I2C_STATUS1_ADMAT2_Pos) /*!< I2C_T::STATUS1: ADMAT2 Mask */
#define I2C_STATUS1_ADMAT3_Pos (3) /*!< I2C_T::STATUS1: ADMAT3 Position */
#define I2C_STATUS1_ADMAT3_Msk (0x1ul << I2C_STATUS1_ADMAT3_Pos) /*!< I2C_T::STATUS1: ADMAT3 Mask */
#define I2C_STATUS1_ONBUSY_Pos (8) /*!< I2C_T::STATUS1: ONBUSY Position */
#define I2C_STATUS1_ONBUSY_Msk (0x1ul << I2C_STATUS1_ONBUSY_Pos) /*!< I2C_T::STATUS1: ONBUSY Mask */
#define I2C_TMCTL_STCTL_Pos (0) /*!< I2C_T::TMCTL: STCTL Position */
#define I2C_TMCTL_STCTL_Msk (0x1fful << I2C_TMCTL_STCTL_Pos) /*!< I2C_T::TMCTL: STCTL Mask */
#define I2C_TMCTL_HTCTL_Pos (16) /*!< I2C_T::TMCTL: HTCTL Position */
#define I2C_TMCTL_HTCTL_Msk (0x1fful << I2C_TMCTL_HTCTL_Pos) /*!< I2C_T::TMCTL: HTCTL Mask */
#define I2C_BUSCTL_ACKMEN_Pos (0) /*!< I2C_T::BUSCTL: ACKMEN Position */
#define I2C_BUSCTL_ACKMEN_Msk (0x1ul << I2C_BUSCTL_ACKMEN_Pos) /*!< I2C_T::BUSCTL: ACKMEN Mask */
#define I2C_BUSCTL_PECEN_Pos (1) /*!< I2C_T::BUSCTL: PECEN Position */
#define I2C_BUSCTL_PECEN_Msk (0x1ul << I2C_BUSCTL_PECEN_Pos) /*!< I2C_T::BUSCTL: PECEN Mask */
#define I2C_BUSCTL_BMDEN_Pos (2) /*!< I2C_T::BUSCTL: BMDEN Position */
#define I2C_BUSCTL_BMDEN_Msk (0x1ul << I2C_BUSCTL_BMDEN_Pos) /*!< I2C_T::BUSCTL: BMDEN Mask */
#define I2C_BUSCTL_BMHEN_Pos (3) /*!< I2C_T::BUSCTL: BMHEN Position */
#define I2C_BUSCTL_BMHEN_Msk (0x1ul << I2C_BUSCTL_BMHEN_Pos) /*!< I2C_T::BUSCTL: BMHEN Mask */
#define I2C_BUSCTL_ALERTEN_Pos (4) /*!< I2C_T::BUSCTL: ALERTEN Position */
#define I2C_BUSCTL_ALERTEN_Msk (0x1ul << I2C_BUSCTL_ALERTEN_Pos) /*!< I2C_T::BUSCTL: ALERTEN Mask */
#define I2C_BUSCTL_SCTLOSTS_Pos (5) /*!< I2C_T::BUSCTL: SCTLOSTS Position */
#define I2C_BUSCTL_SCTLOSTS_Msk (0x1ul << I2C_BUSCTL_SCTLOSTS_Pos) /*!< I2C_T::BUSCTL: SCTLOSTS Mask */
#define I2C_BUSCTL_SCTLOEN_Pos (6) /*!< I2C_T::BUSCTL: SCTLOEN Position */
#define I2C_BUSCTL_SCTLOEN_Msk (0x1ul << I2C_BUSCTL_SCTLOEN_Pos) /*!< I2C_T::BUSCTL: SCTLOEN Mask */
#define I2C_BUSCTL_BUSEN_Pos (7) /*!< I2C_T::BUSCTL: BUSEN Position */
#define I2C_BUSCTL_BUSEN_Msk (0x1ul << I2C_BUSCTL_BUSEN_Pos) /*!< I2C_T::BUSCTL: BUSEN Mask */
#define I2C_BUSCTL_PECTXEN_Pos (8) /*!< I2C_T::BUSCTL: PECTXEN Position */
#define I2C_BUSCTL_PECTXEN_Msk (0x1ul << I2C_BUSCTL_PECTXEN_Pos) /*!< I2C_T::BUSCTL: PECTXEN Mask */
#define I2C_BUSCTL_TIDLE_Pos (9) /*!< I2C_T::BUSCTL: TIDLE Position */
#define I2C_BUSCTL_TIDLE_Msk (0x1ul << I2C_BUSCTL_TIDLE_Pos) /*!< I2C_T::BUSCTL: TIDLE Mask */
#define I2C_BUSCTL_PECCLR_Pos (10) /*!< I2C_T::BUSCTL: PECCLR Position */
#define I2C_BUSCTL_PECCLR_Msk (0x1ul << I2C_BUSCTL_PECCLR_Pos) /*!< I2C_T::BUSCTL: PECCLR Mask */
#define I2C_BUSCTL_ACKM9SI_Pos (11) /*!< I2C_T::BUSCTL: ACKM9SI Position */
#define I2C_BUSCTL_ACKM9SI_Msk (0x1ul << I2C_BUSCTL_ACKM9SI_Pos) /*!< I2C_T::BUSCTL: ACKM9SI Mask */
#define I2C_BUSCTL_BCDIEN_Pos (12) /*!< I2C_T::BUSCTL: BCDIEN Position */
#define I2C_BUSCTL_BCDIEN_Msk (0x1ul << I2C_BUSCTL_BCDIEN_Pos) /*!< I2C_T::BUSCTL: BCDIEN Mask */
#define I2C_BUSCTL_PECDIEN_Pos (13) /*!< I2C_T::BUSCTL: PECDIEN Position */
#define I2C_BUSCTL_PECDIEN_Msk (0x1ul << I2C_BUSCTL_PECDIEN_Pos) /*!< I2C_T::BUSCTL: PECDIEN Mask */
#define I2C_BUSTCTL_BUSTOEN_Pos (0) /*!< I2C_T::BUSTCTL: BUSTOEN Position */
#define I2C_BUSTCTL_BUSTOEN_Msk (0x1ul << I2C_BUSTCTL_BUSTOEN_Pos) /*!< I2C_T::BUSTCTL: BUSTOEN Mask */
#define I2C_BUSTCTL_CLKTOEN_Pos (1) /*!< I2C_T::BUSTCTL: CLKTOEN Position */
#define I2C_BUSTCTL_CLKTOEN_Msk (0x1ul << I2C_BUSTCTL_CLKTOEN_Pos) /*!< I2C_T::BUSTCTL: CLKTOEN Mask */
#define I2C_BUSTCTL_BUSTOIEN_Pos (2) /*!< I2C_T::BUSTCTL: BUSTOIEN Position */
#define I2C_BUSTCTL_BUSTOIEN_Msk (0x1ul << I2C_BUSTCTL_BUSTOIEN_Pos) /*!< I2C_T::BUSTCTL: BUSTOIEN Mask */
#define I2C_BUSTCTL_CLKTOIEN_Pos (3) /*!< I2C_T::BUSTCTL: CLKTOIEN Position */
#define I2C_BUSTCTL_CLKTOIEN_Msk (0x1ul << I2C_BUSTCTL_CLKTOIEN_Pos) /*!< I2C_T::BUSTCTL: CLKTOIEN Mask */
#define I2C_BUSTCTL_TORSTEN_Pos (4) /*!< I2C_T::BUSTCTL: TORSTEN Position */
#define I2C_BUSTCTL_TORSTEN_Msk (0x1ul << I2C_BUSTCTL_TORSTEN_Pos) /*!< I2C_T::BUSTCTL: TORSTEN Mask */
#define I2C_BUSSTS_BUSY_Pos (0) /*!< I2C_T::BUSSTS: BUSY Position */
#define I2C_BUSSTS_BUSY_Msk (0x1ul << I2C_BUSSTS_BUSY_Pos) /*!< I2C_T::BUSSTS: BUSY Mask */
#define I2C_BUSSTS_BCDONE_Pos (1) /*!< I2C_T::BUSSTS: BCDONE Position */
#define I2C_BUSSTS_BCDONE_Msk (0x1ul << I2C_BUSSTS_BCDONE_Pos) /*!< I2C_T::BUSSTS: BCDONE Mask */
#define I2C_BUSSTS_PECERR_Pos (2) /*!< I2C_T::BUSSTS: PECERR Position */
#define I2C_BUSSTS_PECERR_Msk (0x1ul << I2C_BUSSTS_PECERR_Pos) /*!< I2C_T::BUSSTS: PECERR Mask */
#define I2C_BUSSTS_ALERT_Pos (3) /*!< I2C_T::BUSSTS: ALERT Position */
#define I2C_BUSSTS_ALERT_Msk (0x1ul << I2C_BUSSTS_ALERT_Pos) /*!< I2C_T::BUSSTS: ALERT Mask */
#define I2C_BUSSTS_SCTLDIN_Pos (4) /*!< I2C_T::BUSSTS: SCTLDIN Position */
#define I2C_BUSSTS_SCTLDIN_Msk (0x1ul << I2C_BUSSTS_SCTLDIN_Pos) /*!< I2C_T::BUSSTS: SCTLDIN Mask */
#define I2C_BUSSTS_BUSTO_Pos (5) /*!< I2C_T::BUSSTS: BUSTO Position */
#define I2C_BUSSTS_BUSTO_Msk (0x1ul << I2C_BUSSTS_BUSTO_Pos) /*!< I2C_T::BUSSTS: BUSTO Mask */
#define I2C_BUSSTS_CLKTO_Pos (6) /*!< I2C_T::BUSSTS: CLKTO Position */
#define I2C_BUSSTS_CLKTO_Msk (0x1ul << I2C_BUSSTS_CLKTO_Pos) /*!< I2C_T::BUSSTS: CLKTO Mask */
#define I2C_BUSSTS_PECDONE_Pos (7) /*!< I2C_T::BUSSTS: PECDONE Position */
#define I2C_BUSSTS_PECDONE_Msk (0x1ul << I2C_BUSSTS_PECDONE_Pos) /*!< I2C_T::BUSSTS: PECDONE Mask */
#define I2C_PKTSIZE_PLDSIZE_Pos (0) /*!< I2C_T::PKTSIZE: PLDSIZE Position */
#define I2C_PKTSIZE_PLDSIZE_Msk (0x1fful << I2C_PKTSIZE_PLDSIZE_Pos) /*!< I2C_T::PKTSIZE: PLDSIZE Mask */
#define I2C_PKTCRC_PECCRC_Pos (0) /*!< I2C_T::PKTCRC: PECCRC Position */
#define I2C_PKTCRC_PECCRC_Msk (0xfful << I2C_PKTCRC_PECCRC_Pos) /*!< I2C_T::PKTCRC: PECCRC Mask */
#define I2C_BUSTOUT_BUSTO_Pos (0) /*!< I2C_T::BUSTOUT: BUSTO Position */
#define I2C_BUSTOUT_BUSTO_Msk (0xfful << I2C_BUSTOUT_BUSTO_Pos) /*!< I2C_T::BUSTOUT: BUSTO Mask */
#define I2C_CLKTOUT_CLKTO_Pos (0) /*!< I2C_T::CLKTOUT: CLKTO Position */
#define I2C_CLKTOUT_CLKTO_Msk (0xfful << I2C_CLKTOUT_CLKTO_Pos) /*!< I2C_T::CLKTOUT: CLKTO Mask */
/**@}*/ /* I2C_CONST */
/**@}*/ /* end of I2C register group */
/*---------------------- UART Mode of USCI Controller -------------------------*/
/**
@addtogroup UUART UART Mode of USCI Controller(UUART)
Memory Mapped Structure for UUART Controller
@{ */
typedef struct {
/**
* @var UUART_T::CTL
* Offset: 0x00 USCI Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[2:0] |FUNMODE |Function Mode
* | | |This bit field selects the protocol for this USCI controller
* | | |Selecting a protocol that is not available or a reserved combination disables the USCI
* | | |When switching between two protocols, the USCI has to be disabled before selecting a new protocol
* | | |Simultaneously, the USCI will be reset when user write 000 to FUNMODE.
* | | |000 = The USCI is disabled. All protocol related state machines are set to idle state.
* | | |001 = The SPI protocol is selected.
* | | |010 = The UART protocol is selected.
* | | |100 = The I2C protocol is selected.
* | | |Note: Other bit combinations are reserved.
* @var UUART_T::INTEN
* Offset: 0x04 USCI Interrupt Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1] |TXSTIEN |Transmit Start Interrupt Enable Bit
* | | |This bit enables the interrupt generation in case of a transmit start event.
* | | |0 = The transmit start interrupt is disabled.
* | | |1 = The transmit start interrupt is enabled.
* |[2] |TXENDIEN |Transmit End Interrupt Enable Bit
* | | |This bit enables the interrupt generation in case of a transmit finish event.
* | | |0 = The transmit finish interrupt is disabled.
* | | |1 = The transmit finish interrupt is enabled.
* |[3] |RXSTIEN |Receive Start Interrupt Enable BIt
* | | |This bit enables the interrupt generation in case of a receive start event.
* | | |0 = The receive start interrupt is disabled.
* | | |1 = The receive start interrupt is enabled.
* |[4] |RXENDIEN |Receive End Interrupt Enable Bit
* | | |This bit enables the interrupt generation in case of a receive finish event.
* | | |0 = The receive end interrupt is disabled.
* | | |1 = The receive end interrupt is enabled.
* @var UUART_T::BRGEN
* Offset: 0x08 USCI Baud Rate Generator Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |RCLKSEL |Reference Clock Source Selection
* | | |This bit selects the source signal of reference clock (fREF_CLK).
* | | |0 = Peripheral device clock fPCLK.
* | | |1 = Reserved.
* |[1] |PTCLKSEL |Protocol Clock Source Selection
* | | |This bit selects the source signal of protocol clock (fPROT_CLK).
* | | |0 = Reference clock fREF_CLK.
* | | |1 = fREF_CLK2 (its frequency is half of fREF_CLK).
* |[3:2] |SPCLKSEL |Sample Clock Source Selection
* | | |This bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor.
* | | |00 = fSAMP_CLK = fDIV_CLK.
* | | |01 = fSAMP_CLK = fPROT_CLK.
* | | |10 = fSAMP_CLK = fSCLK.
* | | |11 = fSAMP_CLK = fREF_CLK.
* |[4] |TMCNTEN |Timing Measurement Counter Enable Bit
* | | |This bit enables the 10-bit timing measurement counter.
* | | |0 = Timing measurement counter is Disabled.
* | | |1 = Timing measurement counter is Enabled.
* |[5] |TMCNTSRC |Timing Measurement Counter Clock Source Selection
* | | |0 = Timing measurement counter with fPROT_CLK.
* | | |1 = Timing measurement counter with fDIV_CLK.
* |[9:8] |PDSCNT |Pre-divider for Sample Counter
* | | |This bit field defines the divide ratio of the clock division from sample clock fSAMP_CLK
* | | |The divided frequency fPDS_CNT = fSAMP_CLK / (PDSCNT+1).
* |[14:10] |DSCNT |Denominator for Sample Counter
* | | |This bit field defines the divide ratio of the sample clock fSAMP_CLK.
* | | |The divided frequency fDS_CNT = fPDS_CNT / (DSCNT+1).
* | | |Note: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value
* |[25:16] |CLKDIV |Clock Divider
* | | |This bit field defines the ratio between the protocol clock frequency fPROT_CLK and
* | | |the clock divider frequency fDIV_CLK (fDIV_CLK = fPROT_CLK / (CLKDIV+1) ).
* | | |Note: In UART function, it can be updated by hardware in the 4th falling edge of the input data 0x55
* | | |when the auto baud rate function (ABREN(USCI_PROTCTL[6])) is enabled
* | | |The revised value is the average bit time between bit 5 and bit 6
* | | |The user can use revised CLKDIV and new BRDETITV (USCI_PROTCTL[24:16]) to calculate the precise baud rate.
* @var UUART_T::DATIN0
* Offset: 0x10 USCI Input Data Signal Configuration Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SYNCSEL |Input Signal Synchronization Selection
* | | |This bit selects if the un-synchronized input signal (with optionally inverted) or
* | | |the synchronized (and optionally filtered) signal can be used as input for the data shift unit.
* | | |0 = The un-synchronized signal can be taken as input for the data shift unit.
* | | |1 = The synchronized signal can be taken as input for the data shift unit.
* |[2] |ININV |Input Signal Inverse Selection
* | | |This bit defines the inverter enable of the input asynchronous signal.
* | | |0 = The un-synchronized input signal will not be inverted.
* | | |1 = The un-synchronized input signal will be inverted.
* |[4:3] |EDGEDET |Input Signal Edge Detection Mode
* | | |This bit field selects which edge actives the trigger event of input data signal.
* | | |00 = The trigger event activation is disabled.
* | | |01 = A rising edge activates the trigger event of input data signal.
* | | |10 = A falling edge activates the trigger event of input data signal.
* | | |11 = Both edges activate the trigger event of input data signal.
* | | |Note: In UART function mode, it is suggested to set this bit field as 10.
* @var UUART_T::CTLIN0
* Offset: 0x20 USCI Input Control Signal Configuration Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SYNCSEL |Input Synchronization Signal Selection
* | | |This bit selects if the un-synchronized input signal (with optionally inverted) or
* | | |the synchronized (and optionally filtered) signal can be used as input for the data shift unit.
* | | |0 = The un-synchronized signal can be taken as input for the data shift unit.
* | | |1 = The synchronized signal can be taken as input for the data shift unit.
* |[2] |ININV |Input Signal Inverse Selection
* | | |This bit defines the inverter enable of the input asynchronous signal.
* | | |0 = The un-synchronized input signal will not be inverted.
* | | |1 = The un-synchronized input signal will be inverted.
* @var UUART_T::CLKIN
* Offset: 0x28 USCI Input Clock Signal Configuration Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SYNCSEL |Input Synchronization Signal Selection
* | | |This bit selects if the un-synchronized input signal or
* | | |the synchronized (and optionally filtered) signal can be used as input for the data shift unit.
* | | |0 = The un-synchronized signal can be taken as input for the data shift unit.
* | | |1 = The synchronized signal can be taken as input for the data shift unit.
* @var UUART_T::LINECTL
* Offset: 0x2C USCI Line Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |LSB |LSB First Transmission Selection
* | | |0 = The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first.
* | | |1 = The LSB, the bit 0 of data buffer, will be transmitted/received first.
* |[5] |DATOINV |Data Output Inverse Selection
* | | |This bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT1 pin.
* | | |0 = The value of USCIx_DAT1 is equal to the data shift register.
* | | |1 = The value of USCIx_DAT1 is the inversion of data shift register.
* |[7] |CTLOINV |Control Signal Output Inverse Selection
* | | |This bit defines the relation between the internal control signal and the output control signal.
* | | |0 = No effect.
* | | |1 = The control signal will be inverted before its output.
* | | |Note: In UART protocol, the control signal means nRTS signal.
* |[11:8] |DWIDTH |Word Length of Transmission
* | | |This bit field defines the data word length (amount of bits) for reception and transmission
* | | |The data word is always right-aligned in the data buffer
* | | |USCI support word length from 4 to 16 bits.
* | | |0x0: The data word contains 16 bits located at bit positions [15:0].
* | | |0x1: Reserved.
* | | |0x2: Reserved.
* | | |0x3: Reserved.
* | | |0x4: The data word contains 4 bits located at bit positions [3:0].
* | | |0x5: The data word contains 5 bits located at bit positions [4:0].
* | | |..
* | | |0xF: The data word contains 15 bits located at bit positions [14:0].
* | | |Note: In UART protocol, the length can be configured as 6~13 bits.
* @var UUART_T::TXDAT
* Offset: 0x30 USCI Transmit Data Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |TXDAT |Transmit Data
* | | |Software can use this bit field to write 16-bit transmit data for transmission.
* @var UUART_T::RXDAT
* Offset: 0x34 USCI Receive Data Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |RXDAT |Received Data
* | | |This bit field monitors the received data which stored in receive data buffer.
* | | |Note: RXDAT[15:13] indicate the same frame status of BREAK, FRMERR and PARITYERR (USCI_PROTSTS[7:5]).
* @var UUART_T::BUFCTL
* Offset: 0x38 USCI Transmit/Receive Buffer Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7] |TXCLR |Clear Transmit Buffer
* | | |0 = No effect.
* | | |1 = The transmit buffer is cleared (filling level is cleared and output pointer is set to input pointer value)
* | | |Should only be used while the buffer is not taking part in data traffic.
* | | |Note: It is cleared automatically after one PCLK cycle.
* |[14] |RXOVIEN |Receive Buffer Overrun Error Interrupt Enable Control
* | | |0 = Receive overrun interrupt Disabled.
* | | |1 = Receive overrun interrupt Enabled.
* |[15] |RXCLR |Clear Receive Buffer
* | | |0 = No effect.
* | | |1 = The receive buffer is cleared (filling level is cleared and output pointer is set to input pointer value)
* | | |Should only be used while the buffer is not taking part in data traffic.
* | | |Note: It is cleared automatically after one PCLK cycle.
* |[16] |TXRST |Transmit Reset
* | | |0 = No effect.
* | | |1 = Reset the transmit-related counters, state machine, and the content of transmit shift register and data buffer.
* | | |Note: It is cleared automatically after one PCLK cycle.
* |[17] |RXRST |Receive Reset
* | | |0 = No effect.
* | | |1 = Reset the receive-related counters, state machine, and the content of receive shift register and data buffer.
* | | |Note 1: It is cleared automatically after one PCLK cycle.
* | | |Note 2: It is suggest to check the RXBUSY (USCI_PROTSTS[10]) before this bit will be set to 1.
* @var UUART_T::BUFSTS
* Offset: 0x3C USCI Transmit/Receive Buffer Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |RXEMPTY |Receive Buffer Empty Indicator
* | | |0 = Receive buffer is not empty.
* | | |1 = Receive buffer is empty.
* |[1] |RXFULL |Receive Buffer Full Indicator
* | | |0 = Receive buffer is not full.
* | | |1 = Receive buffer is full.
* |[3] |RXOVIF |Receive Buffer Over-run Error Interrupt Status
* | | |This bit indicates that a receive buffer overrun error event has been detected
* | | |If RXOVIEN (USCI_BUFCTL[14]) is enabled, the corresponding interrupt request is activated
* | | |It is cleared by software writes 1 to this bit.
* | | |0 = A receive buffer overrun error event has not been detected.
* | | |1 = A receive buffer overrun error event has been detected.
* |[8] |TXEMPTY |Transmit Buffer Empty Indicator
* | | |0 = Transmit buffer is not empty.
* | | |1 = Transmit buffer is empty.
* |[9] |TXFULL |Transmit Buffer Full Indicator
* | | |0 = Transmit buffer is not full.
* | | |1 = Transmit buffer is full.
* @var UUART_T::PDMACTL
* Offset: 0x40 USCI PDMA Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |PDMARST |PDMA Reset
* | | |0 = No effect.
* | | |1 = Reset the USCI's PDMA control logic. This bit will be cleared to 0 automatically.
* |[1] |TXPDMAEN |PDMA Transmit Channel Available
* | | |0 = Transmit PDMA function Disabled.
* | | |1 = Transmit PDMA function Enabled.
* |[2] |RXPDMAEN |PDMA Receive Channel Available
* | | |0 = Receive PDMA function Disabled.
* | | |1 = Receive PDMA function Enabled.
* |[3] |PDMAEN |PDMA Mode Enable Bit
* | | |0 = PDMA function Disabled.
* | | |1 = PDMA function Enabled.
* @var UUART_T::WKCTL
* Offset: 0x54 USCI Wake-up Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |WKEN |Wake-up Enable Bit
* | | |0 = Wake-up function Disabled.
* | | |1 = Wake-up function Enabled.
* |[2] |PDBOPT |Power Down Blocking Option
* | | |0 = If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, MCU will stop the transfer and enter Power-down mode immediately.
* | | |1 = If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, the on-going transfer will not be stopped and MCU will enter idle mode immediately.
* @var UUART_T::WKSTS
* Offset: 0x58 USCI Wake-up Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |WKF |Wake-up Flag
* | | |When chip is woken up from Power-down mode, this bit is set to 1
* | | |Software can write 1 to clear this bit.
* @var UUART_T::PROTCTL
* Offset: 0x5C USCI Protocol Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |STOPB |Stop Bits
* | | |This bit defines the number of stop bits in an UART frame.
* | | |0 = The number of stop bits is 1.
* | | |1 = The number of stop bits is 2.
* |[1] |PARITYEN |Parity Enable Bit
* | | |This bit defines the parity bit is enabled in an UART frame.
* | | |0 = The parity bit Disabled.
* | | |1 = The parity bit Enabled.
* |[2] |EVENPARITY|Even Parity Enable Bit
* | | |0 = Odd number of logic 1's is transmitted and checked in each word.
* | | |1 = Even number of logic 1's is transmitted and checked in each word.
* | | |Note: This bit has effect only when PARITYEN is set.
* |[3] |RTSAUTOEN |nRTS Auto-flow Control Enable Bit
* | | |When nRTS auto-flow is enabled, if the receiver buffer is full (RXFULL (USCI_BUFSTS[1] = 1'b1)), the UART will de-assert nRTS signal.
* | | |0 = nRTS auto-flow control Disabled.
* | | |1 = nRTS auto-flow control Enabled.
* | | |Note: This bit has effect only when the RTSAUDIREN is not set.
* |[4] |CTSAUTOEN |nCTS Auto-flow Control Enable Bit
* | | |When nCTS auto-flow is enabled, the UART will send data to external device when nCTS input assert (UART will not send data to device if nCTS input is dis-asserted).
* | | |0 = nCTS auto-flow control Disabled.
* | | |1 = nCTS auto-flow control Enabled.
* |[5] |RTSAUDIREN|nRTS Auto Direction Enable Bit
* | | |When nRTS auto direction is enabled, if the transmitted bytes in the TX buffer is empty, the UART asserted nRTS signal automatically.
* | | |0 = nRTS auto direction control Disabled.
* | | |1 = nRTS auto direction control Enabled.
* | | |Note 1: This bit is used for nRTS auto direction control for RS485.
* | | |Note 2: This bit has effect only when the RTSAUTOEN is not set.
* |[6] |ABREN |Auto-baud Rate Detect Enable Bit
* | | |0 = Auto-baud rate detect function Disabled.
* | | |1 = Auto-baud rate detect function Enabled.
* | | |Note: When the auto - baud rate detect operation finishes, hardware will clear this bit
* | | |The associated interrupt ABRDETIF (USCI_PROTST[9]) will be generated (If ARBIEN (USCI_PROTIEN [1]) is enabled).
* |[9] |DATWKEN |Data Wake-up Mode Enable Bit
* | | |0 = Data wake-up mode Disabled.
* | | |1 = Data wake-up mode Enabled.
* |[10] |CTSWKEN |nCTS Wake-up Mode Enable Bit
* | | |0 = nCTS wake-up mode Disabled.
* | | |1 = nCTS wake-up mode Enabled.
* |[14:11] |WAKECNT |Wake-up Counter
* | | |These bits field indicate how many clock cycle selected by fPDS_CNT do the slave can get the 1st bit (start bit) when the device is wake-up from Power-down mode.
* |[24:16] |BRDETITV |Baud Rate Detection Interval
* | | |This bit fields indicate how many clock cycle selected by TMCNTSRC (USCI_BRGEN [5]) does the slave calculates the baud rate in one bits
* | | |The order of the bus shall be 1 and 0 step by step (e.g. the input data pattern shall be 0x55)
* | | |The user can read the value to know the current input baud rate of the bus whenever the ABRDETIF (USCI_PROTCTL[9]) is set.
* | | |Note: This bit can be cleared to 0 by software writing '0' to the BRDETITV.
* |[26] |STICKEN |Stick Parity Enable Bit
* | | |0 = Stick parity Disabled.
* | | |1 = Stick parity Enabled.
* | | |Note: Refer to RS-485 Support section for detail information.
* |[29] |BCEN |Transmit Break Control Enable Bit
* | | |0 = Transmit Break Control Disabled.
* | | |1 = Transmit Break Control Enabled.
* | | |Note: When this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0)
* | | |This bit acts only on TX line and has no effect on the transmitter logic.
* |[31] |PROTEN |UART Protocol Enable Bit
* | | |0 = UART Protocol Disabled.
* | | |1 = UART Protocol Enabled.
* @var UUART_T::PROTIEN
* Offset: 0x60 USCI Protocol Interrupt Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1] |ABRIEN |Auto-baud Rate Interrupt Enable Bit
* | | |0 = Auto-baud rate interrupt Disabled.
* | | |1 = Auto-baud rate interrupt Enabled.
* |[2] |RLSIEN |Receive Line Status Interrupt Enable Bit
* | | |0 = Receive line status interrupt Disabled.
* | | |1 = Receive line status interrupt Enabled.
* | | |Note: USCI_PROTSTS[7:5] indicates the current interrupt event for receive line status interrupt.
* @var UUART_T::PROTSTS
* Offset: 0x64 USCI Protocol Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1] |TXSTIF |Transmit Start Interrupt Flag
* | | |0 = A transmit start interrupt status has not occurred.
* | | |1 = A transmit start interrupt status has occurred.
* | | |Note 1: It is cleared by software writing one into this bit.
* | | |Note 2: Used for user to load next transmit data when there is no data in transmit buffer.
* |[2] |TXENDIF |Transmit End Interrupt Flag
* | | |0 = A transmit end interrupt status has not occurred.
* | | |1 = A transmit end interrupt status has occurred.
* | | |Note: It is cleared by software writing one into this bit.
* |[3] |RXSTIF |Receive Start Interrupt Flag
* | | |0 = A receive start interrupt status has not occurred.
* | | |1 = A receive start interrupt status has occurred.
* | | |Note: It is cleared by software writing one into this bit.
* |[4] |RXENDIF |Receive End Interrupt Flag
* | | |0 = A receive finish interrupt status has not occurred.
* | | |1 = A receive finish interrupt status has occurred.
* | | |Note: It is cleared by software writing one into this bit.
* |[5] |PARITYERR |Parity Error Flag
* | | |This bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.
* | | |0 = No parity error is generated.
* | | |1 = Parity error is generated.
* | | |Note: This bit can be cleared by write '1' among the BREAK, FRMERR and PARITYERR bits.
* |[6] |FRMERR |Framing Error Flag
* | | |This bit is set to logic 1 whenever the received character does not have a valid 'stop bit'
* | | |(that is, the stop bit following the last data bit or parity bit is detected as logic 0).
* | | |0 = No framing error is generated.
* | | |1 = Framing error is generated.
* | | |Note: This bit can be cleared by write '1' among the BREAK, FRMERR and PARITYERR bits.
* |[7] |BREAK |Break Flag
* | | |This bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state'
* | | |(logic 0) for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits).
* | | |0 = No Break is generated.
* | | |1 = Break is generated in the receiver bus.
* | | |Note: This bit can be cleared by write '1' among the BREAK, FRMERR and PARITYERR bits.
* |[9] |ABRDETIF |Auto-baud Rate Interrupt Flag
* | | |This bit is set when auto-baud rate detection is done among the falling edge of the input data
* | | |If the ABRIEN (USCI_PROTCTL[6]) is set, the auto-baud rate interrupt will be generated
* | | |This bit can be set 4 times when the input data pattern is 0x55 and it is cleared before the next falling edge of the input bus.
* | | |0 = Auto-baud rate detect function is not done.
* | | |1 = One Bit auto-baud rate detect function is done.
* | | |Note: This bit can be cleared by writing '1' to it.
* |[10] |RXBUSY |RX Bus Status Flag (Read Only)
* | | |This bit indicates the busy status of the receiver.
* | | |0 = The receiver is Idle.
* | | |1 = The receiver is BUSY.
* |[11] |ABERRSTS |Auto-baud Rate Error Status
* | | |This bit is set when auto-baud rate detection counter overrun
* | | |When the auto-baud rate counter overrun, the user shall revise the CLKDIV (USCI_BRGEN[25:16]) value and
* | | |enable ABREN (USCI_PROTCTL[6]) to detect the correct baud rate again.
* | | |0 = Auto-baud rate detect counter is not overrun.
* | | |1 = Auto-baud rate detect counter is overrun.
* | | |Note 1: This bit is set at the same time of ABRDETIF.
* | | |Note 2: This bit can be cleared by writing '1' to ABRDETIF or ABERRSTS.
* |[16] |CTSSYNCLV |nCTS Synchronized Level Status (Read Only)
* | | |This bit used to indicate the current status of the internal synchronized nCTS signal.
* | | |0 = The internal synchronized nCTS is low.
* | | |1 = The internal synchronized nCTS is high.
* |[17] |CTSLV |nCTS Pin Status (Read Only)
* | | |This bit used to monitor the current status of nCTS pin input.
* | | |0 = nCTS pin input is low level voltage logic state.
* | | |1 = nCTS pin input is high level voltage logic state.
*/
__IO uint32_t CTL; /*!< [0x0000] USCI Control Register */
__IO uint32_t INTEN; /*!< [0x0004] USCI Interrupt Enable Register */
__IO uint32_t BRGEN; /*!< [0x0008] USCI Baud Rate Generator Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE0[1];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t DATIN0; /*!< [0x0010] USCI Input Data Signal Configuration Register 0 */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE1[3];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t CTLIN0; /*!< [0x0020] USCI Input Control Signal Configuration Register 0 */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE2[1];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t CLKIN; /*!< [0x0028] USCI Input Clock Signal Configuration Register */
__IO uint32_t LINECTL; /*!< [0x002c] USCI Line Control Register */
__IO uint32_t TXDAT; /*!< [0x0030] USCI Transmit Data Register */
__IO uint32_t RXDAT; /*!< [0x0034] USCI Receive Data Register */
__IO uint32_t BUFCTL; /*!< [0x0038] USCI Transmit/Receive Buffer Control Register */
__IO uint32_t BUFSTS; /*!< [0x003c] USCI Transmit/Receive Buffer Status Register */
__IO uint32_t PDMACTL; /*!< [0x0040] USCI PDMA Control Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE3[4];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t WKCTL; /*!< [0x0054] USCI Wake-up Control Register */
__IO uint32_t WKSTS; /*!< [0x0058] USCI Wake-up Status Register */
__IO uint32_t PROTCTL; /*!< [0x005c] USCI Protocol Control Register */
__IO uint32_t PROTIEN; /*!< [0x0060] USCI Protocol Interrupt Enable Register */
__IO uint32_t PROTSTS; /*!< [0x0064] USCI Protocol Status Register */
} UUART_T;
/**
@addtogroup UUART_CONST UUART Bit Field Definition
Constant Definitions for UUART Controller
@{ */
#define UUART_CTL_FUNMODE_Pos (0) /*!< UUART_T::CTL: FUNMODE Position */
#define UUART_CTL_FUNMODE_Msk (0x7ul << UUART_CTL_FUNMODE_Pos) /*!< UUART_T::CTL: FUNMODE Mask */
#define UUART_INTEN_TXSTIEN_Pos (1) /*!< UUART_T::INTEN: TXSTIEN Position */
#define UUART_INTEN_TXSTIEN_Msk (0x1ul << UUART_INTEN_TXSTIEN_Pos) /*!< UUART_T::INTEN: TXSTIEN Mask */
#define UUART_INTEN_TXENDIEN_Pos (2) /*!< UUART_T::INTEN: TXENDIEN Position */
#define UUART_INTEN_TXENDIEN_Msk (0x1ul << UUART_INTEN_TXENDIEN_Pos) /*!< UUART_T::INTEN: TXENDIEN Mask */
#define UUART_INTEN_RXSTIEN_Pos (3) /*!< UUART_T::INTEN: RXSTIEN Position */
#define UUART_INTEN_RXSTIEN_Msk (0x1ul << UUART_INTEN_RXSTIEN_Pos) /*!< UUART_T::INTEN: RXSTIEN Mask */
#define UUART_INTEN_RXENDIEN_Pos (4) /*!< UUART_T::INTEN: RXENDIEN Position */
#define UUART_INTEN_RXENDIEN_Msk (0x1ul << UUART_INTEN_RXENDIEN_Pos) /*!< UUART_T::INTEN: RXENDIEN Mask */
#define UUART_BRGEN_RCLKSEL_Pos (0) /*!< UUART_T::BRGEN: RCLKSEL Position */
#define UUART_BRGEN_RCLKSEL_Msk (0x1ul << UUART_BRGEN_RCLKSEL_Pos) /*!< UUART_T::BRGEN: RCLKSEL Mask */
#define UUART_BRGEN_PTCLKSEL_Pos (1) /*!< UUART_T::BRGEN: PTCLKSEL Position */
#define UUART_BRGEN_PTCLKSEL_Msk (0x1ul << UUART_BRGEN_PTCLKSEL_Pos) /*!< UUART_T::BRGEN: PTCLKSEL Mask */
#define UUART_BRGEN_SPCLKSEL_Pos (2) /*!< UUART_T::BRGEN: SPCLKSEL Position */
#define UUART_BRGEN_SPCLKSEL_Msk (0x3ul << UUART_BRGEN_SPCLKSEL_Pos) /*!< UUART_T::BRGEN: SPCLKSEL Mask */
#define UUART_BRGEN_TMCNTEN_Pos (4) /*!< UUART_T::BRGEN: TMCNTEN Position */
#define UUART_BRGEN_TMCNTEN_Msk (0x1ul << UUART_BRGEN_TMCNTEN_Pos) /*!< UUART_T::BRGEN: TMCNTEN Mask */
#define UUART_BRGEN_TMCNTSRC_Pos (5) /*!< UUART_T::BRGEN: TMCNTSRC Position */
#define UUART_BRGEN_TMCNTSRC_Msk (0x1ul << UUART_BRGEN_TMCNTSRC_Pos) /*!< UUART_T::BRGEN: TMCNTSRC Mask */
#define UUART_BRGEN_PDSCNT_Pos (8) /*!< UUART_T::BRGEN: PDSCNT Position */
#define UUART_BRGEN_PDSCNT_Msk (0x3ul << UUART_BRGEN_PDSCNT_Pos) /*!< UUART_T::BRGEN: PDSCNT Mask */
#define UUART_BRGEN_DSCNT_Pos (10) /*!< UUART_T::BRGEN: DSCNT Position */
#define UUART_BRGEN_DSCNT_Msk (0x1ful << UUART_BRGEN_DSCNT_Pos) /*!< UUART_T::BRGEN: DSCNT Mask */
#define UUART_BRGEN_CLKDIV_Pos (16) /*!< UUART_T::BRGEN: CLKDIV Position */
#define UUART_BRGEN_CLKDIV_Msk (0x3fful << UUART_BRGEN_CLKDIV_Pos) /*!< UUART_T::BRGEN: CLKDIV Mask */
#define UUART_DATIN0_SYNCSEL_Pos (0) /*!< UUART_T::DATIN0: SYNCSEL Position */
#define UUART_DATIN0_SYNCSEL_Msk (0x1ul << UUART_DATIN0_SYNCSEL_Pos) /*!< UUART_T::DATIN0: SYNCSEL Mask */
#define UUART_DATIN0_ININV_Pos (2) /*!< UUART_T::DATIN0: ININV Position */
#define UUART_DATIN0_ININV_Msk (0x1ul << UUART_DATIN0_ININV_Pos) /*!< UUART_T::DATIN0: ININV Mask */
#define UUART_DATIN0_EDGEDET_Pos (3) /*!< UUART_T::DATIN0: EDGEDET Position */
#define UUART_DATIN0_EDGEDET_Msk (0x3ul << UUART_DATIN0_EDGEDET_Pos) /*!< UUART_T::DATIN0: EDGEDET Mask */
#define UUART_CTLIN0_SYNCSEL_Pos (0) /*!< UUART_T::CTLIN0: SYNCSEL Position */
#define UUART_CTLIN0_SYNCSEL_Msk (0x1ul << UUART_CTLIN0_SYNCSEL_Pos) /*!< UUART_T::CTLIN0: SYNCSEL Mask */
#define UUART_CTLIN0_ININV_Pos (2) /*!< UUART_T::CTLIN0: ININV Position */
#define UUART_CTLIN0_ININV_Msk (0x1ul << UUART_CTLIN0_ININV_Pos) /*!< UUART_T::CTLIN0: ININV Mask */
#define UUART_CLKIN_SYNCSEL_Pos (0) /*!< UUART_T::CLKIN: SYNCSEL Position */
#define UUART_CLKIN_SYNCSEL_Msk (0x1ul << UUART_CLKIN_SYNCSEL_Pos) /*!< UUART_T::CLKIN: SYNCSEL Mask */
#define UUART_LINECTL_LSB_Pos (0) /*!< UUART_T::LINECTL: LSB Position */
#define UUART_LINECTL_LSB_Msk (0x1ul << UUART_LINECTL_LSB_Pos) /*!< UUART_T::LINECTL: LSB Mask */
#define UUART_LINECTL_DATOINV_Pos (5) /*!< UUART_T::LINECTL: DATOINV Position */
#define UUART_LINECTL_DATOINV_Msk (0x1ul << UUART_LINECTL_DATOINV_Pos) /*!< UUART_T::LINECTL: DATOINV Mask */
#define UUART_LINECTL_CTLOINV_Pos (7) /*!< UUART_T::LINECTL: CTLOINV Position */
#define UUART_LINECTL_CTLOINV_Msk (0x1ul << UUART_LINECTL_CTLOINV_Pos) /*!< UUART_T::LINECTL: CTLOINV Mask */
#define UUART_LINECTL_DWIDTH_Pos (8) /*!< UUART_T::LINECTL: DWIDTH Position */
#define UUART_LINECTL_DWIDTH_Msk (0xful << UUART_LINECTL_DWIDTH_Pos) /*!< UUART_T::LINECTL: DWIDTH Mask */
#define UUART_TXDAT_TXDAT_Pos (0) /*!< UUART_T::TXDAT: TXDAT Position */
#define UUART_TXDAT_TXDAT_Msk (0xfffful << UUART_TXDAT_TXDAT_Pos) /*!< UUART_T::TXDAT: TXDAT Mask */
#define UUART_RXDAT_RXDAT_Pos (0) /*!< UUART_T::RXDAT: RXDAT Position */
#define UUART_RXDAT_RXDAT_Msk (0xfffful << UUART_RXDAT_RXDAT_Pos) /*!< UUART_T::RXDAT: RXDAT Mask */
#define UUART_BUFCTL_TXCLR_Pos (7) /*!< UUART_T::BUFCTL: TXCLR Position */
#define UUART_BUFCTL_TXCLR_Msk (0x1ul << UUART_BUFCTL_TXCLR_Pos) /*!< UUART_T::BUFCTL: TXCLR Mask */
#define UUART_BUFCTL_RXOVIEN_Pos (14) /*!< UUART_T::BUFCTL: RXOVIEN Position */
#define UUART_BUFCTL_RXOVIEN_Msk (0x1ul << UUART_BUFCTL_RXOVIEN_Pos) /*!< UUART_T::BUFCTL: RXOVIEN Mask */
#define UUART_BUFCTL_RXCLR_Pos (15) /*!< UUART_T::BUFCTL: RXCLR Position */
#define UUART_BUFCTL_RXCLR_Msk (0x1ul << UUART_BUFCTL_RXCLR_Pos) /*!< UUART_T::BUFCTL: RXCLR Mask */
#define UUART_BUFCTL_TXRST_Pos (16) /*!< UUART_T::BUFCTL: TXRST Position */
#define UUART_BUFCTL_TXRST_Msk (0x1ul << UUART_BUFCTL_TXRST_Pos) /*!< UUART_T::BUFCTL: TXRST Mask */
#define UUART_BUFCTL_RXRST_Pos (17) /*!< UUART_T::BUFCTL: RXRST Position */
#define UUART_BUFCTL_RXRST_Msk (0x1ul << UUART_BUFCTL_RXRST_Pos) /*!< UUART_T::BUFCTL: RXRST Mask */
#define UUART_BUFSTS_RXEMPTY_Pos (0) /*!< UUART_T::BUFSTS: RXEMPTY Position */
#define UUART_BUFSTS_RXEMPTY_Msk (0x1ul << UUART_BUFSTS_RXEMPTY_Pos) /*!< UUART_T::BUFSTS: RXEMPTY Mask */
#define UUART_BUFSTS_RXFULL_Pos (1) /*!< UUART_T::BUFSTS: RXFULL Position */
#define UUART_BUFSTS_RXFULL_Msk (0x1ul << UUART_BUFSTS_RXFULL_Pos) /*!< UUART_T::BUFSTS: RXFULL Mask */
#define UUART_BUFSTS_RXOVIF_Pos (3) /*!< UUART_T::BUFSTS: RXOVIF Position */
#define UUART_BUFSTS_RXOVIF_Msk (0x1ul << UUART_BUFSTS_RXOVIF_Pos) /*!< UUART_T::BUFSTS: RXOVIF Mask */
#define UUART_BUFSTS_TXEMPTY_Pos (8) /*!< UUART_T::BUFSTS: TXEMPTY Position */
#define UUART_BUFSTS_TXEMPTY_Msk (0x1ul << UUART_BUFSTS_TXEMPTY_Pos) /*!< UUART_T::BUFSTS: TXEMPTY Mask */
#define UUART_BUFSTS_TXFULL_Pos (9) /*!< UUART_T::BUFSTS: TXFULL Position */
#define UUART_BUFSTS_TXFULL_Msk (0x1ul << UUART_BUFSTS_TXFULL_Pos) /*!< UUART_T::BUFSTS: TXFULL Mask */
#define UUART_PDMACTL_PDMARST_Pos (0) /*!< UUART_T::PDMACTL: PDMARST Position */
#define UUART_PDMACTL_PDMARST_Msk (0x1ul << UUART_PDMACTL_PDMARST_Pos) /*!< UUART_T::PDMACTL: PDMARST Mask */
#define UUART_PDMACTL_TXPDMAEN_Pos (1) /*!< UUART_T::PDMACTL: TXPDMAEN Position */
#define UUART_PDMACTL_TXPDMAEN_Msk (0x1ul << UUART_PDMACTL_TXPDMAEN_Pos) /*!< UUART_T::PDMACTL: TXPDMAEN Mask */
#define UUART_PDMACTL_RXPDMAEN_Pos (2) /*!< UUART_T::PDMACTL: RXPDMAEN Position */
#define UUART_PDMACTL_RXPDMAEN_Msk (0x1ul << UUART_PDMACTL_RXPDMAEN_Pos) /*!< UUART_T::PDMACTL: RXPDMAEN Mask */
#define UUART_PDMACTL_PDMAEN_Pos (3) /*!< UUART_T::PDMACTL: PDMAEN Position */
#define UUART_PDMACTL_PDMAEN_Msk (0x1ul << UUART_PDMACTL_PDMAEN_Pos) /*!< UUART_T::PDMACTL: PDMAEN Mask */
#define UUART_WKCTL_WKEN_Pos (0) /*!< UUART_T::WKCTL: WKEN Position */
#define UUART_WKCTL_WKEN_Msk (0x1ul << UUART_WKCTL_WKEN_Pos) /*!< UUART_T::WKCTL: WKEN Mask */
#define UUART_WKCTL_PDBOPT_Pos (2) /*!< UUART_T::WKCTL: PDBOPT Position */
#define UUART_WKCTL_PDBOPT_Msk (0x1ul << UUART_WKCTL_PDBOPT_Pos) /*!< UUART_T::WKCTL: PDBOPT Mask */
#define UUART_WKSTS_WKF_Pos (0) /*!< UUART_T::WKSTS: WKF Position */
#define UUART_WKSTS_WKF_Msk (0x1ul << UUART_WKSTS_WKF_Pos) /*!< UUART_T::WKSTS: WKF Mask */
#define UUART_PROTCTL_STOPB_Pos (0) /*!< UUART_T::PROTCTL: STOPB Position */
#define UUART_PROTCTL_STOPB_Msk (0x1ul << UUART_PROTCTL_STOPB_Pos) /*!< UUART_T::PROTCTL: STOPB Mask */
#define UUART_PROTCTL_PARITYEN_Pos (1) /*!< UUART_T::PROTCTL: PARITYEN Position */
#define UUART_PROTCTL_PARITYEN_Msk (0x1ul << UUART_PROTCTL_PARITYEN_Pos) /*!< UUART_T::PROTCTL: PARITYEN Mask */
#define UUART_PROTCTL_EVENPARITY_Pos (2) /*!< UUART_T::PROTCTL: EVENPARITY Position */
#define UUART_PROTCTL_EVENPARITY_Msk (0x1ul << UUART_PROTCTL_EVENPARITY_Pos) /*!< UUART_T::PROTCTL: EVENPARITY Mask */
#define UUART_PROTCTL_RTSAUTOEN_Pos (3) /*!< UUART_T::PROTCTL: RTSAUTOEN Position */
#define UUART_PROTCTL_RTSAUTOEN_Msk (0x1ul << UUART_PROTCTL_RTSAUTOEN_Pos) /*!< UUART_T::PROTCTL: RTSAUTOEN Mask */
#define UUART_PROTCTL_CTSAUTOEN_Pos (4) /*!< UUART_T::PROTCTL: CTSAUTOEN Position */
#define UUART_PROTCTL_CTSAUTOEN_Msk (0x1ul << UUART_PROTCTL_CTSAUTOEN_Pos) /*!< UUART_T::PROTCTL: CTSAUTOEN Mask */
#define UUART_PROTCTL_RTSAUDIREN_Pos (5) /*!< UUART_T::PROTCTL: RTSAUDIREN Position */
#define UUART_PROTCTL_RTSAUDIREN_Msk (0x1ul << UUART_PROTCTL_RTSAUDIREN_Pos) /*!< UUART_T::PROTCTL: RTSAUDIREN Mask */
#define UUART_PROTCTL_ABREN_Pos (6) /*!< UUART_T::PROTCTL: ABREN Position */
#define UUART_PROTCTL_ABREN_Msk (0x1ul << UUART_PROTCTL_ABREN_Pos) /*!< UUART_T::PROTCTL: ABREN Mask */
#define UUART_PROTCTL_DATWKEN_Pos (9) /*!< UUART_T::PROTCTL: DATWKEN Position */
#define UUART_PROTCTL_DATWKEN_Msk (0x1ul << UUART_PROTCTL_DATWKEN_Pos) /*!< UUART_T::PROTCTL: DATWKEN Mask */
#define UUART_PROTCTL_CTSWKEN_Pos (10) /*!< UUART_T::PROTCTL: CTSWKEN Position */
#define UUART_PROTCTL_CTSWKEN_Msk (0x1ul << UUART_PROTCTL_CTSWKEN_Pos) /*!< UUART_T::PROTCTL: CTSWKEN Mask */
#define UUART_PROTCTL_WAKECNT_Pos (11) /*!< UUART_T::PROTCTL: WAKECNT Position */
#define UUART_PROTCTL_WAKECNT_Msk (0xful << UUART_PROTCTL_WAKECNT_Pos) /*!< UUART_T::PROTCTL: WAKECNT Mask */
#define UUART_PROTCTL_BRDETITV_Pos (16) /*!< UUART_T::PROTCTL: BRDETITV Position */
#define UUART_PROTCTL_BRDETITV_Msk (0x1fful << UUART_PROTCTL_BRDETITV_Pos) /*!< UUART_T::PROTCTL: BRDETITV Mask */
#define UUART_PROTCTL_STICKEN_Pos (26) /*!< UUART_T::PROTCTL: STICKEN Position */
#define UUART_PROTCTL_STICKEN_Msk (0x1ul << UUART_PROTCTL_STICKEN_Pos) /*!< UUART_T::PROTCTL: STICKEN Mask */
#define UUART_PROTCTL_BCEN_Pos (29) /*!< UUART_T::PROTCTL: BCEN Position */
#define UUART_PROTCTL_BCEN_Msk (0x1ul << UUART_PROTCTL_BCEN_Pos) /*!< UUART_T::PROTCTL: BCEN Mask */
#define UUART_PROTCTL_PROTEN_Pos (31) /*!< UUART_T::PROTCTL: PROTEN Position */
#define UUART_PROTCTL_PROTEN_Msk (0x1ul << UUART_PROTCTL_PROTEN_Pos) /*!< UUART_T::PROTCTL: PROTEN Mask */
#define UUART_PROTIEN_ABRIEN_Pos (1) /*!< UUART_T::PROTIEN: ABRIEN Position */
#define UUART_PROTIEN_ABRIEN_Msk (0x1ul << UUART_PROTIEN_ABRIEN_Pos) /*!< UUART_T::PROTIEN: ABRIEN Mask */
#define UUART_PROTIEN_RLSIEN_Pos (2) /*!< UUART_T::PROTIEN: RLSIEN Position */
#define UUART_PROTIEN_RLSIEN_Msk (0x1ul << UUART_PROTIEN_RLSIEN_Pos) /*!< UUART_T::PROTIEN: RLSIEN Mask */
#define UUART_PROTSTS_TXSTIF_Pos (1) /*!< UUART_T::PROTSTS: TXSTIF Position */
#define UUART_PROTSTS_TXSTIF_Msk (0x1ul << UUART_PROTSTS_TXSTIF_Pos) /*!< UUART_T::PROTSTS: TXSTIF Mask */
#define UUART_PROTSTS_TXENDIF_Pos (2) /*!< UUART_T::PROTSTS: TXENDIF Position */
#define UUART_PROTSTS_TXENDIF_Msk (0x1ul << UUART_PROTSTS_TXENDIF_Pos) /*!< UUART_T::PROTSTS: TXENDIF Mask */
#define UUART_PROTSTS_RXSTIF_Pos (3) /*!< UUART_T::PROTSTS: RXSTIF Position */
#define UUART_PROTSTS_RXSTIF_Msk (0x1ul << UUART_PROTSTS_RXSTIF_Pos) /*!< UUART_T::PROTSTS: RXSTIF Mask */
#define UUART_PROTSTS_RXENDIF_Pos (4) /*!< UUART_T::PROTSTS: RXENDIF Position */
#define UUART_PROTSTS_RXENDIF_Msk (0x1ul << UUART_PROTSTS_RXENDIF_Pos) /*!< UUART_T::PROTSTS: RXENDIF Mask */
#define UUART_PROTSTS_PARITYERR_Pos (5) /*!< UUART_T::PROTSTS: PARITYERR Position */
#define UUART_PROTSTS_PARITYERR_Msk (0x1ul << UUART_PROTSTS_PARITYERR_Pos) /*!< UUART_T::PROTSTS: PARITYERR Mask */
#define UUART_PROTSTS_FRMERR_Pos (6) /*!< UUART_T::PROTSTS: FRMERR Position */
#define UUART_PROTSTS_FRMERR_Msk (0x1ul << UUART_PROTSTS_FRMERR_Pos) /*!< UUART_T::PROTSTS: FRMERR Mask */
#define UUART_PROTSTS_BREAK_Pos (7) /*!< UUART_T::PROTSTS: BREAK Position */
#define UUART_PROTSTS_BREAK_Msk (0x1ul << UUART_PROTSTS_BREAK_Pos) /*!< UUART_T::PROTSTS: BREAK Mask */
#define UUART_PROTSTS_ABRDETIF_Pos (9) /*!< UUART_T::PROTSTS: ABRDETIF Position */
#define UUART_PROTSTS_ABRDETIF_Msk (0x1ul << UUART_PROTSTS_ABRDETIF_Pos) /*!< UUART_T::PROTSTS: ABRDETIF Mask */
#define UUART_PROTSTS_RXBUSY_Pos (10) /*!< UUART_T::PROTSTS: RXBUSY Position */
#define UUART_PROTSTS_RXBUSY_Msk (0x1ul << UUART_PROTSTS_RXBUSY_Pos) /*!< UUART_T::PROTSTS: RXBUSY Mask */
#define UUART_PROTSTS_ABERRSTS_Pos (11) /*!< UUART_T::PROTSTS: ABERRSTS Position */
#define UUART_PROTSTS_ABERRSTS_Msk (0x1ul << UUART_PROTSTS_ABERRSTS_Pos) /*!< UUART_T::PROTSTS: ABERRSTS Mask */
#define UUART_PROTSTS_CTSSYNCLV_Pos (16) /*!< UUART_T::PROTSTS: CTSSYNCLV Position */
#define UUART_PROTSTS_CTSSYNCLV_Msk (0x1ul << UUART_PROTSTS_CTSSYNCLV_Pos) /*!< UUART_T::PROTSTS: CTSSYNCLV Mask */
#define UUART_PROTSTS_CTSLV_Pos (17) /*!< UUART_T::PROTSTS: CTSLV Position */
#define UUART_PROTSTS_CTSLV_Msk (0x1ul << UUART_PROTSTS_CTSLV_Pos) /*!< UUART_T::PROTSTS: CTSLV Mask */
/**@}*/ /* UUART_CONST */
/**@}*/ /* end of UUART register group */
/*---------------------- SPI Mode of USCI Controller -------------------------*/
/**
@addtogroup USPI SPI Mode of USCI Controller(USPI)
Memory Mapped Structure for USPI Controller
@{ */
typedef struct {
/**
* @var USPI_T::CTL
* Offset: 0x00 USCI Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[2:0] |FUNMODE |Function Mode
* | | |This bit field selects the protocol for this USCI controller
* | | |Selecting a protocol that is not available or a reserved combination disables the USCI
* | | |When switching between two protocols, the USCI has to be disabled before selecting a new protocol
* | | |Simultaneously, the USCI will be reset when user write 000 to FUNMODE.
* | | |000 = The USCI is disabled. All protocol related state machines are set to idle state.
* | | |001 = The SPI protocol is selected.
* | | |010 = The UART protocol is selected.
* | | |100 = The I2C protocol is selected.
* | | |Note: Other bit combinations are reserved.
* @var USPI_T::INTEN
* Offset: 0x04 USCI Interrupt Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1] |TXSTIEN |Transmit Start Interrupt Enable Bit
* | | |This bit enables the interrupt generation in case of a transmit start event.
* | | |0 = The transmit start interrupt is disabled.
* | | |1 = The transmit start interrupt is enabled.
* |[2] |TXENDIEN |Transmit End Interrupt Enable Bit
* | | |This bit enables the interrupt generation in case of a transmit finish event.
* | | |0 = The transmit finish interrupt is disabled.
* | | |1 = The transmit finish interrupt is enabled.
* |[3] |RXSTIEN |Receive Start Interrupt Enable Bit
* | | |This bit enables the interrupt generation in case of a receive start event.
* | | |0 = The receive start interrupt is disabled.
* | | |1 = The receive start interrupt is enabled.
* |[4] |RXENDIEN |Receive End Interrupt Enable Bit
* | | |This bit enables the interrupt generation in case of a receive finish event.
* | | |0 = The receive end interrupt is disabled.
* | | |1 = The receive end interrupt is enabled.
* @var USPI_T::BRGEN
* Offset: 0x08 USCI Baud Rate Generator Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |RCLKSEL |Reference Clock Source Selection
* | | |This bit selects the source of reference clock (fREF_CLK).
* | | |0 = Peripheral device clock fPCLK.
* | | |1 = Reserved.
* |[1] |PTCLKSEL |Protocol Clock Source Selection
* | | |This bit selects the source of protocol clock (fPROT_CLK).
* | | |0 = Reference clock fREF_CLK.
* | | |1 = fREF_CLK2 (its frequency is half of fREF_CLK).
* |[3:2] |SPCLKSEL |Sample Clock Source Selection
* | | |This bit field used for the clock source selection of sample clock (fSAMP_CLK) for the protocol processor.
* | | |00 = fDIV_CLK.
* | | |01 = fPROT_CLK.
* | | |10 = fSCLK.
* | | |11 = fREF_CLK.
* |[4] |TMCNTEN |Time Measurement Counter Enable Bit
* | | |This bit enables the 10-bit timing measurement counter.
* | | |0 = Time measurement counter is Disabled.
* | | |1 = Time measurement counter is Enabled.
* |[5] |TMCNTSRC |Time Measurement Counter Clock Source Selection
* | | |0 = Time measurement counter with fPROT_CLK.
* | | |1 = Time measurement counter with fDIV_CLK.
* |[25:16] |CLKDIV |Clock Divider
* | | |This bit field defines the ratio between the protocol clock frequency fPROT_CLK and the clock divider frequency fDIV_CLK (fDIV_CLK = fPROT_CLK / (CLKDIV+1) ).
* | | |Note: In UART function, it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(USPI_PROTCTL[6])) is enabled
* | | |The revised value is the average bit time between bit 5 and bit 6
* | | |The user can use revised CLKDIV and new BRDETITV (USPI_PROTCTL[24:16]) to calculate the precise baud rate.
* @var USPI_T::DATIN0
* Offset: 0x10 USCI Input Data Signal Configuration Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SYNCSEL |Input Signal Synchronization Selection
* | | |This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.
* | | |0 = The un-synchronized signal can be taken as input for the data shift unit.
* | | |1 = The synchronized signal can be taken as input for the data shift unit.
* | | |Note: In SPI protocol, we suggest this bit should be set as 0.
* |[2] |ININV |Input Signal Inverse Selection
* | | |This bit defines the inverter enable of the input asynchronous signal.
* | | |0 = The un-synchronized input signal will not be inverted.
* | | |1 = The un-synchronized input signal will be inverted.
* | | |Note: In SPI protocol, we suggest this bit should be set as 0.
* @var USPI_T::CTLIN0
* Offset: 0x20 USCI Input Control Signal Configuration Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SYNCSEL |Input Synchronization Signal Selection
* | | |This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.
* | | |0 = The un-synchronized signal can be taken as input for the data shift unit.
* | | |1 = The synchronized signal can be taken as input for the data shift unit.
* | | |Note: In SPI protocol, we suggest this bit should be set as 0.
* |[2] |ININV |Input Signal Inverse Selection
* | | |This bit defines the inverter enable of the input asynchronous signal.
* | | |0 = The un-synchronized input signal will not be inverted.
* | | |1 = The un-synchronized input signal will be inverted.
* @var USPI_T::CLKIN
* Offset: 0x28 USCI Input Clock Signal Configuration Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SYNCSEL |Input Synchronization Signal Selection
* | | |This bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.
* | | |0 = The un-synchronized signal can be taken as input for the data shift unit.
* | | |1 = The synchronized signal can be taken as input for the data shift unit.
* | | |Note: In SPI protocol, we suggest this bit should be set as 0.
* @var USPI_T::LINECTL
* Offset: 0x2C USCI Line Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |LSB |LSB First Transmission Selection
* | | |0 = The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first.
* | | |1 = The LSB, the bit 0 of data buffer, will be transmitted/received first.
* |[5] |DATOINV |Data Output Inverse Selection
* | | |This bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT0/1 pin.
* | | |0 = Data output level is not inverted.
* | | |1 = Data output level is inverted.
* |[7] |CTLOINV |Control Signal Output Inverse Selection
* | | |This bit defines the relation between the internal control signal and the output control signal.
* | | |0 = No effect.
* | | |1 = The control signal will be inverted before its output.
* | | |Note: The control signal has different definitions in different protocol
* | | |In SPI protocol, the control signal means slave select signal
* |[11:8] |DWIDTH |Word Length of Transmission
* | | |This bit field defines the data word length (amount of bits) for reception and transmission
* | | |The data word is always right-aligned in the data buffer
* | | |USCI support word length from 4 to 16 bits.
* | | |0x0: The data word contains 16 bits located at bit positions [15:0].
* | | |0x1: Reserved.
* | | |0x2: Reserved.
* | | |0x3: Reserved.
* | | |0x4: The data word contains 4 bits located at bit positions [3:0].
* | | |0x5: The data word contains 5 bits located at bit positions [4:0].
* | | |...
* | | |0xF: The data word contains 15 bits located at bit positions [14:0].
* @var USPI_T::TXDAT
* Offset: 0x30 USCI Transmit Data Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |TXDAT |Transmit Data
* | | |Software can use this bit field to write 16-bit transmit data for transmission
* | | |In order to avoid overwriting the transmit data, user have to check TXEMPTY (USPI_BUFSTS[8]) status before writing transmit data into this bit field.
* |[16] |PORTDIR |Port Direction Control
* | | |This bit field is only available while USCI operates in SPI protocol (FUNMODE = 0x1) with half-duplex transfer
* | | |It is used to define the direction of the data port pin
* | | |When software writes USPI_TXDAT register, the transmit data and its port direction are settled simultaneously.
* | | |0 = The data pin is configured as output mode.
* | | |1 = The data pin is configured as input mode.
* @var USPI_T::RXDAT
* Offset: 0x34 USCI Receive Data Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |RXDAT |Received Data
* | | |This bit field monitors the received data which stored in receive data buffer.
* @var USPI_T::BUFCTL
* Offset: 0x38 USCI Transmit/Receive Buffer Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[6] |TXUDRIEN |Slave Transmit Under Run Interrupt Enable Bit
* | | |0 = Transmit under-run interrupt Disabled.
* | | |1 = Transmit under-run interrupt Enabled.
* |[7] |TXCLR |Clear Transmit Buffer
* | | |0 = No effect.
* | | |1 = The transmit buffer is cleared
* | | |Should only be used while the buffer is not taking part in data traffic.
* | | |Note: It is cleared automatically after one PCLK cycle.
* |[14] |RXOVIEN |Receive Buffer Overrun Interrupt Enable Bit
* | | |0 = Receive overrun interrupt Disabled.
* | | |1 = Receive overrun interrupt Enabled.
* |[15] |RXCLR |Clear Receive Buffer
* | | |0 = No effect.
* | | |1 = The receive buffer is cleared
* | | |Should only be used while the buffer is not taking part in data traffic.
* | | |Note: It is cleared automatically after one PCLK cycle.
* |[16] |TXRST |Transmit Reset
* | | |0 = No effect.
* | | |1 = Reset the transmit-related counters, state machine, and the content of transmit shift register and data buffer.
* | | |Note: It is cleared automatically after one PCLK cycle.
* |[17] |RXRST |Receive Reset
* | | |0 = No effect.
* | | |1 = Reset the receive-related counters, state machine, and the content of receive shift register and data buffer.
* | | |Note: It is cleared automatically after one PCLK cycle.
* @var USPI_T::BUFSTS
* Offset: 0x3C USCI Transmit/Receive Buffer Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |RXEMPTY |Receive Buffer Empty Indicator
* | | |0 = Receive buffer is not empty.
* | | |1 = Receive buffer is empty.
* |[1] |RXFULL |Receive Buffer Full Indicator
* | | |0 = Receive buffer is not full.
* | | |1 = Receive buffer is full.
* |[3] |RXOVIF |Receive Buffer Over-run Interrupt Status
* | | |This bit indicates that a receive buffer overrun event has been detected
* | | |If RXOVIEN (USPI_BUFCTL[14]) is enabled, the corresponding interrupt request is activated
* | | |It is cleared by software writes 1 to this bit.
* | | |0 = A receive buffer overrun event has not been detected.
* | | |1 = A receive buffer overrun event has been detected.
* |[8] |TXEMPTY |Transmit Buffer Empty Indicator
* | | |0 = Transmit buffer is not empty.
* | | |1 = Transmit buffer is empty and available for the next transmission datum.
* |[9] |TXFULL |Transmit Buffer Full Indicator
* | | |0 = Transmit buffer is not full.
* | | |1 = Transmit buffer is full.
* |[11] |TXUDRIF |Transmit Buffer Under-run Interrupt Status
* | | |This bit indicates that a transmit buffer under-run event has been detected
* | | |If enabled by TXUDRIEN (USPI_BUFCTL[6]), the corresponding interrupt request is activated
* | | |It is cleared by software writes 1 to this bit
* | | |0 = A transmit buffer under-run event has not been detected.
* | | |1 = A transmit buffer under-run event has been detected.
* @var USPI_T::PDMACTL
* Offset: 0x40 USCI PDMA Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |PDMARST |PDMA Reset
* | | |0 = No effect.
* | | |1 = Reset the USCI's PDMA control logic. This bit will be cleared to 0 automatically.
* |[1] |TXPDMAEN |PDMA Transmit Channel Available
* | | |0 = Transmit PDMA function Disabled.
* | | |1 = Transmit PDMA function Enabled.
* |[2] |RXPDMAEN |PDMA Receive Channel Available
* | | |0 = Receive PDMA function Disabled.
* | | |1 = Receive PDMA function Enabled.
* |[3] |PDMAEN |PDMA Mode Enable Bit
* | | |0 = PDMA function Disabled.
* | | |1 = PDMA function Enabled.
* | | |Notice: The I2C is not supporting PDMA function.
* @var USPI_T::WKCTL
* Offset: 0x54 USCI Wake-up Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |WKEN |Wake-up Enable Bit
* | | |0 = Wake-up function Disabled.
* | | |1 = Wake-up function Enabled.
* |[1] |WKADDREN |Wake-up Address Match Enable Bit
* | | |0 = The chip is woken up according data toggle.
* | | |1 = The chip is woken up according address match.
* |[2] |PDBOPT |Power Down Blocking Option
* | | |0 = If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, MCU will stop the transfer and enter Power-down mode immediately.
* | | |1 = If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, the on-going transfer will not be stopped and MCU will enter idle mode immediately.
* @var USPI_T::WKSTS
* Offset: 0x58 USCI Wake-up Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |WKF |Wake-up Flag
* | | |When chip is woken up from Power-down mode, this bit is set to 1
* | | |Software can write 1 to clear this bit.
* @var USPI_T::PROTCTL
* Offset: 0x5C USCI Protocol Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SLAVE |Slave Mode Selection
* | | |0 = Master mode.
* | | |1 = Slave mode.
* |[1] |SLV3WIRE |Slave 3-wire Mode Selection (Slave Only)
* | | |The SPI protocol can work with 3-wire interface (without slave select signal) in Slave mode.
* | | |0 = 4-wire bi-direction interface.
* | | |1 = 3-wire bi-direction interface.
* |[2] |SS |Slave Select Control (Master Only)
* | | |If AUTOSS bit is cleared, setting this bit to 1 will set the slave select signal to active state, and setting this bit to 0 will set the slave select signal back to inactive state.
* | | |If the AUTOSS function is enabled (AUTOSS = 1), the setting value of this bit will not affect the current state of slave select signal.
* | | |Note: In SPI protocol, the internal slave select signal is active high.
* |[3] |AUTOSS |Automatic Slave Select Function Enable (Master Only)
* | | |0 = Slave select signal will be controlled by the setting value of SS (USPI_PROTCTL[2]) bit.
* | | |1 = Slave select signal will be generated automatically
* | | |The slave select signal will be asserted by the SPI controller when transmit/receive is started, and will be de-asserted after each transmit/receive is finished.
* |[7:6] |SCLKMODE |Serial Bus Clock Mode
* | | |This bit field defines the SCLK idle status, data transmit, and data receive edge.
* | | |MODE0 = The idle state of SPI clock is low level
* | | |Data is transmitted with falling edge and received with rising edge.
* | | |MODE1 = The idle state of SPI clock is low level
* | | |Data is transmitted with rising edge and received with falling edge.
* | | |MODE2 = The idle state of SPI clock is high level
* | | |Data is transmitted with rising edge and received with falling edge.
* | | |MODE3 = The idle state of SPI clock is high level
* | | |Data is transmitted with falling edge and received with rising edge.
* |[11:8] |SUSPITV |Suspend Interval (Master Only)
* | | |This bit field provides the configurable suspend interval between two successive transmit/receive transaction in a transfer
* | | |The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word
* | | |The default value is 0x3
* | | |The period of the suspend interval is obtained according to the following equation.
* | | |(SUSPITV[3:0] + 0.5) * period of SPI_CLK clock cycle
* | | |Example:
* | | |SUSPITV = 0x0 ... 0.5 SPI_CLK clock cycle.
* | | |SUSPITV = 0x1 ... 1.5 SPI_CLK clock cycle.
* | | |.....
* | | |SUSPITV = 0xE ... 14.5 SPI_CLK clock cycle.
* | | |SUSPITV = 0xF ... 15.5 SPI_CLK clock cycle.
* |[14:12] |TSMSEL |Transmit Data Mode Selection
* | | |This bit field describes how receive and transmit data is shifted in and out.
* | | |TSMSEL = 000b: Full-duplex SPI.
* | | |TSMSEL = 100b: Half-duplex SPI.
* | | |Other values are reserved.
* | | |Note: Changing the value of this bit field will produce the TXRST and RXRST to clear the TX/RX data buffer automatically.
* |[25:16] |SLVTOCNT |Slave Mode Time-out Period (Slave Only)
* | | |In Slave mode, this bit field is used for Slave time-out period
* | | |This bit field indicates how many clock periods (selected by TMCNTSRC, USPI_BRGEN[5]) between the two edges of input SCLK will assert the Slave time-out event
* | | |Writing 0x0 into this bit field will disable the Slave time-out function.
* | | |Example: Assume SLVTOCNT is 0x0A and TMCNTSRC (USPI_BRGEN[5]) is 1, it means the time-out event will occur if the state of SPI bus clock pin is not changed more than (10+1) periods of fDIV_CLK.
* |[28] |TXUDRPOL |Transmit Under-run Data Polarity (for Slave)
* | | |This bit defines the transmitting data level when no data is available for transferring.
* | | |0 = The output data level is 0 if TX under run event occurs.
* | | |1 = The output data level is 1 if TX under run event occurs.
* |[31] |PROTEN |SPI Protocol Enable Bit
* | | |0 = SPI Protocol Disabled.
* | | |1 = SPI Protocol Enabled.
* @var USPI_T::PROTIEN
* Offset: 0x60 USCI Protocol Interrupt Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SSINAIEN |Slave Select Inactive Interrupt Enable Control
* | | |This bit enables/disables the generation of a slave select interrupt if the slave select changes to inactive.
* | | |0 = Slave select inactive interrupt generation Disabled.
* | | |1 = Slave select inactive interrupt generation Enabled.
* |[1] |SSACTIEN |Slave Select Active Interrupt Enable Control
* | | |This bit enables/disables the generation of a slave select interrupt if the slave select changes to active.
* | | |0 = Slave select active interrupt generation Disabled.
* | | |1 = Slave select active interrupt generation Enabled.
* |[2] |SLVTOIEN |Slave Time-out Interrupt Enable Control
* | | |In SPI protocol, this bit enables the interrupt generation in case of a Slave time-out event.
* | | |0 = The Slave time-out interrupt Disabled.
* | | |1 = The Slave time-out interrupt Enabled.
* |[3] |SLVBEIEN |Slave Mode Bit Count Error Interrupt Enable Control
* | | |If data transfer is terminated by slave time-out or slave select inactive event in Slave mode, so that the transmit/receive data bit count does not match the setting of DWIDTH (USPI_LINECTL[11:8])
* | | |Bit count error event occurs.
* | | |0 = The Slave mode bit count error interrupt Disabled.
* | | |1 = The Slave mode bit count error interrupt Enabled.
* @var USPI_T::PROTSTS
* Offset: 0x64 USCI Protocol Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1] |TXSTIF |Transmit Start Interrupt Flag
* | | |0 = Transmit start event does not occur.
* | | |1 = Transmit start event occurs.
* | | |Note: It is cleared by software writes 1 to this bit
* |[2] |TXENDIF |Transmit End Interrupt Flag
* | | |0 = Transmit end event does not occur.
* | | |1 = Transmit end event occurs.
* | | |Note: It is cleared by software writes 1 to this bit
* |[3] |RXSTIF |Receive Start Interrupt Flag
* | | |0 = Receive start event does not occur.
* | | |1 = Receive start event occurs.
* | | |Note: It is cleared by software writes 1 to this bit
* |[4] |RXENDIF |Receive End Interrupt Flag
* | | |0 = Receive end event does not occur.
* | | |1 = Receive end event occurs.
* | | |Note: It is cleared by software writes 1 to this bit
* |[5] |SLVTOIF |Slave Time-out Interrupt Flag (for Slave Only)
* | | |0 = Slave time-out event does not occur.
* | | |1 = Slave time-out event occurs.
* | | |Note: It is cleared by software writes 1 to this bit
* |[6] |SLVBEIF |Slave Bit Count Error Interrupt Flag (for Slave Only)
* | | |0 = Slave bit count error event does not occur.
* | | |1 = Slave bit count error event occurs.
* | | |Note: It is cleared by software writes 1 to this bit.
* |[8] |SSINAIF |Slave Select Inactive Interrupt Flag (for Slave Only)
* | | |This bit indicates that the internal slave select signal has changed to inactive
* | | |It is cleared by software writes 1 to this bit
* | | |0 = The slave select signal has not changed to inactive.
* | | |1 = The slave select signal has changed to inactive.
* | | |Note: The internal slave select signal is active high.
* |[9] |SSACTIF |Slave Select Active Interrupt Flag (for Slave Only)
* | | |This bit indicates that the internal slave select signal has changed to active
* | | |It is cleared by software writes one to this bit
* | | |0 = The slave select signal has not changed to active.
* | | |1 = The slave select signal has changed to active.
* | | |Note: The internal slave select signal is active high.
* |[16] |SSLINE |Slave Select Line Bus Status (Read Only)
* | | |This bit is only available in Slave mode
* | | |It used to monitor the current status of the input slave select signal on the bus.
* | | |0 = The slave select line status is 0.
* | | |1 = The slave select line status is 1.
* |[17] |BUSY |Busy Status (Read Only)
* | | |0 = SPI is in idle state.
* | | |1 = SPI is in busy state.
* | | |The following listing are the bus busy conditions:
* | | |a. USPI_PROTCTL[31] = 1 and the TXEMPTY = 0.
* | | |b. For SPI Master mode, the TXEMPTY = 1 but the current transaction is not finished yet.
* | | |c
* | | |For SPI Slave mode, the USPI_PROTCTL[31] = 1 and there is serial clock input into the SPI core logic when slave select is active.
* | | |d
* | | |For SPI Slave mode, the USPI_PROTCTL[31] = 1 and the transmit buffer or transmit shift register is not empty even if the slave select is inactive.
* |[18] |SLVUDR |Slave Mode Transmit Under-run Status (Read Only)
* | | |In Slave mode, if there is no available transmit data in buffer while transmit data shift out caused by input serial bus clock, this status flag will be set to 1
* | | |This bit indicates whether the current shift-out data of word transmission is switched to TXUDRPOL (USPI_PROTCTL[28]) or not.
* | | |0 = Slave transmit under-run event does not occur.
* | | |1 = Slave transmit under-run event occurs.
*/
__IO uint32_t CTL; /*!< [0x0000] USCI Control Register */
__IO uint32_t INTEN; /*!< [0x0004] USCI Interrupt Enable Register */
__IO uint32_t BRGEN; /*!< [0x0008] USCI Baud Rate Generator Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE0[1];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t DATIN0; /*!< [0x0010] USCI Input Data Signal Configuration Register 0 */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE1[3];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t CTLIN0; /*!< [0x0020] USCI Input Control Signal Configuration Register 0 */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE2[1];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t CLKIN; /*!< [0x0028] USCI Input Clock Signal Configuration Register */
__IO uint32_t LINECTL; /*!< [0x002c] USCI Line Control Register */
__O uint32_t TXDAT; /*!< [0x0030] USCI Transmit Data Register */
__I uint32_t RXDAT; /*!< [0x0034] USCI Receive Data Register */
__IO uint32_t BUFCTL; /*!< [0x0038] USCI Transmit/Receive Buffer Control Register */
__IO uint32_t BUFSTS; /*!< [0x003c] USCI Transmit/Receive Buffer Status Register */
__IO uint32_t PDMACTL; /*!< [0x0040] USCI PDMA Control Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE3[4];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t WKCTL; /*!< [0x0054] USCI Wake-up Control Register */
__IO uint32_t WKSTS; /*!< [0x0058] USCI Wake-up Status Register */
__IO uint32_t PROTCTL; /*!< [0x005c] USCI Protocol Control Register */
__IO uint32_t PROTIEN; /*!< [0x0060] USCI Protocol Interrupt Enable Register */
__IO uint32_t PROTSTS; /*!< [0x0064] USCI Protocol Status Register */
} USPI_T;
/**
@addtogroup USPI_CONST USPI Bit Field Definition
Constant Definitions for USPI Controller
@{ */
#define USPI_CTL_FUNMODE_Pos (0) /*!< USPI_T::CTL: FUNMODE Position */
#define USPI_CTL_FUNMODE_Msk (0x7ul << USPI_CTL_FUNMODE_Pos) /*!< USPI_T::CTL: FUNMODE Mask */
#define USPI_INTEN_TXSTIEN_Pos (1) /*!< USPI_T::INTEN: TXSTIEN Position */
#define USPI_INTEN_TXSTIEN_Msk (0x1ul << USPI_INTEN_TXSTIEN_Pos) /*!< USPI_T::INTEN: TXSTIEN Mask */
#define USPI_INTEN_TXENDIEN_Pos (2) /*!< USPI_T::INTEN: TXENDIEN Position */
#define USPI_INTEN_TXENDIEN_Msk (0x1ul << USPI_INTEN_TXENDIEN_Pos) /*!< USPI_T::INTEN: TXENDIEN Mask */
#define USPI_INTEN_RXSTIEN_Pos (3) /*!< USPI_T::INTEN: RXSTIEN Position */
#define USPI_INTEN_RXSTIEN_Msk (0x1ul << USPI_INTEN_RXSTIEN_Pos) /*!< USPI_T::INTEN: RXSTIEN Mask */
#define USPI_INTEN_RXENDIEN_Pos (4) /*!< USPI_T::INTEN: RXENDIEN Position */
#define USPI_INTEN_RXENDIEN_Msk (0x1ul << USPI_INTEN_RXENDIEN_Pos) /*!< USPI_T::INTEN: RXENDIEN Mask */
#define USPI_BRGEN_RCLKSEL_Pos (0) /*!< USPI_T::BRGEN: RCLKSEL Position */
#define USPI_BRGEN_RCLKSEL_Msk (0x1ul << USPI_BRGEN_RCLKSEL_Pos) /*!< USPI_T::BRGEN: RCLKSEL Mask */
#define USPI_BRGEN_PTCLKSEL_Pos (1) /*!< USPI_T::BRGEN: PTCLKSEL Position */
#define USPI_BRGEN_PTCLKSEL_Msk (0x1ul << USPI_BRGEN_PTCLKSEL_Pos) /*!< USPI_T::BRGEN: PTCLKSEL Mask */
#define USPI_BRGEN_SPCLKSEL_Pos (2) /*!< USPI_T::BRGEN: SPCLKSEL Position */
#define USPI_BRGEN_SPCLKSEL_Msk (0x3ul << USPI_BRGEN_SPCLKSEL_Pos) /*!< USPI_T::BRGEN: SPCLKSEL Mask */
#define USPI_BRGEN_TMCNTEN_Pos (4) /*!< USPI_T::BRGEN: TMCNTEN Position */
#define USPI_BRGEN_TMCNTEN_Msk (0x1ul << USPI_BRGEN_TMCNTEN_Pos) /*!< USPI_T::BRGEN: TMCNTEN Mask */
#define USPI_BRGEN_TMCNTSRC_Pos (5) /*!< USPI_T::BRGEN: TMCNTSRC Position */
#define USPI_BRGEN_TMCNTSRC_Msk (0x1ul << USPI_BRGEN_TMCNTSRC_Pos) /*!< USPI_T::BRGEN: TMCNTSRC Mask */
#define USPI_BRGEN_CLKDIV_Pos (16) /*!< USPI_T::BRGEN: CLKDIV Position */
#define USPI_BRGEN_CLKDIV_Msk (0x3fful << USPI_BRGEN_CLKDIV_Pos) /*!< USPI_T::BRGEN: CLKDIV Mask */
#define USPI_DATIN0_SYNCSEL_Pos (0) /*!< USPI_T::DATIN0: SYNCSEL Position */
#define USPI_DATIN0_SYNCSEL_Msk (0x1ul << USPI_DATIN0_SYNCSEL_Pos) /*!< USPI_T::DATIN0: SYNCSEL Mask */
#define USPI_DATIN0_ININV_Pos (2) /*!< USPI_T::DATIN0: ININV Position */
#define USPI_DATIN0_ININV_Msk (0x1ul << USPI_DATIN0_ININV_Pos) /*!< USPI_T::DATIN0: ININV Mask */
#define USPI_CTLIN0_SYNCSEL_Pos (0) /*!< USPI_T::CTLIN0: SYNCSEL Position */
#define USPI_CTLIN0_SYNCSEL_Msk (0x1ul << USPI_CTLIN0_SYNCSEL_Pos) /*!< USPI_T::CTLIN0: SYNCSEL Mask */
#define USPI_CTLIN0_ININV_Pos (2) /*!< USPI_T::CTLIN0: ININV Position */
#define USPI_CTLIN0_ININV_Msk (0x1ul << USPI_CTLIN0_ININV_Pos) /*!< USPI_T::CTLIN0: ININV Mask */
#define USPI_CLKIN_SYNCSEL_Pos (0) /*!< USPI_T::CLKIN: SYNCSEL Position */
#define USPI_CLKIN_SYNCSEL_Msk (0x1ul << USPI_CLKIN_SYNCSEL_Pos) /*!< USPI_T::CLKIN: SYNCSEL Mask */
#define USPI_LINECTL_LSB_Pos (0) /*!< USPI_T::LINECTL: LSB Position */
#define USPI_LINECTL_LSB_Msk (0x1ul << USPI_LINECTL_LSB_Pos) /*!< USPI_T::LINECTL: LSB Mask */
#define USPI_LINECTL_DATOINV_Pos (5) /*!< USPI_T::LINECTL: DATOINV Position */
#define USPI_LINECTL_DATOINV_Msk (0x1ul << USPI_LINECTL_DATOINV_Pos) /*!< USPI_T::LINECTL: DATOINV Mask */
#define USPI_LINECTL_CTLOINV_Pos (7) /*!< USPI_T::LINECTL: CTLOINV Position */
#define USPI_LINECTL_CTLOINV_Msk (0x1ul << USPI_LINECTL_CTLOINV_Pos) /*!< USPI_T::LINECTL: CTLOINV Mask */
#define USPI_LINECTL_DWIDTH_Pos (8) /*!< USPI_T::LINECTL: DWIDTH Position */
#define USPI_LINECTL_DWIDTH_Msk (0xful << USPI_LINECTL_DWIDTH_Pos) /*!< USPI_T::LINECTL: DWIDTH Mask */
#define USPI_TXDAT_TXDAT_Pos (0) /*!< USPI_T::TXDAT: TXDAT Position */
#define USPI_TXDAT_TXDAT_Msk (0xfffful << USPI_TXDAT_TXDAT_Pos) /*!< USPI_T::TXDAT: TXDAT Mask */
#define USPI_TXDAT_PORTDIR_Pos (16) /*!< USPI_T::TXDAT: PORTDIR Position */
#define USPI_TXDAT_PORTDIR_Msk (0x1ul << USPI_TXDAT_PORTDIR_Pos) /*!< USPI_T::TXDAT: PORTDIR Mask */
#define USPI_RXDAT_RXDAT_Pos (0) /*!< USPI_T::RXDAT: RXDAT Position */
#define USPI_RXDAT_RXDAT_Msk (0xfffful << USPI_RXDAT_RXDAT_Pos) /*!< USPI_T::RXDAT: RXDAT Mask */
#define USPI_BUFCTL_TXUDRIEN_Pos (6) /*!< USPI_T::BUFCTL: TXUDRIEN Position */
#define USPI_BUFCTL_TXUDRIEN_Msk (0x1ul << USPI_BUFCTL_TXUDRIEN_Pos) /*!< USPI_T::BUFCTL: TXUDRIEN Mask */
#define USPI_BUFCTL_TXCLR_Pos (7) /*!< USPI_T::BUFCTL: TXCLR Position */
#define USPI_BUFCTL_TXCLR_Msk (0x1ul << USPI_BUFCTL_TXCLR_Pos) /*!< USPI_T::BUFCTL: TXCLR Mask */
#define USPI_BUFCTL_RXOVIEN_Pos (14) /*!< USPI_T::BUFCTL: RXOVIEN Position */
#define USPI_BUFCTL_RXOVIEN_Msk (0x1ul << USPI_BUFCTL_RXOVIEN_Pos) /*!< USPI_T::BUFCTL: RXOVIEN Mask */
#define USPI_BUFCTL_RXCLR_Pos (15) /*!< USPI_T::BUFCTL: RXCLR Position */
#define USPI_BUFCTL_RXCLR_Msk (0x1ul << USPI_BUFCTL_RXCLR_Pos) /*!< USPI_T::BUFCTL: RXCLR Mask */
#define USPI_BUFCTL_TXRST_Pos (16) /*!< USPI_T::BUFCTL: TXRST Position */
#define USPI_BUFCTL_TXRST_Msk (0x1ul << USPI_BUFCTL_TXRST_Pos) /*!< USPI_T::BUFCTL: TXRST Mask */
#define USPI_BUFCTL_RXRST_Pos (17) /*!< USPI_T::BUFCTL: RXRST Position */
#define USPI_BUFCTL_RXRST_Msk (0x1ul << USPI_BUFCTL_RXRST_Pos) /*!< USPI_T::BUFCTL: RXRST Mask */
#define USPI_BUFSTS_RXEMPTY_Pos (0) /*!< USPI_T::BUFSTS: RXEMPTY Position */
#define USPI_BUFSTS_RXEMPTY_Msk (0x1ul << USPI_BUFSTS_RXEMPTY_Pos) /*!< USPI_T::BUFSTS: RXEMPTY Mask */
#define USPI_BUFSTS_RXFULL_Pos (1) /*!< USPI_T::BUFSTS: RXFULL Position */
#define USPI_BUFSTS_RXFULL_Msk (0x1ul << USPI_BUFSTS_RXFULL_Pos) /*!< USPI_T::BUFSTS: RXFULL Mask */
#define USPI_BUFSTS_RXOVIF_Pos (3) /*!< USPI_T::BUFSTS: RXOVIF Position */
#define USPI_BUFSTS_RXOVIF_Msk (0x1ul << USPI_BUFSTS_RXOVIF_Pos) /*!< USPI_T::BUFSTS: RXOVIF Mask */
#define USPI_BUFSTS_TXEMPTY_Pos (8) /*!< USPI_T::BUFSTS: TXEMPTY Position */
#define USPI_BUFSTS_TXEMPTY_Msk (0x1ul << USPI_BUFSTS_TXEMPTY_Pos) /*!< USPI_T::BUFSTS: TXEMPTY Mask */
#define USPI_BUFSTS_TXFULL_Pos (9) /*!< USPI_T::BUFSTS: TXFULL Position */
#define USPI_BUFSTS_TXFULL_Msk (0x1ul << USPI_BUFSTS_TXFULL_Pos) /*!< USPI_T::BUFSTS: TXFULL Mask */
#define USPI_BUFSTS_TXUDRIF_Pos (11) /*!< USPI_T::BUFSTS: TXUDRIF Position */
#define USPI_BUFSTS_TXUDRIF_Msk (0x1ul << USPI_BUFSTS_TXUDRIF_Pos) /*!< USPI_T::BUFSTS: TXUDRIF Mask */
#define USPI_PDMACTL_PDMARST_Pos (0) /*!< USPI_T::PDMACTL: PDMARST Position */
#define USPI_PDMACTL_PDMARST_Msk (0x1ul << USPI_PDMACTL_PDMARST_Pos) /*!< USPI_T::PDMACTL: PDMARST Mask */
#define USPI_PDMACTL_TXPDMAEN_Pos (1) /*!< USPI_T::PDMACTL: TXPDMAEN Position */
#define USPI_PDMACTL_TXPDMAEN_Msk (0x1ul << USPI_PDMACTL_TXPDMAEN_Pos) /*!< USPI_T::PDMACTL: TXPDMAEN Mask */
#define USPI_PDMACTL_RXPDMAEN_Pos (2) /*!< USPI_T::PDMACTL: RXPDMAEN Position */
#define USPI_PDMACTL_RXPDMAEN_Msk (0x1ul << USPI_PDMACTL_RXPDMAEN_Pos) /*!< USPI_T::PDMACTL: RXPDMAEN Mask */
#define USPI_PDMACTL_PDMAEN_Pos (3) /*!< USPI_T::PDMACTL: PDMAEN Position */
#define USPI_PDMACTL_PDMAEN_Msk (0x1ul << USPI_PDMACTL_PDMAEN_Pos) /*!< USPI_T::PDMACTL: PDMAEN Mask */
#define USPI_WKCTL_WKEN_Pos (0) /*!< USPI_T::WKCTL: WKEN Position */
#define USPI_WKCTL_WKEN_Msk (0x1ul << USPI_WKCTL_WKEN_Pos) /*!< USPI_T::WKCTL: WKEN Mask */
#define USPI_WKCTL_WKADDREN_Pos (1) /*!< USPI_T::WKCTL: WKADDREN Position */
#define USPI_WKCTL_WKADDREN_Msk (0x1ul << USPI_WKCTL_WKADDREN_Pos) /*!< USPI_T::WKCTL: WKADDREN Mask */
#define USPI_WKCTL_PDBOPT_Pos (2) /*!< USPI_T::WKCTL: PDBOPT Position */
#define USPI_WKCTL_PDBOPT_Msk (0x1ul << USPI_WKCTL_PDBOPT_Pos) /*!< USPI_T::WKCTL: PDBOPT Mask */
#define USPI_WKSTS_WKF_Pos (0) /*!< USPI_T::WKSTS: WKF Position */
#define USPI_WKSTS_WKF_Msk (0x1ul << USPI_WKSTS_WKF_Pos) /*!< USPI_T::WKSTS: WKF Mask */
#define USPI_PROTCTL_SLAVE_Pos (0) /*!< USPI_T::PROTCTL: SLAVE Position */
#define USPI_PROTCTL_SLAVE_Msk (0x1ul << USPI_PROTCTL_SLAVE_Pos) /*!< USPI_T::PROTCTL: SLAVE Mask */
#define USPI_PROTCTL_SLV3WIRE_Pos (1) /*!< USPI_T::PROTCTL: SLV3WIRE Position */
#define USPI_PROTCTL_SLV3WIRE_Msk (0x1ul << USPI_PROTCTL_SLV3WIRE_Pos) /*!< USPI_T::PROTCTL: SLV3WIRE Mask */
#define USPI_PROTCTL_SS_Pos (2) /*!< USPI_T::PROTCTL: SS Position */
#define USPI_PROTCTL_SS_Msk (0x1ul << USPI_PROTCTL_SS_Pos) /*!< USPI_T::PROTCTL: SS Mask */
#define USPI_PROTCTL_AUTOSS_Pos (3) /*!< USPI_T::PROTCTL: AUTOSS Position */
#define USPI_PROTCTL_AUTOSS_Msk (0x1ul << USPI_PROTCTL_AUTOSS_Pos) /*!< USPI_T::PROTCTL: AUTOSS Mask */
#define USPI_PROTCTL_SCLKMODE_Pos (6) /*!< USPI_T::PROTCTL: SCLKMODE Position */
#define USPI_PROTCTL_SCLKMODE_Msk (0x3ul << USPI_PROTCTL_SCLKMODE_Pos) /*!< USPI_T::PROTCTL: SCLKMODE Mask */
#define USPI_PROTCTL_SUSPITV_Pos (8) /*!< USPI_T::PROTCTL: SUSPITV Position */
#define USPI_PROTCTL_SUSPITV_Msk (0xful << USPI_PROTCTL_SUSPITV_Pos) /*!< USPI_T::PROTCTL: SUSPITV Mask */
#define USPI_PROTCTL_TSMSEL_Pos (12) /*!< USPI_T::PROTCTL: TSMSEL Position */
#define USPI_PROTCTL_TSMSEL_Msk (0x7ul << USPI_PROTCTL_TSMSEL_Pos) /*!< USPI_T::PROTCTL: TSMSEL Mask */
#define USPI_PROTCTL_SLVTOCNT_Pos (16) /*!< USPI_T::PROTCTL: SLVTOCNT Position */
#define USPI_PROTCTL_SLVTOCNT_Msk (0x3fful << USPI_PROTCTL_SLVTOCNT_Pos) /*!< USPI_T::PROTCTL: SLVTOCNT Mask */
#define USPI_PROTCTL_TXUDRPOL_Pos (28) /*!< USPI_T::PROTCTL: TXUDRPOL Position */
#define USPI_PROTCTL_TXUDRPOL_Msk (0x1ul << USPI_PROTCTL_TXUDRPOL_Pos) /*!< USPI_T::PROTCTL: TXUDRPOL Mask */
#define USPI_PROTCTL_PROTEN_Pos (31) /*!< USPI_T::PROTCTL: PROTEN Position */
#define USPI_PROTCTL_PROTEN_Msk (0x1ul << USPI_PROTCTL_PROTEN_Pos) /*!< USPI_T::PROTCTL: PROTEN Mask */
#define USPI_PROTIEN_SSINAIEN_Pos (0) /*!< USPI_T::PROTIEN: SSINAIEN Position */
#define USPI_PROTIEN_SSINAIEN_Msk (0x1ul << USPI_PROTIEN_SSINAIEN_Pos) /*!< USPI_T::PROTIEN: SSINAIEN Mask */
#define USPI_PROTIEN_SSACTIEN_Pos (1) /*!< USPI_T::PROTIEN: SSACTIEN Position */
#define USPI_PROTIEN_SSACTIEN_Msk (0x1ul << USPI_PROTIEN_SSACTIEN_Pos) /*!< USPI_T::PROTIEN: SSACTIEN Mask */
#define USPI_PROTIEN_SLVTOIEN_Pos (2) /*!< USPI_T::PROTIEN: SLVTOIEN Position */
#define USPI_PROTIEN_SLVTOIEN_Msk (0x1ul << USPI_PROTIEN_SLVTOIEN_Pos) /*!< USPI_T::PROTIEN: SLVTOIEN Mask */
#define USPI_PROTIEN_SLVBEIEN_Pos (3) /*!< USPI_T::PROTIEN: SLVBEIEN Position */
#define USPI_PROTIEN_SLVBEIEN_Msk (0x1ul << USPI_PROTIEN_SLVBEIEN_Pos) /*!< USPI_T::PROTIEN: SLVBEIEN Mask */
#define USPI_PROTSTS_TXSTIF_Pos (1) /*!< USPI_T::PROTSTS: TXSTIF Position */
#define USPI_PROTSTS_TXSTIF_Msk (0x1ul << USPI_PROTSTS_TXSTIF_Pos) /*!< USPI_T::PROTSTS: TXSTIF Mask */
#define USPI_PROTSTS_TXENDIF_Pos (2) /*!< USPI_T::PROTSTS: TXENDIF Position */
#define USPI_PROTSTS_TXENDIF_Msk (0x1ul << USPI_PROTSTS_TXENDIF_Pos) /*!< USPI_T::PROTSTS: TXENDIF Mask */
#define USPI_PROTSTS_RXSTIF_Pos (3) /*!< USPI_T::PROTSTS: RXSTIF Position */
#define USPI_PROTSTS_RXSTIF_Msk (0x1ul << USPI_PROTSTS_RXSTIF_Pos) /*!< USPI_T::PROTSTS: RXSTIF Mask */
#define USPI_PROTSTS_RXENDIF_Pos (4) /*!< USPI_T::PROTSTS: RXENDIF Position */
#define USPI_PROTSTS_RXENDIF_Msk (0x1ul << USPI_PROTSTS_RXENDIF_Pos) /*!< USPI_T::PROTSTS: RXENDIF Mask */
#define USPI_PROTSTS_SLVTOIF_Pos (5) /*!< USPI_T::PROTSTS: SLVTOIF Position */
#define USPI_PROTSTS_SLVTOIF_Msk (0x1ul << USPI_PROTSTS_SLVTOIF_Pos) /*!< USPI_T::PROTSTS: SLVTOIF Mask */
#define USPI_PROTSTS_SLVBEIF_Pos (6) /*!< USPI_T::PROTSTS: SLVBEIF Position */
#define USPI_PROTSTS_SLVBEIF_Msk (0x1ul << USPI_PROTSTS_SLVBEIF_Pos) /*!< USPI_T::PROTSTS: SLVBEIF Mask */
#define USPI_PROTSTS_SSINAIF_Pos (8) /*!< USPI_T::PROTSTS: SSINAIF Position */
#define USPI_PROTSTS_SSINAIF_Msk (0x1ul << USPI_PROTSTS_SSINAIF_Pos) /*!< USPI_T::PROTSTS: SSINAIF Mask */
#define USPI_PROTSTS_SSACTIF_Pos (9) /*!< USPI_T::PROTSTS: SSACTIF Position */
#define USPI_PROTSTS_SSACTIF_Msk (0x1ul << USPI_PROTSTS_SSACTIF_Pos) /*!< USPI_T::PROTSTS: SSACTIF Mask */
#define USPI_PROTSTS_SSLINE_Pos (16) /*!< USPI_T::PROTSTS: SSLINE Position */
#define USPI_PROTSTS_SSLINE_Msk (0x1ul << USPI_PROTSTS_SSLINE_Pos) /*!< USPI_T::PROTSTS: SSLINE Mask */
#define USPI_PROTSTS_BUSY_Pos (17) /*!< USPI_T::PROTSTS: BUSY Position */
#define USPI_PROTSTS_BUSY_Msk (0x1ul << USPI_PROTSTS_BUSY_Pos) /*!< USPI_T::PROTSTS: BUSY Mask */
#define USPI_PROTSTS_SLVUDR_Pos (18) /*!< USPI_T::PROTSTS: SLVUDR Position */
#define USPI_PROTSTS_SLVUDR_Msk (0x1ul << USPI_PROTSTS_SLVUDR_Pos) /*!< USPI_T::PROTSTS: SLVUDR Mask */
/**@}*/ /* USPI_CONST */
/**@}*/ /* end of USPI register group */
/*---------------------- I2C Mode of USCI Controller -------------------------*/
/**
@addtogroup UI2C I2C Mode of USCI Controller(UI2C)
Memory Mapped Structure for UI2C Controller
@{ */
typedef struct {
/**
* @var UI2C_T::CTL
* Offset: 0x00 USCI Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[2:0] |FUNMODE |Function Mode
* | | |This bit field selects the protocol for this USCI controller
* | | |Selecting a protocol that is not available or a reserved combination disables the USCI
* | | |When switching between two protocols, the USCI has to be disabled before selecting a new protocol
* | | |Simultaneously, the USCI will be reset when user write 000 to FUNMODE.
* | | |000 = The USCI is disabled. All protocol related state machines are set to idle state.
* | | |001 = The SPI protocol is selected.
* | | |010 = The UART protocol is selected.
* | | |100 = The I2C protocol is selected.
* | | |Note: Other bit combinations are reserved.
* @var UI2C_T::BRGEN
* Offset: 0x08 USCI Baud Rate Generator Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |RCLKSEL |Reference Clock Source Selection
* | | |This bit selects the source signal of reference clock (fREF_CLK).
* | | |0 = Peripheral device clock fPCLK.
* | | |1 = Reserved.
* |[1] |PTCLKSEL |Protocol Clock Source Selection
* | | |This bit selects the source signal of protocol clock (fPROT_CLK).
* | | |0 = Reference clock fREF_CLK.
* | | |1 = fREF_CLK2 (its frequency is half of fREF_CLK).
* |[3:2] |SPCLKSEL |Sample Clock Source Selection
* | | |This bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor.
* | | |00 = fSAMP_CLK = fDIV_CLK.
* | | |01 = fSAMP_CLK = fPROT_CLK.
* | | |10 = fSAMP_CLK = fSCLK.
* | | |11 = fSAMP_CLK = fREF_CLK.
* |[4] |TMCNTEN |Time Measurement Counter Enable Bit
* | | |This bit enables the 10-bit timing measurement counter.
* | | |0 = Time measurement counter is Disabled.
* | | |1 = Time measurement counter is Enabled.
* |[5] |TMCNTSRC |Time Measurement Counter Clock Source Selection
* | | |0 = Time measurement counter with fPROT_CLK.
* | | |1 = Time measurement counter with fDIV_CLK.
* |[9:8] |PDSCNT |Pre-divider for Sample Counter
* | | |This bit field defines the divide ratio of the clock division from sample clock fSAMP_CLK
* | | |The divided frequency fPDS_CNT = fSAMP_CLK / (PDSCNT+1).
* |[14:10] |DSCNT |Denominator for Sample Counter
* | | |This bit field defines the divide ratio of the sample clock fSAMP_CLK.
* | | |The divided frequency fDS_CNT = fPDS_CNT / (DSCNT+1).
* | | |Note: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value
* |[25:16] |CLKDIV |Clock Divider
* | | |This bit field defines the ratio between the protocol clock frequency fPROT_CLK and the clock divider frequency fDIV_CLK (fDIV_CLK = fPROT_CLK / (CLKDIV+1) ).
* | | |Note: In UART function, it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(USCI_PROTCTL[6])) is enabled
* | | |The revised value is the average bit time between bit 5 and bit 6
* | | |The user can use revised CLKDIV and new BRDETITV (USCI_PROTCTL[24:16]) to calculate the precise baud rate.
* @var UI2C_T::LINECTL
* Offset: 0x2C USCI Line Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |LSB |LSB First Transmission Selection
* | | |0 = The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first.
* | | |1 = The LSB, the bit 0 of data buffer, will be transmitted/received first.
* |[11:8] |DWIDTH |Word Length of Transmission
* | | |This bit field defines the data word length (amount of bits) for reception and transmission
* | | |The data word is always right-aligned in the data buffer
* | | |USCI support word length from 4 to 16 bits.
* | | |0x0: The data word contains 16 bits located at bit positions [15:0].
* | | |0x1: Reserved.
* | | |0x2: Reserved.
* | | |0x3: Reserved.
* | | |0x4: The data word contains 4 bits located at bit positions [3:0].
* | | |0x5: The data word contains 5 bits located at bit positions [4:0].
* | | |...
* | | |0xF: The data word contains 15 bits located at bit positions [14:0].
* | | |Note: In UART protocol, the length can be configured as 6~13 bits
* | | |And in I2C protocol, the length fixed as 8 bits.
* @var UI2C_T::TXDAT
* Offset: 0x30 USCI Transmit Data Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |TXDAT |Transmit Data
* | | |Software can use this bit field to write 16-bit transmit data for transmission.
* @var UI2C_T::RXDAT
* Offset: 0x34 USCI Receive Data Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |RXDAT |Received Data
* | | |This bit field monitors the received data which stored in receive data buffer.
* | | |Note 1: In I2C protocol, RXDAT[12:8] indicate the different transmission conditions which defined in I2C.
* | | |Note 2: In UART protocol, RXDAT[15:13] indicate the same frame status of BREAK, FRMERR and PARITYERR (USCI_PROTSTS[7:5]).
* @var UI2C_T::DEVADDR0
* Offset: 0x44 USCI Device Address Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[9:0] |DEVADDR |Device Address
* | | |In I2C protocol, this bit field contains the programmed slave address
* | | |If the first received address byte are 1111 0AAXB, the AA bits are compared to the bits DEVADDR[9:8] to check for address match, where the X is R/W bit
* | | |Then the second address byte is also compared to DEVADDR[7:0].
* | | |Note 1: The DEVADDR [9:7] must be set 3'b000 when I2C operating in 7-bit address mode.
* | | |Note 2: When software set 10'h000, the address can not be used.
* @var UI2C_T::DEVADDR1
* Offset: 0x48 USCI Device Address Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[9:0] |DEVADDR |Device Address
* | | |In I2C protocol, this bit field contains the programmed slave address
* | | |If the first received address byte are 1111 0AAXB, the AA bits are compared to the bits DEVADDR[9:8] to check for address match, where the X is R/W bit
* | | |Then the second address byte is also compared to DEVADDR[7:0].
* | | |Note 1: The DEVADDR [9:7] must be set 3'000 when I2C operating in 7-bit address mode.
* | | |Note 2: When software set 10'h000, the address can not be used.
* @var UI2C_T::ADDRMSK0
* Offset: 0x4C USCI Device Address Mask Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[9:0] |ADDRMSK |USCI Device Address Mask
* | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
* | | |1 = Mask Enabled (the received corresponding address bit is don't care.).
* | | |USCI support multiple address recognition with two address mask register
* | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care
* | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
* | | |Note: The wake-up function can not use address mask.
* @var UI2C_T::ADDRMSK1
* Offset: 0x50 USCI Device Address Mask Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[9:0] |ADDRMSK |USCI Device Address Mask
* | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
* | | |1 = Mask Enabled (the received corresponding address bit is don't care.).
* | | |USCI support multiple address recognition with two address mask register
* | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care
* | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
* | | |Note: The wake-up function can not use address mask.
* @var UI2C_T::WKCTL
* Offset: 0x54 USCI Wake-up Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |WKEN |Wake-up Enable Bit
* | | |0 = Wake-up function Disabled.
* | | |1 = Wake-up function Enabled.
* |[1] |WKADDREN |Wake-up Address Match Enable Bit
* | | |0 = The chip is woken up according data toggle.
* | | |1 = The chip is woken up according address match.
* @var UI2C_T::WKSTS
* Offset: 0x58 USCI Wake-up Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |WKF |Wake-up Flag
* | | |When chip is woken up from Power-down mode, this bit is set to 1
* | | |Software can write 1 to clear this bit.
* @var UI2C_T::PROTCTL
* Offset: 0x5C USCI Protocol Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |GCFUNC |General Call Function
* | | |0 = General Call Function Disabled.
* | | |1 = General Call Function Enabled.
* |[1] |AA |Assert Acknowledge Control
* | | |When AA=1 prior to address or data received, an acknowledged (low level to SDA) will be returned during the acknowledge clock pulse on the SCL line when 1.) A slave is acknowledging the address sent from master, 2.) The receiver devices are acknowledging the data sent by transmitter
* | | |When AA=0 prior to address or data received, a Not acknowledged (high level to SDA) will be returned during the acknowledge clock pulse on the SCL line.
* |[2] |STO |I2C STOP Control
* | | |In Master mode, setting STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically
* | | |In a slave mode, setting STO resets I2C hardware to the defined "not addressed" slave mode when bus error (USCI_PROTSTS.ERRIF = 1).
* |[3] |STA |I2C START Control
* | | |Setting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free.
* |[4] |ADDR10EN |Address 10-bit Function Enable Bit
* | | |0 = Address match 10 bit function is disabled.
* | | |1 = Address match 10 bit function is enabled.
* |[5] |PTRG |I2C Protocol Trigger (Write Only)
* | | |When a new state is present in the USCI_PROTSTS register, if the related interrupt enable bits are set, the I2C interrupt is requested
* | | |It must write one by software to this bit after the related interrupt flags are set to 1 and the I2C protocol function will go ahead until the STOP is active or the PROTEN is disabled.
* | | |0 = I2C's stretch disabled and the I2C protocol function will go ahead.
* | | |1 = I2C's stretch active.
* |[8] |SCLOUTEN |SCL Output Enable Bit
* | | |This bit enables monitor pulling SCL to low
* | | |This monitor will pull SCL to low until it has had time to respond to an I2C interrupt.
* | | |0 = SCL output will be forced high due to open drain mechanism.
* | | |1 = I2C module may act as a slave peripheral just like in normal operation, the I2C holds the clock line low until it has had time to clear I2C interrupt.
* |[9] |MONEN |Monitor Mode Enable Bit
* | | |This bit enables monitor mode
* | | |In monitor mode the SDA output will be put in high impedance mode
* | | |This prevents the I2C module from outputting data of any kind (including ACK) onto the I2C data bus.
* | | |0 = The monitor mode is disabled.
* | | |1 = The monitor mode is enabled.
* | | |Note: Depending on the state of the SCLOUTEN bit, the SCL output may be also forced high, preventing the module from having control over the I2C clock line.
* |[25:16] |TOCNT |Time-out Clock Cycle
* | | |This bit field indicates how many clock cycle selected by TMCNTSRC (USCI_BRGEN [5]) when each interrupt flags are clear
* | | |The time-out is enable when TOCNT bigger than 0.
* | | |Note: The TMCNTSRC (USCI_BRGEN [5]) must be set zero on I2C mode.
* |[31] |PROTEN |I2C Protocol Enable Bit
* | | |0 = I2C Protocol disable.
* | | |1 = I2C Protocol enable.
* @var UI2C_T::PROTIEN
* Offset: 0x60 USCI Protocol Interrupt Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |TOIEN |Time-out Interrupt Enable Control
* | | |In I2C protocol, this bit enables the interrupt generation in case of a time-out event.
* | | |0 = The time-out interrupt is disabled.
* | | |1 = The time-out interrupt is enabled.
* |[1] |STARIEN |Start Condition Received Interrupt Enable Control
* | | |This bit enables the generation of a protocol interrupt if a start condition is detected.
* | | |0 = The start condition interrupt is disabled.
* | | |1 = The start condition interrupt is enabled.
* |[2] |STORIEN |Stop Condition Received Interrupt Enable Control
* | | |This bit enables the generation of a protocol interrupt if a stop condition is detected.
* | | |0 = The stop condition interrupt is disabled.
* | | |1 = The stop condition interrupt is enabled.
* |[3] |NACKIEN |Non - Acknowledge Interrupt Enable Control
* | | |This bit enables the generation of a protocol interrupt if a non - acknowledge is detected by a master.
* | | |0 = The non - acknowledge interrupt is disabled.
* | | |1 = The non - acknowledge interrupt is enabled.
* |[4] |ARBLOIEN |Arbitration Lost Interrupt Enable Control
* | | |This bit enables the generation of a protocol interrupt if an arbitration lost event is detected.
* | | |0 = The arbitration lost interrupt is disabled.
* | | |1 = The arbitration lost interrupt is enabled.
* |[5] |ERRIEN |Error Interrupt Enable Control
* | | |This bit enables the generation of a protocol interrupt if an I2C error condition is detected (indicated by ERR (USCI_PROTSTS [16])).
* | | |0 = The error interrupt is disabled.
* | | |1 = The error interrupt is enabled.
* |[6] |ACKIEN |Acknowledge Interrupt Enable Control
* | | |This bit enables the generation of a protocol interrupt if an acknowledge is detected by a master.
* | | |0 = The acknowledge interrupt is disabled.
* | | |1 = The acknowledge interrupt is enabled.
* @var UI2C_T::PROTSTS
* Offset: 0x64 USCI Protocol Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[5] |TOIF |Time-out Interrupt Flag
* | | |0 = A time-out interrupt status has not occurred.
* | | |1 = A time-out interrupt status has occurred.
* | | |Note: It is cleared by software writing one into this bit
* |[6] |ONBUSY |On Bus Busy
* | | |Indicates that a communication is in progress on the bus
* | | |It is set by hardware when a START condition is detected
* | | |It is cleared by hardware when a STOP condition is detected
* | | |0 = The bus is IDLE (both SCLK and SDA High).
* | | |1 = The bus is busy.
* |[8] |STARIF |Start Condition Received Interrupt Flag
* | | |This bit indicates that a start condition or repeated start condition has been detected on master mode
* | | |However, this bit also indicates that a repeated start condition has been detected on slave mode.
* | | |A protocol interrupt can be generated if USCI_PROTCTL.STARIEN = 1.
* | | |0 = A start condition has not yet been detected.
* | | |1 = A start condition has been detected.
* | | |It is cleared by software writing one into this bit
* |[9] |STORIF |Stop Condition Received Interrupt Flag
* | | |This bit indicates that a stop condition has been detected on the I2C bus lines
* | | |A protocol interrupt can be generated if USCI_PROTCTL.STORIEN = 1.
* | | |0 = A stop condition has not yet been detected.
* | | |1 = A stop condition has been detected.
* | | |It is cleared by software writing one into this bit
* | | |Note: This bit is set when slave RX mode.
* |[10] |NACKIF |Non - Acknowledge Received Interrupt Flag
* | | |This bit indicates that a non - acknowledge has been received in master mode
* | | |A protocol interrupt can be generated if USCI_PROTCTL.NACKIEN = 1.
* | | |0 = A non - acknowledge has not been received.
* | | |1 = A non - acknowledge has been received.
* | | |It is cleared by software writing one into this bit
* |[11] |ARBLOIF |Arbitration Lost Interrupt Flag
* | | |This bit indicates that an arbitration has been lost
* | | |A protocol interrupt can be generated if USCI_PROTCTL.ARBLOIEN = 1.
* | | |0 = An arbitration has not been lost.
* | | |1 = An arbitration has been lost.
* | | |It is cleared by software writing one into this bit
* |[12] |ERRIF |Error Interrupt Flag
* | | |This bit indicates that a Bus Error occurs when a START or STOP condition is present at an illegal position in the formation frame
* | | |Example of illegal position are during the serial transfer of an address byte, a data byte or an acknowledge bit
* | | |A protocol interrupt can be generated if USCI_PROTCTL.ERRIEN = 1.
* | | |0 = An I2C error has not been detected.
* | | |1 = An I2C error has been detected.
* | | |It is cleared by software writing one into this bit
* | | |Note: This bit is set when slave mode, user must write one into STO register to the defined "not addressed" slave mode.
* |[13] |ACKIF |Acknowledge Received Interrupt Flag
* | | |This bit indicates that an acknowledge has been received in master mode
* | | |A protocol interrupt can be generated if USCI_PROTCTL.ACKIEN = 1.
* | | |0 = An acknowledge has not been received.
* | | |1 = An acknowledge has been received.
* | | |It is cleared by software writing one into this bit
* |[14] |SLASEL |Slave Select Status
* | | |This bit indicates that this device has been selected as slave.
* | | |0 = The device is not selected as slave.
* | | |1 = The device is selected as slave.
* | | |Note: This bit has no interrupt signal, and it will be cleared automatically by hardware.
* |[15] |SLAREAD |Slave Read Request Status
* | | |This bit indicates that a slave read request has been detected.
* | | |0 = A slave R/W bit is 1 has not been detected.
* | | |1 = A slave R/W bit is 1 has been detected.
* | | |Note: This bit has no interrupt signal, and it will be cleared automatically by hardware.
* |[16] |WKAKDONE |Wakeup Address Frame Acknowledge Bit Done
* | | |0 = The ACK bit cycle of address match frame isn't done.
* | | |1 = The ACK bit cycle of address match frame is done in power-down.
* | | |Note: This bit can't release when WKUPIF is set.
* |[17] |WRSTSWK |Read/Write Status Bit in Address Wakeup Frame
* | | |0 = Write command be record on the address match wakeup frame.
* | | |1 = Read command be record on the address match wakeup frame.
* |[18] |BUSHANG |Bus Hang-up
* | | |This bit indicates bus hang-up status
* | | |There is 4-bit counter count when SCL hold high and refer fSAMP_CLK
* | | |The hang-up counter will count to overflow and set this bit when SDA is low
* | | |The counter will be reset by falling edge of SCL signal.
* | | |0 = The bus is normal status for transmission.
* | | |1 = The bus is hang-up status for transmission.
* | | |Note: This bit has no interrupt signal, and it will be cleared automatically by hardware when a START condition is present.
* |[19] |ERRARBLO |Error Arbitration Lost
* | | |This bit indicates bus arbitration lost due to bigger noise which is can't be filtered by input processor
* | | |The I2C can send start condition when ERRARBLO is set
* | | |Thus this bit doesn't be cared on slave mode.
* | | |0 = The bus is normal status for transmission.
* | | |1 = The bus is error arbitration lost status for transmission.
* | | |Note: This bit has no interrupt signal, and it will be cleared automatically by hardware when a START condition is present.
* @var UI2C_T::ADMAT
* Offset: 0x88 I2C Slave Match Address Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ADMAT0 |USCI Address 0 Match Status Register
* | | |When address 0 is matched, hardware will inform which address used
* | | |This bit will set to 1, and software can write 1 to clear this bit.
* |[1] |ADMAT1 |USCI Address 1 Match Status Register
* | | |When address 1 is matched, hardware will inform which address used
* | | |This bit will set to 1, and software can write 1 to clear this bit.
* @var UI2C_T::TMCTL
* Offset: 0x8C I2C Timing Configure Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[8:0] |STCTL |Setup Time Configure Control Register
* | | |This field is used to generate a delay timing between SDA edge and SCL rising edge in transmission mode.
* | | |The delay setup time is numbers of peripheral clock = STCTL x fPCLK.
* |[24:16] |HTCTL |Hold Time Configure Control Register
* | | |This field is used to generate the delay timing between SCL falling edge SDA edge in
* | | |transmission mode.
* | | |The delay hold time is numbers of peripheral clock = HTCTL x fPCLK.
*/
__IO uint32_t CTL; /*!< [0x0000] USCI Control Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE0[1];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t BRGEN; /*!< [0x0008] USCI Baud Rate Generator Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE1[8];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t LINECTL; /*!< [0x002c] USCI Line Control Register */
__O uint32_t TXDAT; /*!< [0x0030] USCI Transmit Data Register */
__I uint32_t RXDAT; /*!< [0x0034] USCI Receive Data Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE2[3];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t DEVADDR0; /*!< [0x0044] USCI Device Address Register 0 */
__IO uint32_t DEVADDR1; /*!< [0x0048] USCI Device Address Register 1 */
__IO uint32_t ADDRMSK0; /*!< [0x004c] USCI Device Address Mask Register 0 */
__IO uint32_t ADDRMSK1; /*!< [0x0050] USCI Device Address Mask Register 1 */
__IO uint32_t WKCTL; /*!< [0x0054] USCI Wake-up Control Register */
__IO uint32_t WKSTS; /*!< [0x0058] USCI Wake-up Status Register */
__IO uint32_t PROTCTL; /*!< [0x005c] USCI Protocol Control Register */
__IO uint32_t PROTIEN; /*!< [0x0060] USCI Protocol Interrupt Enable Register */
__IO uint32_t PROTSTS; /*!< [0x0064] USCI Protocol Status Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE3[8];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t ADMAT; /*!< [0x0088] I2C Slave Match Address Register */
__IO uint32_t TMCTL; /*!< [0x008c] I2C Timing Configure Control Register */
} UI2C_T;
/**
@addtogroup UI2C_CONST UI2C Bit Field Definition
Constant Definitions for UI2C Controller
@{ */
#define UI2C_CTL_FUNMODE_Pos (0) /*!< UI2C_T::CTL: FUNMODE Position */
#define UI2C_CTL_FUNMODE_Msk (0x7ul << UI2C_CTL_FUNMODE_Pos) /*!< UI2C_T::CTL: FUNMODE Mask */
#define UI2C_BRGEN_RCLKSEL_Pos (0) /*!< UI2C_T::BRGEN: RCLKSEL Position */
#define UI2C_BRGEN_RCLKSEL_Msk (0x1ul << UI2C_BRGEN_RCLKSEL_Pos) /*!< UI2C_T::BRGEN: RCLKSEL Mask */
#define UI2C_BRGEN_PTCLKSEL_Pos (1) /*!< UI2C_T::BRGEN: PTCLKSEL Position */
#define UI2C_BRGEN_PTCLKSEL_Msk (0x1ul << UI2C_BRGEN_PTCLKSEL_Pos) /*!< UI2C_T::BRGEN: PTCLKSEL Mask */
#define UI2C_BRGEN_SPCLKSEL_Pos (2) /*!< UI2C_T::BRGEN: SPCLKSEL Position */
#define UI2C_BRGEN_SPCLKSEL_Msk (0x3ul << UI2C_BRGEN_SPCLKSEL_Pos) /*!< UI2C_T::BRGEN: SPCLKSEL Mask */
#define UI2C_BRGEN_TMCNTEN_Pos (4) /*!< UI2C_T::BRGEN: TMCNTEN Position */
#define UI2C_BRGEN_TMCNTEN_Msk (0x1ul << UI2C_BRGEN_TMCNTEN_Pos) /*!< UI2C_T::BRGEN: TMCNTEN Mask */
#define UI2C_BRGEN_TMCNTSRC_Pos (5) /*!< UI2C_T::BRGEN: TMCNTSRC Position */
#define UI2C_BRGEN_TMCNTSRC_Msk (0x1ul << UI2C_BRGEN_TMCNTSRC_Pos) /*!< UI2C_T::BRGEN: TMCNTSRC Mask */
#define UI2C_BRGEN_PDSCNT_Pos (8) /*!< UI2C_T::BRGEN: PDSCNT Position */
#define UI2C_BRGEN_PDSCNT_Msk (0x3ul << UI2C_BRGEN_PDSCNT_Pos) /*!< UI2C_T::BRGEN: PDSCNT Mask */
#define UI2C_BRGEN_DSCNT_Pos (10) /*!< UI2C_T::BRGEN: DSCNT Position */
#define UI2C_BRGEN_DSCNT_Msk (0x1ful << UI2C_BRGEN_DSCNT_Pos) /*!< UI2C_T::BRGEN: DSCNT Mask */
#define UI2C_BRGEN_CLKDIV_Pos (16) /*!< UI2C_T::BRGEN: CLKDIV Position */
#define UI2C_BRGEN_CLKDIV_Msk (0x3fful << UI2C_BRGEN_CLKDIV_Pos) /*!< UI2C_T::BRGEN: CLKDIV Mask */
#define UI2C_LINECTL_LSB_Pos (0) /*!< UI2C_T::LINECTL: LSB Position */
#define UI2C_LINECTL_LSB_Msk (0x1ul << UI2C_LINECTL_LSB_Pos) /*!< UI2C_T::LINECTL: LSB Mask */
#define UI2C_LINECTL_DWIDTH_Pos (8) /*!< UI2C_T::LINECTL: DWIDTH Position */
#define UI2C_LINECTL_DWIDTH_Msk (0xful << UI2C_LINECTL_DWIDTH_Pos) /*!< UI2C_T::LINECTL: DWIDTH Mask */
#define UI2C_TXDAT_TXDAT_Pos (0) /*!< UI2C_T::TXDAT: TXDAT Position */
#define UI2C_TXDAT_TXDAT_Msk (0xfffful << UI2C_TXDAT_TXDAT_Pos) /*!< UI2C_T::TXDAT: TXDAT Mask */
#define UI2C_RXDAT_RXDAT_Pos (0) /*!< UI2C_T::RXDAT: RXDAT Position */
#define UI2C_RXDAT_RXDAT_Msk (0xfffful << UI2C_RXDAT_RXDAT_Pos) /*!< UI2C_T::RXDAT: RXDAT Mask */
#define UI2C_DEVADDR0_DEVADDR_Pos (0) /*!< UI2C_T::DEVADDR0: DEVADDR Position */
#define UI2C_DEVADDR0_DEVADDR_Msk (0x3fful << UI2C_DEVADDR0_DEVADDR_Pos) /*!< UI2C_T::DEVADDR0: DEVADDR Mask */
#define UI2C_DEVADDR1_DEVADDR_Pos (0) /*!< UI2C_T::DEVADDR1: DEVADDR Position */
#define UI2C_DEVADDR1_DEVADDR_Msk (0x3fful << UI2C_DEVADDR1_DEVADDR_Pos) /*!< UI2C_T::DEVADDR1: DEVADDR Mask */
#define UI2C_ADDRMSK0_ADDRMSK_Pos (0) /*!< UI2C_T::ADDRMSK0: ADDRMSK Position */
#define UI2C_ADDRMSK0_ADDRMSK_Msk (0x3fful << UI2C_ADDRMSK0_ADDRMSK_Pos) /*!< UI2C_T::ADDRMSK0: ADDRMSK Mask */
#define UI2C_ADDRMSK1_ADDRMSK_Pos (0) /*!< UI2C_T::ADDRMSK1: ADDRMSK Position */
#define UI2C_ADDRMSK1_ADDRMSK_Msk (0x3fful << UI2C_ADDRMSK1_ADDRMSK_Pos) /*!< UI2C_T::ADDRMSK1: ADDRMSK Mask */
#define UI2C_WKCTL_WKEN_Pos (0) /*!< UI2C_T::WKCTL: WKEN Position */
#define UI2C_WKCTL_WKEN_Msk (0x1ul << UI2C_WKCTL_WKEN_Pos) /*!< UI2C_T::WKCTL: WKEN Mask */
#define UI2C_WKCTL_WKADDREN_Pos (1) /*!< UI2C_T::WKCTL: WKADDREN Position */
#define UI2C_WKCTL_WKADDREN_Msk (0x1ul << UI2C_WKCTL_WKADDREN_Pos) /*!< UI2C_T::WKCTL: WKADDREN Mask */
#define UI2C_WKSTS_WKF_Pos (0) /*!< UI2C_T::WKSTS: WKF Position */
#define UI2C_WKSTS_WKF_Msk (0x1ul << UI2C_WKSTS_WKF_Pos) /*!< UI2C_T::WKSTS: WKF Mask */
#define UI2C_PROTCTL_GCFUNC_Pos (0) /*!< UI2C_T::PROTCTL: GCFUNC Position */
#define UI2C_PROTCTL_GCFUNC_Msk (0x1ul << UI2C_PROTCTL_GCFUNC_Pos) /*!< UI2C_T::PROTCTL: GCFUNC Mask */
#define UI2C_PROTCTL_AA_Pos (1) /*!< UI2C_T::PROTCTL: AA Position */
#define UI2C_PROTCTL_AA_Msk (0x1ul << UI2C_PROTCTL_AA_Pos) /*!< UI2C_T::PROTCTL: AA Mask */
#define UI2C_PROTCTL_STO_Pos (2) /*!< UI2C_T::PROTCTL: STO Position */
#define UI2C_PROTCTL_STO_Msk (0x1ul << UI2C_PROTCTL_STO_Pos) /*!< UI2C_T::PROTCTL: STO Mask */
#define UI2C_PROTCTL_STA_Pos (3) /*!< UI2C_T::PROTCTL: STA Position */
#define UI2C_PROTCTL_STA_Msk (0x1ul << UI2C_PROTCTL_STA_Pos) /*!< UI2C_T::PROTCTL: STA Mask */
#define UI2C_PROTCTL_ADDR10EN_Pos (4) /*!< UI2C_T::PROTCTL: ADDR10EN Position */
#define UI2C_PROTCTL_ADDR10EN_Msk (0x1ul << UI2C_PROTCTL_ADDR10EN_Pos) /*!< UI2C_T::PROTCTL: ADDR10EN Mask */
#define UI2C_PROTCTL_PTRG_Pos (5) /*!< UI2C_T::PROTCTL: PTRG Position */
#define UI2C_PROTCTL_PTRG_Msk (0x1ul << UI2C_PROTCTL_PTRG_Pos) /*!< UI2C_T::PROTCTL: PTRG Mask */
#define UI2C_PROTCTL_SCLOUTEN_Pos (8) /*!< UI2C_T::PROTCTL: SCLOUTEN Position */
#define UI2C_PROTCTL_SCLOUTEN_Msk (0x1ul << UI2C_PROTCTL_SCLOUTEN_Pos) /*!< UI2C_T::PROTCTL: SCLOUTEN Mask */
#define UI2C_PROTCTL_MONEN_Pos (9) /*!< UI2C_T::PROTCTL: MONEN Position */
#define UI2C_PROTCTL_MONEN_Msk (0x1ul << UI2C_PROTCTL_MONEN_Pos) /*!< UI2C_T::PROTCTL: MONEN Mask */
#define UI2C_PROTCTL_TOCNT_Pos (16) /*!< UI2C_T::PROTCTL: TOCNT Position */
#define UI2C_PROTCTL_TOCNT_Msk (0x3fful << UI2C_PROTCTL_TOCNT_Pos) /*!< UI2C_T::PROTCTL: TOCNT Mask */
#define UI2C_PROTCTL_PROTEN_Pos (31) /*!< UI2C_T::PROTCTL: PROTEN Position */
#define UI2C_PROTCTL_PROTEN_Msk (0x1ul << UI2C_PROTCTL_PROTEN_Pos) /*!< UI2C_T::PROTCTL: PROTEN Mask */
#define UI2C_PROTIEN_TOIEN_Pos (0) /*!< UI2C_T::PROTIEN: TOIEN Position */
#define UI2C_PROTIEN_TOIEN_Msk (0x1ul << UI2C_PROTIEN_TOIEN_Pos) /*!< UI2C_T::PROTIEN: TOIEN Mask */
#define UI2C_PROTIEN_STARIEN_Pos (1) /*!< UI2C_T::PROTIEN: STARIEN Position */
#define UI2C_PROTIEN_STARIEN_Msk (0x1ul << UI2C_PROTIEN_STARIEN_Pos) /*!< UI2C_T::PROTIEN: STARIEN Mask */
#define UI2C_PROTIEN_STORIEN_Pos (2) /*!< UI2C_T::PROTIEN: STORIEN Position */
#define UI2C_PROTIEN_STORIEN_Msk (0x1ul << UI2C_PROTIEN_STORIEN_Pos) /*!< UI2C_T::PROTIEN: STORIEN Mask */
#define UI2C_PROTIEN_NACKIEN_Pos (3) /*!< UI2C_T::PROTIEN: NACKIEN Position */
#define UI2C_PROTIEN_NACKIEN_Msk (0x1ul << UI2C_PROTIEN_NACKIEN_Pos) /*!< UI2C_T::PROTIEN: NACKIEN Mask */
#define UI2C_PROTIEN_ARBLOIEN_Pos (4) /*!< UI2C_T::PROTIEN: ARBLOIEN Position */
#define UI2C_PROTIEN_ARBLOIEN_Msk (0x1ul << UI2C_PROTIEN_ARBLOIEN_Pos) /*!< UI2C_T::PROTIEN: ARBLOIEN Mask */
#define UI2C_PROTIEN_ERRIEN_Pos (5) /*!< UI2C_T::PROTIEN: ERRIEN Position */
#define UI2C_PROTIEN_ERRIEN_Msk (0x1ul << UI2C_PROTIEN_ERRIEN_Pos) /*!< UI2C_T::PROTIEN: ERRIEN Mask */
#define UI2C_PROTIEN_ACKIEN_Pos (6) /*!< UI2C_T::PROTIEN: ACKIEN Position */
#define UI2C_PROTIEN_ACKIEN_Msk (0x1ul << UI2C_PROTIEN_ACKIEN_Pos) /*!< UI2C_T::PROTIEN: ACKIEN Mask */
#define UI2C_PROTSTS_TOIF_Pos (5) /*!< UI2C_T::PROTSTS: TOIF Position */
#define UI2C_PROTSTS_TOIF_Msk (0x1ul << UI2C_PROTSTS_TOIF_Pos) /*!< UI2C_T::PROTSTS: TOIF Mask */
#define UI2C_PROTSTS_ONBUSY_Pos (6) /*!< UI2C_T::PROTSTS: ONBUSY Position */
#define UI2C_PROTSTS_ONBUSY_Msk (0x1ul << UI2C_PROTSTS_ONBUSY_Pos) /*!< UI2C_T::PROTSTS: ONBUSY Mask */
#define UI2C_PROTSTS_STARIF_Pos (8) /*!< UI2C_T::PROTSTS: STARIF Position */
#define UI2C_PROTSTS_STARIF_Msk (0x1ul << UI2C_PROTSTS_STARIF_Pos) /*!< UI2C_T::PROTSTS: STARIF Mask */
#define UI2C_PROTSTS_STORIF_Pos (9) /*!< UI2C_T::PROTSTS: STORIF Position */
#define UI2C_PROTSTS_STORIF_Msk (0x1ul << UI2C_PROTSTS_STORIF_Pos) /*!< UI2C_T::PROTSTS: STORIF Mask */
#define UI2C_PROTSTS_NACKIF_Pos (10) /*!< UI2C_T::PROTSTS: NACKIF Position */
#define UI2C_PROTSTS_NACKIF_Msk (0x1ul << UI2C_PROTSTS_NACKIF_Pos) /*!< UI2C_T::PROTSTS: NACKIF Mask */
#define UI2C_PROTSTS_ARBLOIF_Pos (11) /*!< UI2C_T::PROTSTS: ARBLOIF Position */
#define UI2C_PROTSTS_ARBLOIF_Msk (0x1ul << UI2C_PROTSTS_ARBLOIF_Pos) /*!< UI2C_T::PROTSTS: ARBLOIF Mask */
#define UI2C_PROTSTS_ERRIF_Pos (12) /*!< UI2C_T::PROTSTS: ERRIF Position */
#define UI2C_PROTSTS_ERRIF_Msk (0x1ul << UI2C_PROTSTS_ERRIF_Pos) /*!< UI2C_T::PROTSTS: ERRIF Mask */
#define UI2C_PROTSTS_ACKIF_Pos (13) /*!< UI2C_T::PROTSTS: ACKIF Position */
#define UI2C_PROTSTS_ACKIF_Msk (0x1ul << UI2C_PROTSTS_ACKIF_Pos) /*!< UI2C_T::PROTSTS: ACKIF Mask */
#define UI2C_PROTSTS_SLASEL_Pos (14) /*!< UI2C_T::PROTSTS: SLASEL Position */
#define UI2C_PROTSTS_SLASEL_Msk (0x1ul << UI2C_PROTSTS_SLASEL_Pos) /*!< UI2C_T::PROTSTS: SLASEL Mask */
#define UI2C_PROTSTS_SLAREAD_Pos (15) /*!< UI2C_T::PROTSTS: SLAREAD Position */
#define UI2C_PROTSTS_SLAREAD_Msk (0x1ul << UI2C_PROTSTS_SLAREAD_Pos) /*!< UI2C_T::PROTSTS: SLAREAD Mask */
#define UI2C_PROTSTS_WKAKDONE_Pos (16) /*!< UI2C_T::PROTSTS: WKAKDONE Position */
#define UI2C_PROTSTS_WKAKDONE_Msk (0x1ul << UI2C_PROTSTS_WKAKDONE_Pos) /*!< UI2C_T::PROTSTS: WKAKDONE Mask */
#define UI2C_PROTSTS_WRSTSWK_Pos (17) /*!< UI2C_T::PROTSTS: WRSTSWK Position */
#define UI2C_PROTSTS_WRSTSWK_Msk (0x1ul << UI2C_PROTSTS_WRSTSWK_Pos) /*!< UI2C_T::PROTSTS: WRSTSWK Mask */
#define UI2C_PROTSTS_BUSHANG_Pos (18) /*!< UI2C_T::PROTSTS: BUSHANG Position */
#define UI2C_PROTSTS_BUSHANG_Msk (0x1ul << UI2C_PROTSTS_BUSHANG_Pos) /*!< UI2C_T::PROTSTS: BUSHANG Mask */
#define UI2C_PROTSTS_ERRARBLO_Pos (19) /*!< UI2C_T::PROTSTS: ERRARBLO Position */
#define UI2C_PROTSTS_ERRARBLO_Msk (0x1ul << UI2C_PROTSTS_ERRARBLO_Pos) /*!< UI2C_T::PROTSTS: ERRARBLO Mask */
#define UI2C_ADMAT_ADMAT0_Pos (0) /*!< UI2C_T::ADMAT: ADMAT0 Position */
#define UI2C_ADMAT_ADMAT0_Msk (0x1ul << UI2C_ADMAT_ADMAT0_Pos) /*!< UI2C_T::ADMAT: ADMAT0 Mask */
#define UI2C_ADMAT_ADMAT1_Pos (1) /*!< UI2C_T::ADMAT: ADMAT1 Position */
#define UI2C_ADMAT_ADMAT1_Msk (0x1ul << UI2C_ADMAT_ADMAT1_Pos) /*!< UI2C_T::ADMAT: ADMAT1 Mask */
#define UI2C_TMCTL_STCTL_Pos (0) /*!< UI2C_T::TMCTL: STCTL Position */
#define UI2C_TMCTL_STCTL_Msk (0x1fful << UI2C_TMCTL_STCTL_Pos) /*!< UI2C_T::TMCTL: STCTL Mask */
#define UI2C_TMCTL_HTCTL_Pos (16) /*!< UI2C_T::TMCTL: HTCTL Position */
#define UI2C_TMCTL_HTCTL_Msk (0x1fful << UI2C_TMCTL_HTCTL_Pos) /*!< UI2C_T::TMCTL: HTCTL Mask */
/**@}*/ /* UI2C_CONST */
/**@}*/ /* end of UI2C register group */
/*---------------------- Controller Area Network Controller -------------------------*/
/**
@addtogroup CAN Controller Area Network Controller(CAN)
Memory Mapped Structure for CAN Controller
@{ */
typedef struct {
/**
* @var CAN_IF_T::CREQ
* Offset: 0x20, 0x80 IFn Command Request Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[5:0] |MessageNumber|Message Number
* | | |0x01-0x20: Valid Message Number, the Message Object in the Message
* | | |RAM is selected for data transfer.
* | | |0x00: Not a valid Message Number, interpreted as 0x20.
* | | |0x21-0x3F: Not a valid Message Number, interpreted as 0x01-0x1F.
* |[15] |Busy |Busy Flag
* | | |0 = Read/write action has finished.
* | | |1 = Writing to the IFn Command Request Register is in progress
* | | |This bit can only be read by the software.
* @var CAN_IF_T::CMASK
* Offset: 0x24, 0x84 IFn Command Mask Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |DAT_B |Access Data Bytes [7:4]
* | | |Write Operation:
* | | |0 = Data Bytes [7:4] unchanged.
* | | |1 = Transfer Data Bytes [7:4] to Message Object.
* | | |Read Operation:
* | | |0 = Data Bytes [7:4] unchanged.
* | | |1 = Transfer Data Bytes [7:4] to IFn Message Buffer Register.
* |[1] |DAT_A |Access Data Bytes [3:0]
* | | |Write Operation:
* | | |0 = Data Bytes [3:0] unchanged.
* | | |1 = Transfer Data Bytes [3:0] to Message Object.
* | | |Read Operation:
* | | |0 = Data Bytes [3:0] unchanged.
* | | |1 = Transfer Data Bytes [3:0] to IFn Message Buffer Register.
* |[2] |TxRqst_NewDat|Access Transmission Request Bit When Write Operation
* | | |0 = TxRqst bit unchanged.
* | | |1 = Set TxRqst bit.
* | | |Note: If a transmission is requested by programming bit TxRqst/NewDat in the IFn Command Mask Register, bit TxRqst in the IFn Message Control Register will be ignored.
* | | |Access New Data Bit when Read Operation.
* | | |0 = NewDat bit remains unchanged.
* | | |1 = Clear NewDat bit in the Message Object.
* | | |Note: A read access to a Message Object can be combined with the reset of the control bits IntPnd and NewDat
* | | |The values of these bits transferred to the IFn Message Control Register always reflect the status before resetting these bits.
* |[3] |ClrIntPnd |Clear Interrupt Pending Bit
* | | |Write Operation:
* | | |When writing to a Message Object, this bit is ignored.
* | | |Read Operation:
* | | |0 = IntPnd bit (CAN_IFn_MCON[13]) remains unchanged.
* | | |1 = Clear IntPnd bit in the Message Object.
* |[4] |Control |Control Access Control Bits
* | | |Write Operation:
* | | |0 = Control Bits unchanged.
* | | |1 = Transfer Control Bits to Message Object.
* | | |Read Operation:
* | | |0 = Control Bits unchanged.
* | | |1 = Transfer Control Bits to IFn Message Buffer Register.
* |[5] |Arb |Access Arbitration Bits
* | | |Write Operation:
* | | |0 = Arbitration bits unchanged.
* | | |1 = Transfer Identifier + Dir (CAN_IFn_ARB2[13]) + Xtd (CAN_IFn_ARB2[14]) + MsgVal (CAN_IFn_ARB2[15]) to Message Object.
* | | |Read Operation:
* | | |0 = Arbitration bits unchanged.
* | | |1 = Transfer Identifier + Dir + Xtd + MsgVal to IFn Message Buffer Register.
* |[6] |Mask |Access Mask Bits
* | | |Write Operation:
* | | |0 = Mask bits unchanged.
* | | |1 = Transfer Identifier Mask + MDir + MXtd to Message Object.
* | | |Read Operation:
* | | |0 = Mask bits unchanged.
* | | |1 = Transfer Identifier Mask + MDir + MXtd to IFn Message Buffer Register.
* |[7] |WR_RD |Write / Read Mode
* | | |0 = Read: Transfer data from the Message Object addressed by the Command Request Register into the selected Message Buffer Registers.
* | | |1 = Write: Transfer data from the selected Message Buffer Registers to the Message Object addressed by the Command Request Register.
* @var CAN_IF_T::MASK1
* Offset: 0x28, 0x88 IFn Mask 1 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |Msk |Identifier Mask 15-0
* | | |0 = The corresponding bit in the identifier of the message object cannot inhibit the match in the acceptance filtering.
* | | |1 = The corresponding identifier bit is used for acceptance filtering.
* @var CAN_IF_T::MASK2
* Offset: 0x2C, 0x8C IFn Mask 2 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[12:0] |Msk |Identifier Mask 28-16
* | | |0 = The corresponding bit in the identifier of the message object cannot inhibit the match in the acceptance filtering.
* | | |1 = The corresponding identifier bit is used for acceptance filtering.
* |[14] |MDir |Mask Message Direction
* | | |0 = The message direction bit (Dir (CAN_IFn_ARB2[13])) has no effect on the acceptance filtering.
* | | |1 = The message direction bit (Dir) is used for acceptance filtering.
* |[15] |MXtd |Mask Extended Identifier
* | | |0 = The extended identifier bit (IDE) has no effect on the acceptance filtering.
* | | |1 = The extended identifier bit (IDE) is used for acceptance filtering.
* | | |Note: When 11-bit (standard) Identifiers are used for a Message Object, the identifiers of received Data Frames are written into bits ID28 to ID18 (CAN_IFn_ARB2[12:2])
* | | |For acceptance filtering, only these bits together with mask bits Msk28 to Msk18 (CAN_IFn_MASK2[12:2]) are considered.
* @var CAN_IF_T::ARB1
* Offset: 0x30, 0x90 IFn Arbitration 1 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |ID |Message Identifier 15-0
* | | |ID28 - ID0, 29-bit Identifier (Extended Frame)
* | | |ID28 - ID18, 11-bit Identifier (Standard Frame)
* @var CAN_IF_T::ARB2
* Offset: 0x34, 0x94 IFn Arbitration 2 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[12:0] |ID |Message Identifier 28-16
* | | |ID28 - ID0, 29-bit Identifier (Extended Frame)
* | | |ID28 - ID18, 11-bit Identifier (Standard Frame)
* |[13] |Dir |Message Direction
* | | |0 = Direction is receive.
* | | |On TxRqst, a Remote Frame with the identifier of this Message Object is transmitted
* | | |On reception of a Data Frame with matching identifier, that message is stored in this Message Object.
* | | |1 = Direction is transmit.
* | | |On TxRqst, the respective Message Object is transmitted as a Data Frame
* | | |On reception of a Remote Frame with matching identifier, the TxRqst bit (CAN_IFn_CMASK[2]) of this Message Object is set (if RmtEn (CAN_IFn_MCON[9]) = one).
* |[14] |Xtd |Extended Identifier
* | | |0 = The 11-bit (standard) Identifier will be used for this Message Object.
* | | |1 = The 29-bit (extended) Identifier will be used for this Message Object.
* |[15] |MsgVal |Message Valid
* | | |0 = The Message Object is ignored by the Message Handler.
* | | |1 = The Message Object is configured and should be considered by the Message Handler.
* | | |Note: The application software must reset the MsgVal bit of all unused Messages Objects during the initialization before it resets bit Init (CAN_CON[0])
* | | |This bit must also be reset before the identifier Id28-0 (CAN_IFn_ARB1/2), the control bits Xtd (CAN_IFn_ARB2[14]), Dir (CAN_IFn_ARB2[13]), or the Data Length Code DLC3-0 (CAN_IFn_MCON[3:0]) are modified, or if the Messages Object is no longer required.
* @var CAN_IF_T::MCON
* Offset: 0x38, 0x98 IFn Message Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |DLC |Data Length Code
* | | |0-8: Data Frame has 0-8 data bytes.
* | | |9-15: Data Frame has 8 data bytes
* | | |Note: The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes
* | | |When the Message Handler stores a data frame, it will write the DLC to the value given by the received message.
* | | |Data(0): 1st data byte of a CAN Data Frame
* | | |Data(1): 2nd data byte of a CAN Data Frame
* | | |Data(2): 3rd data byte of a CAN Data Frame
* | | |Data(3): 4th data byte of a CAN Data Frame
* | | |Data(4): 5th data byte of a CAN Data Frame
* | | |Data(5): 6th data byte of a CAN Data Frame
* | | |Data(6): 7th data byte of a CAN Data Frame
* | | |Data(7): 8th data byte of a CAN Data Frame
* | | |Note: The Data(0) byte is the first data byte shifted into the shift register of the CAN Core during a reception while the Data(7) byte is the last
* | | |When the Message Handler stores a Data Frame, it will write all the eight data bytes into a Message Object
* | | |If the Data Length Code is less than 8, the remaining bytes of the Message Object will be overwritten by unspecified values.
* |[7] |EoB |End of Buffer
* | | |0 = Message Object belongs to a FIFO Buffer and is not the last Message Object of that FIFO Buffer.
* | | |1 = Single Message Object or last Message Object of a FIFO Buffer.
* | | |Note: This bit is used to concatenate two or more Message Objects (up to 32) to build a FIFO Buffer
* | | |For single Message Objects (not belonging to a FIFO Buffer), this bit must always be set to one
* |[8] |TxRqst |Transmit Request
* | | |0 = This Message Object is not waiting for transmission.
* | | |1 = The transmission of this Message Object is requested and is not yet done.
* |[9] |RmtEn |Remote Enable Bit
* | | |0 = At the reception of a Remote Frame, TxRqst (CAN_IFn_MCON[8]) is left unchanged.
* | | |1 = At the reception of a Remote Frame, TxRqst is set.
* |[10] |RxIE |Receive Interrupt Enable Bit
* | | |0 = IntPnd (CAN_IFn_MCON[13]) will be left unchanged after a successful reception of a frame.
* | | |1 = IntPnd will be set after a successful reception of a frame.
* |[11] |TxIE |Transmit Interrupt Enable Bit
* | | |0 = IntPnd (CAN_IFn_MCON[13]) will be left unchanged after the successful transmission of a frame.
* | | |1 = IntPnd will be set after a successful transmission of a frame.
* |[12] |UMask |Use Acceptance Mask
* | | |0 = Mask ignored.
* | | |1 = Use Mask (Msk28-0, MXtd, and MDir) for acceptance filtering.
* | | |Note: If the UMask bit is set to one, the Message Object's mask bits have to be programmed during initialization of the Message Object before MsgVal bit (CAN_IFn_ARB2[15]) is set to one.
* |[13] |IntPnd |Interrupt Pending
* | | |0 = This message object is not the source of an interrupt.
* | | |1 = This message object is the source of an interrupt
* | | |The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority.
* |[14] |MsgLst |Message Lost (only valid for Message Objects with direction = receive).
* | | |0 = No message lost since last time this bit was reset by the CPU.
* | | |1 = The Message Handler stored a new message into this object when NewDat was still set, the CPU has lost a message.
* |[15] |NewDat |New Data
* | | |0 = No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the application software.
* | | |1 = The Message Handler or the application software has written new data into the data portion of this Message Object.
* @var CAN_IF_T::DAT_A1
* Offset: 0x3C, 0x9C IFn Data A1 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |Data_0_ |Data Byte 0
* | | |1st data byte of a CAN Data Frame
* |[15:8] |Data_1_ |Data Byte 1
* | | |2nd data byte of a CAN Data Frame
* @var CAN_IF_T::DAT_A2
* Offset: 0x40, 0xA0 IFn Data A2 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |Data_2_ |Data Byte 2
* | | |3rd data byte of CAN Data Frame
* |[15:8] |Data_3_ |Data Byte 3
* | | |4th data byte of CAN Data Frame
* @var CAN_IF_T::DAT_B1
* Offset: 0x44, 0xA4 IFn Data B1 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |Data_4_ |Data Byte 4
* | | |5th data byte of CAN Data Frame
* |[15:8] |Data_5_ |Data Byte 5
* | | |6th data byte of CAN Data Frame
* @var CAN_IF_T::DAT_B2
* Offset: 0x48, 0xA8 IFn Data B2 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |Data_6_ |Data Byte 6
* | | |7th data byte of CAN Data Frame.
* |[15:8] |Data_7_ |Data Byte 7
* | | |8th data byte of CAN Data Frame.
*/
__IO uint32_t CREQ; /*!< [0x0020] IFn Command Request Register */
__IO uint32_t CMASK; /*!< [0x0024] IFn Command Mask Register */
__IO uint32_t MASK1; /*!< [0x0028] IFn Mask 1 Register */
__IO uint32_t MASK2; /*!< [0x002c] IFn Mask 2 Register */
__IO uint32_t ARB1; /*!< [0x0030] IFn Arbitration 1 Register */
__IO uint32_t ARB2; /*!< [0x0034] IFn Arbitration 2 Register */
__IO uint32_t MCON; /*!< [0x0038] IFn Message Control Register */
__IO uint32_t DAT_A1; /*!< [0x003c] IFn Data A1 Register */
__IO uint32_t DAT_A2; /*!< [0x0040] IFn Data A2 Register */
__IO uint32_t DAT_B1; /*!< [0x0044] IFn Data B1 Register */
__IO uint32_t DAT_B2; /*!< [0x0048] IFn Data B2 Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE0[13];
/// @endcond //HIDDEN_SYMBOLS
} CAN_IF_T;
typedef struct {
/**
* @var CAN_T::CON
* Offset: 0x00 Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |Init |Init Initialization
* | | |0 = Normal Operation.
* | | |1 = Initialization is started.
* |[1] |IE |Module Interrupt Enable Bit
* | | |0 = Function interrupt is Disabled.
* | | |1 = Function interrupt is Enabled.
* |[2] |SIE |Status Change Interrupt Enable Bit
* | | |0 = Disabled - No Status Change Interrupt will be generated.
* | | |1 = Enabled - An interrupt will be generated when a message transfer is successfully completed or a CAN bus error is detected.
* |[3] |EIE |Error Interrupt Enable Bit
* | | |0 = Disabled - No Error Status Interrupt will be generated.
* | | |1 = Enabled - A change in the bits BOff (CAN_STATUS[7]) or EWarn (CAN_STATUS[6]) in the Status Register will generate an interrupt.
* |[5] |DAR |Automatic Re-transmission Disable Bit
* | | |0 = Automatic Retransmission of disturbed messages Enabled.
* | | |1 = Automatic Retransmission Disabled.
* |[6] |CCE |Configuration Change Enable Bit
* | | |0 = No write access to the Bit Timing Register.
* | | |1 = Write access to the Bit Timing Register (CAN_BTIME) allowed. (while Init bit (CAN_CON[0]) = 1).
* |[7] |Test |Test Mode Enable Bit
* | | |0 = Normal Operation.
* | | |1 = Test Mode.
* @var CAN_T::STATUS
* Offset: 0x04 Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[2:0] |LEC |Last Error Code (Type of the Last Error to Occur on the CAN Bus)
* | | |The LEC field holds a code, which indicates the type of the last error to occur on the CAN bus
* | | |This field will be cleared to '0' when a message has been transferred (reception or transmission) without error
* | | |The unused code '7' may be written by the CPU to check for updates
* | | |The Error! Reference source not found
* | | |describes the error code.
* |[3] |TxOK |Transmitted a Message Successfully
* | | |0 = Since this bit was reset by the CPU, no message has been successfully transmitted
* | | |This bit is never reset by the CAN Core.
* | | |1 = Since this bit was last reset by the CPU, a message has been successfully (error free and acknowledged by at least one other node) transmitted.
* |[4] |RxOK |Received a Message Successfully
* | | |0 = No message has been successfully received since this bit was last reset by the CPU
* | | |This bit is never reset by the CAN Core.
* | | |1 = A message has been successfully received since this bit was last reset by the CPU (independent of the result of acceptance filtering).
* |[5] |EPass |Error Passive (Read Only)
* | | |0 = The CAN Core is error active.
* | | |1 = The CAN Core is in the error passive state as defined in the CAN Specification.
* |[6] |EWarn |Error Warning Status (Read Only)
* | | |0 = Both error counters are below the error warning limit of 96.
* | | |1 = At least one of the error counters in the EML has reached the error warning limit of 96.
* |[7] |BOff |Bus-off Status (Read Only)
* | | |0 = The CAN module is not in bus-off state.
* | | |1 = The CAN module is in bus-off state.
* @var CAN_T::ERR
* Offset: 0x08 Error Counter Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |TEC |Transmit Error Counter
* | | |Actual state of the Transmit Error Counter. Values between 0 and 255.
* |[14:8] |REC |Receive Error Counter
* | | |Actual state of the Receive Error Counter. Values between 0 and 127.
* |[15] |RP |Receive Error Passive
* | | |0 = The Receive Error Counter is below the error passive level.
* | | |1 = The Receive Error Counter has reached the error passive level as defined in the CAN Specification.
* @var CAN_T::BTIME
* Offset: 0x0C Bit Timing Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[5:0] |BRP |Baud Rate Prescaler
* | | |0x01-0x3F: The value by which the oscillator frequency is divided for generating the bit time quanta
* | | |The bit time is built up from a multiple of this quanta
* | | |Valid values for the Baud Rate Prescaler are [0...63]
* | | |The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.
* |[7:6] |SJW |(Re)Synchronization Jump Width
* | | |0x0-0x3: Valid programmed values are [0...3]
* | | |The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.
* |[11:8] |TSeg1 |Time Segment Before the Sample Point Minus Sync_Seg
* | | |0x01-0x0F: valid values for TSeg1 are [1...15]
* | | |The actual interpretation by the hardware of this value is such that one more than the value programmed is used.
* |[14:12] |TSeg2 |Time Segment After Sample Point
* | | |0x0-0x7: Valid values for TSeg2 are [0...7]
* | | |The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.
* @var CAN_T::IIDR
* Offset: 0x10 Interrupt Identifier Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |IntId |Interrupt Identifier (Indicates the Source of the Interrupt)
* | | |If several interrupts are pending, the CAN Interrupt Register will point to the pending interrupt with the highest priority, disregarding their chronological order
* | | |An interrupt remains pending until the application software has cleared it
* | | |If IntId is different from 0x0000 and IE (CAN_CON[1]) is set, the IRQ interrupt signal to the EIC is active
* | | |The interrupt remains active until IntId is back to value 0x0000 (the cause of the interrupt is reset) or until IE is reset.
* | | |The Status Interrupt has the highest priority
* | | |Among the message interrupts, the Message Object' s interrupt priority decreases with increasing message number.
* | | |A message interrupt is cleared by clearing the Message Object's IntPnd bit (CAN_IFn_MCON[13])
* | | |The Status Interrupt is cleared by reading the Status Register.
* @var CAN_T::TEST
* Offset: 0x14 Test Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[2] |Basic |Basic Mode
* | | |0 = Basic Mode Disabled.
* | | |1= IF1 Registers used as Tx Buffer, IF2 Registers used as Rx Buffer.
* |[3] |Silent |Silent Mode
* | | |0 = Normal operation.
* | | |1 = The module is in Silent Mode.
* |[4] |LBack |Loop Back Mode Enable Bit
* | | |0 = Loop Back Mode is Disabled.
* | | |1 = Loop Back Mode is Enabled.
* |[6:5] |Tx |Tx[1:0]: Control of CAN_TX Pin
* | | |00 = Reset value, CAN_TX pin is controlled by the CAN Core.
* | | |01 = Sample Point can be monitored at CAN_TX pin.
* | | |10 = CAN_TX pin drives a dominant ('0') value.
* | | |11 = CAN_TX pin drives a recessive ('1') value.
* |[7] |Rx |Monitors the Actual Value of CAN_RX Pin (Read Only) *(1)
* | | |0 = The CAN bus is dominant (CAN_RX = '0').
* | | |1 = The CAN bus is recessive (CAN_RX = '1').
* @var CAN_T::BRPE
* Offset: 0x18 Baud Rate Prescaler Extension Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |BRPE |BRPE: Baud Rate Prescaler Extension
* | | |0x00-0x0F: By programming BRPE, the Baud Rate Prescaler can be extended to values up to 1023
* | | |The actual interpretation by the hardware is that one more than the value programmed by BRPE (MSBs) and BTIME (LSBs) is used.
* @var CAN_T::TXREQ1
* Offset: 0x100 Transmission Request Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |TxRqst16_1|Transmission Request Bits 16-1 (of All Message Objects)
* | | |0 = This Message Object is not waiting for transmission.
* | | |1 = The transmission of this Message Object is requested and is not yet done.
* | | |These bits are read only.
* @var CAN_T::TXREQ2
* Offset: 0x104 Transmission Request Register 2
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |TxRqst32_17|Transmission Request Bits 32-17 (of All Message Objects)
* | | |0 = This Message Object is not waiting for transmission.
* | | |1 = The transmission of this Message Object is requested and is not yet done.
* | | |These bits are read only.
* @var CAN_T::NDAT1
* Offset: 0x120 New Data Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |NewData16_1|New Data Bits 16-1 (of All Message Objects)
* | | |0 = No new data has been written into the data portion of this Message Object by the Message Handler since the last time this flag was cleared by the application software.
* | | |1 = The Message Handler or the application software has written new data into the data portion of this Message Object.
* @var CAN_T::NDAT2
* Offset: 0x124 New Data Register 2
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |NewData32_17|New Data Bits 32-17 (of All Message Objects)
* | | |0 = No new data has been written into the data portion of this Message Object by the Message Handler since the last time this flag was cleared by the application software.
* | | |1 = The Message Handler or the application software has written new data into the data portion of this Message Object.
* @var CAN_T::IPND1
* Offset: 0x140 Interrupt Pending Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |IntPnd16_1|Interrupt Pending Bits 16-1 (of All Message Objects)
* | | |0 = This message object is not the source of an interrupt.
* | | |1 = This message object is the source of an interrupt.
* @var CAN_T::IPND2
* Offset: 0x144 Interrupt Pending Register 2
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |IntPnd32_17|Interrupt Pending Bits 32-17 (of All Message Objects)
* | | |0 = This message object is not the source of an interrupt.
* | | |1 = This message object is the source of an interrupt.
* @var CAN_T::MVLD1
* Offset: 0x160 Message Valid Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |MsgVal16_1|Message Valid Bits 16-1 (of All Message Objects) (Read Only)
* | | |0 = This Message Object is ignored by the Message Handler.
* | | |1 = This Message Object is configured and should be considered by the Message Handler.
* | | |Ex
* | | |CAN_MVLD1[0] means Message object No.1 is valid or not
* | | |If CAN_MVLD1[0] is set, message object No.1 is configured.
* @var CAN_T::MVLD2
* Offset: 0x164 Message Valid Register 2
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |MsgVal32_17|Message Valid Bits 32-17 (of All Message Objects) (Read Only)
* | | |0 = This Message Object is ignored by the Message Handler.
* | | |1 = This Message Object is configured and should be considered by the Message Handler.
* | | |Ex.CAN_MVLD2[15] means Message object No.32 is valid or not
* | | |If CAN_MVLD2[15] is set, message object No.32 is configured.
* @var CAN_T::WU_EN
* Offset: 0x168 Wake-up Enable Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |WAKUP_EN |Wake-up Enable Bit
* | | |0 = The wake-up function Disabled.
* | | |1 = The wake-up function Enabled.
* | | |Note: User can wake-up system when there is a falling edge in the CAN_Rx pin.
* @var CAN_T::WU_STATUS
* Offset: 0x16C Wake-up Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |WAKUP_STS |Wake-up Status
* | | |0 = No wake-up event occurred.
* | | |1 = Wake-up event occurred.
* | | |Note: This bit can be cleared by writing '0'.
*/
__IO uint32_t CON; /*!< [0x0000] Control Register */
__IO uint32_t STATUS; /*!< [0x0004] Status Register */
__I uint32_t ERR; /*!< [0x0008] Error Counter Register */
__IO uint32_t BTIME; /*!< [0x000c] Bit Timing Register */
__I uint32_t IIDR; /*!< [0x0010] Interrupt Identifier Register */
__IO uint32_t TEST; /*!< [0x0014] Test Register */
__IO uint32_t BRPE; /*!< [0x0018] Baud Rate Prescaler Extension Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE0[1];
/// @endcond //HIDDEN_SYMBOLS
__IO CAN_IF_T IF[2];
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE2[8];
/// @endcond //HIDDEN_SYMBOLS
__I uint32_t TXREQ1; /*!< [0x0100] Transmission Request Register 1 */
__I uint32_t TXREQ2; /*!< [0x0104] Transmission Request Register 2 */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE3[6];
/// @endcond //HIDDEN_SYMBOLS
__I uint32_t NDAT1; /*!< [0x0120] New Data Register 1 */
__I uint32_t NDAT2; /*!< [0x0124] New Data Register 2 */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE4[6];
/// @endcond //HIDDEN_SYMBOLS
__I uint32_t IPND1; /*!< [0x0140] Interrupt Pending Register 1 */
__I uint32_t IPND2; /*!< [0x0144] Interrupt Pending Register 2 */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE5[6];
/// @endcond //HIDDEN_SYMBOLS
__I uint32_t MVLD1; /*!< [0x0160] Message Valid Register 1 */
__I uint32_t MVLD2; /*!< [0x0164] Message Valid Register 2 */
__IO uint32_t WU_EN; /*!< [0x0168] Wake-up Enable Control Register */
__IO uint32_t WU_STATUS; /*!< [0x016c] Wake-up Status Register */
} CAN_T;
/**
@addtogroup CAN_CONST CAN Bit Field Definition
Constant Definitions for CAN Controller
@{ */
#define CAN_CON_INIT_Pos (0) /*!< CAN_T::CON: Init Position */
#define CAN_CON_INIT_Msk (0x1ul << CAN_CON_INIT_Pos) /*!< CAN_T::CON: Init Mask */
#define CAN_CON_IE_Pos (1) /*!< CAN_T::CON: IE Position */
#define CAN_CON_IE_Msk (0x1ul << CAN_CON_IE_Pos) /*!< CAN_T::CON: IE Mask */
#define CAN_CON_SIE_Pos (2) /*!< CAN_T::CON: SIE Position */
#define CAN_CON_SIE_Msk (0x1ul << CAN_CON_SIE_Pos) /*!< CAN_T::CON: SIE Mask */
#define CAN_CON_EIE_Pos (3) /*!< CAN_T::CON: EIE Position */
#define CAN_CON_EIE_Msk (0x1ul << CAN_CON_EIE_Pos) /*!< CAN_T::CON: EIE Mask */
#define CAN_CON_DAR_Pos (5) /*!< CAN_T::CON: DAR Position */
#define CAN_CON_DAR_Msk (0x1ul << CAN_CON_DAR_Pos) /*!< CAN_T::CON: DAR Mask */
#define CAN_CON_CCE_Pos (6) /*!< CAN_T::CON: CCE Position */
#define CAN_CON_CCE_Msk (0x1ul << CAN_CON_CCE_Pos) /*!< CAN_T::CON: CCE Mask */
#define CAN_CON_TEST_Pos (7) /*!< CAN_T::CON: Test Position */
#define CAN_CON_TEST_Msk (0x1ul << CAN_CON_TEST_Pos) /*!< CAN_T::CON: Test Mask */
#define CAN_STATUS_LEC_Pos (0) /*!< CAN_T::STATUS: LEC Position */
#define CAN_STATUS_LEC_Msk (0x7ul << CAN_STATUS_LEC_Pos) /*!< CAN_T::STATUS: LEC Mask */
#define CAN_STATUS_TXOK_Pos (3) /*!< CAN_T::STATUS: TxOK Position */
#define CAN_STATUS_TXOK_Msk (0x1ul << CAN_STATUS_TXOK_Pos) /*!< CAN_T::STATUS: TxOK Mask */
#define CAN_STATUS_RXOK_Pos (4) /*!< CAN_T::STATUS: RxOK Position */
#define CAN_STATUS_RXOK_Msk (0x1ul << CAN_STATUS_RXOK_Pos) /*!< CAN_T::STATUS: RxOK Mask */
#define CAN_STATUS_EPASS_Pos (5) /*!< CAN_T::STATUS: EPass Position */
#define CAN_STATUS_EPASS_Msk (0x1ul << CAN_STATUS_EPASS_Pos) /*!< CAN_T::STATUS: EPass Mask */
#define CAN_STATUS_EWARN_Pos (6) /*!< CAN_T::STATUS: EWarn Position */
#define CAN_STATUS_EWARN_Msk (0x1ul << CAN_STATUS_EWARN_Pos) /*!< CAN_T::STATUS: EWarn Mask */
#define CAN_STATUS_BOFF_Pos (7) /*!< CAN_T::STATUS: BOff Position */
#define CAN_STATUS_BOFF_Msk (0x1ul << CAN_STATUS_BOFF_Pos) /*!< CAN_T::STATUS: BOff Mask */
#define CAN_ERR_TEC_Pos (0) /*!< CAN_T::ERR: TEC Position */
#define CAN_ERR_TEC_Msk (0xfful << CAN_ERR_TEC_Pos) /*!< CAN_T::ERR: TEC Mask */
#define CAN_ERR_REC_Pos (8) /*!< CAN_T::ERR: REC Position */
#define CAN_ERR_REC_Msk (0x7ful << CAN_ERR_REC_Pos) /*!< CAN_T::ERR: REC Mask */
#define CAN_ERR_RP_Pos (15) /*!< CAN_T::ERR: RP Position */
#define CAN_ERR_RP_Msk (0x1ul << CAN_ERR_RP_Pos) /*!< CAN_T::ERR: RP Mask */
#define CAN_BTIME_BRP_Pos (0) /*!< CAN_T::BTIME: BRP Position */
#define CAN_BTIME_BRP_Msk (0x3ful << CAN_BTIME_BRP_Pos) /*!< CAN_T::BTIME: BRP Mask */
#define CAN_BTIME_SJW_Pos (6) /*!< CAN_T::BTIME: SJW Position */
#define CAN_BTIME_SJW_Msk (0x3ul << CAN_BTIME_SJW_Pos) /*!< CAN_T::BTIME: SJW Mask */
#define CAN_BTIME_TSEG1_Pos (8) /*!< CAN_T::BTIME: TSeg1 Position */
#define CAN_BTIME_TSEG1_Msk (0xful << CAN_BTIME_TSEG1_Pos) /*!< CAN_T::BTIME: TSeg1 Mask */
#define CAN_BTIME_TSEG2_Pos (12) /*!< CAN_T::BTIME: TSeg2 Position */
#define CAN_BTIME_TSEG2_Msk (0x7ul << CAN_BTIME_TSEG2_Pos) /*!< CAN_T::BTIME: TSeg2 Mask */
#define CAN_IIDR_IntId_Pos (0) /*!< CAN_T::IIDR: IntId Position */
#define CAN_IIDR_IntId_Msk (0xfffful << CAN_IIDR_IntId_Pos) /*!< CAN_T::IIDR: IntId Mask */
#define CAN_TEST_BASIC_Pos (2) /*!< CAN_T::TEST: Basic Position */
#define CAN_TEST_BASIC_Msk (0x1ul << CAN_TEST_BASIC_Pos) /*!< CAN_T::TEST: Basic Mask */
#define CAN_TEST_SILENT_Pos (3) /*!< CAN_T::TEST: Silent Position */
#define CAN_TEST_SILENT_Msk (0x1ul << CAN_TEST_SILENT_Pos) /*!< CAN_T::TEST: Silent Mask */
#define CAN_TEST_LBACK_Pos (4) /*!< CAN_T::TEST: LBack Position */
#define CAN_TEST_LBACK_Msk (0x1ul << CAN_TEST_LBACK_Pos) /*!< CAN_T::TEST: LBack Mask */
#define CAN_TEST_Tx_Pos (5) /*!< CAN_T::TEST: Tx Position */
#define CAN_TEST_Tx_Msk (0x3ul << CAN_TEST_Tx_Pos) /*!< CAN_T::TEST: Tx Mask */
#define CAN_TEST_Rx_Pos (7) /*!< CAN_T::TEST: Rx Position */
#define CAN_TEST_Rx_Msk (0x1ul << CAN_TEST_Rx_Pos) /*!< CAN_T::TEST: Rx Mask */
#define CAN_BRPE_BRPE_Pos (0) /*!< CAN_T::BRPE: BRPE Position */
#define CAN_BRPE_BRPE_Msk (0xful << CAN_BRPE_BRPE_Pos) /*!< CAN_T::BRPE: BRPE Mask */
#define CAN_IF_CREQ_MSGNUM_Pos (0) /*!< CAN_IF_T::CREQ: MessageNumber Position*/
#define CAN_IF_CREQ_MSGNUM_Msk (0x3ful << CAN_IF_CREQ_MSGNUM_Pos) /*!< CAN_IF_T::CREQ: MessageNumber Mask */
#define CAN_IF_CREQ_BUSY_Pos (15) /*!< CAN_IF_T::CREQ: Busy Position */
#define CAN_IF_CREQ_BUSY_Msk (0x1ul << CAN_IF_CREQ_BUSY_Pos) /*!< CAN_IF_T::CREQ: Busy Mask */
#define CAN_IF_CMASK_DATAB_Pos (0) /*!< CAN_IF_T::CMASK: DAT_B Position */
#define CAN_IF_CMASK_DATAB_Msk (0x1ul << CAN_IF_CMASK_DATAB_Pos) /*!< CAN_IF_T::CMASK: DAT_B Mask */
#define CAN_IF_CMASK_DATAA_Pos (1) /*!< CAN_IF_T::CMASK: DAT_A Position */
#define CAN_IF_CMASK_DATAA_Msk (0x1ul << CAN_IF_CMASK_DATAA_Pos) /*!< CAN_IF_T::CMASK: DAT_A Mask */
#define CAN_IF_CMASK_TXRQSTNEWDAT_Pos (2) /*!< CAN_IF_T::CMASK: TxRqst_NewDat Position*/
#define CAN_IF_CMASK_TXRQSTNEWDAT_Msk (0x1ul << CAN_IF_CMASK_TXRQSTNEWDAT_Pos) /*!< CAN_IF_T::CMASK: TxRqst_NewDat Mask */
#define CAN_IF_CMASK_CLRINTPND_Pos (3) /*!< CAN_IF_T::CMASK: ClrIntPnd Position */
#define CAN_IF_CMASK_CLRINTPND_Msk (0x1ul << CAN_IF_CMASK_CLRINTPND_Pos) /*!< CAN_IF_T::CMASK: ClrIntPnd Mask */
#define CAN_IF_CMASK_CONTROL_Pos (4) /*!< CAN_IF_T::CMASK: Control Position */
#define CAN_IF_CMASK_CONTROL_Msk (0x1ul << CAN_IF_CMASK_CONTROL_Pos) /*!< CAN_IF_T::CMASK: Control Mask */
#define CAN_IF_CMASK_ARB_Pos (5) /*!< CAN_IF_T::CMASK: Arb Position */
#define CAN_IF_CMASK_ARB_Msk (0x1ul << CAN_IF_CMASK_ARB_Pos) /*!< CAN_IF_T::CMASK: Arb Mask */
#define CAN_IF_CMASK_MASK_Pos (6) /*!< CAN_IF_T::CMASK: Mask Position */
#define CAN_IF_CMASK_MASK_Msk (0x1ul << CAN_IF_CMASK_MASK_Pos) /*!< CAN_IF_T::CMASK: Mask Mask */
#define CAN_IF_CMASK_WRRD_Pos (7) /*!< CAN_IF_T::CMASK: WR_RD Position */
#define CAN_IF_CMASK_WRRD_Msk (0x1ul << CAN_IF_CMASK_WRRD_Pos) /*!< CAN_IF_T::CMASK: WR_RD Mask */
#define CAN_IF_MASK1_Msk_Pos (0) /*!< CAN_IF_T::MASK1: Msk Position */
#define CAN_IF_MASK1_Msk_Msk (0xfffful << CAN_IF_MASK1_Msk_Pos) /*!< CAN_IF_T::MASK1: Msk Mask */
#define CAN_IF_MASK2_Msk_Pos (0) /*!< CAN_IF_T::MASK2: Msk Position */
#define CAN_IF_MASK2_Msk_Msk (0x1ffful << CAN_IF_MASK2_Msk_Pos) /*!< CAN_IF_T::MASK2: Msk Mask */
#define CAN_IF_MASK2_MDIR_Pos (14) /*!< CAN_IF_T::MASK2: MDir Position */
#define CAN_IF_MASK2_MDIR_Msk (0x1ul << CAN_IF_MASK2_MDIR_Pos) /*!< CAN_IF_T::MASK2: MDir Mask */
#define CAN_IF_MASK2_MXTD_Pos (15) /*!< CAN_IF_T::MASK2: MXtd Position */
#define CAN_IF_MASK2_MXTD_Msk (0x1ul << CAN_IF_MASK2_MXTD_Pos) /*!< CAN_IF_T::MASK2: MXtd Mask */
#define CAN_IF_ARB1_ID_Pos (0) /*!< CAN_IF_T::ARB1: ID Position */
#define CAN_IF_ARB1_ID_Msk (0xfffful << CAN_IF_ARB1_ID_Pos) /*!< CAN_IF_T::ARB1: ID Mask */
#define CAN_IF_ARB2_ID_Pos (0) /*!< CAN_IF_T::ARB2: ID Position */
#define CAN_IF_ARB2_ID_Msk (0x1ffful << CAN_IF_ARB2_ID_Pos) /*!< CAN_IF_T::ARB2: ID Mask */
#define CAN_IF_ARB2_DIR_Pos (13) /*!< CAN_IF_T::ARB2: Dir Position */
#define CAN_IF_ARB2_DIR_Msk (0x1ul << CAN_IF_ARB2_DIR_Pos) /*!< CAN_IF_T::ARB2: Dir Mask */
#define CAN_IF_ARB2_XTD_Pos (14) /*!< CAN_IF_T::ARB2: Xtd Position */
#define CAN_IF_ARB2_XTD_Msk (0x1ul << CAN_IF_ARB2_XTD_Pos) /*!< CAN_IF_T::ARB2: Xtd Mask */
#define CAN_IF_ARB2_MSGVAL_Pos (15) /*!< CAN_IF_T::ARB2: MsgVal Position */
#define CAN_IF_ARB2_MSGVAL_Msk (0x1ul << CAN_IF_ARB2_MSGVAL_Pos) /*!< CAN_IF_T::ARB2: MsgVal Mask */
#define CAN_IF_MCON_DLC_Pos (0) /*!< CAN_IF_T::MCON: DLC Position */
#define CAN_IF_MCON_DLC_Msk (0xful << CAN_IF_MCON_DLC_Pos) /*!< CAN_IF_T::MCON: DLC Mask */
#define CAN_IF_MCON_EOB_Pos (7) /*!< CAN_IF_T::MCON: EoB Position */
#define CAN_IF_MCON_EOB_Msk (0x1ul << CAN_IF_MCON_EOB_Pos) /*!< CAN_IF_T::MCON: EoB Mask */
#define CAN_IF_MCON_TxRqst_Pos (8) /*!< CAN_IF_T::MCON: TxRqst Position */
#define CAN_IF_MCON_TxRqst_Msk (0x1ul << CAN_IF_MCON_TxRqst_Pos) /*!< CAN_IF_T::MCON: TxRqst Mask */
#define CAN_IF_MCON_RmtEn_Pos (9) /*!< CAN_IF_T::MCON: RmtEn Position */
#define CAN_IF_MCON_RmtEn_Msk (0x1ul << CAN_IF_MCON_RmtEn_Pos) /*!< CAN_IF_T::MCON: RmtEn Mask */
#define CAN_IF_MCON_RXIE_Pos (10) /*!< CAN_IF_T::MCON: RxIE Position */
#define CAN_IF_MCON_RXIE_Msk (0x1ul << CAN_IF_MCON_RXIE_Pos) /*!< CAN_IF_T::MCON: RxIE Mask */
#define CAN_IF_MCON_TXIE_Pos (11) /*!< CAN_IF_T::MCON: TxIE Position */
#define CAN_IF_MCON_TXIE_Msk (0x1ul << CAN_IF_MCON_TXIE_Pos) /*!< CAN_IF_T::MCON: TxIE Mask */
#define CAN_IF_MCON_UMASK_Pos (12) /*!< CAN_IF_T::MCON: UMask Position */
#define CAN_IF_MCON_UMASK_Msk (0x1ul << CAN_IF_MCON_UMASK_Pos) /*!< CAN_IF_T::MCON: UMask Mask */
#define CAN_IF_MCON_IntPnd_Pos (13) /*!< CAN_IF_T::MCON: IntPnd Position */
#define CAN_IF_MCON_IntPnd_Msk (0x1ul << CAN_IF_MCON_IntPnd_Pos) /*!< CAN_IF_T::MCON: IntPnd Mask */
#define CAN_IF_MCON_MsgLst_Pos (14) /*!< CAN_IF_T::MCON: MsgLst Position */
#define CAN_IF_MCON_MsgLst_Msk (0x1ul << CAN_IF_MCON_MsgLst_Pos) /*!< CAN_IF_T::MCON: MsgLst Mask */
#define CAN_IF_MCON_NEWDAT_Pos (15) /*!< CAN_IF_T::MCON: NewDat Position */
#define CAN_IF_MCON_NEWDAT_Msk (0x1ul << CAN_IF_MCON_NEWDAT_Pos) /*!< CAN_IF_T::MCON: NewDat Mask */
#define CAN_IF_DAT_A1_DATA0_Pos (0) /*!< CAN_IF_T::DAT_A1: Data_0_ Position */
#define CAN_IF_DAT_A1_DATA0_Msk (0xfful << CAN_IF_DAT_A1_DATA0_Pos) /*!< CAN_IF_T::DAT_A1: Data_0_ Mask */
#define CAN_IF_DAT_A1_DATA1_Pos (8) /*!< CAN_IF_T::DAT_A1: Data_1_ Position */
#define CAN_IF_DAT_A1_DATA1_Msk (0xfful << CAN_IF_DAT_A1_DATA1_Pos) /*!< CAN_IF_T::DAT_A1: Data_1_ Mask */
#define CAN_IF_DAT_A2_DATA2_Pos (0) /*!< CAN_IF_T::DAT_A2: Data_2_ Position */
#define CAN_IF_DAT_A2_DATA2_Msk (0xfful << CAN_IF_DAT_A2_DATA2_Pos) /*!< CAN_IF_T::DAT_A2: Data_2_ Mask */
#define CAN_IF_DAT_A2_DATA3_Pos (8) /*!< CAN_IF_T::DAT_A2: Data_3_ Position */
#define CAN_IF_DAT_A2_DATA3_Msk (0xfful << CAN_IF_DAT_A2_DATA3_Pos) /*!< CAN_IF_T::DAT_A2: Data_3_ Mask */
#define CAN_IF_DAT_B1_DATA4_Pos (0) /*!< CAN_IF_T::DAT_B1: Data_4_ Position */
#define CAN_IF_DAT_B1_DATA4_Msk (0xfful << CAN_IF_DAT_B1_DATA4_Pos) /*!< CAN_IF_T::DAT_B1: Data_4_ Mask */
#define CAN_IF_DAT_B1_DATA5_Pos (8) /*!< CAN_IF_T::DAT_B1: Data_5_ Position */
#define CAN_IF_DAT_B1_DATA5_Msk (0xfful << CAN_IF_DAT_B1_DATA5_Pos) /*!< CAN_IF_T::DAT_B1: Data_5_ Mask */
#define CAN_IF_DAT_B2_DATA6_Pos (0) /*!< CAN_IF_T::DAT_B2: Data_6_ Position */
#define CAN_IF_DAT_B2_DATA6_Msk (0xfful << CAN_IF_DAT_B2_DATA6_Pos) /*!< CAN_IF_T::DAT_B2: Data_6_ Mask */
#define CAN_IF_DAT_B2_DATA7_Pos (8) /*!< CAN_IF_T::DAT_B2: Data_7_ Position */
#define CAN_IF_DAT_B2_DATA7_Msk (0xfful << CAN_IF_DAT_B2_DATA7_Pos) /*!< CAN_IF_T::DAT_B2: Data_7_ Mask */
#define CAN_TXREQ1_TXRQST16_1_Pos (0) /*!< CAN_T::TXREQ1: TxRqst16_1 Position */
#define CAN_TXREQ1_TXRQST16_1_Msk (0xfffful << CAN_TXREQ1_TXRQST16_1_Pos) /*!< CAN_T::TXREQ1: TxRqst16_1 Mask */
#define CAN_TXREQ2_TXRQST32_17_Pos (0) /*!< CAN_T::TXREQ2: TxRqst32_17 Position */
#define CAN_TXREQ2_TXRQST32_17_Msk (0xfffful << CAN_TXREQ2_TXRQST32_17_Pos) /*!< CAN_T::TXREQ2: TxRqst32_17 Mask */
#define CAN_NDAT1_NewData16_1_Pos (0) /*!< CAN_T::NDAT1: NewData16_1 Position */
#define CAN_NDAT1_NewData16_1_Msk (0xfffful << CAN_NDAT1_NewData16_1_Pos) /*!< CAN_T::NDAT1: NewData16_1 Mask */
#define CAN_NDAT2_NewData32_17_Pos (0) /*!< CAN_T::NDAT2: NewData32_17 Position */
#define CAN_NDAT2_NewData32_17_Msk (0xfffful << CAN_NDAT2_NewData32_17_Pos) /*!< CAN_T::NDAT2: NewData32_17 Mask */
#define CAN_IPND1_IntPnd16_1_Pos (0) /*!< CAN_T::IPND1: IntPnd16_1 Position */
#define CAN_IPND1_IntPnd16_1_Msk (0xfffful << CAN_IPND1_IntPnd16_1_Pos) /*!< CAN_T::IPND1: IntPnd16_1 Mask */
#define CAN_IPND2_IntPnd32_17_Pos (0) /*!< CAN_T::IPND2: IntPnd32_17 Position */
#define CAN_IPND2_IntPnd32_17_Msk (0xfffful << CAN_IPND2_IntPnd32_17_Pos) /*!< CAN_T::IPND2: IntPnd32_17 Mask */
#define CAN_MVLD1_MsgVal16_1_Pos (0) /*!< CAN_T::MVLD1: MsgVal16_1 Position */
#define CAN_MVLD1_MsgVal16_1_Msk (0xfffful << CAN_MVLD1_MsgVal16_1_Pos) /*!< CAN_T::MVLD1: MsgVal16_1 Mask */
#define CAN_MVLD2_MsgVal32_17_Pos (0) /*!< CAN_T::MVLD2: MsgVal32_17 Position */
#define CAN_MVLD2_MsgVal32_17_Msk (0xfffful << CAN_MVLD2_MsgVal32_17_Pos) /*!< CAN_T::MVLD2: MsgVal32_17 Mask */
#define CAN_WU_EN_WAKUP_EN_Pos (0) /*!< CAN_T::WU_EN: WAKUP_EN Position */
#define CAN_WU_EN_WAKUP_EN_Msk (0x1ul << CAN_WU_EN_WAKUP_EN_Pos) /*!< CAN_T::WU_EN: WAKUP_EN Mask */
#define CAN_WU_STATUS_WAKUP_STS_Pos (0) /*!< CAN_T::WU_STATUS: WAKUP_STS Position */
#define CAN_WU_STATUS_WAKUP_STS_Msk (0x1ul << CAN_WU_STATUS_WAKUP_STS_Pos) /*!< CAN_T::WU_STATUS: WAKUP_STS Mask */
/**@}*/ /* CAN_CONST */
/**@}*/ /* end of CAN register group */
/*---------------------- SD Card Host Interface -------------------------*/
/**
@addtogroup SDH SD Card Host Interface(SDH)
Memory Mapped Structure for SDH Controller
@{ */
typedef struct {
/**
* @var SDH_T::FB
* Offset: 0x00~0x7C Shared Buffer (FIFO)
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |BUFFER |Shared Buffer
* | | |Buffer for DMA transfer
* @var SDH_T::DMACTL
* Offset: 0x400 DMA Control and Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |DMAEN |DMA Engine Enable Bit
* | | |0 = DMA Disabled.
* | | |1 = DMA Enabled.
* | | |If this bit is cleared, DMA will ignore all requests from SD host and force bus master into IDLE state.
* | | |Note: If target abort is occurred, DMAEN will be cleared.
* |[1] |DMARST |Software Engine Reset
* | | |0 = No effect.
* | | |1 = Reset internal state machine and pointers
* | | |The contents of control register will not be cleared
* | | |This bit will auto be cleared after few clock cycles.
* | | |Note: The software reset DMA related registers.
* |[3] |SGEN |Scatter-gather Function Enable Bit
* | | |0 = Scatter-gather function Disabled (DMA will treat the starting address in DMASAR as starting pointer of a single block memory).
* | | |1 = Scatter-gather function Enabled (DMA will treat the starting address in DMASAR as a starting address of Physical Address Descriptor (PAD) table
* | | |The format of these Pads' will be described later).
* |[9] |DMABUSY |DMA Transfer Is in Progress
* | | |This bit indicates if SD Host is granted and doing DMA transfer or not.
* | | |0 = DMA transfer is not in progress.
* | | |1 = DMA transfer is in progress.
* @var SDH_T::DMASA
* Offset: 0x408 DMA Transfer Starting Address Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ORDER |Determined to the PAD Table Fetching Is in Order or Out of Order
* | | |0 = PAD table is fetched in order.
* | | |1 = PAD table is fetched out of order.
* | | |Note: the bit0 is valid in scatter-gather mode when SGEN = 1.
* |[31:1] |DMASA |DMA Transfer Starting Address
* | | |This field pads 0 as least significant bit indicates a 32-bit starting address of system memory (SRAM) for DMA to retrieve or fill in data.
* | | |If DMA is not in normal mode, this field will be interpreted as a starting address of Physical Address Descriptor (PAD) table.
* | | |Note: Starting address of the SRAM must be word aligned, for example, 0x0000_0000, 0x0000_0004.
* @var SDH_T::DMABCNT
* Offset: 0x40C DMA Transfer Byte Count Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[25:0] |BCNT |DMA Transfer Byte Count (Read Only)
* | | |This field indicates the remained byte count of DMA transfer
* | | |The value of this field is valid only when DMA is busy; otherwise, it is 0.
* @var SDH_T::DMAINTEN
* Offset: 0x410 DMA Interrupt Enable Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ABORTIEN |DMA Read/Write Target Abort Interrupt Enable Bit
* | | |0 = Target abort interrupt generation Disabled during DMA transfer.
* | | |1 = Target abort interrupt generation Enabled during DMA transfer.
* |[1] |WEOTIEN |Wrong EOT Encountered Interrupt Enable Bit
* | | |0 = Interrupt generation Disabled when wrong EOT is encountered.
* | | |1 = Interrupt generation Enabled when wrong EOT is encountered.
* @var SDH_T::DMAINTSTS
* Offset: 0x414 DMA Interrupt Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ABORTIF |DMA Read/Write Target Abort Interrupt Flag
* | | |0 = No bus ERROR response received.
* | | |1 = Bus ERROR response received.
* | | |Note1: This bit is read only, but can be cleared by writing '1' to it.
* | | |Note2: When DMA's bus master received ERROR response, it means that target abort is happened
* | | |DMA will stop transfer and respond this event and then go to IDLE state
* | | |When target abort occurred or WEOTIF is set, software must reset DMA and SD host, and then transfer those data again.
* |[1] |WEOTIF |Wrong EOT Encountered Interrupt Flag
* | | |When DMA Scatter-Gather function is enabled, and EOT of the descriptor is encountered before DMA transfer finished (that means the total sector count of all PAD is less than the sector count of SD host), this bit will be set.
* | | |0 = No EOT encountered before DMA transfer finished.
* | | |1 = EOT encountered before DMA transfer finished.
* | | |Note: This bit is read only, but can be cleared by writing '1' to it.
* @var SDH_T::GCTL
* Offset: 0x800 Global Control and Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |GCTLRST |Software Engine Reset
* | | |0 = No effect.
* | | |1 = Reset SD host
* | | |The contents of control register will not be cleared
* | | |This bit will auto cleared after reset complete.
* |[1] |SDEN |Secure Digital Functionality Enable Bit
* | | |0 = SD functionality disabled.
* | | |1 = SD functionality enabled.
* @var SDH_T::GINTEN
* Offset: 0x804 Global Interrupt Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |DTAIEN |DMA READ/WRITE Target Abort Interrupt Enable Bit
* | | |0 = DMA READ/WRITE target abort interrupt generation disabled.
* | | |1 = DMA READ/WRITE target abort interrupt generation enabled.
* @var SDH_T::GINTSTS
* Offset: 0x808 Global Interrupt Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |DTAIF |DMA READ/WRITE Target Abort Interrupt Flag (Read Only)
* | | |This bit indicates DMA received an ERROR response from internal AHB bus during DMA read/write operation
* | | |When Target Abort is occurred, please reset all engine.
* | | |0 = No bus ERROR response received.
* | | |1 = Bus ERROR response received.
* | | |Note: This bit is read only, but can be cleared by writing '1' to it.
* @var SDH_T::CTL
* Offset: 0x820 SD Control and Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |COEN |Command Output Enable Bit
* | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.)
* | | |1 = Enabled, SD host will output a command to SD card.
* | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
* |[1] |RIEN |Response Input Enable Bit
* | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.)
* | | |1 = Enabled, SD host will wait to receive a response from SD card.
* | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
* |[2] |DIEN |Data Input Enable Bit
* | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.)
* | | |1 = Enabled, SD host will wait to receive block data and the CRC16 value from SD card.
* | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
* |[3] |DOEN |Data Output Enable Bit
* | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.)
* | | |1 = Enabled, SD host will transfer block data and the CRC16 value to SD card.
* | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
* |[4] |R2EN |Response R2 Input Enable Bit
* | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.)
* | | |1 = Enabled, SD host will wait to receive a response R2 from SD card and store the response data into DMC's flash buffer (exclude CRC7).
* | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
* |[5] |CLK74OEN |Initial 74 Clock Cycles Output Enable Bit
* | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.)
* | | |1 = Enabled, SD host will output 74 clock cycles to SD card.
* | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
* |[6] |CLK8OEN |Generating 8 Clock Cycles Output Enable Bit
* | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.)
* | | |1 = Enabled, SD host will output 8 clock cycles.
* | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
* |[7] |CLKKEEP |SD Clock Enable Control
* | | |0 = SD host decided when to output clock and when to disable clock output automatically.
* | | |1 = SD clock always keeps free running.
* |[13:8] |CMDCODE |SD Command Code
* | | |This register contains the SD command code (0x00 - 0x3F).
* |[14] |CTLRST |Software Engine Reset
* | | |0 = No effect.
* | | |1 = Reset the internal state machine and counters
* | | |The contents of control register will not be cleared (but RIEN, DIEN, DOEN and R2_EN will be cleared)
* | | |This bit will be auto cleared after few clock cycles.
* |[15] |DBW |SD Data Bus Width (for 1-bit / 4-bit Selection)
* | | |0 = Data bus width is 1-bit.
* | | |1 = Data bus width is 4-bit.
* |[23:16] |BLKCNT |Block Counts to Be Transferred or Received
* | | |This field contains the block counts for data-in and data-out transfer
* | | |For READ_MULTIPLE_BLOCK and WRITE_MULTIPLE_BLOCK command, software can use this function to accelerate data transfer and improve performance
* | | |Don't fill 0x0 to this field.
* | | |Note: For READ_MULTIPLE_BLOCK and WRITE_MULTIPLE_BLOCK command, the actual total length is BLKCNT * (BLKLEN +1).
* |[27:24] |SDNWR |NWR Parameter for Block Write Operation
* | | |This value indicates the NWR parameter for data block write operation in SD clock counts
* | | |The actual clock cycle will be SDNWR+1.
* @var SDH_T::CMDARG
* Offset: 0x824 SD Command Argument Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |ARGUMENT |SD Command Argument
* | | |This register contains a 32-bit value specifies the argument of SD command from host controller to SD card
* | | |Before trigger COEN (SDH_CTL [0]), software should fill argument in this field.
* @var SDH_T::INTEN
* Offset: 0x828 SD Interrupt Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |BLKDIEN |Block Transfer Done Interrupt Enable Bit
* | | |0 = BLKDIF (SDH_INTEN[0]) trigger interrupt Disable.
* | | |1 = BLKDIF (SDH_INTEN[0]) trigger interrupt Enabled.
* |[1] |CRCIEN |CRC7, CRC16 and CRC Status Error Interrupt Enable Bit
* | | |0 = CRCIF (SDH_INTEN[1]) trigger interrupt Disable.
* | | |1 = CRCIF (SDH_INTEN[1]) trigger interrupt Enabled.
* |[8] |CDIEN |SD Card Detection Interrupt Enable Bit
* | | |Enable/Disable interrupts generation of SD controller when card is inserted or removed.
* | | |0 = CDIF (SDH_INTEN[8]) trigger interrupt Disable.
* | | |1 = CDIF (SDH_INTEN[8]) trigger interrupt Enabled.
* |[12] |RTOIEN |Response Time-out Interrupt Enable Bit
* | | |Enable/Disable interrupts generation of SD controller when receiving response or R2 time-out
* | | |Time-out value is specified at TOUT register.
* | | |0 = RTOIF (SDH_INTEN[12]) trigger interrupt Disabled.
* | | |1 = RTOIF (SDH_INTEN[12]) trigger interrupt Enabled.
* |[13] |DITOIEN |Data Input Time-out Interrupt Enable Bit
* | | |Enable/Disable interrupts generation of SD controller when data input time-out
* | | |Time-out value is specified at TOUT register.
* | | |0 = DITOIF (SDH_INTEN[13]) trigger interrupt Disabled.
* | | |1 = DITOIF (SDH_INTEN[13]) trigger interrupt Enabled.
* |[14] |WKIEN |Wake-up Signal Generating Enable Bit
* | | |Enable/Disable wake-up signal generating of SD host when current using SD card issues an interrupt (wake-up) via DAT [1] to host.
* | | |0 = SD Card interrupt to wake-up chip Disabled.
* | | |1 = SD Card interrupt to wake-up chip Enabled.
* |[30] |CDSRC |SD Card Detect Source Selection
* | | |0 = From SD card's DAT3 pin.
* | | |Host need clock to got data on pin DAT3
* | | |Please make sure CLKKEEP (SDH_CTL[7]) is 1 in order to generate free running clock for DAT3 pin.
* | | |1 = From GPIO pin.
* @var SDH_T::INTSTS
* Offset: 0x82C SD Interrupt Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |BLKDIF |Block Transfer Done Interrupt Flag (Read Only)
* | | |This bit indicates that SD host has finished all data-in or data-out block transfer
* | | |If there is a CRC16 error or incorrect CRC status during multiple block data transfer, the transfer will be broken and this bit will also be set.
* | | |0 = Not finished yet.
* | | |1 = Done.
* | | |Note: This bit is read only, but can be cleared by writing '1' to it.
* |[1] |CRCIF |CRC7, CRC16 and CRC Status Error Interrupt Flag (Read Only)
* | | |This bit indicates that SD host has occurred CRC error during response in, data-in or data-out (CRC status error) transfer
* | | |When CRC error is occurred, software should reset SD engine
* | | |Some response (ex
* | | |R3) doesn't have CRC7 information with it; SD host will still calculate CRC7, get CRC error and set this flag
* | | |In this condition, software should ignore CRC error and clears this bit manually.
* | | |0 = No CRC error is occurred.
* | | |1 = CRC error is occurred.
* | | |Note: This bit is read only, but can be cleared by writing '1' to it.
* |[2] |CRC7 |CRC7 Check Status (Read Only)
* | | |SD host will check CRC7 correctness during each response in
* | | |If that response does not contain CRC7 information (ex
* | | |R3), then software should turn off CRCIEN (SDH_INTEN[1]) and ignore this bit.
* | | |0 = Fault.
* | | |1 = OK.
* |[3] |CRC16 |CRC16 Check Status of Data-in Transfer (Read Only)
* | | |SD host will check CRC16 correctness after data-in transfer.
* | | |0 = Fault.
* | | |1 = OK.
* |[6:4] |CRCSTS |CRC Status Value of Data-out Transfer (Read Only)
* | | |SD host will record CRC status of data-out transfer
* | | |Software could use this value to identify what type of error is during data-out transfer.
* | | |010 = Positive CRC status.
* | | |101 = Negative CRC status.
* | | |111 = SD card programming error occurs.
* |[7] |DAT0STS |DAT0 Pin Status of Current Selected SD Port (Read Only)
* | | |This bit is the DAT0 pin status of current selected SD port.
* |[8] |CDIF |SD Card Detection Interrupt Flag (Read Only)
* | | |This bit indicates that SD card is inserted or removed
* | | |Only when CDIEN (SDH_INTEN[8]) is set to 1, this bit is active.
* | | |0 = No card is inserted or removed.
* | | |1 = There is a card inserted in or removed from SD.
* | | |Note: This bit is read only, but can be cleared by writing '1' to it.
* |[12] |RTOIF |Response Time-out Interrupt Flag (Read Only)
* | | |This bit indicates that SD host counts to time-out value when receiving response or R2 (waiting start bit).
* | | |0 = Not time-out.
* | | |1 = Response time-out.
* | | |Note: This bit is read only, but can be cleared by writing '1' to it.
* |[13] |DITOIF |Data Input Time-out Interrupt Flag (Read Only)
* | | |This bit indicates that SD host counts to time-out value when receiving data (waiting start bit).
* | | |0 = Not time-out.
* | | |1 = Data input time-out.
* | | |Note: This bit is read only, but can be cleared by writing '1' to it.
* |[16] |CDSTS |Card Detect Status of SD (Read Only)
* | | |This bit indicates the card detect pin status of SD, and is used for card detection
* | | |When there is a card inserted in or removed from SD, software should check this bit to confirm if there is really a card insertion or removal.
* | | |If CDSRC (SDH_INTEN[30]) = 0, to select DAT3 for card detection:.
* | | |0 = Card removed.
* | | |1 = Card inserted.
* | | |If CDSRC (SDH_INTEN[30]) = 1, to select GPIO for card detection:.
* | | |0 = Card inserted.
* | | |1 = Card removed.
* |[18] |DAT1STS |DAT1 Pin Status of SD Port (Read Only)
* | | |This bit indicates the DAT1 pin status of SD port.
* @var SDH_T::RESP0
* Offset: 0x830 SD Receiving Response Token Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |RESPTK0 |SD Receiving Response Token 0
* | | |SD host controller will receive a response token for getting a reply from SD card when RIEN (SDH_CTL[1]) is set
* | | |This field contains response bit 47-16 of the response token.
* @var SDH_T::RESP1
* Offset: 0x834 SD Receiving Response Token Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |RESPTK1 |SD Receiving Response Token 1
* | | |SD host controller will receive a response token for getting a reply from SD card when RIEN (SDH_CTL[1]) is set
* | | |This register contains the bit 15-8 of the response token.
* @var SDH_T::BLEN
* Offset: 0x838 SD Block Length Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[10:0] |BLKLEN |SD BLOCK LENGTH in Byte Unit
* | | |An 11-bit value specifies the SD transfer byte count of a block
* | | |The actual byte count is equal to BLKLEN+1.
* | | |Note: The default SD block length is 512 bytes
* @var SDH_T::TOUT
* Offset: 0x83C SD Response/Data-in Time-out Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[23:0] |TOUT |SD Response/Data-in Time-out Value
* | | |A 24-bit value specifies the time-out counts of response and data input
* | | |SD host controller will wait start bit of response or data-in until this value reached
* | | |The time period depends on SD engine clock frequency
* | | |Do not write a small number into this field, or you may never get response or data due to time-out.
* | | |Note: Filling 0x0 into this field will disable hardware time-out function.
*/
__IO uint32_t FB[32]; /*!< Shared Buffer (FIFO) */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE0[224];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t DMACTL; /*!< [0x0400] DMA Control and Status Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE1[1];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t DMASA; /*!< [0x0408] DMA Transfer Starting Address Register */
__I uint32_t DMABCNT; /*!< [0x040c] DMA Transfer Byte Count Register */
__IO uint32_t DMAINTEN; /*!< [0x0410] DMA Interrupt Enable Control Register */
__IO uint32_t DMAINTSTS; /*!< [0x0414] DMA Interrupt Status Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE2[250];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t GCTL; /*!< [0x0800] Global Control and Status Register */
__IO uint32_t GINTEN; /*!< [0x0804] Global Interrupt Control Register */
__I uint32_t GINTSTS; /*!< [0x0808] Global Interrupt Status Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE3[5];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t CTL; /*!< [0x0820] SD Control and Status Register */
__IO uint32_t CMDARG; /*!< [0x0824] SD Command Argument Register */
__IO uint32_t INTEN; /*!< [0x0828] SD Interrupt Control Register */
__IO uint32_t INTSTS; /*!< [0x082c] SD Interrupt Status Register */
__I uint32_t RESP0; /*!< [0x0830] SD Receiving Response Token Register 0 */
__I uint32_t RESP1; /*!< [0x0834] SD Receiving Response Token Register 1 */
__IO uint32_t BLEN; /*!< [0x0838] SD Block Length Register */
__IO uint32_t TOUT; /*!< [0x083c] SD Response/Data-in Time-out Register */
} SDH_T;
/**
@addtogroup SDH_CONST SDH Bit Field Definition
Constant Definitions for SDH Controller
@{ */
#define SDH_DMACTL_DMAEN_Pos (0) /*!< SDH_T::DMACTL: DMAEN Position */
#define SDH_DMACTL_DMAEN_Msk (0x1ul << SDH_DMACTL_DMAEN_Pos) /*!< SDH_T::DMACTL: DMAEN Mask */
#define SDH_DMACTL_DMARST_Pos (1) /*!< SDH_T::DMACTL: DMARST Position */
#define SDH_DMACTL_DMARST_Msk (0x1ul << SDH_DMACTL_DMARST_Pos) /*!< SDH_T::DMACTL: DMARST Mask */
#define SDH_DMACTL_SGEN_Pos (3) /*!< SDH_T::DMACTL: SGEN Position */
#define SDH_DMACTL_SGEN_Msk (0x1ul << SDH_DMACTL_SGEN_Pos) /*!< SDH_T::DMACTL: SGEN Mask */
#define SDH_DMACTL_DMABUSY_Pos (9) /*!< SDH_T::DMACTL: DMABUSY Position */
#define SDH_DMACTL_DMABUSY_Msk (0x1ul << SDH_DMACTL_DMABUSY_Pos) /*!< SDH_T::DMACTL: DMABUSY Mask */
#define SDH_DMASA_ORDER_Pos (0) /*!< SDH_T::DMASA: ORDER Position */
#define SDH_DMASA_ORDER_Msk (0x1ul << SDH_DMASA_ORDER_Pos) /*!< SDH_T::DMASA: ORDER Mask */
#define SDH_DMASA_DMASA_Pos (1) /*!< SDH_T::DMASA: DMASA Position */
#define SDH_DMASA_DMASA_Msk (0x7ffffffful << SDH_DMASA_DMASA_Pos) /*!< SDH_T::DMASA: DMASA Mask */
#define SDH_DMABCNT_BCNT_Pos (0) /*!< SDH_T::DMABCNT: BCNT Position */
#define SDH_DMABCNT_BCNT_Msk (0x3fffffful << SDH_DMABCNT_BCNT_Pos) /*!< SDH_T::DMABCNT: BCNT Mask */
#define SDH_DMAINTEN_ABORTIEN_Pos (0) /*!< SDH_T::DMAINTEN: ABORTIEN Position */
#define SDH_DMAINTEN_ABORTIEN_Msk (0x1ul << SDH_DMAINTEN_ABORTIEN_Pos) /*!< SDH_T::DMAINTEN: ABORTIEN Mask */
#define SDH_DMAINTEN_WEOTIEN_Pos (1) /*!< SDH_T::DMAINTEN: WEOTIEN Position */
#define SDH_DMAINTEN_WEOTIEN_Msk (0x1ul << SDH_DMAINTEN_WEOTIEN_Pos) /*!< SDH_T::DMAINTEN: WEOTIEN Mask */
#define SDH_DMAINTSTS_ABORTIF_Pos (0) /*!< SDH_T::DMAINTSTS: ABORTIF Position */
#define SDH_DMAINTSTS_ABORTIF_Msk (0x1ul << SDH_DMAINTSTS_ABORTIF_Pos) /*!< SDH_T::DMAINTSTS: ABORTIF Mask */
#define SDH_DMAINTSTS_WEOTIF_Pos (1) /*!< SDH_T::DMAINTSTS: WEOTIF Position */
#define SDH_DMAINTSTS_WEOTIF_Msk (0x1ul << SDH_DMAINTSTS_WEOTIF_Pos) /*!< SDH_T::DMAINTSTS: WEOTIF Mask */
#define SDH_GCTL_GCTLRST_Pos (0) /*!< SDH_T::GCTL: GCTLRST Position */
#define SDH_GCTL_GCTLRST_Msk (0x1ul << SDH_GCTL_GCTLRST_Pos) /*!< SDH_T::GCTL: GCTLRST Mask */
#define SDH_GCTL_SDEN_Pos (1) /*!< SDH_T::GCTL: SDEN Position */
#define SDH_GCTL_SDEN_Msk (0x1ul << SDH_GCTL_SDEN_Pos) /*!< SDH_T::GCTL: SDEN Mask */
#define SDH_GINTEN_DTAIEN_Pos (0) /*!< SDH_T::GINTEN: DTAIEN Position */
#define SDH_GINTEN_DTAIEN_Msk (0x1ul << SDH_GINTEN_DTAIEN_Pos) /*!< SDH_T::GINTEN: DTAIEN Mask */
#define SDH_GINTSTS_DTAIF_Pos (0) /*!< SDH_T::GINTSTS: DTAIF Position */
#define SDH_GINTSTS_DTAIF_Msk (0x1ul << SDH_GINTSTS_DTAIF_Pos) /*!< SDH_T::GINTSTS: DTAIF Mask */
#define SDH_CTL_COEN_Pos (0) /*!< SDH_T::CTL: COEN Position */
#define SDH_CTL_COEN_Msk (0x1ul << SDH_CTL_COEN_Pos) /*!< SDH_T::CTL: COEN Mask */
#define SDH_CTL_RIEN_Pos (1) /*!< SDH_T::CTL: RIEN Position */
#define SDH_CTL_RIEN_Msk (0x1ul << SDH_CTL_RIEN_Pos) /*!< SDH_T::CTL: RIEN Mask */
#define SDH_CTL_DIEN_Pos (2) /*!< SDH_T::CTL: DIEN Position */
#define SDH_CTL_DIEN_Msk (0x1ul << SDH_CTL_DIEN_Pos) /*!< SDH_T::CTL: DIEN Mask */
#define SDH_CTL_DOEN_Pos (3) /*!< SDH_T::CTL: DOEN Position */
#define SDH_CTL_DOEN_Msk (0x1ul << SDH_CTL_DOEN_Pos) /*!< SDH_T::CTL: DOEN Mask */
#define SDH_CTL_R2EN_Pos (4) /*!< SDH_T::CTL: R2EN Position */
#define SDH_CTL_R2EN_Msk (0x1ul << SDH_CTL_R2EN_Pos) /*!< SDH_T::CTL: R2EN Mask */
#define SDH_CTL_CLK74OEN_Pos (5) /*!< SDH_T::CTL: CLK74OEN Position */
#define SDH_CTL_CLK74OEN_Msk (0x1ul << SDH_CTL_CLK74OEN_Pos) /*!< SDH_T::CTL: CLK74OEN Mask */
#define SDH_CTL_CLK8OEN_Pos (6) /*!< SDH_T::CTL: CLK8OEN Position */
#define SDH_CTL_CLK8OEN_Msk (0x1ul << SDH_CTL_CLK8OEN_Pos) /*!< SDH_T::CTL: CLK8OEN Mask */
#define SDH_CTL_CLKKEEP_Pos (7) /*!< SDH_T::CTL: CLKKEEP Position */
#define SDH_CTL_CLKKEEP_Msk (0x1ul << SDH_CTL_CLKKEEP_Pos) /*!< SDH_T::CTL: CLKKEEP Mask */
#define SDH_CTL_CMDCODE_Pos (8) /*!< SDH_T::CTL: CMDCODE Position */
#define SDH_CTL_CMDCODE_Msk (0x3ful << SDH_CTL_CMDCODE_Pos) /*!< SDH_T::CTL: CMDCODE Mask */
#define SDH_CTL_CTLRST_Pos (14) /*!< SDH_T::CTL: CTLRST Position */
#define SDH_CTL_CTLRST_Msk (0x1ul << SDH_CTL_CTLRST_Pos) /*!< SDH_T::CTL: CTLRST Mask */
#define SDH_CTL_DBW_Pos (15) /*!< SDH_T::CTL: DBW Position */
#define SDH_CTL_DBW_Msk (0x1ul << SDH_CTL_DBW_Pos) /*!< SDH_T::CTL: DBW Mask */
#define SDH_CTL_BLKCNT_Pos (16) /*!< SDH_T::CTL: BLKCNT Position */
#define SDH_CTL_BLKCNT_Msk (0xfful << SDH_CTL_BLKCNT_Pos) /*!< SDH_T::CTL: BLKCNT Mask */
#define SDH_CTL_SDNWR_Pos (24) /*!< SDH_T::CTL: SDNWR Position */
#define SDH_CTL_SDNWR_Msk (0xful << SDH_CTL_SDNWR_Pos) /*!< SDH_T::CTL: SDNWR Mask */
#define SDH_CMDARG_ARGUMENT_Pos (0) /*!< SDH_T::CMDARG: ARGUMENT Position */
#define SDH_CMDARG_ARGUMENT_Msk (0xfffffffful << SDH_CMDARG_ARGUMENT_Pos) /*!< SDH_T::CMDARG: ARGUMENT Mask */
#define SDH_INTEN_BLKDIEN_Pos (0) /*!< SDH_T::INTEN: BLKDIEN Position */
#define SDH_INTEN_BLKDIEN_Msk (0x1ul << SDH_INTEN_BLKDIEN_Pos) /*!< SDH_T::INTEN: BLKDIEN Mask */
#define SDH_INTEN_CRCIEN_Pos (1) /*!< SDH_T::INTEN: CRCIEN Position */
#define SDH_INTEN_CRCIEN_Msk (0x1ul << SDH_INTEN_CRCIEN_Pos) /*!< SDH_T::INTEN: CRCIEN Mask */
#define SDH_INTEN_CDIEN_Pos (8) /*!< SDH_T::INTEN: CDIEN Position */
#define SDH_INTEN_CDIEN_Msk (0x1ul << SDH_INTEN_CDIEN_Pos) /*!< SDH_T::INTEN: CDIEN Mask */
#define SDH_INTEN_RTOIEN_Pos (12) /*!< SDH_T::INTEN: RTOIEN Position */
#define SDH_INTEN_RTOIEN_Msk (0x1ul << SDH_INTEN_RTOIEN_Pos) /*!< SDH_T::INTEN: RTOIEN Mask */
#define SDH_INTEN_DITOIEN_Pos (13) /*!< SDH_T::INTEN: DITOIEN Position */
#define SDH_INTEN_DITOIEN_Msk (0x1ul << SDH_INTEN_DITOIEN_Pos) /*!< SDH_T::INTEN: DITOIEN Mask */
#define SDH_INTEN_WKIEN_Pos (14) /*!< SDH_T::INTEN: WKIEN Position */
#define SDH_INTEN_WKIEN_Msk (0x1ul << SDH_INTEN_WKIEN_Pos) /*!< SDH_T::INTEN: WKIEN Mask */
#define SDH_INTEN_CDSRC_Pos (30) /*!< SDH_T::INTEN: CDSRC Position */
#define SDH_INTEN_CDSRC_Msk (0x1ul << SDH_INTEN_CDSRC_Pos) /*!< SDH_T::INTEN: CDSRC Mask */
#define SDH_INTSTS_BLKDIF_Pos (0) /*!< SDH_T::INTSTS: BLKDIF Position */
#define SDH_INTSTS_BLKDIF_Msk (0x1ul << SDH_INTSTS_BLKDIF_Pos) /*!< SDH_T::INTSTS: BLKDIF Mask */
#define SDH_INTSTS_CRCIF_Pos (1) /*!< SDH_T::INTSTS: CRCIF Position */
#define SDH_INTSTS_CRCIF_Msk (0x1ul << SDH_INTSTS_CRCIF_Pos) /*!< SDH_T::INTSTS: CRCIF Mask */
#define SDH_INTSTS_CRC7_Pos (2) /*!< SDH_T::INTSTS: CRC7 Position */
#define SDH_INTSTS_CRC7_Msk (0x1ul << SDH_INTSTS_CRC7_Pos) /*!< SDH_T::INTSTS: CRC7 Mask */
#define SDH_INTSTS_CRC16_Pos (3) /*!< SDH_T::INTSTS: CRC16 Position */
#define SDH_INTSTS_CRC16_Msk (0x1ul << SDH_INTSTS_CRC16_Pos) /*!< SDH_T::INTSTS: CRC16 Mask */
#define SDH_INTSTS_CRCSTS_Pos (4) /*!< SDH_T::INTSTS: CRCSTS Position */
#define SDH_INTSTS_CRCSTS_Msk (0x7ul << SDH_INTSTS_CRCSTS_Pos) /*!< SDH_T::INTSTS: CRCSTS Mask */
#define SDH_INTSTS_DAT0STS_Pos (7) /*!< SDH_T::INTSTS: DAT0STS Position */
#define SDH_INTSTS_DAT0STS_Msk (0x1ul << SDH_INTSTS_DAT0STS_Pos) /*!< SDH_T::INTSTS: DAT0STS Mask */
#define SDH_INTSTS_CDIF_Pos (8) /*!< SDH_T::INTSTS: CDIF Position */
#define SDH_INTSTS_CDIF_Msk (0x1ul << SDH_INTSTS_CDIF_Pos) /*!< SDH_T::INTSTS: CDIF Mask */
#define SDH_INTSTS_RTOIF_Pos (12) /*!< SDH_T::INTSTS: RTOIF Position */
#define SDH_INTSTS_RTOIF_Msk (0x1ul << SDH_INTSTS_RTOIF_Pos) /*!< SDH_T::INTSTS: RTOIF Mask */
#define SDH_INTSTS_DITOIF_Pos (13) /*!< SDH_T::INTSTS: DITOIF Position */
#define SDH_INTSTS_DITOIF_Msk (0x1ul << SDH_INTSTS_DITOIF_Pos) /*!< SDH_T::INTSTS: DITOIF Mask */
#define SDH_INTSTS_CDSTS_Pos (16) /*!< SDH_T::INTSTS: CDSTS Position */
#define SDH_INTSTS_CDSTS_Msk (0x1ul << SDH_INTSTS_CDSTS_Pos) /*!< SDH_T::INTSTS: CDSTS Mask */
#define SDH_INTSTS_DAT1STS_Pos (18) /*!< SDH_T::INTSTS: DAT1STS Position */
#define SDH_INTSTS_DAT1STS_Msk (0x1ul << SDH_INTSTS_DAT1STS_Pos) /*!< SDH_T::INTSTS: DAT1STS Mask */
#define SDH_RESP0_RESPTK0_Pos (0) /*!< SDH_T::RESP0: RESPTK0 Position */
#define SDH_RESP0_RESPTK0_Msk (0xfffffffful << SDH_RESP0_RESPTK0_Pos) /*!< SDH_T::RESP0: RESPTK0 Mask */
#define SDH_RESP1_RESPTK1_Pos (0) /*!< SDH_T::RESP1: RESPTK1 Position */
#define SDH_RESP1_RESPTK1_Msk (0xfful << SDH_RESP1_RESPTK1_Pos) /*!< SDH_T::RESP1: RESPTK1 Mask */
#define SDH_BLEN_BLKLEN_Pos (0) /*!< SDH_T::BLEN: BLKLEN Position */
#define SDH_BLEN_BLKLEN_Msk (0x7fful << SDH_BLEN_BLKLEN_Pos) /*!< SDH_T::BLEN: BLKLEN Mask */
#define SDH_TOUT_TOUT_Pos (0) /*!< SDH_T::TOUT: TOUT Position */
#define SDH_TOUT_TOUT_Msk (0xfffffful << SDH_TOUT_TOUT_Pos) /*!< SDH_T::TOUT: TOUT Mask */
/**@}*/ /* SDH_CONST */
/**@}*/ /* end of SDH register group */
/*---------------------- External Bus Interface Controller -------------------------*/
/**
@addtogroup EBI External Bus Interface Controller(EBI)
Memory Mapped Structure for EBI Controller
@{ */
typedef struct {
/**
* @var EBI_T::CTL0
* Offset: 0x00 External Bus Interface Bank0 Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |EN |EBI Enable Bit
* | | |This bit is the functional enable bit for EBI.
* | | |0 = EBI function Disabled.
* | | |1 = EBI function Enabled.
* |[1] |DW16 |EBI Data Width 16-bit Select
* | | |This bit defines if the EBI data width is 8-bit or 16-bit.
* | | |0 = EBI data width is 8-bit.
* | | |1 = EBI data width is 16-bit.
* |[2] |CSPOLINV |Chip Select Pin Polar Inverse
* | | |This bit defines the active level of EBI chip select pin (EBI_nCS).
* | | |0 = Chip select pin (EBI_nCS) is active low.
* | | |1 = Chip select pin (EBI_nCS) is active high.
* |[3] |ADSEPEN |EBI Address/Data Bus Separating Mode Enable Bit
* | | |0 = Address/Data Bus Separating Mode Disabled.
* | | |1 = Address/Data Bus Separating Mode Enabled.
* |[4] |CACCESS |Continuous Data Access Mode
* | | |When con tenuous access mode enabled, the tASU, tALE and tLHD cycles are bypass for continuous data transfer request.
* | | |0 = Continuous data access mode Disabled.
* | | |1 = Continuous data access mode Enabled.
* |[10:8] |MCLKDIV |External Output Clock Divider
* | | |The frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow:
* | | |000 = HCLK/1.
* | | |001 = HCLK/2.
* | | |010 = HCLK/4.
* | | |011 = HCLK/8.
* | | |100 = HCLK/16.
* | | |101 = HCLK/32.
* | | |110 = HCLK/64.
* | | |111 = HCLK/128.
* |[18:16] |TALE |Extend Time of ALE
* | | |The EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE.
* | | |tALE = (TALE+1)*EBI_MCLK.
* | | |Note: This field only available in EBI_CTL0 register
* |[24] |WBUFEN |EBI Write Buffer Enable Bit
* | | |0 = EBI write buffer Disabled.
* | | |1 = EBI write buffer Enabled.
* | | |Note: This bit only available in EBI_CTL0 register
* @var EBI_T::TCTL0
* Offset: 0x04 External Bus Interface Bank0 Timing Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:3] |TACC |EBI Data Access Time
* | | |TACC define data access time (tACC).
* | | |tACC = (TACC +1) * EBI_MCLK.
* |[10:8] |TAHD |EBI Data Access Hold Time
* | | |TAHD define data access hold time (tAHD).
* | | |tAHD = (TAHD +1) * EBI_MCLK.
* |[15:12] |W2X |Idle Cycle After Write
* | | |This field defines the number of W2X idle cycle.
* | | |W2X idle cycle = (W2X * EBI_MCLK).
* | | |When write action is finish, W2X idle cycle is inserted and EBI_nCS return to idle state.
* |[22] |RAHDOFF |Access Hold Time Disable Control When Read
* | | |0 = The Data Access Hold Time (tAHD) during EBI reading is Enabled.
* | | |1 = The Data Access Hold Time (tAHD) during EBI reading is Disabled.
* |[23] |WAHDOFF |Access Hold Time Disable Control When Write
* | | |0 = The Data Access Hold Time (tAHD) during EBI writing is Enabled.
* | | |1 = The Data Access Hold Time (tAHD) during EBI writing is Disabled.
* |[27:24] |R2R |Idle Cycle Between Read-to-read
* | | |This field defines the number of R2R idle cycle.
* | | |R2R idle cycle = (R2R * EBI_MCLK).
* | | |When read action is finish and next action is going to read, R2R idle cycle is inserted and EBI_nCS return to idle state.
* @var EBI_T::CTL1
* Offset: 0x10 External Bus Interface Bank1 Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |EN |EBI Enable Bit
* | | |This bit is the functional enable bit for EBI.
* | | |0 = EBI function Disabled.
* | | |1 = EBI function Enabled.
* |[1] |DW16 |EBI Data Width 16-bit Select
* | | |This bit defines if the EBI data width is 8-bit or 16-bit.
* | | |0 = EBI data width is 8-bit.
* | | |1 = EBI data width is 16-bit.
* |[2] |CSPOLINV |Chip Select Pin Polar Inverse
* | | |This bit defines the active level of EBI chip select pin (EBI_nCS).
* | | |0 = Chip select pin (EBI_nCS) is active low.
* | | |1 = Chip select pin (EBI_nCS) is active high.
* |[3] |ADSEPEN |EBI Address/Data Bus Separating Mode Enable Bit
* | | |0 = Address/Data Bus Separating Mode Disabled.
* | | |1 = Address/Data Bus Separating Mode Enabled.
* |[4] |CACCESS |Continuous Data Access Mode
* | | |When con tenuous access mode enabled, the tASU, tALE and tLHD cycles are bypass for continuous data transfer request.
* | | |0 = Continuous data access mode Disabled.
* | | |1 = Continuous data access mode Enabled.
* |[10:8] |MCLKDIV |External Output Clock Divider
* | | |The frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow:
* | | |000 = HCLK/1.
* | | |001 = HCLK/2.
* | | |010 = HCLK/4.
* | | |011 = HCLK/8.
* | | |100 = HCLK/16.
* | | |101 = HCLK/32.
* | | |110 = HCLK/64.
* | | |111 = HCLK/128.
* |[18:16] |TALE |Extend Time of ALE
* | | |The EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE.
* | | |tALE = (TALE+1)*EBI_MCLK.
* | | |Note: This field only available in EBI_CTL0 register
* |[24] |WBUFEN |EBI Write Buffer Enable Bit
* | | |0 = EBI write buffer Disabled.
* | | |1 = EBI write buffer Enabled.
* | | |Note: This bit only available in EBI_CTL0 register
* @var EBI_T::TCTL1
* Offset: 0x14 External Bus Interface Bank1 Timing Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:3] |TACC |EBI Data Access Time
* | | |TACC define data access time (tACC).
* | | |tACC = (TACC +1) * EBI_MCLK.
* |[10:8] |TAHD |EBI Data Access Hold Time
* | | |TAHD define data access hold time (tAHD).
* | | |tAHD = (TAHD +1) * EBI_MCLK.
* |[15:12] |W2X |Idle Cycle After Write
* | | |This field defines the number of W2X idle cycle.
* | | |W2X idle cycle = (W2X * EBI_MCLK).
* | | |When write action is finish, W2X idle cycle is inserted and EBI_nCS return to idle state.
* |[22] |RAHDOFF |Access Hold Time Disable Control When Read
* | | |0 = The Data Access Hold Time (tAHD) during EBI reading is Enabled.
* | | |1 = The Data Access Hold Time (tAHD) during EBI reading is Disabled.
* |[23] |WAHDOFF |Access Hold Time Disable Control When Write
* | | |0 = The Data Access Hold Time (tAHD) during EBI writing is Enabled.
* | | |1 = The Data Access Hold Time (tAHD) during EBI writing is Disabled.
* |[27:24] |R2R |Idle Cycle Between Read-to-read
* | | |This field defines the number of R2R idle cycle.
* | | |R2R idle cycle = (R2R * EBI_MCLK).
* | | |When read action is finish and next action is going to read, R2R idle cycle is inserted and EBI_nCS return to idle state.
* @var EBI_T::CTL2
* Offset: 0x20 External Bus Interface Bank2 Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |EN |EBI Enable Bit
* | | |This bit is the functional enable bit for EBI.
* | | |0 = EBI function Disabled.
* | | |1 = EBI function Enabled.
* |[1] |DW16 |EBI Data Width 16-bit Select
* | | |This bit defines if the EBI data width is 8-bit or 16-bit.
* | | |0 = EBI data width is 8-bit.
* | | |1 = EBI data width is 16-bit.
* |[2] |CSPOLINV |Chip Select Pin Polar Inverse
* | | |This bit defines the active level of EBI chip select pin (EBI_nCS).
* | | |0 = Chip select pin (EBI_nCS) is active low.
* | | |1 = Chip select pin (EBI_nCS) is active high.
* |[3] |ADSEPEN |EBI Address/Data Bus Separating Mode Enable Bit
* | | |0 = Address/Data Bus Separating Mode Disabled.
* | | |1 = Address/Data Bus Separating Mode Enabled.
* |[4] |CACCESS |Continuous Data Access Mode
* | | |When con tenuous access mode enabled, the tASU, tALE and tLHD cycles are bypass for continuous data transfer request.
* | | |0 = Continuous data access mode Disabled.
* | | |1 = Continuous data access mode Enabled.
* |[10:8] |MCLKDIV |External Output Clock Divider
* | | |The frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow:
* | | |000 = HCLK/1.
* | | |001 = HCLK/2.
* | | |010 = HCLK/4.
* | | |011 = HCLK/8.
* | | |100 = HCLK/16.
* | | |101 = HCLK/32.
* | | |110 = HCLK/64.
* | | |111 = HCLK/128.
* |[18:16] |TALE |Extend Time of ALE
* | | |The EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE.
* | | |tALE = (TALE+1)*EBI_MCLK.
* | | |Note: This field only available in EBI_CTL0 register
* |[24] |WBUFEN |EBI Write Buffer Enable Bit
* | | |0 = EBI write buffer Disabled.
* | | |1 = EBI write buffer Enabled.
* | | |Note: This bit only available in EBI_CTL0 register
* @var EBI_T::TCTL2
* Offset: 0x24 External Bus Interface Bank2 Timing Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:3] |TACC |EBI Data Access Time
* | | |TACC define data access time (tACC).
* | | |tACC = (TACC +1) * EBI_MCLK.
* |[10:8] |TAHD |EBI Data Access Hold Time
* | | |TAHD define data access hold time (tAHD).
* | | |tAHD = (TAHD +1) * EBI_MCLK.
* |[15:12] |W2X |Idle Cycle After Write
* | | |This field defines the number of W2X idle cycle.
* | | |W2X idle cycle = (W2X * EBI_MCLK).
* | | |When write action is finish, W2X idle cycle is inserted and EBI_nCS return to idle state.
* |[22] |RAHDOFF |Access Hold Time Disable Control When Read
* | | |0 = The Data Access Hold Time (tAHD) during EBI reading is Enabled.
* | | |1 = The Data Access Hold Time (tAHD) during EBI reading is Disabled.
* |[23] |WAHDOFF |Access Hold Time Disable Control When Write
* | | |0 = The Data Access Hold Time (tAHD) during EBI writing is Enabled.
* | | |1 = The Data Access Hold Time (tAHD) during EBI writing is Disabled.
* |[27:24] |R2R |Idle Cycle Between Read-to-read
* | | |This field defines the number of R2R idle cycle.
* | | |R2R idle cycle = (R2R * EBI_MCLK).
* | | |When read action is finish and next action is going to read, R2R idle cycle is inserted and EBI_nCS return to idle state.
*/
__IO uint32_t CTL0; /*!< [0x0000] External Bus Interface Bank0 Control Register */
__IO uint32_t TCTL0; /*!< [0x0004] External Bus Interface Bank0 Timing Control Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE0[2];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t CTL1; /*!< [0x0010] External Bus Interface Bank1 Control Register */
__IO uint32_t TCTL1; /*!< [0x0014] External Bus Interface Bank1 Timing Control Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE1[2];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t CTL2; /*!< [0x0020] External Bus Interface Bank2 Control Register */
__IO uint32_t TCTL2; /*!< [0x0024] External Bus Interface Bank2 Timing Control Register */
} EBI_T;
/**
@addtogroup EBI_CONST EBI Bit Field Definition
Constant Definitions for EBI Controller
@{ */
#define EBI_CTL_EN_Pos (0) /*!< EBI_T::CTL: EN Position */
#define EBI_CTL_EN_Msk (0x1ul << EBI_CTL_EN_Pos) /*!< EBI_T::CTL: EN Mask */
#define EBI_CTL_DW16_Pos (1) /*!< EBI_T::CTL: DW16 Position */
#define EBI_CTL_DW16_Msk (0x1ul << EBI_CTL_DW16_Pos) /*!< EBI_T::CTL: DW16 Mask */
#define EBI_CTL_CSPOLINV_Pos (2) /*!< EBI_T::CTL: CSPOLINV Position */
#define EBI_CTL_CSPOLINV_Msk (0x1ul << EBI_CTL_CSPOLINV_Pos) /*!< EBI_T::CTL: CSPOLINV Mask */
#define EBI_CTL_ADSEPEN_Pos (3) /*!< EBI_T::CTL: ADSEPEN Position */
#define EBI_CTL_ADSEPEN_Msk (0x1ul << EBI_CTL_ADSEPEN_Pos) /*!< EBI_T::CTL: ADSEPEN Mask */
#define EBI_CTL_CACCESS_Pos (4) /*!< EBI_T::CTL: CACCESS Position */
#define EBI_CTL_CACCESS_Msk (0x1ul << EBI_CTL_CACCESS_Pos) /*!< EBI_T::CTL: CACCESS Mask */
#define EBI_CTL_MCLKDIV_Pos (8) /*!< EBI_T::CTL: MCLKDIV Position */
#define EBI_CTL_MCLKDIV_Msk (0x7ul << EBI_CTL_MCLKDIV_Pos) /*!< EBI_T::CTL: MCLKDIV Mask */
#define EBI_CTL_TALE_Pos (16) /*!< EBI_T::CTL: TALE Position */
#define EBI_CTL_TALE_Msk (0x7ul << EBI_CTL_TALE_Pos) /*!< EBI_T::CTL: TALE Mask */
#define EBI_CTL_WBUFEN_Pos (24) /*!< EBI_T::CTL: WBUFEN Position */
#define EBI_CTL_WBUFEN_Msk (0x1ul << EBI_CTL_WBUFEN_Pos) /*!< EBI_T::CTL: WBUFEN Mask */
#define EBI_TCTL_TACC_Pos (3) /*!< EBI_T::TCTL: TACC Position */
#define EBI_TCTL_TACC_Msk (0x1ful << EBI_TCTL_TACC_Pos) /*!< EBI_T::TCTL: TACC Mask */
#define EBI_TCTL_TAHD_Pos (8) /*!< EBI_T::TCTL: TAHD Position */
#define EBI_TCTL_TAHD_Msk (0x7ul << EBI_TCTL_TAHD_Pos) /*!< EBI_T::TCTL: TAHD Mask */
#define EBI_TCTL_W2X_Pos (12) /*!< EBI_T::TCTL: W2X Position */
#define EBI_TCTL_W2X_Msk (0xful << EBI_TCTL_W2X_Pos) /*!< EBI_T::TCTL: W2X Mask */
#define EBI_TCTL_RAHDOFF_Pos (22) /*!< EBI_T::TCTL: RAHDOFF Position */
#define EBI_TCTL_RAHDOFF_Msk (0x1ul << EBI_TCTL_RAHDOFF_Pos) /*!< EBI_T::TCTL: RAHDOFF Mask */
#define EBI_TCTL_WAHDOFF_Pos (23) /*!< EBI_T::TCTL: WAHDOFF Position */
#define EBI_TCTL_WAHDOFF_Msk (0x1ul << EBI_TCTL_WAHDOFF_Pos) /*!< EBI_T::TCTL: WAHDOFF Mask */
#define EBI_TCTL_R2R_Pos (24) /*!< EBI_T::TCTL: R2R Position */
#define EBI_TCTL_R2R_Msk (0xful << EBI_TCTL_R2R_Pos) /*!< EBI_T::TCTL: R2R Mask */
#define EBI_CTL0_EN_Pos (0) /*!< EBI_T::CTL0: EN Position */
#define EBI_CTL0_EN_Msk (0x1ul << EBI_CTL0_EN_Pos) /*!< EBI_T::CTL0: EN Mask */
#define EBI_CTL0_DW16_Pos (1) /*!< EBI_T::CTL0: DW16 Position */
#define EBI_CTL0_DW16_Msk (0x1ul << EBI_CTL0_DW16_Pos) /*!< EBI_T::CTL0: DW16 Mask */
#define EBI_CTL0_CSPOLINV_Pos (2) /*!< EBI_T::CTL0: CSPOLINV Position */
#define EBI_CTL0_CSPOLINV_Msk (0x1ul << EBI_CTL0_CSPOLINV_Pos) /*!< EBI_T::CTL0: CSPOLINV Mask */
#define EBI_CTL0_ADSEPEN_Pos (3) /*!< EBI_T::CTL0: ADSEPEN Position */
#define EBI_CTL0_ADSEPEN_Msk (0x1ul << EBI_CTL0_ADSEPEN_Pos) /*!< EBI_T::CTL0: ADSEPEN Mask */
#define EBI_CTL0_CACCESS_Pos (4) /*!< EBI_T::CTL0: CACCESS Position */
#define EBI_CTL0_CACCESS_Msk (0x1ul << EBI_CTL0_CACCESS_Pos) /*!< EBI_T::CTL0: CACCESS Mask */
#define EBI_CTL0_MCLKDIV_Pos (8) /*!< EBI_T::CTL0: MCLKDIV Position */
#define EBI_CTL0_MCLKDIV_Msk (0x7ul << EBI_CTL0_MCLKDIV_Pos) /*!< EBI_T::CTL0: MCLKDIV Mask */
#define EBI_CTL0_TALE_Pos (16) /*!< EBI_T::CTL0: TALE Position */
#define EBI_CTL0_TALE_Msk (0x7ul << EBI_CTL0_TALE_Pos) /*!< EBI_T::CTL0: TALE Mask */
#define EBI_CTL0_WBUFEN_Pos (24) /*!< EBI_T::CTL0: WBUFEN Position */
#define EBI_CTL0_WBUFEN_Msk (0x1ul << EBI_CTL0_WBUFEN_Pos) /*!< EBI_T::CTL0: WBUFEN Mask */
#define EBI_TCTL0_TACC_Pos (3) /*!< EBI_T::TCTL0: TACC Position */
#define EBI_TCTL0_TACC_Msk (0x1ful << EBI_TCTL0_TACC_Pos) /*!< EBI_T::TCTL0: TACC Mask */
#define EBI_TCTL0_TAHD_Pos (8) /*!< EBI_T::TCTL0: TAHD Position */
#define EBI_TCTL0_TAHD_Msk (0x7ul << EBI_TCTL0_TAHD_Pos) /*!< EBI_T::TCTL0: TAHD Mask */
#define EBI_TCTL0_W2X_Pos (12) /*!< EBI_T::TCTL0: W2X Position */
#define EBI_TCTL0_W2X_Msk (0xful << EBI_TCTL0_W2X_Pos) /*!< EBI_T::TCTL0: W2X Mask */
#define EBI_TCTL0_RAHDOFF_Pos (22) /*!< EBI_T::TCTL0: RAHDOFF Position */
#define EBI_TCTL0_RAHDOFF_Msk (0x1ul << EBI_TCTL0_RAHDOFF_Pos) /*!< EBI_T::TCTL0: RAHDOFF Mask */
#define EBI_TCTL0_WAHDOFF_Pos (23) /*!< EBI_T::TCTL0: WAHDOFF Position */
#define EBI_TCTL0_WAHDOFF_Msk (0x1ul << EBI_TCTL0_WAHDOFF_Pos) /*!< EBI_T::TCTL0: WAHDOFF Mask */
#define EBI_TCTL0_R2R_Pos (24) /*!< EBI_T::TCTL0: R2R Position */
#define EBI_TCTL0_R2R_Msk (0xful << EBI_TCTL0_R2R_Pos) /*!< EBI_T::TCTL0: R2R Mask */
#define EBI_CTL1_EN_Pos (0) /*!< EBI_T::CTL1: EN Position */
#define EBI_CTL1_EN_Msk (0x1ul << EBI_CTL1_EN_Pos) /*!< EBI_T::CTL1: EN Mask */
#define EBI_CTL1_DW16_Pos (1) /*!< EBI_T::CTL1: DW16 Position */
#define EBI_CTL1_DW16_Msk (0x1ul << EBI_CTL1_DW16_Pos) /*!< EBI_T::CTL1: DW16 Mask */
#define EBI_CTL1_CSPOLINV_Pos (2) /*!< EBI_T::CTL1: CSPOLINV Position */
#define EBI_CTL1_CSPOLINV_Msk (0x1ul << EBI_CTL1_CSPOLINV_Pos) /*!< EBI_T::CTL1: CSPOLINV Mask */
#define EBI_CTL1_ADSEPEN_Pos (3) /*!< EBI_T::CTL1: ADSEPEN Position */
#define EBI_CTL1_ADSEPEN_Msk (0x1ul << EBI_CTL1_ADSEPEN_Pos) /*!< EBI_T::CTL1: ADSEPEN Mask */
#define EBI_CTL1_CACCESS_Pos (4) /*!< EBI_T::CTL1: CACCESS Position */
#define EBI_CTL1_CACCESS_Msk (0x1ul << EBI_CTL1_CACCESS_Pos) /*!< EBI_T::CTL1: CACCESS Mask */
#define EBI_CTL1_MCLKDIV_Pos (8) /*!< EBI_T::CTL1: MCLKDIV Position */
#define EBI_CTL1_MCLKDIV_Msk (0x7ul << EBI_CTL1_MCLKDIV_Pos) /*!< EBI_T::CTL1: MCLKDIV Mask */
#define EBI_CTL1_TALE_Pos (16) /*!< EBI_T::CTL1: TALE Position */
#define EBI_CTL1_TALE_Msk (0x7ul << EBI_CTL1_TALE_Pos) /*!< EBI_T::CTL1: TALE Mask */
#define EBI_CTL1_WBUFEN_Pos (24) /*!< EBI_T::CTL1: WBUFEN Position */
#define EBI_CTL1_WBUFEN_Msk (0x1ul << EBI_CTL1_WBUFEN_Pos) /*!< EBI_T::CTL1: WBUFEN Mask */
#define EBI_TCTL1_TACC_Pos (3) /*!< EBI_T::TCTL1: TACC Position */
#define EBI_TCTL1_TACC_Msk (0x1ful << EBI_TCTL1_TACC_Pos) /*!< EBI_T::TCTL1: TACC Mask */
#define EBI_TCTL1_TAHD_Pos (8) /*!< EBI_T::TCTL1: TAHD Position */
#define EBI_TCTL1_TAHD_Msk (0x7ul << EBI_TCTL1_TAHD_Pos) /*!< EBI_T::TCTL1: TAHD Mask */
#define EBI_TCTL1_W2X_Pos (12) /*!< EBI_T::TCTL1: W2X Position */
#define EBI_TCTL1_W2X_Msk (0xful << EBI_TCTL1_W2X_Pos) /*!< EBI_T::TCTL1: W2X Mask */
#define EBI_TCTL1_RAHDOFF_Pos (22) /*!< EBI_T::TCTL1: RAHDOFF Position */
#define EBI_TCTL1_RAHDOFF_Msk (0x1ul << EBI_TCTL1_RAHDOFF_Pos) /*!< EBI_T::TCTL1: RAHDOFF Mask */
#define EBI_TCTL1_WAHDOFF_Pos (23) /*!< EBI_T::TCTL1: WAHDOFF Position */
#define EBI_TCTL1_WAHDOFF_Msk (0x1ul << EBI_TCTL1_WAHDOFF_Pos) /*!< EBI_T::TCTL1: WAHDOFF Mask */
#define EBI_TCTL1_R2R_Pos (24) /*!< EBI_T::TCTL1: R2R Position */
#define EBI_TCTL1_R2R_Msk (0xful << EBI_TCTL1_R2R_Pos) /*!< EBI_T::TCTL1: R2R Mask */
#define EBI_CTL2_EN_Pos (0) /*!< EBI_T::CTL2: EN Position */
#define EBI_CTL2_EN_Msk (0x1ul << EBI_CTL2_EN_Pos) /*!< EBI_T::CTL2: EN Mask */
#define EBI_CTL2_DW16_Pos (1) /*!< EBI_T::CTL2: DW16 Position */
#define EBI_CTL2_DW16_Msk (0x1ul << EBI_CTL2_DW16_Pos) /*!< EBI_T::CTL2: DW16 Mask */
#define EBI_CTL2_CSPOLINV_Pos (2) /*!< EBI_T::CTL2: CSPOLINV Position */
#define EBI_CTL2_CSPOLINV_Msk (0x1ul << EBI_CTL2_CSPOLINV_Pos) /*!< EBI_T::CTL2: CSPOLINV Mask */
#define EBI_CTL2_ADSEPEN_Pos (3) /*!< EBI_T::CTL2: ADSEPEN Position */
#define EBI_CTL2_ADSEPEN_Msk (0x1ul << EBI_CTL2_ADSEPEN_Pos) /*!< EBI_T::CTL2: ADSEPEN Mask */
#define EBI_CTL2_CACCESS_Pos (4) /*!< EBI_T::CTL2: CACCESS Position */
#define EBI_CTL2_CACCESS_Msk (0x1ul << EBI_CTL2_CACCESS_Pos) /*!< EBI_T::CTL2: CACCESS Mask */
#define EBI_CTL2_MCLKDIV_Pos (8) /*!< EBI_T::CTL2: MCLKDIV Position */
#define EBI_CTL2_MCLKDIV_Msk (0x7ul << EBI_CTL2_MCLKDIV_Pos) /*!< EBI_T::CTL2: MCLKDIV Mask */
#define EBI_CTL2_TALE_Pos (16) /*!< EBI_T::CTL2: TALE Position */
#define EBI_CTL2_TALE_Msk (0x7ul << EBI_CTL2_TALE_Pos) /*!< EBI_T::CTL2: TALE Mask */
#define EBI_CTL2_WBUFEN_Pos (24) /*!< EBI_T::CTL2: WBUFEN Position */
#define EBI_CTL2_WBUFEN_Msk (0x1ul << EBI_CTL2_WBUFEN_Pos) /*!< EBI_T::CTL2: WBUFEN Mask */
#define EBI_TCTL2_TACC_Pos (3) /*!< EBI_T::TCTL2: TACC Position */
#define EBI_TCTL2_TACC_Msk (0x1ful << EBI_TCTL2_TACC_Pos) /*!< EBI_T::TCTL2: TACC Mask */
#define EBI_TCTL2_TAHD_Pos (8) /*!< EBI_T::TCTL2: TAHD Position */
#define EBI_TCTL2_TAHD_Msk (0x7ul << EBI_TCTL2_TAHD_Pos) /*!< EBI_T::TCTL2: TAHD Mask */
#define EBI_TCTL2_W2X_Pos (12) /*!< EBI_T::TCTL2: W2X Position */
#define EBI_TCTL2_W2X_Msk (0xful << EBI_TCTL2_W2X_Pos) /*!< EBI_T::TCTL2: W2X Mask */
#define EBI_TCTL2_RAHDOFF_Pos (22) /*!< EBI_T::TCTL2: RAHDOFF Position */
#define EBI_TCTL2_RAHDOFF_Msk (0x1ul << EBI_TCTL2_RAHDOFF_Pos) /*!< EBI_T::TCTL2: RAHDOFF Mask */
#define EBI_TCTL2_WAHDOFF_Pos (23) /*!< EBI_T::TCTL2: WAHDOFF Position */
#define EBI_TCTL2_WAHDOFF_Msk (0x1ul << EBI_TCTL2_WAHDOFF_Pos) /*!< EBI_T::TCTL2: WAHDOFF Mask */
#define EBI_TCTL2_R2R_Pos (24) /*!< EBI_T::TCTL2: R2R Position */
#define EBI_TCTL2_R2R_Msk (0xful << EBI_TCTL2_R2R_Pos) /*!< EBI_T::TCTL2: R2R Mask */
/**@}*/ /* EBI_CONST */
/**@}*/ /* end of EBI register group */
/*---------------------- USB Device Controller -------------------------*/
/**
@addtogroup USBD USB Device Controller(USBD)
Memory Mapped Structure for USBD Controller
@{ */
typedef struct {
/**
* @var USBD_EP_T::BUFSEG
* Offset: 0x000 Endpoint n Buffer Segmentation Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[8:3] |BUFSEG |Endpoint Buffer Segmentation
* | | |It is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is
* | | |USBD_SRAM address + { BUFSEG, 3'b000}
* | | |Where the USBD_SRAM address = USBD_BA+0x100h.
* | | |Refer to the section 7.29.5.7 for the endpoint SRAM structure and its description.
* @var USBD_EP_T::MXPLD
* Offset: 0x004 Endpoint n Maximal Payload Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[8:0] |MXPLD |Maximal Payload
* | | |Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token)
* | | |It also used to indicate that the endpoint is ready to be transmitted in IN token or received in OUT token.
* | | |(1) When the register is written by CPU,
* | | |For IN token, the value of MXPLD is used to define the data length to be transmitted and indicate the data buffer is ready.
* | | |For OUT token, it means that the controller is ready to receive data from the host and the value of MXPLD is the maximal data length comes from host.
* | | |(2) When the register is read by CPU,
* | | |For IN token, the value of MXPLD is indicated by the data length be transmitted to host
* | | |For OUT token, the value of MXPLD is indicated the actual data length receiving from host.
* | | |Note: Once MXPLD is written, the data packets will be transmitted/received immediately after IN/OUT token arrived.
* @var USBD_EP_T::CFG
* Offset: 0x008 Endpoint n Configuration Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |EPNUM |Endpoint Number
* | | |These bits are used to define the endpoint number of the current endpoint
* |[4] |ISOCH |Isochronous Endpoint
* | | |This bit is used to set the endpoint as Isochronous endpoint, no handshake.
* | | |0 = No Isochronous endpoint.
* | | |1 = Isochronous endpoint.
* |[6:5] |STATE |Endpoint STATE
* | | |00 = Endpoint is Disabled.
* | | |01 = Out endpoint.
* | | |10 = IN endpoint.
* | | |11 = Undefined.
* |[7] |DSQSYNC |Data Sequence Synchronization
* | | |0 = DATA0 PID.
* | | |1 = DATA1 PID.
* | | |Note: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction
* | | |hardware will toggle automatically in IN token base on the bit.
* |[9] |CSTALL |Clear STALL Response
* | | |0 = Disable the device to clear the STALL handshake in setup stage.
* | | |1 = Clear the device to response STALL handshake in setup stage.
* @var USBD_EP_T::CFGP
* Offset: 0x00C Endpoint n Set Stall and Clear In/Out Ready Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CLRRDY |Clear Ready
* | | |When the USBD_MXPLDx register is set by user, it means that the endpoint is ready to transmit or receive data
* | | |If the user wants to disable this transaction before the transaction start, users can set this bit to 1 to disable it and it is auto clear to 0.
* | | |For IN token, write '1' to clear the IN token had ready to transmit the data to USB.
* | | |For OUT token, write '1' to clear the OUT token had ready to receive the data from USB.
* | | |This bit is write 1 only and is always 0 when it is read back.
* |[1] |SSTALL |Set STALL
* | | |0 = Disable the device to response STALL.
* | | |1 = Set the device to respond STALL automatically.
*/
__IO uint32_t BUFSEG; /*!< [0x0000] Endpoint n Buffer Segmentation Register */
__IO uint32_t MXPLD; /*!< [0x0004] Endpoint n Maximal Payload Register */
__IO uint32_t CFG; /*!< [0x0008] Endpoint n Configuration Register */
__IO uint32_t CFGP; /*!< [0x000c] Endpoint n Set Stall and Clear In/Out Ready Control Register */
} USBD_EP_T;
typedef struct {
/**
* @var USBD_T::INTEN
* Offset: 0x00 USB Device Interrupt Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |BUSIEN |Bus Event Interrupt Enable Bit
* | | |0 = BUS event interrupt Disabled.
* | | |1 = BUS event interrupt Enabled.
* |[1] |USBIEN |USB Event Interrupt Enable Bit
* | | |0 = USB event interrupt Disabled.
* | | |1 = USB event interrupt Enabled.
* |[2] |VBDETIEN |VBUS Detection Interrupt Enable Bit
* | | |0 = VBUS detection Interrupt Disabled.
* | | |1 = VBUS detection Interrupt Enabled.
* |[3] |NEVWKIEN |USB No-event-wake-up Interrupt Enable Bit
* | | |0 = No-event-wake-up Interrupt Disabled.
* | | |1 = No-event-wake-up Interrupt Enabled.
* |[4] |SOFIEN |Start of Frame Interrupt Enable Bit
* | | |0 = SOF Interrupt Disabled.
* | | |1 = SOF Interrupt Enabled.
* |[8] |WKEN |Wake-up Function Enable Bit
* | | |0 = USB wake-up function Disabled.
* | | |1 = USB wake-up function Enabled.
* |[15] |INNAKEN |Active NAK Function and Its Status in IN Token
* | | |0 = When device responds NAK after receiving IN token, IN NAK status will not be updated to USBD_EPSTS0 and USBD_EPSTS1register, so that the USB interrupt event will not be asserted.
* | | |1 = IN NAK status will be updated to USBD_EPSTS0 and USBD_EPSTS1 register and the USB interrupt event will be asserted, when the device responds NAK after receiving IN token.
* @var USBD_T::INTSTS
* Offset: 0x04 USB Device Interrupt Event Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |BUSIF |BUS Interrupt Status
* | | |The BUS event means that there is one of the suspense or the resume function in the bus.
* | | |0 = No BUS event occurred.
* | | |1 = Bus event occurred; check USBD_ATTR[3:0] to know which kind of bus event was occurred, cleared by write 1 to USBD_INTSTS[0].
* |[1] |USBIF |USB Event Interrupt Status
* | | |The USB event includes the SETUP Token, IN Token, OUT ACK, ISO IN, or ISO OUT events in the bus.
* | | |0 = No USB event occurred.
* | | |1 = USB event occurred, check EPSTS0~5[2:0] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[1] or EPSTS0~11 and SETUP (USBD_INTSTS[31]).
* |[2] |VBDETIF |VBUS Detection Interrupt Status
* | | |0 = There is not attached/detached event in the USB.
* | | |1 = There is attached/detached event in the USB bus and it is cleared by write 1 to USBD_INTSTS[2].
* |[3] |NEVWKIF |No-event-wake-up Interrupt Status
* | | |0 = NEVWK event does not occur.
* | | |1 = No-event-wake-up event occurred, cleared by write 1 to USBD_INTSTS[3].
* |[4] |SOFIF |Start of Frame Interrupt Status
* | | |0 = SOF event does not occur.
* | | |1 = SOF event occurred, cleared by write 1 to USBD_INTSTS[4].
* |[16] |EPEVT0 |Endpoint 0's USB Event Status
* | | |0 = No event occurred in endpoint 0.
* | | |1 = USB event occurred on Endpoint 0, check USBD_EPSTS0[3:0] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[16] or USBD_INTSTS[1].
* |[17] |EPEVT1 |Endpoint 1's USB Event Status
* | | |0 = No event occurred in endpoint 1.
* | | |1 = USB event occurred on Endpoint 1, check USBD_EPSTS0[7:4] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[17] or USBD_INTSTS[1].
* |[18] |EPEVT2 |Endpoint 2's USB Event Status
* | | |0 = No event occurred in endpoint 2.
* | | |1 = USB event occurred on Endpoint 2, check USBD_EPSTS0[11:8] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[18] or USBD_INTSTS[1].
* |[19] |EPEVT3 |Endpoint 3's USB Event Status
* | | |0 = No event occurred in endpoint 3.
* | | |1 = USB event occurred on Endpoint 3, check USBD_EPSTS0[15:12] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[19] or USBD_INTSTS[1].
* |[20] |EPEVT4 |Endpoint 4's USB Event Status
* | | |0 = No event occurred in endpoint 4.
* | | |1 = USB event occurred on Endpoint 4, check USBD_EPSTS0[19:16] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[20] or USBD_INTSTS[1].
* |[21] |EPEVT5 |Endpoint 5's USB Event Status
* | | |0 = No event occurred in endpoint 5.
* | | |1 = USB event occurred on Endpoint 5, check USBD_EPSTS0[23:20] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[21] or USBD_INTSTS[1].
* |[22] |EPEVT6 |Endpoint 6's USB Event Status
* | | |0 = No event occurred in endpoint 6.
* | | |1 = USB event occurred on Endpoint 6, check USBD_EPSTS0[27:24] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[22] or USBD_INTSTS[1].
* |[23] |EPEVT7 |Endpoint 7's USB Event Status
* | | |0 = No event occurred in endpoint 7.
* | | |1 = USB event occurred on Endpoint 7, check USBD_EPSTS0[31:28] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[23] or USBD_INTSTS[1].
* |[24] |EPEVT8 |Endpoint 8's USB Event Status
* | | |0 = No event occurred in endpoint 8.
* | | |1 = USB event occurred on Endpoint 8, check USBD_EPSTS1[3 :0] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[24] or USBD_INTSTS[1].
* |[25] |EPEVT9 |Endpoint 9's USB Event Status
* | | |0 = No event occurred in endpoint 9.
* | | |1 = USB event occurred on Endpoint 9, check USBD_EPSTS1[7 :4] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[25] or USBD_INTSTS[1].
* |[26] |EPEVT10 |Endpoint 10's USB Event Status
* | | |0 = No event occurred in endpoint 10.
* | | |1 = USB event occurred on Endpoint 10, check USBD_EPSTS1[11 :8] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[26] or USBD_INTSTS[1].
* |[27] |EPEVT11 |Endpoint 11's USB Event Status
* | | |0 = No event occurred in endpoint 11.
* | | |1 = USB event occurred on Endpoint 11, check USBD_EPSTS1[ 15:12] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[27] or USBD_INTSTS[1].
* |[31] |SETUP |Setup Event Status
* | | |0 = No Setup event.
* | | |1 = Setup event occurred, cleared by write 1 to USBD_INTSTS[31].
* @var USBD_T::FADDR
* Offset: 0x08 USB Device Function Address Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[6:0] |FADDR |USB Device Function Address
* @var USBD_T::EPSTS
* Offset: 0x0C USB Device Endpoint Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7] |OV |Overrun
* | | |It indicates that the received data is over the maximum payload number or not.
* | | |0 = No overrun.
* | | |1 = Out Data is more than the Max Payload in MXPLD register or the Setup Data is more than 8 Bytes.
* @var USBD_T::ATTR
* Offset: 0x10 USB Device Bus Status and Attribution Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |USBRST |USB Reset Status
* | | |0 = Bus no reset.
* | | |1 = Bus reset when SE0 (single-ended 0) more than 2.5us.
* | | |Note: This bit is read only.
* |[1] |SUSPEND |Suspend Status
* | | |0 = Bus no suspend.
* | | |1 = Bus idle more than 3ms, either cable is plugged off or host is sleeping.
* | | |Note: This bit is read only.
* |[2] |RESUME |Resume Status
* | | |0 = No bus resume.
* | | |1 = Resume from suspend.
* | | |Note: This bit is read only.
* |[3] |TOUT |Time-out Status
* | | |0 = No time-out.
* | | |1 = No Bus response more than 18 bits time.
* | | |Note: This bit is read only.
* |[4] |PHYEN |PHY Transceiver Function Enable Bit
* | | |0 = PHY transceiver function Disabled.
* | | |1 = PHY transceiver function Enabled.
* |[5] |RWAKEUP |Remote Wake-up
* | | |0 = Release the USB bus from K state.
* | | |1 = Force USB bus to K (USB_D+ low, USB_D-: high) state, used for remote wake-up.
* |[7] |USBEN |USB Controller Enable Bit
* | | |0 = USB Controller Disabled.
* | | |1 = USB Controller Enabled.
* |[8] |DPPUEN |Pull-up Resistor on USB_DP Enable Bit
* | | |0 = Pull-up resistor in USB_D+ bus Disabled.
* | | |1 = Pull-up resistor in USB_D+ bus Active.
* |[10] |BYTEM |CPU Access USB SRAM Size Mode Selection
* | | |0 = Word mode: The size of the transfer from CPU to USB SRAM can be Word only.
* | | |1 = Byte mode: The size of the transfer from CPU to USB SRAM can be Byte only.
* |[11] |LPMACK |LPM Token Acknowledge Enable Bit
* | | |The NYET/ACK will be returned only on a successful LPM transaction if no errors in both the EXT token and the LPM token and a valid bLinkState = 0001 (L1) is received, else ERROR and STALL will be returned automatically, respectively.
* | | |0= the valid LPM Token will be NYET.
* | | |1= the valid LPM Token will be ACK.
* |[12] |L1SUSPEND |LPM L1 Suspend
* | | |0 = Bus no L1 state suspend.
* | | |1 = This bit is set by the hardware when LPM command to enter the L1 state is successfully received and acknowledged.
* | | |Note: This bit is read only.
* |[13] |L1RESUME |LPM L1 Resume
* | | |0 = Bus no LPM L1 state resume.
* | | |1 = LPM L1 state Resume from LPM L1 state suspend.
* | | |Note: This bit is read only.
* @var USBD_T::VBUSDET
* Offset: 0x14 USB Device VBUS Detection Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |VBUSDET |Device VBUS Detection
* | | |0 = Controller is not attached to the USB host.
* | | |1 = Controller is attached to the USB host.
* @var USBD_T::STBUFSEG
* Offset: 0x18 SETUP Token Buffer Segmentation Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[8:3] |STBUFSEG |SETUP Token Buffer Segmentation
* | | |It is used to indicate the offset address for the SETUP token with the USB Device SRAM starting address The effective starting address is
* | | |USBD_SRAM address + {STBUFSEG, 3'b000}
* | | |Where the USBD_SRAM address = USBD_BA+0x100h.
* | | |Note: It is used for SETUP token only.
* @var USBD_T::EPSTS0
* Offset: 0x20 USB Device Endpoint Status Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[03:00] |EPSTS0 |Endpoint 0 Status
* | | |These bits are used to indicate the current status of this endpoint
* | | |0000 = In ACK.
* | | |0001 = In NAK.
* | | |0010 = Out Packet Data0 ACK.
* | | |0011 = Setup ACK.
* | | |0110 = Out Packet Data1 ACK.
* | | |0111 = Isochronous transfer end.
* |[07:04] |EPSTS1 |Endpoint 1 Status
* | | |These bits are used to indicate the current status of this endpoint
* | | |0000 = In ACK.
* | | |0001 = In NAK.
* | | |0010 = Out Packet Data0 ACK.
* | | |0011 = Setup ACK.
* | | |0110 = Out Packet Data1 ACK.
* | | |0111 = Isochronous transfer end.
* |[11:08] |EPSTS2 |Endpoint 2 Status
* | | |These bits are used to indicate the current status of this endpoint
* | | |0000 = In ACK.
* | | |0001 = In NAK.
* | | |0010 = Out Packet Data0 ACK.
* | | |0011 = Setup ACK.
* | | |0110 = Out Packet Data1 ACK.
* | | |0111 = Isochronous transfer end.
* |[15:12] |EPSTS3 |Endpoint 3 Status
* | | |These bits are used to indicate the current status of this endpoint
* | | |0000 = In ACK.
* | | |0001 = In NAK.
* | | |0010 = Out Packet Data0 ACK.
* | | |0011 = Setup ACK.
* | | |0110 = Out Packet Data1 ACK.
* | | |0111 = Isochronous transfer end.
* |[19:16] |EPSTS4 |Endpoint 4 Status
* | | |These bits are used to indicate the current status of this endpoint
* | | |0000 = In ACK.
* | | |0001 = In NAK.
* | | |0010 = Out Packet Data0 ACK.
* | | |0011 = Setup ACK.
* | | |0110 = Out Packet Data1 ACK.
* | | |0111 = Isochronous transfer end.
* |[23:20] |EPSTS5 |Endpoint 5 Status
* | | |These bits are used to indicate the current status of this endpoint
* | | |0000 = In ACK.
* | | |0001 = In NAK.
* | | |0010 = Out Packet Data0 ACK.
* | | |0011 = Setup ACK.
* | | |0110 = Out Packet Data1 ACK.
* | | |0111 = Isochronous transfer end.
* |[27:24] |EPSTS6 |Endpoint 6 Status
* | | |These bits are used to indicate the current status of this endpoint
* | | |0000 = In ACK.
* | | |0001 = In NAK.
* | | |0010 = Out Packet Data0 ACK.
* | | |0011 = Setup ACK.
* | | |0110 = Out Packet Data1 ACK.
* | | |0111 = Isochronous transfer end.
* |[31:28] |EPSTS7 |Endpoint 7 Status
* | | |These bits are used to indicate the current status of this endpoint
* | | |0000 = In ACK.
* | | |0001 = In NAK.
* | | |0010 = Out Packet Data0 ACK.
* | | |0011 = Setup ACK.
* | | |0110 = Out Packet Data1 ACK.
* | | |0111 = Isochronous transfer end.
* @var USBD_T::EPSTS1
* Offset: 0x24 USB Device Endpoint Status Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |EPSTS8 |Endpoint 8 Status
* | | |These bits are used to indicate the current status of this endpoint
* | | |0000 = In ACK.
* | | |0001 = In NAK.
* | | |0010 = Out Packet Data0 ACK.
* | | |0011 = Setup ACK.
* | | |0110 = Out Packet Data1 ACK.
* | | |0111 = Isochronous transfer end.
* |[7:4] |EPSTS9 |Endpoint 9 Status
* | | |These bits are used to indicate the current status of this endpoint
* | | |0000 = In ACK.
* | | |0001 = In NAK.
* | | |0010 = Out Packet Data0 ACK.
* | | |0011 = Setup ACK.
* | | |0110 = Out Packet Data1 ACK.
* | | |0111 = Isochronous transfer end.
* |[11:8] |EPSTS10 |Endpoint 10 Status
* | | |These bits are used to indicate the current status of this endpoint
* | | |0000 = In ACK.
* | | |0001 = In NAK.
* | | |0010 = Out Packet Data0 ACK.
* | | |0011 = Setup ACK.
* | | |0110 = Out Packet Data1 ACK.
* | | |0111 = Isochronous transfer end.
* |[15:12] |EPSTS11 |Endpoint 11 Status
* | | |These bits are used to indicate the current status of this endpoint
* | | |0000 = In ACK.
* | | |0001 = In NAK.
* | | |0010 = Out Packet Data0 ACK.
* | | |0011 = Setup ACK.
* | | |0110 = Out Packet Data1 ACK.
* | | |0111 = Isochronous transfer end.
* @var USBD_T::LPMATTR
* Offset: 0x88 USB LPM Attribution Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |LPMLINKSTS|LPM Link State
* | | |These bits contain the bLinkState received with last ACK LPM Token
* |[7:4] |LPMBESL |LPM Best Effort Service Latency
* | | |These bits contain the BESL value received with last ACK LPM Token
* |[8] |LPMRWAKUP |LPM Remote Wakeup
* | | |This bit contains the bRemoteWake value received with last ACK LPM Token
* @var USBD_T::FN
* Offset: 0x8C USB Frame number Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[10:0] |FN |Frame Number
* | | |These bits contain the 11-bits frame number in the last received SOF packet.
* @var USBD_T::SE0
* Offset: 0x90 USB Device Drive SE0 Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SE0 |Drive Single Ended Zero in USB Bus
* | | |The Single Ended Zero (SE0) is when both lines (USB_D+ and USB_D-) are being pulled low.
* | | |0 = Normal operation.
* | | |1 = Force USB PHY transceiver to drive SE0.
*/
__IO uint32_t INTEN; /*!< [0x0000] USB Device Interrupt Enable Register */
__IO uint32_t INTSTS; /*!< [0x0004] USB Device Interrupt Event Status Register */
__IO uint32_t FADDR; /*!< [0x0008] USB Device Function Address Register */
__I uint32_t EPSTS; /*!< [0x000c] USB Device Endpoint Status Register */
__IO uint32_t ATTR; /*!< [0x0010] USB Device Bus Status and Attribution Register */
__I uint32_t VBUSDET; /*!< [0x0014] USB Device VBUS Detection Register */
__IO uint32_t STBUFSEG; /*!< [0x0018] SETUP Token Buffer Segmentation Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE0[1];
/// @endcond //HIDDEN_SYMBOLS
__I uint32_t EPSTS0; /*!< [0x0020] USB Device Endpoint Status Register 0 */
__I uint32_t EPSTS1; /*!< [0x0024] USB Device Endpoint Status Register 1 */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE1[24];
/// @endcond //HIDDEN_SYMBOLS
__I uint32_t LPMATTR; /*!< [0x0088] USB LPM Attribution Register */
__I uint32_t FN; /*!< [0x008c] USB Frame number Register */
__IO uint32_t SE0; /*!< [0x0090] USB Device Drive SE0 Control Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE2[283];
/// @endcond //HIDDEN_SYMBOLS
USBD_EP_T EP[12]; /*!< [0x500~0x5bc] USB End Point 0 ~ 11 Configuration Register */
} USBD_T;
/**
@addtogroup USBD_CONST USBD Bit Field Definition
Constant Definitions for USBD Controller
@{ */
#define USBD_INTEN_BUSIEN_Pos (0) /*!< USBD_T::INTEN: BUSIEN Position */
#define USBD_INTEN_BUSIEN_Msk (0x1ul << USBD_INTEN_BUSIEN_Pos) /*!< USBD_T::INTEN: BUSIEN Mask */
#define USBD_INTEN_USBIEN_Pos (1) /*!< USBD_T::INTEN: USBIEN Position */
#define USBD_INTEN_USBIEN_Msk (0x1ul << USBD_INTEN_USBIEN_Pos) /*!< USBD_T::INTEN: USBIEN Mask */
#define USBD_INTEN_VBDETIEN_Pos (2) /*!< USBD_T::INTEN: VBDETIEN Position */
#define USBD_INTEN_VBDETIEN_Msk (0x1ul << USBD_INTEN_VBDETIEN_Pos) /*!< USBD_T::INTEN: VBDETIEN Mask */
#define USBD_INTEN_NEVWKIEN_Pos (3) /*!< USBD_T::INTEN: NEVWKIEN Position */
#define USBD_INTEN_NEVWKIEN_Msk (0x1ul << USBD_INTEN_NEVWKIEN_Pos) /*!< USBD_T::INTEN: NEVWKIEN Mask */
#define USBD_INTEN_SOFIEN_Pos (4) /*!< USBD_T::INTEN: SOFIEN Position */
#define USBD_INTEN_SOFIEN_Msk (0x1ul << USBD_INTEN_SOFIEN_Pos) /*!< USBD_T::INTEN: SOFIEN Mask */
#define USBD_INTEN_WKEN_Pos (8) /*!< USBD_T::INTEN: WKEN Position */
#define USBD_INTEN_WKEN_Msk (0x1ul << USBD_INTEN_WKEN_Pos) /*!< USBD_T::INTEN: WKEN Mask */
#define USBD_INTEN_INNAKEN_Pos (15) /*!< USBD_T::INTEN: INNAKEN Position */
#define USBD_INTEN_INNAKEN_Msk (0x1ul << USBD_INTEN_INNAKEN_Pos) /*!< USBD_T::INTEN: INNAKEN Mask */
#define USBD_INTSTS_BUSIF_Pos (0) /*!< USBD_T::INTSTS: BUSIF Position */
#define USBD_INTSTS_BUSIF_Msk (0x1ul << USBD_INTSTS_BUSIF_Pos) /*!< USBD_T::INTSTS: BUSIF Mask */
#define USBD_INTSTS_USBIF_Pos (1) /*!< USBD_T::INTSTS: USBIF Position */
#define USBD_INTSTS_USBIF_Msk (0x1ul << USBD_INTSTS_USBIF_Pos) /*!< USBD_T::INTSTS: USBIF Mask */
#define USBD_INTSTS_VBDETIF_Pos (2) /*!< USBD_T::INTSTS: VBDETIF Position */
#define USBD_INTSTS_VBDETIF_Msk (0x1ul << USBD_INTSTS_VBDETIF_Pos) /*!< USBD_T::INTSTS: VBDETIF Mask */
#define USBD_INTSTS_NEVWKIF_Pos (3) /*!< USBD_T::INTSTS: NEVWKIF Position */
#define USBD_INTSTS_NEVWKIF_Msk (0x1ul << USBD_INTSTS_NEVWKIF_Pos) /*!< USBD_T::INTSTS: NEVWKIF Mask */
#define USBD_INTSTS_SOFIF_Pos (4) /*!< USBD_T::INTSTS: SOFIF Position */
#define USBD_INTSTS_SOFIF_Msk (0x1ul << USBD_INTSTS_SOFIF_Pos) /*!< USBD_T::INTSTS: SOFIF Mask */
#define USBD_INTSTS_EPEVT0_Pos (16) /*!< USBD_T::INTSTS: EPEVT0 Position */
#define USBD_INTSTS_EPEVT0_Msk (0x1ul << USBD_INTSTS_EPEVT0_Pos) /*!< USBD_T::INTSTS: EPEVT0 Mask */
#define USBD_INTSTS_EPEVT1_Pos (17) /*!< USBD_T::INTSTS: EPEVT1 Position */
#define USBD_INTSTS_EPEVT1_Msk (0x1ul << USBD_INTSTS_EPEVT1_Pos) /*!< USBD_T::INTSTS: EPEVT1 Mask */
#define USBD_INTSTS_EPEVT2_Pos (18) /*!< USBD_T::INTSTS: EPEVT2 Position */
#define USBD_INTSTS_EPEVT2_Msk (0x1ul << USBD_INTSTS_EPEVT2_Pos) /*!< USBD_T::INTSTS: EPEVT2 Mask */
#define USBD_INTSTS_EPEVT3_Pos (19) /*!< USBD_T::INTSTS: EPEVT3 Position */
#define USBD_INTSTS_EPEVT3_Msk (0x1ul << USBD_INTSTS_EPEVT3_Pos) /*!< USBD_T::INTSTS: EPEVT3 Mask */
#define USBD_INTSTS_EPEVT4_Pos (20) /*!< USBD_T::INTSTS: EPEVT4 Position */
#define USBD_INTSTS_EPEVT4_Msk (0x1ul << USBD_INTSTS_EPEVT4_Pos) /*!< USBD_T::INTSTS: EPEVT4 Mask */
#define USBD_INTSTS_EPEVT5_Pos (21) /*!< USBD_T::INTSTS: EPEVT5 Position */
#define USBD_INTSTS_EPEVT5_Msk (0x1ul << USBD_INTSTS_EPEVT5_Pos) /*!< USBD_T::INTSTS: EPEVT5 Mask */
#define USBD_INTSTS_EPEVT6_Pos (22) /*!< USBD_T::INTSTS: EPEVT6 Position */
#define USBD_INTSTS_EPEVT6_Msk (0x1ul << USBD_INTSTS_EPEVT6_Pos) /*!< USBD_T::INTSTS: EPEVT6 Mask */
#define USBD_INTSTS_EPEVT7_Pos (23) /*!< USBD_T::INTSTS: EPEVT7 Position */
#define USBD_INTSTS_EPEVT7_Msk (0x1ul << USBD_INTSTS_EPEVT7_Pos) /*!< USBD_T::INTSTS: EPEVT7 Mask */
#define USBD_INTSTS_EPEVT8_Pos (24) /*!< USBD_T::INTSTS: EPEVT8 Position */
#define USBD_INTSTS_EPEVT8_Msk (0x1ul << USBD_INTSTS_EPEVT8_Pos) /*!< USBD_T::INTSTS: EPEVT8 Mask */
#define USBD_INTSTS_EPEVT9_Pos (25) /*!< USBD_T::INTSTS: EPEVT9 Position */
#define USBD_INTSTS_EPEVT9_Msk (0x1ul << USBD_INTSTS_EPEVT9_Pos) /*!< USBD_T::INTSTS: EPEVT9 Mask */
#define USBD_INTSTS_EPEVT10_Pos (26) /*!< USBD_T::INTSTS: EPEVT10 Position */
#define USBD_INTSTS_EPEVT10_Msk (0x1ul << USBD_INTSTS_EPEVT10_Pos) /*!< USBD_T::INTSTS: EPEVT10 Mask */
#define USBD_INTSTS_EPEVT11_Pos (27) /*!< USBD_T::INTSTS: EPEVT11 Position */
#define USBD_INTSTS_EPEVT11_Msk (0x1ul << USBD_INTSTS_EPEVT11_Pos) /*!< USBD_T::INTSTS: EPEVT11 Mask */
#define USBD_INTSTS_SETUP_Pos (31) /*!< USBD_T::INTSTS: SETUP Position */
#define USBD_INTSTS_SETUP_Msk (0x1ul << USBD_INTSTS_SETUP_Pos) /*!< USBD_T::INTSTS: SETUP Mask */
#define USBD_FADDR_FADDR_Pos (0) /*!< USBD_T::FADDR: FADDR Position */
#define USBD_FADDR_FADDR_Msk (0x7ful << USBD_FADDR_FADDR_Pos) /*!< USBD_T::FADDR: FADDR Mask */
#define USBD_EPSTS_OV_Pos (7) /*!< USBD_T::EPSTS: OV Position */
#define USBD_EPSTS_OV_Msk (0x1ul << USBD_EPSTS_OV_Pos) /*!< USBD_T::EPSTS: OV Mask */
#define USBD_ATTR_USBRST_Pos (0) /*!< USBD_T::ATTR: USBRST Position */
#define USBD_ATTR_USBRST_Msk (0x1ul << USBD_ATTR_USBRST_Pos) /*!< USBD_T::ATTR: USBRST Mask */
#define USBD_ATTR_SUSPEND_Pos (1) /*!< USBD_T::ATTR: SUSPEND Position */
#define USBD_ATTR_SUSPEND_Msk (0x1ul << USBD_ATTR_SUSPEND_Pos) /*!< USBD_T::ATTR: SUSPEND Mask */
#define USBD_ATTR_RESUME_Pos (2) /*!< USBD_T::ATTR: RESUME Position */
#define USBD_ATTR_RESUME_Msk (0x1ul << USBD_ATTR_RESUME_Pos) /*!< USBD_T::ATTR: RESUME Mask */
#define USBD_ATTR_TOUT_Pos (3) /*!< USBD_T::ATTR: TOUT Position */
#define USBD_ATTR_TOUT_Msk (0x1ul << USBD_ATTR_TOUT_Pos) /*!< USBD_T::ATTR: TOUT Mask */
#define USBD_ATTR_PHYEN_Pos (4) /*!< USBD_T::ATTR: PHYEN Position */
#define USBD_ATTR_PHYEN_Msk (0x1ul << USBD_ATTR_PHYEN_Pos) /*!< USBD_T::ATTR: PHYEN Mask */
#define USBD_ATTR_RWAKEUP_Pos (5) /*!< USBD_T::ATTR: RWAKEUP Position */
#define USBD_ATTR_RWAKEUP_Msk (0x1ul << USBD_ATTR_RWAKEUP_Pos) /*!< USBD_T::ATTR: RWAKEUP Mask */
#define USBD_ATTR_USBEN_Pos (7) /*!< USBD_T::ATTR: USBEN Position */
#define USBD_ATTR_USBEN_Msk (0x1ul << USBD_ATTR_USBEN_Pos) /*!< USBD_T::ATTR: USBEN Mask */
#define USBD_ATTR_DPPUEN_Pos (8) /*!< USBD_T::ATTR: DPPUEN Position */
#define USBD_ATTR_DPPUEN_Msk (0x1ul << USBD_ATTR_DPPUEN_Pos) /*!< USBD_T::ATTR: DPPUEN Mask */
#define USBD_ATTR_BYTEM_Pos (10) /*!< USBD_T::ATTR: BYTEM Position */
#define USBD_ATTR_BYTEM_Msk (0x1ul << USBD_ATTR_BYTEM_Pos) /*!< USBD_T::ATTR: BYTEM Mask */
#define USBD_ATTR_LPMACK_Pos (11) /*!< USBD_T::ATTR: LPMACK Position */
#define USBD_ATTR_LPMACK_Msk (0x1ul << USBD_ATTR_LPMACK_Pos) /*!< USBD_T::ATTR: LPMACK Mask */
#define USBD_ATTR_L1SUSPEND_Pos (12) /*!< USBD_T::ATTR: L1SUSPEND Position */
#define USBD_ATTR_L1SUSPEND_Msk (0x1ul << USBD_ATTR_L1SUSPEND_Pos) /*!< USBD_T::ATTR: L1SUSPEND Mask */
#define USBD_ATTR_L1RESUME_Pos (13) /*!< USBD_T::ATTR: L1RESUME Position */
#define USBD_ATTR_L1RESUME_Msk (0x1ul << USBD_ATTR_L1RESUME_Pos) /*!< USBD_T::ATTR: L1RESUME Mask */
#define USBD_VBUSDET_VBUSDET_Pos (0) /*!< USBD_T::VBUSDET: VBUSDET Position */
#define USBD_VBUSDET_VBUSDET_Msk (0x1ul << USBD_VBUSDET_VBUSDET_Pos) /*!< USBD_T::VBUSDET: VBUSDET Mask */
#define USBD_STBUFSEG_STBUFSEG_Pos (3) /*!< USBD_T::STBUFSEG: STBUFSEG Position */
#define USBD_STBUFSEG_STBUFSEG_Msk (0x3ful << USBD_STBUFSEG_STBUFSEG_Pos) /*!< USBD_T::STBUFSEG: STBUFSEG Mask */
#define USBD_EPSTS0_EPSTS5_Pos (20) /*!< USBD_T::EPSTS0: EPSTS5 Position */
#define USBD_EPSTS0_EPSTS5_Msk (0xful << USBD_EPSTS0_EPSTS5_Pos) /*!< USBD_T::EPSTS0: EPSTS5 Mask */
#define USBD_EPSTS0_EPSTS6_Pos (24) /*!< USBD_T::EPSTS0: EPSTS6 Position */
#define USBD_EPSTS0_EPSTS6_Msk (0xful << USBD_EPSTS0_EPSTS6_Pos) /*!< USBD_T::EPSTS0: EPSTS6 Mask */
#define USBD_EPSTS0_EPSTS7_Pos (28) /*!< USBD_T::EPSTS0: EPSTS7 Position */
#define USBD_EPSTS0_EPSTS7_Msk (0xful << USBD_EPSTS0_EPSTS7_Pos) /*!< USBD_T::EPSTS0: EPSTS7 Mask */
#define USBD_EPSTS1_EPSTS8_Pos (0) /*!< USBD_T::EPSTS1: EPSTS8 Position */
#define USBD_EPSTS1_EPSTS8_Msk (0xful << USBD_EPSTS1_EPSTS8_Pos) /*!< USBD_T::EPSTS1: EPSTS8 Mask */
#define USBD_EPSTS1_EPSTS9_Pos (4) /*!< USBD_T::EPSTS1: EPSTS9 Position */
#define USBD_EPSTS1_EPSTS9_Msk (0xful << USBD_EPSTS1_EPSTS9_Pos) /*!< USBD_T::EPSTS1: EPSTS9 Mask */
#define USBD_EPSTS1_EPSTS10_Pos (8) /*!< USBD_T::EPSTS1: EPSTS10 Position */
#define USBD_EPSTS1_EPSTS10_Msk (0xful << USBD_EPSTS1_EPSTS10_Pos) /*!< USBD_T::EPSTS1: EPSTS10 Mask */
#define USBD_EPSTS1_EPSTS11_Pos (12) /*!< USBD_T::EPSTS1: EPSTS11 Position */
#define USBD_EPSTS1_EPSTS11_Msk (0xful << USBD_EPSTS1_EPSTS11_Pos) /*!< USBD_T::EPSTS1: EPSTS11 Mask */
#define USBD_LPMATTR_LPMLINKSTS_Pos (0) /*!< USBD_T::LPMATTR: LPMLINKSTS Position */
#define USBD_LPMATTR_LPMLINKSTS_Msk (0xful << USBD_LPMATTR_LPMLINKSTS_Pos) /*!< USBD_T::LPMATTR: LPMLINKSTS Mask */
#define USBD_LPMATTR_LPMBESL_Pos (4) /*!< USBD_T::LPMATTR: LPMBESL Position */
#define USBD_LPMATTR_LPMBESL_Msk (0xful << USBD_LPMATTR_LPMBESL_Pos) /*!< USBD_T::LPMATTR: LPMBESL Mask */
#define USBD_LPMATTR_LPMRWAKUP_Pos (8) /*!< USBD_T::LPMATTR: LPMRWAKUP Position */
#define USBD_LPMATTR_LPMRWAKUP_Msk (0x1ul << USBD_LPMATTR_LPMRWAKUP_Pos) /*!< USBD_T::LPMATTR: LPMRWAKUP Mask */
#define USBD_FN_FN_Pos (0) /*!< USBD_T::FN: FN Position */
#define USBD_FN_FN_Msk (0x7fful << USBD_FN_FN_Pos) /*!< USBD_T::FN: FN Mask */
#define USBD_SE0_SE0_Pos (0) /*!< USBD_T::SE0: SE0 Position */
#define USBD_SE0_SE0_Msk (0x1ul << USBD_SE0_SE0_Pos) /*!< USBD_T::SE0: SE0 Mask */
#define USBD_BUFSEG_BUFSEG_Pos (3) /*!< USBD_EP_T::BUFSEG: BUFSEG Position */
#define USBD_BUFSEG_BUFSEG_Msk (0x3ful << USBD_BUFSEG_BUFSEG_Pos) /*!< USBD_EP_T::BUFSEG: BUFSEG Mask */
#define USBD_MXPLD_MXPLD_Pos (0) /*!< USBD_EP_T::MXPLD: MXPLD Position */
#define USBD_MXPLD_MXPLD_Msk (0x1fful << USBD_MXPLD_MXPLD_Pos) /*!< USBD_EP_T::MXPLD: MXPLD Mask */
#define USBD_CFG_EPNUM_Pos (0) /*!< USBD_EP_T::CFG: EPNUM Position */
#define USBD_CFG_EPNUM_Msk (0xful << USBD_CFG_EPNUM_Pos) /*!< USBD_EP_T::CFG: EPNUM Mask */
#define USBD_CFG_ISOCH_Pos (4) /*!< USBD_EP_T::CFG: ISOCH Position */
#define USBD_CFG_ISOCH_Msk (0x1ul << USBD_CFG_ISOCH_Pos) /*!< USBD_EP_T::CFG: ISOCH Mask */
#define USBD_CFG_STATE_Pos (5) /*!< USBD_EP_T::CFG: STATE Position */
#define USBD_CFG_STATE_Msk (0x3ul << USBD_CFG_STATE_Pos) /*!< USBD_EP_T::CFG: STATE Mask */
#define USBD_CFG_DSQSYNC_Pos (7) /*!< USBD_EP_T::CFG: DSQSYNC Position */
#define USBD_CFG_DSQSYNC_Msk (0x1ul << USBD_CFG_DSQSYNC_Pos) /*!< USBD_EP_T::CFG: DSQSYNC Mask */
#define USBD_CFG_CSTALL_Pos (9) /*!< USBD_EP_T::CFG: CSTALL Position */
#define USBD_CFG_CSTALL_Msk (0x1ul << USBD_CFG_CSTALL_Pos) /*!< USBD_EP_T::CFG: CSTALL Mask */
#define USBD_CFGP_CLRRDY_Pos (0) /*!< USBD_EP_T::CFGP: CLRRDY Position */
#define USBD_CFGP_CLRRDY_Msk (0x1ul << USBD_CFGP_CLRRDY_Pos) /*!< USBD_EP_T::CFGP: CLRRDY Mask */
#define USBD_CFGP_SSTALL_Pos (1) /*!< USBD_EP_T::CFGP: SSTALL Position */
#define USBD_CFGP_SSTALL_Msk (0x1ul << USBD_CFGP_SSTALL_Pos) /*!< USBD_EP_T::CFGP: SSTALL Mask */
/**@}*/ /* USBD_CONST */
/**@}*/ /* end of USBD register group */
/*---------------------- High Speed USB 2.0 Device Controller -------------------------*/
/**
@addtogroup HSUSBD USB 2.0 Device Controller(HSUSBD)
Memory Mapped Structure for HSUSBD Controller
@{ */
typedef struct {
/**
* @var HSUSBD_EP_T::EPDAT
* Offset: 0x00 Endpoint n Data Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |EPDAT |Endpoint A~L Data Register
* | | |Endpoint A~L data buffer for the buffer transaction (read or write).
* | | |Note: Only word access is supported.
* @var HSUSBD_EP_T::EPDAT_BYTE
* Offset: 0x00 Endpoint n Data Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |EPDAT |Endpoint A~L Data Register
* | | |Endpoint A~L data buffer for the buffer transaction (read or write).
* | | |Note: Only byte access is supported.
* @var HSUSBD_EP_T::EPINTSTS
* Offset: 0x04 Endpoint n Interrupt Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |BUFFULLIF |Buffer Full
* | | |For an IN endpoint, the currently selected buffer is full, or no buffer is available to the local side for writing (no space to write)
* | | |For an OUT endpoint, there is a buffer available on the local side, and there are FIFO full of bytes available to be read (entire packet is available for reading).
* | | |0 = The endpoint packet buffer is not full.
* | | |1 = The endpoint packet buffer is full.
* | | |Note: This bit is read-only.
* |[1] |BUFEMPTYIF|Buffer Empty
* | | |For an IN endpoint, a buffer is available to the local side for writing up to FIFO full of bytes.
* | | |0 = The endpoint buffer is not empty.
* | | |1 = The endpoint buffer is empty.
* | | |For an OUT endpoint:
* | | |0 = The currently selected buffer has not a count of 0.
* | | |1 = The currently selected buffer has a count of 0, or no buffer is available on the local side (nothing to read).
* | | |Note: This bit is read-only.
* |[2] |SHORTTXIF |Short Packet Transferred Interrupt
* | | |0 = The length of the last packet was not less than the Maximum Packet Size (EPMPS).
* | | |1 = The length of the last packet was less than the Maximum Packet Size (EPMPS).
* | | |Note: Write 1 to clear this bit to 0.
* |[3] |TXPKIF |Data Packet Transmitted Interrupt
* | | |0 = Not a data packet is transmitted from the endpoint to the host.
* | | |1 = A data packet is transmitted from the endpoint to the host.
* | | |Note: Write 1 to clear this bit to 0.
* |[4] |RXPKIF |Data Packet Received Interrupt
* | | |0 = No data packet is received from the host by the endpoint.
* | | |1 = A data packet is received from the host by the endpoint.
* | | |Note: Write 1 to clear this bit to 0.
* |[5] |OUTTKIF |Data OUT Token Interrupt
* | | |0 = A Data OUT token has not been received from the host.
* | | |1 = A Data OUT token has been received from the host
* | | |This bit also set by PING token (in high-speed only).
* | | |Note: Write 1 to clear this bit to 0.
* |[6] |INTKIF |Data IN Token Interrupt
* | | |0 = Not Data IN token has been received from the host.
* | | |1 = A Data IN token has been received from the host.
* | | |Note: Write 1 to clear this bit to 0.
* |[7] |PINGIF |PING Token Interrupt
* | | |0 = A Data PING token has not been received from the host.
* | | |1 = A Data PING token has been received from the host.
* | | |Note: Write 1 to clear this bit to 0.
* |[8] |NAKIF |USB NAK Sent
* | | |0 = The last USB IN packet could be provided, and was acknowledged with an ACK.
* | | |1 = The last USB IN packet could not be provided, and was acknowledged with a NAK.
* | | |Note: Write 1 to clear this bit to 0.
* |[9] |STALLIF |USB STALL Sent
* | | |0 = The last USB packet could be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL.
* | | |1 = The last USB packet could not be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL.
* | | |Note: Write 1 to clear this bit to 0.
* |[10] |NYETIF |NYET Sent
* | | |0 = The space available in the RAM is sufficient to accommodate the next on coming data packet.
* | | |1 = The space available in the RAM is not sufficient to accommodate the next on coming data packet.
* | | |Note: Write 1 to clear this bit to 0.
* |[11] |ERRIF |ERR Sent
* | | |0 = No any error in the transaction.
* | | |1 = There occurs any error in the transaction.
* | | |Note: Write 1 to clear this bit to 0.
* |[12] |SHORTRXIF |Bulk Out Short Packet Received
* | | |0 = No bulk out short packet is received.
* | | |1 = Received bulk out short packet (including zero length packet).
* | | |Note: Write 1 to clear this bit to 0.
* @var HSUSBD_EP_T::EPINTEN
* Offset: 0x08 Endpoint n Interrupt Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |BUFFULLIEN|Buffer Full Interrupt
* | | |When set, this bit enables a local interrupt to be set when a buffer full condition is detected on the bus.
* | | |0 = Buffer full interrupt Disabled.
* | | |1 = Buffer full interrupt Enabled.
* |[1] |BUFEMPTYIEN|Buffer Empty Interrupt
* | | |When set, this bit enables a local interrupt to be set when a buffer empty condition is detected on the bus.
* | | |0 = Buffer empty interrupt Disabled.
* | | |1 = Buffer empty interrupt Enabled.
* |[2] |SHORTTXIEN|Short Packet Transferred Interrupt Enable Bit
* | | |When set, this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host.
* | | |0 = Short data packet interrupt Disabled.
* | | |1 = Short data packet interrupt Enabled.
* |[3] |TXPKIEN |Data Packet Transmitted Interrupt Enable Bit
* | | |When set, this bit enables a local interrupt to be set when a data packet has been received from the host.
* | | |0 = Data packet has been received from the host interrupt Disabled.
* | | |1 = Data packet has been received from the host interrupt Enabled.
* |[4] |RXPKIEN |Data Packet Received Interrupt Enable Bit
* | | |When set, this bit enables a local interrupt to be set when a data packet has been transmitted to the host.
* | | |0 = Data packet has been transmitted to the host interrupt Disabled.
* | | |1 = Data packet has been transmitted to the host interrupt Enabled.
* |[5] |OUTTKIEN |Data OUT Token Interrupt Enable Bit
* | | |When set, this bit enables a local interrupt to be set when a Data OUT token has been received from the host.
* | | |0 = Data OUT token interrupt Disabled.
* | | |1 = Data OUT token interrupt Enabled.
* |[6] |INTKIEN |Data IN Token Interrupt Enable Bit
* | | |When set, this bit enables a local interrupt to be set when a Data IN token has been received from the host.
* | | |0 = Data IN token interrupt Disabled.
* | | |1 = Data IN token interrupt Enabled.
* |[7] |PINGIEN |PING Token Interrupt Enable Bit
* | | |When set, this bit enables a local interrupt to be set when a PING token has been received from the host.
* | | |0 = PING token interrupt Disabled.
* | | |1 = PING token interrupt Enabled.
* |[8] |NAKIEN |USB NAK Sent Interrupt Enable Bit
* | | |When set, this bit enables a local interrupt to be set when a NAK token is sent to the host.
* | | |0 = NAK token interrupt Disabled.
* | | |1 = NAK token interrupt Enabled.
* |[9] |STALLIEN |USB STALL Sent Interrupt Enable Bit
* | | |When set, this bit enables a local interrupt to be set when a stall token is sent to the host.
* | | |0 = STALL token interrupt Disabled.
* | | |1 = STALL token interrupt Enabled.
* |[10] |NYETIEN |NYET Interrupt Enable Bit
* | | |When set, this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint.
* | | |0 = NYET condition interrupt Disabled.
* | | |1 = NYET condition interrupt Enabled.
* |[11] |ERRIEN |ERR Interrupt Enable Bit
* | | |When set, this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint.
* | | |0 = Error event interrupt Disabled.
* | | |1 = Error event interrupt Enabled.
* |[12] |SHORTRXIEN|Bulk Out Short Packet Interrupt Enable Bit
* | | |When set, this bit enables a local interrupt to be set whenever bulk out short packet occurs on the bus for this endpoint.
* | | |0 = Bulk out interrupt Disabled.
* | | |1 = Bulk out interrupt Enabled.
* @var HSUSBD_EP_T::EPDATCNT
* Offset: 0x0C Endpoint n Data Available Count Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |DATCNT |Data Count
* | | |For an IN endpoint (EPDIR(USBD_EPxCFG[3] is high.), this register returns the number of valid bytes in the IN endpoint packet buffer.
* | | |For an OUT endpoint (EPDIR(USBD_EPxCFG[3] is low.), this register returns the number of received valid bytes in the Host OUT transfer.
* |[30:16] |DMALOOP |DMA Loop
* | | |This register is the remaining DMA loop to complete. Each loop means 32-byte transfer.
* @var HSUSBD_EP_T::EPRSPCTL
* Offset: 0x10 Endpoint n Response Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |FLUSH |Buffer Flush
* | | |Writing 1 to this bit causes the packet buffer to be flushed and the corresponding EP_AVAIL register to be cleared
* | | |This bit is self-clearing
* | | |This bit should always be written after an configuration event.
* | | |0 = The packet buffer is not flushed.
* | | |1 = The packet buffer is flushed by user.
* |[2:1] |MODE |Mode Control
* | | |The two bits decide the operation mode of the in-endpoint.
* | | |00: Auto-Validate Mode
* | | |01: Manual-Validate Mode
* | | |10: Fly Mode
* | | |11: Reserved
* | | |These bits are not valid for an out-endpoint
* | | |The auto validate mode will be activated when the reserved mode is selected
* |[3] |TOGGLE |Endpoint Toggle
* | | |This bit is used to clear the endpoint data toggle bit
* | | |Reading this bit returns the current state of the endpoint data toggle bit.
* | | |The local CPU may use this bit to initialize the end-point's toggle in case of reception of a Set Interface request or a Clear Feature (ep_halt) request from the host
* | | |Only when toggle bit is "1", this bit can be written into the inversed write data bit[3].
* | | |0 = Not clear the endpoint data toggle bit.
* | | |1 = Clear the endpoint data toggle bit.
* |[4] |HALT |Endpoint Halt
* | | |This bit is used to send a STALL handshake as response to the token from the host
* | | |When an Endpoint Set Feature (ep_halt) is detected by the local CPU, it must write a '1' to this bit.
* | | |0 = Not send a STALL handshake as response to the token from the host.
* | | |1 = Send a STALL handshake as response to the token from the host.
* |[5] |ZEROLEN |Zero Length
* | | |This bit is used to send a zero-length packet response to an IN-token
* | | |When this bit is set, a zero packet is sent to the host on reception of an IN-token
* | | |This bit gets cleared once the zero length data packet is sent.
* | | |0 = A zero packet is not sent to the host on reception of an IN-token.
* | | |1 = A zero packet is sent to the host on reception of an IN-token.
* |[6] |SHORTTXEN |Short Packet Transfer Enable
* | | |This bit is applicable only in case of Auto-Validate Method
* | | |This bit is set to validate any remaining data in the buffer which is not equal to the MPS of the endpoint, and happens to be the last transfer
* | | |This bit gets cleared once the data packet is sent.
* | | |0 = Not validate any remaining data in the buffer which is not equal to the MPS of the endpoint.
* | | |1 = Validate any remaining data in the buffer which is not equal to the MPS of the endpoint.
* |[7] |DISBUF |Buffer Disable Bit
* | | |This bit is used to receive unknown size OUT short packet
* | | |The received packet size is reference USBD_EPxDATCNT register.
* | | |0 = Buffer Not Disabled when Bulk-OUT short packet is received.
* | | |1 = Buffer Disabled when Bulk-OUT short packet is received.
* @var HSUSBD_EP_T::EPMPS
* Offset: 0x14 Endpoint n Maximum Packet Size Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[10:0] |EPMPS |Endpoint Maximum Packet Size
* | | |This field determines the Maximum Packet Size of the Endpoint.
* @var HSUSBD_EP_T::EPTXCNT
* Offset: 0x18 Endpoint n Transfer Count Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[10:0] |TXCNT |Endpoint Transfer Count
* | | |For IN endpoints, this field determines the total number of bytes to be sent to the host in case of manual validation method.
* | | |For OUT endpoints, this field has no effect.
* @var HSUSBD_EP_T::EPCFG
* Offset: 0x1C Endpoint n Configuration Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |EPEN |Endpoint Valid
* | | |When set, this bit enables this endpoint
* | | |This bit has no effect on Endpoint 0, which is always enabled.
* | | |0 = The endpoint Disabled.
* | | |1 = The endpoint Enabled.
* |[2:1] |EPTYPE |Endpoint Type
* | | |This field selects the type of this endpoint. Endpoint 0 is forced to a Control type.
* | | |00 = Reserved.
* | | |01 = Bulk.
* | | |10 = Interrupt.
* | | |11 = Isochronous.
* |[3] |EPDIR |Endpoint Direction
* | | |0 = out-endpoint (Host OUT to Device).
* | | |1 = in-endpoint (Host IN to Device).
* | | |Note: A maximum of one OUT and IN endpoint is allowed for each endpoint number.
* |[7:4] |EPNUM |Endpoint Number
* | | |This field selects the number of the endpoint. Valid numbers 1 to 15.
* | | |Note: Do not support two endpoints have same endpoint number.
* @var HSUSBD_EP_T::EPBUFST
* Offset: 0x20 Endpoint n RAM Start Address Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[11:0] |SADDR |Endpoint Start Address
* | | |This is the start-address of the RAM space allocated for the endpoint A~L.
* @var HSUSBD_EP_T::EPBUFEND
* Offset: 0x24 Endpoint n RAM End Address Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[11:0] |EADDR |Endpoint End Address
* | | |This is the end-address of the RAM space allocated for the endpoint A~L.
*/
union {
__IO uint32_t EPDAT;
__IO uint8_t EPDAT_BYTE;
}; /*!< [0x0000] Endpoint n Data Register */
__IO uint32_t EPINTSTS; /*!< [0x0004] Endpoint n Interrupt Status Register */
__IO uint32_t EPINTEN; /*!< [0x0008] Endpoint n Interrupt Enable Register */
__I uint32_t EPDATCNT; /*!< [0x000c] Endpoint n Data Available Count Register */
__IO uint32_t EPRSPCTL; /*!< [0x0010] Endpoint n Response Control Register */
__IO uint32_t EPMPS; /*!< [0x0014] Endpoint n Maximum Packet Size Register */
__IO uint32_t EPTXCNT; /*!< [0x0018] Endpoint n Transfer Count Register */
__IO uint32_t EPCFG; /*!< [0x001c] Endpoint n Configuration Register */
__IO uint32_t EPBUFST; /*!< [0x0020] Endpoint n RAM Start Address Register */
__IO uint32_t EPBUFEND; /*!< [0x0024] Endpoint n RAM End Address Register */
} HSUSBD_EP_T;
typedef struct {
/**
* @var HSUSBD_T::GINTSTS
* Offset: 0x00 Global Interrupt Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |USBIF |USB Interrupt
* | | |This bit conveys the interrupt status for USB specific events endpoint
* | | |When set, USB interrupt status register should be read to determine the cause of the interrupt.
* | | |0 = No interrupt event occurred.
* | | |1 = The related interrupt event is occurred.
* |[1] |CEPIF |Control Endpoint Interrupt
* | | |This bit conveys the interrupt status for control endpoint
* | | |When set, Control-ep's interrupt status register should be read to determine the cause of the interrupt.
* | | |0 = No interrupt event occurred.
* | | |1 = The related interrupt event is occurred.
* |[2] |EPAIF |Endpoint a Interrupt
* | | |When set, the corresponding Endpoint A's interrupt status register should be read to determine the cause of the interrupt.
* | | |0 = No interrupt event occurred.
* | | |1 = The related interrupt event is occurred.
* |[3] |EPBIF |Endpoint B Interrupt
* | | |When set, the corresponding Endpoint B's interrupt status register should be read to determine the cause of the interrupt.
* | | |0 = No interrupt event occurred.
* | | |1 = The related interrupt event is occurred.
* |[4] |EPCIF |Endpoint C Interrupt
* | | |When set, the corresponding Endpoint C's interrupt status register should be read to determine the cause of the interrupt.
* | | |0 = No interrupt event occurred.
* | | |1 = The related interrupt event is occurred.
* |[5] |EPDIF |Endpoint D Interrupt
* | | |When set, the corresponding Endpoint D's interrupt status register should be read to determine the cause of the interrupt.
* | | |0 = No interrupt event occurred.
* | | |1 = The related interrupt event is occurred.
* |[6] |EPEIF |Endpoint E Interrupt
* | | |When set, the corresponding Endpoint E's interrupt status register should be read to determine the cause of the interrupt.
* | | |0 = No interrupt event occurred.
* | | |1 = The related interrupt event is occurred.
* |[7] |EPFIF |Endpoint F Interrupt
* | | |When set, the corresponding Endpoint F's interrupt status register should be read to determine the cause of the interrupt.
* | | |0 = No interrupt event occurred.
* | | |1 = The related interrupt event is occurred.
* |[8] |EPGIF |Endpoint G Interrupt
* | | |When set, the corresponding Endpoint G's interrupt status register should be read to determine the cause of the interrupt.
* | | |0 = No interrupt event occurred.
* | | |1 = The related interrupt event is occurred.
* |[9] |EPHIF |Endpoint H Interrupt
* | | |When set, the corresponding Endpoint H's interrupt status register should be read to determine the cause of the interrupt.
* | | |0 = No interrupt event occurred.
* | | |1 = The related interrupt event is occurred.
* |[10] |EPIIF |Endpoint I Interrupt
* | | |When set, the corresponding Endpoint I's interrupt status register should be read to determine the cause of the interrupt.
* | | |0 = No interrupt event occurred.
* | | |1 = The related interrupt event is occurred.
* |[11] |EPJIF |Endpoint J Interrupt
* | | |When set, the corresponding Endpoint J's interrupt status register should be read to determine the cause of the interrupt.
* | | |0 = No interrupt event occurred.
* | | |1 = The related interrupt event is occurred.
* |[12] |EPKIF |Endpoint K Interrupt
* | | |When set, the corresponding Endpoint K's interrupt status register should be read to determine the cause of the interrupt.
* | | |0 = No interrupt event occurred.
* | | |1 = The related interrupt event is occurred.
* |[13] |EPLIF |Endpoint L Interrupt
* | | |When set, the corresponding Endpoint L's interrupt status register should be read to determine the cause of the interrupt.
* | | |0 = No interrupt event occurred.
* | | |1 = The related interrupt event is occurred.
* @var HSUSBD_T::GINTEN
* Offset: 0x08 Global Interrupt Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |USBIEN |USB Interrupt Enable Bit
* | | |When set, this bit enables a local interrupt to be generated when a USB event occurs on the bus.
* | | |0 = The related interrupt Disabled.
* | | |1 = The related interrupt Enabled.
* |[1] |CEPIEN |Control Endpoint Interrupt Enable Bit
* | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the control endpoint.
* | | |0 = The related interrupt Disabled.
* | | |1 = The related interrupt Enabled.
* |[2] |EPAIEN |Interrupt Enable Control for Endpoint a
* | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint A.
* | | |0 = The related interrupt Disabled.
* | | |1 = The related interrupt Enabled.
* |[3] |EPBIEN |Interrupt Enable Control for Endpoint B
* | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint B
* | | |0 = The related interrupt Disabled.
* | | |1 = The related interrupt Enabled.
* |[4] |EPCIEN |Interrupt Enable Control for Endpoint C
* | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint C
* | | |0 = The related interrupt Disabled.
* | | |1 = The related interrupt Enabled.
* |[5] |EPDIEN |Interrupt Enable Control for Endpoint D
* | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint D
* | | |0 = The related interrupt Disabled.
* | | |1 = The related interrupt Enabled.
* |[6] |EPEIEN |Interrupt Enable Control for Endpoint E
* | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint E
* | | |0 = The related interrupt Disabled.
* | | |1 = The related interrupt Enabled.
* |[7] |EPFIEN |Interrupt Enable Control for Endpoint F
* | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint F
* | | |0 = The related interrupt Disabled.
* | | |1 = The related interrupt Enabled.
* |[8] |EPGIEN |Interrupt Enable Control for Endpoint G
* | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint G
* | | |0 = The related interrupt Disabled.
* | | |1 = The related interrupt Enabled.
* |[9] |EPHIEN |Interrupt Enable Control for Endpoint H
* | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint H
* | | |0 = The related interrupt Disabled.
* | | |1 = The related interrupt Enabled.
* |[10] |EPIIEN |Interrupt Enable Control for Endpoint I
* | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint I
* | | |0 = The related interrupt Disabled.
* | | |1 = The related interrupt Enabled.
* |[11] |EPJIEN |Interrupt Enable Control for Endpoint J
* | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint J
* | | |0 = The related interrupt Disabled.
* | | |1 = The related interrupt Enabled.
* |[12] |EPKIEN |Interrupt Enable Control for Endpoint K
* | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint K
* | | |0 = The related interrupt Disabled.
* | | |1 = The related interrupt Enabled.
* |[13] |EPLIEN |Interrupt Enable Control for Endpoint L
* | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint L
* | | |0 = The related interrupt Disabled.
* | | |1 = The related interrupt Enabled.
* @var HSUSBD_T::BUSINTSTS
* Offset: 0x10 USB Bus Interrupt Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SOFIF |SOF Receive Control
* | | |This bit indicates when a start-of-frame packet has been received.
* | | |0 = No start-of-frame packet has been received.
* | | |1 = Start-of-frame packet has been received.
* | | |Note: Write 1 to clear this bit to 0.
* |[1] |RSTIF |Reset Status
* | | |When set, this bit indicates that either the USB root port reset is end.
* | | |0 = No USB root port reset is end.
* | | |1 = USB root port reset is end.
* | | |Note: Write 1 to clear this bit to 0.
* |[2] |RESUMEIF |Resume
* | | |When set, this bit indicates that a device resume has occurred.
* | | |0 = No device resume has occurred.
* | | |1 = Device resume has occurred.
* | | |Note: Write 1 to clear this bit to 0.
* |[3] |SUSPENDIF |Suspend Request
* | | |This bit is set as default and it has to be cleared by writing '1' before the USB reset
* | | |This bit is also set when a USB Suspend request is detected from the host.
* | | |0 = No USB Suspend request is detected from the host.
* | | |1= USB Suspend request is detected from the host.
* | | |Note: Write 1 to clear this bit to 0.
* |[4] |HISPDIF |High-speed Settle
* | | |0 = No valid high-speed reset protocol is detected.
* | | |1 = Valid high-speed reset protocol is over and the device has settled in high-speed.
* | | |Note: Write 1 to clear this bit to 0.
* |[5] |DMADONEIF |DMA Completion Interrupt
* | | |0 = No DMA transfer over.
* | | |1 = DMA transfer is over.
* | | |Note: Write 1 to clear this bit to 0.
* |[6] |PHYCLKVLDIF|Usable Clock Interrupt
* | | |0 = Usable clock is not available.
* | | |1 = Usable clock is available from the transceiver.
* | | |Note: Write 1 to clear this bit to 0.
* |[8] |VBUSDETIF |VBUS Detection Interrupt Status
* | | |0 = No VBUS is plug-in.
* | | |1 = VBUS is plug-in.
* | | |Note: Write 1 to clear this bit to 0.
* @var HSUSBD_T::BUSINTEN
* Offset: 0x14 USB Bus Interrupt Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SOFIEN |SOF Interrupt
* | | |This bit enables the SOF interrupt.
* | | |0 = SOF interrupt Disabled.
* | | |1 = SOF interrupt Enabled.
* |[1] |RSTIEN |Reset Status
* | | |This bit enables the USB-Reset interrupt.
* | | |0 = USB-Reset interrupt Disabled.
* | | |1 = USB-Reset interrupt Enabled.
* |[2] |RESUMEIEN |Resume
* | | |This bit enables the Resume interrupt.
* | | |0 = Resume interrupt Disabled.
* | | |1 = Resume interrupt Enabled.
* |[3] |SUSPENDIEN|Suspend Request
* | | |This bit enables the Suspend interrupt.
* | | |0 = Suspend interrupt Disabled.
* | | |1 = Suspend interrupt Enabled.
* |[4] |HISPDIEN |High-speed Settle
* | | |This bit enables the high-speed settle interrupt.
* | | |0 = High-speed settle interrupt Disabled.
* | | |1 = High-speed settle interrupt Enabled.
* |[5] |DMADONEIEN|DMA Completion Interrupt
* | | |This bit enables the DMA completion interrupt
* | | |0 = DMA completion interrupt Disabled.
* | | |1 = DMA completion interrupt Enabled.
* |[6] |PHYCLKVLDIEN|Usable Clock Interrupt
* | | |This bit enables the usable clock interrupt.
* | | |0 = Usable clock interrupt Disabled.
* | | |1 = Usable clock interrupt Enabled.
* |[8] |VBUSDETIEN|VBUS Detection Interrupt Enable Bit
* | | |This bit enables the VBUS floating detection interrupt.
* | | |0 = VBUS floating detection interrupt Disabled.
* | | |1 = VBUS floating detection interrupt Enabled.
* @var HSUSBD_T::OPER
* Offset: 0x18 USB Operational Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |RESUMEEN |Generate Resume
* | | |0 = No Resume sequence to be initiated to the host.
* | | |1 = A Resume sequence to be initiated to the host if device remote wakeup is enabled
* | | |This bit is self-clearing.
* |[1] |HISPDEN |USB High-speed
* | | |0 = The USB device controller to suppress the chirp-sequence during reset protocol, thereby allowing the USB device controller to settle in full-speed, even though it is connected to a USB2.0 Host.
* | | |1 = The USB device controller to initiate a chirp-sequence during reset protocol.
* |[2] |CURSPD |USB Current Speed
* | | |0 = The device has settled in Full Speed.
* | | |1 = The USB device controller has settled in High-speed.
* @var HSUSBD_T::FRAMECNT
* Offset: 0x1C USB Frame Count Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[2:0] |MFRAMECNT |Micro-frame Counter
* | | |This field contains the micro-frame number for the frame number in the frame counter field.
* |[13:3] |FRAMECNT |Frame Counter
* | | |This field contains the frame count from the most recent start-of-frame packet.
* @var HSUSBD_T::FADDR
* Offset: 0x20 USB Function Address Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[6:0] |FADDR |USB Function Address
* | | |This field contains the current USB address of the device
* | | |This field is cleared when a root port reset is detected
* @var HSUSBD_T::TEST
* Offset: 0x24 USB Test Mode Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[2:0] |TESTMODE |Test Mode Selection
* | | |000 = Normal Operation.
* | | |001 = Test_J.
* | | |010 = Test_K.
* | | |011 = Test_SE0_NAK.
* | | |100 = Test_Packet.
* | | |101 = Test_Force_Enable.
* | | |110 = Reserved.
* | | |111 = Reserved.
* | | |Note: This field is cleared when root port reset is detected.
* @var HSUSBD_T::CEPDAT
* Offset: 0x28 Control-Endpoint Data Buffer
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |DAT |Control-endpoint Data Buffer
* | | |Control endpoint data buffer for the buffer transaction (read or write).
* | | |Note: Only word access is supported.
* @var HSUSBD_T::CEPDAT_BYTE
* Offset: 0x28 Control-Endpoint Data Buffer
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |DAT |Control-endpoint Data Buffer
* | | |Control endpoint data buffer for the buffer transaction (read or write).
* | | |Note: Only byte access is supported.
* @var HSUSBD_T::CEPCTL
* Offset: 0x2C Control-Endpoint Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |NAKCLR |No Acknowledge Control
* | | |This bit plays a crucial role in any control transfer.
* | | |0 = The bit is being cleared by the local CPU by writing zero, the USB device controller will be responding with NAKs for the subsequent status phase
* | | |This mechanism holds the host from moving to the next request, until the local CPU is also ready to process the next request.
* | | |1 = This bit is set to one by the USB device controller, whenever a setup token is received
* | | |The local CPU can take its own time to finish off any house-keeping work based on the request and then clear this bit.
* | | |Note: Only when CPU writes data[1:0] is 2'b10 or 2'b00, this bit can be updated.
* |[1] |STALLEN |Stall Enable Bit
* | | |When this stall bit is set, the control endpoint sends a stall handshake in response to any in or out token thereafter
* | | |This is typically used for response to invalid/unsupported requests
* | | |When this bit is being set the NAK clear bit has to be cleared at the same time since the NAK clear bit has highest priority than STALL
* | | |It is automatically cleared on receipt of a next setup-token
* | | |So, the local CPU need not write again to clear this bit.
* | | |0 = No sends a stall handshake in response to any in or out token thereafter.
* | | |1 = The control endpoint sends a stall handshake in response to any in or out token thereafter.
* | | |Note: Only when CPU writes data[1:0] is 2'b10 or 2'b00, this bit can be updated.
* |[2] |ZEROLEN |Zero Packet Length
* | | |This bit is valid for Auto Validation mode only.
* | | |0 = No zero length packet to the host during Data stage to an IN token.
* | | |1 = USB device controller can send a zero length packet to the host during Data stage to an IN token
* | | |This bit gets cleared once the zero length data packet is sent
* | | |So, the local CPU need not write again to clear this bit.
* |[3] |FLUSH |CEP-flush Bit
* | | |0 = No the packet buffer and its corresponding USBD_CEPDATCNT register to be cleared.
* | | |1 = The packet buffer and its corresponding USBD_CEPDATCNT register to be cleared
* | | |This bit is self-cleaning.
* @var HSUSBD_T::CEPINTEN
* Offset: 0x30 Control-Endpoint Interrupt Enable
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SETUPTKIEN|Setup Token Interrupt Enable Bit
* | | |0 = The SETUP token interrupt in Control Endpoint Disabled.
* | | |1 = The SETUP token interrupt in Control Endpoint Enabled.
* |[1] |SETUPPKIEN|Setup Packet Interrupt
* | | |0 = The SETUP packet interrupt in Control Endpoint Disabled.
* | | |1 = The SETUP packet interrupt in Control Endpoint Enabled.
* |[2] |OUTTKIEN |Out Token Interrupt
* | | |0 = The OUT token interrupt in Control Endpoint Disabled.
* | | |1 = The OUT token interrupt in Control Endpoint Enabled.
* |[3] |INTKIEN |In Token Interrupt
* | | |0 = The IN token interrupt in Control Endpoint Disabled.
* | | |1 = The IN token interrupt in Control Endpoint Enabled.
* |[4] |PINGIEN |Ping Token Interrupt
* | | |0 = The ping token interrupt in Control Endpoint Disabled.
* | | |1 = The ping token interrupt Control Endpoint Enabled.
* |[5] |TXPKIEN |Data Packet Transmitted Interrupt
* | | |0 = The data packet transmitted interrupt in Control Endpoint Disabled.
* | | |1 = The data packet transmitted interrupt in Control Endpoint Enabled.
* |[6] |RXPKIEN |Data Packet Received Interrupt
* | | |0 = The data received interrupt in Control Endpoint Disabled.
* | | |1 = The data received interrupt in Control Endpoint Enabled.
* |[7] |NAKIEN |NAK Sent Interrupt
* | | |0 = The NAK sent interrupt in Control Endpoint Disabled.
* | | |1 = The NAK sent interrupt in Control Endpoint Enabled.
* |[8] |STALLIEN |STALL Sent Interrupt
* | | |0 = The STALL sent interrupt in Control Endpoint Disabled.
* | | |1 = The STALL sent interrupt in Control Endpoint Enabled.
* |[9] |ERRIEN |USB Error Interrupt
* | | |0 = The USB Error interrupt in Control Endpoint Disabled.
* | | |1 = The USB Error interrupt in Control Endpoint Enabled.
* |[10] |STSDONEIEN|Status Completion Interrupt
* | | |0 = The Status Completion interrupt in Control Endpoint Disabled.
* | | |1 = The Status Completion interrupt in Control Endpoint Enabled.
* |[11] |BUFFULLIEN|Buffer Full Interrupt
* | | |0 = The buffer full interrupt in Control Endpoint Disabled.
* | | |1 = The buffer full interrupt in Control Endpoint Enabled.
* |[12] |BUFEMPTYIEN|Buffer Empty Interrupt
* | | |0 = The buffer empty interrupt in Control Endpoint Disabled.
* | | |1= The buffer empty interrupt in Control Endpoint Enabled.
* @var HSUSBD_T::CEPINTSTS
* Offset: 0x34 Control-Endpoint Interrupt Status
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SETUPTKIF |Setup Token Interrupt
* | | |0 = Not a Setup token is received.
* | | |1 = A Setup token is received. Writing 1 clears this status bit
* | | |Note: Write 1 to clear this bit to 0.
* |[1] |SETUPPKIF |Setup Packet Interrupt
* | | |This bit must be cleared (by writing 1) before the next setup packet can be received
* | | |If the bit is not cleared, then the successive setup packets will be overwritten in the setup packet buffer.
* | | |0 = Not a Setup packet has been received from the host.
* | | |1 = A Setup packet has been received from the host.
* | | |Note: Write 1 to clear this bit to 0.
* |[2] |OUTTKIF |Out Token Interrupt
* | | |0 = The control-endpoint does not received an OUT token from the host.
* | | |1 = The control-endpoint receives an OUT token from the host.
* | | |Note: Write 1 to clear this bit to 0.
* |[3] |INTKIF |in Token Interrupt
* | | |0 = The control-endpoint does not received an IN token from the host.
* | | |1 = The control-endpoint receives an IN token from the host.
* | | |Note: Write 1 to clear this bit to 0.
* |[4] |PINGIF |Ping Token Interrupt
* | | |0 = The control-endpoint does not received a ping token from the host.
* | | |1 = The control-endpoint receives a ping token from the host.
* | | |Note: Write 1 to clear this bit to 0.
* |[5] |TXPKIF |Data Packet Transmitted Interrupt
* | | |0 = Not a data packet is successfully transmitted to the host in response to an IN-token and an ACK-token is received for the same.
* | | |1 = A data packet is successfully transmitted to the host in response to an IN-token and an ACK-token is received for the same.
* | | |Note: Write 1 to clear this bit to 0.
* |[6] |RXPKIF |Data Packet Received Interrupt
* | | |0 = Not a data packet is successfully received from the host for an OUT-token and an ACK is sent to the host.
* | | |1 = A data packet is successfully received from the host for an OUT-token and an ACK is sent to the host.
* | | |Note: Write 1 to clear this bit to 0.
* |[7] |NAKIF |NAK Sent Interrupt
* | | |0 = Not a NAK-token is sent in response to an IN/OUT token.
* | | |1 = A NAK-token is sent in response to an IN/OUT token.
* | | |Note: Write 1 to clear this bit to 0.
* |[8] |STALLIF |STALL Sent Interrupt
* | | |0 = Not a stall-token is sent in response to an IN/OUT token.
* | | |1 = A stall-token is sent in response to an IN/OUT token.
* | | |Note: Write 1 to clear this bit to 0.
* |[9] |ERRIF |USB Error Interrupt
* | | |0 = No error had occurred during the transaction.
* | | |1 = An error had occurred during the transaction.
* | | |Note: Write 1 to clear this bit to 0.
* |[10] |STSDONEIF |Status Completion Interrupt
* | | |0 = Not a USB transaction has completed successfully.
* | | |1 = The status stage of a USB transaction has completed successfully.
* | | |Note: Write 1 to clear this bit to 0.
* |[11] |BUFFULLIF |Buffer Full Interrupt
* | | |0 = The control-endpoint buffer is not full.
* | | |1 = The control-endpoint buffer is full.
* | | |Note: Write 1 to clear this bit to 0.
* |[12] |BUFEMPTYIF|Buffer Empty Interrupt
* | | |0 = The control-endpoint buffer is not empty.
* | | |1 = The control-endpoint buffer is empty.
* | | |Note: Write 1 to clear this bit to 0.
* @var HSUSBD_T::CEPTXCNT
* Offset: 0x38 Control-Endpoint In-transfer Data Count
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |TXCNT |In-transfer Data Count
* | | |There is no mode selection for the control endpoint (but it operates like manual mode).The local-CPU has to fill the control-endpoint buffer with the data to be sent for an in-token and to write the count of bytes in this register
* | | |When zero is written into this field, a zero length packet is sent to the host
* | | |When the count written in the register is more than the MPS, the data sent will be of only MPS.
* @var HSUSBD_T::CEPRXCNT
* Offset: 0x3C Control-Endpoint Out-transfer Data Count
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |RXCNT |Out-transfer Data Count
* | | |The USB device controller maintains the count of the data received in case of an out transfer, during the control transfer.
* @var HSUSBD_T::CEPDATCNT
* Offset: 0x40 Control-Endpoint data count
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |DATCNT |Control-endpoint Data Count
* | | |The USB device controller maintains the count of the data of control-endpoint.
* @var HSUSBD_T::SETUP1_0
* Offset: 0x44 Setup1 & Setup0 bytes
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |SETUP0 |Setup Byte 0[7:0]
* | | |This register provides byte 0 of the last setup packet received
* | | |For a Standard Device Request, the following bmRequestType information is returned.
* | | |Bit 7(Direction):
* | | | 0: Host to device
* | | | 1: Device to host
* | | |Bit 6-5 (Type):
* | | | 00: Standard
* | | | 01: Class
* | | | 10: Vendor
* | | | 11: Reserved
* | | |Bit 4-0 (Recipient)
* | | | 00000: Device
* | | | 00001: Interface
* | | | 00010: Endpoint
* | | | 00011: Other
* | | | Others: Reserved
* |[15:8] |SETUP1 |Setup Byte 1[15:8]
* | | |This register provides byte 1 of the last setup packet received
* | | |For a Standard Device Request, the following bRequest Code information is returned.
* | | |00000000 = Get Status.
* | | |00000001 = Clear Feature.
* | | |00000010 = Reserved.
* | | |00000011 = Set Feature.
* | | |00000100 = Reserved.
* | | |00000101 = Set Address.
* | | |00000110 = Get Descriptor.
* | | |00000111 = Set Descriptor.
* | | |00001000 = Get Configuration.
* | | |00001001 = Set Configuration.
* | | |00001010 = Get Interface.
* | | |00001011 = Set Interface.
* | | |00001100 = Sync Frame.
* @var HSUSBD_T::SETUP3_2
* Offset: 0x48 Setup3 & Setup2 Bytes
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |SETUP2 |Setup Byte 2 [7:0]
* | | |This register provides byte 2 of the last setup packet received
* | | |For a Standard Device Request, the least significant byte of the wValue field is returned
* |[15:8] |SETUP3 |Setup Byte 3 [15:8]
* | | |This register provides byte 3 of the last setup packet received
* | | |For a Standard Device Request, the most significant byte of the wValue field is returned.
* @var HSUSBD_T::SETUP5_4
* Offset: 0x4C Setup5 & Setup4 Bytes
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |SETUP4 |Setup Byte 4[7:0]
* | | |This register provides byte 4 of the last setup packet received
* | | |For a Standard Device Request, the least significant byte of the wIndex is returned.
* |[15:8] |SETUP5 |Setup Byte 5[15:8]
* | | |This register provides byte 5 of the last setup packet received
* | | |For a Standard Device Request, the most significant byte of the wIndex field is returned.
* @var HSUSBD_T::SETUP7_6
* Offset: 0x50 Setup7 & Setup6 Bytes
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |SETUP6 |Setup Byte 6[7:0]
* | | |This register provides byte 6 of the last setup packet received
* | | |For a Standard Device Request, the least significant byte of the wLength field is returned.
* |[15:8] |SETUP7 |Setup Byte 7[15:8]
* | | |This register provides byte 7 of the last setup packet received
* | | |For a Standard Device Request, the most significant byte of the wLength field is returned.
* @var HSUSBD_T::CEPBUFST
* Offset: 0x54 Control Endpoint RAM Start Address Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[11:0] |SADDR |Control-endpoint Start Address
* | | |This is the start-address of the RAM space allocated for the control-endpoint.
* @var HSUSBD_T::CEPBUFEND
* Offset: 0x58 Control Endpoint RAM End Address Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[11:0] |EADDR |Control-endpoint End Address
* | | |This is the end-address of the RAM space allocated for the control-endpoint.
* @var HSUSBD_T::DMACTL
* Offset: 0x5C DMA Control Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |EPNUM |DMA Endpoint Address Bits
* | | |Used to define the Endpoint Address
* |[4] |DMARD |DMA Operation
* | | |0 : The operation is a DMA write (read from USB buffer)
* | | |DMA will check endpoint data available count (USBD_EPxDATCNT) according to EPNM setting before to perform DMA write operation.
* | | |1 : The operation is a DMA read (write to USB buffer).
* |[5] |DMAEN |DMA Enable Bit
* | | |0 : DMA function Disabled.
* | | |1 : DMA function Enabled.
* |[6] |SGEN |Scatter Gather Function Enable Bit
* | | |0 : Scatter gather function Disabled.
* | | |1 : Scatter gather function Enabled.
* |[7] |DMARST |Reset DMA State Machine
* | | |0 : No reset the DMA state machine.
* | | |1 : Reset the DMA state machine.
* |[8] |SVINEP |Serve IN Endpoint
* | | |This bit is used to specify DMA serving endpoint-IN endpoint or OUT endpoint.
* | | |0: DMA serves OUT endpoint
* | | |1: DMA serves IN endpoint
* @var HSUSBD_T::DMACNT
* Offset: 0x60 DMA Count Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[19:0] |DMACNT |DMA Transfer Count
* | | |The transfer count of the DMA operation to be performed is written to this register.
* @var HSUSBD_T::DMAADDR
* Offset: 0x700 AHB DMA Address Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |DMAADDR |DMAADDR
* | | |The register specifies the address from which the DMA has to read / write
* | | |The address must WORD (32-bit) aligned.
* @var HSUSBD_T::PHYCTL
* Offset: 0x704 USB PHY Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[8] |DPPUEN |DP Pull-up
* | | |0 = Pull-up resistor on D+ Disabled.
* | | |1 = Pull-up resistor on D+ Enabled.
* |[9] |PHYEN |PHY Suspend Enable Bit
* | | |0 = The USB PHY is suspend.
* | | |1 = The USB PHY is not suspend.
* |[24] |WKEN |Wake-up Enable Bit
* | | |0 = The wake-up function Disabled.
* | | |1 = The wake-up function Enabled.
* |[31] |VBUSDET |VBUS Status
* | | |0 = The VBUS is not detected yet.
* | | |1 = The VBUS is detected.
*/
__I uint32_t GINTSTS; /*!< [0x0000] Global Interrupt Status Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE0[1];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t GINTEN; /*!< [0x0008] Global Interrupt Enable Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE1[1];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t BUSINTSTS; /*!< [0x0010] USB Bus Interrupt Status Register */
__IO uint32_t BUSINTEN; /*!< [0x0014] USB Bus Interrupt Enable Register */
__IO uint32_t OPER; /*!< [0x0018] USB Operational Register */
__I uint32_t FRAMECNT; /*!< [0x001c] USB Frame Count Register */
__IO uint32_t FADDR; /*!< [0x0020] USB Function Address Register */
__IO uint32_t TEST; /*!< [0x0024] USB Test Mode Register */
union {
__IO uint32_t CEPDAT;
__IO uint8_t CEPDAT_BYTE;
}; /*!< [0x0028] Control-Endpoint Data Buffer */
__IO uint32_t CEPCTL; /*!< [0x002c] Control-Endpoint Control Register */
__IO uint32_t CEPINTEN; /*!< [0x0030] Control-Endpoint Interrupt Enable */
__IO uint32_t CEPINTSTS; /*!< [0x0034] Control-Endpoint Interrupt Status */
__IO uint32_t CEPTXCNT; /*!< [0x0038] Control-Endpoint In-transfer Data Count */
__I uint32_t CEPRXCNT; /*!< [0x003c] Control-Endpoint Out-transfer Data Count */
__I uint32_t CEPDATCNT; /*!< [0x0040] Control-Endpoint data count */
__I uint32_t SETUP1_0; /*!< [0x0044] Setup1 & Setup0 bytes */
__I uint32_t SETUP3_2; /*!< [0x0048] Setup3 & Setup2 Bytes */
__I uint32_t SETUP5_4; /*!< [0x004c] Setup5 & Setup4 Bytes */
__I uint32_t SETUP7_6; /*!< [0x0050] Setup7 & Setup6 Bytes */
__IO uint32_t CEPBUFST; /*!< [0x0054] Control Endpoint RAM Start Address Register */
__IO uint32_t CEPBUFEND; /*!< [0x0058] Control Endpoint RAM End Address Register */
__IO uint32_t DMACTL; /*!< [0x005c] DMA Control Status Register */
__IO uint32_t DMACNT; /*!< [0x0060] DMA Count Register */
HSUSBD_EP_T EP[12];
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE2[303];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t DMAADDR; /*!< [0x0700] AHB DMA Address Register */
__IO uint32_t PHYCTL; /*!< [0x0704] USB PHY Control Register */
} HSUSBD_T;
/**
@addtogroup HSUSBD_CONST HSUSBD Bit Field Definition
Constant Definitions for HSUSBD Controller
@{ */
#define HSUSBD_GINTSTS_USBIF_Pos (0) /*!< HSUSBD_T::GINTSTS: USBIF Position */
#define HSUSBD_GINTSTS_USBIF_Msk (0x1ul << HSUSBD_GINTSTS_USBIF_Pos) /*!< HSUSBD_T::GINTSTS: USBIF Mask */
#define HSUSBD_GINTSTS_CEPIF_Pos (1) /*!< HSUSBD_T::GINTSTS: CEPIF Position */
#define HSUSBD_GINTSTS_CEPIF_Msk (0x1ul << HSUSBD_GINTSTS_CEPIF_Pos) /*!< HSUSBD_T::GINTSTS: CEPIF Mask */
#define HSUSBD_GINTSTS_EPAIF_Pos (2) /*!< HSUSBD_T::GINTSTS: EPAIF Position */
#define HSUSBD_GINTSTS_EPAIF_Msk (0x1ul << HSUSBD_GINTSTS_EPAIF_Pos) /*!< HSUSBD_T::GINTSTS: EPAIF Mask */
#define HSUSBD_GINTSTS_EPBIF_Pos (3) /*!< HSUSBD_T::GINTSTS: EPBIF Position */
#define HSUSBD_GINTSTS_EPBIF_Msk (0x1ul << HSUSBD_GINTSTS_EPBIF_Pos) /*!< HSUSBD_T::GINTSTS: EPBIF Mask */
#define HSUSBD_GINTSTS_EPCIF_Pos (4) /*!< HSUSBD_T::GINTSTS: EPCIF Position */
#define HSUSBD_GINTSTS_EPCIF_Msk (0x1ul << HSUSBD_GINTSTS_EPCIF_Pos) /*!< HSUSBD_T::GINTSTS: EPCIF Mask */
#define HSUSBD_GINTSTS_EPDIF_Pos (5) /*!< HSUSBD_T::GINTSTS: EPDIF Position */
#define HSUSBD_GINTSTS_EPDIF_Msk (0x1ul << HSUSBD_GINTSTS_EPDIF_Pos) /*!< HSUSBD_T::GINTSTS: EPDIF Mask */
#define HSUSBD_GINTSTS_EPEIF_Pos (6) /*!< HSUSBD_T::GINTSTS: EPEIF Position */
#define HSUSBD_GINTSTS_EPEIF_Msk (0x1ul << HSUSBD_GINTSTS_EPEIF_Pos) /*!< HSUSBD_T::GINTSTS: EPEIF Mask */
#define HSUSBD_GINTSTS_EPFIF_Pos (7) /*!< HSUSBD_T::GINTSTS: EPFIF Position */
#define HSUSBD_GINTSTS_EPFIF_Msk (0x1ul << HSUSBD_GINTSTS_EPFIF_Pos) /*!< HSUSBD_T::GINTSTS: EPFIF Mask */
#define HSUSBD_GINTSTS_EPGIF_Pos (8) /*!< HSUSBD_T::GINTSTS: EPGIF Position */
#define HSUSBD_GINTSTS_EPGIF_Msk (0x1ul << HSUSBD_GINTSTS_EPGIF_Pos) /*!< HSUSBD_T::GINTSTS: EPGIF Mask */
#define HSUSBD_GINTSTS_EPHIF_Pos (9) /*!< HSUSBD_T::GINTSTS: EPHIF Position */
#define HSUSBD_GINTSTS_EPHIF_Msk (0x1ul << HSUSBD_GINTSTS_EPHIF_Pos) /*!< HSUSBD_T::GINTSTS: EPHIF Mask */
#define HSUSBD_GINTSTS_EPIIF_Pos (10) /*!< HSUSBD_T::GINTSTS: EPIIF Position */
#define HSUSBD_GINTSTS_EPIIF_Msk (0x1ul << HSUSBD_GINTSTS_EPIIF_Pos) /*!< HSUSBD_T::GINTSTS: EPIIF Mask */
#define HSUSBD_GINTSTS_EPJIF_Pos (11) /*!< HSUSBD_T::GINTSTS: EPJIF Position */
#define HSUSBD_GINTSTS_EPJIF_Msk (0x1ul << HSUSBD_GINTSTS_EPJIF_Pos) /*!< HSUSBD_T::GINTSTS: EPJIF Mask */
#define HSUSBD_GINTSTS_EPKIF_Pos (12) /*!< HSUSBD_T::GINTSTS: EPKIF Position */
#define HSUSBD_GINTSTS_EPKIF_Msk (0x1ul << HSUSBD_GINTSTS_EPKIF_Pos) /*!< HSUSBD_T::GINTSTS: EPKIF Mask */
#define HSUSBD_GINTSTS_EPLIF_Pos (13) /*!< HSUSBD_T::GINTSTS: EPLIF Position */
#define HSUSBD_GINTSTS_EPLIF_Msk (0x1ul << HSUSBD_GINTSTS_EPLIF_Pos) /*!< HSUSBD_T::GINTSTS: EPLIF Mask */
#define HSUSBD_GINTEN_USBIEN_Pos (0) /*!< HSUSBD_T::GINTEN: USBIEN Position */
#define HSUSBD_GINTEN_USBIEN_Msk (0x1ul << HSUSBD_GINTEN_USBIEN_Pos) /*!< HSUSBD_T::GINTEN: USBIEN Mask */
#define HSUSBD_GINTEN_CEPIEN_Pos (1) /*!< HSUSBD_T::GINTEN: CEPIEN Position */
#define HSUSBD_GINTEN_CEPIEN_Msk (0x1ul << HSUSBD_GINTEN_CEPIEN_Pos) /*!< HSUSBD_T::GINTEN: CEPIEN Mask */
#define HSUSBD_GINTEN_EPAIEN_Pos (2) /*!< HSUSBD_T::GINTEN: EPAIEN Position */
#define HSUSBD_GINTEN_EPAIEN_Msk (0x1ul << HSUSBD_GINTEN_EPAIEN_Pos) /*!< HSUSBD_T::GINTEN: EPAIEN Mask */
#define HSUSBD_GINTEN_EPBIEN_Pos (3) /*!< HSUSBD_T::GINTEN: EPBIEN Position */
#define HSUSBD_GINTEN_EPBIEN_Msk (0x1ul << HSUSBD_GINTEN_EPBIEN_Pos) /*!< HSUSBD_T::GINTEN: EPBIEN Mask */
#define HSUSBD_GINTEN_EPCIEN_Pos (4) /*!< HSUSBD_T::GINTEN: EPCIEN Position */
#define HSUSBD_GINTEN_EPCIEN_Msk (0x1ul << HSUSBD_GINTEN_EPCIEN_Pos) /*!< HSUSBD_T::GINTEN: EPCIEN Mask */
#define HSUSBD_GINTEN_EPDIEN_Pos (5) /*!< HSUSBD_T::GINTEN: EPDIEN Position */
#define HSUSBD_GINTEN_EPDIEN_Msk (0x1ul << HSUSBD_GINTEN_EPDIEN_Pos) /*!< HSUSBD_T::GINTEN: EPDIEN Mask */
#define HSUSBD_GINTEN_EPEIEN_Pos (6) /*!< HSUSBD_T::GINTEN: EPEIEN Position */
#define HSUSBD_GINTEN_EPEIEN_Msk (0x1ul << HSUSBD_GINTEN_EPEIEN_Pos) /*!< HSUSBD_T::GINTEN: EPEIEN Mask */
#define HSUSBD_GINTEN_EPFIEN_Pos (7) /*!< HSUSBD_T::GINTEN: EPFIEN Position */
#define HSUSBD_GINTEN_EPFIEN_Msk (0x1ul << HSUSBD_GINTEN_EPFIEN_Pos) /*!< HSUSBD_T::GINTEN: EPFIEN Mask */
#define HSUSBD_GINTEN_EPGIEN_Pos (8) /*!< HSUSBD_T::GINTEN: EPGIEN Position */
#define HSUSBD_GINTEN_EPGIEN_Msk (0x1ul << HSUSBD_GINTEN_EPGIEN_Pos) /*!< HSUSBD_T::GINTEN: EPGIEN Mask */
#define HSUSBD_GINTEN_EPHIEN_Pos (9) /*!< HSUSBD_T::GINTEN: EPHIEN Position */
#define HSUSBD_GINTEN_EPHIEN_Msk (0x1ul << HSUSBD_GINTEN_EPHIEN_Pos) /*!< HSUSBD_T::GINTEN: EPHIEN Mask */
#define HSUSBD_GINTEN_EPIIEN_Pos (10) /*!< HSUSBD_T::GINTEN: EPIIEN Position */
#define HSUSBD_GINTEN_EPIIEN_Msk (0x1ul << HSUSBD_GINTEN_EPIIEN_Pos) /*!< HSUSBD_T::GINTEN: EPIIEN Mask */
#define HSUSBD_GINTEN_EPJIEN_Pos (11) /*!< HSUSBD_T::GINTEN: EPJIEN Position */
#define HSUSBD_GINTEN_EPJIEN_Msk (0x1ul << HSUSBD_GINTEN_EPJIEN_Pos) /*!< HSUSBD_T::GINTEN: EPJIEN Mask */
#define HSUSBD_GINTEN_EPKIEN_Pos (12) /*!< HSUSBD_T::GINTEN: EPKIEN Position */
#define HSUSBD_GINTEN_EPKIEN_Msk (0x1ul << HSUSBD_GINTEN_EPKIEN_Pos) /*!< HSUSBD_T::GINTEN: EPKIEN Mask */
#define HSUSBD_GINTEN_EPLIEN_Pos (13) /*!< HSUSBD_T::GINTEN: EPLIEN Position */
#define HSUSBD_GINTEN_EPLIEN_Msk (0x1ul << HSUSBD_GINTEN_EPLIEN_Pos) /*!< HSUSBD_T::GINTEN: EPLIEN Mask */
#define HSUSBD_BUSINTSTS_SOFIF_Pos (0) /*!< HSUSBD_T::BUSINTSTS: SOFIF Position */
#define HSUSBD_BUSINTSTS_SOFIF_Msk (0x1ul << HSUSBD_BUSINTSTS_SOFIF_Pos) /*!< HSUSBD_T::BUSINTSTS: SOFIF Mask */
#define HSUSBD_BUSINTSTS_RSTIF_Pos (1) /*!< HSUSBD_T::BUSINTSTS: RSTIF Position */
#define HSUSBD_BUSINTSTS_RSTIF_Msk (0x1ul << HSUSBD_BUSINTSTS_RSTIF_Pos) /*!< HSUSBD_T::BUSINTSTS: RSTIF Mask */
#define HSUSBD_BUSINTSTS_RESUMEIF_Pos (2) /*!< HSUSBD_T::BUSINTSTS: RESUMEIF Position */
#define HSUSBD_BUSINTSTS_RESUMEIF_Msk (0x1ul << HSUSBD_BUSINTSTS_RESUMEIF_Pos) /*!< HSUSBD_T::BUSINTSTS: RESUMEIF Mask */
#define HSUSBD_BUSINTSTS_SUSPENDIF_Pos (3) /*!< HSUSBD_T::BUSINTSTS: SUSPENDIF Position*/
#define HSUSBD_BUSINTSTS_SUSPENDIF_Msk (0x1ul << HSUSBD_BUSINTSTS_SUSPENDIF_Pos) /*!< HSUSBD_T::BUSINTSTS: SUSPENDIF Mask */
#define HSUSBD_BUSINTSTS_HISPDIF_Pos (4) /*!< HSUSBD_T::BUSINTSTS: HISPDIF Position */
#define HSUSBD_BUSINTSTS_HISPDIF_Msk (0x1ul << HSUSBD_BUSINTSTS_HISPDIF_Pos) /*!< HSUSBD_T::BUSINTSTS: HISPDIF Mask */
#define HSUSBD_BUSINTSTS_DMADONEIF_Pos (5) /*!< HSUSBD_T::BUSINTSTS: DMADONEIF Position*/
#define HSUSBD_BUSINTSTS_DMADONEIF_Msk (0x1ul << HSUSBD_BUSINTSTS_DMADONEIF_Pos) /*!< HSUSBD_T::BUSINTSTS: DMADONEIF Mask */
#define HSUSBD_BUSINTSTS_PHYCLKVLDIF_Pos (6) /*!< HSUSBD_T::BUSINTSTS: PHYCLKVLDIF Position*/
#define HSUSBD_BUSINTSTS_PHYCLKVLDIF_Msk (0x1ul << HSUSBD_BUSINTSTS_PHYCLKVLDIF_Pos) /*!< HSUSBD_T::BUSINTSTS: PHYCLKVLDIF Mask */
#define HSUSBD_BUSINTSTS_VBUSDETIF_Pos (8) /*!< HSUSBD_T::BUSINTSTS: VBUSDETIF Position*/
#define HSUSBD_BUSINTSTS_VBUSDETIF_Msk (0x1ul << HSUSBD_BUSINTSTS_VBUSDETIF_Pos) /*!< HSUSBD_T::BUSINTSTS: VBUSDETIF Mask */
#define HSUSBD_BUSINTEN_SOFIEN_Pos (0) /*!< HSUSBD_T::BUSINTEN: SOFIEN Position */
#define HSUSBD_BUSINTEN_SOFIEN_Msk (0x1ul << HSUSBD_BUSINTEN_SOFIEN_Pos) /*!< HSUSBD_T::BUSINTEN: SOFIEN Mask */
#define HSUSBD_BUSINTEN_RSTIEN_Pos (1) /*!< HSUSBD_T::BUSINTEN: RSTIEN Position */
#define HSUSBD_BUSINTEN_RSTIEN_Msk (0x1ul << HSUSBD_BUSINTEN_RSTIEN_Pos) /*!< HSUSBD_T::BUSINTEN: RSTIEN Mask */
#define HSUSBD_BUSINTEN_RESUMEIEN_Pos (2) /*!< HSUSBD_T::BUSINTEN: RESUMEIEN Position */
#define HSUSBD_BUSINTEN_RESUMEIEN_Msk (0x1ul << HSUSBD_BUSINTEN_RESUMEIEN_Pos) /*!< HSUSBD_T::BUSINTEN: RESUMEIEN Mask */
#define HSUSBD_BUSINTEN_SUSPENDIEN_Pos (3) /*!< HSUSBD_T::BUSINTEN: SUSPENDIEN Position*/
#define HSUSBD_BUSINTEN_SUSPENDIEN_Msk (0x1ul << HSUSBD_BUSINTEN_SUSPENDIEN_Pos) /*!< HSUSBD_T::BUSINTEN: SUSPENDIEN Mask */
#define HSUSBD_BUSINTEN_HISPDIEN_Pos (4) /*!< HSUSBD_T::BUSINTEN: HISPDIEN Position */
#define HSUSBD_BUSINTEN_HISPDIEN_Msk (0x1ul << HSUSBD_BUSINTEN_HISPDIEN_Pos) /*!< HSUSBD_T::BUSINTEN: HISPDIEN Mask */
#define HSUSBD_BUSINTEN_DMADONEIEN_Pos (5) /*!< HSUSBD_T::BUSINTEN: DMADONEIEN Position*/
#define HSUSBD_BUSINTEN_DMADONEIEN_Msk (0x1ul << HSUSBD_BUSINTEN_DMADONEIEN_Pos) /*!< HSUSBD_T::BUSINTEN: DMADONEIEN Mask */
#define HSUSBD_BUSINTEN_PHYCLKVLDIEN_Pos (6) /*!< HSUSBD_T::BUSINTEN: PHYCLKVLDIEN Position*/
#define HSUSBD_BUSINTEN_PHYCLKVLDIEN_Msk (0x1ul << HSUSBD_BUSINTEN_PHYCLKVLDIEN_Pos) /*!< HSUSBD_T::BUSINTEN: PHYCLKVLDIEN Mask */
#define HSUSBD_BUSINTEN_VBUSDETIEN_Pos (8) /*!< HSUSBD_T::BUSINTEN: VBUSDETIEN Position*/
#define HSUSBD_BUSINTEN_VBUSDETIEN_Msk (0x1ul << HSUSBD_BUSINTEN_VBUSDETIEN_Pos) /*!< HSUSBD_T::BUSINTEN: VBUSDETIEN Mask */
#define HSUSBD_OPER_RESUMEEN_Pos (0) /*!< HSUSBD_T::OPER: RESUMEEN Position */
#define HSUSBD_OPER_RESUMEEN_Msk (0x1ul << HSUSBD_OPER_RESUMEEN_Pos) /*!< HSUSBD_T::OPER: RESUMEEN Mask */
#define HSUSBD_OPER_HISPDEN_Pos (1) /*!< HSUSBD_T::OPER: HISPDEN Position */
#define HSUSBD_OPER_HISPDEN_Msk (0x1ul << HSUSBD_OPER_HISPDEN_Pos) /*!< HSUSBD_T::OPER: HISPDEN Mask */
#define HSUSBD_OPER_CURSPD_Pos (2) /*!< HSUSBD_T::OPER: CURSPD Position */
#define HSUSBD_OPER_CURSPD_Msk (0x1ul << HSUSBD_OPER_CURSPD_Pos) /*!< HSUSBD_T::OPER: CURSPD Mask */
#define HSUSBD_FRAMECNT_MFRAMECNT_Pos (0) /*!< HSUSBD_T::FRAMECNT: MFRAMECNT Position */
#define HSUSBD_FRAMECNT_MFRAMECNT_Msk (0x7ul << HSUSBD_FRAMECNT_MFRAMECNT_Pos) /*!< HSUSBD_T::FRAMECNT: MFRAMECNT Mask */
#define HSUSBD_FRAMECNT_FRAMECNT_Pos (3) /*!< HSUSBD_T::FRAMECNT: FRAMECNT Position */
#define HSUSBD_FRAMECNT_FRAMECNT_Msk (0x7fful << HSUSBD_FRAMECNT_FRAMECNT_Pos) /*!< HSUSBD_T::FRAMECNT: FRAMECNT Mask */
#define HSUSBD_FADDR_FADDR_Pos (0) /*!< HSUSBD_T::FADDR: FADDR Position */
#define HSUSBD_FADDR_FADDR_Msk (0x7ful << HSUSBD_FADDR_FADDR_Pos) /*!< HSUSBD_T::FADDR: FADDR Mask */
#define HSUSBD_TEST_TESTMODE_Pos (0) /*!< HSUSBD_T::TEST: TESTMODE Position */
#define HSUSBD_TEST_TESTMODE_Msk (0x7ul << HSUSBD_TEST_TESTMODE_Pos) /*!< HSUSBD_T::TEST: TESTMODE Mask */
#define HSUSBD_CEPDAT_DAT_Pos (0) /*!< HSUSBD_T::CEPDAT: DAT Position */
#define HSUSBD_CEPDAT_DAT_Msk (0xfffffffful << HSUSBD_CEPDAT_DAT_Pos) /*!< HSUSBD_T::CEPDAT: DAT Mask */
#define HSUSBD_CEPCTL_NAKCLR_Pos (0) /*!< HSUSBD_T::CEPCTL: NAKCLR Position */
#define HSUSBD_CEPCTL_NAKCLR_Msk (0x1ul << HSUSBD_CEPCTL_NAKCLR_Pos) /*!< HSUSBD_T::CEPCTL: NAKCLR Mask */
#define HSUSBD_CEPCTL_STALLEN_Pos (1) /*!< HSUSBD_T::CEPCTL: STALLEN Position */
#define HSUSBD_CEPCTL_STALLEN_Msk (0x1ul << HSUSBD_CEPCTL_STALLEN_Pos) /*!< HSUSBD_T::CEPCTL: STALLEN Mask */
#define HSUSBD_CEPCTL_ZEROLEN_Pos (2) /*!< HSUSBD_T::CEPCTL: ZEROLEN Position */
#define HSUSBD_CEPCTL_ZEROLEN_Msk (0x1ul << HSUSBD_CEPCTL_ZEROLEN_Pos) /*!< HSUSBD_T::CEPCTL: ZEROLEN Mask */
#define HSUSBD_CEPCTL_FLUSH_Pos (3) /*!< HSUSBD_T::CEPCTL: FLUSH Position */
#define HSUSBD_CEPCTL_FLUSH_Msk (0x1ul << HSUSBD_CEPCTL_FLUSH_Pos) /*!< HSUSBD_T::CEPCTL: FLUSH Mask */
#define HSUSBD_CEPINTEN_SETUPTKIEN_Pos (0) /*!< HSUSBD_T::CEPINTEN: SETUPTKIEN Position*/
#define HSUSBD_CEPINTEN_SETUPTKIEN_Msk (0x1ul << HSUSBD_CEPINTEN_SETUPTKIEN_Pos) /*!< HSUSBD_T::CEPINTEN: SETUPTKIEN Mask */
#define HSUSBD_CEPINTEN_SETUPPKIEN_Pos (1) /*!< HSUSBD_T::CEPINTEN: SETUPPKIEN Position*/
#define HSUSBD_CEPINTEN_SETUPPKIEN_Msk (0x1ul << HSUSBD_CEPINTEN_SETUPPKIEN_Pos) /*!< HSUSBD_T::CEPINTEN: SETUPPKIEN Mask */
#define HSUSBD_CEPINTEN_OUTTKIEN_Pos (2) /*!< HSUSBD_T::CEPINTEN: OUTTKIEN Position */
#define HSUSBD_CEPINTEN_OUTTKIEN_Msk (0x1ul << HSUSBD_CEPINTEN_OUTTKIEN_Pos) /*!< HSUSBD_T::CEPINTEN: OUTTKIEN Mask */
#define HSUSBD_CEPINTEN_INTKIEN_Pos (3) /*!< HSUSBD_T::CEPINTEN: INTKIEN Position */
#define HSUSBD_CEPINTEN_INTKIEN_Msk (0x1ul << HSUSBD_CEPINTEN_INTKIEN_Pos) /*!< HSUSBD_T::CEPINTEN: INTKIEN Mask */
#define HSUSBD_CEPINTEN_PINGIEN_Pos (4) /*!< HSUSBD_T::CEPINTEN: PINGIEN Position */
#define HSUSBD_CEPINTEN_PINGIEN_Msk (0x1ul << HSUSBD_CEPINTEN_PINGIEN_Pos) /*!< HSUSBD_T::CEPINTEN: PINGIEN Mask */
#define HSUSBD_CEPINTEN_TXPKIEN_Pos (5) /*!< HSUSBD_T::CEPINTEN: TXPKIEN Position */
#define HSUSBD_CEPINTEN_TXPKIEN_Msk (0x1ul << HSUSBD_CEPINTEN_TXPKIEN_Pos) /*!< HSUSBD_T::CEPINTEN: TXPKIEN Mask */
#define HSUSBD_CEPINTEN_RXPKIEN_Pos (6) /*!< HSUSBD_T::CEPINTEN: RXPKIEN Position */
#define HSUSBD_CEPINTEN_RXPKIEN_Msk (0x1ul << HSUSBD_CEPINTEN_RXPKIEN_Pos) /*!< HSUSBD_T::CEPINTEN: RXPKIEN Mask */
#define HSUSBD_CEPINTEN_NAKIEN_Pos (7) /*!< HSUSBD_T::CEPINTEN: NAKIEN Position */
#define HSUSBD_CEPINTEN_NAKIEN_Msk (0x1ul << HSUSBD_CEPINTEN_NAKIEN_Pos) /*!< HSUSBD_T::CEPINTEN: NAKIEN Mask */
#define HSUSBD_CEPINTEN_STALLIEN_Pos (8) /*!< HSUSBD_T::CEPINTEN: STALLIEN Position */
#define HSUSBD_CEPINTEN_STALLIEN_Msk (0x1ul << HSUSBD_CEPINTEN_STALLIEN_Pos) /*!< HSUSBD_T::CEPINTEN: STALLIEN Mask */
#define HSUSBD_CEPINTEN_ERRIEN_Pos (9) /*!< HSUSBD_T::CEPINTEN: ERRIEN Position */
#define HSUSBD_CEPINTEN_ERRIEN_Msk (0x1ul << HSUSBD_CEPINTEN_ERRIEN_Pos) /*!< HSUSBD_T::CEPINTEN: ERRIEN Mask */
#define HSUSBD_CEPINTEN_STSDONEIEN_Pos (10) /*!< HSUSBD_T::CEPINTEN: STSDONEIEN Position*/
#define HSUSBD_CEPINTEN_STSDONEIEN_Msk (0x1ul << HSUSBD_CEPINTEN_STSDONEIEN_Pos) /*!< HSUSBD_T::CEPINTEN: STSDONEIEN Mask */
#define HSUSBD_CEPINTEN_BUFFULLIEN_Pos (11) /*!< HSUSBD_T::CEPINTEN: BUFFULLIEN Position*/
#define HSUSBD_CEPINTEN_BUFFULLIEN_Msk (0x1ul << HSUSBD_CEPINTEN_BUFFULLIEN_Pos) /*!< HSUSBD_T::CEPINTEN: BUFFULLIEN Mask */
#define HSUSBD_CEPINTEN_BUFEMPTYIEN_Pos (12) /*!< HSUSBD_T::CEPINTEN: BUFEMPTYIEN Position*/
#define HSUSBD_CEPINTEN_BUFEMPTYIEN_Msk (0x1ul << HSUSBD_CEPINTEN_BUFEMPTYIEN_Pos) /*!< HSUSBD_T::CEPINTEN: BUFEMPTYIEN Mask */
#define HSUSBD_CEPINTSTS_SETUPTKIF_Pos (0) /*!< HSUSBD_T::CEPINTSTS: SETUPTKIF Position*/
#define HSUSBD_CEPINTSTS_SETUPTKIF_Msk (0x1ul << HSUSBD_CEPINTSTS_SETUPTKIF_Pos) /*!< HSUSBD_T::CEPINTSTS: SETUPTKIF Mask */
#define HSUSBD_CEPINTSTS_SETUPPKIF_Pos (1) /*!< HSUSBD_T::CEPINTSTS: SETUPPKIF Position*/
#define HSUSBD_CEPINTSTS_SETUPPKIF_Msk (0x1ul << HSUSBD_CEPINTSTS_SETUPPKIF_Pos) /*!< HSUSBD_T::CEPINTSTS: SETUPPKIF Mask */
#define HSUSBD_CEPINTSTS_OUTTKIF_Pos (2) /*!< HSUSBD_T::CEPINTSTS: OUTTKIF Position */
#define HSUSBD_CEPINTSTS_OUTTKIF_Msk (0x1ul << HSUSBD_CEPINTSTS_OUTTKIF_Pos) /*!< HSUSBD_T::CEPINTSTS: OUTTKIF Mask */
#define HSUSBD_CEPINTSTS_INTKIF_Pos (3) /*!< HSUSBD_T::CEPINTSTS: INTKIF Position */
#define HSUSBD_CEPINTSTS_INTKIF_Msk (0x1ul << HSUSBD_CEPINTSTS_INTKIF_Pos) /*!< HSUSBD_T::CEPINTSTS: INTKIF Mask */
#define HSUSBD_CEPINTSTS_PINGIF_Pos (4) /*!< HSUSBD_T::CEPINTSTS: PINGIF Position */
#define HSUSBD_CEPINTSTS_PINGIF_Msk (0x1ul << HSUSBD_CEPINTSTS_PINGIF_Pos) /*!< HSUSBD_T::CEPINTSTS: PINGIF Mask */
#define HSUSBD_CEPINTSTS_TXPKIF_Pos (5) /*!< HSUSBD_T::CEPINTSTS: TXPKIF Position */
#define HSUSBD_CEPINTSTS_TXPKIF_Msk (0x1ul << HSUSBD_CEPINTSTS_TXPKIF_Pos) /*!< HSUSBD_T::CEPINTSTS: TXPKIF Mask */
#define HSUSBD_CEPINTSTS_RXPKIF_Pos (6) /*!< HSUSBD_T::CEPINTSTS: RXPKIF Position */
#define HSUSBD_CEPINTSTS_RXPKIF_Msk (0x1ul << HSUSBD_CEPINTSTS_RXPKIF_Pos) /*!< HSUSBD_T::CEPINTSTS: RXPKIF Mask */
#define HSUSBD_CEPINTSTS_NAKIF_Pos (7) /*!< HSUSBD_T::CEPINTSTS: NAKIF Position */
#define HSUSBD_CEPINTSTS_NAKIF_Msk (0x1ul << HSUSBD_CEPINTSTS_NAKIF_Pos) /*!< HSUSBD_T::CEPINTSTS: NAKIF Mask */
#define HSUSBD_CEPINTSTS_STALLIF_Pos (8) /*!< HSUSBD_T::CEPINTSTS: STALLIF Position */
#define HSUSBD_CEPINTSTS_STALLIF_Msk (0x1ul << HSUSBD_CEPINTSTS_STALLIF_Pos) /*!< HSUSBD_T::CEPINTSTS: STALLIF Mask */
#define HSUSBD_CEPINTSTS_ERRIF_Pos (9) /*!< HSUSBD_T::CEPINTSTS: ERRIF Position */
#define HSUSBD_CEPINTSTS_ERRIF_Msk (0x1ul << HSUSBD_CEPINTSTS_ERRIF_Pos) /*!< HSUSBD_T::CEPINTSTS: ERRIF Mask */
#define HSUSBD_CEPINTSTS_STSDONEIF_Pos (10) /*!< HSUSBD_T::CEPINTSTS: STSDONEIF Position*/
#define HSUSBD_CEPINTSTS_STSDONEIF_Msk (0x1ul << HSUSBD_CEPINTSTS_STSDONEIF_Pos) /*!< HSUSBD_T::CEPINTSTS: STSDONEIF Mask */
#define HSUSBD_CEPINTSTS_BUFFULLIF_Pos (11) /*!< HSUSBD_T::CEPINTSTS: BUFFULLIF Position*/
#define HSUSBD_CEPINTSTS_BUFFULLIF_Msk (0x1ul << HSUSBD_CEPINTSTS_BUFFULLIF_Pos) /*!< HSUSBD_T::CEPINTSTS: BUFFULLIF Mask */
#define HSUSBD_CEPINTSTS_BUFEMPTYIF_Pos (12) /*!< HSUSBD_T::CEPINTSTS: BUFEMPTYIF Position*/
#define HSUSBD_CEPINTSTS_BUFEMPTYIF_Msk (0x1ul << HSUSBD_CEPINTSTS_BUFEMPTYIF_Pos) /*!< HSUSBD_T::CEPINTSTS: BUFEMPTYIF Mask */
#define HSUSBD_CEPTXCNT_TXCNT_Pos (0) /*!< HSUSBD_T::CEPTXCNT: TXCNT Position */
#define HSUSBD_CEPTXCNT_TXCNT_Msk (0xfful << HSUSBD_CEPTXCNT_TXCNT_Pos) /*!< HSUSBD_T::CEPTXCNT: TXCNT Mask */
#define HSUSBD_CEPRXCNT_RXCNT_Pos (0) /*!< HSUSBD_T::CEPRXCNT: RXCNT Position */
#define HSUSBD_CEPRXCNT_RXCNT_Msk (0xfful << HSUSBD_CEPRXCNT_RXCNT_Pos) /*!< HSUSBD_T::CEPRXCNT: RXCNT Mask */
#define HSUSBD_CEPDATCNT_DATCNT_Pos (0) /*!< HSUSBD_T::CEPDATCNT: DATCNT Position */
#define HSUSBD_CEPDATCNT_DATCNT_Msk (0xfffful << HSUSBD_CEPDATCNT_DATCNT_Pos) /*!< HSUSBD_T::CEPDATCNT: DATCNT Mask */
#define HSUSBD_SETUP1_0_SETUP0_Pos (0) /*!< HSUSBD_T::SETUP1_0: SETUP0 Position */
#define HSUSBD_SETUP1_0_SETUP0_Msk (0xfful << HSUSBD_SETUP1_0_SETUP0_Pos) /*!< HSUSBD_T::SETUP1_0: SETUP0 Mask */
#define HSUSBD_SETUP1_0_SETUP1_Pos (8) /*!< HSUSBD_T::SETUP1_0: SETUP1 Position */
#define HSUSBD_SETUP1_0_SETUP1_Msk (0xfful << HSUSBD_SETUP1_0_SETUP1_Pos) /*!< HSUSBD_T::SETUP1_0: SETUP1 Mask */
#define HSUSBD_SETUP3_2_SETUP2_Pos (0) /*!< HSUSBD_T::SETUP3_2: SETUP2 Position */
#define HSUSBD_SETUP3_2_SETUP2_Msk (0xfful << HSUSBD_SETUP3_2_SETUP2_Pos) /*!< HSUSBD_T::SETUP3_2: SETUP2 Mask */
#define HSUSBD_SETUP3_2_SETUP3_Pos (8) /*!< HSUSBD_T::SETUP3_2: SETUP3 Position */
#define HSUSBD_SETUP3_2_SETUP3_Msk (0xfful << HSUSBD_SETUP3_2_SETUP3_Pos) /*!< HSUSBD_T::SETUP3_2: SETUP3 Mask */
#define HSUSBD_SETUP5_4_SETUP4_Pos (0) /*!< HSUSBD_T::SETUP5_4: SETUP4 Position */
#define HSUSBD_SETUP5_4_SETUP4_Msk (0xfful << HSUSBD_SETUP5_4_SETUP4_Pos) /*!< HSUSBD_T::SETUP5_4: SETUP4 Mask */
#define HSUSBD_SETUP5_4_SETUP5_Pos (8) /*!< HSUSBD_T::SETUP5_4: SETUP5 Position */
#define HSUSBD_SETUP5_4_SETUP5_Msk (0xfful << HSUSBD_SETUP5_4_SETUP5_Pos) /*!< HSUSBD_T::SETUP5_4: SETUP5 Mask */
#define HSUSBD_SETUP7_6_SETUP6_Pos (0) /*!< HSUSBD_T::SETUP7_6: SETUP6 Position */
#define HSUSBD_SETUP7_6_SETUP6_Msk (0xfful << HSUSBD_SETUP7_6_SETUP6_Pos) /*!< HSUSBD_T::SETUP7_6: SETUP6 Mask */
#define HSUSBD_SETUP7_6_SETUP7_Pos (8) /*!< HSUSBD_T::SETUP7_6: SETUP7 Position */
#define HSUSBD_SETUP7_6_SETUP7_Msk (0xfful << HSUSBD_SETUP7_6_SETUP7_Pos) /*!< HSUSBD_T::SETUP7_6: SETUP7 Mask */
#define HSUSBD_CEPBUFST_SADDR_Pos (0) /*!< HSUSBD_T::CEPBUFST: SADDR Position */
#define HSUSBD_CEPBUFST_SADDR_Msk (0xffful << HSUSBD_CEPBUFST_SADDR_Pos) /*!< HSUSBD_T::CEPBUFST: SADDR Mask */
#define HSUSBD_CEPBUFEND_EADDR_Pos (0) /*!< HSUSBD_T::CEPBUFEND: EADDR Position */
#define HSUSBD_CEPBUFEND_EADDR_Msk (0xffful << HSUSBD_CEPBUFEND_EADDR_Pos) /*!< HSUSBD_T::CEPBUFEND: EADDR Mask */
#define HSUSBD_DMACTL_EPNUM_Pos (0) /*!< HSUSBD_T::DMACTL: EPNUM Position */
#define HSUSBD_DMACTL_EPNUM_Msk (0xful << HSUSBD_DMACTL_EPNUM_Pos) /*!< HSUSBD_T::DMACTL: EPNUM Mask */
#define HSUSBD_DMACTL_DMARD_Pos (4) /*!< HSUSBD_T::DMACTL: DMARD Position */
#define HSUSBD_DMACTL_DMARD_Msk (0x1ul << HSUSBD_DMACTL_DMARD_Pos) /*!< HSUSBD_T::DMACTL: DMARD Mask */
#define HSUSBD_DMACTL_DMAEN_Pos (5) /*!< HSUSBD_T::DMACTL: DMAEN Position */
#define HSUSBD_DMACTL_DMAEN_Msk (0x1ul << HSUSBD_DMACTL_DMAEN_Pos) /*!< HSUSBD_T::DMACTL: DMAEN Mask */
#define HSUSBD_DMACTL_SGEN_Pos (6) /*!< HSUSBD_T::DMACTL: SGEN Position */
#define HSUSBD_DMACTL_SGEN_Msk (0x1ul << HSUSBD_DMACTL_SGEN_Pos) /*!< HSUSBD_T::DMACTL: SGEN Mask */
#define HSUSBD_DMACTL_DMARST_Pos (7) /*!< HSUSBD_T::DMACTL: DMARST Position */
#define HSUSBD_DMACTL_DMARST_Msk (0x1ul << HSUSBD_DMACTL_DMARST_Pos) /*!< HSUSBD_T::DMACTL: DMARST Mask */
#define HSUSBD_DMACTL_SVINEP_Pos (8) /*!< HSUSBD_T::DMACTL: SVINEP Position */
#define HSUSBD_DMACTL_SVINEP_Msk (0x1ul << HSUSBD_DMACTL_SVINEP_Pos) /*!< HSUSBD_T::DMACTL: SVINEP Mask */
#define HSUSBD_DMACNT_DMACNT_Pos (0) /*!< HSUSBD_T::DMACNT: DMACNT Position */
#define HSUSBD_DMACNT_DMACNT_Msk (0xffffful << HSUSBD_DMACNT_DMACNT_Pos) /*!< HSUSBD_T::DMACNT: DMACNT Mask */
#define HSUSBD_EPDAT_EPDAT_Pos (0) /*!< HSUSBD_T::EPDAT: EPDAT Position */
#define HSUSBD_EPDAT_EPDAT_Msk (0xfffffffful << HSUSBD_EPDAT_EPDAT_Pos) /*!< HSUSBD_T::EPDAT: EPDAT Mask */
#define HSUSBD_EPINTSTS_BUFFULLIF_Pos (0) /*!< HSUSBD_T::EPINTSTS: BUFFULLIF Position */
#define HSUSBD_EPINTSTS_BUFFULLIF_Msk (0x1ul << HSUSBD_EPINTSTS_BUFFULLIF_Pos) /*!< HSUSBD_T::EPINTSTS: BUFFULLIF Mask */
#define HSUSBD_EPINTSTS_BUFEMPTYIF_Pos (1) /*!< HSUSBD_T::EPINTSTS: BUFEMPTYIF Position*/
#define HSUSBD_EPINTSTS_BUFEMPTYIF_Msk (0x1ul << HSUSBD_EPINTSTS_BUFEMPTYIF_Pos) /*!< HSUSBD_T::EPINTSTS: BUFEMPTYIF Mask */
#define HSUSBD_EPINTSTS_SHORTTXIF_Pos (2) /*!< HSUSBD_T::EPINTSTS: SHORTTXIF Position */
#define HSUSBD_EPINTSTS_SHORTTXIF_Msk (0x1ul << HSUSBD_EPINTSTS_SHORTTXIF_Pos) /*!< HSUSBD_T::EPINTSTS: SHORTTXIF Mask */
#define HSUSBD_EPINTSTS_TXPKIF_Pos (3) /*!< HSUSBD_T::EPINTSTS: TXPKIF Position */
#define HSUSBD_EPINTSTS_TXPKIF_Msk (0x1ul << HSUSBD_EPINTSTS_TXPKIF_Pos) /*!< HSUSBD_T::EPINTSTS: TXPKIF Mask */
#define HSUSBD_EPINTSTS_RXPKIF_Pos (4) /*!< HSUSBD_T::EPINTSTS: RXPKIF Position */
#define HSUSBD_EPINTSTS_RXPKIF_Msk (0x1ul << HSUSBD_EPINTSTS_RXPKIF_Pos) /*!< HSUSBD_T::EPINTSTS: RXPKIF Mask */
#define HSUSBD_EPINTSTS_OUTTKIF_Pos (5) /*!< HSUSBD_T::EPINTSTS: OUTTKIF Position */
#define HSUSBD_EPINTSTS_OUTTKIF_Msk (0x1ul << HSUSBD_EPINTSTS_OUTTKIF_Pos) /*!< HSUSBD_T::EPINTSTS: OUTTKIF Mask */
#define HSUSBD_EPINTSTS_INTKIF_Pos (6) /*!< HSUSBD_T::EPINTSTS: INTKIF Position */
#define HSUSBD_EPINTSTS_INTKIF_Msk (0x1ul << HSUSBD_EPINTSTS_INTKIF_Pos) /*!< HSUSBD_T::EPINTSTS: INTKIF Mask */
#define HSUSBD_EPINTSTS_PINGIF_Pos (7) /*!< HSUSBD_T::EPINTSTS: PINGIF Position */
#define HSUSBD_EPINTSTS_PINGIF_Msk (0x1ul << HSUSBD_EPINTSTS_PINGIF_Pos) /*!< HSUSBD_T::EPINTSTS: PINGIF Mask */
#define HSUSBD_EPINTSTS_NAKIF_Pos (8) /*!< HSUSBD_T::EPINTSTS: NAKIF Position */
#define HSUSBD_EPINTSTS_NAKIF_Msk (0x1ul << HSUSBD_EPINTSTS_NAKIF_Pos) /*!< HSUSBD_T::EPINTSTS: NAKIF Mask */
#define HSUSBD_EPINTSTS_STALLIF_Pos (9) /*!< HSUSBD_T::EPINTSTS: STALLIF Position */
#define HSUSBD_EPINTSTS_STALLIF_Msk (0x1ul << HSUSBD_EPINTSTS_STALLIF_Pos) /*!< HSUSBD_T::EPINTSTS: STALLIF Mask */
#define HSUSBD_EPINTSTS_NYETIF_Pos (10) /*!< HSUSBD_T::EPINTSTS: NYETIF Position */
#define HSUSBD_EPINTSTS_NYETIF_Msk (0x1ul << HSUSBD_EPINTSTS_NYETIF_Pos) /*!< HSUSBD_T::EPINTSTS: NYETIF Mask */
#define HSUSBD_EPINTSTS_ERRIF_Pos (11) /*!< HSUSBD_T::EPINTSTS: ERRIF Position */
#define HSUSBD_EPINTSTS_ERRIF_Msk (0x1ul << HSUSBD_EPINTSTS_ERRIF_Pos) /*!< HSUSBD_T::EPINTSTS: ERRIF Mask */
#define HSUSBD_EPINTSTS_SHORTRXIF_Pos (12) /*!< HSUSBD_T::EPINTSTS: SHORTRXIF Position */
#define HSUSBD_EPINTSTS_SHORTRXIF_Msk (0x1ul << HSUSBD_EPINTSTS_SHORTRXIF_Pos) /*!< HSUSBD_T::EPINTSTS: SHORTRXIF Mask */
#define HSUSBD_EPINTEN_BUFFULLIEN_Pos (0) /*!< HSUSBD_T::EPINTEN: BUFFULLIEN Position */
#define HSUSBD_EPINTEN_BUFFULLIEN_Msk (0x1ul << HSUSBD_EPINTEN_BUFFULLIEN_Pos) /*!< HSUSBD_T::EPINTEN: BUFFULLIEN Mask */
#define HSUSBD_EPINTEN_BUFEMPTYIEN_Pos (1) /*!< HSUSBD_T::EPINTEN: BUFEMPTYIEN Position*/
#define HSUSBD_EPINTEN_BUFEMPTYIEN_Msk (0x1ul << HSUSBD_EPINTEN_BUFEMPTYIEN_Pos) /*!< HSUSBD_T::EPINTEN: BUFEMPTYIEN Mask */
#define HSUSBD_EPINTEN_SHORTTXIEN_Pos (2) /*!< HSUSBD_T::EPINTEN: SHORTTXIEN Position */
#define HSUSBD_EPINTEN_SHORTTXIEN_Msk (0x1ul << HSUSBD_EPINTEN_SHORTTXIEN_Pos) /*!< HSUSBD_T::EPINTEN: SHORTTXIEN Mask */
#define HSUSBD_EPINTEN_TXPKIEN_Pos (3) /*!< HSUSBD_T::EPINTEN: TXPKIEN Position */
#define HSUSBD_EPINTEN_TXPKIEN_Msk (0x1ul << HSUSBD_EPINTEN_TXPKIEN_Pos) /*!< HSUSBD_T::EPINTEN: TXPKIEN Mask */
#define HSUSBD_EPINTEN_RXPKIEN_Pos (4) /*!< HSUSBD_T::EPINTEN: RXPKIEN Position */
#define HSUSBD_EPINTEN_RXPKIEN_Msk (0x1ul << HSUSBD_EPINTEN_RXPKIEN_Pos) /*!< HSUSBD_T::EPINTEN: RXPKIEN Mask */
#define HSUSBD_EPINTEN_OUTTKIEN_Pos (5) /*!< HSUSBD_T::EPINTEN: OUTTKIEN Position */
#define HSUSBD_EPINTEN_OUTTKIEN_Msk (0x1ul << HSUSBD_EPINTEN_OUTTKIEN_Pos) /*!< HSUSBD_T::EPINTEN: OUTTKIEN Mask */
#define HSUSBD_EPINTEN_INTKIEN_Pos (6) /*!< HSUSBD_T::EPINTEN: INTKIEN Position */
#define HSUSBD_EPINTEN_INTKIEN_Msk (0x1ul << HSUSBD_EPINTEN_INTKIEN_Pos) /*!< HSUSBD_T::EPINTEN: INTKIEN Mask */
#define HSUSBD_EPINTEN_PINGIEN_Pos (7) /*!< HSUSBD_T::EPINTEN: PINGIEN Position */
#define HSUSBD_EPINTEN_PINGIEN_Msk (0x1ul << HSUSBD_EPINTEN_PINGIEN_Pos) /*!< HSUSBD_T::EPINTEN: PINGIEN Mask */
#define HSUSBD_EPINTEN_NAKIEN_Pos (8) /*!< HSUSBD_T::EPINTEN: NAKIEN Position */
#define HSUSBD_EPINTEN_NAKIEN_Msk (0x1ul << HSUSBD_EPINTEN_NAKIEN_Pos) /*!< HSUSBD_T::EPINTEN: NAKIEN Mask */
#define HSUSBD_EPINTEN_STALLIEN_Pos (9) /*!< HSUSBD_T::EPINTEN: STALLIEN Position */
#define HSUSBD_EPINTEN_STALLIEN_Msk (0x1ul << HSUSBD_EPINTEN_STALLIEN_Pos) /*!< HSUSBD_T::EPINTEN: STALLIEN Mask */
#define HSUSBD_EPINTEN_NYETIEN_Pos (10) /*!< HSUSBD_T::EPINTEN: NYETIEN Position */
#define HSUSBD_EPINTEN_NYETIEN_Msk (0x1ul << HSUSBD_EPINTEN_NYETIEN_Pos) /*!< HSUSBD_T::EPINTEN: NYETIEN Mask */
#define HSUSBD_EPINTEN_ERRIEN_Pos (11) /*!< HSUSBD_T::EPINTEN: ERRIEN Position */
#define HSUSBD_EPINTEN_ERRIEN_Msk (0x1ul << HSUSBD_EPINTEN_ERRIEN_Pos) /*!< HSUSBD_T::EPINTEN: ERRIEN Mask */
#define HSUSBD_EPINTEN_SHORTRXIEN_Pos (12) /*!< HSUSBD_T::EPINTEN: SHORTRXIEN Position */
#define HSUSBD_EPINTEN_SHORTRXIEN_Msk (0x1ul << HSUSBD_EPINTEN_SHORTRXIEN_Pos) /*!< HSUSBD_T::EPINTEN: SHORTRXIEN Mask */
#define HSUSBD_EPDATCNT_DATCNT_Pos (0) /*!< HSUSBD_T::EPDATCNT: DATCNT Position */
#define HSUSBD_EPDATCNT_DATCNT_Msk (0xfffful << HSUSBD_EPDATCNT_DATCNT_Pos) /*!< HSUSBD_T::EPDATCNT: DATCNT Mask */
#define HSUSBD_EPDATCNT_DMALOOP_Pos (16) /*!< HSUSBD_T::EPDATCNT: DMALOOP Position */
#define HSUSBD_EPDATCNT_DMALOOP_Msk (0x7ffful << HSUSBD_EPDATCNT_DMALOOP_Pos) /*!< HSUSBD_T::EPDATCNT: DMALOOP Mask */
#define HSUSBD_EPRSPCTL_FLUSH_Pos (0) /*!< HSUSBD_T::EPRSPCTL: FLUSH Position */
#define HSUSBD_EPRSPCTL_FLUSH_Msk (0x1ul << HSUSBD_EPRSPCTL_FLUSH_Pos) /*!< HSUSBD_T::EPRSPCTL: FLUSH Mask */
#define HSUSBD_EPRSPCTL_MODE_Pos (1) /*!< HSUSBD_T::EPRSPCTL: MODE Position */
#define HSUSBD_EPRSPCTL_MODE_Msk (0x3ul << HSUSBD_EPRSPCTL_MODE_Pos) /*!< HSUSBD_T::EPRSPCTL: MODE Mask */
#define HSUSBD_EPRSPCTL_TOGGLE_Pos (3) /*!< HSUSBD_T::EPRSPCTL: TOGGLE Position */
#define HSUSBD_EPRSPCTL_TOGGLE_Msk (0x1ul << HSUSBD_EPRSPCTL_TOGGLE_Pos) /*!< HSUSBD_T::EPRSPCTL: TOGGLE Mask */
#define HSUSBD_EPRSPCTL_HALT_Pos (4) /*!< HSUSBD_T::EPRSPCTL: HALT Position */
#define HSUSBD_EPRSPCTL_HALT_Msk (0x1ul << HSUSBD_EPRSPCTL_HALT_Pos) /*!< HSUSBD_T::EPRSPCTL: HALT Mask */
#define HSUSBD_EPRSPCTL_ZEROLEN_Pos (5) /*!< HSUSBD_T::EPRSPCTL: ZEROLEN Position */
#define HSUSBD_EPRSPCTL_ZEROLEN_Msk (0x1ul << HSUSBD_EPRSPCTL_ZEROLEN_Pos) /*!< HSUSBD_T::EPRSPCTL: ZEROLEN Mask */
#define HSUSBD_EPRSPCTL_SHORTTXEN_Pos (6) /*!< HSUSBD_T::EPRSPCTL: SHORTTXEN Position */
#define HSUSBD_EPRSPCTL_SHORTTXEN_Msk (0x1ul << HSUSBD_EPRSPCTL_SHORTTXEN_Pos) /*!< HSUSBD_T::EPRSPCTL: SHORTTXEN Mask */
#define HSUSBD_EPRSPCTL_DISBUF_Pos (7) /*!< HSUSBD_T::EPRSPCTL: DISBUF Position */
#define HSUSBD_EPRSPCTL_DISBUF_Msk (0x1ul << HSUSBD_EPRSPCTL_DISBUF_Pos) /*!< HSUSBD_T::EPRSPCTL: DISBUF Mask */
#define HSUSBD_EPMPS_EPMPS_Pos (0) /*!< HSUSBD_T::EPMPS: EPMPS Position */
#define HSUSBD_EPMPS_EPMPS_Msk (0x7fful << HSUSBD_EPMPS_EPMPS_Pos) /*!< HSUSBD_T::EPMPS: EPMPS Mask */
#define HSUSBD_EPTXCNT_TXCNT_Pos (0) /*!< HSUSBD_T::EPTXCNT: TXCNT Position */
#define HSUSBD_EPTXCNT_TXCNT_Msk (0x7fful << HSUSBD_EPTXCNT_TXCNT_Pos) /*!< HSUSBD_T::EPTXCNT: TXCNT Mask */
#define HSUSBD_EPCFG_EPEN_Pos (0) /*!< HSUSBD_T::EPCFG: EPEN Position */
#define HSUSBD_EPCFG_EPEN_Msk (0x1ul << HSUSBD_EPCFG_EPEN_Pos) /*!< HSUSBD_T::EPCFG: EPEN Mask */
#define HSUSBD_EPCFG_EPTYPE_Pos (1) /*!< HSUSBD_T::EPCFG: EPTYPE Position */
#define HSUSBD_EPCFG_EPTYPE_Msk (0x3ul << HSUSBD_EPCFG_EPTYPE_Pos) /*!< HSUSBD_T::EPCFG: EPTYPE Mask */
#define HSUSBD_EPCFG_EPDIR_Pos (3) /*!< HSUSBD_T::EPCFG: EPDIR Position */
#define HSUSBD_EPCFG_EPDIR_Msk (0x1ul << HSUSBD_EPCFG_EPDIR_Pos) /*!< HSUSBD_T::EPCFG: EPDIR Mask */
#define HSUSBD_EPCFG_EPNUM_Pos (4) /*!< HSUSBD_T::EPCFG: EPNUM Position */
#define HSUSBD_EPCFG_EPNUM_Msk (0xful << HSUSBD_EPCFG_EPNUM_Pos) /*!< HSUSBD_T::EPCFG: EPNUM Mask */
#define HSUSBD_EPBUFST_SADDR_Pos (0) /*!< HSUSBD_T::EPBUFST: SADDR Position */
#define HSUSBD_EPBUFST_SADDR_Msk (0xffful << HSUSBD_EPBUFST_SADDR_Pos) /*!< HSUSBD_T::EPBUFST: SADDR Mask */
#define HSUSBD_EPBUFEND_EADDR_Pos (0) /*!< HSUSBD_T::EPBUFEND: EADDR Position */
#define HSUSBD_EPBUFEND_EADDR_Msk (0xffful << HSUSBD_EPBUFEND_EADDR_Pos) /*!< HSUSBD_T::EPBUFEND: EADDR Mask */
#define HSUSBD_DMAADDR_DMAADDR_Pos (0) /*!< HSUSBD_T::DMAADDR: DMAADDR Position */
#define HSUSBD_DMAADDR_DMAADDR_Msk (0xfffffffful << HSUSBD_DMAADDR_DMAADDR_Pos) /*!< HSUSBD_T::DMAADDR: DMAADDR Mask */
#define HSUSBD_PHYCTL_DPPUEN_Pos (8) /*!< HSUSBD_T::PHYCTL: DPPUEN Position */
#define HSUSBD_PHYCTL_DPPUEN_Msk (0x1ul << HSUSBD_PHYCTL_DPPUEN_Pos) /*!< HSUSBD_T::PHYCTL: DPPUEN Mask */
#define HSUSBD_PHYCTL_PHYEN_Pos (9) /*!< HSUSBD_T::PHYCTL: PHYEN Position */
#define HSUSBD_PHYCTL_PHYEN_Msk (0x1ul << HSUSBD_PHYCTL_PHYEN_Pos) /*!< HSUSBD_T::PHYCTL: PHYEN Mask */
#define HSUSBD_PHYCTL_WKEN_Pos (24) /*!< HSUSBD_T::PHYCTL: WKEN Position */
#define HSUSBD_PHYCTL_WKEN_Msk (0x1ul << HSUSBD_PHYCTL_WKEN_Pos) /*!< HSUSBD_T::PHYCTL: WKEN Mask */
#define HSUSBD_PHYCTL_VBUSDET_Pos (31) /*!< HSUSBD_T::PHYCTL: VBUSDET Position */
#define HSUSBD_PHYCTL_VBUSDET_Msk (0x1ul << HSUSBD_PHYCTL_VBUSDET_Pos) /*!< HSUSBD_T::PHYCTL: VBUSDET Mask */
/**@}*/ /* HSUSBD_CONST */
/**@}*/ /* end of HSUSBD register group */
/*---------------------- USB Host Controller -------------------------*/
/**
@addtogroup USBH USB Host Controller(USBH)
Memory Mapped Structure for USBH Controller
@{ */
typedef struct {
/**
* @var USBH_T::HcRevision
* Offset: 0x00 Host Controller Revision Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |REV |Revision Number
* | | |Indicates the Open HCI Specification revision number implemented by the Hardware
* | | |Host Controller supports 1.1 specification.
* | | |(X.Y = XYh).
* @var USBH_T::HcControl
* Offset: 0x04 Host Controller Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1:0] |CBSR |Control Bulk Service Ratio
* | | |This specifies the service ratio between Control and Bulk EDs
* | | |Before processing any of the non-periodic lists, HC must compare the ratio specified with its internal count on how many nonempty Control EDs have been processed, in determining whether to continue serving another Control ED or switching to Bulk EDs
* | | |The internal count will be retained when crossing the frame boundary
* | | |In case of reset, HCD is responsible for restoring this
* | | |Value.
* | | |00 = Number of Control EDs over Bulk EDs served is 1:1.
* | | |01 = Number of Control EDs over Bulk EDs served is 2:1.
* | | |10 = Number of Control EDs over Bulk EDs served is 3:1.
* | | |11 = Number of Control EDs over Bulk EDs served is 4:1.
* |[2] |PLE |Periodic List Enable Bit
* | | |When set, this bit enables processing of the Periodic (interrupt and isochronous) list
* | | |The Host Controller checks this bit prior to attempting any periodic transfers in a frame.
* | | |0 = Processing of the Periodic (Interrupt and Isochronous) list after next SOF (Start-Of-Frame) Disabled.
* | | |1 = Processing of the Periodic (Interrupt and Isochronous) list in the next frame Enabled.
* | | |Note: To enable the processing of the Isochronous list, user has to set both PLE and IE (HcControl[3]) high.
* |[3] |IE |Isochronous List Enable Bit
* | | |Both ISOEn and PLE (HcControl[2]) high enables Host Controller to process the Isochronous list
* | | |Either ISOEn or PLE (HcControl[2]) is low disables Host Controller to process the Isochronous list.
* | | |0 = Processing of the Isochronous list after next SOF (Start-Of-Frame) Disabled.
* | | |1 = Processing of the Isochronous list in the next frame Enabled, if the PLE (HcControl[2]) is high, too.
* |[4] |CLE |Control List Enable Bit
* | | |0 = Processing of the Control list after next SOF (Start-Of-Frame) Disabled.
* | | |1 = Processing of the Control list in the next frame Enabled.
* |[5] |BLE |Bulk List Enable Bit
* | | |0 = Processing of the Bulk list after next SOF (Start-Of-Frame) Disabled.
* | | |1 = Processing of the Bulk list in the next frame Enabled.
* |[7:6] |HCFS |Host Controller Functional State
* | | |This field sets the Host Controller state
* | | |The Controller may force a state change from USBSUSPEND to USBRESUME after detecting resume signaling from a downstream port
* | | |States are:
* | | |00 = USBSUSPEND.
* | | |01 = USBOPERATIONAL.
* | | |10 = USBRESUME.
* | | |11 = USBRESET.
* @var USBH_T::HcCommandStatus
* Offset: 0x08 Host Controller Command Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |HCR |Host Controller Reset
* | | |This bit is set to initiate the software reset of Host Controller
* | | |This bit is cleared by the Host Controller, upon completed of the reset operation.
* | | |This bit, when set, didn't reset the Root Hub and no subsequent reset signaling be asserted to its downstream ports.
* | | |0 = Host Controller is not in software reset state.
* | | |1 = Host Controller is in software reset state.
* |[1] |CLF |Control List Filled
* | | |Set high to indicate there is an active TD on the Control List
* | | |It may be set by either software or the Host Controller and cleared by the Host Controller each time it begins processing the head of the Control List.
* | | |0 = No active TD found or Host Controller begins to process the head of the Control list.
* | | |1 = An active TD added or found on the Control list.
* |[2] |BLF |Bulk List Filled
* | | |Set high to indicate there is an active TD on the Bulk list
* | | |This bit may be set by either software or the Host Controller and cleared by the Host Controller each time it begins processing the head of the Bulk list.
* | | |0 = No active TD found or Host Controller begins to process the head of the Bulk list.
* | | |1 = An active TD added or found on the Bulk list.
* |[17:16] |SOC |Schedule Overrun Count
* | | |These bits are incremented on each scheduling overrun error
* | | |It is initialized to 00b and wraps around at 11b
* | | |This will be incremented when a scheduling overrun is detected even if SO (HcInterruptStatus[0]) has already been set.
* @var USBH_T::HcInterruptStatus
* Offset: 0x0C Host Controller Interrupt Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SO |Scheduling Overrun
* | | |Set when the List Processor determines a Schedule Overrun has occurred.
* | | |0 = Schedule Overrun didn't occur.
* | | |1 = Schedule Overrun has occurred.
* |[1] |WDH |Write Back Done Head
* | | |Set after the Host Controller has written HcDoneHead to HccaDoneHead
* | | |Further updates of the HccaDoneHead will not occur until this bit has been cleared.
* | | |0 =.Host Controller didn't update HccaDoneHead.
* | | |1 =.Host Controller has written HcDoneHead to HccaDoneHead.
* |[2] |SF |Start of Frame
* | | |Set when the Frame Management functional block signals a 'Start of Frame' event
* | | |Host Control generates a SOF token at the same time.
* | | |0 =.Not the start of a frame.
* | | |1 =.Indicate the start of a frame and Host Controller generates a SOF token.
* |[3] |RD |Resume Detected
* | | |Set when Host Controller detects resume signaling on a downstream port.
* | | |0 = No resume signaling detected on a downstream port.
* | | |1 = Resume signaling detected on a downstream port.
* |[5] |FNO |Frame Number Overflow
* | | |This bit is set when bit 15 of Frame Number changes from 1 to 0 or from 0 to 1.
* | | |0 = The bit 15 of Frame Number didn't change.
* | | |1 = The bit 15 of Frame Number changes from 1 to 0 or from 0 to 1.
* |[6] |RHSC |Root Hub Status Change
* | | |This bit is set when the content of HcRhStatus or the content of HcRhPortStatus register has changed.
* | | |0 = The content of HcRhStatus and the content of HcRhPortStatus register didn't change.
* | | |1 = The content of HcRhStatus or the content of HcRhPortStatus register has changed.
* @var USBH_T::HcInterruptEnable
* Offset: 0x10 Host Controller Interrupt Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SO |Scheduling Overrun Enable Bit
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Interrupt generation due to SO (HcInterruptStatus[0]) Enabled.
* | | |Read Operation:
* | | |0 = Interrupt generation due to SO (HcInterruptStatus[0]) Disabled.
* | | |1 = Interrupt generation due to SO (HcInterruptStatus[0]) Enabled.
* |[1] |WDH |Write Back Done Head Enable Bit
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Interrupt generation due to WDH (HcInterruptStatus[1]) Enabled.
* | | |Read Operation:
* | | |0 = Interrupt generation due to WDH (HcInterruptStatus[1]) Disabled.
* | | |1 = Interrupt generation due to WDH (HcInterruptStatus[1]) Enabled.
* |[2] |SF |Start of Frame Enable Bit
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Interrupt generation due to SF (HcInterruptStatus[2]) Enabled.
* | | |Read Operation:
* | | |0 = Interrupt generation due to SF (HcInterruptStatus[2]) Disabled.
* | | |1 = Interrupt generation due to SF (HcInterruptStatus[2]) Enabled.
* |[3] |RD |Resume Detected Enable Bit
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Interrupt generation due to RD (HcInterruptStatus[3]) Enabled.
* | | |Read Operation:
* | | |0 = Interrupt generation due to RD (HcInterruptStatus[3]) Disabled.
* | | |1 = Interrupt generation due to RD (HcInterruptStatus[3]) Enabled.
* |[5] |FNO |Frame Number Overflow Enable Bit
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Interrupt generation due to FNO (HcInterruptStatus[5]) Enabled.
* | | |Read Operation:
* | | |0 = Interrupt generation due to FNO (HcInterruptStatus[5]) Disabled.
* | | |1 = Interrupt generation due to FNO (HcInterruptStatus[5]) Enabled.
* |[6] |RHSC |Root Hub Status Change Enable Bit
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Enabled.
* | | |Read Operation:
* | | |0 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Disabled.
* | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Enabled.
* |[31] |MIE |Master Interrupt Enable Bit
* | | |This bit is a global interrupt enable
* | | |A write of '1' allows interrupts to be enabled via the specific enable bits listed above.
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Enabled if the corresponding bit in HcInterruptEnable is high.
* | | |Read Operation:
* | | |0 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Disabled even if the corresponding bit in HcInterruptEnable is high.
* | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Enabled if the corresponding bit in HcInterruptEnable is high.
* @var USBH_T::HcInterruptDisable
* Offset: 0x14 Host Controller Interrupt Disable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SO |Scheduling Overrun Disable Bit
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Interrupt generation due to SO (HcInterruptStatus[0]) Disabled.
* | | |Read Operation:
* | | |0 = Interrupt generation due to SO (HcInterruptStatus[0]) Disabled.
* | | |1 = Interrupt generation due to SO (HcInterruptStatus[0]) Enabled.
* |[1] |WDH |Write Back Done Head Disable Bit
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Interrupt generation due to WDH (HcInterruptStatus[1]) Disabled.
* | | |Read Operation:
* | | |0 = Interrupt generation due to WDH (HcInterruptStatus[1]) Disabled.
* | | |1 = Interrupt generation due to WDH (HcInterruptStatus[1]) Enabled.
* |[2] |SF |Start of Frame Disable Bit
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Interrupt generation due to SF (HcInterruptStatus[2]) Disabled.
* | | |Read Operation:
* | | |0 = Interrupt generation due to SF (HcInterruptStatus[2]) Disabled.
* | | |1 = Interrupt generation due to SF (HcInterruptStatus[2]) Enabled.
* |[3] |RD |Resume Detected Disable Bit
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Interrupt generation due to RD (HcInterruptStatus[3]) Disabled.
* | | |Read Operation:
* | | |0 = Interrupt generation due to RD (HcInterruptStatus[3]) Disabled.
* | | |1 = Interrupt generation due to RD (HcInterruptStatus[3]) Enabled.
* |[5] |FNO |Frame Number Overflow Disable Bit
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Interrupt generation due to FNO (HcInterruptStatus[5]) Disabled.
* | | |Read Operation:
* | | |0 = Interrupt generation due to FNO (HcInterruptStatus[5]) Disabled.
* | | |1 = Interrupt generation due to FNO (HcInterruptStatus[5]) Enabled.
* |[6] |RHSC |Root Hub Status Change Disable Bit
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Disabled.
* | | |Read Operation:
* | | |0 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Disabled.
* | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Enabled.
* |[31] |MIE |Master Interrupt Disable Bit
* | | |Global interrupt disable. Writing '1' to disable all interrupts.
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Disabled if the corresponding bit in HcInterruptEnable is high.
* | | |Read Operation:
* | | |0 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Disabled even if the corresponding bit in HcInterruptEnable is high.
* | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Enabled if the corresponding bit in HcInterruptEnable is high.
* @var USBH_T::HcHCCA
* Offset: 0x18 Host Controller Communication Area Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:8] |HCCA |Host Controller Communication Area
* | | |Pointer to indicate base address of the Host Controller Communication Area (HCCA).
* @var USBH_T::HcPeriodCurrentED
* Offset: 0x1C Host Controller Period Current ED Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:4] |PCED |Periodic Current ED
* | | |Pointer to indicate physical address of the current Isochronous or Interrupt Endpoint Descriptor.
* @var USBH_T::HcControlHeadED
* Offset: 0x20 Host Controller Control Head ED Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:4] |CHED |Control Head ED
* | | |Pointer to indicate physical address of the first Endpoint Descriptor of the Control list.
* @var USBH_T::HcControlCurrentED
* Offset: 0x24 Host Controller Control Current ED Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:4] |CCED |Control Current Head ED
* | | |Pointer to indicate the physical address of the current Endpoint Descriptor of the Control list.
* @var USBH_T::HcBulkHeadED
* Offset: 0x28 Host Controller Bulk Head ED Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:4] |BHED |Bulk Head ED
* | | |Pointer to indicate the physical address of the first Endpoint Descriptor of the Bulk list.
* @var USBH_T::HcBulkCurrentED
* Offset: 0x2C Host Controller Bulk Current ED Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:4] |BCED |Bulk Current Head ED
* | | |Pointer to indicate the physical address of the current endpoint of the Bulk list.
* @var USBH_T::HcDoneHead
* Offset: 0x30 Host Controller Done Head Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:4] |DH |Done Head
* | | |Pointer to indicate the physical address of the last completed Transfer Descriptor that was added to the Done queue.
* @var USBH_T::HcFmInterval
* Offset: 0x34 Host Controller Frame Interval Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[13:0] |FI |Frame Interval
* | | |This field specifies the length of a frame as (bit times - 1)
* | | |For 12,000 bit times in a frame, a value of 11,999 is stored here.
* |[30:16] |FSMPS |FS Largest Data Packet
* | | |This field specifies a value that is loaded into the Largest Data Packet Counter at the beginning of each frame.
* |[31] |FIT |Frame Interval Toggle
* | | |This bit is toggled by Host Controller Driver when it loads a new value into FI (HcFmInterval[13:0]).
* | | |0 = Host Controller Driver didn't load new value into FI (HcFmInterval[13:0]).
* | | |1 = Host Controller Driver loads a new value into FI (HcFmInterval[13:0]).
* @var USBH_T::HcFmRemaining
* Offset: 0x38 Host Controller Frame Remaining Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[13:0] |FR |Frame Remaining
* | | |When the Host Controller is in the USBOPERATIONAL state, this 14-bit field decrements each 12 MHz clock period
* | | |When the count reaches 0, (end of frame) the counter reloads with Frame Interval
* | | |In addition, the counter loads when the Host Controller transitions into USBOPERATIONAL.
* |[31] |FRT |Frame Remaining Toggle
* | | |This bit is loaded from the FIT (HcFmInterval[31]) whenever FR (HcFmRemaining[13:0]) reaches 0.
* @var USBH_T::HcFmNumber
* Offset: 0x3C Host Controller Frame Number Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |FN |Frame Number
* | | |This 16-bit incrementing counter field is incremented coincident with the re-load of FR (HcFmRemaining[13:0])
* | | |The count rolls over from 'FFFFh' to '0h.'
* @var USBH_T::HcPeriodicStart
* Offset: 0x40 Host Controller Periodic Start Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[13:0] |PS |Periodic Start
* | | |This field contains a value used by the List Processor to determine where in a frame the Periodic List processing must begin.
* @var USBH_T::HcLSThreshold
* Offset: 0x44 Host Controller Low-speed Threshold Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[11:0] |LST |Low-speed Threshold
* | | |This field contains a value which is compared to the FR (HcFmRemaining[13:0]) field prior to initiating a Low-speed transaction
* | | |The transaction is started only if FR (HcFmRemaining[13:0]) >= this field
* | | |The value is calculated by Host Controller Driver with the consideration of transmission and setup overhead.
* @var USBH_T::HcRhDescriptorA
* Offset: 0x48 Host Controller Root Hub Descriptor A Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |NDP |Number Downstream Ports
* | | |USB host control supports two downstream ports and only one port is available in this series of chip.
* |[8] |PSM |Power Switching Mode
* | | |This bit is used to specify how the power switching of the Root Hub ports is controlled.
* | | |0 = Global Switching.
* | | |1 = Individual Switching.
* |[11] |OCPM |over Current Protection Mode
* | | |This bit describes how the over current status for the Root Hub ports reported
* | | |This bit is only valid when NOCP (HcRhDescriptorA[12]) is cleared.
* | | |0 = Global Over current.
* | | |1 = Individual Over current.
* |[12] |NOCP |No over Current Protection
* | | |This bit describes how the over current status for the Root Hub ports reported.
* | | |0 = Over current status is reported.
* | | |1 = Over current status is not reported.
* @var USBH_T::HcRhDescriptorB
* Offset: 0x4C Host Controller Root Hub Descriptor B Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:16] |PPCM |Port Power Control Mask
* | | |Global power switching
* | | |This field is only valid if PowerSwitchingMode is set (individual port switching)
* | | |When set, the port only responds to individual port power switching commands (Set/ClearPortPower)
* | | |When cleared, the port only responds to global power switching commands (Set/ClearGlobalPower).
* | | |0 = Port power controlled by global power switching.
* | | |1 = Port power controlled by port power switching.
* | | |Note: PPCM[15:2] and PPCM[0] are reserved.
* @var USBH_T::HcRhStatus
* Offset: 0x50 Host Controller Root Hub Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |LPS |Clear Global Power
* | | |In global power mode (PSM (HcRhDescriptorA[8]) = 0), this bit is written to one to clear all ports' power.
* | | |This bit always read as zero.
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Clear global power.
* |[1] |OCI |over Current Indicator
* | | |This bit reflects the state of the over current status pin
* | | |This field is only valid if NOCP (HcRhDesA[12]) and OCPM (HcRhDesA[11]) are cleared.
* | | |0 = No over current condition.
* | | |1 = Over current condition.
* |[15] |DRWE |Device Remote Wakeup Enable Bit
* | | |This bit controls if port's Connect Status Change as a remote wake-up event.
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Connect Status Change as a remote wake-up event Enabled.
* | | |Read Operation:
* | | |0 = Connect Status Change as a remote wake-up event Disabled.
* | | |1 = Connect Status Change as a remote wake-up event Enabled.
* |[16] |LPSC |Set Global Power
* | | |In global power mode (PSM (HcRhDescriptorA[8]) = 0), this bit is written to one to enable power to all ports.
* | | |This bit always read as zero.
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Set global power.
* |[17] |OCIC |over Current Indicator Change
* | | |This bit is set by hardware when a change has occurred in OCI (HcRhStatus[1]).
* | | |Write 1 to clear this bit to zero.
* | | |0 = OCI (HcRhStatus[1]) didn't change.
* | | |1 = OCI (HcRhStatus[1]) change.
* |[31] |CRWE |Clear Remote Wake-up Enable Bit
* | | |This bit is use to clear DRWE (HcRhStatus[15]).
* | | |This bit always read as zero.
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Clear DRWE (HcRhStatus[15]).
* @var USBH_T::HcRhPortStatus[2]
* Offset: 0x54 Host Controller Root Hub Port Status
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CCS |CurrentConnectStatus (Read) or ClearPortEnable Bit (Write)
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Clear port enable.
* | | |Read Operation:
* | | |0 = No device connected.
* | | |1 = Device connected.
* |[1] |PES |Port Enable Status
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Set port enable.
* | | |Read Operation:
* | | |0 = Port Disabled.
* | | |1 = Port Enabled.
* |[2] |PSS |Port Suspend Status
* | | |This bit indicates the port is suspended
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Set port suspend.
* | | |Read Operation:
* | | |0 = Port is not suspended.
* | | |1 = Port is selectively suspended.
* |[3] |POCI |Port over Current Indicator (Read) or Clear Port Suspend (Write)
* | | |This bit reflects the state of the over current status pin dedicated to this port
* | | |This field is only valid if NOCP (HcRhDescriptorA[12]) is cleared and OCPM (HcRhDescriptorA[11]) is set.
* | | |This bit is also used to initiate the selective result sequence for the port.
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Clear port suspend.
* | | |Read Operation:
* | | |0 = No over current condition.
* | | |1 = Over current condition.
* |[4] |PRS |Port Reset Status
* | | |This bit reflects the reset state of the port.
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Set port reset.
* | | |Read Operation
* | | |0 = Port reset signal is not active.
* | | |1 = Port reset signal is active.
* |[8] |PPS |Port Power Status
* | | |This bit reflects the power state of the port regardless of the power switching mode.
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Port Power Enabled.
* | | |Read Operation:
* | | |0 = Port power is Disabled.
* | | |1 = Port power is Enabled.
* |[9] |LSDA |Low Speed Device Attached (Read) or Clear Port Power (Write)
* | | |This bit defines the speed (and bud idle) of the attached device
* | | |It is only valid when CCS (HcRhPortStatus1[0]) is set.
* | | |This bit is also used to clear port power.
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Clear PPS (HcRhPortStatus1[8]).
* | | |Read Operation:
* | | |0 = Full Speed device.
* | | |1 = Low-speed device.
* |[16] |CSC |Connect Status Change
* | | |This bit indicates connect or disconnect event has been detected (CCS (HcRhPortStatus1[0]) changed).
* | | |Write 1 to clear this bit to zero.
* | | |0 = No connect/disconnect event (CCS (HcRhPortStatus1[0]) didn't change).
* | | |1 = Hardware detection of connect/disconnect event (CCS (HcRhPortStatus1[0]) changed).
* |[17] |PESC |Port Enable Status Change
* | | |This bit indicates that the port has been disabled (PES (HcRhPortStatus1[1]) cleared) due to a hardware event.
* | | |Write 1 to clear this bit to zero.
* | | |0 = PES (HcRhPortStatus1[1]) didn't change.
* | | |1 = PES (HcRhPortStatus1[1]) changed.
* |[18] |PSSC |Port Suspend Status Change
* | | |This bit indicates the completion of the selective resume sequence for the port.
* | | |Write 1 to clear this bit to zero.
* | | |0 = Port resume is not completed.
* | | |1 = Port resume completed.
* |[19] |OCIC |Port over Current Indicator Change
* | | |This bit is set when POCI (HcRhPortStatus1[3]) changes.
* | | |Write 1 to clear this bit to zero.
* | | |0 = POCI (HcRhPortStatus1[3]) didn't change.
* | | |1 = POCI (HcRhPortStatus1[3]) changes.
* |[20] |PRSC |Port Reset Status Change
* | | |This bit indicates that the port reset signal has completed.
* | | |Write 1 to clear this bit to zero.
* | | |0 = Port reset is not complete.
* | | |1 = Port reset is complete.
* @var USBH_T::HcPhyControl
* Offset: 0x200 Host Controller PHY Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[27] |STBYEN |USB Transceiver Standby Enable Bit
* | | |This bit controls if USB transceiver could enter the standby mode to reduce power consumption.
* | | |0 = The USB transceiver would never enter the standby mode.
* | | |1 = The USB transceiver will enter standby mode while port is in power off state (port power is inactive).
* @var USBH_T::HcMiscControl
* Offset: 0x204 Host Controller Miscellaneous Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1] |ABORT |AHB Bus ERROR Response
* | | |This bit indicates there is an ERROR response received in AHB bus.
* | | |0 = No ERROR response received.
* | | |1 = ERROR response received.
* |[3] |OCAL |over Current Active Low
* | | |This bit controls the polarity of over current flag from external power IC.
* | | |0 = Over current flag is high active.
* | | |1 = Over current flag is low active.
* |[16] |DPRT1 |Disable Port 1
* | | |This bit controls if the connection between USB host controller and transceiver of port 1 is disabled
* | | |If the connection is disabled, the USB host controller will not recognize any event of USB bus.
* | | |Set this bit high, the transceiver of port 1 will also be forced into the standby mode no matter what USB host controller operation is.
* | | |0 = The connection between USB host controller and transceiver of port 1 Enabled.
* | | |1 = The connection between USB host controller and transceiver of port 1 Disabled and the transceiver of port 1 will also be forced into the standby mode.
*/
__I uint32_t HcRevision; /*!< [0x0000] Host Controller Revision Register */
__IO uint32_t HcControl; /*!< [0x0004] Host Controller Control Register */
__IO uint32_t HcCommandStatus; /*!< [0x0008] Host Controller Command Status Register */
__IO uint32_t HcInterruptStatus; /*!< [0x000c] Host Controller Interrupt Status Register */
__IO uint32_t HcInterruptEnable; /*!< [0x0010] Host Controller Interrupt Enable Register */
__IO uint32_t HcInterruptDisable; /*!< [0x0014] Host Controller Interrupt Disable Register */
__IO uint32_t HcHCCA; /*!< [0x0018] Host Controller Communication Area Register */
__IO uint32_t HcPeriodCurrentED; /*!< [0x001c] Host Controller Period Current ED Register */
__IO uint32_t HcControlHeadED; /*!< [0x0020] Host Controller Control Head ED Register */
__IO uint32_t HcControlCurrentED; /*!< [0x0024] Host Controller Control Current ED Register */
__IO uint32_t HcBulkHeadED; /*!< [0x0028] Host Controller Bulk Head ED Register */
__IO uint32_t HcBulkCurrentED; /*!< [0x002c] Host Controller Bulk Current ED Register */
__IO uint32_t HcDoneHead; /*!< [0x0030] Host Controller Done Head Register */
__IO uint32_t HcFmInterval; /*!< [0x0034] Host Controller Frame Interval Register */
__I uint32_t HcFmRemaining; /*!< [0x0038] Host Controller Frame Remaining Register */
__I uint32_t HcFmNumber; /*!< [0x003c] Host Controller Frame Number Register */
__IO uint32_t HcPeriodicStart; /*!< [0x0040] Host Controller Periodic Start Register */
__IO uint32_t HcLSThreshold; /*!< [0x0044] Host Controller Low-speed Threshold Register */
__IO uint32_t HcRhDescriptorA; /*!< [0x0048] Host Controller Root Hub Descriptor A Register */
__IO uint32_t HcRhDescriptorB; /*!< [0x004c] Host Controller Root Hub Descriptor B Register */
__IO uint32_t HcRhStatus; /*!< [0x0050] Host Controller Root Hub Status Register */
__IO uint32_t HcRhPortStatus[2]; /*!< [0x0054] Host Controller Root Hub Port Status [1] */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE0[105];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t HcPhyControl; /*!< [0x0200] Host Controller PHY Control Register */
__IO uint32_t HcMiscControl; /*!< [0x0204] Host Controller Miscellaneous Control Register */
} USBH_T;
/**
@addtogroup USBH_CONST USBH Bit Field Definition
Constant Definitions for USBH Controller
@{ */
#define USBH_HcRevision_REV_Pos (0) /*!< USBH_T::HcRevision: REV Position */
#define USBH_HcRevision_REV_Msk (0xfful << USBH_HcRevision_REV_Pos) /*!< USBH_T::HcRevision: REV Mask */
#define USBH_HcControl_CBSR_Pos (0) /*!< USBH_T::HcControl: CBSR Position */
#define USBH_HcControl_CBSR_Msk (0x3ul << USBH_HcControl_CBSR_Pos) /*!< USBH_T::HcControl: CBSR Mask */
#define USBH_HcControl_PLE_Pos (2) /*!< USBH_T::HcControl: PLE Position */
#define USBH_HcControl_PLE_Msk (0x1ul << USBH_HcControl_PLE_Pos) /*!< USBH_T::HcControl: PLE Mask */
#define USBH_HcControl_IE_Pos (3) /*!< USBH_T::HcControl: IE Position */
#define USBH_HcControl_IE_Msk (0x1ul << USBH_HcControl_IE_Pos) /*!< USBH_T::HcControl: IE Mask */
#define USBH_HcControl_CLE_Pos (4) /*!< USBH_T::HcControl: CLE Position */
#define USBH_HcControl_CLE_Msk (0x1ul << USBH_HcControl_CLE_Pos) /*!< USBH_T::HcControl: CLE Mask */
#define USBH_HcControl_BLE_Pos (5) /*!< USBH_T::HcControl: BLE Position */
#define USBH_HcControl_BLE_Msk (0x1ul << USBH_HcControl_BLE_Pos) /*!< USBH_T::HcControl: BLE Mask */
#define USBH_HcControl_HCFS_Pos (6) /*!< USBH_T::HcControl: HCFS Position */
#define USBH_HcControl_HCFS_Msk (0x3ul << USBH_HcControl_HCFS_Pos) /*!< USBH_T::HcControl: HCFS Mask */
#define USBH_HcCommandStatus_HCR_Pos (0) /*!< USBH_T::HcCommandStatus: HCR Position */
#define USBH_HcCommandStatus_HCR_Msk (0x1ul << USBH_HcCommandStatus_HCR_Pos) /*!< USBH_T::HcCommandStatus: HCR Mask */
#define USBH_HcCommandStatus_CLF_Pos (1) /*!< USBH_T::HcCommandStatus: CLF Position */
#define USBH_HcCommandStatus_CLF_Msk (0x1ul << USBH_HcCommandStatus_CLF_Pos) /*!< USBH_T::HcCommandStatus: CLF Mask */
#define USBH_HcCommandStatus_BLF_Pos (2) /*!< USBH_T::HcCommandStatus: BLF Position */
#define USBH_HcCommandStatus_BLF_Msk (0x1ul << USBH_HcCommandStatus_BLF_Pos) /*!< USBH_T::HcCommandStatus: BLF Mask */
#define USBH_HcCommandStatus_SOC_Pos (16) /*!< USBH_T::HcCommandStatus: SOC Position */
#define USBH_HcCommandStatus_SOC_Msk (0x3ul << USBH_HcCommandStatus_SOC_Pos) /*!< USBH_T::HcCommandStatus: SOC Mask */
#define USBH_HcInterruptStatus_SO_Pos (0) /*!< USBH_T::HcInterruptStatus: SO Position */
#define USBH_HcInterruptStatus_SO_Msk (0x1ul << USBH_HcInterruptStatus_SO_Pos) /*!< USBH_T::HcInterruptStatus: SO Mask */
#define USBH_HcInterruptStatus_WDH_Pos (1) /*!< USBH_T::HcInterruptStatus: WDH Position*/
#define USBH_HcInterruptStatus_WDH_Msk (0x1ul << USBH_HcInterruptStatus_WDH_Pos) /*!< USBH_T::HcInterruptStatus: WDH Mask */
#define USBH_HcInterruptStatus_SF_Pos (2) /*!< USBH_T::HcInterruptStatus: SF Position */
#define USBH_HcInterruptStatus_SF_Msk (0x1ul << USBH_HcInterruptStatus_SF_Pos) /*!< USBH_T::HcInterruptStatus: SF Mask */
#define USBH_HcInterruptStatus_RD_Pos (3) /*!< USBH_T::HcInterruptStatus: RD Position */
#define USBH_HcInterruptStatus_RD_Msk (0x1ul << USBH_HcInterruptStatus_RD_Pos) /*!< USBH_T::HcInterruptStatus: RD Mask */
#define USBH_HcInterruptStatus_FNO_Pos (5) /*!< USBH_T::HcInterruptStatus: FNO Position*/
#define USBH_HcInterruptStatus_FNO_Msk (0x1ul << USBH_HcInterruptStatus_FNO_Pos) /*!< USBH_T::HcInterruptStatus: FNO Mask */
#define USBH_HcInterruptStatus_RHSC_Pos (6) /*!< USBH_T::HcInterruptStatus: RHSC Position*/
#define USBH_HcInterruptStatus_RHSC_Msk (0x1ul << USBH_HcInterruptStatus_RHSC_Pos) /*!< USBH_T::HcInterruptStatus: RHSC Mask */
#define USBH_HcInterruptEnable_SO_Pos (0) /*!< USBH_T::HcInterruptEnable: SO Position */
#define USBH_HcInterruptEnable_SO_Msk (0x1ul << USBH_HcInterruptEnable_SO_Pos) /*!< USBH_T::HcInterruptEnable: SO Mask */
#define USBH_HcInterruptEnable_WDH_Pos (1) /*!< USBH_T::HcInterruptEnable: WDH Position*/
#define USBH_HcInterruptEnable_WDH_Msk (0x1ul << USBH_HcInterruptEnable_WDH_Pos) /*!< USBH_T::HcInterruptEnable: WDH Mask */
#define USBH_HcInterruptEnable_SF_Pos (2) /*!< USBH_T::HcInterruptEnable: SF Position */
#define USBH_HcInterruptEnable_SF_Msk (0x1ul << USBH_HcInterruptEnable_SF_Pos) /*!< USBH_T::HcInterruptEnable: SF Mask */
#define USBH_HcInterruptEnable_RD_Pos (3) /*!< USBH_T::HcInterruptEnable: RD Position */
#define USBH_HcInterruptEnable_RD_Msk (0x1ul << USBH_HcInterruptEnable_RD_Pos) /*!< USBH_T::HcInterruptEnable: RD Mask */
#define USBH_HcInterruptEnable_FNO_Pos (5) /*!< USBH_T::HcInterruptEnable: FNO Position*/
#define USBH_HcInterruptEnable_FNO_Msk (0x1ul << USBH_HcInterruptEnable_FNO_Pos) /*!< USBH_T::HcInterruptEnable: FNO Mask */
#define USBH_HcInterruptEnable_RHSC_Pos (6) /*!< USBH_T::HcInterruptEnable: RHSC Position*/
#define USBH_HcInterruptEnable_RHSC_Msk (0x1ul << USBH_HcInterruptEnable_RHSC_Pos) /*!< USBH_T::HcInterruptEnable: RHSC Mask */
#define USBH_HcInterruptEnable_MIE_Pos (31) /*!< USBH_T::HcInterruptEnable: MIE Position*/
#define USBH_HcInterruptEnable_MIE_Msk (0x1ul << USBH_HcInterruptEnable_MIE_Pos) /*!< USBH_T::HcInterruptEnable: MIE Mask */
#define USBH_HcInterruptDisable_SO_Pos (0) /*!< USBH_T::HcInterruptDisable: SO Position*/
#define USBH_HcInterruptDisable_SO_Msk (0x1ul << USBH_HcInterruptDisable_SO_Pos) /*!< USBH_T::HcInterruptDisable: SO Mask */
#define USBH_HcInterruptDisable_WDH_Pos (1) /*!< USBH_T::HcInterruptDisable: WDH Position*/
#define USBH_HcInterruptDisable_WDH_Msk (0x1ul << USBH_HcInterruptDisable_WDH_Pos) /*!< USBH_T::HcInterruptDisable: WDH Mask */
#define USBH_HcInterruptDisable_SF_Pos (2) /*!< USBH_T::HcInterruptDisable: SF Position*/
#define USBH_HcInterruptDisable_SF_Msk (0x1ul << USBH_HcInterruptDisable_SF_Pos) /*!< USBH_T::HcInterruptDisable: SF Mask */
#define USBH_HcInterruptDisable_RD_Pos (3) /*!< USBH_T::HcInterruptDisable: RD Position*/
#define USBH_HcInterruptDisable_RD_Msk (0x1ul << USBH_HcInterruptDisable_RD_Pos) /*!< USBH_T::HcInterruptDisable: RD Mask */
#define USBH_HcInterruptDisable_FNO_Pos (5) /*!< USBH_T::HcInterruptDisable: FNO Position*/
#define USBH_HcInterruptDisable_FNO_Msk (0x1ul << USBH_HcInterruptDisable_FNO_Pos) /*!< USBH_T::HcInterruptDisable: FNO Mask */
#define USBH_HcInterruptDisable_RHSC_Pos (6) /*!< USBH_T::HcInterruptDisable: RHSC Position*/
#define USBH_HcInterruptDisable_RHSC_Msk (0x1ul << USBH_HcInterruptDisable_RHSC_Pos) /*!< USBH_T::HcInterruptDisable: RHSC Mask */
#define USBH_HcInterruptDisable_MIE_Pos (31) /*!< USBH_T::HcInterruptDisable: MIE Position*/
#define USBH_HcInterruptDisable_MIE_Msk (0x1ul << USBH_HcInterruptDisable_MIE_Pos) /*!< USBH_T::HcInterruptDisable: MIE Mask */
#define USBH_HcHCCA_HCCA_Pos (8) /*!< USBH_T::HcHCCA: HCCA Position */
#define USBH_HcHCCA_HCCA_Msk (0xfffffful << USBH_HcHCCA_HCCA_Pos) /*!< USBH_T::HcHCCA: HCCA Mask */
#define USBH_HcPeriodCurrentED_PCED_Pos (4) /*!< USBH_T::HcPeriodCurrentED: PCED Position*/
#define USBH_HcPeriodCurrentED_PCED_Msk (0xffffffful << USBH_HcPeriodCurrentED_PCED_Pos) /*!< USBH_T::HcPeriodCurrentED: PCED Mask */
#define USBH_HcControlHeadED_CHED_Pos (4) /*!< USBH_T::HcControlHeadED: CHED Position */
#define USBH_HcControlHeadED_CHED_Msk (0xffffffful << USBH_HcControlHeadED_CHED_Pos) /*!< USBH_T::HcControlHeadED: CHED Mask */
#define USBH_HcControlCurrentED_CCED_Pos (4) /*!< USBH_T::HcControlCurrentED: CCED Position*/
#define USBH_HcControlCurrentED_CCED_Msk (0xffffffful << USBH_HcControlCurrentED_CCED_Pos) /*!< USBH_T::HcControlCurrentED: CCED Mask */
#define USBH_HcBulkHeadED_BHED_Pos (4) /*!< USBH_T::HcBulkHeadED: BHED Position */
#define USBH_HcBulkHeadED_BHED_Msk (0xffffffful << USBH_HcBulkHeadED_BHED_Pos) /*!< USBH_T::HcBulkHeadED: BHED Mask */
#define USBH_HcBulkCurrentED_BCED_Pos (4) /*!< USBH_T::HcBulkCurrentED: BCED Position */
#define USBH_HcBulkCurrentED_BCED_Msk (0xffffffful << USBH_HcBulkCurrentED_BCED_Pos) /*!< USBH_T::HcBulkCurrentED: BCED Mask */
#define USBH_HcDoneHead_DH_Pos (4) /*!< USBH_T::HcDoneHead: DH Position */
#define USBH_HcDoneHead_DH_Msk (0xffffffful << USBH_HcDoneHead_DH_Pos) /*!< USBH_T::HcDoneHead: DH Mask */
#define USBH_HcFmInterval_FI_Pos (0) /*!< USBH_T::HcFmInterval: FI Position */
#define USBH_HcFmInterval_FI_Msk (0x3ffful << USBH_HcFmInterval_FI_Pos) /*!< USBH_T::HcFmInterval: FI Mask */
#define USBH_HcFmInterval_FSMPS_Pos (16) /*!< USBH_T::HcFmInterval: FSMPS Position */
#define USBH_HcFmInterval_FSMPS_Msk (0x7ffful << USBH_HcFmInterval_FSMPS_Pos) /*!< USBH_T::HcFmInterval: FSMPS Mask */
#define USBH_HcFmInterval_FIT_Pos (31) /*!< USBH_T::HcFmInterval: FIT Position */
#define USBH_HcFmInterval_FIT_Msk (0x1ul << USBH_HcFmInterval_FIT_Pos) /*!< USBH_T::HcFmInterval: FIT Mask */
#define USBH_HcFmRemaining_FR_Pos (0) /*!< USBH_T::HcFmRemaining: FR Position */
#define USBH_HcFmRemaining_FR_Msk (0x3ffful << USBH_HcFmRemaining_FR_Pos) /*!< USBH_T::HcFmRemaining: FR Mask */
#define USBH_HcFmRemaining_FRT_Pos (31) /*!< USBH_T::HcFmRemaining: FRT Position */
#define USBH_HcFmRemaining_FRT_Msk (0x1ul << USBH_HcFmRemaining_FRT_Pos) /*!< USBH_T::HcFmRemaining: FRT Mask */
#define USBH_HcFmNumber_FN_Pos (0) /*!< USBH_T::HcFmNumber: FN Position */
#define USBH_HcFmNumber_FN_Msk (0xfffful << USBH_HcFmNumber_FN_Pos) /*!< USBH_T::HcFmNumber: FN Mask */
#define USBH_HcPeriodicStart_PS_Pos (0) /*!< USBH_T::HcPeriodicStart: PS Position */
#define USBH_HcPeriodicStart_PS_Msk (0x3ffful << USBH_HcPeriodicStart_PS_Pos) /*!< USBH_T::HcPeriodicStart: PS Mask */
#define USBH_HcLSThreshold_LST_Pos (0) /*!< USBH_T::HcLSThreshold: LST Position */
#define USBH_HcLSThreshold_LST_Msk (0xffful << USBH_HcLSThreshold_LST_Pos) /*!< USBH_T::HcLSThreshold: LST Mask */
#define USBH_HcRhDescriptorA_NDP_Pos (0) /*!< USBH_T::HcRhDescriptorA: NDP Position */
#define USBH_HcRhDescriptorA_NDP_Msk (0xfful << USBH_HcRhDescriptorA_NDP_Pos) /*!< USBH_T::HcRhDescriptorA: NDP Mask */
#define USBH_HcRhDescriptorA_PSM_Pos (8) /*!< USBH_T::HcRhDescriptorA: PSM Position */
#define USBH_HcRhDescriptorA_PSM_Msk (0x1ul << USBH_HcRhDescriptorA_PSM_Pos) /*!< USBH_T::HcRhDescriptorA: PSM Mask */
#define USBH_HcRhDescriptorA_OCPM_Pos (11) /*!< USBH_T::HcRhDescriptorA: OCPM Position */
#define USBH_HcRhDescriptorA_OCPM_Msk (0x1ul << USBH_HcRhDescriptorA_OCPM_Pos) /*!< USBH_T::HcRhDescriptorA: OCPM Mask */
#define USBH_HcRhDescriptorA_NOCP_Pos (12) /*!< USBH_T::HcRhDescriptorA: NOCP Position */
#define USBH_HcRhDescriptorA_NOCP_Msk (0x1ul << USBH_HcRhDescriptorA_NOCP_Pos) /*!< USBH_T::HcRhDescriptorA: NOCP Mask */
#define USBH_HcRhDescriptorB_PPCM_Pos (16) /*!< USBH_T::HcRhDescriptorB: PPCM Position */
#define USBH_HcRhDescriptorB_PPCM_Msk (0xfffful << USBH_HcRhDescriptorB_PPCM_Pos) /*!< USBH_T::HcRhDescriptorB: PPCM Mask */
#define USBH_HcRhStatus_LPS_Pos (0) /*!< USBH_T::HcRhStatus: LPS Position */
#define USBH_HcRhStatus_LPS_Msk (0x1ul << USBH_HcRhStatus_LPS_Pos) /*!< USBH_T::HcRhStatus: LPS Mask */
#define USBH_HcRhStatus_OCI_Pos (1) /*!< USBH_T::HcRhStatus: OCI Position */
#define USBH_HcRhStatus_OCI_Msk (0x1ul << USBH_HcRhStatus_OCI_Pos) /*!< USBH_T::HcRhStatus: OCI Mask */
#define USBH_HcRhStatus_DRWE_Pos (15) /*!< USBH_T::HcRhStatus: DRWE Position */
#define USBH_HcRhStatus_DRWE_Msk (0x1ul << USBH_HcRhStatus_DRWE_Pos) /*!< USBH_T::HcRhStatus: DRWE Mask */
#define USBH_HcRhStatus_LPSC_Pos (16) /*!< USBH_T::HcRhStatus: LPSC Position */
#define USBH_HcRhStatus_LPSC_Msk (0x1ul << USBH_HcRhStatus_LPSC_Pos) /*!< USBH_T::HcRhStatus: LPSC Mask */
#define USBH_HcRhStatus_OCIC_Pos (17) /*!< USBH_T::HcRhStatus: OCIC Position */
#define USBH_HcRhStatus_OCIC_Msk (0x1ul << USBH_HcRhStatus_OCIC_Pos) /*!< USBH_T::HcRhStatus: OCIC Mask */
#define USBH_HcRhStatus_CRWE_Pos (31) /*!< USBH_T::HcRhStatus: CRWE Position */
#define USBH_HcRhStatus_CRWE_Msk (0x1ul << USBH_HcRhStatus_CRWE_Pos) /*!< USBH_T::HcRhStatus: CRWE Mask */
#define USBH_HcRhPortStatus_CCS_Pos (0) /*!< USBH_T::HcRhPortStatus1: CCS Position */
#define USBH_HcRhPortStatus_CCS_Msk (0x1ul << USBH_HcRhPortStatus_CCS_Pos) /*!< USBH_T::HcRhPortStatus1: CCS Mask */
#define USBH_HcRhPortStatus_PES_Pos (1) /*!< USBH_T::HcRhPortStatus1: PES Position */
#define USBH_HcRhPortStatus_PES_Msk (0x1ul << USBH_HcRhPortStatus_PES_Pos) /*!< USBH_T::HcRhPortStatus1: PES Mask */
#define USBH_HcRhPortStatus_PSS_Pos (2) /*!< USBH_T::HcRhPortStatus1: PSS Position */
#define USBH_HcRhPortStatus_PSS_Msk (0x1ul << USBH_HcRhPortStatus_PSS_Pos) /*!< USBH_T::HcRhPortStatus1: PSS Mask */
#define USBH_HcRhPortStatus_POCI_Pos (3) /*!< USBH_T::HcRhPortStatus1: POCI Position */
#define USBH_HcRhPortStatus_POCI_Msk (0x1ul << USBH_HcRhPortStatus_POCI_Pos) /*!< USBH_T::HcRhPortStatus1: POCI Mask */
#define USBH_HcRhPortStatus_PRS_Pos (4) /*!< USBH_T::HcRhPortStatus1: PRS Position */
#define USBH_HcRhPortStatus_PRS_Msk (0x1ul << USBH_HcRhPortStatus_PRS_Pos) /*!< USBH_T::HcRhPortStatus1: PRS Mask */
#define USBH_HcRhPortStatus_PPS_Pos (8) /*!< USBH_T::HcRhPortStatus1: PPS Position */
#define USBH_HcRhPortStatus_PPS_Msk (0x1ul << USBH_HcRhPortStatus_PPS_Pos) /*!< USBH_T::HcRhPortStatus1: PPS Mask */
#define USBH_HcRhPortStatus_LSDA_Pos (9) /*!< USBH_T::HcRhPortStatus1: LSDA Position */
#define USBH_HcRhPortStatus_LSDA_Msk (0x1ul << USBH_HcRhPortStatus_LSDA_Pos) /*!< USBH_T::HcRhPortStatus1: LSDA Mask */
#define USBH_HcRhPortStatus_CSC_Pos (16) /*!< USBH_T::HcRhPortStatus1: CSC Position */
#define USBH_HcRhPortStatus_CSC_Msk (0x1ul << USBH_HcRhPortStatus_CSC_Pos) /*!< USBH_T::HcRhPortStatus1: CSC Mask */
#define USBH_HcRhPortStatus_PESC_Pos (17) /*!< USBH_T::HcRhPortStatus1: PESC Position */
#define USBH_HcRhPortStatus_PESC_Msk (0x1ul << USBH_HcRhPortStatus_PESC_Pos) /*!< USBH_T::HcRhPortStatus1: PESC Mask */
#define USBH_HcRhPortStatus_PSSC_Pos (18) /*!< USBH_T::HcRhPortStatus1: PSSC Position */
#define USBH_HcRhPortStatus_PSSC_Msk (0x1ul << USBH_HcRhPortStatus_PSSC_Pos) /*!< USBH_T::HcRhPortStatus1: PSSC Mask */
#define USBH_HcRhPortStatus_OCIC_Pos (19) /*!< USBH_T::HcRhPortStatus1: OCIC Position */
#define USBH_HcRhPortStatus_OCIC_Msk (0x1ul << USBH_HcRhPortStatus_OCIC_Pos) /*!< USBH_T::HcRhPortStatus1: OCIC Mask */
#define USBH_HcRhPortStatus_PRSC_Pos (20) /*!< USBH_T::HcRhPortStatus1: PRSC Position */
#define USBH_HcRhPortStatus_PRSC_Msk (0x1ul << USBH_HcRhPortStatus_PRSC_Pos) /*!< USBH_T::HcRhPortStatus1: PRSC Mask */
#define USBH_HcPhyControl_STBYEN_Pos (27) /*!< USBH_T::HcPhyControl: STBYEN Position */
#define USBH_HcPhyControl_STBYEN_Msk (0x1ul << USBH_HcPhyControl_STBYEN_Pos) /*!< USBH_T::HcPhyControl: STBYEN Mask */
#define USBH_HcMiscControl_ABORT_Pos (1) /*!< USBH_T::HcMiscControl: ABORT Position */
#define USBH_HcMiscControl_ABORT_Msk (0x1ul << USBH_HcMiscControl_ABORT_Pos) /*!< USBH_T::HcMiscControl: ABORT Mask */
#define USBH_HcMiscControl_OCAL_Pos (3) /*!< USBH_T::HcMiscControl: OCAL Position */
#define USBH_HcMiscControl_OCAL_Msk (0x1ul << USBH_HcMiscControl_OCAL_Pos) /*!< USBH_T::HcMiscControl: OCAL Mask */
#define USBH_HcMiscControl_DPRT1_Pos (16) /*!< USBH_T::HcMiscControl: DPRT1 Position */
#define USBH_HcMiscControl_DPRT1_Msk (0x1ul << USBH_HcMiscControl_DPRT1_Pos) /*!< USBH_T::HcMiscControl: DPRT1 Mask */
/**@}*/ /* USBH_CONST */
/**@}*/ /* end of USBH register group */
/*---------------------- HSUSBH USB Host Controller -------------------------*/
/**
@addtogroup HSUSBH Host Controller (UBH20)
Memory Mapped Structure for HSUSBH Controller
@{ */
typedef struct {
/**
* @var HSUSBH_T::EHCVNR
* Offset: 0x00 EHCI Version Number Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |CRLEN |Capability Registers Length
* | | |This register is used as an offset to add to register base to find the beginning of the Operational Register Space.
* |[31:16] |VERSION |Host Controller Interface Version Number
* | | |This is a two-byte register containing a BCD encoding of the EHCI revision number supported by this host controller
* | | |The most significant byte of this register represents a major revision and the least significant byte is the minor revision.
* @var HSUSBH_T::EHCSPR
* Offset: 0x04 EHCI Structural Parameters Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |N_PORTS |Number of Physical Downstream Ports
* | | |This field specifies the number of physical downstream ports implemented on this host controller
* | | |The value of this field determines how many port registers are addressable in the Operational Register Space (see Table 2-8)
* | | |Valid values are in the range of 1H to FH.
* | | |A zero in this field is undefined.
* |[4] |PPC |Port Power Control
* | | |This field indicates whether the host controller implementation includes port power control
* | | |A one in this bit indicates the ports have port power switches
* | | |A zero in this bit indicates the port do not have port power stitches
* | | |The value of this field affects the functionality of the Port Power field in each port status and control register.
* |[11:8] |N_PCC |Number of Ports Per Companion Controller
* | | |This field indicates the number of ports supported per companion host controller
* | | |It is used to indicate the port routing configuration to system software.
* | | |For example, if N_PORTS has a value of 6 and N_CC has a value of 2 then N_PCC could have a value of 3
* | | |The convention is that the first N_PCC ports are assumed to be routed to companion controller 1, the next N_PCC ports to companion controller 2, etc
* | | |In the previous example, the N_PCC could have been 4, where the first 4 are routed to companion controller 1 and the last two are routed to companion controller 2.
* | | |The number in this field must be consistent with N_PORTS and N_CC.
* |[15:12] |N_CC |Number of Companion Controller
* | | |This field indicates the number of companion controllers associated with this USB 2.0 host controller.
* | | |A zero in this field indicates there are no companion host controllers
* | | |Port-ownership hand-off is not supported
* | | |Only high-speed devices are supported on the host controller root ports.
* | | |A value larger than zero in this field indicates there are companion USB 1.1 host controller(s)
* | | |Port-ownership hand-offs are supported
* | | |High, Full- and Low-speed devices are supported on the host controller root ports.
* @var HSUSBH_T::EHCCPR
* Offset: 0x08 EHCI Capability Parameters Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |AC64 |64-bit Addressing Capability
* | | |0 = Data structure using 32-bit address memory pointers.
* |[1] |PFLF |Programmable Frame List Flag
* | | |0 = System software must use a frame list length of 1024 elements with this EHCI host controller.
* |[2] |ASPC |Asynchronous Schedule Park Capability
* | | |0 = This EHCI host controller doesn't support park feature of high-speed queue heads in the Asynchronous Schedule.
* |[7:4] |IST |Isochronous Scheduling Threshold
* | | |This field indicates, relative to the current position of the executing host controller, where software can reliably update the isochronous schedule.
* | | |When bit [7] is zero, the value of the least significant 3 bits indicates the number of micro-frames a host controller can hold a set of isochronous data structures (one or more) before flushing the state.
* |[15:8] |EECP |EHCI Extended Capabilities Pointer (EECP)
* | | |0 = No extended capabilities are implemented.
* @var HSUSBH_T::UCMDR
* Offset: 0x20 USB Command Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |RUN |Run/Stop (R/W)
* | | |When set to a 1, the Host Controller proceeds with execution of the schedule
* | | |The Host Controller continues execution as long as this bit is set to a 1
* | | |When this bit is set to 0, the Host Controller completes the current and any actively pipelined transactions on the USB and then halts
* | | |The Host Controller must halt within 16 micro-frames after software clears the Run bit
* | | |The HC Halted bit in the status register indicates when the Host Controller has finished its pending pipelined transactions and has entered the stopped state
* | | |Software must not write a one to this field unless the host controller is in the Halted state (i.e.
* | | |HCHalted in the USBSTS register is a one)
* | | |Doing so will yield undefined results.
* | | |0 = Stop.
* | | |1 = Run.
* |[1] |HCRST |Host Controller Reset (HCRESET) (R/W)
* | | |This control bit is used by software to reset the host controller
* | | |The effects of this on Root Hub registers are similar to a Chip Hardware Reset.
* | | |When software writes a one to this bit, the Host Controller resets its internal pipelines, timers, counters, state machines, etc
* | | |to their initial value
* | | |Any transaction currently in progress on USB is immediately terminated
* | | |A USB reset is not driven on downstream ports.
* | | |All operational registers, including port registers and port state machines are set to their initial values
* | | |Port ownership reverts to the companion host controller(s), with the side effects
* | | |Software must reinitialize the host controller in order to return the host controller to an operational state.
* | | |This bit is set to zero by the Host Controller when the reset process is complete
* | | |Software cannot terminate the reset process early by writing a zero to this register.
* | | |Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero
* | | |Attempting to reset an actively running host controller will result in undefined behavior.
* |[3:2] |FLSZ |Frame List Size (R/W or RO)
* | | |This field is R/W only if Programmable Frame List Flag in the HCCPARAMS registers is set to a one
* | | |This field specifies the size of the frame list
* | | |The size the frame list controls which bits in the Frame Index Register should be used for the Frame List Current index
* | | |Values mean:
* | | |00 = 1024 elements (4096 bytes) Default value.
* | | |01 = 512 elements (2048 bytes).
* | | |10 = 256 elements (1024 bytes) u2013 for resource-constrained environment.
* | | |11 = Reserved.
* |[4] |PSEN |Periodic Schedule Enable (R/W)
* | | |This bit controls whether the host controller skips processing the Periodic Schedule. Values mean:
* | | |0 = Do not process the Periodic Schedule.
* | | |1 = Use the PERIODICLISTBASE register to access the Periodic Schedule.
* |[5] |ASEN |Asynchronous Schedule Enable (R/W)
* | | |This bit controls whether the host controller skips processing the Asynchronous Schedule. Values mean:
* | | |0 = Do not process the Asynchronous Schedule.
* | | |1 = Use the ASYNCLISTADDR register to access the Asynchronous Schedule.
* |[6] |IAAD |Interrupt on Asynchronous Advance Doorbell (R/W)
* | | |This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule
* | | |Software must write a 1 to this bit to ring the doorbell.
* | | |When the host controller has evicted all appropriate cached schedule state, it sets the Interrupt on Asynchronous Advance status bit in the USBSTS register
* | | |If the Interrupt on Asynchronous Advance Enable bit in the USBINTR register is a one then the host controller will assert an interrupt at the next interrupt threshold.
* | | |The host controller sets this bit to a zero after it has set the Interrupt on Asynchronous Advance status bit in the USBSTS register to a one.
* | | |Software should not write a one to this bit when the asynchronous schedule is disabled
* | | |Doing so will yield undefined results.
* |[23:16] |ITC |Interrupt Threshold Control (R/W)
* | | |This field is used by system software to select the maximum rate at which the host controller will issue interrupts
* | | |The only valid values are defined below
* | | |If software writes an invalid value to this register, the results are undefined
* | | |Value Maximum Interrupt Interval
* | | |0x00 = Reserved.
* | | |0x01 = 1 micro-frame.
* | | |0x02 = 2 micro-frames.
* | | |0x04 = 4 micro-frames.
* | | |0x08 = 8 micro-frames (default, equates to 1 ms).
* | | |0x10 = 16 micro-frames (2 ms).
* | | |0x20 = 32 micro-frames (4 ms).
* | | |0x40 = 64 micro-frames (8 ms).
* | | |Any other value in this register yields undefined results.
* | | |Software modifications to this bit while HCHalted bit is equal to zero results in undefined behavior.
* @var HSUSBH_T::USTSR
* Offset: 0x24 USB Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |USBINT |USB Interrupt (USBINT) (R/WC)
* | | |The Host Controller sets this bit to 1 on the completion of a USB transaction, which results in the retirement of a Transfer Descriptor that had its IOC bit set.
* | | |The Host Controller also sets this bit to 1 when a short packet is detected (actual number of bytes received was less than the expected number of bytes).
* |[1] |UERRINT |USB Error Interrupt (USBERRINT) (R/WC)
* | | |The Host Controller sets this bit to 1 when completion of a USB transaction results in an error condition (e.g., error counter underflow)
* | | |If the TD on which the error interrupt occurred also had its IOC bit set, both this bit and USBINT bit are set.
* |[2] |PCD |Port Change Detect (R/WC)
* | | |The Host Controller sets this bit to a one when any port for which the Port Owner bit is set to zero has a change bit transition from a zero to a one or a Force Port Resume bit transition from a zero to a one as a result of a J-K transition detected on a suspended port
* | | |This bit will also be set as a result of the Connect Status Change being set to a one after system software has relinquished ownership of a connected port by writing a one to a port's Port Owner bit.
* | | |This bit is allowed to be maintained in the Auxiliary power well
* | | |Alternatively, it is also acceptable that on a D3 to D0 transition of the EHCI HC device, this bit is loaded with the OR of all of the PORTSC change bits (including: Force port resume, over-current change, enable/disable change and connect status change).
* |[3] |FLR |Frame List Rollover (R/WC)
* | | |The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to zero
* | | |The exact value at which the rollover occurs depends on the frame list size
* | | |For example, if the frame list size (as programmed in the Frame List Size field of the USBCMD register) is 1024, the Frame Index Register rolls over every time FRINDEX[13] toggles
* | | |Similarly, if the size is 512, the Host Controller sets this bit to a one every time FRINDEX[12] toggles.
* |[4] |HSERR |Host System Error (R/WC)
* | | |The Host Controller sets this bit to 1 when a serious error occurs during a host system access involving the Host Controller module.
* |[5] |IAA |Interrupt on Asynchronous Advance (R/WC)
* | | |System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a one to the Interrupt on Asynchronous Advance Doorbell bit in the USBCMD register
* | | |This status bit indicates the assertion of that interrupt source.
* |[12] |HCHalted |HCHalted (RO)
* | | |This bit is a zero whenever the Run/Stop bit is a one
* | | |The Host Controller sets this bit to one after it has stopped executing as a result of the Run/Stop bit being set to 0, either by software or by the Host Controller hardware (e.g.
* | | |internal error).
* |[13] |RECLA |Reclamation (RO)
* | | |This is a read-only status bit, which is used to detect an empty asynchronous schedule.
* |[14] |PSS |Periodic Schedule Status (RO)
* | | |The bit reports the current real status of the Periodic Schedule
* | | |If this bit is a zero then the status of the Periodic Schedule is disabled
* | | |If this bit is a one then the status of the Periodic Schedule is enabled
* | | |The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register
* | | |When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (1) or disabled (0).
* |[15] |ASS |Asynchronous Schedule Status (RO)
* | | |The bit reports the current real status of the Asynchronous Schedule
* | | |If this bit is a zero then the status of them Asynchronous Schedule is disabled
* | | |If this bit is a one then the status of the Asynchronous Schedule is enabled
* | | |The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register
* | | |When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (1) or disabled (0).
* @var HSUSBH_T::UIENR
* Offset: 0x28 USB Interrupt Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |USBIEN |USB Interrupt Enable or Disable Bit
* | | |When this bit is a one, and the USBINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold
* | | |The interrupt is acknowledged by software clearing the USBINT bit.
* | | |0 = USB interrupt Disabled.
* | | |1 = USB interrupt Enabled.
* |[1] |UERRIEN |USB Error Interrupt Enable or Disable Bit
* | | |When this bit is a one, and the USBERRINT bit in the USBSTS register is a one, the host t controller will issue an interrupt at the next interrupt threshold
* | | |The interrupt is acknowledged by software clearing the USBERRINT bit.
* | | |0 = USB Error interrupt Disabled.
* | | |1 = USB Error interrupt Enabled.
* |[2] |PCIEN |Port Change Interrupt Enable or Disable Bit
* | | |When this bit is a one, and the Port Change Detect bit in the USBSTS register is a one, the host controller will issue an interrupt
* | | |The interrupt is acknowledged by software clearing the Port Change Detect bit.
* | | |0 = Port Change interrupt Disabled.
* | | |1 = Port Change interrupt Enabled.
* |[3] |FLREN |Frame List Rollover Enable or Disable Bit
* | | |When this bit is a one, and the Frame List Rollover bit in the USBSTS register is a one, the host controller will issue an interrupt
* | | |The interrupt is acknowledged by software clearing the Frame List Rollover bit.
* | | |0 = Frame List Rollover interrupt Disabled.
* | | |1 = Frame List Rollover interrupt Enabled.
* |[4] |HSERREN |Host System Error Enable or Disable Bit
* | | |When this bit is a one, and the Host System Error Status bit in the USBSTS register is a one, the host controller will issue an interrupt
* | | |The interrupt is acknowledged by software clearing the Host System Error bit.
* | | |0 = Host System Error interrupt Disabled.
* | | |1 = Host System Error interrupt Enabled.
* |[5] |IAAEN |Interrupt on Asynchronous Advance Enable or Disable Bit
* | | |When this bit is a one, and the Interrupt on Asynchronous Advance bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold
* | | |The interrupt is acknowledged by software clearing the Interrupt on Asynchronous Advance bit.
* | | |0 = Interrupt on Asynchronous Advance Disabled.
* | | |1 = Interrupt on Asynchronous Advance Enabled.
* @var HSUSBH_T::UFINDR
* Offset: 0x2C USB Frame Index Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[13:0] |FI |Frame Index
* | | |The value in this register increment at the end of each time frame (e.g.
* | | |micro-frame)
* | | |Bits [N:3] are used for the Frame List current index
* | | |This means that each location of the frame list is accessed 8 times (frames or micro-frames) before moving to the next index
* | | |The following illustrates values of N based on the value of the Frame List Size field in the USBCMD register.
* | | |FLSZ (UCMDR[3:2] Number Elements N
* | | |0x0 1024 12
* | | |0x1 512 11
* | | |0x2 256 10
* | | |0x3 Reserved
* @var HSUSBH_T::UPFLBAR
* Offset: 0x34 USB Periodic Frame List Base Address Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:12] |BADDR |Base Address
* | | |These bits correspond to memory address signals [31:12], respectively.
* @var HSUSBH_T::UCALAR
* Offset: 0x38 USB Current Asynchronous List Address Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:5] |LPL |Link Pointer Low (LPL)
* | | |These bits correspond to memory address signals [31:5], respectively
* | | |This field may only reference a Queue Head (QH).
* @var HSUSBH_T::UASSTR
* Offset: 0x3C USB Asynchronous Schedule Sleep Timer Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[11:0] |ASSTMR |Asynchronous Schedule Sleep Timer
* | | |This field defines the AsyncSchedSleepTime of EHCI spec.
* | | |The asynchronous schedule sleep timer is used to control how often the host controller fetches asynchronous schedule list from system memory while the asynchronous schedule is empty.
* | | |The default value of this timer is 12'hBD6
* | | |Because this timer is implemented in UTMI clock (30MHz) domain, the default sleeping time will be about 100us.
* @var HSUSBH_T::UCFGR
* Offset: 0x60 USB Configure Flag Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CF |Configure Flag (CF)
* | | |Host software sets this bit as the last action in its process of configuring the Host Controller
* | | |This bit controls the default port-routing control logic
* | | |Bit values and side-effects are listed below.
* | | |0 = Port routing control logic default-routes each port to an implementation dependent classic host controller.
* | | |1 = Port routing control logic default-routes all ports to this host controller.
* @var HSUSBH_T::UPSCR[2]
* Offset: 0x64~0x68 USB Port 0~1 Status and Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CCS |Current Connect Status (RO)
* | | |This value reflects the current state of the port, and may not correspond directly to the event that caused the Connect Status Change bit (Bit 1) to be set.
* | | |This field is zero if Port Power is zero.
* | | |0 = No device is present.
* | | |1 = Device is present on port.
* |[1] |CSC |Connect Status Change (R/W)
* | | |Indicates a change has occurred in the port's Current Connect Status
* | | |The host controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change
* | | |For example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be "setting" an already-set bit (i.e., the bit will remain set).Software sets this bit to 0 by writing a 1 to it.
* | | |This field is zero if Port Power is zero.
* | | |0 = No change.
* | | |1 = Change in Current Connect Status.
* |[2] |PE |Port Enabled/Disabled (R/W)
* | | |Ports can only be enabled by the host controller as a part of the reset and enable
* | | |Software cannot enable a port by writing a one to this field
* | | |The host controller will only set this bit to a one when the reset sequence determines that the attached device is a high-speed device.
* | | |Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by host software
* | | |Note that the bit status does not change until the port state actually changes
* | | |There may be a delay in disabling or enabling a port due to other host controller and bus events.
* | | |When the port is disabled (0b) downstream propagation of data is blocked on this port, except for reset.
* | | |This field is zero if Port Power is zero.
* | | |0 = Port Disabled.
* | | |1 = Port Enabled.
* |[3] |PEC |Port Enable/Disable Change (R/WC)
* | | |For the root hub, this bit gets set to a one only when a port is disabled due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification for the definition of a Port Error)
* | | |Software clears this bit by writing a 1 to it.
* | | |This field is zero if Port Power is zero.
* | | |0 = No change.
* | | |1 = Port enabled/disabled status has changed.
* |[4] |OCA |Over-current Active (RO)
* | | |This bit will automatically transition from a one to a zero when the over current condition is removed.
* | | |0 = This port does not have an over-current condition.
* | | |1 = This port currently has an over-current condition.
* |[5] |OCC |Over-current Change (R/WC)
* | | |1 = This bit gets set to a one when there is a change to Over-current Active
* | | |Software clears this bit by writing a one to this bit position.
* |[6] |FPR |Force Port Resume (R/W)
* | | |This functionality defined for manipulating this bit depends on the value of the Suspend bit
* | | |For example, if the port is not suspended (Suspend and Enabled bits are a one) and software transitions this bit to a one, then the effects on the bus are undefined.
* | | |Software sets this bit to a 1 to drive resume signaling
* | | |The Host Controller sets this bit to a 1 if a J-to-K transition is detected while the port is in the Suspend state
* | | |When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to a one
* | | |If software sets this bit to a one, the host controller must not set the Port Change Detect bit.
* | | |Note that when the EHCI controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0
* | | |The resume signaling (Full-speed 'K') is driven on the port as long as this bit remains a one
* | | |Software must appropriately time the Resume and set this bit to a zero when the appropriate amount of time has elapsed
* | | |Writing a zero (from one) causes the port to return to high-speed mode (forcing the bus below the port into a high-speed idle)
* | | |This bit will remain a one until the port has switched to the high-speed idle
* | | |The host controller must complete this transition within 2 milliseconds of software setting this bit to a zero.
* | | |This field is zero if Port Power is zero.
* | | |0 = No resume (K-state) detected/driven on port.
* | | |1 = Resume detected/driven on port.
* |[7] |SUSPEND |Suspend (R/W)
* | | |Port Enabled Bit and Suspend bit of this register define the port states as follows:
* | | |Port enable is 0 and suspend is 0 = Disable.
* | | |Port enable is 0 and suspend is 1 = Disable.
* | | |Port enable is 1 and suspend is 0 = Enable.
* | | |Port enable is 1 and suspend is 1 = Suspend.
* | | |When in suspend state, downstream propagation of data is blocked on this port, except for port reset
* | | |The blocking occurs at the end of the current transaction, if a transaction was in progress when this bit was written to 1
* | | |In the suspend state, the port is sensitive to resume detection
* | | |Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB.
* | | |A write of zero to this bit is ignored by the host controller
* | | |The host controller will unconditionally set this bit to a zero when:
* | | |Software sets the Force Port Resume bit to a zero (from a one).
* | | |Software sets the Port Reset bit to a one (from a zero).
* | | |If host software sets this bit to a one when the port is not enabled (i.e.
* | | |Port enabled bit is a zero) the results are undefined.
* | | |This field is zero if Port Power is zero.
* | | |0 = Port not in suspend state.
* | | |1 = Port in suspend state.
* |[8] |PRST |Port Reset (R/W)
* | | |When software writes a one to this bit (from a zero), the bus reset sequence as defined in the USB Specification Revision 2.0 is started
* | | |Software writes a zero to this bit to terminate the bus reset sequence
* | | |Software must keep this bit at a one long enough to ensure the reset sequence, as specified in the USB Specification Revision 2.0, completes
* | | |Note: when software writes this bit to a one, it must also write a zero to the Port Enable bit.
* | | |Note that when software writes a zero to this bit there may be a delay before the bit status changes to a zero
* | | |The bit status will not read as a zero until after the reset has completed
* | | |If the port is in high-speed mode after reset is complete, the host controller will automatically enable this port (e.g.
* | | |set the Port Enable bit to a one)
* | | |A host controller must terminate the reset and stabilize the state of the port within 2 milliseconds of software transitioning this bit from a one to a zero
* | | |For example: if the port detects that the attached device is high-speed during reset, then the host controller must have the port in the enabled state within 2ms of software writing this bit to a zero.
* | | |The HCHalted bit in the USBSTS register should be a zero before software attempts to use this bit
* | | |The host controller may hold Port Reset asserted to a one when the HCHalted bit is a one.
* | | |This field is zero if Port Power is zero.
* | | |0 = Port is not in Reset.
* | | |1 = Port is in Reset.
* |[11:10] |LSTS |Line Status (RO)
* | | |These bits reflect the current logical levels of the D+ (bit 11) and D- (bit 10) signal lines
* | | |These bits are used for detection of low-speed USB devices prior to the port reset and enable sequence
* | | |This field is valid only when the port enable bit is zero and the current connect status bit is set to a one.
* | | |The encoding of the bits are:
* | | |Bits[11:10] USB State Interpretation
* | | |00 = SE0 Not Low-speed device, perform EHCI reset.
* | | |01 = K-state Low-speed device, release ownership of port.
* | | |10 = J-state Not Low-speed device, perform EHCI reset.
* | | |11 = Undefined Not Low-speed device, perform EHCI reset.
* | | |This value of this field is undefined if Port Power is zero.
* |[12] |PP |Port Power (PP)
* | | |Host controller has port power control switches
* | | |This bit represents the Current setting of the switch (0 = off, 1 = on)
* | | |When power is not available on a port (i.e.
* | | |PP equals a 0), the port is nonfunctional and will not report attaches, detaches, etc.
* | | |When an over-current condition is detected on a powered port and PPC is a one, the PP bit in each affected port may be transitioned by the host controller from a 1 to 0 (removing power from the port).
* |[13] |PO |Port Owner (R/W)
* | | |This bit unconditionally goes to a 0b when the Configured bit in the CONFIGFLAG register makes a 0 to 1 transition
* | | |This bit unconditionally goes to 1 whenever the Configured bit is zero.
* | | |System software uses this field to release ownership of the port to a selected host controller (in the event that the attached device is not a high-speed device)
* | | |Software writes a one to this bit when the attached device is not a high-speed device
* | | |A one in this bit means that a companion host controller owns and controls the port.
* |[19:16] |PTC |Port Test Control (R/W)
* | | |When this field is zero, the port is NOT operating in a test mode
* | | |A non-zero value indicates that it is operating in test mode and the specific test mode is indicated by the specific value
* | | |The encoding of the test mode bits are (0x6 ~ 0xF are reserved):
* | | |Bits Test Mode
* | | |0x0 = Test mode not enabled.
* | | |0x1 = Test J_STATE.
* | | |0x2 = Test K_STATE.
* | | |0x3 = Test SE0_NAK.
* | | |0x4 = Test Packet.
* | | |0x5 = Test FORCE_ENABLE.
* @var HSUSBH_T::USBPCR0
* Offset: 0xC4 USB PHY 0 Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[8] |SUSPEND |Suspend Assertion
* | | |This bit controls the suspend mode of USB PHY 0.
* | | |While PHY was suspended, all circuits of PHY were powered down and outputs are tri-state.
* | | |This bit is 1'b0 in default
* | | |This means the USB PHY 0 is suspended in default
* | | |It is necessary to set this bit 1'b1 to make USB PHY 0 leave suspend mode before doing configuration of USB host.
* | | |0 = USB PHY 0 was suspended.
* | | |1 = USB PHY 0 was not suspended.
* |[11] |CLKVALID |UTMI Clock Valid
* | | |This bit is a flag to indicate if the UTMI clock from USB 2.0 PHY is ready
* | | |S/W program must prevent to write other control registers before this UTMI clock valid flag is active.
* | | |0 = UTMI clock is not valid.
* | | |1 = UTMI clock is valid.
* @var HSUSBH_T::USBPCR1
* Offset: 0xC8 USB PHY 1 Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[8] |SUSPEND |Suspend Assertion
* | | |This bit controls the suspend mode of USB PHY 1.
* | | |While PHY was suspended, all circuits of PHY were powered down and outputs are tri-state.
* | | |This bit is 1'b0 in default
* | | |This means the USB PHY 0 is suspended in default
* | | |It is necessary to set this bit 1'b1 to make USB PHY 0 leave suspend mode before doing configuration of USB host.
* | | |0 = USB PHY 1 was suspended.
* | | |1 = USB PHY 1 was not suspended.
*/
__I uint32_t EHCVNR; /*!< [0x0000] EHCI Version Number Register */
__I uint32_t EHCSPR; /*!< [0x0004] EHCI Structural Parameters Register */
__I uint32_t EHCCPR; /*!< [0x0008] EHCI Capability Parameters Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE0[5];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t UCMDR; /*!< [0x0020] USB Command Register */
__IO uint32_t USTSR; /*!< [0x0024] USB Status Register */
__IO uint32_t UIENR; /*!< [0x0028] USB Interrupt Enable Register */
__IO uint32_t UFINDR; /*!< [0x002c] USB Frame Index Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE1[1];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t UPFLBAR; /*!< [0x0034] USB Periodic Frame List Base Address Register */
__IO uint32_t UCALAR; /*!< [0x0038] USB Current Asynchronous List Address Register */
__IO uint32_t UASSTR; /*!< [0x003c] USB Asynchronous Schedule Sleep Timer Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE2[8];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t UCFGR; /*!< [0x0060] USB Configure Flag Register */
__IO uint32_t UPSCR[2]; /*!< [0x0064] ~ [0x0068] USB Port 0 & 1 Status and Control Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE3[22];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t USBPCR0; /*!< [0x00c4] USB PHY 0 Control Register */
__IO uint32_t USBPCR1; /*!< [0x00c8] USB PHY 1 Control Register */
} HSUSBH_T;
/**
@addtogroup HSUSBH_CONST HSUSBH Bit Field Definition
Constant Definitions for HSUSBH Controller
@{ */
#define HSUSBH_EHCVNR_CRLEN_Pos (0) /*!< HSUSBH_T::EHCVNR: CRLEN Position */
#define HSUSBH_EHCVNR_CRLEN_Msk (0xfful << HSUSBH_EHCVNR_CRLEN_Pos) /*!< HSUSBH_T::EHCVNR: CRLEN Mask */
#define HSUSBH_EHCVNR_VERSION_Pos (16) /*!< HSUSBH_T::EHCVNR: VERSION Position */
#define HSUSBH_EHCVNR_VERSION_Msk (0xfffful << HSUSBH_EHCVNR_VERSION_Pos) /*!< HSUSBH_T::EHCVNR: VERSION Mask */
#define HSUSBH_EHCSPR_N_PORTS_Pos (0) /*!< HSUSBH_T::EHCSPR: N_PORTS Position */
#define HSUSBH_EHCSPR_N_PORTS_Msk (0xful << HSUSBH_EHCSPR_N_PORTS_Pos) /*!< HSUSBH_T::EHCSPR: N_PORTS Mask */
#define HSUSBH_EHCSPR_PPC_Pos (4) /*!< HSUSBH_T::EHCSPR: PPC Position */
#define HSUSBH_EHCSPR_PPC_Msk (0x1ul << HSUSBH_EHCSPR_PPC_Pos) /*!< HSUSBH_T::EHCSPR: PPC Mask */
#define HSUSBH_EHCSPR_N_PCC_Pos (8) /*!< HSUSBH_T::EHCSPR: N_PCC Position */
#define HSUSBH_EHCSPR_N_PCC_Msk (0xful << HSUSBH_EHCSPR_N_PCC_Pos) /*!< HSUSBH_T::EHCSPR: N_PCC Mask */
#define HSUSBH_EHCSPR_N_CC_Pos (12) /*!< HSUSBH_T::EHCSPR: N_CC Position */
#define HSUSBH_EHCSPR_N_CC_Msk (0xful << HSUSBH_EHCSPR_N_CC_Pos) /*!< HSUSBH_T::EHCSPR: N_CC Mask */
#define HSUSBH_EHCCPR_AC64_Pos (0) /*!< HSUSBH_T::EHCCPR: AC64 Position */
#define HSUSBH_EHCCPR_AC64_Msk (0x1ul << HSUSBH_EHCCPR_AC64_Pos) /*!< HSUSBH_T::EHCCPR: AC64 Mask */
#define HSUSBH_EHCCPR_PFLF_Pos (1) /*!< HSUSBH_T::EHCCPR: PFLF Position */
#define HSUSBH_EHCCPR_PFLF_Msk (0x1ul << HSUSBH_EHCCPR_PFLF_Pos) /*!< HSUSBH_T::EHCCPR: PFLF Mask */
#define HSUSBH_EHCCPR_ASPC_Pos (2) /*!< HSUSBH_T::EHCCPR: ASPC Position */
#define HSUSBH_EHCCPR_ASPC_Msk (0x1ul << HSUSBH_EHCCPR_ASPC_Pos) /*!< HSUSBH_T::EHCCPR: ASPC Mask */
#define HSUSBH_EHCCPR_IST_Pos (4) /*!< HSUSBH_T::EHCCPR: IST Position */
#define HSUSBH_EHCCPR_IST_Msk (0xful << HSUSBH_EHCCPR_IST_Pos) /*!< HSUSBH_T::EHCCPR: IST Mask */
#define HSUSBH_EHCCPR_EECP_Pos (8) /*!< HSUSBH_T::EHCCPR: EECP Position */
#define HSUSBH_EHCCPR_EECP_Msk (0xfful << HSUSBH_EHCCPR_EECP_Pos) /*!< HSUSBH_T::EHCCPR: EECP Mask */
#define HSUSBH_UCMDR_RUN_Pos (0) /*!< HSUSBH_T::UCMDR: RUN Position */
#define HSUSBH_UCMDR_RUN_Msk (0x1ul << HSUSBH_UCMDR_RUN_Pos) /*!< HSUSBH_T::UCMDR: RUN Mask */
#define HSUSBH_UCMDR_HCRST_Pos (1) /*!< HSUSBH_T::UCMDR: HCRST Position */
#define HSUSBH_UCMDR_HCRST_Msk (0x1ul << HSUSBH_UCMDR_HCRST_Pos) /*!< HSUSBH_T::UCMDR: HCRST Mask */
#define HSUSBH_UCMDR_FLSZ_Pos (2) /*!< HSUSBH_T::UCMDR: FLSZ Position */
#define HSUSBH_UCMDR_FLSZ_Msk (0x3ul << HSUSBH_UCMDR_FLSZ_Pos) /*!< HSUSBH_T::UCMDR: FLSZ Mask */
#define HSUSBH_UCMDR_PSEN_Pos (4) /*!< HSUSBH_T::UCMDR: PSEN Position */
#define HSUSBH_UCMDR_PSEN_Msk (0x1ul << HSUSBH_UCMDR_PSEN_Pos) /*!< HSUSBH_T::UCMDR: PSEN Mask */
#define HSUSBH_UCMDR_ASEN_Pos (5) /*!< HSUSBH_T::UCMDR: ASEN Position */
#define HSUSBH_UCMDR_ASEN_Msk (0x1ul << HSUSBH_UCMDR_ASEN_Pos) /*!< HSUSBH_T::UCMDR: ASEN Mask */
#define HSUSBH_UCMDR_IAAD_Pos (6) /*!< HSUSBH_T::UCMDR: IAAD Position */
#define HSUSBH_UCMDR_IAAD_Msk (0x1ul << HSUSBH_UCMDR_IAAD_Pos) /*!< HSUSBH_T::UCMDR: IAAD Mask */
#define HSUSBH_UCMDR_ITC_Pos (16) /*!< HSUSBH_T::UCMDR: ITC Position */
#define HSUSBH_UCMDR_ITC_Msk (0xfful << HSUSBH_UCMDR_ITC_Pos) /*!< HSUSBH_T::UCMDR: ITC Mask */
#define HSUSBH_USTSR_USBINT_Pos (0) /*!< HSUSBH_T::USTSR: USBINT Position */
#define HSUSBH_USTSR_USBINT_Msk (0x1ul << HSUSBH_USTSR_USBINT_Pos) /*!< HSUSBH_T::USTSR: USBINT Mask */
#define HSUSBH_USTSR_UERRINT_Pos (1) /*!< HSUSBH_T::USTSR: UERRINT Position */
#define HSUSBH_USTSR_UERRINT_Msk (0x1ul << HSUSBH_USTSR_UERRINT_Pos) /*!< HSUSBH_T::USTSR: UERRINT Mask */
#define HSUSBH_USTSR_PCD_Pos (2) /*!< HSUSBH_T::USTSR: PCD Position */
#define HSUSBH_USTSR_PCD_Msk (0x1ul << HSUSBH_USTSR_PCD_Pos) /*!< HSUSBH_T::USTSR: PCD Mask */
#define HSUSBH_USTSR_FLR_Pos (3) /*!< HSUSBH_T::USTSR: FLR Position */
#define HSUSBH_USTSR_FLR_Msk (0x1ul << HSUSBH_USTSR_FLR_Pos) /*!< HSUSBH_T::USTSR: FLR Mask */
#define HSUSBH_USTSR_HSERR_Pos (4) /*!< HSUSBH_T::USTSR: HSERR Position */
#define HSUSBH_USTSR_HSERR_Msk (0x1ul << HSUSBH_USTSR_HSERR_Pos) /*!< HSUSBH_T::USTSR: HSERR Mask */
#define HSUSBH_USTSR_IAA_Pos (5) /*!< HSUSBH_T::USTSR: IAA Position */
#define HSUSBH_USTSR_IAA_Msk (0x1ul << HSUSBH_USTSR_IAA_Pos) /*!< HSUSBH_T::USTSR: IAA Mask */
#define HSUSBH_USTSR_HCHalted_Pos (12) /*!< HSUSBH_T::USTSR: HCHalted Position */
#define HSUSBH_USTSR_HCHalted_Msk (0x1ul << HSUSBH_USTSR_HCHalted_Pos) /*!< HSUSBH_T::USTSR: HCHalted Mask */
#define HSUSBH_USTSR_RECLA_Pos (13) /*!< HSUSBH_T::USTSR: RECLA Position */
#define HSUSBH_USTSR_RECLA_Msk (0x1ul << HSUSBH_USTSR_RECLA_Pos) /*!< HSUSBH_T::USTSR: RECLA Mask */
#define HSUSBH_USTSR_PSS_Pos (14) /*!< HSUSBH_T::USTSR: PSS Position */
#define HSUSBH_USTSR_PSS_Msk (0x1ul << HSUSBH_USTSR_PSS_Pos) /*!< HSUSBH_T::USTSR: PSS Mask */
#define HSUSBH_USTSR_ASS_Pos (15) /*!< HSUSBH_T::USTSR: ASS Position */
#define HSUSBH_USTSR_ASS_Msk (0x1ul << HSUSBH_USTSR_ASS_Pos) /*!< HSUSBH_T::USTSR: ASS Mask */
#define HSUSBH_UIENR_USBIEN_Pos (0) /*!< HSUSBH_T::UIENR: USBIEN Position */
#define HSUSBH_UIENR_USBIEN_Msk (0x1ul << HSUSBH_UIENR_USBIEN_Pos) /*!< HSUSBH_T::UIENR: USBIEN Mask */
#define HSUSBH_UIENR_UERRIEN_Pos (1) /*!< HSUSBH_T::UIENR: UERRIEN Position */
#define HSUSBH_UIENR_UERRIEN_Msk (0x1ul << HSUSBH_UIENR_UERRIEN_Pos) /*!< HSUSBH_T::UIENR: UERRIEN Mask */
#define HSUSBH_UIENR_PCIEN_Pos (2) /*!< HSUSBH_T::UIENR: PCIEN Position */
#define HSUSBH_UIENR_PCIEN_Msk (0x1ul << HSUSBH_UIENR_PCIEN_Pos) /*!< HSUSBH_T::UIENR: PCIEN Mask */
#define HSUSBH_UIENR_FLREN_Pos (3) /*!< HSUSBH_T::UIENR: FLREN Position */
#define HSUSBH_UIENR_FLREN_Msk (0x1ul << HSUSBH_UIENR_FLREN_Pos) /*!< HSUSBH_T::UIENR: FLREN Mask */
#define HSUSBH_UIENR_HSERREN_Pos (4) /*!< HSUSBH_T::UIENR: HSERREN Position */
#define HSUSBH_UIENR_HSERREN_Msk (0x1ul << HSUSBH_UIENR_HSERREN_Pos) /*!< HSUSBH_T::UIENR: HSERREN Mask */
#define HSUSBH_UIENR_IAAEN_Pos (5) /*!< HSUSBH_T::UIENR: IAAEN Position */
#define HSUSBH_UIENR_IAAEN_Msk (0x1ul << HSUSBH_UIENR_IAAEN_Pos) /*!< HSUSBH_T::UIENR: IAAEN Mask */
#define HSUSBH_UFINDR_FI_Pos (0) /*!< HSUSBH_T::UFINDR: FI Position */
#define HSUSBH_UFINDR_FI_Msk (0x3ffful << HSUSBH_UFINDR_FI_Pos) /*!< HSUSBH_T::UFINDR: FI Mask */
#define HSUSBH_UPFLBAR_BADDR_Pos (12) /*!< HSUSBH_T::UPFLBAR: BADDR Position */
#define HSUSBH_UPFLBAR_BADDR_Msk (0xffffful << HSUSBH_UPFLBAR_BADDR_Pos) /*!< HSUSBH_T::UPFLBAR: BADDR Mask */
#define HSUSBH_UCALAR_LPL_Pos (5) /*!< HSUSBH_T::UCALAR: LPL Position */
#define HSUSBH_UCALAR_LPL_Msk (0x7fffffful << HSUSBH_UCALAR_LPL_Pos) /*!< HSUSBH_T::UCALAR: LPL Mask */
#define HSUSBH_UASSTR_ASSTMR_Pos (0) /*!< HSUSBH_T::UASSTR: ASSTMR Position */
#define HSUSBH_UASSTR_ASSTMR_Msk (0xffful << HSUSBH_UASSTR_ASSTMR_Pos) /*!< HSUSBH_T::UASSTR: ASSTMR Mask */
#define HSUSBH_UCFGR_CF_Pos (0) /*!< HSUSBH_T::UCFGR: CF Position */
#define HSUSBH_UCFGR_CF_Msk (0x1ul << HSUSBH_UCFGR_CF_Pos) /*!< HSUSBH_T::UCFGR: CF Mask */
#define HSUSBH_UPSCR_CCS_Pos (0) /*!< HSUSBH_T::UPSCR[2]: CCS Position */
#define HSUSBH_UPSCR_CCS_Msk (0x1ul << HSUSBH_UPSCR_CCS_Pos) /*!< HSUSBH_T::UPSCR[2]: CCS Mask */
#define HSUSBH_UPSCR_CSC_Pos (1) /*!< HSUSBH_T::UPSCR[2]: CSC Position */
#define HSUSBH_UPSCR_CSC_Msk (0x1ul << HSUSBH_UPSCR_CSC_Pos) /*!< HSUSBH_T::UPSCR[2]: CSC Mask */
#define HSUSBH_UPSCR_PE_Pos (2) /*!< HSUSBH_T::UPSCR[2]: PE Position */
#define HSUSBH_UPSCR_PE_Msk (0x1ul << HSUSBH_UPSCR_PE_Pos) /*!< HSUSBH_T::UPSCR[2]: PE Mask */
#define HSUSBH_UPSCR_PEC_Pos (3) /*!< HSUSBH_T::UPSCR[2]: PEC Position */
#define HSUSBH_UPSCR_PEC_Msk (0x1ul << HSUSBH_UPSCR_PEC_Pos) /*!< HSUSBH_T::UPSCR[2]: PEC Mask */
#define HSUSBH_UPSCR_OCA_Pos (4) /*!< HSUSBH_T::UPSCR[2]: OCA Position */
#define HSUSBH_UPSCR_OCA_Msk (0x1ul << HSUSBH_UPSCR_OCA_Pos) /*!< HSUSBH_T::UPSCR[2]: OCA Mask */
#define HSUSBH_UPSCR_OCC_Pos (5) /*!< HSUSBH_T::UPSCR[2]: OCC Position */
#define HSUSBH_UPSCR_OCC_Msk (0x1ul << HSUSBH_UPSCR_OCC_Pos) /*!< HSUSBH_T::UPSCR[2]: OCC Mask */
#define HSUSBH_UPSCR_FPR_Pos (6) /*!< HSUSBH_T::UPSCR[2]: FPR Position */
#define HSUSBH_UPSCR_FPR_Msk (0x1ul << HSUSBH_UPSCR_FPR_Pos) /*!< HSUSBH_T::UPSCR[2]: FPR Mask */
#define HSUSBH_UPSCR_SUSPEND_Pos (7) /*!< HSUSBH_T::UPSCR[2]: SUSPEND Position */
#define HSUSBH_UPSCR_SUSPEND_Msk (0x1ul << HSUSBH_UPSCR_SUSPEND_Pos) /*!< HSUSBH_T::UPSCR[2]: SUSPEND Mask */
#define HSUSBH_UPSCR_PRST_Pos (8) /*!< HSUSBH_T::UPSCR[2]: PRST Position */
#define HSUSBH_UPSCR_PRST_Msk (0x1ul << HSUSBH_UPSCR_PRST_Pos) /*!< HSUSBH_T::UPSCR[2]: PRST Mask */
#define HSUSBH_UPSCR_LSTS_Pos (10) /*!< HSUSBH_T::UPSCR[2]: LSTS Position */
#define HSUSBH_UPSCR_LSTS_Msk (0x3ul << HSUSBH_UPSCR_LSTS_Pos) /*!< HSUSBH_T::UPSCR[2]: LSTS Mask */
#define HSUSBH_UPSCR_PP_Pos (12) /*!< HSUSBH_T::UPSCR[2]: PP Position */
#define HSUSBH_UPSCR_PP_Msk (0x1ul << HSUSBH_UPSCR_PP_Pos) /*!< HSUSBH_T::UPSCR[2]: PP Mask */
#define HSUSBH_UPSCR_PO_Pos (13) /*!< HSUSBH_T::UPSCR[2]: PO Position */
#define HSUSBH_UPSCR_PO_Msk (0x1ul << HSUSBH_UPSCR_PO_Pos) /*!< HSUSBH_T::UPSCR[2]: PO Mask */
#define HSUSBH_UPSCR_PTC_Pos (16) /*!< HSUSBH_T::UPSCR[2]: PTC Position */
#define HSUSBH_UPSCR_PTC_Msk (0xful << HSUSBH_UPSCR_PTC_Pos) /*!< HSUSBH_T::UPSCR[2]: PTC Mask */
#define HSUSBH_USBPCR0_SUSPEND_Pos (8) /*!< HSUSBH_T::USBPCR0: SUSPEND Position */
#define HSUSBH_USBPCR0_SUSPEND_Msk (0x1ul << HSUSBH_USBPCR0_SUSPEND_Pos) /*!< HSUSBH_T::USBPCR0: SUSPEND Mask */
#define HSUSBH_USBPCR0_CLKVALID_Pos (11) /*!< HSUSBH_T::USBPCR0: CLKVALID Position */
#define HSUSBH_USBPCR0_CLKVALID_Msk (0x1ul << HSUSBH_USBPCR0_CLKVALID_Pos) /*!< HSUSBH_T::USBPCR0: CLKVALID Mask */
#define HSUSBH_USBPCR1_SUSPEND_Pos (8) /*!< HSUSBH_T::USBPCR1: SUSPEND Position */
#define HSUSBH_USBPCR1_SUSPEND_Msk (0x1ul << HSUSBH_USBPCR1_SUSPEND_Pos) /*!< HSUSBH_T::USBPCR1: SUSPEND Mask */
/**@}*/ /* HSUSBH_CONST */
/**@}*/ /* end of HSUSBH register group */
/*---------------------- USB On-The-Go Controller -------------------------*/
/**
@addtogroup OTG USB On-The-Go Controller(OTG)
Memory Mapped Structure for OTG Controller
@{ */
typedef struct {
/**
* @var OTG_T::CTL
* Offset: 0x00 OTG Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |VBUSDROP |Drop VBUS Control
* | | |If user application running on this OTG A-device wants to conserve power, set this bit to drop VBUS
* | | |BUSREQ (OTG_CTL[1]) will be also cleared no matter A-device or B-device.
* | | |0 = Not drop the VBUS.
* | | |1 = Drop the VBUS.
* |[1] |BUSREQ |OTG Bus Request
* | | |If OTG A-device wants to do data transfers via USB bus, setting this bit will drive VBUS high to detect USB device connection
* | | |If user won't use the bus any more, clearing this bit will drop VBUS to save power
* | | |This bit will be cleared when A-device goes to A_wait_vfall state
* | | |This bit will be also cleared if VBUSDROP (OTG_CTL[0]) bit is set or IDSTS (OTG_STATUS[1]) changed.
* | | |If user of an OTG-B Device wants to request VBUS, setting this bit will run SRP protocol
* | | |This bit will be cleared if SRP failure (OTG A-device does not provide VBUS after B-device issues ARP in specified interval, defined in OTG specification)
* | | |This bit will be also cleared if VBUSDROP (OTG_CTL[0]) bit is set IDSTS (OTG_STATUS[1]) changed.
* | | |0 = Not launch VBUS in OTG A-device or not request SRP in OTG B-device.
* | | |1 = Launch VBUS in OTG A-device or request SRP in OTG B-device.
* |[2] |HNPREQEN |OTG HNP Request Enable Bit
* | | |When USB frame as A-device, set this bit when A-device allows to process HNP protocol -- A-device changes role from Host to Peripheral
* | | |This bit will be cleared when OTG state changes from a_suspend to a_peripheral or goes back to a_idle state
* | | |When USB frame as B-device, set this bit after the OTG A-device successfully sends a SetFeature (b_hnp_enable) command to the OTG B-device to start role change -- B-device changes role from Peripheral to Host
* | | |This bit will be cleared when OTG state changes from b_peripheral to b_wait_acon or goes back to b_idle state.
* | | |0 = HNP request Disabled.
* | | |1 = HNP request Enabled (A-device can change role from Host to Peripheral or B-device can change role from Peripheral to Host).
* | | |Note: Refer to OTG specification to get a_suspend, a_peripheral, a_idle and b_idle state.
* |[4] |OTGEN |OTG Function Enable Bit
* | | |User needs to set this bit to enable OTG function while USB frame configured as OTG device
* | | |When USB frame not configured as OTG device, this bit is must be low.
* | | |0= OTG function Disabled.
* | | |1 = OTG function Enabled.
* |[5] |WKEN |OTG ID Pin Wake-up Enable Bit
* | | |0 = OTG ID pin status change wake-up function Disabled.
* | | |1 = OTG ID pin status change wake-up function Enabled.
* @var OTG_T::PHYCTL
* Offset: 0x04 OTG PHY Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |OTGPHYEN |OTG PHY Enable
* | | |When USB frame is configured as OTG-device or ID-dependent, user needs to set this bit before using OTG function
* | | |If device is not configured as OTG-device nor ID-dependent , this bit is "don't care".
* | | |0 = OTG PHY Disabled.
* | | |1 = OTG PHY Enabled.
* |[1] |IDDETEN |ID Detection Enable Bit
* | | |0 = Detect ID pin status Disabled.
* | | |1 = Detect ID pin status Enabled.
* |[4] |VBENPOL |Off-chip USB VBUS Power Switch Enable Polarity
* | | |The OTG controller will enable off-chip USB VBUS power switch to provide VBUS power when need
* | | |A USB_VBUS_EN pin is used to control the off-chip USB VBUS power switch.
* | | |The polarity of enabling off-chip USB VBUS power switch (high active or low active) depends on the selected component
* | | |Set this bit as following according to the polarity of off-chip USB VBUS power switch.
* | | |0 = The off-chip USB VBUS power switch enable is active high.
* | | |1 = The off-chip USB VBUS power switch enable is active low.
* |[5] |VBSTSPOL |Off-chip USB VBUS Power Switch Status Polarity
* | | |The polarity of off-chip USB VBUS power switch valid signal depends on the selected component
* | | |A USB_VBUS_ST pin is used to monitor the valid signal of the off-chip USB VBUS power switch
* | | |Set this bit as following according to the polarity of off-chip USB VBUS power switch.
* | | |0 = The polarity of off-chip USB VBUS power switch valid status is high.
* | | |1 = The polarity of off-chip USB VBUS power switch valid status is low.
* @var OTG_T::INTEN
* Offset: 0x08 OTG Interrupt Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ROLECHGIEN|Role (Host or Peripheral) Changed Interrupt Enable Bit
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* |[1] |VBEIEN |VBUS Error Interrupt Enable Bit
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* | | |Note: VBUS error means going to a_vbus_err state. Please refer to A-device state diagram in OTG spec.
* |[2] |SRPFIEN |SRP Fail Interrupt Enable Bit
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* |[3] |HNPFIEN |HNP Fail Interrupt Enable Bit
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* |[4] |GOIDLEIEN |OTG Device Goes to IDLE State Interrupt Enable Bit
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* | | |Note: Going to idle state means going to a_idle or b_idle state
* | | |Please refer to A-device state diagram and B-device state diagram in OTG spec.
* |[5] |IDCHGIEN |IDSTS Changed Interrupt Enable Bit
* | | |If this bit is set to 1 and IDSTS (OTG_STATUS[1]) status is changed from high to low or from low to high, a interrupt will be asserted.
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* |[6] |PDEVIEN |Act As Peripheral Interrupt Enable Bit
* | | |If this bit is set to 1 and the device is changed as a peripheral, a interrupt will be asserted.
* | | |0 = This device as a peripheral interrupt Disabled.
* | | |1 = This device as a peripheral interrupt Enabled.
* |[7] |HOSTIEN |Act As Host Interrupt Enable Bit
* | | |If this bit is set to 1 and the device is changed as a host, a interrupt will be asserted.
* | | |0 = This device as a host interrupt Disabled.
* | | |1 = This device as a host interrupt Enabled.
* |[8] |BVLDCHGIEN|B-device Session Valid Status Changed Interrupt Enable Bit
* | | |If this bit is set to 1 and BVLD (OTG_STATUS[3]) status is changed from high to low or from low to high, a interrupt will be asserted.
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* |[9] |AVLDCHGIEN|A-device Session Valid Status Changed Interrupt Enable Bit
* | | |If this bit is set to 1 and AVLD (OTG_STATUS[4]) status is changed from high to low or from low to high, a interrupt will be asserted.
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* |[10] |VBCHGIEN |VBUSVLD Status Changed Interrupt Enable Bit
* | | |If this bit is set to 1 and VBUSVLD (OTG_STATUS[5]) status is changed from high to low or from low to high, a interrupt will be asserted.
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* |[11] |SECHGIEN |SESSEND Status Changed Interrupt Enable Bit
* | | |If this bit is set to 1 and SESSEND (OTG_STATUS[2]) status is changed from high to low or from low to high, a interrupt will be asserted.
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* |[13] |SRPDETIEN |SRP Detected Interrupt Enable Bit
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* @var OTG_T::INTSTS
* Offset: 0x0C OTG Interrupt Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ROLECHGIF |OTG Role Change Interrupt Status
* | | |This flag is set when the role of an OTG device changed from a host to a peripheral, or changed from a peripheral to a host while USB_ID pin status does not change.
* | | |0 = OTG device role not changed.
* | | |1 = OTG device role changed.
* | | |Note: Write 1 to clear this flag.
* |[1] |VBEIF |VBUS Error Interrupt Status
* | | |This bit will be set when voltage on VBUS cannot reach a minimum valid threshold 4.4V within a maximum time of 100ms after OTG A-device starting to drive VBUS high.
* | | |0 = OTG A-device drives VBUS over threshold voltage before this interval expires.
* | | |1 = OTG A-device cannot drive VBUS over threshold voltage before this interval expires.
* | | |Note: Write 1 to clear this flag and recover from the VBUS error state.
* |[2] |SRPFIF |SRP Fail Interrupt Status
* | | |After initiating SRP, an OTG B-device will wait for the OTG A-device to drive VBUS high at least TB_SRP_FAIL minimum, defined in OTG specification
* | | |This flag is set when the OTG B-device does not get VBUS high after this interval.
* | | |0 = OTG B-device gets VBUS high before this interval.
* | | |1 = OTG B-device does not get VBUS high before this interval.
* | | |Note: Write 1 to clear this flag.
* |[3] |HNPFIF |HNP Fail Interrupt Status
* | | |When A-device has granted B-device to be host and USB bus is in SE0 (both USB_D+ and USB_D- low) state, this bit will be set when A-device does not connect after specified interval expires.
* | | |0 = A-device connects to B-device before specified interval expires.
* | | |1 = A-device does not connect to B-device before specified interval expires.
* | | |Note: Write 1 to clear this flag.
* |[4] |GOIDLEIF |OTG Device Goes to IDLE Interrupt Status
* | | |Flag is set if the OTG device transfers from non-idle state to idle state
* | | |The OTG device will be neither a host nor a peripheral.
* | | |0 = OTG device does not go back to idle state (a_idle or b_idle).
* | | |1 = OTG device goes back to idle state(a_idle or b_idle).
* | | |Note 1: Going to idle state means going to a_idle or b_idle state. Please refer to OTG specification.
* | | |Note 2: Write 1 to clear this flag.
* |[5] |IDCHGIF |ID State Change Interrupt Status
* | | |0 = IDSTS (OTG_STATUS[1]) not toggled.
* | | |1 = IDSTS (OTG_STATUS[1]) from high to low or from low to high.
* | | |Note: Write 1 to clear this flag.
* |[6] |PDEVIF |Act As Peripheral Interrupt Status
* | | |0= This device does not act as a peripheral.
* | | |1 = This device acts as a peripheral.
* | | |Note: Write 1 to clear this flag.
* |[7] |HOSTIF |Act As Host Interrupt Status
* | | |0= This device does not act as a host.
* | | |1 = This device acts as a host.
* | | |Note: Write 1 to clear this flag.
* |[8] |BVLDCHGIF |B-device Session Valid State Change Interrupt Status
* | | |0 = BVLD (OTG_STATUS[3]) is not toggled.
* | | |1 = BVLD (OTG_STATUS[3]) from high to low or low to high.
* | | |Note: Write 1 to clear this status.
* |[9] |AVLDCHGIF |A-device Session Valid State Change Interrupt Status
* | | |0 = AVLD (OTG_STATUS[4]) not toggled.
* | | |1 = AVLD (OTG_STATUS[4]) from high to low or low to high.
* | | |Note: Write 1 to clear this status.
* |[10] |VBCHGIF |VBUSVLD State Change Interrupt Status
* | | |0 = VBUSVLD (OTG_STATUS[5]) not toggled.
* | | |1 = VBUSVLD (OTG_STATUS[5]) from high to low or from low to high.
* | | |Note: Write 1 to clear this status.
* |[11] |SECHGIF |SESSEND State Change Interrupt Status
* | | |0 = SESSEND (OTG_STATUS[2]) not toggled.
* | | |1 = SESSEND (OTG_STATUS[2]) from high to low or from low to high.
* | | |Note: Write 1 to clear this flag.
* |[13] |SRPDETIF |SRP Detected Interrupt Status
* | | |0 = SRP not detected.
* | | |1 = SRP detected.
* | | |Note: Write 1 to clear this status.
* @var OTG_T::STATUS
* Offset: 0x10 OTG Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |OVERCUR |over Current Condition
* | | |The voltage on VBUS cannot reach a minimum VBUS valid threshold, 4.4V minimum, within a maximum time of 100ms after OTG A-device drives VBUS high.
* | | |0 = OTG A-device drives VBUS successfully.
* | | |1 = OTG A-device cannot drives VBUS high in this interval.
* |[1] |IDSTS |USB_ID Pin State of Mini-b/Micro-plug
* | | |0 = Mini-A/Micro-A plug is attached.
* | | |1 = Mini-B/Micro-B plug is attached.
* |[2] |SESSEND |Session End Status
* | | |When VBUS voltage is lower than 0.4V, this bit will be set to 1
* | | |Session end means no meaningful power on VBUS.
* | | |0 = Session is not end.
* | | |1 = Session is end.
* |[3] |BVLD |B-device Session Valid Status
* | | |0 = B-device session is not valid.
* | | |1 = B-device session is valid.
* |[4] |AVLD |A-device Session Valid Status
* | | |0 = A-device session is not valid.
* | | |1 = A-device session is valid.
* |[5] |VBUSVLD |VBUS Valid Status
* | | |When VBUS is larger than 4.7V, this bit will be set to 1.
* | | |0 = VBUS is not valid.
* | | |1 = VBUS is valid.
* |[6] |ASPERI |As Peripheral Status
* | | |When OTG as peripheral, this bit is set.
* | | |0: OTG not as peripheral
* | | |1: OTG as peripheral
* |[7] |ASHOST |As Host Status
* | | |When OTG as Host, this bit is set.
* | | |0: OTG not as Host
* | | |1: OTG as Host
*/
__IO uint32_t CTL; /*!< [0x0000] OTG Control Register */
__IO uint32_t PHYCTL; /*!< [0x0004] OTG PHY Control Register */
__IO uint32_t INTEN; /*!< [0x0008] OTG Interrupt Enable Register */
__IO uint32_t INTSTS; /*!< [0x000c] OTG Interrupt Status Register */
__I uint32_t STATUS; /*!< [0x0010] OTG Status Register */
} OTG_T;
/**
@addtogroup OTG_CONST OTG Bit Field Definition
Constant Definitions for OTG Controller
@{ */
#define OTG_CTL_VBUSDROP_Pos (0) /*!< OTG_T::CTL: VBUSDROP Position */
#define OTG_CTL_VBUSDROP_Msk (0x1ul << OTG_CTL_VBUSDROP_Pos) /*!< OTG_T::CTL: VBUSDROP Mask */
#define OTG_CTL_BUSREQ_Pos (1) /*!< OTG_T::CTL: BUSREQ Position */
#define OTG_CTL_BUSREQ_Msk (0x1ul << OTG_CTL_BUSREQ_Pos) /*!< OTG_T::CTL: BUSREQ Mask */
#define OTG_CTL_HNPREQEN_Pos (2) /*!< OTG_T::CTL: HNPREQEN Position */
#define OTG_CTL_HNPREQEN_Msk (0x1ul << OTG_CTL_HNPREQEN_Pos) /*!< OTG_T::CTL: HNPREQEN Mask */
#define OTG_CTL_OTGEN_Pos (4) /*!< OTG_T::CTL: OTGEN Position */
#define OTG_CTL_OTGEN_Msk (0x1ul << OTG_CTL_OTGEN_Pos) /*!< OTG_T::CTL: OTGEN Mask */
#define OTG_CTL_WKEN_Pos (5) /*!< OTG_T::CTL: WKEN Position */
#define OTG_CTL_WKEN_Msk (0x1ul << OTG_CTL_WKEN_Pos) /*!< OTG_T::CTL: WKEN Mask */
#define OTG_PHYCTL_OTGPHYEN_Pos (0) /*!< OTG_T::PHYCTL: OTGPHYEN Position */
#define OTG_PHYCTL_OTGPHYEN_Msk (0x1ul << OTG_PHYCTL_OTGPHYEN_Pos) /*!< OTG_T::PHYCTL: OTGPHYEN Mask */
#define OTG_PHYCTL_IDDETEN_Pos (1) /*!< OTG_T::PHYCTL: IDDETEN Position */
#define OTG_PHYCTL_IDDETEN_Msk (0x1ul << OTG_PHYCTL_IDDETEN_Pos) /*!< OTG_T::PHYCTL: IDDETEN Mask */
#define OTG_PHYCTL_VBENPOL_Pos (4) /*!< OTG_T::PHYCTL: VBENPOL Position */
#define OTG_PHYCTL_VBENPOL_Msk (0x1ul << OTG_PHYCTL_VBENPOL_Pos) /*!< OTG_T::PHYCTL: VBENPOL Mask */
#define OTG_PHYCTL_VBSTSPOL_Pos (5) /*!< OTG_T::PHYCTL: VBSTSPOL Position */
#define OTG_PHYCTL_VBSTSPOL_Msk (0x1ul << OTG_PHYCTL_VBSTSPOL_Pos) /*!< OTG_T::PHYCTL: VBSTSPOL Mask */
#define OTG_INTEN_ROLECHGIEN_Pos (0) /*!< OTG_T::INTEN: ROLECHGIEN Position */
#define OTG_INTEN_ROLECHGIEN_Msk (0x1ul << OTG_INTEN_ROLECHGIEN_Pos) /*!< OTG_T::INTEN: ROLECHGIEN Mask */
#define OTG_INTEN_VBEIEN_Pos (1) /*!< OTG_T::INTEN: VBEIEN Position */
#define OTG_INTEN_VBEIEN_Msk (0x1ul << OTG_INTEN_VBEIEN_Pos) /*!< OTG_T::INTEN: VBEIEN Mask */
#define OTG_INTEN_SRPFIEN_Pos (2) /*!< OTG_T::INTEN: SRPFIEN Position */
#define OTG_INTEN_SRPFIEN_Msk (0x1ul << OTG_INTEN_SRPFIEN_Pos) /*!< OTG_T::INTEN: SRPFIEN Mask */
#define OTG_INTEN_HNPFIEN_Pos (3) /*!< OTG_T::INTEN: HNPFIEN Position */
#define OTG_INTEN_HNPFIEN_Msk (0x1ul << OTG_INTEN_HNPFIEN_Pos) /*!< OTG_T::INTEN: HNPFIEN Mask */
#define OTG_INTEN_GOIDLEIEN_Pos (4) /*!< OTG_T::INTEN: GOIDLEIEN Position */
#define OTG_INTEN_GOIDLEIEN_Msk (0x1ul << OTG_INTEN_GOIDLEIEN_Pos) /*!< OTG_T::INTEN: GOIDLEIEN Mask */
#define OTG_INTEN_IDCHGIEN_Pos (5) /*!< OTG_T::INTEN: IDCHGIEN Position */
#define OTG_INTEN_IDCHGIEN_Msk (0x1ul << OTG_INTEN_IDCHGIEN_Pos) /*!< OTG_T::INTEN: IDCHGIEN Mask */
#define OTG_INTEN_PDEVIEN_Pos (6) /*!< OTG_T::INTEN: PDEVIEN Position */
#define OTG_INTEN_PDEVIEN_Msk (0x1ul << OTG_INTEN_PDEVIEN_Pos) /*!< OTG_T::INTEN: PDEVIEN Mask */
#define OTG_INTEN_HOSTIEN_Pos (7) /*!< OTG_T::INTEN: HOSTIEN Position */
#define OTG_INTEN_HOSTIEN_Msk (0x1ul << OTG_INTEN_HOSTIEN_Pos) /*!< OTG_T::INTEN: HOSTIEN Mask */
#define OTG_INTEN_BVLDCHGIEN_Pos (8) /*!< OTG_T::INTEN: BVLDCHGIEN Position */
#define OTG_INTEN_BVLDCHGIEN_Msk (0x1ul << OTG_INTEN_BVLDCHGIEN_Pos) /*!< OTG_T::INTEN: BVLDCHGIEN Mask */
#define OTG_INTEN_AVLDCHGIEN_Pos (9) /*!< OTG_T::INTEN: AVLDCHGIEN Position */
#define OTG_INTEN_AVLDCHGIEN_Msk (0x1ul << OTG_INTEN_AVLDCHGIEN_Pos) /*!< OTG_T::INTEN: AVLDCHGIEN Mask */
#define OTG_INTEN_VBCHGIEN_Pos (10) /*!< OTG_T::INTEN: VBCHGIEN Position */
#define OTG_INTEN_VBCHGIEN_Msk (0x1ul << OTG_INTEN_VBCHGIEN_Pos) /*!< OTG_T::INTEN: VBCHGIEN Mask */
#define OTG_INTEN_SECHGIEN_Pos (11) /*!< OTG_T::INTEN: SECHGIEN Position */
#define OTG_INTEN_SECHGIEN_Msk (0x1ul << OTG_INTEN_SECHGIEN_Pos) /*!< OTG_T::INTEN: SECHGIEN Mask */
#define OTG_INTEN_SRPDETIEN_Pos (13) /*!< OTG_T::INTEN: SRPDETIEN Position */
#define OTG_INTEN_SRPDETIEN_Msk (0x1ul << OTG_INTEN_SRPDETIEN_Pos) /*!< OTG_T::INTEN: SRPDETIEN Mask */
#define OTG_INTSTS_ROLECHGIF_Pos (0) /*!< OTG_T::INTSTS: ROLECHGIF Position */
#define OTG_INTSTS_ROLECHGIF_Msk (0x1ul << OTG_INTSTS_ROLECHGIF_Pos) /*!< OTG_T::INTSTS: ROLECHGIF Mask */
#define OTG_INTSTS_VBEIF_Pos (1) /*!< OTG_T::INTSTS: VBEIF Position */
#define OTG_INTSTS_VBEIF_Msk (0x1ul << OTG_INTSTS_VBEIF_Pos) /*!< OTG_T::INTSTS: VBEIF Mask */
#define OTG_INTSTS_SRPFIF_Pos (2) /*!< OTG_T::INTSTS: SRPFIF Position */
#define OTG_INTSTS_SRPFIF_Msk (0x1ul << OTG_INTSTS_SRPFIF_Pos) /*!< OTG_T::INTSTS: SRPFIF Mask */
#define OTG_INTSTS_HNPFIF_Pos (3) /*!< OTG_T::INTSTS: HNPFIF Position */
#define OTG_INTSTS_HNPFIF_Msk (0x1ul << OTG_INTSTS_HNPFIF_Pos) /*!< OTG_T::INTSTS: HNPFIF Mask */
#define OTG_INTSTS_GOIDLEIF_Pos (4) /*!< OTG_T::INTSTS: GOIDLEIF Position */
#define OTG_INTSTS_GOIDLEIF_Msk (0x1ul << OTG_INTSTS_GOIDLEIF_Pos) /*!< OTG_T::INTSTS: GOIDLEIF Mask */
#define OTG_INTSTS_IDCHGIF_Pos (5) /*!< OTG_T::INTSTS: IDCHGIF Position */
#define OTG_INTSTS_IDCHGIF_Msk (0x1ul << OTG_INTSTS_IDCHGIF_Pos) /*!< OTG_T::INTSTS: IDCHGIF Mask */
#define OTG_INTSTS_PDEVIF_Pos (6) /*!< OTG_T::INTSTS: PDEVIF Position */
#define OTG_INTSTS_PDEVIF_Msk (0x1ul << OTG_INTSTS_PDEVIF_Pos) /*!< OTG_T::INTSTS: PDEVIF Mask */
#define OTG_INTSTS_HOSTIF_Pos (7) /*!< OTG_T::INTSTS: HOSTIF Position */
#define OTG_INTSTS_HOSTIF_Msk (0x1ul << OTG_INTSTS_HOSTIF_Pos) /*!< OTG_T::INTSTS: HOSTIF Mask */
#define OTG_INTSTS_BVLDCHGIF_Pos (8) /*!< OTG_T::INTSTS: BVLDCHGIF Position */
#define OTG_INTSTS_BVLDCHGIF_Msk (0x1ul << OTG_INTSTS_BVLDCHGIF_Pos) /*!< OTG_T::INTSTS: BVLDCHGIF Mask */
#define OTG_INTSTS_AVLDCHGIF_Pos (9) /*!< OTG_T::INTSTS: AVLDCHGIF Position */
#define OTG_INTSTS_AVLDCHGIF_Msk (0x1ul << OTG_INTSTS_AVLDCHGIF_Pos) /*!< OTG_T::INTSTS: AVLDCHGIF Mask */
#define OTG_INTSTS_VBCHGIF_Pos (10) /*!< OTG_T::INTSTS: VBCHGIF Position */
#define OTG_INTSTS_VBCHGIF_Msk (0x1ul << OTG_INTSTS_VBCHGIF_Pos) /*!< OTG_T::INTSTS: VBCHGIF Mask */
#define OTG_INTSTS_SECHGIF_Pos (11) /*!< OTG_T::INTSTS: SECHGIF Position */
#define OTG_INTSTS_SECHGIF_Msk (0x1ul << OTG_INTSTS_SECHGIF_Pos) /*!< OTG_T::INTSTS: SECHGIF Mask */
#define OTG_INTSTS_SRPDETIF_Pos (13) /*!< OTG_T::INTSTS: SRPDETIF Position */
#define OTG_INTSTS_SRPDETIF_Msk (0x1ul << OTG_INTSTS_SRPDETIF_Pos) /*!< OTG_T::INTSTS: SRPDETIF Mask */
#define OTG_STATUS_OVERCUR_Pos (0) /*!< OTG_T::STATUS: OVERCUR Position */
#define OTG_STATUS_OVERCUR_Msk (0x1ul << OTG_STATUS_OVERCUR_Pos) /*!< OTG_T::STATUS: OVERCUR Mask */
#define OTG_STATUS_IDSTS_Pos (1) /*!< OTG_T::STATUS: IDSTS Position */
#define OTG_STATUS_IDSTS_Msk (0x1ul << OTG_STATUS_IDSTS_Pos) /*!< OTG_T::STATUS: IDSTS Mask */
#define OTG_STATUS_SESSEND_Pos (2) /*!< OTG_T::STATUS: SESSEND Position */
#define OTG_STATUS_SESSEND_Msk (0x1ul << OTG_STATUS_SESSEND_Pos) /*!< OTG_T::STATUS: SESSEND Mask */
#define OTG_STATUS_BVLD_Pos (3) /*!< OTG_T::STATUS: BVLD Position */
#define OTG_STATUS_BVLD_Msk (0x1ul << OTG_STATUS_BVLD_Pos) /*!< OTG_T::STATUS: BVLD Mask */
#define OTG_STATUS_AVLD_Pos (4) /*!< OTG_T::STATUS: AVLD Position */
#define OTG_STATUS_AVLD_Msk (0x1ul << OTG_STATUS_AVLD_Pos) /*!< OTG_T::STATUS: AVLD Mask */
#define OTG_STATUS_VBUSVLD_Pos (5) /*!< OTG_T::STATUS: VBUSVLD Position */
#define OTG_STATUS_VBUSVLD_Msk (0x1ul << OTG_STATUS_VBUSVLD_Pos) /*!< OTG_T::STATUS: VBUSVLD Mask */
#define OTG_STATUS_ASPERI_Pos (6) /*!< OTG_T::STATUS: ASPERI Position */
#define OTG_STATUS_ASPERI_Msk (0x1ul << OTG_STATUS_ASPERI_Pos) /*!< OTG_T::STATUS: ASPERI Mask */
#define OTG_STATUS_ASHOST_Pos (7) /*!< OTG_T::STATUS: ASHOST Position */
#define OTG_STATUS_ASHOST_Msk (0x1ul << OTG_STATUS_ASHOST_Pos) /*!< OTG_T::STATUS: ASHOST Mask */
/**@}*/ /* OTG_CONST */
/**@}*/ /* end of OTG register group */
/*---------------------- USB High Speed On-The-Go Controller -------------------------*/
/**
@addtogroup HSOTG USB On-The-Go Controller(HSOTG)
Memory Mapped Structure for HSOTG Controller
@{ */
typedef struct {
/**
* @var HSOTG_T::CTL
* Offset: 0x00 HSOTG Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |VBUSDROP |Drop VBUS Control
* | | |If user application running on this OTG A-device wants to conserve power, set this bit to drop VBUS
* | | |BUSREQ (OTG_CTL[1]) will be also cleared no matter A-device or B-device.
* | | |0 = Not drop the VBUS.
* | | |1 = Drop the VBUS.
* |[1] |BUSREQ |OTG Bus Request
* | | |If OTG A-device wants to do data transfers via USB bus, setting this bit will drive VBUS high to detect USB device connection
* | | |If user won't use the bus any more, clearing this bit will drop VBUS to save power
* | | |This bit will be cleared when A-device goes to A_wait_vfall state
* | | |This bit will be also cleared if VBUSDROP (OTG_CTL[0]) bit is set or IDSTS (OTG_STATUS[1]) changed.
* | | |If user of an OTG-B Device wants to request VBUS, setting this bit will run SRP protocol
* | | |This bit will be cleared if SRP failure (OTG A-device does not provide VBUS after B-device issues ARP in specified interval, defined in OTG specification)
* | | |This bit will be also cleared if VBUSDROP (OTG_CTL[0]) bit is set IDSTS (OTG_STATUS[1]) changed.
* | | |0 = Not launch VBUS in OTG A-device or not request SRP in OTG B-device.
* | | |1 = Launch VBUS in OTG A-device or request SRP in OTG B-device.
* |[2] |HNPREQEN |OTG HNP Request Enable Bit
* | | |When USB frame as A-device, set this bit when A-device allows to process HNP protocol -- A-device changes role from Host to Peripheral
* | | |This bit will be cleared when OTG state changes from a_suspend to a_peripheral or goes back to a_idle state
* | | |When USB frame as B-device, set this bit after the OTG A-device successfully sends a SetFeature (b_hnp_enable) command to the OTG B-device to start role change -- B-device changes role from Peripheral to Host
* | | |This bit will be cleared when OTG state changes from b_peripheral to b_wait_acon or goes back to b_idle state.
* | | |0 = HNP request Disabled.
* | | |1 = HNP request Enabled (A-device can change role from Host to Peripheral or B-device can change role from Peripheral to Host).
* | | |Note: Refer to OTG specification to get a_suspend, a_peripheral, a_idle and b_idle state.
* |[4] |OTGEN |OTG Function Enable Bit
* | | |User needs to set this bit to enable OTG function while USB frame configured as OTG device
* | | |When USB frame not configured as OTG device, this bit is must be low.
* | | |0= OTG function Disabled.
* | | |1 = OTG function Enabled.
* |[5] |WKEN |OTG ID Pin Wake-up Enable Bit
* | | |0 = OTG ID pin status change wake-up function Disabled.
* | | |1 = OTG ID pin status change wake-up function Enabled.
* @var HSOTG_T::PHYCTL
* Offset: 0x04 HSOTG PHY Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |OTGPHYEN |OTG PHY Enable
* | | |When USB frame is configured as OTG-device or ID-dependent, user needs to set this bit before using OTG function
* | | |If device is not configured as OTG-device nor ID-dependent, this bit is "don't care".
* | | |0 = OTG PHY Disabled.
* | | |1 = OTG PHY Enabled.
* |[1] |IDDETEN |ID Detection Enable Bit
* | | |0 = Detect ID pin status Disabled.
* | | |1 = Detect ID pin status Enabled.
* |[4] |VBENPOL |Off-chip USB VBUS Power Switch Enable Polarity
* | | |The OTG controller will enable off-chip USB VBUS power switch to provide VBUS power when need
* | | |A USB_VBUS_EN pin is used to control the off-chip USB VBUS power switch.
* | | |The polarity of enabling off-chip USB VBUS power switch (high active or low active) depends on the selected component
* | | |Set this bit as following according to the polarity of off-chip USB VBUS power switch.
* | | |0 = The off-chip USB VBUS power switch enable is active high.
* | | |1 = The off-chip USB VBUS power switch enable is active low.
* |[5] |VBSTSPOL |Off-chip USB VBUS Power Switch Status Polarity
* | | |The polarity of off-chip USB VBUS power switch valid signal depends on the selected component
* | | |A USB_VBUS_ST pin is used to monitor the valid signal of the off-chip USB VBUS power switch
* | | |Set this bit as following according to the polarity of off-chip USB VBUS power switch.
* | | |0 = The polarity of off-chip USB VBUS power switch valid status is high.
* | | |1 = The polarity of off-chip USB VBUS power switch valid status is low.
* @var HSOTG_T::INTEN
* Offset: 0x08 HSOTG Interrupt Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ROLECHGIEN|Role (Host or Peripheral) Changed Interrupt Enable Bit
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* |[1] |VBEIEN |VBUS Error Interrupt Enable Bit
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* | | |Note: VBUS error means going to a_vbus_err state. Please refer to A-device state diagram in OTG spec.
* |[2] |SRPFIEN |SRP Fail Interrupt Enable Bit
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* |[3] |HNPFIEN |HNP Fail Interrupt Enable Bit
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* |[4] |GOIDLEIEN |OTG Device Goes to IDLE State Interrupt Enable Bit
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* | | |Note: Going to idle state means going to a_idle or b_idle state
* | | |Please refer to A-device state diagram and B-device state diagram in OTG spec.
* |[5] |IDCHGIEN |IDSTS Changed Interrupt Enable Bit
* | | |If this bit is set to 1 and IDSTS (OTG_STATUS[1]) status is changed from high to low or from low to high, a interrupt will be asserted.
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* |[6] |PDEVIEN |Act As Peripheral Interrupt Enable Bit
* | | |If this bit is set to 1 and the device is changed as a peripheral, a interrupt will be asserted.
* | | |0 = This device as a peripheral interrupt Disabled.
* | | |1 = This device as a peripheral interrupt Enabled.
* |[7] |HOSTIEN |Act As Host Interrupt Enable Bit
* | | |If this bit is set to 1 and the device is changed as a host, a interrupt will be asserted.
* | | |0 = This device as a host interrupt Disabled.
* | | |1 = This device as a host interrupt Enabled.
* |[8] |BVLDCHGIEN|B-device Session Valid Status Changed Interrupt Enable Bit
* | | |If this bit is set to 1 and BVLD (OTG_STATUS[3]) status is changed from high to low or from low to high, a interrupt will be asserted.
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* |[9] |AVLDCHGIEN|A-device Session Valid Status Changed Interrupt Enable Bit
* | | |If this bit is set to 1 and AVLD (OTG_STATUS[4]) status is changed from high to low or from low to high, a interrupt will be asserted.
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* |[10] |VBCHGIEN |VBUSVLD Status Changed Interrupt Enable Bit
* | | |If this bit is set to 1 and VBUSVLD (OTG_STATUS[5]) status is changed from high to low or from low to high, a interrupt will be asserted.
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* |[11] |SECHGIEN |SESSEND Status Changed Interrupt Enable Bit
* | | |If this bit is set to 1 and SESSEND (OTG_STATUS[2]) status is changed from high to low or from low to high, a interrupt will be asserted.
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* |[13] |SRPDETIEN |SRP Detected Interrupt Enable Bit
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* @var HSOTG_T::INTSTS
* Offset: 0x0C HSOTG Interrupt Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ROLECHGIF |OTG Role Change Interrupt Status
* | | |This flag is set when the role of an OTG device changed from a host to a peripheral, or changed from a peripheral to a host while USB_ID pin status does not change.
* | | |0 = OTG device role not changed.
* | | |1 = OTG device role changed.
* | | |Note: Write 1 to clear this flag.
* |[1] |VBEIF |VBUS Error Interrupt Status
* | | |This bit will be set when voltage on VBUS cannot reach a minimum valid threshold 4.4V within a maximum time of 100ms after OTG A-device starting to drive VBUS high.
* | | |0 = OTG A-device drives VBUS over threshold voltage before this interval expires.
* | | |1 = OTG A-device cannot drive VBUS over threshold voltage before this interval expires.
* | | |Note: Write 1 to clear this flag and recover from the VBUS error state.
* |[2] |SRPFIF |SRP Fail Interrupt Status
* | | |After initiating SRP, an OTG B-device will wait for the OTG A-device to drive VBUS high at least TB_SRP_FAIL minimum, defined in OTG specification
* | | |This flag is set when the OTG B-device does not get VBUS high after this interval.
* | | |0 = OTG B-device gets VBUS high before this interval.
* | | |1 = OTG B-device does not get VBUS high before this interval.
* | | |Note: Write 1 to clear this flag.
* |[3] |HNPFIF |HNP Fail Interrupt Status
* | | |When A-device has granted B-device to be host and USB bus is in SE0 (both USB_D+ and USB_D- low) state, this bit will be set when A-device does not connect after specified interval expires.
* | | |0 = A-device connects to B-device before specified interval expires.
* | | |1 = A-device does not connect to B-device before specified interval expires.
* | | |Note: Write 1 to clear this flag.
* |[4] |GOIDLEIF |OTG Device Goes to IDLE Interrupt Status
* | | |Flag is set if the OTG device transfers from non-idle state to idle state
* | | |The OTG device will be neither a host nor a peripheral.
* | | |0 = OTG device does not go back to idle state (a_idle or b_idle).
* | | |1 = OTG device goes back to idle state(a_idle or b_idle).
* | | |Note 1: Going to idle state means going to a_idle or b_idle state. Please refer to OTG specification.
* | | |Note 2: Write 1 to clear this flag.
* |[5] |IDCHGIF |ID State Change Interrupt Status
* | | |0 = IDSTS (OTG_STATUS[1]) not toggled.
* | | |1 = IDSTS (OTG_STATUS[1]) from high to low or from low to high.
* | | |Note: Write 1 to clear this flag.
* |[6] |PDEVIF |Act As Peripheral Interrupt Status
* | | |0= This device does not act as a peripheral.
* | | |1 = This device acts as a peripheral.
* | | |Note: Write 1 to clear this flag.
* |[7] |HOSTIF |Act As Host Interrupt Status
* | | |0= This device does not act as a host.
* | | |1 = This device acts as a host.
* | | |Note: Write 1 to clear this flag.
* |[8] |BVLDCHGIF |B-device Session Valid State Change Interrupt Status
* | | |0 = BVLD (OTG_STATUS[3]) is not toggled.
* | | |1 = BVLD (OTG_STATUS[3]) from high to low or low to high.
* | | |Note: Write 1 to clear this status.
* |[9] |AVLDCHGIF |A-device Session Valid State Change Interrupt Status
* | | |0 = AVLD (OTG_STATUS[4]) not toggled.
* | | |1 = AVLD (OTG_STATUS[4]) from high to low or low to high.
* | | |Note: Write 1 to clear this status.
* |[10] |VBCHGIF |VBUSVLD State Change Interrupt Status
* | | |0 = VBUSVLD (OTG_STATUS[5]) not toggled.
* | | |1 = VBUSVLD (OTG_STATUS[5]) from high to low or from low to high.
* | | |Note: Write 1 to clear this status.
* |[11] |SECHGIF |SESSEND State Change Interrupt Status
* | | |0 = SESSEND (OTG_STATUS[2]) not toggled.
* | | |1 = SESSEND (OTG_STATUS[2]) from high to low or from low to high.
* | | |Note: Write 1 to clear this flag.
* |[13] |SRPDETIF |SRP Detected Interrupt Status
* | | |0 = SRP not detected.
* | | |1 = SRP detected.
* | | |Note: Write 1 to clear this status.
* @var HSOTG_T::STATUS
* Offset: 0x10 HSOTG Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |OVERCUR |over Current Condition
* | | |The voltage on VBUS cannot reach a minimum VBUS valid threshold, 4.4V minimum, within a maximum time of 100ms after OTG A-device drives VBUS high.
* | | |0 = OTG A-device drives VBUS successfully.
* | | |1 = OTG A-device cannot drives VBUS high in this interval.
* |[1] |IDSTS |USB_ID Pin State of Mini-b/Micro-plug
* | | |0 = Mini-A/Micro-A plug is attached.
* | | |1 = Mini-B/Micro-B plug is attached.
* |[2] |SESSEND |Session End Status
* | | |When VBUS voltage is lower than 0.4V, this bit will be set to 1
* | | |Session end means no meaningful power on VBUS.
* | | |0 = Session is not end.
* | | |1 = Session is end.
* |[3] |BVLD |B-device Session Valid Status
* | | |0 = B-device session is not valid.
* | | |1 = B-device session is valid.
* |[4] |AVLD |A-device Session Valid Status
* | | |0 = A-device session is not valid.
* | | |1 = A-device session is valid.
* |[5] |VBUSVLD |VBUS Valid Status
* | | |When VBUS is larger than 4.7V and A-device drives VBUS , this bit will be set to 1.
* | | |0 = VBUS is not valid.
* | | |1 = VBUS is valid.
* |[6] |ASPERI |As Peripheral Status
* | | |When OTG as peripheral, this bit is set.
* | | |0: OTG not as peripheral
* | | |1: OTG as peripheral
* |[7] |ASHOST |As Host Status
* | | |When OTG as Host, this bit is set.
* | | |0: OTG not as Host
* | | |1: OTG as Host
*/
__IO uint32_t CTL; /*!< [0x0000] HSOTG Control Register */
__IO uint32_t PHYCTL; /*!< [0x0004] HSOTG PHY Control Register */
__IO uint32_t INTEN; /*!< [0x0008] HSOTG Interrupt Enable Register */
__IO uint32_t INTSTS; /*!< [0x000c] HSOTG Interrupt Status Register */
__I uint32_t STATUS; /*!< [0x0010] HSOTG Status Register */
} HSOTG_T;
/**
@addtogroup HSOTG_CONST HSOTG Bit Field Definition
Constant Definitions for HSOTG Controller
@{ */
#define HSOTG_CTL_VBUSDROP_Pos (0) /*!< HSOTG_T::CTL: VBUSDROP Position */
#define HSOTG_CTL_VBUSDROP_Msk (0x1ul << HSOTG_CTL_VBUSDROP_Pos) /*!< HSOTG_T::CTL: VBUSDROP Mask */
#define HSOTG_CTL_BUSREQ_Pos (1) /*!< HSOTG_T::CTL: BUSREQ Position */
#define HSOTG_CTL_BUSREQ_Msk (0x1ul << HSOTG_CTL_BUSREQ_Pos) /*!< HSOTG_T::CTL: BUSREQ Mask */
#define HSOTG_CTL_HNPREQEN_Pos (2) /*!< HSOTG_T::CTL: HNPREQEN Position */
#define HSOTG_CTL_HNPREQEN_Msk (0x1ul << HSOTG_CTL_HNPREQEN_Pos) /*!< HSOTG_T::CTL: HNPREQEN Mask */
#define HSOTG_CTL_OTGEN_Pos (4) /*!< HSOTG_T::CTL: OTGEN Position */
#define HSOTG_CTL_OTGEN_Msk (0x1ul << HSOTG_CTL_OTGEN_Pos) /*!< HSOTG_T::CTL: OTGEN Mask */
#define HSOTG_CTL_WKEN_Pos (5) /*!< HSOTG_T::CTL: WKEN Position */
#define HSOTG_CTL_WKEN_Msk (0x1ul << HSOTG_CTL_WKEN_Pos) /*!< HSOTG_T::CTL: WKEN Mask */
#define HSOTG_PHYCTL_OTGPHYEN_Pos (0) /*!< HSOTG_T::PHYCTL: OTGPHYEN Position */
#define HSOTG_PHYCTL_OTGPHYEN_Msk (0x1ul << HSOTG_PHYCTL_OTGPHYEN_Pos) /*!< HSOTG_T::PHYCTL: OTGPHYEN Mask */
#define HSOTG_PHYCTL_IDDETEN_Pos (1) /*!< HSOTG_T::PHYCTL: IDDETEN Position */
#define HSOTG_PHYCTL_IDDETEN_Msk (0x1ul << HSOTG_PHYCTL_IDDETEN_Pos) /*!< HSOTG_T::PHYCTL: IDDETEN Mask */
#define HSOTG_PHYCTL_VBENPOL_Pos (4) /*!< HSOTG_T::PHYCTL: VBENPOL Position */
#define HSOTG_PHYCTL_VBENPOL_Msk (0x1ul << HSOTG_PHYCTL_VBENPOL_Pos) /*!< HSOTG_T::PHYCTL: VBENPOL Mask */
#define HSOTG_PHYCTL_VBSTSPOL_Pos (5) /*!< HSOTG_T::PHYCTL: VBSTSPOL Position */
#define HSOTG_PHYCTL_VBSTSPOL_Msk (0x1ul << HSOTG_PHYCTL_VBSTSPOL_Pos) /*!< HSOTG_T::PHYCTL: VBSTSPOL Mask */
#define HSOTG_INTEN_ROLECHGIEN_Pos (0) /*!< HSOTG_T::INTEN: ROLECHGIEN Position */
#define HSOTG_INTEN_ROLECHGIEN_Msk (0x1ul << HSOTG_INTEN_ROLECHGIEN_Pos) /*!< HSOTG_T::INTEN: ROLECHGIEN Mask */
#define HSOTG_INTEN_VBEIEN_Pos (1) /*!< HSOTG_T::INTEN: VBEIEN Position */
#define HSOTG_INTEN_VBEIEN_Msk (0x1ul << HSOTG_INTEN_VBEIEN_Pos) /*!< HSOTG_T::INTEN: VBEIEN Mask */
#define HSOTG_INTEN_SRPFIEN_Pos (2) /*!< HSOTG_T::INTEN: SRPFIEN Position */
#define HSOTG_INTEN_SRPFIEN_Msk (0x1ul << HSOTG_INTEN_SRPFIEN_Pos) /*!< HSOTG_T::INTEN: SRPFIEN Mask */
#define HSOTG_INTEN_HNPFIEN_Pos (3) /*!< HSOTG_T::INTEN: HNPFIEN Position */
#define HSOTG_INTEN_HNPFIEN_Msk (0x1ul << HSOTG_INTEN_HNPFIEN_Pos) /*!< HSOTG_T::INTEN: HNPFIEN Mask */
#define HSOTG_INTEN_GOIDLEIEN_Pos (4) /*!< HSOTG_T::INTEN: GOIDLEIEN Position */
#define HSOTG_INTEN_GOIDLEIEN_Msk (0x1ul << HSOTG_INTEN_GOIDLEIEN_Pos) /*!< HSOTG_T::INTEN: GOIDLEIEN Mask */
#define HSOTG_INTEN_IDCHGIEN_Pos (5) /*!< HSOTG_T::INTEN: IDCHGIEN Position */
#define HSOTG_INTEN_IDCHGIEN_Msk (0x1ul << HSOTG_INTEN_IDCHGIEN_Pos) /*!< HSOTG_T::INTEN: IDCHGIEN Mask */
#define HSOTG_INTEN_PDEVIEN_Pos (6) /*!< HSOTG_T::INTEN: PDEVIEN Position */
#define HSOTG_INTEN_PDEVIEN_Msk (0x1ul << HSOTG_INTEN_PDEVIEN_Pos) /*!< HSOTG_T::INTEN: PDEVIEN Mask */
#define HSOTG_INTEN_HOSTIEN_Pos (7) /*!< HSOTG_T::INTEN: HOSTIEN Position */
#define HSOTG_INTEN_HOSTIEN_Msk (0x1ul << HSOTG_INTEN_HOSTIEN_Pos) /*!< HSOTG_T::INTEN: HOSTIEN Mask */
#define HSOTG_INTEN_BVLDCHGIEN_Pos (8) /*!< HSOTG_T::INTEN: BVLDCHGIEN Position */
#define HSOTG_INTEN_BVLDCHGIEN_Msk (0x1ul << HSOTG_INTEN_BVLDCHGIEN_Pos) /*!< HSOTG_T::INTEN: BVLDCHGIEN Mask */
#define HSOTG_INTEN_AVLDCHGIEN_Pos (9) /*!< HSOTG_T::INTEN: AVLDCHGIEN Position */
#define HSOTG_INTEN_AVLDCHGIEN_Msk (0x1ul << HSOTG_INTEN_AVLDCHGIEN_Pos) /*!< HSOTG_T::INTEN: AVLDCHGIEN Mask */
#define HSOTG_INTEN_VBCHGIEN_Pos (10) /*!< HSOTG_T::INTEN: VBCHGIEN Position */
#define HSOTG_INTEN_VBCHGIEN_Msk (0x1ul << HSOTG_INTEN_VBCHGIEN_Pos) /*!< HSOTG_T::INTEN: VBCHGIEN Mask */
#define HSOTG_INTEN_SECHGIEN_Pos (11) /*!< HSOTG_T::INTEN: SECHGIEN Position */
#define HSOTG_INTEN_SECHGIEN_Msk (0x1ul << HSOTG_INTEN_SECHGIEN_Pos) /*!< HSOTG_T::INTEN: SECHGIEN Mask */
#define HSOTG_INTEN_SRPDETIEN_Pos (13) /*!< HSOTG_T::INTEN: SRPDETIEN Position */
#define HSOTG_INTEN_SRPDETIEN_Msk (0x1ul << HSOTG_INTEN_SRPDETIEN_Pos) /*!< HSOTG_T::INTEN: SRPDETIEN Mask */
#define HSOTG_INTSTS_ROLECHGIF_Pos (0) /*!< HSOTG_T::INTSTS: ROLECHGIF Position */
#define HSOTG_INTSTS_ROLECHGIF_Msk (0x1ul << HSOTG_INTSTS_ROLECHGIF_Pos) /*!< HSOTG_T::INTSTS: ROLECHGIF Mask */
#define HSOTG_INTSTS_VBEIF_Pos (1) /*!< HSOTG_T::INTSTS: VBEIF Position */
#define HSOTG_INTSTS_VBEIF_Msk (0x1ul << HSOTG_INTSTS_VBEIF_Pos) /*!< HSOTG_T::INTSTS: VBEIF Mask */
#define HSOTG_INTSTS_SRPFIF_Pos (2) /*!< HSOTG_T::INTSTS: SRPFIF Position */
#define HSOTG_INTSTS_SRPFIF_Msk (0x1ul << HSOTG_INTSTS_SRPFIF_Pos) /*!< HSOTG_T::INTSTS: SRPFIF Mask */
#define HSOTG_INTSTS_HNPFIF_Pos (3) /*!< HSOTG_T::INTSTS: HNPFIF Position */
#define HSOTG_INTSTS_HNPFIF_Msk (0x1ul << HSOTG_INTSTS_HNPFIF_Pos) /*!< HSOTG_T::INTSTS: HNPFIF Mask */
#define HSOTG_INTSTS_GOIDLEIF_Pos (4) /*!< HSOTG_T::INTSTS: GOIDLEIF Position */
#define HSOTG_INTSTS_GOIDLEIF_Msk (0x1ul << HSOTG_INTSTS_GOIDLEIF_Pos) /*!< HSOTG_T::INTSTS: GOIDLEIF Mask */
#define HSOTG_INTSTS_IDCHGIF_Pos (5) /*!< HSOTG_T::INTSTS: IDCHGIF Position */
#define HSOTG_INTSTS_IDCHGIF_Msk (0x1ul << HSOTG_INTSTS_IDCHGIF_Pos) /*!< HSOTG_T::INTSTS: IDCHGIF Mask */
#define HSOTG_INTSTS_PDEVIF_Pos (6) /*!< HSOTG_T::INTSTS: PDEVIF Position */
#define HSOTG_INTSTS_PDEVIF_Msk (0x1ul << HSOTG_INTSTS_PDEVIF_Pos) /*!< HSOTG_T::INTSTS: PDEVIF Mask */
#define HSOTG_INTSTS_HOSTIF_Pos (7) /*!< HSOTG_T::INTSTS: HOSTIF Position */
#define HSOTG_INTSTS_HOSTIF_Msk (0x1ul << HSOTG_INTSTS_HOSTIF_Pos) /*!< HSOTG_T::INTSTS: HOSTIF Mask */
#define HSOTG_INTSTS_BVLDCHGIF_Pos (8) /*!< HSOTG_T::INTSTS: BVLDCHGIF Position */
#define HSOTG_INTSTS_BVLDCHGIF_Msk (0x1ul << HSOTG_INTSTS_BVLDCHGIF_Pos) /*!< HSOTG_T::INTSTS: BVLDCHGIF Mask */
#define HSOTG_INTSTS_AVLDCHGIF_Pos (9) /*!< HSOTG_T::INTSTS: AVLDCHGIF Position */
#define HSOTG_INTSTS_AVLDCHGIF_Msk (0x1ul << HSOTG_INTSTS_AVLDCHGIF_Pos) /*!< HSOTG_T::INTSTS: AVLDCHGIF Mask */
#define HSOTG_INTSTS_VBCHGIF_Pos (10) /*!< HSOTG_T::INTSTS: VBCHGIF Position */
#define HSOTG_INTSTS_VBCHGIF_Msk (0x1ul << HSOTG_INTSTS_VBCHGIF_Pos) /*!< HSOTG_T::INTSTS: VBCHGIF Mask */
#define HSOTG_INTSTS_SECHGIF_Pos (11) /*!< HSOTG_T::INTSTS: SECHGIF Position */
#define HSOTG_INTSTS_SECHGIF_Msk (0x1ul << HSOTG_INTSTS_SECHGIF_Pos) /*!< HSOTG_T::INTSTS: SECHGIF Mask */
#define HSOTG_INTSTS_SRPDETIF_Pos (13) /*!< HSOTG_T::INTSTS: SRPDETIF Position */
#define HSOTG_INTSTS_SRPDETIF_Msk (0x1ul << HSOTG_INTSTS_SRPDETIF_Pos) /*!< HSOTG_T::INTSTS: SRPDETIF Mask */
#define HSOTG_STATUS_OVERCUR_Pos (0) /*!< HSOTG_T::STATUS: OVERCUR Position */
#define HSOTG_STATUS_OVERCUR_Msk (0x1ul << HSOTG_STATUS_OVERCUR_Pos) /*!< HSOTG_T::STATUS: OVERCUR Mask */
#define HSOTG_STATUS_IDSTS_Pos (1) /*!< HSOTG_T::STATUS: IDSTS Position */
#define HSOTG_STATUS_IDSTS_Msk (0x1ul << HSOTG_STATUS_IDSTS_Pos) /*!< HSOTG_T::STATUS: IDSTS Mask */
#define HSOTG_STATUS_SESSEND_Pos (2) /*!< HSOTG_T::STATUS: SESSEND Position */
#define HSOTG_STATUS_SESSEND_Msk (0x1ul << HSOTG_STATUS_SESSEND_Pos) /*!< HSOTG_T::STATUS: SESSEND Mask */
#define HSOTG_STATUS_BVLD_Pos (3) /*!< HSOTG_T::STATUS: BVLD Position */
#define HSOTG_STATUS_BVLD_Msk (0x1ul << HSOTG_STATUS_BVLD_Pos) /*!< HSOTG_T::STATUS: BVLD Mask */
#define HSOTG_STATUS_AVLD_Pos (4) /*!< HSOTG_T::STATUS: AVLD Position */
#define HSOTG_STATUS_AVLD_Msk (0x1ul << HSOTG_STATUS_AVLD_Pos) /*!< HSOTG_T::STATUS: AVLD Mask */
#define HSOTG_STATUS_VBUSVLD_Pos (5) /*!< HSOTG_T::STATUS: VBUSVLD Position */
#define HSOTG_STATUS_VBUSVLD_Msk (0x1ul << HSOTG_STATUS_VBUSVLD_Pos) /*!< HSOTG_T::STATUS: VBUSVLD Mask */
#define HSOTG_STATUS_ASPERI_Pos (6) /*!< HSOTG_T::STATUS: ASPERI Position */
#define HSOTG_STATUS_ASPERI_Msk (0x1ul << HSOTG_STATUS_ASPERI_Pos) /*!< HSOTG_T::STATUS: ASPERI Mask */
#define HSOTG_STATUS_ASHOST_Pos (7) /*!< HSOTG_T::STATUS: ASHOST Position */
#define HSOTG_STATUS_ASHOST_Msk (0x1ul << HSOTG_STATUS_ASHOST_Pos) /*!< HSOTG_T::STATUS: ASHOST Mask */
/**@}*/ /* HSOTG_CONST */
/**@}*/ /* end of HSOTG register group */
/*---------------------- Cyclic Redundancy Check Controller -------------------------*/
/**
@addtogroup CRC Cyclic Redundancy Check Controller(CRC)
Memory Mapped Structure for CRC Controller
@{ */
typedef struct {
/**
* @var CRC_T::CTL
* Offset: 0x00 CRC Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CRCEN |CRC Channel Enable Bit
* | | |0 = No effect.
* | | |1 = CRC operation Enabled.
* |[1] |CHKSINIT |Checksum Initialization
* | | |0 = No effect.
* | | |1 = Initial checksum value by auto reload CRC_SEED register value to CRC_CHECKSUM register value.
* | | |Note: This bit will be cleared automatically.
* |[24] |DATREV |Write Data Bit Order Reverse
* | | |This bit is used to enable the bit order reverse function per byte for write data value in CRC_DAT register.
* | | |0 = Bit order reversed for CRC write data in Disabled.
* | | |1 = Bit order reversed for CRC write data in Enabled (per byte).
* | | |Note: If the write data is 0xAABBCCDD, the bit order reverse for CRC write data in is 0x55DD33BB.
* |[25] |CHKSREV |Checksum Bit Order Reverse
* | | |This bit is used to enable the bit order reverse function for checksum result in CRC_CHECKSUM register.
* | | |0 = Bit order reverse for CRC checksum Disabled.
* | | |1 = Bit order reverse for CRC checksum Enabled.
* | | |Note: If the checksum result is 0xDD7B0F2E, the bit order reverse for CRC checksum is 0x74F0DEBB.
* |[26] |DATFMT |Write Data 1's Complement
* | | |This bit is used to enable the 1's complement function for write data value in CRC_DAT register.
* | | |0 = 1's complement for CRC writes data in Disabled.
* | | |1 = 1's complement for CRC writes data in Enabled.
* |[27] |CHKSFMT |Checksum 1's Complement
* | | |This bit is used to enable the 1's complement function for checksum result in CRC_CHECKSUM register.
* | | |0 = 1's complement for CRC checksum Disabled.
* | | |1 = 1's complement for CRC checksum Enabled.
* |[29:28] |DATLEN |CPU Write Data Length
* | | |This field indicates the write data length.
* | | |00 = Data length is 8-bit mode.
* | | |01 = Data length is 16-bit mode.
* | | |1x = Data length is 32-bit mode.
* | | |Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0]
* |[31:30] |CRCMODE |CRC Polynomial Mode
* | | |This field indicates the CRC operation polynomial mode.
* | | |00 = CRC-CCITT Polynomial mode.
* | | |01 = CRC-8 Polynomial mode.
* | | |10 = CRC-16 Polynomial mode.
* | | |11 = CRC-32 Polynomial mode.
* @var CRC_T::DAT
* Offset: 0x04 CRC Write Data Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |DATA |CRC Write Data Bits
* | | |User can write data directly by CPU mode or use PDMA function to write data to this field to perform CRC operation.
* | | |Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0].
* @var CRC_T::SEED
* Offset: 0x08 CRC Seed Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |SEED |CRC Seed Value
* | | |This field indicates the CRC seed value.
* | | |Note: This field will be reloaded as checksum initial value (CRC_CHECKSUM register) after perform CHKSINIT (CRC_CTL[1]).
* @var CRC_T::CHECKSUM
* Offset: 0x0C CRC Checksum Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |CHECKSUM |CRC Checksum Results
* | | |This field indicates the CRC checksum result.
*/
__IO uint32_t CTL; /*!< [0x0000] CRC Control Register */
__IO uint32_t DAT; /*!< [0x0004] CRC Write Data Register */
__IO uint32_t SEED; /*!< [0x0008] CRC Seed Register */
__I uint32_t CHECKSUM; /*!< [0x000c] CRC Checksum Register */
} CRC_T;
/**
@addtogroup CRC_CONST CRC Bit Field Definition
Constant Definitions for CRC Controller
@{ */
#define CRC_CTL_CRCEN_Pos (0) /*!< CRC_T::CTL: CRCEN Position */
#define CRC_CTL_CRCEN_Msk (0x1ul << CRC_CTL_CRCEN_Pos) /*!< CRC_T::CTL: CRCEN Mask */
#define CRC_CTL_CHKSINIT_Pos (1) /*!< CRC_T::CTL: CHKSINIT Position */
#define CRC_CTL_CHKSINIT_Msk (0x1ul << CRC_CTL_CHKSINIT_Pos) /*!< CRC_T::CTL: CHKSINIT Mask */
#define CRC_CTL_DATREV_Pos (24) /*!< CRC_T::CTL: DATREV Position */
#define CRC_CTL_DATREV_Msk (0x1ul << CRC_CTL_DATREV_Pos) /*!< CRC_T::CTL: DATREV Mask */
#define CRC_CTL_CHKSREV_Pos (25) /*!< CRC_T::CTL: CHKSREV Position */
#define CRC_CTL_CHKSREV_Msk (0x1ul << CRC_CTL_CHKSREV_Pos) /*!< CRC_T::CTL: CHKSREV Mask */
#define CRC_CTL_DATFMT_Pos (26) /*!< CRC_T::CTL: DATFMT Position */
#define CRC_CTL_DATFMT_Msk (0x1ul << CRC_CTL_DATFMT_Pos) /*!< CRC_T::CTL: DATFMT Mask */
#define CRC_CTL_CHKSFMT_Pos (27) /*!< CRC_T::CTL: CHKSFMT Position */
#define CRC_CTL_CHKSFMT_Msk (0x1ul << CRC_CTL_CHKSFMT_Pos) /*!< CRC_T::CTL: CHKSFMT Mask */
#define CRC_CTL_DATLEN_Pos (28) /*!< CRC_T::CTL: DATLEN Position */
#define CRC_CTL_DATLEN_Msk (0x3ul << CRC_CTL_DATLEN_Pos) /*!< CRC_T::CTL: DATLEN Mask */
#define CRC_CTL_CRCMODE_Pos (30) /*!< CRC_T::CTL: CRCMODE Position */
#define CRC_CTL_CRCMODE_Msk (0x3ul << CRC_CTL_CRCMODE_Pos) /*!< CRC_T::CTL: CRCMODE Mask */
#define CRC_DAT_DATA_Pos (0) /*!< CRC_T::DAT: DATA Position */
#define CRC_DAT_DATA_Msk (0xfffffffful << CRC_DAT_DATA_Pos) /*!< CRC_T::DAT: DATA Mask */
#define CRC_SEED_SEED_Pos (0) /*!< CRC_T::SEED: SEED Position */
#define CRC_SEED_SEED_Msk (0xfffffffful << CRC_SEED_SEED_Pos) /*!< CRC_T::SEED: SEED Mask */
#define CRC_CHECKSUM_CHECKSUM_Pos (0) /*!< CRC_T::CHECKSUM: CHECKSUM Position */
#define CRC_CHECKSUM_CHECKSUM_Msk (0xfffffffful << CRC_CHECKSUM_CHECKSUM_Pos) /*!< CRC_T::CHECKSUM: CHECKSUM Mask */
/**@}*/ /* CRC_CONST */
/**@}*/ /* end of CRC register group */
/*---------------------- Cryptographic Accelerator -------------------------*/
/**
@addtogroup CRPT Cryptographic Accelerator(CRPT)
Memory Mapped Structure for Cryptographic Accelerator
@{ */
typedef struct {
/**
* @var CRPT_T::INTEN
* Offset: 0x00 Crypto Interrupt Enable Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |AESIEN |AES Interrupt Enable Control
* | | |0 = AES interrupt Disabled.
* | | |1 = AES interrupt Enabled.
* | | |In DMA mode, an interrupt will be triggered when amount of data set in AES_DMA_CNT is fed into the AES engine.
* | | |In Non-DMA mode, an interrupt will be triggered when the AES engine finishes the operation.
* |[1] |AESEIEN |AES Error Flag Enable Control
* | | |0 = AES error interrupt flag Disabled.
* | | |1 = AES error interrupt flag Enabled.
* |[8] |TDESIEN |TDES/DES Interrupt Enable Control
* | | |0 = TDES/DES interrupt Disabled.
* | | |1 = TDES/DES interrupt Enabled.
* | | |In DMA mode, an interrupt will be triggered when amount of data set in TDES_DMA_CNT is fed into the TDES engine.
* | | |In Non-DMA mode, an interrupt will be triggered when the TDES engine finishes the operation.
* |[9] |TDESEIEN |TDES/DES Error Flag Enable Control
* | | |0 = TDES/DES error interrupt flag Disabled.
* | | |1 = TDES/DES error interrupt flag Enabled.
* |[16] |PRNGIEN |PRNG Interrupt Enable Control
* | | |0 = PRNG interrupt Disabled.
* | | |1 = PRNG interrupt Enabled.
* |[22] |ECCIEN |ECC Interrupt Enable Control
* | | |0 = ECC interrupt Disabled.
* | | |1 = ECC interrupt Enabled.
* | | |In DMA mode, an interrupt will be triggered when amount of data set in ECC_DMA_CNT is fed into the ECC engine.
* | | |In Non-DMA mode, an interrupt will be triggered when the ECC engine finishes the operation.
* |[23] |ECCEIEN |ECC Error Interrupt Enable Control
* | | |0 = ECC error interrupt flag Disabled.
* | | |1 = ECC error interrupt flag Enabled.
* |[24] |HMACIEN |SHA/HMAC Interrupt Enable Control
* | | |0 = SHA/HMAC interrupt Disabled.
* | | |1 = SHA/HMAC interrupt Enabled.
* | | |In DMA mode, an interrupt will be triggered when amount of data set in SHA _DMA_CNT is fed into the SHA/HMAC engine
* | | |In Non-DMA mode, an interrupt will be triggered when the SHA/HMAC engine finishes the operation.
* |[25] |HMACEIEN |SHA/HMAC Error Interrupt Enable Control
* | | |0 = SHA/HMAC error interrupt flag Disabled.
* | | |1 = SHA/HMAC error interrupt flag Enabled.
* @var CRPT_T::INTSTS
* Offset: 0x04 Crypto Interrupt Flag
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |AESIF |AES Finish Interrupt Flag
* | | |This bit is cleared by writing 1, and it has no effect by writing 0.
* | | |0 = No AES interrupt.
* | | |= AES encryption/decryption done interrupt.
* |[1] |AESEIF |AES Error Flag
* | | |This bit is cleared by writing 1, and it has no effect by writing 0.
* | | |0 = No AES error.
* | | |1 = AES encryption/decryption done interrupt.
* |[8] |TDESIF |TDES/DES Finish Interrupt Flag
* | | |This bit is cleared by writing 1, and it has no effect by writing 0.
* | | |0 = No TDES/DES interrupt.
* | | |1 = TDES/DES encryption/decryption done interrupt.
* |[9] |TDESEIF |TDES/DES Error Flag
* | | |This bit includes the operating and setting error
* | | |The detailed flag is shown in the CRPT_TDES_STS register
* | | |This includes operating and setting error.
* | | |This bit is cleared by writing 1, and it has no effect by writing 0.
* | | |0 = No TDES/DES error.
* | | |1 = TDES/DES encryption/decryption error interrupt.
* |[16] |PRNGIF |PRNG Finish Interrupt Flag
* | | |This bit is cleared by writing 1, and it has no effect by writing 0.
* | | |0 = No PRNG interrupt.
* | | |1 = PRNG key generation done interrupt.
* |[22] |ECCIF |ECC Finish Interrupt Flag
* | | |This bit is cleared by writing 1, and it has no effect by writing 0.
* | | |0 = No ECC interrupt.
* | | |1 = ECC operation done interrupt.
* |[23] |ECCEIF |ECC Error Flag
* | | |This register includes operating and setting error. The detail flag is shown in CRPT_ECC_STS register.
* | | |This bit is cleared by writing 1, and it has no effect by writing 0.
* | | |0 = No ECC error.
* | | |1 = ECC error interrupt.
* |[24] |HMACIF |SHA/HMAC Finish Interrupt Flag
* | | |This bit is cleared by writing 1, and it has no effect by writing 0.
* | | |0 = No SHA/HMAC interrupt.
* | | |1 = SHA/HMAC operation done interrupt.
* |[25] |HMACEIF |SHA/HMAC Error Flag
* | | |This register includes operating and setting error. The detail flag is shown in CRPT_HMAC_STS register.
* | | |This bit is cleared by writing 1, and it has no effect by writing 0.
* | | |0 = No SHA/HMAC error.
* | | |1 = SHA/HMAC error interrupt.
* @var CRPT_T::PRNG_CTL
* Offset: 0x08 PRNG Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |START |Start PRNG Engine
* | | |0 = Stop PRNG engine.
* | | |1 = Generate new key and store the new key to register CRPT_PRNG_KEYx , which will be cleared when the new key is generated.
* |[1] |SEEDRLD |Reload New Seed for PRNG Engine
* | | |0 = Generating key based on the current seed.
* | | |1 = Reload new seed.
* |[3:2] |KEYSZ |PRNG Generate Key Size
* | | |00 = 64 bits.
* | | |01 = 128 bits.
* | | |10 = 192 bits.
* | | |11 = 256 bits.
* |[8] |BUSY |PRNG Busy (Read Only)
* | | |0 = PRNG engine is idle.
* | | |1 = Indicate that the PRNG engine is generating CRPT_PRNG_KEYx.
* @var CRPT_T::PRNG_SEED
* Offset: 0x0C Seed for PRNG
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |SEED |Seed for PRNG (Write Only)
* | | |The bits store the seed for PRNG engine.
* @var CRPT_T::PRNG_KEY[8]
* Offset: 0x10 ~ 0x2C PRNG Generated Key0 ~ Key7
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |KEY |Store PRNG Generated Key (Read Only)
* | | |The bits store the key that is generated by PRNG.
* @var CRPT_T::AES_FDBCK[4]
* Offset: 0x50 ~ 0x5C AES Engine Output Feedback Data after Cryptographic Operation
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |FDBCK |AES Feedback Information
* | | |The feedback value is 128 bits in size.
* | | |The AES engine uses the data from CRPT_AES_FDBCKx as the data inputted to CRPT_AESn_IVx for the next block in DMA cascade mode.
* | | |The AES engine outputs feedback information for IV in the next block's operation
* | | |Software can use this feedback information to implement more than four DMA channels
* | | |Software can store that feedback value temporarily
* | | |After switching back, fill the stored feedback value to this register in the same channel operation, and then continue the operation with the original setting.
* @var CRPT_T::TDES_FDBCKH
* Offset: 0x60 TDES/DES Engine Output Feedback High Word Data after Cryptographic Operation
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |FDBCK |TDES/DES Feedback
* | | |The feedback value is 64 bits in size.
* | | |The TDES/DES engine uses the data from {CRPT_TDES_FDBCKH, CRPT_TDES_FDBCKL} as the data inputted to {CRPT_TDESn_IVH, CRPT_TDESn_IVL} for the next block in DMA cascade mode
* | | |The feedback register is for CBC, CFB, and OFB mode.
* | | |TDES/DES engine outputs feedback information for IV in the next block's operation
* | | |Software can use this feedback information to implement more than four DMA channels
* | | |Software can store that feedback value temporarily
* | | |After switching back, fill the stored feedback value to this register in the same channel operation
* | | |Then can continue the operation with the original setting.
* @var CRPT_T::TDES_FDBCKL
* Offset: 0x64 TDES/DES Engine Output Feedback Low Word Data after Cryptographic Operation
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |FDBCK |TDES/DES Feedback
* | | |The feedback value is 64 bits in size.
* | | |The TDES/DES engine uses the data from {CRPT_TDES_FDBCKH, CRPT_TDES_FDBCKL} as the data inputted to {CRPT_TDESn_IVH, CRPT_TDESn_IVL} for the next block in DMA cascade mode
* | | |The feedback register is for CBC, CFB, and OFB mode.
* | | |TDES/DES engine outputs feedback information for IV in the next block's operation
* | | |Software can use this feedback information to implement more than four DMA channels
* | | |Software can store that feedback value temporarily
* | | |After switching back, fill the stored feedback value to this register in the same channel operation
* | | |Then can continue the operation with the original setting.
* @var CRPT_T::AES_CTL
* Offset: 0x100 AES Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |START |AES Engine Start
* | | |0 = No effect.
* | | |1 = Start AES engine. BUSY flag will be set.
* | | |Note: This bit is always 0 when it's read back.
* |[1] |STOP |AES Engine Stop
* | | |0 = No effect.
* | | |1 = Stop AES engine.
* | | |Note: This bit is always 0 when it's read back.
* |[3:2] |KEYSZ |AES Key Size
* | | |This bit defines three different key size for AES operation.
* | | |2'b00 = 128 bits key.
* | | |2'b01 = 192 bits key.
* | | |2'b10 = 256 bits key.
* | | |2'b11 = Reserved.
* | | |If the AES accelerator is operating and the corresponding flag BUSY is 1, updating this register has no effect.
* |[5] |DMALAST |AES Last Block
* | | |In DMA mode, this bit must be set as beginning the last DMA cascade round.
* | | |In Non-DMA mode, this bit must be set when feeding in the last block of data in ECB, CBC, CTR, OFB, and CFB mode, and feeding in the (last-1) block of data at CBC-CS1, CBC-CS2, and CBC-CS3 mode.
* | | |This bit is always 0 when it's read back. Must be written again once START is triggered.
* |[6] |DMACSCAD |AES Engine DMA with Cascade Mode
* | | |0 = DMA cascade function Disabled.
* | | |1 = In DMA cascade mode, software can update DMA source address register, destination address register, and byte count register during a cascade operation, without finishing the accelerator operation.
* |[7] |DMAEN |AES Engine DMA Enable Control
* | | |0 = AES DMA engine Disabled.
* | | |The AES engine operates in Non-DMA mode, and gets data from the port CRPT_AES_DATIN.
* | | |1 = AES_DMA engine Enabled.
* | | |The AES engine operates in DMA mode, and data movement from/to the engine is done by DMA logic.
* |[15:8] |OPMODE |AES Engine Operation Modes
* | | |0x00 = ECB (Electronic Codebook Mode) 0x01 = CBC (Cipher Block Chaining Mode).
* | | |0x02 = CFB (Cipher Feedback Mode).
* | | |0x03 = OFB (Output Feedback Mode).
* | | |0x04 = CTR (Counter Mode).
* | | |0x10 = CBC-CS1 (CBC Ciphertext-Stealing 1 Mode).
* | | |0x11 = CBC-CS2 (CBC Ciphertext-Stealing 2 Mode).
* | | |0x12 = CBC-CS3 (CBC Ciphertext-Stealing 3 Mode).
* |[16] |ENCRPT |AES Encryption/Decryption
* | | |0 = AES engine executes decryption operation.
* | | |1 = AES engine executes encryption operation.
* |[22] |OUTSWAP |AES Engine Output Data Swap
* | | |0 = Keep the original order.
* | | |1 = The order that CPU outputs data from the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}.
* |[23] |INSWAP |AES Engine Input Data Swap
* | | |0 = Keep the original order.
* | | |1 = The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}.
* |[25:24] |CHANNEL |AES Engine Working Channel
* | | |00 = Current control register setting is for channel 0.
* | | |01 = Current control register setting is for channel 1.
* | | |10 = Current control register setting is for channel 2.
* | | |11 = Current control register setting is for channel 3.
* |[30:26] |KEYUNPRT |Unprotect Key
* | | |Writing 0 to CRPT_AES_CTL[31] and "10110" to CRPT_AES_CTL[30:26] is to unprotect the AES key.
* | | |The KEYUNPRT can be read and written
* | | |When it is written as the AES engine is operating, BUSY flag is 1, there would be no effect on KEYUNPRT.
* |[31] |KEYPRT |Protect Key
* | | |Read as a flag to reflect KEYPRT.
* | | |0 = No effect.
* | | |1 = Protect the content of the AES key from reading
* | | |The return value for reading CRPT_AESn_KEYx is not the content of the registers CRPT_AESn_KEYx
* | | |Once it is set, it can be cleared by asserting KEYUNPRT
* | | |And the key content would be cleared as well.
* @var CRPT_T::AES_STS
* Offset: 0x104 AES Engine Flag
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |BUSY |AES Engine Busy
* | | |0 = The AES engine is idle or finished.
* | | |1 = The AES engine is under processing.
* |[8] |INBUFEMPTY|AES Input Buffer Empty
* | | |0 = There are some data in input buffer waiting for the AES engine to process.
* | | |1 = AES input buffer is empty
* | | |Software needs to feed data to the AES engine
* | | |Otherwise, the AES engine will be pending to wait for input data.
* |[9] |INBUFFULL |AES Input Buffer Full Flag
* | | |0 = AES input buffer is not full. Software can feed the data into the AES engine.
* | | |1 = AES input buffer is full
* | | |Software cannot feed data to the AES engine
* | | |Otherwise, the flag INBUFERR will be set to 1.
* |[10] |INBUFERR |AES Input Buffer Error Flag
* | | |0 = No error.
* | | |1 = Error happens during feeding data to the AES engine.
* |[12] |CNTERR |CRPT_AESn_CNT Setting Error
* | | |0 = No error in CRPT_AESn_CNT setting.
* | | |1 = CRPT_AESn_CNT is not a multiply of 16 in ECB, CBC, CFB, OFB, and CTR mode.
* |[16] |OUTBUFEMPTY|AES Out Buffer Empty
* | | |0 = AES output buffer is not empty. There are some valid data kept in output buffer.
* | | |1 = AES output buffer is empty
* | | |Software cannot get data from CRPT_AES_DATOUT
* | | |Otherwise, the flag OUTBUFERR will be set to 1 since the output buffer is empty.
* |[17] |OUTBUFFULL|AES Out Buffer Full Flag
* | | |0 = AES output buffer is not full.
* | | |1 = AES output buffer is full, and software needs to get data from CRPT_AES_DATOUT
* | | |Otherwise, the AES engine will be pending since the output buffer is full.
* |[18] |OUTBUFERR |AES Out Buffer Error Flag
* | | |0 = No error.
* | | |1 = Error happens during getting the result from AES engine.
* |[20] |BUSERR |AES DMA Access Bus Error Flag
* | | |0 = No error.
* | | |1 = Bus error will stop DMA operation and AES engine.
* @var CRPT_T::AES_DATIN
* Offset: 0x108 AES Engine Data Input Port Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |DATIN |AES Engine Input Port
* | | |CPU feeds data to AES engine through this port by checking CRPT_AES_STS. Feed data as INBUFFULL is 0.
* @var CRPT_T::AES_DATOUT
* Offset: 0x10C AES Engine Data Output Port Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |DATOUT |AES Engine Output Port
* | | |CPU gets results from the AES engine through this port by checking CRPT_AES_STS
* | | |Get data as OUTBUFEMPTY is 0.
* @var CRPT_T::AES0_KEY[8]
* Offset: 0x110 ~ 0x12C AES Key Word 0 ~ 7 Register for Channel 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |KEY |CRPT_AESn_KEYx
* | | |The KEY keeps the security key for AES operation.
* | | |n = 0, 1..3.
* | | |x = 0, 1..7.
* | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key
* | | |{CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 128-bit security key for AES operation
* | | |{CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 192-bit security key for AES operation
* | | |{CRPT_AESn_KEY7, CRPT_AESn_KEY6, CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 256-bit security key for AES operation.
* @var CRPT_T::AES0_IV[4]
* Offset: 0x130 ~ 0x13C AES Initial Vector Word 0 ~ 3 Register for Channel 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |IV |AES Initial Vectors
* | | |n = 0, 1..3.
* | | |x = 0, 1..3.
* | | |Four initial vectors (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) are for AES operating in CBC, CFB, and OFB mode
* | | |Four registers (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) act as Nonce counter when the AES engine is operating in CTR mode.
* @var CRPT_T::AES0_SADDR
* Offset: 0x140 AES DMA Source Address Register for Channel 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |SADDR |AES DMA Source Address
* | | |The AES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO
* | | |The SADDR keeps the source address of the data buffer where the source text is stored
* | | |Based on the source address, the AES accelerator can read the plain text from system memory and do AES operation
* | | |The start of source address should be located at word boundary
* | | |In other words, bit 1 and 0 of SADDR are ignored.
* | | |SADDR can be read and written
* | | |Writing to SADDR while the AES accelerator is operating doesn't affect the current AES operation
* | | |But the value of SADDR will be updated later on
* | | |Consequently, software can prepare the DMA source address for the next AES operation.
* | | |In DMA mode, software can update the next CRPT_AESn_SADDR before triggering START.
* | | |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same.
* @var CRPT_T::AES0_DADDR
* Offset: 0x144 AES DMA Destination Address Register for Channel 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |DADDR |AES DMA Destination Address
* | | |The AES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO
* | | |The DADDR keeps the destination address of the data buffer where the engine output's text will be stored
* | | |Based on the destination address, the AES accelerator can write the cipher text back to system memory after the AES operation is finished
* | | |The start of destination address should be located at word boundary
* | | |In other words, bit 1 and 0 of DADDR are ignored.
* | | |DADDR can be read and written
* | | |Writing to DADDR while the AES accelerator is operating doesn't affect the current AES operation
* | | |But the value of DADDR will be updated later on
* | | |Consequently, software can prepare the destination address for the next AES operation.
* | | |In DMA mode, software can update the next CRPT_AESn_DADDR before triggering START.
* | | |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same.
* @var CRPT_T::AES0_CNT
* Offset: 0x148 AES Byte Count Register for Channel 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |CNT |AES Byte Count
* | | |The CRPT_AESn_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode
* | | |The CRPT_AESn_CNT is 32-bit and the maximum of byte count is 4G bytes.
* | | |CRPT_AESn_CNT can be read and written
* | | |Writing to CRPT_AESn_CNT while the AES accelerator is operating doesn't affect the current AES operation
* | | |But the value of CRPT_AESn_CNT will be updated later on
* | | |Consequently, software can prepare the byte count of data for the next AES operation.
* | | |According to CBC-CS1, CBC-CS2, and CBC-CS3 standard, the count of operation data must be at least one block
* | | |Operations that are less than one block will output unexpected result.
* | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_AESn_CNT must be set as byte count for the last block of data before feeding in the last block of data
* | | |In Non-DMA CBC-CS1, CBC-CS2, and CBC-CS3 mode, CRPT_AESn_CNT must be set as byte count for the last two blocks of data before feeding in the last two blocks of data.
* @var CRPT_T::AES1_KEY[8]
* Offset: 0x14C ~ 0x168 AES Key Word 0 ~ 7 Register for Channel 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |KEY |CRPT_AESn_KEYx
* | | |The KEY keeps the security key for AES operation.
* | | |n = 0, 1..3.
* | | |x = 0, 1..7.
* | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key
* | | |{CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 128-bit security key for AES operation
* | | |{CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 192-bit security key for AES operation
* | | |{CRPT_AESn_KEY7, CRPT_AESn_KEY6, CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 256-bit security key for AES operation.
* @var CRPT_T::AES1_IV[4]
* Offset: 0x16C ~ 0x178 AES Initial Vector Word 0 ~ 3 Register for Channel 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |IV |AES Initial Vectors
* | | |n = 0, 1..3.
* | | |x = 0, 1..3.
* | | |Four initial vectors (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) are for AES operating in CBC, CFB, and OFB mode
* | | |Four registers (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) act as Nonce counter when the AES engine is operating in CTR mode.
* @var CRPT_T::AES1_SADDR
* Offset: 0x17C AES DMA Source Address Register for Channel 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |SADDR |AES DMA Source Address
* | | |The AES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO
* | | |The SADDR keeps the source address of the data buffer where the source text is stored
* | | |Based on the source address, the AES accelerator can read the plain text from system memory and do AES operation
* | | |The start of source address should be located at word boundary
* | | |In other words, bit 1 and 0 of SADDR are ignored.
* | | |SADDR can be read and written
* | | |Writing to SADDR while the AES accelerator is operating doesn't affect the current AES operation
* | | |But the value of SADDR will be updated later on
* | | |Consequently, software can prepare the DMA source address for the next AES operation.
* | | |In DMA mode, software can update the next CRPT_AESn_SADDR before triggering START.
* | | |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same.
* @var CRPT_T::AES1_DADDR
* Offset: 0x180 AES DMA Destination Address Register for Channel 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |DADDR |AES DMA Destination Address
* | | |The AES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO
* | | |The DADDR keeps the destination address of the data buffer where the engine output's text will be stored
* | | |Based on the destination address, the AES accelerator can write the cipher text back to system memory after the AES operation is finished
* | | |The start of destination address should be located at word boundary
* | | |In other words, bit 1 and 0 of DADDR are ignored.
* | | |DADDR can be read and written
* | | |Writing to DADDR while the AES accelerator is operating doesn't affect the current AES operation
* | | |But the value of DADDR will be updated later on
* | | |Consequently, software can prepare the destination address for the next AES operation.
* | | |In DMA mode, software can update the next CRPT_AESn_DADDR before triggering START.
* | | |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same.
* @var CRPT_T::AES1_CNT
* Offset: 0x184 AES Byte Count Register for Channel 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |CNT |AES Byte Count
* | | |The CRPT_AESn_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode
* | | |The CRPT_AESn_CNT is 32-bit and the maximum of byte count is 4G bytes.
* | | |CRPT_AESn_CNT can be read and written
* | | |Writing to CRPT_AESn_CNT while the AES accelerator is operating doesn't affect the current AES operation
* | | |But the value of CRPT_AESn_CNT will be updated later on
* | | |Consequently, software can prepare the byte count of data for the next AES operation.
* | | |According to CBC-CS1, CBC-CS2, and CBC-CS3 standard, the count of operation data must be at least one block
* | | |Operations that are less than one block will output unexpected result.
* | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_AESn_CNT must be set as byte count for the last block of data before feeding in the last block of data
* | | |In Non-DMA CBC-CS1, CBC-CS2, and CBC-CS3 mode, CRPT_AESn_CNT must be set as byte count for the last two blocks of data before feeding in the last two blocks of data.
* @var CRPT_T::AES2_KEY[8]
* Offset: 0x188 ~ 0x1A4 AES Key Word 0 ~ 7 Register for Channel 2
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |KEY |CRPT_AESn_KEYx
* | | |The KEY keeps the security key for AES operation.
* | | |n = 0, 1..3.
* | | |x = 0, 1..7.
* | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key
* | | |{CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 128-bit security key for AES operation
* | | |{CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 192-bit security key for AES operation
* | | |{CRPT_AESn_KEY7, CRPT_AESn_KEY6, CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 256-bit security key for AES operation.
* @var CRPT_T::AES2_IV[4]
* Offset: 0x1A8 ~ 0x1B4 AES Initial Vector Word 0 ~ 3 Register for Channel 2
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |IV |AES Initial Vectors
* | | |n = 0, 1..3.
* | | |x = 0, 1..3.
* | | |Four initial vectors (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) are for AES operating in CBC, CFB, and OFB mode
* | | |Four registers (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) act as Nonce counter when the AES engine is operating in CTR mode.
* @var CRPT_T::AES2_SADDR
* Offset: 0x1B8 AES DMA Source Address Register for Channel 2
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |SADDR |AES DMA Source Address
* | | |The AES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO
* | | |The SADDR keeps the source address of the data buffer where the source text is stored
* | | |Based on the source address, the AES accelerator can read the plain text from system memory and do AES operation
* | | |The start of source address should be located at word boundary
* | | |In other words, bit 1 and 0 of SADDR are ignored.
* | | |SADDR can be read and written
* | | |Writing to SADDR while the AES accelerator is operating doesn't affect the current AES operation
* | | |But the value of SADDR will be updated later on
* | | |Consequently, software can prepare the DMA source address for the next AES operation.
* | | |In DMA mode, software can update the next CRPT_AESn_SADDR before triggering START.
* | | |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same.
* @var CRPT_T::AES2_DADDR
* Offset: 0x1BC AES DMA Destination Address Register for Channel 2
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |DADDR |AES DMA Destination Address
* | | |The AES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO
* | | |The DADDR keeps the destination address of the data buffer where the engine output's text will be stored
* | | |Based on the destination address, the AES accelerator can write the cipher text back to system memory after the AES operation is finished
* | | |The start of destination address should be located at word boundary
* | | |In other words, bit 1 and 0 of DADDR are ignored.
* | | |DADDR can be read and written
* | | |Writing to DADDR while the AES accelerator is operating doesn't affect the current AES operation
* | | |But the value of DADDR will be updated later on
* | | |Consequently, software can prepare the destination address for the next AES operation.
* | | |In DMA mode, software can update the next CRPT_AESn_DADDR before triggering START.
* | | |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same.
* @var CRPT_T::AES2_CNT
* Offset: 0x1C0 AES Byte Count Register for Channel 2
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |CNT |AES Byte Count
* | | |The CRPT_AESn_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode
* | | |The CRPT_AESn_CNT is 32-bit and the maximum of byte count is 4G bytes.
* | | |CRPT_AESn_CNT can be read and written
* | | |Writing to CRPT_AESn_CNT while the AES accelerator is operating doesn't affect the current AES operation
* | | |But the value of CRPT_AESn_CNT will be updated later on
* | | |Consequently, software can prepare the byte count of data for the next AES operation.
* | | |According to CBC-CS1, CBC-CS2, and CBC-CS3 standard, the count of operation data must be at least one block
* | | |Operations that are less than one block will output unexpected result.
* | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_AESn_CNT must be set as byte count for the last block of data before feeding in the last block of data
* | | |In Non-DMA CBC-CS1, CBC-CS2, and CBC-CS3 mode, CRPT_AESn_CNT must be set as byte count for the last two blocks of data before feeding in the last two blocks of data.
* @var CRPT_T::AES3_KEY[8]
* Offset: 0x1C4 ~ 0x1E0 AES Key Word 0 ~ 7 Register for Channel 3
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |KEY |CRPT_AESn_KEYx
* | | |The KEY keeps the security key for AES operation.
* | | |n = 0, 1..3.
* | | |x = 0, 1..7.
* | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key
* | | |{CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 128-bit security key for AES operation
* | | |{CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 192-bit security key for AES operation
* | | |{CRPT_AESn_KEY7, CRPT_AESn_KEY6, CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 256-bit security key for AES operation.
* @var CRPT_T::AES3_IV[4]
* Offset: 0x1E4 ~ 0x1F0 AES Initial Vector Word 0 ~ 3 Register for Channel 3
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |IV |AES Initial Vectors
* | | |n = 0, 1..3.
* | | |x = 0, 1..3.
* | | |Four initial vectors (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) are for AES operating in CBC, CFB, and OFB mode
* | | |Four registers (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) act as Nonce counter when the AES engine is operating in CTR mode.
* @var CRPT_T::AES3_SADDR
* Offset: 0x1F4 AES DMA Source Address Register for Channel 3
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |SADDR |AES DMA Source Address
* | | |The AES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO
* | | |The SADDR keeps the source address of the data buffer where the source text is stored
* | | |Based on the source address, the AES accelerator can read the plain text from system memory and do AES operation
* | | |The start of source address should be located at word boundary
* | | |In other words, bit 1 and 0 of SADDR are ignored.
* | | |SADDR can be read and written
* | | |Writing to SADDR while the AES accelerator is operating doesn't affect the current AES operation
* | | |But the value of SADDR will be updated later on
* | | |Consequently, software can prepare the DMA source address for the next AES operation.
* | | |In DMA mode, software can update the next CRPT_AESn_SADDR before triggering START.
* | | |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same.
* @var CRPT_T::AES3_DADDR
* Offset: 0x1F8 AES DMA Destination Address Register for Channel 3
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |DADDR |AES DMA Destination Address
* | | |The AES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO
* | | |The DADDR keeps the destination address of the data buffer where the engine output's text will be stored
* | | |Based on the destination address, the AES accelerator can write the cipher text back to system memory after the AES operation is finished
* | | |The start of destination address should be located at word boundary
* | | |In other words, bit 1 and 0 of DADDR are ignored.
* | | |DADDR can be read and written
* | | |Writing to DADDR while the AES accelerator is operating doesn't affect the current AES operation
* | | |But the value of DADDR will be updated later on
* | | |Consequently, software can prepare the destination address for the next AES operation.
* | | |In DMA mode, software can update the next CRPT_AESn_DADDR before triggering START.
* | | |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same.
* @var CRPT_T::AES3_CNT
* Offset: 0x1FC AES Byte Count Register for Channel 3
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |CNT |AES Byte Count
* | | |The CRPT_AESn_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode
* | | |The CRPT_AESn_CNT is 32-bit and the maximum of byte count is 4G bytes.
* | | |CRPT_AESn_CNT can be read and written
* | | |Writing to CRPT_AESn_CNT while the AES accelerator is operating doesn't affect the current AES operation
* | | |But the value of CRPT_AESn_CNT will be updated later on
* | | |Consequently, software can prepare the byte count of data for the next AES operation.
* | | |According to CBC-CS1, CBC-CS2, and CBC-CS3 standard, the count of operation data must be at least one block
* | | |Operations that are less than one block will output unexpected result.
* | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_AESn_CNT must be set as byte count for the last block of data before feeding in the last block of data
* | | |In Non-DMA CBC-CS1, CBC-CS2, and CBC-CS3 mode, CRPT_AESn_CNT must be set as byte count for the last two blocks of data before feeding in the last two blocks of data.
* @var CRPT_T::TDES_CTL
* Offset: 0x200 TDES/DES Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |START |TDES/DES Engine Start
* | | |0 = No effect.
* | | |1 = Start TDES/DES engine. The flag BUSY would be set.
* | | |Note: The bit is always 0 when it's read back.
* |[1] |STOP |TDES/DES Engine Stop
* | | |0 = No effect.
* | | |1 = Stop TDES/DES engine.
* | | |Note: The bit is always 0 when it's read back.
* |[2] |TMODE |TDES/DES Engine Operating Mode
* | | |0 = Set DES mode for TDES/DES engine.
* | | |1 = Set Triple DES mode for TDES/DES engine.
* |[3] |3KEYS |TDES/DES Key Number
* | | |0 = Select KEY1 and KEY2 in TDES/DES engine.
* | | |1 = Triple keys in TDES/DES engine Enabled.
* |[5] |DMALAST |TDES/DES Engine Start for the Last Block
* | | |In DMA mode, this bit must be set as beginning the last DMA cascade round.
* | | |In Non-DMA mode, this bit must be set as feeding in last block of data.
* |[6] |DMACSCAD |TDES/DES Engine DMA with Cascade Mode
* | | |0 = DMA cascade function Disabled.
* | | |1 = In DMA Cascade mode, software can update DMA source address register, destination address register, and byte count register during a cascade operation, without finishing the accelerator operation.
* |[7] |DMAEN |TDES/DES Engine DMA Enable Control
* | | |0 = TDES_DMA engine Disabled.
* | | |TDES engine operates in Non-DMA mode, and get data from the port CRPT_TDES_DATIN.
* | | |1 = TDES_DMA engine Enabled.
* | | |TDES engine operates in DMA mode, and data movement from/to the engine is done by DMA logic.
* |[10:8] |OPMODE |TDES/DES Engine Operation Mode
* | | |0x00 = ECB (Electronic Codebook Mode).
* | | |0x01 = CBC (Cipher Block Chaining Mode).
* | | |0x02 = CFB (Cipher Feedback Mode).
* | | |0x03 = OFB (Output Feedback Mode).
* | | |0x04 = CTR (Counter Mode).
* | | |Others = CTR (Counter Mode).
* |[16] |ENCRPT |TDES/DES Encryption/Decryption
* | | |0 = TDES engine executes decryption operation.
* | | |1 = TDES engine executes encryption operation.
* |[21] |BLKSWAP |TDES/DES Engine Block Double Word Endian Swap
* | | |0 = Keep the original order, e.g. {WORD_H, WORD_L}.
* | | |1 = When this bit is set to 1, the TDES engine would exchange high and low word in the sequence {WORD_L, WORD_H}.
* |[22] |OUTSWAP |TDES/DES Engine Output Data Swap
* | | |0 = Keep the original order.
* | | |1 = The order that CPU outputs data from the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}.
* |[23] |INSWAP |TDES/DES Engine Input Data Swap
* | | |0 = Keep the original order.
* | | |1 = The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}.
* |[25:24] |CHANNEL |TDES/DES Engine Working Channel
* | | |00 = Current control register setting is for channel 0.
* | | |01 = Current control register setting is for channel 1.
* | | |10 = Current control register setting is for channel 2.
* | | |11 = Current control register setting is for channel 3.
* |[30:26] |KEYUNPRT |Unprotect Key
* | | |Writing 0 to CRPT_TDES_CTL [31] and "10110" to CRPT_TDES_CTL [30:26] is to unprotect TDES key.
* | | |The KEYUNPRT can be read and written
* | | |When it is written as the TDES engine is operating, BUSY flag is 1, there would be no effect on KEYUNPRT.
* |[31] |KEYPRT |Protect Key
* | | |Read as a flag to reflect KEYPRT.
* | | |0 = No effect.
* | | |1 = This bit is to protect the content of TDES key from reading
* | | |The return value for reading CRPT_ TDESn_KEYxH/L is not the content in the registers CRPT_ TDESn_KEYxH/L
* | | |Once it is set, it can be cleared by asserting KEYUNPRT
* | | |The key content would be cleared as well.
* @var CRPT_T::TDES_STS
* Offset: 0x204 TDES/DES Engine Flag
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |BUSY |TDES/DES Engine Busy
* | | |0 = TDES/DES engine is idle or finished.
* | | |1 = TDES/DES engine is under processing.
* |[8] |INBUFEMPTY|TDES/DES in Buffer Empty
* | | |0 = There are some data in input buffer waiting for the TDES/DES engine to process.
* | | |1 = TDES/DES input buffer is empty
* | | |Software needs to feed data to the TDES/DES engine
* | | |Otherwise, the TDES/DES engine will be pending to wait for input data.
* |[9] |INBUFFULL |TDES/DES in Buffer Full Flag
* | | |0 = TDES/DES input buffer is not full. Software can feed the data into the TDES/DES engine.
* | | |1 = TDES input buffer is full
* | | |Software cannot feed data to the TDES/DES engine
* | | |Otherwise, the flag INBUFERR will be set to 1.
* |[10] |INBUFERR |TDES/DES in Buffer Error Flag
* | | |0 = No error.
* | | |1 = Error happens during feeding data to the TDES/DES engine.
* |[16] |OUTBUFEMPTY|TDES/DES Output Buffer Empty Flag
* | | |0 = TDES/DES output buffer is not empty. There are some valid data kept in output buffer.
* | | |1 = TDES/DES output buffer is empty, Software cannot get data from TDES_DATA_OUT
* | | |Otherwise the flag OUTBUFERR will be set to 1, since output buffer is empty.
* |[17] |OUTBUFFULL|TDES/DES Output Buffer Full Flag
* | | |0 = TDES/DES output buffer is not full.
* | | |1 = TDES/DES output buffer is full, and software needs to get data from TDES_DATA_OUT
* | | |Otherwise, the TDES/DES engine will be pending since output buffer is full.
* |[18] |OUTBUFERR |TDES/DES Out Buffer Error Flag
* | | |0 = No error.
* | | |1 = Error happens during getting test result from TDES/DES engine.
* |[20] |BUSERR |TDES/DES DMA Access Bus Error Flag
* | | |0 = No error.
* | | |1 = Bus error will stop DMA operation and TDES/DES engine.
* @var CRPT_T::TDES0_KEY1H
* Offset: 0x208 TDES/DES Key 1 High Word Register for Channel 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |KEY |TDES/DES Key 1 High Word
* | | |The key registers for TDES/DES algorithm calculation
* | | |The security key for the TDES/DES accelerator is 64 bits
* | | |Thus, it needs two 32-bit registers to store a security key
* | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
* @var CRPT_T::TDES0_KEY1L
* Offset: 0x20C TDES/DES Key 1 Low Word Register for Channel 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |KEY |TDES/DES Key 1 Low Word
* | | |The key registers for TDES/DES algorithm calculation
* | | |The security key for the TDES/DES accelerator is 64 bits
* | | |Thus, it needs two 32-bit registers to store a security key
* | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
* @var CRPT_T::TDES0_KEY2H
* Offset: 0x210 TDES Key 2 High Word Register for Channel 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |KEY |TDES/DES Key 2 High Word
* | | |The key registers for TDES/DES algorithm calculation
* | | |The security key for the TDES/DES accelerator is 64 bits
* | | |Thus, it needs two 32-bit registers to store a security key
* | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
* @var CRPT_T::TDES0_KEY2L
* Offset: 0x214 TDES Key 2 Low Word Register for Channel 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |KEY |TDES/DES Key 2 Low Word
* | | |The key registers for TDES/DES algorithm calculation
* | | |The security key for the TDES/DES accelerator is 64 bits
* | | |Thus, it needs two 32-bit registers to store a security key
* | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
* @var CRPT_T::TDES0_KEY3H
* Offset: 0x218 TDES Key 3 High Word Register for Channel 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |KEY |TDES/DES Key 3 High Word
* | | |The key registers for TDES/DES algorithm calculation
* | | |The security key for the TDES/DES accelerator is 64 bits
* | | |Thus, it needs two 32-bit registers to store a security key
* | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
* @var CRPT_T::TDES0_KEY3L
* Offset: 0x21C TDES Key 3 Low Word Register for Channel 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |KEY |TDES/DES Key 3 Low Word
* | | |The key registers for TDES/DES algorithm calculation
* | | |The security key for the TDES/DES accelerator is 64 bits
* | | |Thus, it needs two 32-bit registers to store a security key
* | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
* @var CRPT_T::TDES0_IVH
* Offset: 0x220 TDES/DES Initial Vector High Word Register for Channel 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |IV |TDES/DES Initial Vector High Word
* | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode
* | | |IV is Nonce counter for TDES/DES engine in CTR mode.
* @var CRPT_T::TDES0_IVL
* Offset: 0x224 TDES/DES Initial Vector Low Word Register for Channel 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |IV |TDES/DES Initial Vector Low Word
* | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode
* | | |IV is Nonce counter for TDES/DES engine in CTR mode.
* @var CRPT_T::TDES0_SA
* Offset: 0x228 TDES/DES DMA Source Address Register for Channel 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |SADDR |TDES/DES DMA Source Address
* | | |The TDES/DES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO
* | | |The CRPT_TDESn_SA keeps the source address of the data buffer where the source text is stored
* | | |Based on the source address, the TDES/DES accelerator can read the plain text from system memory and do TDES/DES operation
* | | |The start of source address should be located at word boundary
* | | |In other words, bit 1 and 0 of CRPT_TDESn_SA are ignored.
* | | |CRPT_TDESn_SA can be read and written
* | | |Writing to CRPT_TDESn_SA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation
* | | |But the value of CRPT_TDESn_SA will be updated later on
* | | |Consequently, software can prepare the DMA source address for the next TDES/DES operation.
* | | |In DMA mode, software can update the next CRPT_TDESn_SA before triggering START.
* | | |CRPT_TDESn_SA and CRPT_TDESn_DA can be the same in the value.
* @var CRPT_T::TDES0_DA
* Offset: 0x22C TDES/DES DMA Destination Address Register for Channel 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |DADDR |TDES/DES DMA Destination Address
* | | |The TDES/DES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO
* | | |The CRPT_TDESn_DA keeps the destination address of the data buffer where the engine output's text will be stored
* | | |Based on the destination address, the TDES/DES accelerator can write the cipher text back to system memory after the TDES/DES operation is finished
* | | |The start of destination address should be located at word boundary
* | | |In other words, bit 1 and 0 of CRPT_TDESn_DA are ignored.
* | | |CRPT_TDESn_DA can be read and written
* | | |Writing to CRPT_TDESn_DA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation
* | | |But the value of CRPT_TDESn_DA will be updated later on
* | | |Consequently, software can prepare the destination address for the next TDES/DES operation.
* | | |In DMA mode, software can update the next CRPT_TDESn_DA before triggering START.
* | | |CRPT_TDESn_SAD and CRPT_TDESn_DA can be the same in the value.
* @var CRPT_T::TDES0_CNT
* Offset: 0x230 TDES/DES Byte Count Register for Channel 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |CNT |TDES/DES Byte Count
* | | |The CRPT_TDESn_CNT keeps the byte count of source text that is for the TDES/DES engine operating in DMA mode
* | | |The CRPT_TDESn_CNT is 32-bit and the maximum of byte count is 4G bytes.
* | | |CRPT_TDESn_CNT can be read and written
* | | |Writing to CRPT_TDESn_CNT while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation
* | | |But the value of CRPT_TDESn_CNT will be updated later on
* | | |Consequently, software can prepare the byte count of data for the next TDES /DES operation.
* | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_TDESn_CNT must be set as byte count for the last block of data before feeding in the last block of data.
* @var CRPT_T::TDES_DATIN
* Offset: 0x234 TDES/DES Engine Input data Word Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |DATIN |TDES/DES Engine Input Port
* | | |CPU feeds data to TDES/DES engine through this port by checking CRPT_TDES_STS
* | | |Feed data as INBUFFULL is 0.
* @var CRPT_T::TDES_DATOUT
* Offset: 0x238 TDES/DES Engine Output data Word Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |DATOUT |TDES/DES Engine Output Port
* | | |CPU gets result from the TDES/DES engine through this port by checking CRPT_TDES_STS
* | | |Get data as OUTBUFEMPTY is 0.
* @var CRPT_T::TDES1_KEY1H
* Offset: 0x248 TDES/DES Key 1 High Word Register for Channel 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |KEY |TDES/DES Key 1 High Word
* | | |The key registers for TDES/DES algorithm calculation
* | | |The security key for the TDES/DES accelerator is 64 bits
* | | |Thus, it needs two 32-bit registers to store a security key
* | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
* @var CRPT_T::TDES1_KEY1L
* Offset: 0x24C TDES/DES Key 1 Low Word Register for Channel 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |KEY |TDES/DES Key 1 Low Word
* | | |The key registers for TDES/DES algorithm calculation
* | | |The security key for the TDES/DES accelerator is 64 bits
* | | |Thus, it needs two 32-bit registers to store a security key
* | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
* @var CRPT_T::TDES1_KEY2H
* Offset: 0x250 TDES Key 2 High Word Register for Channel 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |KEY |TDES/DES Key 2 High Word
* | | |The key registers for TDES/DES algorithm calculation
* | | |The security key for the TDES/DES accelerator is 64 bits
* | | |Thus, it needs two 32-bit registers to store a security key
* | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
* @var CRPT_T::TDES1_KEY2L
* Offset: 0x254 TDES Key 2 Low Word Register for Channel 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |KEY |TDES/DES Key 2 Low Word
* | | |The key registers for TDES/DES algorithm calculation
* | | |The security key for the TDES/DES accelerator is 64 bits
* | | |Thus, it needs two 32-bit registers to store a security key
* | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
* @var CRPT_T::TDES1_KEY3H
* Offset: 0x258 TDES Key 3 High Word Register for Channel 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |KEY |TDES/DES Key 3 High Word
* | | |The key registers for TDES/DES algorithm calculation
* | | |The security key for the TDES/DES accelerator is 64 bits
* | | |Thus, it needs two 32-bit registers to store a security key
* | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
* @var CRPT_T::TDES1_KEY3L
* Offset: 0x25C TDES Key 3 Low Word Register for Channel 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |KEY |TDES/DES Key 3 Low Word
* | | |The key registers for TDES/DES algorithm calculation
* | | |The security key for the TDES/DES accelerator is 64 bits
* | | |Thus, it needs two 32-bit registers to store a security key
* | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
* @var CRPT_T::TDES1_IVH
* Offset: 0x260 TDES/DES Initial Vector High Word Register for Channel 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |IV |TDES/DES Initial Vector High Word
* | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode
* | | |IV is Nonce counter for TDES/DES engine in CTR mode.
* @var CRPT_T::TDES1_IVL
* Offset: 0x264 TDES/DES Initial Vector Low Word Register for Channel 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |IV |TDES/DES Initial Vector Low Word
* | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode
* | | |IV is Nonce counter for TDES/DES engine in CTR mode.
* @var CRPT_T::TDES1_SA
* Offset: 0x268 TDES/DES DMA Source Address Register for Channel 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |SADDR |TDES/DES DMA Source Address
* | | |The TDES/DES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO
* | | |The CRPT_TDESn_SA keeps the source address of the data buffer where the source text is stored
* | | |Based on the source address, the TDES/DES accelerator can read the plain text from system memory and do TDES/DES operation
* | | |The start of source address should be located at word boundary
* | | |In other words, bit 1 and 0 of CRPT_TDESn_SA are ignored.
* | | |CRPT_TDESn_SA can be read and written
* | | |Writing to CRPT_TDESn_SA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation
* | | |But the value of CRPT_TDESn_SA will be updated later on
* | | |Consequently, software can prepare the DMA source address for the next TDES/DES operation.
* | | |In DMA mode, software can update the next CRPT_TDESn_SA before triggering START.
* | | |CRPT_TDESn_SA and CRPT_TDESn_DA can be the same in the value.
* @var CRPT_T::TDES1_DA
* Offset: 0x26C TDES/DES DMA Destination Address Register for Channel 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |DADDR |TDES/DES DMA Destination Address
* | | |The TDES/DES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO
* | | |The CRPT_TDESn_DA keeps the destination address of the data buffer where the engine output's text will be stored
* | | |Based on the destination address, the TDES/DES accelerator can write the cipher text back to system memory after the TDES/DES operation is finished
* | | |The start of destination address should be located at word boundary
* | | |In other words, bit 1 and 0 of CRPT_TDESn_DA are ignored.
* | | |CRPT_TDESn_DA can be read and written
* | | |Writing to CRPT_TDESn_DA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation
* | | |But the value of CRPT_TDESn_DA will be updated later on
* | | |Consequently, software can prepare the destination address for the next TDES/DES operation.
* | | |In DMA mode, software can update the next CRPT_TDESn_DA before triggering START.
* | | |CRPT_TDESn_SAD and CRPT_TDESn_DA can be the same in the value.
* @var CRPT_T::TDES1_CNT
* Offset: 0x270 TDES/DES Byte Count Register for Channel 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |CNT |TDES/DES Byte Count
* | | |The CRPT_TDESn_CNT keeps the byte count of source text that is for the TDES/DES engine operating in DMA mode
* | | |The CRPT_TDESn_CNT is 32-bit and the maximum of byte count is 4G bytes.
* | | |CRPT_TDESn_CNT can be read and written
* | | |Writing to CRPT_TDESn_CNT while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation
* | | |But the value of CRPT_TDESn_CNT will be updated later on
* | | |Consequently, software can prepare the byte count of data for the next TDES /DES operation.
* | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_TDESn_CNT must be set as byte count for the last block of data before feeding in the last block of data.
* @var CRPT_T::TDES2_KEY1H
* Offset: 0x288 TDES/DES Key 1 High Word Register for Channel 2
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |KEY |TDES/DES Key 1 High Word
* | | |The key registers for TDES/DES algorithm calculation
* | | |The security key for the TDES/DES accelerator is 64 bits
* | | |Thus, it needs two 32-bit registers to store a security key
* | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
* @var CRPT_T::TDES2_KEY1L
* Offset: 0x28C TDES/DES Key 1 Low Word Register for Channel 2
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |KEY |TDES/DES Key 1 Low Word
* | | |The key registers for TDES/DES algorithm calculation
* | | |The security key for the TDES/DES accelerator is 64 bits
* | | |Thus, it needs two 32-bit registers to store a security key
* | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
* @var CRPT_T::TDES2_KEY2H
* Offset: 0x290 TDES Key 2 High Word Register for Channel 2
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |KEY |TDES/DES Key 2 High Word
* | | |The key registers for TDES/DES algorithm calculation
* | | |The security key for the TDES/DES accelerator is 64 bits
* | | |Thus, it needs two 32-bit registers to store a security key
* | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
* @var CRPT_T::TDES2_KEY2L
* Offset: 0x294 TDES Key 2 Low Word Register for Channel 2
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |KEY |TDES/DES Key 2 Low Word
* | | |The key registers for TDES/DES algorithm calculation
* | | |The security key for the TDES/DES accelerator is 64 bits
* | | |Thus, it needs two 32-bit registers to store a security key
* | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
* @var CRPT_T::TDES2_KEY3H
* Offset: 0x298 TDES Key 3 High Word Register for Channel 2
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |KEY |TDES/DES Key 3 High Word
* | | |The key registers for TDES/DES algorithm calculation
* | | |The security key for the TDES/DES accelerator is 64 bits
* | | |Thus, it needs two 32-bit registers to store a security key
* | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
* @var CRPT_T::TDES2_KEY3L
* Offset: 0x29C TDES Key 3 Low Word Register for Channel 2
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |KEY |TDES/DES Key 3 Low Word
* | | |The key registers for TDES/DES algorithm calculation
* | | |The security key for the TDES/DES accelerator is 64 bits
* | | |Thus, it needs two 32-bit registers to store a security key
* | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
* @var CRPT_T::TDES2_IVH
* Offset: 0x2A0 TDES/DES Initial Vector High Word Register for Channel 2
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |IV |TDES/DES Initial Vector High Word
* | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode
* | | |IV is Nonce counter for TDES/DES engine in CTR mode.
* @var CRPT_T::TDES2_IVL
* Offset: 0x2A4 TDES/DES Initial Vector Low Word Register for Channel 2
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |IV |TDES/DES Initial Vector Low Word
* | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode
* | | |IV is Nonce counter for TDES/DES engine in CTR mode.
* @var CRPT_T::TDES2_SA
* Offset: 0x2A8 TDES/DES DMA Source Address Register for Channel 2
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |SADDR |TDES/DES DMA Source Address
* | | |The TDES/DES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO
* | | |The CRPT_TDESn_SA keeps the source address of the data buffer where the source text is stored
* | | |Based on the source address, the TDES/DES accelerator can read the plain text from system memory and do TDES/DES operation
* | | |The start of source address should be located at word boundary
* | | |In other words, bit 1 and 0 of CRPT_TDESn_SA are ignored.
* | | |CRPT_TDESn_SA can be read and written
* | | |Writing to CRPT_TDESn_SA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation
* | | |But the value of CRPT_TDESn_SA will be updated later on
* | | |Consequently, software can prepare the DMA source address for the next TDES/DES operation.
* | | |In DMA mode, software can update the next CRPT_TDESn_SA before triggering START.
* | | |CRPT_TDESn_SA and CRPT_TDESn_DA can be the same in the value.
* @var CRPT_T::TDES2_DA
* Offset: 0x2AC TDES/DES DMA Destination Address Register for Channel 2
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |DADDR |TDES/DES DMA Destination Address
* | | |The TDES/DES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO
* | | |The CRPT_TDESn_DA keeps the destination address of the data buffer where the engine output's text will be stored
* | | |Based on the destination address, the TDES/DES accelerator can write the cipher text back to system memory after the TDES/DES operation is finished
* | | |The start of destination address should be located at word boundary
* | | |In other words, bit 1 and 0 of CRPT_TDESn_DA are ignored.
* | | |CRPT_TDESn_DA can be read and written
* | | |Writing to CRPT_TDESn_DA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation
* | | |But the value of CRPT_TDESn_DA will be updated later on
* | | |Consequently, software can prepare the destination address for the next TDES/DES operation.
* | | |In DMA mode, software can update the next CRPT_TDESn_DA before triggering START.
* | | |CRPT_TDESn_SAD and CRPT_TDESn_DA can be the same in the value.
* @var CRPT_T::TDES2_CNT
* Offset: 0x2B0 TDES/DES Byte Count Register for Channel 2
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |CNT |TDES/DES Byte Count
* | | |The CRPT_TDESn_CNT keeps the byte count of source text that is for the TDES/DES engine operating in DMA mode
* | | |The CRPT_TDESn_CNT is 32-bit and the maximum of byte count is 4G bytes.
* | | |CRPT_TDESn_CNT can be read and written
* | | |Writing to CRPT_TDESn_CNT while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation
* | | |But the value of CRPT_TDESn_CNT will be updated later on
* | | |Consequently, software can prepare the byte count of data for the next TDES /DES operation.
* | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_TDESn_CNT must be set as byte count for the last block of data before feeding in the last block of data.
* @var CRPT_T::TDES3_KEY1H
* Offset: 0x2C8 TDES/DES Key 1 High Word Register for Channel 3
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |KEY |TDES/DES Key 1 High Word
* | | |The key registers for TDES/DES algorithm calculation
* | | |The security key for the TDES/DES accelerator is 64 bits
* | | |Thus, it needs two 32-bit registers to store a security key
* | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
* @var CRPT_T::TDES3_KEY1L
* Offset: 0x2CC TDES/DES Key 1 Low Word Register for Channel 3
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |KEY |TDES/DES Key 1 High Word
* | | |The key registers for TDES/DES algorithm calculation
* | | |The security key for the TDES/DES accelerator is 64 bits
* | | |Thus, it needs two 32-bit registers to store a security key
* | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
* @var CRPT_T::TDES3_KEY2H
* Offset: 0x2D0 TDES Key 2 High Word Register for Channel 3
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |KEY |TDES/DES Key 2 High Word
* | | |The key registers for TDES/DES algorithm calculation
* | | |The security key for the TDES/DES accelerator is 64 bits
* | | |Thus, it needs two 32-bit registers to store a security key
* | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
* @var CRPT_T::TDES3_KEY2L
* Offset: 0x2D4 TDES Key 2 Low Word Register for Channel 3
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |KEY |TDES/DES Key 2 Low Word
* | | |The key registers for TDES/DES algorithm calculation
* | | |The security key for the TDES/DES accelerator is 64 bits
* | | |Thus, it needs two 32-bit registers to store a security key
* | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
* @var CRPT_T::TDES3_KEY3H
* Offset: 0x2D8 TDES Key 3 High Word Register for Channel 3
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |KEY |TDES/DES Key 3 High Word
* | | |The key registers for TDES/DES algorithm calculation
* | | |The security key for the TDES/DES accelerator is 64 bits
* | | |Thus, it needs two 32-bit registers to store a security key
* | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
* @var CRPT_T::TDES3_KEY3L
* Offset: 0x2DC TDES Key 3 Low Word Register for Channel 3
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |KEY |TDES/DES Key 3 Low Word
* | | |The key registers for TDES/DES algorithm calculation
* | | |The security key for the TDES/DES accelerator is 64 bits
* | | |Thus, it needs two 32-bit registers to store a security key
* | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
* @var CRPT_T::TDES3_IVH
* Offset: 0x2E0 TDES/DES Initial Vector High Word Register for Channel 3
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |IV |TDES/DES Initial Vector High Word
* | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode
* | | |IV is Nonce counter for TDES/DES engine in CTR mode.
* @var CRPT_T::TDES3_IVL
* Offset: 0x2E4 TDES/DES Initial Vector Low Word Register for Channel 3
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |IV |TDES/DES Initial Vector Low Word
* | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode
* | | |IV is Nonce counter for TDES/DES engine in CTR mode.
* @var CRPT_T::TDES3_SA
* Offset: 0x2E8 TDES/DES DMA Source Address Register for Channel 3
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |SADDR |TDES/DES DMA Source Address
* | | |The TDES/DES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO
* | | |The CRPT_TDESn_SA keeps the source address of the data buffer where the source text is stored
* | | |Based on the source address, the TDES/DES accelerator can read the plain text from system memory and do TDES/DES operation
* | | |The start of source address should be located at word boundary
* | | |In other words, bit 1 and 0 of CRPT_TDESn_SA are ignored.
* | | |CRPT_TDESn_SA can be read and written
* | | |Writing to CRPT_TDESn_SA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation
* | | |But the value of CRPT_TDESn_SA will be updated later on
* | | |Consequently, software can prepare the DMA source address for the next TDES/DES operation.
* | | |In DMA mode, software can update the next CRPT_TDESn_SA before triggering START.
* | | |CRPT_TDESn_SA and CRPT_TDESn_DA can be the same in the value.
* @var CRPT_T::TDES3_DA
* Offset: 0x2EC TDES/DES DMA Destination Address Register for Channel 3
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |DADDR |TDES/DES DMA Destination Address
* | | |The TDES/DES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO
* | | |The CRPT_TDESn_DA keeps the destination address of the data buffer where the engine output's text will be stored
* | | |Based on the destination address, the TDES/DES accelerator can write the cipher text back to system memory after the TDES/DES operation is finished
* | | |The start of destination address should be located at word boundary
* | | |In other words, bit 1 and 0 of CRPT_TDESn_DA are ignored.
* | | |CRPT_TDESn_DA can be read and written
* | | |Writing to CRPT_TDESn_DA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation
* | | |But the value of CRPT_TDESn_DA will be updated later on
* | | |Consequently, software can prepare the destination address for the next TDES/DES operation.
* | | |In DMA mode, software can update the next CRPT_TDESn_DA before triggering START.
* | | |CRPT_TDESn_SAD and CRPT_TDESn_DA can be the same in the value.
* @var CRPT_T::TDES3_CNT
* Offset: 0x2F0 TDES/DES Byte Count Register for Channel 3
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |CNT |TDES/DES Byte Count
* | | |The CRPT_TDESn_CNT keeps the byte count of source text that is for the TDES/DES engine operating in DMA mode
* | | |The CRPT_TDESn_CNT is 32-bit and the maximum of byte count is 4G bytes.
* | | |CRPT_TDESn_CNT can be read and written
* | | |Writing to CRPT_TDESn_CNT while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation
* | | |But the value of CRPT_TDESn_CNT will be updated later on
* | | |Consequently, software can prepare the byte count of data for the next TDES /DES operation.
* | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_TDESn_CNT must be set as byte count for the last block of data before feeding in the last block of data.
* @var CRPT_T::HMAC_CTL
* Offset: 0x300 SHA/HMAC Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |START |SHA/HMAC Engine Start
* | | |0 = No effect.
* | | |1 = Start SHA/HMAC engine. BUSY flag will be set.
* | | |This bit is always 0 when it's read back.
* |[1] |STOP |SHA/HMAC Engine Stop
* | | |0 = No effect.
* | | |1 = Stop SHA/HMAC engine.
* | | |This bit is always 0 when it's read back.
* |[4] |HMACEN |HMAC_SHA Engine Operating Mode
* | | |0 = execute SHA function.
* | | |1 = execute HMAC function.
* |[5] |DMALAST |SHA/HMAC Last Block
* | | |This bit must be set as feeding in last byte of data.
* |[7] |DMAEN |SHA/HMAC Engine DMA Enable Control
* | | |0 = SHA/HMAC DMA engine Disabled.
* | | |SHA/HMAC engine operates in Non-DMA mode, and gets data from the port CRPT_HMAC_DATIN.
* | | |1 = SHA/HMAC DMA engine Enabled.
* | | |SHA/HMAC engine operates in DMA mode, and data movement from/to the engine is done by DMA logic.
* |[10:8] |OPMODE |SHA/HMAC Engine Operation Modes
* | | |0x0xx: SHA160
* | | |0x100: SHA256
* | | |0x101: SHA224
* | | |0x110: SHA512
* | | |0x111: SHA384
* | | |These bits can be read and written. But writing to them wouldn't take effect as BUSY is 1.
* |[22] |OUTSWAP |SHA/HMAC Engine Output Data Swap
* | | |0 = Keep the original order.
* | | |1 = The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}.
* |[23] |INSWAP |SHA/HMAC Engine Input Data Swap
* | | |0 = Keep the original order.
* | | |1 = The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}.
* @var CRPT_T::HMAC_STS
* Offset: 0x304 SHA/HMAC Status Flag
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |BUSY |SHA/HMAC Engine Busy
* | | |0 = SHA/HMAC engine is idle or finished.
* | | |1 = SHA/HMAC engine is busy.
* |[1] |DMABUSY |SHA/HMAC Engine DMA Busy Flag
* | | |0 = SHA/HMAC DMA engine is idle or finished.
* | | |1 = SHA/HMAC DMA engine is busy.
* |[8] |DMAERR |SHA/HMAC Engine DMA Error Flag
* | | |0 = Show the SHA/HMAC engine access normal.
* | | |1 = Show the SHA/HMAC engine access error.
* |[16] |DATINREQ |SHA/HMAC Non-DMA Mode Data Input Request
* | | |0 = No effect.
* | | |1 = Request SHA/HMAC Non-DMA mode data input.
* @var CRPT_T::HMAC_DGST[16]
* Offset: 0x308 ~ 0x344 SHA/HMAC Digest Message 0 ~ 15
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |DGST |SHA/HMAC Digest Message Output Register
* | | |For SHA-160, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST4.
* | | |For SHA-224, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST6.
* | | |For SHA-256, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST7.
* | | |For SHA-384, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST11.
* | | |For SHA-512, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST15.
* @var CRPT_T::HMAC_KEYCNT
* Offset: 0x348 SHA/HMAC Key Byte Count Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |KEYCNT |SHA/HMAC Key Byte Count
* | | |The CRPT_HMAC_KEYCNT keeps the byte count of key that SHA/HMAC engine operates
* | | |The register is 32-bit and the maximum byte count is 4G bytes
* | | |It can be read and written.
* | | |Writing to the register CRPT_HMAC_KEYCNT as the SHA/HMAC accelerator operating doesn't affect the current SHA/HMAC operation
* | | |But the value of CRPT_SHA _KEYCNT will be updated later on
* | | |Consequently, software can prepare the key count for the next SHA/HMAC operation.
* @var CRPT_T::HMAC_SADDR
* Offset: 0x34C SHA/HMAC DMA Source Address Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |SADDR |SHA/HMAC DMA Source Address
* | | |The SHA/HMAC accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO
* | | |The CRPT_HMAC_SADDR keeps the source address of the data buffer where the source text is stored
* | | |Based on the source address, the SHA/HMAC accelerator can read the plain text from system memory and do SHA/HMAC operation
* | | |The start of source address should be located at word boundary
* | | |In other words, bit 1 and 0 of CRPT_HMAC_SADDR are ignored.
* | | |CRPT_HMAC_SADDR can be read and written
* | | |Writing to CRPT_HMAC_SADDR while the SHA/HMAC accelerator is operating doesn't affect the current SHA/HMAC operation
* | | |But the value of CRPT_HMAC_SADDR will be updated later on
* | | |Consequently, software can prepare the DMA source address for the next SHA/HMAC operation.
* | | |In DMA mode, software can update the next CRPT_HMAC_SADDR before triggering START.
* | | |CRPT_HMAC_SADDR and CRPT_HMAC_DADDR can be the same in the value.
* @var CRPT_T::HMAC_DMACNT
* Offset: 0x350 SHA/HMAC Byte Count Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |DMACNT |SHA/HMAC Operation Byte Count
* | | |The CRPT_HMAC_DMACNT keeps the byte count of source text that is for the SHA/HMAC engine operating in DMA mode
* | | |The CRPT_HMAC_DMACNT is 32-bit and the maximum of byte count is 4G bytes.
* | | |CRPT_HMAC_DMACNT can be read and written
* | | |Writing to CRPT_HMAC_DMACNT while the SHA/HMAC accelerator is operating doesn't affect the current SHA/HMAC operation
* | | |But the value of CRPT_HMAC_DMACNT will be updated later on
* | | |Consequently, software can prepare the byte count of data for the next SHA/HMAC operation.
* | | |In Non-DMA mode, CRPT_HMAC_DMACNT must be set as the byte count of the last block before feeding in the last block of data.
* @var CRPT_T::HMAC_DATIN
* Offset: 0x354 SHA/HMAC Engine Non-DMA Mode Data Input Port Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |DATIN |SHA/HMAC Engine Input Port
* | | |CPU feeds data to SHA/HMAC engine through this port by checking CRPT_HMAC_STS
* | | |Feed data as DATINREQ is 1.
* @var CRPT_T::ECC_CTL
* Offset: 0x800 ECC Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |START |ECC Accelerator Start
* | | |0 = No effect.
* | | |1 = Start ECC accelerator. BUSY flag will be set.
* | | |This bit is always 0 when it's read back.
* | | |ECC accelerator will ignore this START signal when BUSY flag is 1.
* |[1] |STOP |ECC Accelerator Stop
* | | |0 = No effect.
* | | |1 = Abort ECC accelerator and make it into idle state.
* | | |This bit is always 0 when it's read back.
* | | |Remember to clear ECC interrupt flag after stopping ECC accelerator.
* |[7] |DMAEN |ECC Accelerator DMA Enable Control
* | | |0 = ECC DMA engine Disabled.
* | | |1 = ECC DMA engine Enabled.
* | | |Only when START and DMAEN are 1, ECC DMA engine will be active
* |[8] |FSEL |Field Selection
* | | |0 = Binary Field (GF(2^m)).
* | | |1 = Prime Field (GF(p)).
* |[10:9] |ECCOP |Point Operation for BF and PF
* | | |00 = Point multiplication :.
* | | |(POINTX1, POINTY1) = SCALARK * (POINTX1, POINTY1).
* | | |01 = Modulus operation : choose by MODOP (CRPT_ECC_CTL[12:11]).
* | | |10 = Point addition :.
* | | |(POINTX1, POINTY1) = (POINTX1, POINTY1) +.
* | | |(POINTX2, POINTY2)
* | | |11 = Point doubling :.
* | | |(POINTX1, POINTY1) = 2 * (POINTX1, POINTY1).
* | | |Besides above three input data, point operations still need the parameters of elliptic curve (CURVEA, CURVEB, CURVEN and CURVEM) as shown in Figure 6.27-11
* |[12:11] |MODOP |Modulus Operation for PF
* | | |00 = Division :.
* | | |POINTX1 = (POINTY1 / POINTX1) % CURVEN.
* | | |01 = Multiplication :.
* | | |POINTX1 = (POINTX1 * POINTY1) % CURVEN.
* | | |10 = Addition :.
* | | |POINTX1 = (POINTX1 + POINTY1) % CURVEN.
* | | |11 = Subtraction :.
* | | |POINTX1 = (POINTX1 - POINTY1) % CURVEN.
* | | |MODOP is active only when ECCOP = 01.
* |[16] |LDP1 |The Control Signal of Register for the X and Y Coordinate of the First Point (POINTX1, POINTY1)
* | | |0 = The register for POINTX1 and POINTY1 is not modified by DMA or user.
* | | |1 = The register for POINTX1 and POINTY1 is modified by DMA or user.
* |[17] |LDP2 |The Control Signal of Register for the X and Y Coordinate of the Second Point (POINTX2, POINTY2)
* | | |0 = The register for POINTX2 and POINTY2 is not modified by DMA or user.
* | | |1 = The register for POINTX2 and POINTY2 is modified by DMA or user.
* |[18] |LDA |The Control Signal of Register for the Parameter CURVEA of Elliptic Curve
* | | |0 = The register for CURVEA is not modified by DMA or user.
* | | |1 = The register for CURVEA is modified by DMA or user.
* |[19] |LDB |The Control Signal of Register for the Parameter CURVEB of Elliptic Curve
* | | |0 = The register for CURVEB is not modified by DMA or user.
* | | |1 = The register for CURVEB is modified by DMA or user.
* |[20] |LDN |The Control Signal of Register for the Parameter CURVEN of Elliptic Curve
* | | |0 = The register for CURVEN is not modified by DMA or user.
* | | |1 = The register for CURVEN is modified by DMA or user.
* |[21] |LDK |The Control Signal of Register for SCALARK
* | | |0 = The register for SCALARK is not modified by DMA or user.
* | | |1 = The register for SCALARK is modified by DMA or user.
* |[31:22] |CURVEM |The key length of elliptic curve.
* @var CRPT_T::ECC_STS
* Offset: 0x804 ECC Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |BUSY |ECC Accelerator Busy Flag
* | | |0 = The ECC accelerator is idle or finished.
* | | |1 = The ECC accelerator is under processing and protects all registers.
* | | |Remember to clear ECC interrupt flag after ECC accelerator finished
* |[1] |DMABUSY |ECC DMA Busy Flag
* | | |0 = ECC DMA is idle or finished.
* | | |1 = ECC DMA is busy.
* |[16] |BUSERR |ECC DMA Access Bus Error Flag
* | | |0 = No error.
* | | |1 = Bus error will stop DMA operation and ECC accelerator.
* @var CRPT_T::ECC_X1[18]
* Offset: 0x808 ~ 0x84C ECC The X-coordinate word 0 ~ 17 of the first point
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |POINTX1 |ECC the x-coordinate Value of the First Point (POINTX1)
* | | |For B-163 or K-163, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_05
* | | |For B-233 or K-233, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_07
* | | |For B-283 or K-283, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_08
* | | |For B-409 or K-409, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_12
* | | |For B-571 or K-571, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_17
* | | |For P-192, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_05
* | | |For P-224, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_06
* | | |For P-256, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_07
* | | |For P-384, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_11
* | | |For P-521, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_16
* @var CRPT_T::ECC_Y1[18]
* Offset: 0x850 ~ 0x894 ECC The Y-coordinate word 0 ~ 17 of the first point
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |POINTY1 |ECC the Y-coordinate Value of the First Point (POINTY1)
* | | |For B-163 or K-163, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_05
* | | |For B-233 or K-233, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_07
* | | |For B-283 or K-283, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_08
* | | |For B-409 or K-409, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_12
* | | |For B-571 or K-571, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_17
* | | |For P-192, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_05
* | | |For P-224, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_06
* | | |For P-256, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_07
* | | |For P-384, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_11
* | | |For P-521, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_16
* @var CRPT_T::ECC_X2[18]
* Offset: 0x898 ~ 0x8DC ECC The X-coordinate word 0 ~ 17 of the second point
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |POINTX2 |ECC the x-coordinate Value of the Second Point (POINTX2)
* | | |For B-163 or K-163, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_05
* | | |For B-233 or K-233, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_07
* | | |For B-283 or K-283, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_08
* | | |For B-409 or K-409, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_12
* | | |For B-571 or K-571, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_17
* | | |For P-192, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_05
* | | |For P-224, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_06
* | | |For P-256, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_07
* | | |For P-384, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_11
* | | |For P-521, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_16
* @var CRPT_T::ECC_Y2[18]
* Offset: 0x8E0 ~ 0x924 ECC The Y-coordinate word 0 ~ 17 of the second point
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |POINTY2 |ECC the Y-coordinate Value of the Second Point (POINTY2)
* | | |For B-163 or K-163, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_05
* | | |For B-233 or K-233, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_07
* | | |For B-283 or K-283, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_08
* | | |For B-409 or K-409, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_12
* | | |For B-571 or K-571, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_17
* | | |For P-192, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_05
* | | |For P-224, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_06
* | | |For P-256, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_07
* | | |For P-384, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_11
* | | |For P-521, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_16
* @var CRPT_T::ECC_A[18]
* Offset: 0x928 ~ 0x96C ECC The parameter CURVEA word 0 ~ 17 of elliptic curve
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |CURVEA |ECC the Parameter CURVEA Value of Elliptic Curve (CURVEA)
* | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2^m).
* | | |For B-163 or K-163, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_05
* | | |For B-233 or K-233, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_07
* | | |For B-283 or K-283, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_08
* | | |For B-409 or K-409, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_12
* | | |For B-571 or K-571, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_17
* | | |For P-192, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_05
* | | |For P-224, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_06
* | | |For P-256, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_07
* | | |For P-384, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_11
* | | |For P-521, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_16
* @var CRPT_T::ECC_B[18]
* Offset: 0x970 ~ 0x9B4 ECC The parameter CURVEB word 0 ~ 17 of elliptic curve
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |CURVEB |ECC the Parameter CURVEB Value of Elliptic Curve (CURVEA)
* | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2^m).
* | | |For B-163 or K-163, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_05
* | | |For B-233 or K-233, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_07
* | | |For B-283 or K-283, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_08
* | | |For B-409 or K-409, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_12
* | | |For B-521 or K-521, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_17
* | | |For P-192, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_05
* | | |For P-224, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_06
* | | |For P-256, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_07
* | | |For P-384, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_11
* | | |For P-521, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_16
* @var CRPT_T::ECC_N[18]
* Offset: 0x9B8 ~ 0x9FC ECC The parameter CURVEN word 0 ~ 17 of elliptic curve
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |CURVEN |ECC the Parameter CURVEN Value of Elliptic Curve (CURVEN)
* | | |In GF(p), CURVEN is the prime p.
* | | |In GF(2^m), CURVEN is the irreducible polynomial.
* | | |For B-163 or K-163, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_05
* | | |For B-233 or K-233, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_07
* | | |For B-283 or K-283, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_08
* | | |For B-409 or K-409, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_12
* | | |For B-571 or K-571, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_17
* | | |For P-192, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_05
* | | |For P-224, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_06
* | | |For P-256, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_07
* | | |For P-384, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_11
* | | |For P-521, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_16
* @var CRPT_T::ECC_K[18]
* Offset: 0xA00 ~ 0xA44 ECC The scalar SCALARK word0 of point multiplication
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |SCALARK |ECC the Scalar SCALARK Value of Point Multiplication(SCALARK)
* | | |Because the SCALARK usually stores the private key, ECC accelerator do not allow to read the register SCALARK.
* | | |For B-163 or K-163, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_05
* | | |For B-233 or K-233, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_07
* | | |For B-283 or K-283, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_08
* | | |For B-409 or K-409, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_12
* | | |For B-571 or K-571, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_17
* | | |For P-192, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_05
* | | |For P-224, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_06
* | | |For P-256, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_07
* | | |For P-384, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_11
* | | |For P-521, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_16
* @var CRPT_T::ECC_SADDR
* Offset: 0xA48 ECC DMA Source Address Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |SADDR |ECC DMA Source Address
* | | |The ECC accelerator supports DMA function to transfer the DATA and PARAMETER between
* | | |SRAM memory space and ECC accelerator. The SADDR keeps the source address of the data
* | | |buffer where the source text is stored. Based on the source address, the ECC accelerator
* | | |can read the DATA and PARAMETER from SRAM memory space and do ECC operation. The start
* | | |of source address should be located at word boundary. That is, bit 1 and 0 of SADDR are
* | | |ignored. SADDR can be read and written. In DMA mode, software must update the CRPT_ECC_SADDR
* | | |before triggering START.
* @var CRPT_T::ECC_DADDR
* Offset: 0xA4C ECC DMA Destination Address Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |DADDR |ECC DMA Destination Address
* | | |The ECC accelerator supports DMA function to transfer the DATA and PARAMETER between system memory and ECC accelerator
* | | |The DADDR keeps the destination address of the data buffer where output data of ECC engine will be stored
* | | |Based on the destination address, the ECC accelerator can write the result data back to system memory after the ECC operation is finished
* | | |The start of destination address should be located at word boundary
* | | |That is, bit 1 and 0 of DADDR are ignored
* | | |DADDR can be read and written
* | | |In DMA mode, software must update the CRPT_ECC_DADDR before triggering START
* @var CRPT_T::ECC_STARTREG
* Offset: 0xA50 ECC Starting Address of Updated Registers
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |STARTREG |ECC Starting Address of Updated Registers
* | | |The address of the updated registers that DMA feeds the first data or parameter to ECC engine
* | | |When ECC engine is active, ECC accelerator does not allow users to modify STARTREG
* | | |For example, we want to updated input data from register CRPT_ECC POINTX1
* | | |Thus, the value of STARTREG is 0x808.
* @var CRPT_T::ECC_WORDCNT
* Offset: 0xA54 ECC DMA Word Count
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |WORDCNT |ECC DMA Word Count
* | | |The CRPT_ECC_WORDCNT keeps the word count of source data that is for the required input data of ECC accelerator with various operations in DMA mode
* | | |Although CRPT_ECC_WORDCNT is 32-bit, the maximum of word count in ECC accelerator is 144 words
* | | |CRPT_ECC_WORDCNT can be read and written
*/
__IO uint32_t INTEN; /*!< [0x0000] Crypto Interrupt Enable Control Register */
__IO uint32_t INTSTS; /*!< [0x0004] Crypto Interrupt Flag */
__IO uint32_t PRNG_CTL; /*!< [0x0008] PRNG Control Register */
__O uint32_t PRNG_SEED; /*!< [0x000c] Seed for PRNG */
__I uint32_t PRNG_KEY[8]; /*!< [0x0010] ~ [0x002c] PRNG Generated Key0 ~ Key7 */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE0[8];
/// @endcond //HIDDEN_SYMBOLS
__I uint32_t AES_FDBCK[4]; /*!< [0x0050] ~ [0x005c] AES Engine Output Feedback Data after Cryptographic Operation */
__I uint32_t TDES_FDBCKH; /*!< [0x0060] TDES/DES Engine Output Feedback High Word Data after Cryptographic Operation */
__I uint32_t TDES_FDBCKL; /*!< [0x0064] TDES/DES Engine Output Feedback Low Word Data after Cryptographic Operation */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE1[38];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t AES_CTL; /*!< [0x0100] AES Control Register */
__I uint32_t AES_STS; /*!< [0x0104] AES Engine Flag */
__IO uint32_t AES_DATIN; /*!< [0x0108] AES Engine Data Input Port Register */
__I uint32_t AES_DATOUT; /*!< [0x010c] AES Engine Data Output Port Register */
__IO uint32_t AES0_KEY[8]; /*!< [0x0110] ~ [0x012c] AES Key Word 0~7 Register for Channel 0 */
__IO uint32_t AES0_IV[4]; /*!< [0x0130] ~ [0x013c] AES Initial Vector Word 0 ~ 3 Register for Channel 0 */
__IO uint32_t AES0_SADDR; /*!< [0x0140] AES DMA Source Address Register for Channel 0 */
__IO uint32_t AES0_DADDR; /*!< [0x0144] AES DMA Destination Address Register for Channel 0 */
__IO uint32_t AES0_CNT; /*!< [0x0148] AES Byte Count Register for Channel 0 */
__IO uint32_t AES1_KEY[8]; /*!< [0x014c] ~ [0x0168] AES Key Word 0~7 Register for Channel 1 */
__IO uint32_t AES1_IV[4]; /*!< [0x016c] ~ [0x0178] AES Initial Vector Word 0~3 Register for Channel 1 */
__IO uint32_t AES1_SADDR; /*!< [0x017c] AES DMA Source Address Register for Channel 1 */
__IO uint32_t AES1_DADDR; /*!< [0x0180] AES DMA Destination Address Register for Channel 1 */
__IO uint32_t AES1_CNT; /*!< [0x0184] AES Byte Count Register for Channel 1 */
__IO uint32_t AES2_KEY[8]; /*!< [0x0188] ~ [0x01a4] AES Key Word 0~7 Register for Channel 2 */
__IO uint32_t AES2_IV[4]; /*!< [0x01a8] ~ [0x01b4] AES Initial Vector Word 0~3 Register for Channel 2 */
__IO uint32_t AES2_SADDR; /*!< [0x01b8] AES DMA Source Address Register for Channel 2 */
__IO uint32_t AES2_DADDR; /*!< [0x01bc] AES DMA Destination Address Register for Channel 2 */
__IO uint32_t AES2_CNT; /*!< [0x01c0] AES Byte Count Register for Channel 2 */
__IO uint32_t AES3_KEY[8]; /*!< [0x01c4] ~ [0x01e0] AES Key Word 0~7 Register for Channel 3 */
__IO uint32_t AES3_IV[4]; /*!< [0x01e4] ~ [0x01f0] AES Initial Vector Word 0~3 Register for Channel 3 */
__IO uint32_t AES3_SADDR; /*!< [0x01f4] AES DMA Source Address Register for Channel 3 */
__IO uint32_t AES3_DADDR; /*!< [0x01f8] AES DMA Destination Address Register for Channel 3 */
__IO uint32_t AES3_CNT; /*!< [0x01fc] AES Byte Count Register for Channel 3 */
__IO uint32_t TDES_CTL; /*!< [0x0200] TDES/DES Control Register */
__I uint32_t TDES_STS; /*!< [0x0204] TDES/DES Engine Flag */
__IO uint32_t TDES0_KEY1H; /*!< [0x0208] TDES/DES Key 1 High Word Register for Channel 0 */
__IO uint32_t TDES0_KEY1L; /*!< [0x020c] TDES/DES Key 1 Low Word Register for Channel 0 */
__IO uint32_t TDES0_KEY2H; /*!< [0x0210] TDES Key 2 High Word Register for Channel 0 */
__IO uint32_t TDES0_KEY2L; /*!< [0x0214] TDES Key 2 Low Word Register for Channel 0 */
__IO uint32_t TDES0_KEY3H; /*!< [0x0218] TDES Key 3 High Word Register for Channel 0 */
__IO uint32_t TDES0_KEY3L; /*!< [0x021c] TDES Key 3 Low Word Register for Channel 0 */
__IO uint32_t TDES0_IVH; /*!< [0x0220] TDES/DES Initial Vector High Word Register for Channel 0 */
__IO uint32_t TDES0_IVL; /*!< [0x0224] TDES/DES Initial Vector Low Word Register for Channel 0 */
__IO uint32_t TDES0_SA; /*!< [0x0228] TDES/DES DMA Source Address Register for Channel 0 */
__IO uint32_t TDES0_DA; /*!< [0x022c] TDES/DES DMA Destination Address Register for Channel 0 */
__IO uint32_t TDES0_CNT; /*!< [0x0230] TDES/DES Byte Count Register for Channel 0 */
__IO uint32_t TDES_DATIN; /*!< [0x0234] TDES/DES Engine Input data Word Register */
__I uint32_t TDES_DATOUT; /*!< [0x0238] TDES/DES Engine Output data Word Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE2[3];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t TDES1_KEY1H; /*!< [0x0248] TDES/DES Key 1 High Word Register for Channel 1 */
__IO uint32_t TDES1_KEY1L; /*!< [0x024c] TDES/DES Key 1 Low Word Register for Channel 1 */
__IO uint32_t TDES1_KEY2H; /*!< [0x0250] TDES Key 2 High Word Register for Channel 1 */
__IO uint32_t TDES1_KEY2L; /*!< [0x0254] TDES Key 2 Low Word Register for Channel 1 */
__IO uint32_t TDES1_KEY3H; /*!< [0x0258] TDES Key 3 High Word Register for Channel 1 */
__IO uint32_t TDES1_KEY3L; /*!< [0x025c] TDES Key 3 Low Word Register for Channel 1 */
__IO uint32_t TDES1_IVH; /*!< [0x0260] TDES/DES Initial Vector High Word Register for Channel 1 */
__IO uint32_t TDES1_IVL; /*!< [0x0264] TDES/DES Initial Vector Low Word Register for Channel 1 */
__IO uint32_t TDES1_SA; /*!< [0x0268] TDES/DES DMA Source Address Register for Channel 1 */
__IO uint32_t TDES1_DA; /*!< [0x026c] TDES/DES DMA Destination Address Register for Channel 1 */
__IO uint32_t TDES1_CNT; /*!< [0x0270] TDES/DES Byte Count Register for Channel 1 */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE3[5];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t TDES2_KEY1H; /*!< [0x0288] TDES/DES Key 1 High Word Register for Channel 2 */
__IO uint32_t TDES2_KEY1L; /*!< [0x028c] TDES/DES Key 1 Low Word Register for Channel 2 */
__IO uint32_t TDES2_KEY2H; /*!< [0x0290] TDES Key 2 High Word Register for Channel 2 */
__IO uint32_t TDES2_KEY2L; /*!< [0x0294] TDES Key 2 Low Word Register for Channel 2 */
__IO uint32_t TDES2_KEY3H; /*!< [0x0298] TDES Key 3 High Word Register for Channel 2 */
__IO uint32_t TDES2_KEY3L; /*!< [0x029c] TDES Key 3 Low Word Register for Channel 2 */
__IO uint32_t TDES2_IVH; /*!< [0x02a0] TDES/DES Initial Vector High Word Register for Channel 2 */
__IO uint32_t TDES2_IVL; /*!< [0x02a4] TDES/DES Initial Vector Low Word Register for Channel 2 */
__IO uint32_t TDES2_SA; /*!< [0x02a8] TDES/DES DMA Source Address Register for Channel 2 */
__IO uint32_t TDES2_DA; /*!< [0x02ac] TDES/DES DMA Destination Address Register for Channel 2 */
__IO uint32_t TDES2_CNT; /*!< [0x02b0] TDES/DES Byte Count Register for Channel 2 */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE4[5];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t TDES3_KEY1H; /*!< [0x02c8] TDES/DES Key 1 High Word Register for Channel 3 */
__IO uint32_t TDES3_KEY1L; /*!< [0x02cc] TDES/DES Key 1 Low Word Register for Channel 3 */
__IO uint32_t TDES3_KEY2H; /*!< [0x02d0] TDES Key 2 High Word Register for Channel 3 */
__IO uint32_t TDES3_KEY2L; /*!< [0x02d4] TDES Key 2 Low Word Register for Channel 3 */
__IO uint32_t TDES3_KEY3H; /*!< [0x02d8] TDES Key 3 High Word Register for Channel 3 */
__IO uint32_t TDES3_KEY3L; /*!< [0x02dc] TDES Key 3 Low Word Register for Channel 3 */
__IO uint32_t TDES3_IVH; /*!< [0x02e0] TDES/DES Initial Vector High Word Register for Channel 3 */
__IO uint32_t TDES3_IVL; /*!< [0x02e4] TDES/DES Initial Vector Low Word Register for Channel 3 */
__IO uint32_t TDES3_SA; /*!< [0x02e8] TDES/DES DMA Source Address Register for Channel 3 */
__IO uint32_t TDES3_DA; /*!< [0x02ec] TDES/DES DMA Destination Address Register for Channel 3 */
__IO uint32_t TDES3_CNT; /*!< [0x02f0] TDES/DES Byte Count Register for Channel 3 */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE5[3];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t HMAC_CTL; /*!< [0x0300] SHA/HMAC Control Register */
__I uint32_t HMAC_STS; /*!< [0x0304] SHA/HMAC Status Flag */
__I uint32_t HMAC_DGST[16]; /*!< [0x0308] ~ [0x0344] SHA/HMAC Digest Message 0~15 */
__IO uint32_t HMAC_KEYCNT; /*!< [0x0348] SHA/HMAC Key Byte Count Register */
__IO uint32_t HMAC_SADDR; /*!< [0x034c] SHA/HMAC DMA Source Address Register */
__IO uint32_t HMAC_DMACNT; /*!< [0x0350] SHA/HMAC Byte Count Register */
__IO uint32_t HMAC_DATIN; /*!< [0x0354] SHA/HMAC Engine Non-DMA Mode Data Input Port Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE6[298];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t ECC_CTL; /*!< [0x0800] ECC Control Register */
__I uint32_t ECC_STS; /*!< [0x0804] ECC Status Register */
__IO uint32_t ECC_X1[18]; /*!< [0x0808] ~ [0x084c] ECC The X-coordinate word 0~17 of the first point */
__IO uint32_t ECC_Y1[18]; /*!< [0x0850] ~ [0x0894] ECC The Y-coordinate word 0~17 of the first point */
__IO uint32_t ECC_X2[18]; /*!< [0x0898] ~ [0x08dc] ECC The X-coordinate word 0~17 of the second point */
__IO uint32_t ECC_Y2[18]; /*!< [0x08e0] ~ [0x0924] ECC The Y-coordinate word 0~17 of the second point */
__IO uint32_t ECC_A[18]; /*!< [0x0928] ~ [0x096c] ECC The parameter CURVEA word 0~17 of elliptic curve */
__IO uint32_t ECC_B[18]; /*!< [0x0970] ~ [0x09b4] ECC The parameter CURVEB word 0~17 of elliptic curve */
__IO uint32_t ECC_N[18]; /*!< [0x09b8] ~ [0x09fc] ECC The parameter CURVEN word 0~17 of elliptic curve */
__O uint32_t ECC_K[18]; /*!< [0x0a00] ~ [0x0a44] ECC The scalar SCALARK word 0~17 of point multiplication */
__IO uint32_t ECC_SADDR; /*!< [0x0a48] ECC DMA Source Address Register */
__IO uint32_t ECC_DADDR; /*!< [0x0a4c] ECC DMA Destination Address Register */
__IO uint32_t ECC_STARTREG; /*!< [0x0a50] ECC Starting Address of Updated Registers */
__IO uint32_t ECC_WORDCNT; /*!< [0x0a54] ECC DMA Word Count */
} CRPT_T;
/**
@addtogroup CRPT_CONST CRPT Bit Field Definition
Constant Definitions for CRPT Controller
@{ */
#define CRPT_INTEN_AESIEN_Pos (0) /*!< CRPT_T::INTEN: AESIEN Position */
#define CRPT_INTEN_AESIEN_Msk (0x1ul << CRPT_INTEN_AESIEN_Pos) /*!< CRPT_T::INTEN: AESIEN Mask */
#define CRPT_INTEN_AESEIEN_Pos (1) /*!< CRPT_T::INTEN: AESEIEN Position */
#define CRPT_INTEN_AESEIEN_Msk (0x1ul << CRPT_INTEN_AESEIEN_Pos) /*!< CRPT_T::INTEN: AESEIEN Mask */
#define CRPT_INTEN_TDESIEN_Pos (8) /*!< CRPT_T::INTEN: TDESIEN Position */
#define CRPT_INTEN_TDESIEN_Msk (0x1ul << CRPT_INTEN_TDESIEN_Pos) /*!< CRPT_T::INTEN: TDESIEN Mask */
#define CRPT_INTEN_TDESEIEN_Pos (9) /*!< CRPT_T::INTEN: TDESEIEN Position */
#define CRPT_INTEN_TDESEIEN_Msk (0x1ul << CRPT_INTEN_TDESEIEN_Pos) /*!< CRPT_T::INTEN: TDESEIEN Mask */
#define CRPT_INTEN_PRNGIEN_Pos (16) /*!< CRPT_T::INTEN: PRNGIEN Position */
#define CRPT_INTEN_PRNGIEN_Msk (0x1ul << CRPT_INTEN_PRNGIEN_Pos) /*!< CRPT_T::INTEN: PRNGIEN Mask */
#define CRPT_INTEN_ECCIEN_Pos (22) /*!< CRPT_T::INTEN: ECCIEN Position */
#define CRPT_INTEN_ECCIEN_Msk (0x1ul << CRPT_INTEN_ECCIEN_Pos) /*!< CRPT_T::INTEN: ECCIEN Mask */
#define CRPT_INTEN_ECCEIEN_Pos (23) /*!< CRPT_T::INTEN: ECCEIEN Position */
#define CRPT_INTEN_ECCEIEN_Msk (0x1ul << CRPT_INTEN_ECCEIEN_Pos) /*!< CRPT_T::INTEN: ECCEIEN Mask */
#define CRPT_INTEN_HMACIEN_Pos (24) /*!< CRPT_T::INTEN: HMACIEN Position */
#define CRPT_INTEN_HMACIEN_Msk (0x1ul << CRPT_INTEN_HMACIEN_Pos) /*!< CRPT_T::INTEN: HMACIEN Mask */
#define CRPT_INTEN_HMACEIEN_Pos (25) /*!< CRPT_T::INTEN: HMACEIEN Position */
#define CRPT_INTEN_HMACEIEN_Msk (0x1ul << CRPT_INTEN_HMACEIEN_Pos) /*!< CRPT_T::INTEN: HMACEIEN Mask */
#define CRPT_INTSTS_AESIF_Pos (0) /*!< CRPT_T::INTSTS: AESIF Position */
#define CRPT_INTSTS_AESIF_Msk (0x1ul << CRPT_INTSTS_AESIF_Pos) /*!< CRPT_T::INTSTS: AESIF Mask */
#define CRPT_INTSTS_AESEIF_Pos (1) /*!< CRPT_T::INTSTS: AESEIF Position */
#define CRPT_INTSTS_AESEIF_Msk (0x1ul << CRPT_INTSTS_AESEIF_Pos) /*!< CRPT_T::INTSTS: AESEIF Mask */
#define CRPT_INTSTS_TDESIF_Pos (8) /*!< CRPT_T::INTSTS: TDESIF Position */
#define CRPT_INTSTS_TDESIF_Msk (0x1ul << CRPT_INTSTS_TDESIF_Pos) /*!< CRPT_T::INTSTS: TDESIF Mask */
#define CRPT_INTSTS_TDESEIF_Pos (9) /*!< CRPT_T::INTSTS: TDESEIF Position */
#define CRPT_INTSTS_TDESEIF_Msk (0x1ul << CRPT_INTSTS_TDESEIF_Pos) /*!< CRPT_T::INTSTS: TDESEIF Mask */
#define CRPT_INTSTS_PRNGIF_Pos (16) /*!< CRPT_T::INTSTS: PRNGIF Position */
#define CRPT_INTSTS_PRNGIF_Msk (0x1ul << CRPT_INTSTS_PRNGIF_Pos) /*!< CRPT_T::INTSTS: PRNGIF Mask */
#define CRPT_INTSTS_ECCIF_Pos (22) /*!< CRPT_T::INTSTS: ECCIF Position */
#define CRPT_INTSTS_ECCIF_Msk (0x1ul << CRPT_INTSTS_ECCIF_Pos) /*!< CRPT_T::INTSTS: ECCIF Mask */
#define CRPT_INTSTS_ECCEIF_Pos (23) /*!< CRPT_T::INTSTS: ECCEIF Position */
#define CRPT_INTSTS_ECCEIF_Msk (0x1ul << CRPT_INTSTS_ECCEIF_Pos) /*!< CRPT_T::INTSTS: ECCEIF Mask */
#define CRPT_INTSTS_HMACIF_Pos (24) /*!< CRPT_T::INTSTS: HMACIF Position */
#define CRPT_INTSTS_HMACIF_Msk (0x1ul << CRPT_INTSTS_HMACIF_Pos) /*!< CRPT_T::INTSTS: HMACIF Mask */
#define CRPT_INTSTS_HMACEIF_Pos (25) /*!< CRPT_T::INTSTS: HMACEIF Position */
#define CRPT_INTSTS_HMACEIF_Msk (0x1ul << CRPT_INTSTS_HMACEIF_Pos) /*!< CRPT_T::INTSTS: HMACEIF Mask */
#define CRPT_PRNG_CTL_START_Pos (0) /*!< CRPT_T::PRNG_CTL: START Position */
#define CRPT_PRNG_CTL_START_Msk (0x1ul << CRPT_PRNG_CTL_START_Pos) /*!< CRPT_T::PRNG_CTL: START Mask */
#define CRPT_PRNG_CTL_SEEDRLD_Pos (1) /*!< CRPT_T::PRNG_CTL: SEEDRLD Position */
#define CRPT_PRNG_CTL_SEEDRLD_Msk (0x1ul << CRPT_PRNG_CTL_SEEDRLD_Pos) /*!< CRPT_T::PRNG_CTL: SEEDRLD Mask */
#define CRPT_PRNG_CTL_KEYSZ_Pos (2) /*!< CRPT_T::PRNG_CTL: KEYSZ Position */
#define CRPT_PRNG_CTL_KEYSZ_Msk (0x3ul << CRPT_PRNG_CTL_KEYSZ_Pos) /*!< CRPT_T::PRNG_CTL: KEYSZ Mask */
#define CRPT_PRNG_CTL_BUSY_Pos (8) /*!< CRPT_T::PRNG_CTL: BUSY Position */
#define CRPT_PRNG_CTL_BUSY_Msk (0x1ul << CRPT_PRNG_CTL_BUSY_Pos) /*!< CRPT_T::PRNG_CTL: BUSY Mask */
#define CRPT_PRNG_SEED_SEED_Pos (0) /*!< CRPT_T::PRNG_SEED: SEED Position */
#define CRPT_PRNG_SEED_SEED_Msk (0xfffffffful << CRPT_PRNG_SEED_SEED_Pos) /*!< CRPT_T::PRNG_SEED: SEED Mask */
#define CRPT_PRNG_KEYx_KEY_Pos (0) /*!< CRPT_T::PRNG_KEY[8]: KEY Position */
#define CRPT_PRNG_KEYx_KEY_Msk (0xfffffffful << CRPT_PRNG_KEYx_KEY_Pos) /*!< CRPT_T::PRNG_KEY[8]: KEY Mask */
#define CRPT_AES_FDBCKx_FDBCK_Pos (0) /*!< CRPT_T::AES_FDBCK[4]: FDBCK Position */
#define CRPT_AES_FDBCKx_FDBCK_Msk (0xfffffffful << CRPT_AES_FDBCKx_FDBCK_Pos) /*!< CRPT_T::AES_FDBCK[4]: FDBCK Mask */
#define CRPT_TDES_FDBCKH_FDBCK_Pos (0) /*!< CRPT_T::TDES_FDBCKH: FDBCK Position */
#define CRPT_TDES_FDBCKH_FDBCK_Msk (0xfffffffful << CRPT_TDES_FDBCKH_FDBCK_Pos) /*!< CRPT_T::TDES_FDBCKH: FDBCK Mask */
#define CRPT_TDES_FDBCKL_FDBCK_Pos (0) /*!< CRPT_T::TDES_FDBCKL: FDBCK Position */
#define CRPT_TDES_FDBCKL_FDBCK_Msk (0xfffffffful << CRPT_TDES_FDBCKL_FDBCK_Pos) /*!< CRPT_T::TDES_FDBCKL: FDBCK Mask */
#define CRPT_AES_CTL_START_Pos (0) /*!< CRPT_T::AES_CTL: START Position */
#define CRPT_AES_CTL_START_Msk (0x1ul << CRPT_AES_CTL_START_Pos) /*!< CRPT_T::AES_CTL: START Mask */
#define CRPT_AES_CTL_STOP_Pos (1) /*!< CRPT_T::AES_CTL: STOP Position */
#define CRPT_AES_CTL_STOP_Msk (0x1ul << CRPT_AES_CTL_STOP_Pos) /*!< CRPT_T::AES_CTL: STOP Mask */
#define CRPT_AES_CTL_KEYSZ_Pos (2) /*!< CRPT_T::AES_CTL: KEYSZ Position */
#define CRPT_AES_CTL_KEYSZ_Msk (0x3ul << CRPT_AES_CTL_KEYSZ_Pos) /*!< CRPT_T::AES_CTL: KEYSZ Mask */
#define CRPT_AES_CTL_DMALAST_Pos (5) /*!< CRPT_T::AES_CTL: DMALAST Position */
#define CRPT_AES_CTL_DMALAST_Msk (0x1ul << CRPT_AES_CTL_DMALAST_Pos) /*!< CRPT_T::AES_CTL: DMALAST Mask */
#define CRPT_AES_CTL_DMACSCAD_Pos (6) /*!< CRPT_T::AES_CTL: DMACSCAD Position */
#define CRPT_AES_CTL_DMACSCAD_Msk (0x1ul << CRPT_AES_CTL_DMACSCAD_Pos) /*!< CRPT_T::AES_CTL: DMACSCAD Mask */
#define CRPT_AES_CTL_DMAEN_Pos (7) /*!< CRPT_T::AES_CTL: DMAEN Position */
#define CRPT_AES_CTL_DMAEN_Msk (0x1ul << CRPT_AES_CTL_DMAEN_Pos) /*!< CRPT_T::AES_CTL: DMAEN Mask */
#define CRPT_AES_CTL_OPMODE_Pos (8) /*!< CRPT_T::AES_CTL: OPMODE Position */
#define CRPT_AES_CTL_OPMODE_Msk (0xfful << CRPT_AES_CTL_OPMODE_Pos) /*!< CRPT_T::AES_CTL: OPMODE Mask */
#define CRPT_AES_CTL_ENCRPT_Pos (16) /*!< CRPT_T::AES_CTL: ENCRPT Position */
#define CRPT_AES_CTL_ENCRPT_Msk (0x1ul << CRPT_AES_CTL_ENCRPT_Pos) /*!< CRPT_T::AES_CTL: ENCRPT Mask */
#define CRPT_AES_CTL_OUTSWAP_Pos (22) /*!< CRPT_T::AES_CTL: OUTSWAP Position */
#define CRPT_AES_CTL_OUTSWAP_Msk (0x1ul << CRPT_AES_CTL_OUTSWAP_Pos) /*!< CRPT_T::AES_CTL: OUTSWAP Mask */
#define CRPT_AES_CTL_INSWAP_Pos (23) /*!< CRPT_T::AES_CTL: INSWAP Position */
#define CRPT_AES_CTL_INSWAP_Msk (0x1ul << CRPT_AES_CTL_INSWAP_Pos) /*!< CRPT_T::AES_CTL: INSWAP Mask */
#define CRPT_AES_CTL_CHANNEL_Pos (24) /*!< CRPT_T::AES_CTL: CHANNEL Position */
#define CRPT_AES_CTL_CHANNEL_Msk (0x3ul << CRPT_AES_CTL_CHANNEL_Pos) /*!< CRPT_T::AES_CTL: CHANNEL Mask */
#define CRPT_AES_CTL_KEYUNPRT_Pos (26) /*!< CRPT_T::AES_CTL: KEYUNPRT Position */
#define CRPT_AES_CTL_KEYUNPRT_Msk (0x1ful << CRPT_AES_CTL_KEYUNPRT_Pos) /*!< CRPT_T::AES_CTL: KEYUNPRT Mask */
#define CRPT_AES_CTL_KEYPRT_Pos (31) /*!< CRPT_T::AES_CTL: KEYPRT Position */
#define CRPT_AES_CTL_KEYPRT_Msk (0x1ul << CRPT_AES_CTL_KEYPRT_Pos) /*!< CRPT_T::AES_CTL: KEYPRT Mask */
#define CRPT_AES_STS_BUSY_Pos (0) /*!< CRPT_T::AES_STS: BUSY Position */
#define CRPT_AES_STS_BUSY_Msk (0x1ul << CRPT_AES_STS_BUSY_Pos) /*!< CRPT_T::AES_STS: BUSY Mask */
#define CRPT_AES_STS_INBUFEMPTY_Pos (8) /*!< CRPT_T::AES_STS: INBUFEMPTY Position */
#define CRPT_AES_STS_INBUFEMPTY_Msk (0x1ul << CRPT_AES_STS_INBUFEMPTY_Pos) /*!< CRPT_T::AES_STS: INBUFEMPTY Mask */
#define CRPT_AES_STS_INBUFFULL_Pos (9) /*!< CRPT_T::AES_STS: INBUFFULL Position */
#define CRPT_AES_STS_INBUFFULL_Msk (0x1ul << CRPT_AES_STS_INBUFFULL_Pos) /*!< CRPT_T::AES_STS: INBUFFULL Mask */
#define CRPT_AES_STS_INBUFERR_Pos (10) /*!< CRPT_T::AES_STS: INBUFERR Position */
#define CRPT_AES_STS_INBUFERR_Msk (0x1ul << CRPT_AES_STS_INBUFERR_Pos) /*!< CRPT_T::AES_STS: INBUFERR Mask */
#define CRPT_AES_STS_CNTERR_Pos (12) /*!< CRPT_T::AES_STS: CNTERR Position */
#define CRPT_AES_STS_CNTERR_Msk (0x1ul << CRPT_AES_STS_CNTERR_Pos) /*!< CRPT_T::AES_STS: CNTERR Mask */
#define CRPT_AES_STS_OUTBUFEMPTY_Pos (16) /*!< CRPT_T::AES_STS: OUTBUFEMPTY Position */
#define CRPT_AES_STS_OUTBUFEMPTY_Msk (0x1ul << CRPT_AES_STS_OUTBUFEMPTY_Pos) /*!< CRPT_T::AES_STS: OUTBUFEMPTY Mask */
#define CRPT_AES_STS_OUTBUFFULL_Pos (17) /*!< CRPT_T::AES_STS: OUTBUFFULL Position */
#define CRPT_AES_STS_OUTBUFFULL_Msk (0x1ul << CRPT_AES_STS_OUTBUFFULL_Pos) /*!< CRPT_T::AES_STS: OUTBUFFULL Mask */
#define CRPT_AES_STS_OUTBUFERR_Pos (18) /*!< CRPT_T::AES_STS: OUTBUFERR Position */
#define CRPT_AES_STS_OUTBUFERR_Msk (0x1ul << CRPT_AES_STS_OUTBUFERR_Pos) /*!< CRPT_T::AES_STS: OUTBUFERR Mask */
#define CRPT_AES_STS_BUSERR_Pos (20) /*!< CRPT_T::AES_STS: BUSERR Position */
#define CRPT_AES_STS_BUSERR_Msk (0x1ul << CRPT_AES_STS_BUSERR_Pos) /*!< CRPT_T::AES_STS: BUSERR Mask */
#define CRPT_AES_DATIN_DATIN_Pos (0) /*!< CRPT_T::AES_DATIN: DATIN Position */
#define CRPT_AES_DATIN_DATIN_Msk (0xfffffffful << CRPT_AES_DATIN_DATIN_Pos) /*!< CRPT_T::AES_DATIN: DATIN Mask */
#define CRPT_AES_DATOUT_DATOUT_Pos (0) /*!< CRPT_T::AES_DATOUT: DATOUT Position */
#define CRPT_AES_DATOUT_DATOUT_Msk (0xfffffffful << CRPT_AES_DATOUT_DATOUT_Pos) /*!< CRPT_T::AES_DATOUT: DATOUT Mask */
#define CRPT_AES0_KEYx_KEY_Pos (0) /*!< CRPT_T::AES0_KEY[8]: KEY Position */
#define CRPT_AES0_KEYx_KEY_Msk (0xfffffffful << CRPT_AES0_KEYx_KEY_Pos) /*!< CRPT_T::AES0_KEY[8]: KEY Mask */
#define CRPT_AES0_IVx_IV_Pos (0) /*!< CRPT_T::AES0_IV[4]: IV Position */
#define CRPT_AES0_IVx_IV_Msk (0xfffffffful << CRPT_AES0_IVx_IV_Pos) /*!< CRPT_T::AES0_IV[4]: IV Mask */
#define CRPT_AES0_SADDR_SADDR_Pos (0) /*!< CRPT_T::AES0_SADDR: SADDR Position */
#define CRPT_AES0_SADDR_SADDR_Msk (0xfffffffful << CRPT_AES0_SADDR_SADDR_Pos) /*!< CRPT_T::AES0_SADDR: SADDR Mask */
#define CRPT_AES0_DADDR_DADDR_Pos (0) /*!< CRPT_T::AES0_DADDR: DADDR Position */
#define CRPT_AES0_DADDR_DADDR_Msk (0xfffffffful << CRPT_AES0_DADDR_DADDR_Pos) /*!< CRPT_T::AES0_DADDR: DADDR Mask */
#define CRPT_AES0_CNT_CNT_Pos (0) /*!< CRPT_T::AES0_CNT: CNT Position */
#define CRPT_AES0_CNT_CNT_Msk (0xfffffffful << CRPT_AES0_CNT_CNT_Pos) /*!< CRPT_T::AES0_CNT: CNT Mask */
#define CRPT_AES1_KEYx_KEY_Pos (0) /*!< CRPT_T::AES1_KEY[8]: KEY Position */
#define CRPT_AES1_KEYx_KEY_Msk (0xfffffffful << CRPT_AES1_KEYx_KEY_Pos) /*!< CRPT_T::AES1_KEY[8]: KEY Mask */
#define CRPT_AES1_IVx_IV_Pos (0) /*!< CRPT_T::AES1_IV[4]: IV Position */
#define CRPT_AES1_IVx_IV_Msk (0xfffffffful << CRPT_AES1_IVx_IV_Pos) /*!< CRPT_T::AES1_IV[4]: IV Mask */
#define CRPT_AES1_SADDR_SADDR_Pos (0) /*!< CRPT_T::AES1_SADDR: SADDR Position */
#define CRPT_AES1_SADDR_SADDR_Msk (0xfffffffful << CRPT_AES1_SADDR_SADDR_Pos) /*!< CRPT_T::AES1_SADDR: SADDR Mask */
#define CRPT_AES1_DADDR_DADDR_Pos (0) /*!< CRPT_T::AES1_DADDR: DADDR Position */
#define CRPT_AES1_DADDR_DADDR_Msk (0xfffffffful << CRPT_AES1_DADDR_DADDR_Pos) /*!< CRPT_T::AES1_DADDR: DADDR Mask */
#define CRPT_AES1_CNT_CNT_Pos (0) /*!< CRPT_T::AES1_CNT: CNT Position */
#define CRPT_AES1_CNT_CNT_Msk (0xfffffffful << CRPT_AES1_CNT_CNT_Pos) /*!< CRPT_T::AES1_CNT: CNT Mask */
#define CRPT_AES2_KEYx_KEY_Pos (0) /*!< CRPT_T::AES2_KEY[8]: KEY Position */
#define CRPT_AES2_KEYx_KEY_Msk (0xfffffffful << CRPT_AES2_KEYx_KEY_Pos) /*!< CRPT_T::AES2_KEY[8]: KEY Mask */
#define CRPT_AES2_IVx_IV_Pos (0) /*!< CRPT_T::AES2_IV[4]: IV Position */
#define CRPT_AES2_IVx_IV_Msk (0xfffffffful << CRPT_AES2_IVx_IV_Pos) /*!< CRPT_T::AES2_IV[4]: IV Mask */
#define CRPT_AES2_SADDR_SADDR_Pos (0) /*!< CRPT_T::AES2_SADDR: SADDR Position */
#define CRPT_AES2_SADDR_SADDR_Msk (0xfffffffful << CRPT_AES2_SADDR_SADDR_Pos) /*!< CRPT_T::AES2_SADDR: SADDR Mask */
#define CRPT_AES2_DADDR_DADDR_Pos (0) /*!< CRPT_T::AES2_DADDR: DADDR Position */
#define CRPT_AES2_DADDR_DADDR_Msk (0xfffffffful << CRPT_AES2_DADDR_DADDR_Pos) /*!< CRPT_T::AES2_DADDR: DADDR Mask */
#define CRPT_AES2_CNT_CNT_Pos (0) /*!< CRPT_T::AES2_CNT: CNT Position */
#define CRPT_AES2_CNT_CNT_Msk (0xfffffffful << CRPT_AES2_CNT_CNT_Pos) /*!< CRPT_T::AES2_CNT: CNT Mask */
#define CRPT_AES3_KEYx_KEY_Pos (0) /*!< CRPT_T::AES3_KEY[8]: KEY Position */
#define CRPT_AES3_KEYx_KEY_Msk (0xfffffffful << CRPT_AES3_KEYx_KEY_Pos) /*!< CRPT_T::AES3_KEY[8]: KEY Mask */
#define CRPT_AES3_IVx_IV_Pos (0) /*!< CRPT_T::AES3_IV[4]: IV Position */
#define CRPT_AES3_IVx_IV_Msk (0xfffffffful << CRPT_AES3_IVx_IV_Pos) /*!< CRPT_T::AES3_IV[4]: IV Mask */
#define CRPT_AES3_SADDR_SADDR_Pos (0) /*!< CRPT_T::AES3_SADDR: SADDR Position */
#define CRPT_AES3_SADDR_SADDR_Msk (0xfffffffful << CRPT_AES3_SADDR_SADDR_Pos) /*!< CRPT_T::AES3_SADDR: SADDR Mask */
#define CRPT_AES3_DADDR_DADDR_Pos (0) /*!< CRPT_T::AES3_DADDR: DADDR Position */
#define CRPT_AES3_DADDR_DADDR_Msk (0xfffffffful << CRPT_AES3_DADDR_DADDR_Pos) /*!< CRPT_T::AES3_DADDR: DADDR Mask */
#define CRPT_AES3_CNT_CNT_Pos (0) /*!< CRPT_T::AES3_CNT: CNT Position */
#define CRPT_AES3_CNT_CNT_Msk (0xfffffffful << CRPT_AES3_CNT_CNT_Pos) /*!< CRPT_T::AES3_CNT: CNT Mask */
#define CRPT_TDES_CTL_START_Pos (0) /*!< CRPT_T::TDES_CTL: START Position */
#define CRPT_TDES_CTL_START_Msk (0x1ul << CRPT_TDES_CTL_START_Pos) /*!< CRPT_T::TDES_CTL: START Mask */
#define CRPT_TDES_CTL_STOP_Pos (1) /*!< CRPT_T::TDES_CTL: STOP Position */
#define CRPT_TDES_CTL_STOP_Msk (0x1ul << CRPT_TDES_CTL_STOP_Pos) /*!< CRPT_T::TDES_CTL: STOP Mask */
#define CRPT_TDES_CTL_TMODE_Pos (2) /*!< CRPT_T::TDES_CTL: TMODE Position */
#define CRPT_TDES_CTL_TMODE_Msk (0x1ul << CRPT_TDES_CTL_TMODE_Pos) /*!< CRPT_T::TDES_CTL: TMODE Mask */
#define CRPT_TDES_CTL_3KEYS_Pos (3) /*!< CRPT_T::TDES_CTL: 3KEYS Position */
#define CRPT_TDES_CTL_3KEYS_Msk (0x1ul << CRPT_TDES_CTL_3KEYS_Pos) /*!< CRPT_T::TDES_CTL: 3KEYS Mask */
#define CRPT_TDES_CTL_DMALAST_Pos (5) /*!< CRPT_T::TDES_CTL: DMALAST Position */
#define CRPT_TDES_CTL_DMALAST_Msk (0x1ul << CRPT_TDES_CTL_DMALAST_Pos) /*!< CRPT_T::TDES_CTL: DMALAST Mask */
#define CRPT_TDES_CTL_DMACSCAD_Pos (6) /*!< CRPT_T::TDES_CTL: DMACSCAD Position */
#define CRPT_TDES_CTL_DMACSCAD_Msk (0x1ul << CRPT_TDES_CTL_DMACSCAD_Pos) /*!< CRPT_T::TDES_CTL: DMACSCAD Mask */
#define CRPT_TDES_CTL_DMAEN_Pos (7) /*!< CRPT_T::TDES_CTL: DMAEN Position */
#define CRPT_TDES_CTL_DMAEN_Msk (0x1ul << CRPT_TDES_CTL_DMAEN_Pos) /*!< CRPT_T::TDES_CTL: DMAEN Mask */
#define CRPT_TDES_CTL_OPMODE_Pos (8) /*!< CRPT_T::TDES_CTL: OPMODE Position */
#define CRPT_TDES_CTL_OPMODE_Msk (0x7ul << CRPT_TDES_CTL_OPMODE_Pos) /*!< CRPT_T::TDES_CTL: OPMODE Mask */
#define CRPT_TDES_CTL_ENCRPT_Pos (16) /*!< CRPT_T::TDES_CTL: ENCRPT Position */
#define CRPT_TDES_CTL_ENCRPT_Msk (0x1ul << CRPT_TDES_CTL_ENCRPT_Pos) /*!< CRPT_T::TDES_CTL: ENCRPT Mask */
#define CRPT_TDES_CTL_BLKSWAP_Pos (21) /*!< CRPT_T::TDES_CTL: BLKSWAP Position */
#define CRPT_TDES_CTL_BLKSWAP_Msk (0x1ul << CRPT_TDES_CTL_BLKSWAP_Pos) /*!< CRPT_T::TDES_CTL: BLKSWAP Mask */
#define CRPT_TDES_CTL_OUTSWAP_Pos (22) /*!< CRPT_T::TDES_CTL: OUTSWAP Position */
#define CRPT_TDES_CTL_OUTSWAP_Msk (0x1ul << CRPT_TDES_CTL_OUTSWAP_Pos) /*!< CRPT_T::TDES_CTL: OUTSWAP Mask */
#define CRPT_TDES_CTL_INSWAP_Pos (23) /*!< CRPT_T::TDES_CTL: INSWAP Position */
#define CRPT_TDES_CTL_INSWAP_Msk (0x1ul << CRPT_TDES_CTL_INSWAP_Pos) /*!< CRPT_T::TDES_CTL: INSWAP Mask */
#define CRPT_TDES_CTL_CHANNEL_Pos (24) /*!< CRPT_T::TDES_CTL: CHANNEL Position */
#define CRPT_TDES_CTL_CHANNEL_Msk (0x3ul << CRPT_TDES_CTL_CHANNEL_Pos) /*!< CRPT_T::TDES_CTL: CHANNEL Mask */
#define CRPT_TDES_CTL_KEYUNPRT_Pos (26) /*!< CRPT_T::TDES_CTL: KEYUNPRT Position */
#define CRPT_TDES_CTL_KEYUNPRT_Msk (0x1ful << CRPT_TDES_CTL_KEYUNPRT_Pos) /*!< CRPT_T::TDES_CTL: KEYUNPRT Mask */
#define CRPT_TDES_CTL_KEYPRT_Pos (31) /*!< CRPT_T::TDES_CTL: KEYPRT Position */
#define CRPT_TDES_CTL_KEYPRT_Msk (0x1ul << CRPT_TDES_CTL_KEYPRT_Pos) /*!< CRPT_T::TDES_CTL: KEYPRT Mask */
#define CRPT_TDES_STS_BUSY_Pos (0) /*!< CRPT_T::TDES_STS: BUSY Position */
#define CRPT_TDES_STS_BUSY_Msk (0x1ul << CRPT_TDES_STS_BUSY_Pos) /*!< CRPT_T::TDES_STS: BUSY Mask */
#define CRPT_TDES_STS_INBUFEMPTY_Pos (8) /*!< CRPT_T::TDES_STS: INBUFEMPTY Position */
#define CRPT_TDES_STS_INBUFEMPTY_Msk (0x1ul << CRPT_TDES_STS_INBUFEMPTY_Pos) /*!< CRPT_T::TDES_STS: INBUFEMPTY Mask */
#define CRPT_TDES_STS_INBUFFULL_Pos (9) /*!< CRPT_T::TDES_STS: INBUFFULL Position */
#define CRPT_TDES_STS_INBUFFULL_Msk (0x1ul << CRPT_TDES_STS_INBUFFULL_Pos) /*!< CRPT_T::TDES_STS: INBUFFULL Mask */
#define CRPT_TDES_STS_INBUFERR_Pos (10) /*!< CRPT_T::TDES_STS: INBUFERR Position */
#define CRPT_TDES_STS_INBUFERR_Msk (0x1ul << CRPT_TDES_STS_INBUFERR_Pos) /*!< CRPT_T::TDES_STS: INBUFERR Mask */
#define CRPT_TDES_STS_OUTBUFEMPTY_Pos (16) /*!< CRPT_T::TDES_STS: OUTBUFEMPTY Position */
#define CRPT_TDES_STS_OUTBUFEMPTY_Msk (0x1ul << CRPT_TDES_STS_OUTBUFEMPTY_Pos) /*!< CRPT_T::TDES_STS: OUTBUFEMPTY Mask */
#define CRPT_TDES_STS_OUTBUFFULL_Pos (17) /*!< CRPT_T::TDES_STS: OUTBUFFULL Position */
#define CRPT_TDES_STS_OUTBUFFULL_Msk (0x1ul << CRPT_TDES_STS_OUTBUFFULL_Pos) /*!< CRPT_T::TDES_STS: OUTBUFFULL Mask */
#define CRPT_TDES_STS_OUTBUFERR_Pos (18) /*!< CRPT_T::TDES_STS: OUTBUFERR Position */
#define CRPT_TDES_STS_OUTBUFERR_Msk (0x1ul << CRPT_TDES_STS_OUTBUFERR_Pos) /*!< CRPT_T::TDES_STS: OUTBUFERR Mask */
#define CRPT_TDES_STS_BUSERR_Pos (20) /*!< CRPT_T::TDES_STS: BUSERR Position */
#define CRPT_TDES_STS_BUSERR_Msk (0x1ul << CRPT_TDES_STS_BUSERR_Pos) /*!< CRPT_T::TDES_STS: BUSERR Mask */
#define CRPT_TDES0_KEYxH_KEY_Pos (0) /*!< CRPT_T::TDES0_KEYxH: KEY Position */
#define CRPT_TDES0_KEYxH_KEY_Msk (0xfffffffful << CRPT_TDES0_KEYxH_KEY_Pos) /*!< CRPT_T::TDES0_KEYxH: KEY Mask */
#define CRPT_TDES0_KEYxL_KEY_Pos (0) /*!< CRPT_T::TDES0_KEYxL: KEY Position */
#define CRPT_TDES0_KEYxL_KEY_Msk (0xfffffffful << CRPT_TDES0_KEYxL_KEY_Pos) /*!< CRPT_T::TDES0_KEYxL: KEY Mask */
#define CRPT_TDES0_IVH_IV_Pos (0) /*!< CRPT_T::TDES0_IVH: IV Position */
#define CRPT_TDES0_IVH_IV_Msk (0xfffffffful << CRPT_TDES0_IVH_IV_Pos) /*!< CRPT_T::TDES0_IVH: IV Mask */
#define CRPT_TDES0_IVL_IV_Pos (0) /*!< CRPT_T::TDES0_IVL: IV Position */
#define CRPT_TDES0_IVL_IV_Msk (0xfffffffful << CRPT_TDES0_IVL_IV_Pos) /*!< CRPT_T::TDES0_IVL: IV Mask */
#define CRPT_TDES0_SADDR_SADDR_Pos (0) /*!< CRPT_T::TDES0_SADDR: SADDR Position */
#define CRPT_TDES0_SADDR_SADDR_Msk (0xfffffffful << CRPT_TDES0_SADDR_SADDR_Pos) /*!< CRPT_T::TDES0_SADDR: SADDR Mask */
#define CRPT_TDES0_DADDR_DADDR_Pos (0) /*!< CRPT_T::TDES0_DADDR: DADDR Position */
#define CRPT_TDES0_DADDR_DADDR_Msk (0xfffffffful << CRPT_TDES0_DADDR_DADDR_Pos) /*!< CRPT_T::TDES0_DADDR: DADDR Mask */
#define CRPT_TDES0_CNT_CNT_Pos (0) /*!< CRPT_T::TDES0_CNT: CNT Position */
#define CRPT_TDES0_CNT_CNT_Msk (0xfffffffful << CRPT_TDES0_CNT_CNT_Pos) /*!< CRPT_T::TDES0_CNT: CNT Mask */
#define CRPT_TDES_DATIN_DATIN_Pos (0) /*!< CRPT_T::TDES_DATIN: DATIN Position */
#define CRPT_TDES_DATIN_DATIN_Msk (0xfffffffful << CRPT_TDES_DATIN_DATIN_Pos) /*!< CRPT_T::TDES_DATIN: DATIN Mask */
#define CRPT_TDES_DATOUT_DATOUT_Pos (0) /*!< CRPT_T::TDES_DATOUT: DATOUT Position */
#define CRPT_TDES_DATOUT_DATOUT_Msk (0xfffffffful << CRPT_TDES_DATOUT_DATOUT_Pos) /*!< CRPT_T::TDES_DATOUT: DATOUT Mask */
#define CRPT_TDES1_KEYxH_KEY_Pos (0) /*!< CRPT_T::TDES1_KEYxH: KEY Position */
#define CRPT_TDES1_KEYxH_KEY_Msk (0xfffffffful << CRPT_TDES1_KEYxH_KEY_Pos) /*!< CRPT_T::TDES1_KEYxH: KEY Mask */
#define CRPT_TDES1_KEYxL_KEY_Pos (0) /*!< CRPT_T::TDES1_KEYxL: KEY Position */
#define CRPT_TDES1_KEYxL_KEY_Msk (0xfffffffful << CRPT_TDES1_KEY1L_KEY_Pos) /*!< CRPT_T::TDES1_KEYxL: KEY Mask */
#define CRPT_TDES1_IVH_IV_Pos (0) /*!< CRPT_T::TDES1_IVH: IV Position */
#define CRPT_TDES1_IVH_IV_Msk (0xfffffffful << CRPT_TDES1_IVH_IV_Pos) /*!< CRPT_T::TDES1_IVH: IV Mask */
#define CRPT_TDES1_IVL_IV_Pos (0) /*!< CRPT_T::TDES1_IVL: IV Position */
#define CRPT_TDES1_IVL_IV_Msk (0xfffffffful << CRPT_TDES1_IVL_IV_Pos) /*!< CRPT_T::TDES1_IVL: IV Mask */
#define CRPT_TDES1_SADDR_SADDR_Pos (0) /*!< CRPT_T::TDES1_SADDR: SADDR Position */
#define CRPT_TDES1_SADDR_SADDR_Msk (0xfffffffful << CRPT_TDES1_SADDR_SADDR_Pos) /*!< CRPT_T::TDES1_SADDR: SADDR Mask */
#define CRPT_TDES1_DADDR_DADDR_Pos (0) /*!< CRPT_T::TDES1_DADDR: DADDR Position */
#define CRPT_TDES1_DADDR_DADDR_Msk (0xfffffffful << CRPT_TDES1_DADDR_DADDR_Pos) /*!< CRPT_T::TDES1_DADDR: DADDR Mask */
#define CRPT_TDES1_CNT_CNT_Pos (0) /*!< CRPT_T::TDES1_CNT: CNT Position */
#define CRPT_TDES1_CNT_CNT_Msk (0xfffffffful << CRPT_TDES1_CNT_CNT_Pos) /*!< CRPT_T::TDES1_CNT: CNT Mask */
#define CRPT_TDES2_KEYxH_KEY_Pos (0) /*!< CRPT_T::TDES2_KEYxH: KEY Position */
#define CRPT_TDES2_KEYxH_KEY_Msk (0xfffffffful << CRPT_TDES2_KEYxH_KEY_Pos) /*!< CRPT_T::TDES2_KEYxH: KEY Mask */
#define CRPT_TDES2_KEYxL_KEY_Pos (0) /*!< CRPT_T::TDES2_KEYxL: KEY Position */
#define CRPT_TDES2_KEYxL_KEY_Msk (0xfffffffful << CRPT_TDES2_KEYxL_KEY_Pos) /*!< CRPT_T::TDES2_KEYxL: KEY Mask */
#define CRPT_TDES2_IVH_IV_Pos (0) /*!< CRPT_T::TDES2_IVH: IV Position */
#define CRPT_TDES2_IVH_IV_Msk (0xfffffffful << CRPT_TDES2_IVH_IV_Pos) /*!< CRPT_T::TDES2_IVH: IV Mask */
#define CRPT_TDES2_IVL_IV_Pos (0) /*!< CRPT_T::TDES2_IVL: IV Position */
#define CRPT_TDES2_IVL_IV_Msk (0xfffffffful << CRPT_TDES2_IVL_IV_Pos) /*!< CRPT_T::TDES2_IVL: IV Mask */
#define CRPT_TDES2_SADDR_SADDR_Pos (0) /*!< CRPT_T::TDES2_SADDR: SADDR Position */
#define CRPT_TDES2_SADDR_SADDR_Msk (0xfffffffful << CRPT_TDES2_SADDR_SADDR_Pos) /*!< CRPT_T::TDES2_SADDR: SADDR Mask */
#define CRPT_TDES2_DADDR_DADDR_Pos (0) /*!< CRPT_T::TDES2_DADDR: DADDR Position */
#define CRPT_TDES2_DADDR_DADDR_Msk (0xfffffffful << CRPT_TDES2_DADDR_DADDR_Pos) /*!< CRPT_T::TDES2_DADDR: DADDR Mask */
#define CRPT_TDES2_CNT_CNT_Pos (0) /*!< CRPT_T::TDES2_CNT: CNT Position */
#define CRPT_TDES2_CNT_CNT_Msk (0xfffffffful << CRPT_TDES2_CNT_CNT_Pos) /*!< CRPT_T::TDES2_CNT: CNT Mask */
#define CRPT_TDES3_KEYxH_KEY_Pos (0) /*!< CRPT_T::TDES3_KEYxH: KEY Position */
#define CRPT_TDES3_KEYxH_KEY_Msk (0xfffffffful << CRPT_TDES3_KEYxH_KEY_Pos) /*!< CRPT_T::TDES3_KEYxH: KEY Mask */
#define CRPT_TDES3_KEYxL_KEY_Pos (0) /*!< CRPT_T::TDES3_KEYxL: KEY Position */
#define CRPT_TDES3_KEYxL_KEY_Msk (0xfffffffful << CRPT_TDES3_KEYxL_KEY_Pos) /*!< CRPT_T::TDES3_KEYxL: KEY Mask */
#define CRPT_TDES3_IVH_IV_Pos (0) /*!< CRPT_T::TDES3_IVH: IV Position */
#define CRPT_TDES3_IVH_IV_Msk (0xfffffffful << CRPT_TDES3_IVH_IV_Pos) /*!< CRPT_T::TDES3_IVH: IV Mask */
#define CRPT_TDES3_IVL_IV_Pos (0) /*!< CRPT_T::TDES3_IVL: IV Position */
#define CRPT_TDES3_IVL_IV_Msk (0xfffffffful << CRPT_TDES3_IVL_IV_Pos) /*!< CRPT_T::TDES3_IVL: IV Mask */
#define CRPT_TDES3_SADDR_SADDR_Pos (0) /*!< CRPT_T::TDES3_SADDR: SADDR Position */
#define CRPT_TDES3_SADDR_SADDR_Msk (0xfffffffful << CRPT_TDES3_SADDR_SADDR_Pos) /*!< CRPT_T::TDES3_SADDR: SADDR Mask */
#define CRPT_TDES3_DADDR_DADDR_Pos (0) /*!< CRPT_T::TDES3_DADDR: DADDR Position */
#define CRPT_TDES3_DADDR_DADDR_Msk (0xfffffffful << CRPT_TDES3_DADDR_DADDR_Pos) /*!< CRPT_T::TDES3_DADDR: DADDR Mask */
#define CRPT_TDES3_CNT_CNT_Pos (0) /*!< CRPT_T::TDES3_CNT: CNT Position */
#define CRPT_TDES3_CNT_CNT_Msk (0xfffffffful << CRPT_TDES3_CNT_CNT_Pos) /*!< CRPT_T::TDES3_CNT: CNT Mask */
#define CRPT_HMAC_CTL_START_Pos (0) /*!< CRPT_T::HMAC_CTL: START Position */
#define CRPT_HMAC_CTL_START_Msk (0x1ul << CRPT_HMAC_CTL_START_Pos) /*!< CRPT_T::HMAC_CTL: START Mask */
#define CRPT_HMAC_CTL_STOP_Pos (1) /*!< CRPT_T::HMAC_CTL: STOP Position */
#define CRPT_HMAC_CTL_STOP_Msk (0x1ul << CRPT_HMAC_CTL_STOP_Pos) /*!< CRPT_T::HMAC_CTL: STOP Mask */
#define CRPT_HMAC_CTL_HMACEN_Pos (4) /*!< CRPT_T::HMAC_CTL: HMACEN Position */
#define CRPT_HMAC_CTL_HMACEN_Msk (0x1ul << CRPT_HMAC_CTL_HMACEN_Pos) /*!< CRPT_T::HMAC_CTL: HMACEN Mask */
#define CRPT_HMAC_CTL_DMALAST_Pos (5) /*!< CRPT_T::HMAC_CTL: DMALAST Position */
#define CRPT_HMAC_CTL_DMALAST_Msk (0x1ul << CRPT_HMAC_CTL_DMALAST_Pos) /*!< CRPT_T::HMAC_CTL: DMALAST Mask */
#define CRPT_HMAC_CTL_DMAEN_Pos (7) /*!< CRPT_T::HMAC_CTL: DMAEN Position */
#define CRPT_HMAC_CTL_DMAEN_Msk (0x1ul << CRPT_HMAC_CTL_DMAEN_Pos) /*!< CRPT_T::HMAC_CTL: DMAEN Mask */
#define CRPT_HMAC_CTL_OPMODE_Pos (8) /*!< CRPT_T::HMAC_CTL: OPMODE Position */
#define CRPT_HMAC_CTL_OPMODE_Msk (0x7ul << CRPT_HMAC_CTL_OPMODE_Pos) /*!< CRPT_T::HMAC_CTL: OPMODE Mask */
#define CRPT_HMAC_CTL_OUTSWAP_Pos (22) /*!< CRPT_T::HMAC_CTL: OUTSWAP Position */
#define CRPT_HMAC_CTL_OUTSWAP_Msk (0x1ul << CRPT_HMAC_CTL_OUTSWAP_Pos) /*!< CRPT_T::HMAC_CTL: OUTSWAP Mask */
#define CRPT_HMAC_CTL_INSWAP_Pos (23) /*!< CRPT_T::HMAC_CTL: INSWAP Position */
#define CRPT_HMAC_CTL_INSWAP_Msk (0x1ul << CRPT_HMAC_CTL_INSWAP_Pos) /*!< CRPT_T::HMAC_CTL: INSWAP Mask */
#define CRPT_HMAC_STS_BUSY_Pos (0) /*!< CRPT_T::HMAC_STS: BUSY Position */
#define CRPT_HMAC_STS_BUSY_Msk (0x1ul << CRPT_HMAC_STS_BUSY_Pos) /*!< CRPT_T::HMAC_STS: BUSY Mask */
#define CRPT_HMAC_STS_DMABUSY_Pos (1) /*!< CRPT_T::HMAC_STS: DMABUSY Position */
#define CRPT_HMAC_STS_DMABUSY_Msk (0x1ul << CRPT_HMAC_STS_DMABUSY_Pos) /*!< CRPT_T::HMAC_STS: DMABUSY Mask */
#define CRPT_HMAC_STS_DMAERR_Pos (8) /*!< CRPT_T::HMAC_STS: DMAERR Position */
#define CRPT_HMAC_STS_DMAERR_Msk (0x1ul << CRPT_HMAC_STS_DMAERR_Pos) /*!< CRPT_T::HMAC_STS: DMAERR Mask */
#define CRPT_HMAC_STS_DATINREQ_Pos (16) /*!< CRPT_T::HMAC_STS: DATINREQ Position */
#define CRPT_HMAC_STS_DATINREQ_Msk (0x1ul << CRPT_HMAC_STS_DATINREQ_Pos) /*!< CRPT_T::HMAC_STS: DATINREQ Mask */
#define CRPT_HMAC_DGSTx_DGST_Pos (0) /*!< CRPT_T::HMAC_DGST[16]: DGST Position */
#define CRPT_HMAC_DGSTx_DGST_Msk (0xfffffffful << CRPT_HMAC_DGSTx_DGST_Pos) /*!< CRPT_T::HMAC_DGST[16]: DGST Mask */
#define CRPT_HMAC_KEYCNT_KEYCNT_Pos (0) /*!< CRPT_T::HMAC_KEYCNT: KEYCNT Position */
#define CRPT_HMAC_KEYCNT_KEYCNT_Msk (0xfffffffful << CRPT_HMAC_KEYCNT_KEYCNT_Pos) /*!< CRPT_T::HMAC_KEYCNT: KEYCNT Mask */
#define CRPT_HMAC_SADDR_SADDR_Pos (0) /*!< CRPT_T::HMAC_SADDR: SADDR Position */
#define CRPT_HMAC_SADDR_SADDR_Msk (0xfffffffful << CRPT_HMAC_SADDR_SADDR_Pos) /*!< CRPT_T::HMAC_SADDR: SADDR Mask */
#define CRPT_HMAC_DMACNT_DMACNT_Pos (0) /*!< CRPT_T::HMAC_DMACNT: DMACNT Position */
#define CRPT_HMAC_DMACNT_DMACNT_Msk (0xfffffffful << CRPT_HMAC_DMACNT_DMACNT_Pos) /*!< CRPT_T::HMAC_DMACNT: DMACNT Mask */
#define CRPT_HMAC_DATIN_DATIN_Pos (0) /*!< CRPT_T::HMAC_DATIN: DATIN Position */
#define CRPT_HMAC_DATIN_DATIN_Msk (0xfffffffful << CRPT_HMAC_DATIN_DATIN_Pos) /*!< CRPT_T::HMAC_DATIN: DATIN Mask */
#define CRPT_ECC_CTL_START_Pos (0) /*!< CRPT_T::ECC_CTL: START Position */
#define CRPT_ECC_CTL_START_Msk (0x1ul << CRPT_ECC_CTL_START_Pos) /*!< CRPT_T::ECC_CTL: START Mask */
#define CRPT_ECC_CTL_STOP_Pos (1) /*!< CRPT_T::ECC_CTL: STOP Position */
#define CRPT_ECC_CTL_STOP_Msk (0x1ul << CRPT_ECC_CTL_STOP_Pos) /*!< CRPT_T::ECC_CTL: STOP Mask */
#define CRPT_ECC_CTL_DMAEN_Pos (7) /*!< CRPT_T::ECC_CTL: DMAEN Position */
#define CRPT_ECC_CTL_DMAEN_Msk (0x1ul << CRPT_ECC_CTL_DMAEN_Pos) /*!< CRPT_T::ECC_CTL: DMAEN Mask */
#define CRPT_ECC_CTL_FSEL_Pos (8) /*!< CRPT_T::ECC_CTL: FSEL Position */
#define CRPT_ECC_CTL_FSEL_Msk (0x1ul << CRPT_ECC_CTL_FSEL_Pos) /*!< CRPT_T::ECC_CTL: FSEL Mask */
#define CRPT_ECC_CTL_ECCOP_Pos (9) /*!< CRPT_T::ECC_CTL: ECCOP Position */
#define CRPT_ECC_CTL_ECCOP_Msk (0x3ul << CRPT_ECC_CTL_ECCOP_Pos) /*!< CRPT_T::ECC_CTL: ECCOP Mask */
#define CRPT_ECC_CTL_MODOP_Pos (11) /*!< CRPT_T::ECC_CTL: MODOP Position */
#define CRPT_ECC_CTL_MODOP_Msk (0x3ul << CRPT_ECC_CTL_MODOP_Pos) /*!< CRPT_T::ECC_CTL: MODOP Mask */
#define CRPT_ECC_CTL_LDP1_Pos (16) /*!< CRPT_T::ECC_CTL: LDP1 Position */
#define CRPT_ECC_CTL_LDP1_Msk (0x1ul << CRPT_ECC_CTL_LDP1_Pos) /*!< CRPT_T::ECC_CTL: LDP1 Mask */
#define CRPT_ECC_CTL_LDP2_Pos (17) /*!< CRPT_T::ECC_CTL: LDP2 Position */
#define CRPT_ECC_CTL_LDP2_Msk (0x1ul << CRPT_ECC_CTL_LDP2_Pos) /*!< CRPT_T::ECC_CTL: LDP2 Mask */
#define CRPT_ECC_CTL_LDA_Pos (18) /*!< CRPT_T::ECC_CTL: LDA Position */
#define CRPT_ECC_CTL_LDA_Msk (0x1ul << CRPT_ECC_CTL_LDA_Pos) /*!< CRPT_T::ECC_CTL: LDA Mask */
#define CRPT_ECC_CTL_LDB_Pos (19) /*!< CRPT_T::ECC_CTL: LDB Position */
#define CRPT_ECC_CTL_LDB_Msk (0x1ul << CRPT_ECC_CTL_LDB_Pos) /*!< CRPT_T::ECC_CTL: LDB Mask */
#define CRPT_ECC_CTL_LDN_Pos (20) /*!< CRPT_T::ECC_CTL: LDN Position */
#define CRPT_ECC_CTL_LDN_Msk (0x1ul << CRPT_ECC_CTL_LDN_Pos) /*!< CRPT_T::ECC_CTL: LDN Mask */
#define CRPT_ECC_CTL_LDK_Pos (21) /*!< CRPT_T::ECC_CTL: LDK Position */
#define CRPT_ECC_CTL_LDK_Msk (0x1ul << CRPT_ECC_CTL_LDK_Pos) /*!< CRPT_T::ECC_CTL: LDK Mask */
#define CRPT_ECC_CTL_CURVEM_Pos (22) /*!< CRPT_T::ECC_CTL: CURVEM Position */
#define CRPT_ECC_CTL_CURVEM_Msk (0x3fful << CRPT_ECC_CTL_CURVEM_Pos) /*!< CRPT_T::ECC_CTL: CURVEM Mask */
#define CRPT_ECC_STS_BUSY_Pos (0) /*!< CRPT_T::ECC_STS: BUSY Position */
#define CRPT_ECC_STS_BUSY_Msk (0x1ul << CRPT_ECC_STS_BUSY_Pos) /*!< CRPT_T::ECC_STS: BUSY Mask */
#define CRPT_ECC_STS_DMABUSY_Pos (1) /*!< CRPT_T::ECC_STS: DMABUSY Position */
#define CRPT_ECC_STS_DMABUSY_Msk (0x1ul << CRPT_ECC_STS_DMABUSY_Pos) /*!< CRPT_T::ECC_STS: DMABUSY Mask */
#define CRPT_ECC_STS_BUSERR_Pos (16) /*!< CRPT_T::ECC_STS: BUSERR Position */
#define CRPT_ECC_STS_BUSERR_Msk (0x1ul << CRPT_ECC_STS_BUSERR_Pos) /*!< CRPT_T::ECC_STS: BUSERR Mask */
#define CRPT_ECC_X1_POINTX1_Pos (0) /*!< CRPT_T::ECC_X1[18]: POINTX1 Position */
#define CRPT_ECC_X1_POINTX1_Msk (0xfffffffful << CRPT_ECC_X1_POINTX1_Pos) /*!< CRPT_T::ECC_X1[18]: POINTX1 Mask */
#define CRPT_ECC_Y1_POINTY1_Pos (0) /*!< CRPT_T::ECC_Y1[18]: POINTY1 Position */
#define CRPT_ECC_Y1_POINTY1_Msk (0xfffffffful << CRPT_ECC_Y1_POINTY1_Pos) /*!< CRPT_T::ECC_Y1[18]: POINTY1 Mask */
#define CRPT_ECC_X2_POINTX2_Pos (0) /*!< CRPT_T::ECC_X2[18]: POINTX2 Position */
#define CRPT_ECC_X2_POINTX2_Msk (0xfffffffful << CRPT_ECC_X2_POINTX2_Pos) /*!< CRPT_T::ECC_X2[18]: POINTX2 Mask */
#define CRPT_ECC_Y2_POINTY2_Pos (0) /*!< CRPT_T::ECC_Y2[18]: POINTY2 Position */
#define CRPT_ECC_Y2_POINTY2_Msk (0xfffffffful << CRPT_ECC_Y2_POINTY2_Pos) /*!< CRPT_T::ECC_Y2[18]: POINTY2 Mask */
#define CRPT_ECC_A_CURVEA_Pos (0) /*!< CRPT_T::ECC_A[18]: CURVEA Position */
#define CRPT_ECC_A_CURVEA_Msk (0xfffffffful << CRPT_ECC_A_CURVEA_Pos) /*!< CRPT_T::ECC_A[18]: CURVEA Mask */
#define CRPT_ECC_B_CURVEB_Pos (0) /*!< CRPT_T::ECC_B[18]: CURVEB Position */
#define CRPT_ECC_B_CURVEB_Msk (0xfffffffful << CRPT_ECC_B_CURVEB_Pos) /*!< CRPT_T::ECC_B[18]: CURVEB Mask */
#define CRPT_ECC_N_CURVEN_Pos (0) /*!< CRPT_T::ECC_N[18]: CURVEN Position */
#define CRPT_ECC_N_CURVEN_Msk (0xfffffffful << CRPT_ECC_N_CURVEN_Pos) /*!< CRPT_T::ECC_N[18]: CURVEN Mask */
#define CRPT_ECC_K_SCALARK_Pos (0) /*!< CRPT_T::ECC_K[18]: SCALARK Position */
#define CRPT_ECC_K_SCALARK_Msk (0xfffffffful << CRPT_ECC_K_SCALARK_Pos) /*!< CRPT_T::ECC_K[18]: SCALARK Mask */
#define CRPT_ECC_DADDR_DADDR_Pos (0) /*!< CRPT_T::ECC_DADDR: DADDR Position */
#define CRPT_ECC_DADDR_DADDR_Msk (0xfffffffful << CRPT_ECC_DADDR_DADDR_Pos) /*!< CRPT_T::ECC_DADDR: DADDR Mask */
#define CRPT_ECC_STARTREG_STARTREG_Pos (0) /*!< CRPT_T::ECC_STARTREG: STARTREG Position*/
#define CRPT_ECC_STARTREG_STARTREG_Msk (0xfffffffful << CRPT_ECC_STARTREG_STARTREG_Pos) /*!< CRPT_T::ECC_STARTREG: STARTREG Mask */
#define CRPT_ECC_WORDCNT_WORDCNT_Pos (0) /*!< CRPT_T::ECC_WORDCNT: WORDCNT Position */
#define CRPT_ECC_WORDCNT_WORDCNT_Msk (0xfffffffful << CRPT_ECC_WORDCNT_WORDCNT_Pos) /*!< CRPT_T::ECC_WORDCNT: WORDCNT Mask */
/**@}*/ /* CRPT_CONST CRYPTO */
/**@}*/ /* end of CRYPTO register group */
/*---------------------- Enhanced Analog to Digital Converter -------------------------*/
/**
@addtogroup EADC Enhanced Analog to Digital Converter(EADC)
Memory Mapped Structure for EADC Controller
@{ */
typedef struct {
/**
* @var EADC_T::DAT[19]
* Offset: 0x00 ADC Data Register 0~18 for Sample Module 0~18
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |RESULT |ADC Conversion Result
* | | |This field contains 12 bits conversion result.
* | | |When DMOF (EADC_CTL[9]) is set to 0, 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].
* | | |When DMOF (EADC_CTL[9]) set to 1, 12-bit ADC conversion result with 2'complement format will be filled in RESULT[11:0] and signed bits to will be filled in RESULT[15:12].
* |[16] |OV |Overrun Flag
* | | |If converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register, OV is set to 1.
* | | |0 = Data in RESULT[11:0] is recent conversion result.
* | | |1 = Data in RESULT[11:0] is overwrite.
* | | |Note: It is cleared by hardware after EADC_DAT register is read.
* |[17] |VALID |Valid Flag
* | | |This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read.
* | | |0 = Data in RESULT[11:0] bits is not valid.
* | | |1 = Data in RESULT[11:0] bits is valid.
* @var EADC_T::CURDAT
* Offset: 0x4C ADC PDMA Current Transfer Data Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[17:0] |CURDAT |ADC PDMA Current Transfer Data Register
* | | |This register is a shadow register of EADC_DATn (n=0~18) for PDMA support.
* | | |This is a read only register.
* @var EADC_T::CTL
* Offset: 0x50 ADC Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ADCEN |ADC Converter Enable Bit
* | | |0 = Disabled EADC.
* | | |1 = Enabled EADC.
* | | |Note: Before starting ADC conversion function, this bit should be set to 1
* | | |Clear it to 0 to disable ADC converter analog circuit power consumption.
* |[1] |ADCRST |ADC Converter Control Circuits Reset
* | | |0 = No effect.
* | | |1 = Cause ADC control circuits reset to initial state, but not change the ADC registers value.
* | | |Note: ADCRST bit remains 1 during ADC reset, when ADC reset end, the ADCRST bit is automatically cleared to 0.
* |[2] |ADCIEN0 |Specific Sample Module ADC ADINT0 Interrupt Enable Bit
* | | |The ADC converter generates a conversion end ADIF0 (EADC_STATUS2[0]) upon the end of specific sample module ADC conversion
* | | |If ADCIEN0 bit is set then conversion end interrupt request ADINT0 is generated.
* | | |0 = Specific sample module ADC ADINT0 interrupt function Disabled.
* | | |1 = Specific sample module ADC ADINT0 interrupt function Enabled.
* |[3] |ADCIEN1 |Specific Sample Module ADC ADINT1 Interrupt Enable Bit
* | | |The ADC converter generates a conversion end ADIF1 (EADC_STATUS2[1]) upon the end of specific sample module ADC conversion
* | | |If ADCIEN1 bit is set then conversion end interrupt request ADINT1 is generated.
* | | |0 = Specific sample module ADC ADINT1 interrupt function Disabled.
* | | |1 = Specific sample module ADC ADINT1 interrupt function Enabled.
* |[4] |ADCIEN2 |Specific Sample Module ADC ADINT2 Interrupt Enable Bit
* | | |The ADC converter generates a conversion end ADIF2 (EADC_STATUS2[2]) upon the end of specific sample module ADC conversion
* | | |If ADCIEN2 bit is set then conversion end interrupt request ADINT2 is generated.
* | | |0 = Specific sample module ADC ADINT2 interrupt function Disabled.
* | | |1 = Specific sample module ADC ADINT2 interrupt function Enabled.
* |[5] |ADCIEN3 |Specific Sample Module ADC ADINT3 Interrupt Enable Bit
* | | |The ADC converter generates a conversion end ADIF3 (EADC_STATUS2[3]) upon the end of specific sample module ADC conversion
* | | |If ADCIEN3 bit is set then conversion end interrupt request ADINT3 is generated.
* | | |0 = Specific sample module ADC ADINT3 interrupt function Disabled.
* | | |1 = Specific sample module ADC ADINT3 interrupt function Enabled.
* |[7:6] |RESSEL |Resolution Selection
* | | |00 = 6-bit ADC result will be put at RESULT (EADC_DATn[5:0]).
* | | |01 = 8-bit ADC result will be put at RESULT (EADC_DATn[7:0]).
* | | |10 = 10-bit ADC result will be put at RESULT (EADC_DATn[9:0]).
* | | |11 = 12-bit ADC result will be put at RESULT (EADC_DATn[11:0]).
* |[8] |DIFFEN |Differential Analog Input Mode Enable Bit
* | | |0 = Single-end analog input mode.
* | | |1 = Differential analog input mode.
* |[9] |DMOF |ADC Differential Input Mode Output Format
* | | |0 = ADC conversion result will be filled in RESULT (EADC_DATn[15:0] , n= 0 ~18) with unsigned format.
* | | |1 = ADC conversion result will be filled in RESULT (EADC_DATn[15:0] , n= 0 ~18) with 2'complement format.
* |[11] |PDMAEN |PDMA Transfer Enable Bit
* | | |When ADC conversion is completed, the converted data is loaded into EADC_DATn (n: 0 ~ 18) register, user can enable this bit to generate a PDMA data transfer request.
* | | |0 = PDMA data transfer Disabled.
* | | |1 = PDMA data transfer Enabled.
* | | |Note: When set this bit field to 1, user must set ADCIENn (EADC_CTL[5:2], n=0~3) = 0 to disable interrupt.
* @var EADC_T::SWTRG
* Offset: 0x54 ADC Sample Module Software Start Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[18:0] |SWTRG |ADC Sample Module 0~18 Software Force to Start ADC Conversion
* | | |0 = No effect.
* | | |1 = Cause an ADC conversion when the priority is given to sample module.
* | | |Note: After write this register to start ADC conversion, the EADC_PENDSTS register will show which sample module will conversion
* | | |If user want to disable the conversion of the sample module, user can write EADC_PENDSTS register to clear it.
* @var EADC_T::PENDSTS
* Offset: 0x58 ADC Start of Conversion Pending Flag Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[18:0] |STPF |ADC Sample Module 0~18 Start of Conversion Pending Flag
* | | |Read:
* | | |0 = There is no pending conversion for sample module.
* | | |1 = Sample module ADC start of conversion is pending.
* | | |Write:
* | | |1 = clear pending flag & cancel the conversion for sample module.
* | | |Note: This bit remains 1 during pending state, when the respective ADC conversion is end, the STPFn (n=0~18) bit is automatically cleared to 0
* @var EADC_T::OVSTS
* Offset: 0x5C ADC Sample Module Start of Conversion Overrun Flag Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[18:0] |SPOVF |ADC SAMPLE0~18 Overrun Flag
* | | |0 = No sample module event overrun.
* | | |1 = Indicates a new sample module event is generated while an old one event is pending.
* | | |Note: This bit is cleared by writing 1 to it.
* @var EADC_T::SCTL[19]
* Offset: 0x80 ADC Sample Module 0~18 Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |CHSEL |ADC Sample Module Channel Selection
* | | |00H = EADC_CH0 (slow channel).
* | | |01H = EADC_CH1 (slow channel).
* | | |02H = EADC_CH2 (slow channel).
* | | |03H = EADC_CH3 (slow channel).
* | | |04H = EADC_CH4 (slow channel).
* | | |05H = EADC_CH5 (slow channel).
* | | |06H = EADC_CH6 (slow channel).
* | | |07H = EADC_CH7 (slow channel).
* | | |08H = EADC_CH8 (slow channel).
* | | |09H = EADC_CH9 (slow channel).
* | | |0AH = EADC_CH10 (fast channel).
* | | |0BH = EADC_CH11 (fast channel).
* | | |0CH = EADC_CH12 (fast channel).
* | | |0DH = EADC_CH13 (fast channel).
* | | |0EH = EADC_CH14 (fast channel).
* | | |0FH = EADC_CH15 (fast channel).
* |[4] |EXTREN |ADC External Trigger Rising Edge Enable Bit
* | | |0 = Rising edge Disabled when ADC selects EADC0_ST as trigger source.
* | | |1 = Rising edge Enabled when ADC selects EADC0_ST as trigger source.
* |[5] |EXTFEN |ADC External Trigger Falling Edge Enable Bit
* | | |0 = Falling edge Disabled when ADC selects EADC0_ST as trigger source.
* | | |1 = Falling edge Enabled when ADC selects EADC0_ST as trigger source.
* |[7:6] |TRGDLYDIV |ADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection
* | | |Trigger delay clock frequency:
* | | |00 = ADC_CLK/1.
* | | |01 = ADC_CLK/2.
* | | |10 = ADC_CLK/4.
* | | |11 = ADC_CLK/16.
* |[15:8] |TRGDLYCNT |ADC Sample Module Start of Conversion Trigger Delay Time
* | | |Trigger delay time = TRGDLYCNT x ADC_CLK x n (n=1,2,4,16 from TRGDLYDIV setting).
* |[20:16] |TRGSEL |ADC Sample Module Start of Conversion Trigger Source Selection
* | | |0H = Disable trigger.
* | | |1H = External trigger from EADC0_ST pin input.
* | | |2H = ADC ADINT0 interrupt EOC (End of conversion) pulse trigger.
* | | |3H = ADC ADINT1 interrupt EOC (End of conversion) pulse trigger.
* | | |4H = Timer0 overflow pulse trigger.
* | | |5H = Timer1 overflow pulse trigger.
* | | |6H = Timer2 overflow pulse trigger.
* | | |7H = Timer3 overflow pulse trigger.
* | | |8H = EPWM0TG0.
* | | |9H = EPWM0TG1.
* | | |AH = EPWM0TG2.
* | | |BH = EPWM0TG3.
* | | |CH = EPWM0TG4.
* | | |DH = EPWM0TG5.
* | | |EH = EPWM1TG0.
* | | |FH = EPWM1TG1.
* | | |10H = EPWM1TG2.
* | | |11H = EPWM1TG3.
* | | |12H = EPWM1TG4.
* | | |13H = EPWM1TG5.
* | | |14H = BPWM0TG.
* | | |15H = BPWM1TG.
* | | |other = Reserved.
* |[22] |INTPOS |Interrupt Flag Position Select
* | | |0 = Set ADIFn (EADC_STATUS2[n], n=0~3) at ADC end of conversion.
* | | |1 = Set ADIFn (EADC_STATUS2[n], n=0~3) at ADC start of conversion.
* |[23] |DBMEN |Double Buffer Mode Enable Bit
* | | |0 = Sample has one sample result register. (default).
* | | |1 = Sample has two sample result registers.
* |[31:24] |EXTSMPT |ADC Sampling Time Extend
* | | |When ADC converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, user can extend ADC sampling time after trigger source is coming to get enough sampling time.
* | | |The range of start delay time is from 0~255 ADC clock.
* @var EADC_T::INTSRC[4]
* Offset: 0xD0 ADC interrupt 0~3 Source Enable Control Register.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SPLIE0 |Sample Module 0 Interrupt Enable Bit
* | | |0 = Sample Module 0 interrupt Disabled.
* | | |1 = Sample Module 0 interrupt Enabled.
* |[1] |SPLIE1 |Sample Module 1 Interrupt Enable Bit
* | | |0 = Sample Module 1 interrupt Disabled.
* | | |1 = Sample Module 1 interrupt Enabled.
* |[2] |SPLIE2 |Sample Module 2 Interrupt Enable Bit
* | | |0 = Sample Module 2 interrupt Disabled.
* | | |1 = Sample Module 2 interrupt Enabled.
* |[3] |SPLIE3 |Sample Module 3 Interrupt Enable Bit
* | | |0 = Sample Module 3 interrupt Disabled.
* | | |1 = Sample Module 3 interrupt Enabled.
* |[4] |SPLIE4 |Sample Module 4 Interrupt Enable Bit
* | | |0 = Sample Module 4 interrupt Disabled.
* | | |1 = Sample Module 4 interrupt Enabled.
* |[5] |SPLIE5 |Sample Module 5 Interrupt Enable Bit
* | | |0 = Sample Module 5 interrupt Disabled.
* | | |1 = Sample Module 5 interrupt Enabled.
* |[6] |SPLIE6 |Sample Module 6 Interrupt Enable Bit
* | | |0 = Sample Module 6 interrupt Disabled.
* | | |1 = Sample Module 6 interrupt Enabled.
* |[7] |SPLIE7 |Sample Module 7 Interrupt Enable Bit
* | | |0 = Sample Module 7 interrupt Disabled.
* | | |1 = Sample Module 7 interrupt Enabled.
* |[8] |SPLIE8 |Sample Module 8 Interrupt Enable Bit
* | | |0 = Sample Module 8 interrupt Disabled.
* | | |1 = Sample Module 8 interrupt Enabled.
* |[9] |SPLIE9 |Sample Module 9 Interrupt Enable Bit
* | | |0 = Sample Module 9 interrupt Disabled.
* | | |1 = Sample Module 9 interrupt Enabled.
* |[10] |SPLIE10 |Sample Module 10 Interrupt Enable Bit
* | | |0 = Sample Module 10 interrupt Disabled.
* | | |1 = Sample Module 10 interrupt Enabled.
* |[11] |SPLIE11 |Sample Module 11 Interrupt Enable Bit
* | | |0 = Sample Module 11 interrupt Disabled.
* | | |1 = Sample Module 11 interrupt Enabled.
* |[12] |SPLIE12 |Sample Module 12 Interrupt Enable Bit
* | | |0 = Sample Module 12 interrupt Disabled.
* | | |1 = Sample Module 12 interrupt Enabled.
* |[13] |SPLIE13 |Sample Module 13 Interrupt Enable Bit
* | | |0 = Sample Module 13 interrupt Disabled.
* | | |1 = Sample Module 13 interrupt Enabled.
* |[14] |SPLIE14 |Sample Module 14 Interrupt Enable Bit
* | | |0 = Sample Module 14 interrupt Disabled.
* | | |1 = Sample Module 14 interrupt Enabled.
* |[15] |SPLIE15 |Sample Module 15 Interrupt Enable Bit
* | | |0 = Sample Module 15 interrupt Disabled.
* | | |1 = Sample Module 15 interrupt Enabled.
* |[16] |SPLIE16 |Sample Module 16 Interrupt Enable Bit
* | | |0 = Sample Module 16 interrupt Disabled.
* | | |1 = Sample Module 16 interrupt Enabled.
* |[17] |SPLIE17 |Sample Module 17 Interrupt Enable Bit
* | | |0 = Sample Module 17 interrupt Disabled.
* | | |1 = Sample Module 17 interrupt Enabled.
* |[18] |SPLIE18 |Sample Module 18 Interrupt Enable Bit
* | | |0 = Sample Module 18 interrupt Disabled.
* | | |1 = Sample Module 18 interrupt Enabled.
* @var EADC_T::CMP[4]
* Offset: 0xE0 ADC Result Compare Register 0~3
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ADCMPEN |ADC Result Compare Enable Bit
* | | |0 = Compare Disabled.
* | | |1 = Compare Enabled.
* | | |Set this bit to 1 to enable compare CMPDAT (EADC_CMPn[27:16], n=0~3) with specified sample module conversion result when converted data is loaded into EADC_DAT register.
* |[1] |ADCMPIE |ADC Result Compare Interrupt Enable Bit
* | | |0 = Compare function interrupt Disabled.
* | | |1 = Compare function interrupt Enabled.
* | | |If the compare function is enabled and the compare condition matches the setting of CMPCOND (EADC_CMPn[2], n=0~3) and CMPMCNT (EADC_CMPn[11:8], n=0~3), ADCMPFn (EADC_STATUS2[7:4], n=0~3) will be asserted, in the meanwhile, if ADCMPIE is set to 1, a compare interrupt request is generated.
* |[2] |CMPCOND |Compare Condition
* | | |0= Set the compare condition as that when a 12-bit ADC conversion result is less than the 12-bit CMPDAT (EADC_CMPn [27:16]), the internal match counter will increase one.
* | | |1= Set the compare condition as that when a 12-bit ADC conversion result is greater or equal to the 12-bit CMPDAT (EADC_CMPn [27:16]), the internal match counter will increase one.
* | | |Note: When the internal counter reaches the value to (CMPMCNT (EADC_CMPn[11:8], n=0~3) +1), the CMPF bit will be set.
* |[7:3] |CMPSPL |Compare Sample Module Selection
* | | |00000 = Sample Module 0 conversion result EADC_DAT0 is selected to be compared.
* | | |00001 = Sample Module 1 conversion result EADC_DAT1 is selected to be compared.
* | | |00010 = Sample Module 2 conversion result EADC_DAT2 is selected to be compared.
* | | |00011 = Sample Module 3 conversion result EADC_DAT3 is selected to be compared.
* | | |00100 = Sample Module 4 conversion result EADC_DAT4 is selected to be compared.
* | | |00101 = Sample Module 5 conversion result EADC_DAT5 is selected to be compared.
* | | |00110 = Sample Module 6 conversion result EADC_DAT6 is selected to be compared.
* | | |00111 = Sample Module 7 conversion result EADC_DAT7 is selected to be compared.
* | | |01000 = Sample Module 8 conversion result EADC_DAT8 is selected to be compared.
* | | |01001 = Sample Module 9 conversion result EADC_DAT9 is selected to be compared.
* | | |01010 = Sample Module 10 conversion result EADC_DAT10 is selected to be compared.
* | | |01011 = Sample Module 11 conversion result EADC_DAT11 is selected to be compared.
* | | |01100 = Sample Module 12 conversion result EADC_DAT12 is selected to be compared.
* | | |01101 = Sample Module 13 conversion result EADC_DAT13 is selected to be compared.
* | | |01110 = Sample Module 14 conversion result EADC_DAT14 is selected to be compared.
* | | |01111 = Sample Module 15 conversion result EADC_DAT15 is selected to be compared.
* | | |10000 = Sample Module 16 conversion result EADC_DAT16 is selected to be compared.
* | | |10001 = Sample Module 17 conversion result EADC_DAT17 is selected to be compared.
* | | |10010 = Sample Module 18 conversion result EADC_DAT18 is selected to be compared.
* |[11:8] |CMPMCNT |Compare Match Count
* | | |When the specified ADC sample module analog conversion result matches the compare condition defined by CMPCOND (EADC_CMPn[2], n=0~3), the internal match counter will increase 1
* | | |If the compare result does not meet the compare condition, the internal compare match counter will reset to 0
* | | |When the internal counter reaches the value to (CMPMCNT +1), the ADCMPFn (EADC_STATUS2[7:4], n=0~3) will be set.
* |[15] |CMPWEN |Compare Window Mode Enable Bit
* | | |0 = ADCMPF0 (EADC_STATUS2[4]) will be set when EADC_CMP0 compared condition matched
* | | |ADCMPF2 (EADC_STATUS2[6]) will be set when EADC_CMP2 compared condition matched
* | | |1 = ADCMPF0 (EADC_STATUS2[4]) will be set when both EADC_CMP0 and EADC_CMP1 compared condition matched
* | | |ADCMPF2 (EADC_STATUS2[6]) will be set when both EADC_CMP2 and EADC_CMP3 compared condition matched.
* | | |Note: This bit is only present in EADC_CMP0 and EADC_CMP2 register.
* |[27:16] |CMPDAT |Comparison Data
* | | |The 12 bits data is used to compare with conversion result of specified sample module
* | | |User can use it to monitor the external analog input pin voltage transition without imposing a load on software.
* @var EADC_T::STATUS0
* Offset: 0xF0 ADC Status Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |VALID |EADC_DAT0~15 Data Valid Flag
* | | |It is a mirror of VALID bit in sample module ADC result data register EADC_DATn. (n=0~18).
* |[31:16] |OV |EADC_DAT0~15 Overrun Flag
* | | |It is a mirror to OV bit in sample module ADC result data register EADC_DATn. (n=0~18).
* @var EADC_T::STATUS1
* Offset: 0xF4 ADC Status Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[2:0] |VALID |EADC_DAT16~18 Data Valid Flag
* | | |It is a mirror of VALID bit in sample module ADC result data register EADC_DATn. (n=0~18).
* |[18:16] |OV |EADC_DAT16~18 Overrun Flag
* | | |It is a mirror to OV bit in sample module ADC result data register EADC_DATn. (n=0~18).
* @var EADC_T::STATUS2
* Offset: 0xF8 ADC Status Register 2
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ADIF0 |ADC ADINT0 Interrupt Flag
* | | |0 = No ADINT0 interrupt pulse received.
* | | |1 = ADINT0 interrupt pulse has been received.
* | | |Note1: This bit is cleared by writing 1 to it.
* | | |Note2:This bit indicates whether an ADC conversion of specific sample module has been completed
* |[1] |ADIF1 |ADC ADINT1 Interrupt Flag
* | | |0 = No ADINT1 interrupt pulse received.
* | | |1 = ADINT1 interrupt pulse has been received.
* | | |Note1: This bit is cleared by writing 1 to it.
* | | |Note2:This bit indicates whether an ADC conversion of specific sample module has been completed
* |[2] |ADIF2 |ADC ADINT2 Interrupt Flag
* | | |0 = No ADINT2 interrupt pulse received.
* | | |1 = ADINT2 interrupt pulse has been received.
* | | |Note1: This bit is cleared by writing 1 to it.
* | | |Note2:This bit indicates whether an ADC conversion of specific sample module has been completed
* |[3] |ADIF3 |ADC ADINT3 Interrupt Flag
* | | |0 = No ADINT3 interrupt pulse received.
* | | |1 = ADINT3 interrupt pulse has been received.
* | | |Note1: This bit is cleared by writing 1 to it.
* | | |Note2:This bit indicates whether an ADC conversion of specific sample module has been completed
* |[4] |ADCMPF0 |ADC Compare 0 Flag
* | | |When the specific sample module ADC conversion result meets setting condition in EADC_CMP0 then this bit is set to 1.
* | | |0 = Conversion result in EADC_DAT does not meet EADC_CMP0 register setting.
* | | |1 = Conversion result in EADC_DAT meets EADC_CMP0 register setting.
* | | |Note: This bit is cleared by writing 1 to it.
* |[5] |ADCMPF1 |ADC Compare 1 Flag
* | | |When the specific sample module ADC conversion result meets setting condition in EADC_CMP1 then this bit is set to 1.
* | | |0 = Conversion result in EADC_DAT does not meet EADC_CMP1 register setting.
* | | |1 = Conversion result in EADC_DAT meets EADC_CMP1 register setting.
* | | |Note: This bit is cleared by writing 1 to it.
* |[6] |ADCMPF2 |ADC Compare 2 Flag
* | | |When the specific sample module ADC conversion result meets setting condition in EADC_CMP2 then this bit is set to 1.
* | | |0 = Conversion result in EADC_DAT does not meet EADC_CMP2 register setting.
* | | |1 = Conversion result in EADC_DAT meets EADC_CMP2 register setting.
* | | |Note: This bit is cleared by writing 1 to it.
* |[7] |ADCMPF3 |ADC Compare 3 Flag
* | | |When the specific sample module ADC conversion result meets setting condition in EADC_CMP3 then this bit is set to 1.
* | | |0 = Conversion result in EADC_DAT does not meet EADC_CMP3 register setting.
* | | |1 = Conversion result in EADC_DAT meets EADC_CMP3 register setting.
* | | |Note: This bit is cleared by writing 1 to it.
* |[8] |ADOVIF0 |ADC ADINT0 Interrupt Flag Overrun
* | | |0 = ADINT0 interrupt flag is not overwritten to 1.
* | | |1 = ADINT0 interrupt flag is overwritten to 1.
* | | |Note: This bit is cleared by writing 1 to it.
* |[9] |ADOVIF1 |ADC ADINT1 Interrupt Flag Overrun
* | | |0 = ADINT1 interrupt flag is not overwritten to 1.
* | | |1 = ADINT1 interrupt flag is overwritten to 1.
* | | |Note: This bit is cleared by writing 1 to it.
* |[10] |ADOVIF2 |ADC ADINT2 Interrupt Flag Overrun
* | | |0 = ADINT2 interrupt flag is not overwritten to 1.
* | | |1 = ADINT2 interrupt flag is s overwritten to 1.
* | | |Note: This bit is cleared by writing 1 to it.
* |[11] |ADOVIF3 |ADC ADINT3 Interrupt Flag Overrun
* | | |0 = ADINT3 interrupt flag is not overwritten to 1.
* | | |1 = ADINT3 interrupt flag is overwritten to 1.
* | | |Note: This bit is cleared by writing 1 to it.
* |[12] |ADCMPO0 |ADC Compare 0 Output Status (Read Only)
* | | |The 12 bits compare0 data CMPDAT0 (EADC_CMP0[27:16]) is used to compare with conversion result of specified sample module
* | | |User can use it to monitor the external analog input pin voltage status.
* | | |0 = Conversion result in EADC_DAT less than CMPDAT0 setting.
* | | |1 = Conversion result in EADC_DAT great than or equal CMPDAT0 setting.
* |[13] |ADCMPO1 |ADC Compare 1 Output Status (Read Only)
* | | |The 12 bits compare1 data CMPDAT1 (EADC_CMP1[27:16]) is used to compare with conversion result of specified sample module
* | | |User can use it to monitor the external analog input pin voltage status.
* | | |0 = Conversion result in EADC_DAT less than CMPDAT1 setting.
* | | |1 = Conversion result in EADC_DAT great than or equal CMPDAT1 setting.
* |[14] |ADCMPO2 |ADC Compare 2 Output Status (Read Only)
* | | |The 12 bits compare2 data CMPDAT2 (EADC_CMP2[27:16]) is used to compare with conversion result of specified sample module
* | | |User can use it to monitor the external analog input pin voltage status.
* | | |0 = Conversion result in EADC_DAT less than CMPDAT2 setting.
* | | |1 = Conversion result in EADC_DAT great than or equal CMPDAT2 setting.
* |[15] |ADCMPO3 |ADC Compare 3 Output Status (Read Only)
* | | |The 12 bits compare3 data CMPDAT3 (EADC_CMP3[27:16]) is used to compare with conversion result of specified sample module
* | | |User can use it to monitor the external analog input pin voltage status.
* | | |0 = Conversion result in EADC_DAT less than CMPDAT3 setting.
* | | |1 = Conversion result in EADC_DAT great than or equal CMPDAT3 setting.
* |[20:16] |CHANNEL |Current Conversion Channel (Read Only)
* | | |This filed reflects ADC current conversion channel when BUSY=1.
* | | |It is read only.
* | | |00H = EADC_CH0.
* | | |01H = EADC_CH1.
* | | |02H = EADC_CH2.
* | | |03H = EADC_CH3.
* | | |04H = EADC_CH4.
* | | |05H = EADC_CH5.
* | | |06H = EADC_CH6.
* | | |07H = EADC_CH7.
* | | |08H = EADC_CH8.
* | | |09H = EADC_CH9.
* | | |0AH = EADC_CH10.
* | | |0BH = EADC_CH11.
* | | |0CH = EADC_CH12.
* | | |0DH = EADC_CH13.
* | | |0EH = EADC_CH14.
* | | |0FH = EADC_CH15.
* | | |10H = VBG.
* | | |11H = VTEMP.
* | | |12H = VBAT/4.
* |[23] |BUSY |Busy/Idle (Read Only)
* | | |0 = EADC is in idle state.
* | | |1 = EADC is busy at conversion.
* |[24] |ADOVIF |All ADC Interrupt Flag Overrun Bits Check (Read Only)
* | | |n=0~3.
* | | |0 = None of ADINT interrupt flag ADOVIFn (EADC_STATUS2[11:8]) is overwritten to 1.
* | | |1 = Any one of ADINT interrupt flag ADOVIFn (EADC_STATUS2[11:8]) is overwritten to 1.
* | | |Note: This bit will keep 1 when any ADOVIFn Flag is equal to 1.
* |[25] |STOVF |for All ADC Sample Module Start of Conversion Overrun Flags Check (Read Only)
* | | |n=0~18.
* | | |0 = None of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1.
* | | |1 = Any one of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1.
* | | |Note: This bit will keep 1 when any SPOVFn Flag is equal to 1.
* |[26] |AVALID |for All Sample Module ADC Result Data Register EADC_DAT Data Valid Flag Check (Read Only)
* | | |n=0~18.
* | | |0 = None of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1.
* | | |1 = Any one of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1.
* | | |Note: This bit will keep 1 when any VALIDn Flag is equal to 1.
* |[27] |AOV |for All Sample Module ADC Result Data Register Overrun Flags Check (Read Only)
* | | |n=0~18.
* | | |0 = None of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1.
* | | |1 = Any one of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1.
* | | |Note: This bit will keep 1 when any OVn Flag is equal to 1.
* @var EADC_T::STATUS3
* Offset: 0xFC ADC Status Register 3
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[4:0] |CURSPL |ADC Current Sample Module
* | | |This register show the current ADC is controlled by which sample module control logic modules.
* | | |If the ADC is Idle, this bit filed will set to 0x1F.
* | | |This is a read only register.
* @var EADC_T::DDAT[4]
* Offset: 0x100 ADC Double Data Register 0 for Sample Module 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |RESULT |ADC Conversion Results
* | | |This field contains 12 bits conversion results.
* | | |When the DMOF (EADC_CTL[9]) is set to 0, 12-bit ADC conversion result with unsigned format will be filled in RESULT [11:0] and zero will be filled in RESULT [15:12].
* | | |When DMOF (EADC_CTL[9]) set to 1, 12-bit ADC conversion result with 2'complement format will be filled in RESULT [11:0] and signed bits to will be filled in RESULT [15:12].
* |[16] |OV |Overrun Flag
* | | |0 = Data in RESULT (EADC_DATn[15:0], n=0~3) is recent conversion result.
* | | |1 = Data in RESULT (EADC_DATn[15:0], n=0~3) is overwrite.
* | | |If converted data in RESULT[15:0] has not been read before new conversion result is loaded to this register, OV is set to 1
* | | |It is cleared by hardware after EADC_DDAT register is read.
* |[17] |VALID |Valid Flag
* | | |0 = Double data in RESULT (EADC_DDATn[15:0]) is not valid.
* | | |1 = Double data in RESULT (EADC_DDATn[15:0]) is valid.
* | | |This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DDATn register is read
* | | |(n=0~3).
* @var EADC_T::PWRM
* Offset: 0x110 ADC Power Management Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |PWUPRDY |ADC Power-up Sequence Completed and Ready for Conversion (Read Only)
* | | |0 = ADC is not ready for conversion may be in power down state or in the progress of start up.
* | | |1 = ADC is ready for conversion.
* |[1] |PWUCALEN |Power Up Calibration Function Enable Control
* | | |0 = Disable the function of calibration at power up.
* | | |1 = Enable the function of calibration at power up.
* | | |Note: This bit work together with CALSEL (EADC_CALCTL [3]), see the following
* | | |{PWUCALEN, CALSEL } Description:
* | | |PWUCALEN is 0 and CALSEL is 0: No need to calibrate.
* | | |PWUCALEN is 0 and CALSEL is 1: No need to calibrate.
* | | |PWUCALEN is 1 and CALSEL is 0: Load calibration word when power up.
* | | |PWUCALEN is 1 and CALSEL is 1: Calibrate when power up.
* |[3:2] |PWDMOD |ADC Power-down Mode
* | | |Set this bit fields to select ADC power down mode when system power-down.
* | | |00 = ADC Deep power down mode.
* | | |01 = ADC Power down.
* | | |10 = ADC Standby mode.
* | | |11 = ADC Deep power down mode.
* | | |Note: Different PWDMOD has different power down/up sequence, in order to avoid ADC powering up with wrong sequence; user must keep PWMOD consistent each time in power down and start up
* |[19:8] |LDOSUT |ADC Internal LDO Start-up Time
* | | |Set this bit fields to control LDO start-up time
* | | |The minimum required LDO start-up time is 20us
* | | |LDO start-up time = (1/ADC_CLK) x LDOSUT.
* @var EADC_T::CALCTL
* Offset: 0x114 ADC Calibration Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1] |CALSTART |Calibration Functional Block Start
* | | |0 = Stops calibration functional block.
* | | |1 = Starts calibration functional block.
* | | |Note: This bit is set by SW and clear by HW after re-calibration finish
* |[2] |CALDONE |Calibration Functional Block Complete (Read Only)
* | | |0 = During a calibration.
* | | |1 = Calibration is completed.
* |[3] |CALSEL |Select Calibration Functional Block
* | | |0 = Load calibration word when calibration functional block is active.
* | | |1 = Execute calibration when calibration functional block is active.
* @var EADC_T::CALDWRD
* Offset: 0x118 ADC Calibration Load Word Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[6:0] |CALWORD |Calibration Word Bits
* | | |Write to this register with the previous calibration word before load calibration action.
* | | |Read this register after calibration done.
* | | |Note: The calibration block contains two parts CALIBRATION and LOAD CALIBRATION; if the calibration block configure as CALIBRATION; then this register represent the result of calibration when calibration is completed; if configure as LOAD CALIBRATION ; configure this register before loading calibration action, after loading calibration complete, the laoded calibration word will apply to the ADC; while in loading calibration function the loaded value will not be equal to the original CALWORD until calibration is done.
*/
__I uint32_t DAT[19]; /*!< [0x0000] ADC Data Register 0~18 for Sample Module 0~18 */
__I uint32_t CURDAT; /*!< [0x004c] ADC PDMA Current Transfer Data Register */
__IO uint32_t CTL; /*!< [0x0050] ADC Control Register */
__O uint32_t SWTRG; /*!< [0x0054] ADC Sample Module Software Start Register */
__IO uint32_t PENDSTS; /*!< [0x0058] ADC Start of Conversion Pending Flag Register */
__IO uint32_t OVSTS; /*!< [0x005c] ADC Sample Module Start of Conversion Overrun Flag Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE0[8];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t SCTL[19]; /*!< [0x0080] ADC Sample Module 0~18 Control Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE1[1];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t INTSRC[4]; /*!< [0x00d0] ADC interrupt 0~3 Source Enable Control Register. */
__IO uint32_t CMP[4]; /*!< [0x00e0] ADC Result Compare Register 0~3 */
__I uint32_t STATUS0; /*!< [0x00f0] ADC Status Register 0 */
__I uint32_t STATUS1; /*!< [0x00f4] ADC Status Register 1 */
__IO uint32_t STATUS2; /*!< [0x00f8] ADC Status Register 2 */
__I uint32_t STATUS3; /*!< [0x00fc] ADC Status Register 3 */
__I uint32_t DDAT[4]; /*!< [0x0100] ADC Double Data Register 0~3 for Sample Module 0~3 */
__IO uint32_t PWRM; /*!< [0x0110] ADC Power Management Register */
__IO uint32_t CALCTL; /*!< [0x0114] ADC Calibration Control Register */
__IO uint32_t CALDWRD; /*!< [0x0118] ADC Calibration Load Word Register */
} EADC_T;
/**
@addtogroup EADC_CONST EADC Bit Field Definition
Constant Definitions for EADC Controller
@{ */
#define EADC_DAT_RESULT_Pos (0) /*!< EADC_T::DAT: RESULT Position */
#define EADC_DAT_RESULT_Msk (0xfffful << EADC_DAT_RESULT_Pos) /*!< EADC_T::DAT: RESULT Mask */
#define EADC_DAT_OV_Pos (16) /*!< EADC_T::DAT: OV Position */
#define EADC_DAT_OV_Msk (0x1ul << EADC_DAT_OV_Pos) /*!< EADC_T::DAT: OV Mask */
#define EADC_DAT_VALID_Pos (17) /*!< EADC_T::DAT: VALID Position */
#define EADC_DAT_VALID_Msk (0x1ul << EADC_DAT_VALID_Pos) /*!< EADC_T::DAT: VALID Mask */
#define EADC_DAT0_RESULT_Pos (0) /*!< EADC_T::DAT0: RESULT Position */
#define EADC_DAT0_RESULT_Msk (0xfffful << EADC_DAT0_RESULT_Pos) /*!< EADC_T::DAT0: RESULT Mask */
#define EADC_DAT0_OV_Pos (16) /*!< EADC_T::DAT0: OV Position */
#define EADC_DAT0_OV_Msk (0x1ul << EADC_DAT0_OV_Pos) /*!< EADC_T::DAT0: OV Mask */
#define EADC_DAT0_VALID_Pos (17) /*!< EADC_T::DAT0: VALID Position */
#define EADC_DAT0_VALID_Msk (0x1ul << EADC_DAT0_VALID_Pos) /*!< EADC_T::DAT0: VALID Mask */
#define EADC_DAT1_RESULT_Pos (0) /*!< EADC_T::DAT1: RESULT Position */
#define EADC_DAT1_RESULT_Msk (0xfffful << EADC_DAT1_RESULT_Pos) /*!< EADC_T::DAT1: RESULT Mask */
#define EADC_DAT1_OV_Pos (16) /*!< EADC_T::DAT1: OV Position */
#define EADC_DAT1_OV_Msk (0x1ul << EADC_DAT1_OV_Pos) /*!< EADC_T::DAT1: OV Mask */
#define EADC_DAT1_VALID_Pos (17) /*!< EADC_T::DAT1: VALID Position */
#define EADC_DAT1_VALID_Msk (0x1ul << EADC_DAT1_VALID_Pos) /*!< EADC_T::DAT1: VALID Mask */
#define EADC_DAT2_RESULT_Pos (0) /*!< EADC_T::DAT2: RESULT Position */
#define EADC_DAT2_RESULT_Msk (0xfffful << EADC_DAT2_RESULT_Pos) /*!< EADC_T::DAT2: RESULT Mask */
#define EADC_DAT2_OV_Pos (16) /*!< EADC_T::DAT2: OV Position */
#define EADC_DAT2_OV_Msk (0x1ul << EADC_DAT2_OV_Pos) /*!< EADC_T::DAT2: OV Mask */
#define EADC_DAT2_VALID_Pos (17) /*!< EADC_T::DAT2: VALID Position */
#define EADC_DAT2_VALID_Msk (0x1ul << EADC_DAT2_VALID_Pos) /*!< EADC_T::DAT2: VALID Mask */
#define EADC_DAT3_RESULT_Pos (0) /*!< EADC_T::DAT3: RESULT Position */
#define EADC_DAT3_RESULT_Msk (0xfffful << EADC_DAT3_RESULT_Pos) /*!< EADC_T::DAT3: RESULT Mask */
#define EADC_DAT3_OV_Pos (16) /*!< EADC_T::DAT3: OV Position */
#define EADC_DAT3_OV_Msk (0x1ul << EADC_DAT3_OV_Pos) /*!< EADC_T::DAT3: OV Mask */
#define EADC_DAT3_VALID_Pos (17) /*!< EADC_T::DAT3: VALID Position */
#define EADC_DAT3_VALID_Msk (0x1ul << EADC_DAT3_VALID_Pos) /*!< EADC_T::DAT3: VALID Mask */
#define EADC_DAT4_RESULT_Pos (0) /*!< EADC_T::DAT4: RESULT Position */
#define EADC_DAT4_RESULT_Msk (0xfffful << EADC_DAT4_RESULT_Pos) /*!< EADC_T::DAT4: RESULT Mask */
#define EADC_DAT4_OV_Pos (16) /*!< EADC_T::DAT4: OV Position */
#define EADC_DAT4_OV_Msk (0x1ul << EADC_DAT4_OV_Pos) /*!< EADC_T::DAT4: OV Mask */
#define EADC_DAT4_VALID_Pos (17) /*!< EADC_T::DAT4: VALID Position */
#define EADC_DAT4_VALID_Msk (0x1ul << EADC_DAT4_VALID_Pos) /*!< EADC_T::DAT4: VALID Mask */
#define EADC_DAT5_RESULT_Pos (0) /*!< EADC_T::DAT5: RESULT Position */
#define EADC_DAT5_RESULT_Msk (0xfffful << EADC_DAT5_RESULT_Pos) /*!< EADC_T::DAT5: RESULT Mask */
#define EADC_DAT5_OV_Pos (16) /*!< EADC_T::DAT5: OV Position */
#define EADC_DAT5_OV_Msk (0x1ul << EADC_DAT5_OV_Pos) /*!< EADC_T::DAT5: OV Mask */
#define EADC_DAT5_VALID_Pos (17) /*!< EADC_T::DAT5: VALID Position */
#define EADC_DAT5_VALID_Msk (0x1ul << EADC_DAT5_VALID_Pos) /*!< EADC_T::DAT5: VALID Mask */
#define EADC_DAT6_RESULT_Pos (0) /*!< EADC_T::DAT6: RESULT Position */
#define EADC_DAT6_RESULT_Msk (0xfffful << EADC_DAT6_RESULT_Pos) /*!< EADC_T::DAT6: RESULT Mask */
#define EADC_DAT6_OV_Pos (16) /*!< EADC_T::DAT6: OV Position */
#define EADC_DAT6_OV_Msk (0x1ul << EADC_DAT6_OV_Pos) /*!< EADC_T::DAT6: OV Mask */
#define EADC_DAT6_VALID_Pos (17) /*!< EADC_T::DAT6: VALID Position */
#define EADC_DAT6_VALID_Msk (0x1ul << EADC_DAT6_VALID_Pos) /*!< EADC_T::DAT6: VALID Mask */
#define EADC_DAT7_RESULT_Pos (0) /*!< EADC_T::DAT7: RESULT Position */
#define EADC_DAT7_RESULT_Msk (0xfffful << EADC_DAT7_RESULT_Pos) /*!< EADC_T::DAT7: RESULT Mask */
#define EADC_DAT7_OV_Pos (16) /*!< EADC_T::DAT7: OV Position */
#define EADC_DAT7_OV_Msk (0x1ul << EADC_DAT7_OV_Pos) /*!< EADC_T::DAT7: OV Mask */
#define EADC_DAT7_VALID_Pos (17) /*!< EADC_T::DAT7: VALID Position */
#define EADC_DAT7_VALID_Msk (0x1ul << EADC_DAT7_VALID_Pos) /*!< EADC_T::DAT7: VALID Mask */
#define EADC_DAT8_RESULT_Pos (0) /*!< EADC_T::DAT8: RESULT Position */
#define EADC_DAT8_RESULT_Msk (0xfffful << EADC_DAT8_RESULT_Pos) /*!< EADC_T::DAT8: RESULT Mask */
#define EADC_DAT8_OV_Pos (16) /*!< EADC_T::DAT8: OV Position */
#define EADC_DAT8_OV_Msk (0x1ul << EADC_DAT8_OV_Pos) /*!< EADC_T::DAT8: OV Mask */
#define EADC_DAT8_VALID_Pos (17) /*!< EADC_T::DAT8: VALID Position */
#define EADC_DAT8_VALID_Msk (0x1ul << EADC_DAT8_VALID_Pos) /*!< EADC_T::DAT8: VALID Mask */
#define EADC_DAT9_RESULT_Pos (0) /*!< EADC_T::DAT9: RESULT Position */
#define EADC_DAT9_RESULT_Msk (0xfffful << EADC_DAT9_RESULT_Pos) /*!< EADC_T::DAT9: RESULT Mask */
#define EADC_DAT9_OV_Pos (16) /*!< EADC_T::DAT9: OV Position */
#define EADC_DAT9_OV_Msk (0x1ul << EADC_DAT9_OV_Pos) /*!< EADC_T::DAT9: OV Mask */
#define EADC_DAT9_VALID_Pos (17) /*!< EADC_T::DAT9: VALID Position */
#define EADC_DAT9_VALID_Msk (0x1ul << EADC_DAT9_VALID_Pos) /*!< EADC_T::DAT9: VALID Mask */
#define EADC_DAT10_RESULT_Pos (0) /*!< EADC_T::DAT10: RESULT Position */
#define EADC_DAT10_RESULT_Msk (0xfffful << EADC_DAT10_RESULT_Pos) /*!< EADC_T::DAT10: RESULT Mask */
#define EADC_DAT10_OV_Pos (16) /*!< EADC_T::DAT10: OV Position */
#define EADC_DAT10_OV_Msk (0x1ul << EADC_DAT10_OV_Pos) /*!< EADC_T::DAT10: OV Mask */
#define EADC_DAT10_VALID_Pos (17) /*!< EADC_T::DAT10: VALID Position */
#define EADC_DAT10_VALID_Msk (0x1ul << EADC_DAT10_VALID_Pos) /*!< EADC_T::DAT10: VALID Mask */
#define EADC_DAT11_RESULT_Pos (0) /*!< EADC_T::DAT11: RESULT Position */
#define EADC_DAT11_RESULT_Msk (0xfffful << EADC_DAT11_RESULT_Pos) /*!< EADC_T::DAT11: RESULT Mask */
#define EADC_DAT11_OV_Pos (16) /*!< EADC_T::DAT11: OV Position */
#define EADC_DAT11_OV_Msk (0x1ul << EADC_DAT11_OV_Pos) /*!< EADC_T::DAT11: OV Mask */
#define EADC_DAT11_VALID_Pos (17) /*!< EADC_T::DAT11: VALID Position */
#define EADC_DAT11_VALID_Msk (0x1ul << EADC_DAT11_VALID_Pos) /*!< EADC_T::DAT11: VALID Mask */
#define EADC_DAT12_RESULT_Pos (0) /*!< EADC_T::DAT12: RESULT Position */
#define EADC_DAT12_RESULT_Msk (0xfffful << EADC_DAT12_RESULT_Pos) /*!< EADC_T::DAT12: RESULT Mask */
#define EADC_DAT12_OV_Pos (16) /*!< EADC_T::DAT12: OV Position */
#define EADC_DAT12_OV_Msk (0x1ul << EADC_DAT12_OV_Pos) /*!< EADC_T::DAT12: OV Mask */
#define EADC_DAT12_VALID_Pos (17) /*!< EADC_T::DAT12: VALID Position */
#define EADC_DAT12_VALID_Msk (0x1ul << EADC_DAT12_VALID_Pos) /*!< EADC_T::DAT12: VALID Mask */
#define EADC_DAT13_RESULT_Pos (0) /*!< EADC_T::DAT13: RESULT Position */
#define EADC_DAT13_RESULT_Msk (0xfffful << EADC_DAT13_RESULT_Pos) /*!< EADC_T::DAT13: RESULT Mask */
#define EADC_DAT13_OV_Pos (16) /*!< EADC_T::DAT13: OV Position */
#define EADC_DAT13_OV_Msk (0x1ul << EADC_DAT13_OV_Pos) /*!< EADC_T::DAT13: OV Mask */
#define EADC_DAT13_VALID_Pos (17) /*!< EADC_T::DAT13: VALID Position */
#define EADC_DAT13_VALID_Msk (0x1ul << EADC_DAT13_VALID_Pos) /*!< EADC_T::DAT13: VALID Mask */
#define EADC_DAT14_RESULT_Pos (0) /*!< EADC_T::DAT14: RESULT Position */
#define EADC_DAT14_RESULT_Msk (0xfffful << EADC_DAT14_RESULT_Pos) /*!< EADC_T::DAT14: RESULT Mask */
#define EADC_DAT14_OV_Pos (16) /*!< EADC_T::DAT14: OV Position */
#define EADC_DAT14_OV_Msk (0x1ul << EADC_DAT14_OV_Pos) /*!< EADC_T::DAT14: OV Mask */
#define EADC_DAT14_VALID_Pos (17) /*!< EADC_T::DAT14: VALID Position */
#define EADC_DAT14_VALID_Msk (0x1ul << EADC_DAT14_VALID_Pos) /*!< EADC_T::DAT14: VALID Mask */
#define EADC_DAT15_RESULT_Pos (0) /*!< EADC_T::DAT15: RESULT Position */
#define EADC_DAT15_RESULT_Msk (0xfffful << EADC_DAT15_RESULT_Pos) /*!< EADC_T::DAT15: RESULT Mask */
#define EADC_DAT15_OV_Pos (16) /*!< EADC_T::DAT15: OV Position */
#define EADC_DAT15_OV_Msk (0x1ul << EADC_DAT15_OV_Pos) /*!< EADC_T::DAT15: OV Mask */
#define EADC_DAT15_VALID_Pos (17) /*!< EADC_T::DAT15: VALID Position */
#define EADC_DAT15_VALID_Msk (0x1ul << EADC_DAT15_VALID_Pos) /*!< EADC_T::DAT15: VALID Mask */
#define EADC_DAT16_RESULT_Pos (0) /*!< EADC_T::DAT16: RESULT Position */
#define EADC_DAT16_RESULT_Msk (0xfffful << EADC_DAT16_RESULT_Pos) /*!< EADC_T::DAT16: RESULT Mask */
#define EADC_DAT16_OV_Pos (16) /*!< EADC_T::DAT16: OV Position */
#define EADC_DAT16_OV_Msk (0x1ul << EADC_DAT16_OV_Pos) /*!< EADC_T::DAT16: OV Mask */
#define EADC_DAT16_VALID_Pos (17) /*!< EADC_T::DAT16: VALID Position */
#define EADC_DAT16_VALID_Msk (0x1ul << EADC_DAT16_VALID_Pos) /*!< EADC_T::DAT16: VALID Mask */
#define EADC_DAT17_RESULT_Pos (0) /*!< EADC_T::DAT17: RESULT Position */
#define EADC_DAT17_RESULT_Msk (0xfffful << EADC_DAT17_RESULT_Pos) /*!< EADC_T::DAT17: RESULT Mask */
#define EADC_DAT17_OV_Pos (16) /*!< EADC_T::DAT17: OV Position */
#define EADC_DAT17_OV_Msk (0x1ul << EADC_DAT17_OV_Pos) /*!< EADC_T::DAT17: OV Mask */
#define EADC_DAT17_VALID_Pos (17) /*!< EADC_T::DAT17: VALID Position */
#define EADC_DAT17_VALID_Msk (0x1ul << EADC_DAT17_VALID_Pos) /*!< EADC_T::DAT17: VALID Mask */
#define EADC_DAT18_RESULT_Pos (0) /*!< EADC_T::DAT18: RESULT Position */
#define EADC_DAT18_RESULT_Msk (0xfffful << EADC_DAT18_RESULT_Pos) /*!< EADC_T::DAT18: RESULT Mask */
#define EADC_DAT18_OV_Pos (16) /*!< EADC_T::DAT18: OV Position */
#define EADC_DAT18_OV_Msk (0x1ul << EADC_DAT18_OV_Pos) /*!< EADC_T::DAT18: OV Mask */
#define EADC_DAT18_VALID_Pos (17) /*!< EADC_T::DAT18: VALID Position */
#define EADC_DAT18_VALID_Msk (0x1ul << EADC_DAT18_VALID_Pos) /*!< EADC_T::DAT18: VALID Mask */
#define EADC_CURDAT_CURDAT_Pos (0) /*!< EADC_T::CURDAT: CURDAT Position */
#define EADC_CURDAT_CURDAT_Msk (0x3fffful << EADC_CURDAT_CURDAT_Pos) /*!< EADC_T::CURDAT: CURDAT Mask */
#define EADC_CTL_ADCEN_Pos (0) /*!< EADC_T::CTL: ADCEN Position */
#define EADC_CTL_ADCEN_Msk (0x1ul << EADC_CTL_ADCEN_Pos) /*!< EADC_T::CTL: ADCEN Mask */
#define EADC_CTL_ADCRST_Pos (1) /*!< EADC_T::CTL: ADCRST Position */
#define EADC_CTL_ADCRST_Msk (0x1ul << EADC_CTL_ADCRST_Pos) /*!< EADC_T::CTL: ADCRST Mask */
#define EADC_CTL_ADCIEN0_Pos (2) /*!< EADC_T::CTL: ADCIEN0 Position */
#define EADC_CTL_ADCIEN0_Msk (0x1ul << EADC_CTL_ADCIEN0_Pos) /*!< EADC_T::CTL: ADCIEN0 Mask */
#define EADC_CTL_ADCIEN1_Pos (3) /*!< EADC_T::CTL: ADCIEN1 Position */
#define EADC_CTL_ADCIEN1_Msk (0x1ul << EADC_CTL_ADCIEN1_Pos) /*!< EADC_T::CTL: ADCIEN1 Mask */
#define EADC_CTL_ADCIEN2_Pos (4) /*!< EADC_T::CTL: ADCIEN2 Position */
#define EADC_CTL_ADCIEN2_Msk (0x1ul << EADC_CTL_ADCIEN2_Pos) /*!< EADC_T::CTL: ADCIEN2 Mask */
#define EADC_CTL_ADCIEN3_Pos (5) /*!< EADC_T::CTL: ADCIEN3 Position */
#define EADC_CTL_ADCIEN3_Msk (0x1ul << EADC_CTL_ADCIEN3_Pos) /*!< EADC_T::CTL: ADCIEN3 Mask */
#define EADC_CTL_RESSEL_Pos (6) /*!< EADC_T::CTL: RESSEL Position */
#define EADC_CTL_RESSEL_Msk (0x3ul << EADC_CTL_RESSEL_Pos) /*!< EADC_T::CTL: RESSEL Mask */
#define EADC_CTL_DIFFEN_Pos (8) /*!< EADC_T::CTL: DIFFEN Position */
#define EADC_CTL_DIFFEN_Msk (0x1ul << EADC_CTL_DIFFEN_Pos) /*!< EADC_T::CTL: DIFFEN Mask */
#define EADC_CTL_DMOF_Pos (9) /*!< EADC_T::CTL: DMOF Position */
#define EADC_CTL_DMOF_Msk (0x1ul << EADC_CTL_DMOF_Pos) /*!< EADC_T::CTL: DMOF Mask */
#define EADC_CTL_PDMAEN_Pos (11) /*!< EADC_T::CTL: PDMAEN Position */
#define EADC_CTL_PDMAEN_Msk (0x1ul << EADC_CTL_PDMAEN_Pos) /*!< EADC_T::CTL: PDMAEN Mask */
#define EADC_SWTRG_SWTRG_Pos (0) /*!< EADC_T::SWTRG: SWTRG Position */
#define EADC_SWTRG_SWTRG_Msk (0x7fffful << EADC_SWTRG_SWTRG_Pos) /*!< EADC_T::SWTRG: SWTRG Mask */
#define EADC_PENDSTS_STPF_Pos (0) /*!< EADC_T::PENDSTS: STPF Position */
#define EADC_PENDSTS_STPF_Msk (0x7fffful << EADC_PENDSTS_STPF_Pos) /*!< EADC_T::PENDSTS: STPF Mask */
#define EADC_OVSTS_SPOVF_Pos (0) /*!< EADC_T::OVSTS: SPOVF Position */
#define EADC_OVSTS_SPOVF_Msk (0x7fffful << EADC_OVSTS_SPOVF_Pos) /*!< EADC_T::OVSTS: SPOVF Mask */
#define EADC_SCTL_CHSEL_Pos (0) /*!< EADC_T::SCTL: CHSEL Position */
#define EADC_SCTL_CHSEL_Msk (0xful << EADC_SCTL_CHSEL_Pos) /*!< EADC_T::SCTL: CHSEL Mask */
#define EADC_SCTL_EXTREN_Pos (4) /*!< EADC_T::SCTL: EXTREN Position */
#define EADC_SCTL_EXTREN_Msk (0x1ul << EADC_SCTL_EXTREN_Pos) /*!< EADC_T::SCTL: EXTREN Mask */
#define EADC_SCTL_EXTFEN_Pos (5) /*!< EADC_T::SCTL: EXTFEN Position */
#define EADC_SCTL_EXTFEN_Msk (0x1ul << EADC_SCTL_EXTFEN_Pos) /*!< EADC_T::SCTL: EXTFEN Mask */
#define EADC_SCTL_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL: TRGDLYDIV Position */
#define EADC_SCTL_TRGDLYDIV_Msk (0x3ul << EADC_SCTL_TRGDLYDIV_Pos) /*!< EADC_T::SCTL: TRGDLYDIV Mask */
#define EADC_SCTL_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL: TRGDLYCNT Position */
#define EADC_SCTL_TRGDLYCNT_Msk (0xfful << EADC_SCTL_TRGDLYCNT_Pos) /*!< EADC_T::SCTL: TRGDLYCNT Mask */
#define EADC_SCTL_TRGSEL_Pos (16) /*!< EADC_T::SCTL: TRGSEL Position */
#define EADC_SCTL_TRGSEL_Msk (0x1ful << EADC_SCTL_TRGSEL_Pos) /*!< EADC_T::SCTL: TRGSEL Mask */
#define EADC_SCTL_INTPOS_Pos (22) /*!< EADC_T::SCTL: INTPOS Position */
#define EADC_SCTL_INTPOS_Msk (0x1ul << EADC_SCTL_INTPOS_Pos) /*!< EADC_T::SCTL: INTPOS Mask */
#define EADC_SCTL_DBMEN_Pos (23) /*!< EADC_T::SCTL: DBMEN Position */
#define EADC_SCTL_DBMEN_Msk (0x1ul << EADC_SCTL_DBMEN_Pos) /*!< EADC_T::SCTL: DBMEN Mask */
#define EADC_SCTL_EXTSMPT_Pos (24) /*!< EADC_T::SCTL: EXTSMPT Position */
#define EADC_SCTL_EXTSMPT_Msk (0xfful << EADC_SCTL_EXTSMPT_Pos) /*!< EADC_T::SCTL: EXTSMPT Mask */
#define EADC_SCTL0_CHSEL_Pos (0) /*!< EADC_T::SCTL0: CHSEL Position */
#define EADC_SCTL0_CHSEL_Msk (0xful << EADC_SCTL0_CHSEL_Pos) /*!< EADC_T::SCTL0: CHSEL Mask */
#define EADC_SCTL0_EXTREN_Pos (4) /*!< EADC_T::SCTL0: EXTREN Position */
#define EADC_SCTL0_EXTREN_Msk (0x1ul << EADC_SCTL0_EXTREN_Pos) /*!< EADC_T::SCTL0: EXTREN Mask */
#define EADC_SCTL0_EXTFEN_Pos (5) /*!< EADC_T::SCTL0: EXTFEN Position */
#define EADC_SCTL0_EXTFEN_Msk (0x1ul << EADC_SCTL0_EXTFEN_Pos) /*!< EADC_T::SCTL0: EXTFEN Mask */
#define EADC_SCTL0_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL0: TRGDLYDIV Position */
#define EADC_SCTL0_TRGDLYDIV_Msk (0x3ul << EADC_SCTL0_TRGDLYDIV_Pos) /*!< EADC_T::SCTL0: TRGDLYDIV Mask */
#define EADC_SCTL0_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL0: TRGDLYCNT Position */
#define EADC_SCTL0_TRGDLYCNT_Msk (0xfful << EADC_SCTL0_TRGDLYCNT_Pos) /*!< EADC_T::SCTL0: TRGDLYCNT Mask */
#define EADC_SCTL0_TRGSEL_Pos (16) /*!< EADC_T::SCTL0: TRGSEL Position */
#define EADC_SCTL0_TRGSEL_Msk (0x1ful << EADC_SCTL0_TRGSEL_Pos) /*!< EADC_T::SCTL0: TRGSEL Mask */
#define EADC_SCTL0_INTPOS_Pos (22) /*!< EADC_T::SCTL0: INTPOS Position */
#define EADC_SCTL0_INTPOS_Msk (0x1ul << EADC_SCTL0_INTPOS_Pos) /*!< EADC_T::SCTL0: INTPOS Mask */
#define EADC_SCTL0_DBMEN_Pos (23) /*!< EADC_T::SCTL0: DBMEN Position */
#define EADC_SCTL0_DBMEN_Msk (0x1ul << EADC_SCTL0_DBMEN_Pos) /*!< EADC_T::SCTL0: DBMEN Mask */
#define EADC_SCTL0_EXTSMPT_Pos (24) /*!< EADC_T::SCTL0: EXTSMPT Position */
#define EADC_SCTL0_EXTSMPT_Msk (0xfful << EADC_SCTL0_EXTSMPT_Pos) /*!< EADC_T::SCTL0: EXTSMPT Mask */
#define EADC_SCTL1_CHSEL_Pos (0) /*!< EADC_T::SCTL1: CHSEL Position */
#define EADC_SCTL1_CHSEL_Msk (0xful << EADC_SCTL1_CHSEL_Pos) /*!< EADC_T::SCTL1: CHSEL Mask */
#define EADC_SCTL1_EXTREN_Pos (4) /*!< EADC_T::SCTL1: EXTREN Position */
#define EADC_SCTL1_EXTREN_Msk (0x1ul << EADC_SCTL1_EXTREN_Pos) /*!< EADC_T::SCTL1: EXTREN Mask */
#define EADC_SCTL1_EXTFEN_Pos (5) /*!< EADC_T::SCTL1: EXTFEN Position */
#define EADC_SCTL1_EXTFEN_Msk (0x1ul << EADC_SCTL1_EXTFEN_Pos) /*!< EADC_T::SCTL1: EXTFEN Mask */
#define EADC_SCTL1_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL1: TRGDLYDIV Position */
#define EADC_SCTL1_TRGDLYDIV_Msk (0x3ul << EADC_SCTL1_TRGDLYDIV_Pos) /*!< EADC_T::SCTL1: TRGDLYDIV Mask */
#define EADC_SCTL1_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL1: TRGDLYCNT Position */
#define EADC_SCTL1_TRGDLYCNT_Msk (0xfful << EADC_SCTL1_TRGDLYCNT_Pos) /*!< EADC_T::SCTL1: TRGDLYCNT Mask */
#define EADC_SCTL1_TRGSEL_Pos (16) /*!< EADC_T::SCTL1: TRGSEL Position */
#define EADC_SCTL1_TRGSEL_Msk (0x1ful << EADC_SCTL1_TRGSEL_Pos) /*!< EADC_T::SCTL1: TRGSEL Mask */
#define EADC_SCTL1_INTPOS_Pos (22) /*!< EADC_T::SCTL1: INTPOS Position */
#define EADC_SCTL1_INTPOS_Msk (0x1ul << EADC_SCTL1_INTPOS_Pos) /*!< EADC_T::SCTL1: INTPOS Mask */
#define EADC_SCTL1_DBMEN_Pos (23) /*!< EADC_T::SCTL1: DBMEN Position */
#define EADC_SCTL1_DBMEN_Msk (0x1ul << EADC_SCTL1_DBMEN_Pos) /*!< EADC_T::SCTL1: DBMEN Mask */
#define EADC_SCTL1_EXTSMPT_Pos (24) /*!< EADC_T::SCTL1: EXTSMPT Position */
#define EADC_SCTL1_EXTSMPT_Msk (0xfful << EADC_SCTL1_EXTSMPT_Pos) /*!< EADC_T::SCTL1: EXTSMPT Mask */
#define EADC_SCTL2_CHSEL_Pos (0) /*!< EADC_T::SCTL2: CHSEL Position */
#define EADC_SCTL2_CHSEL_Msk (0xful << EADC_SCTL2_CHSEL_Pos) /*!< EADC_T::SCTL2: CHSEL Mask */
#define EADC_SCTL2_EXTREN_Pos (4) /*!< EADC_T::SCTL2: EXTREN Position */
#define EADC_SCTL2_EXTREN_Msk (0x1ul << EADC_SCTL2_EXTREN_Pos) /*!< EADC_T::SCTL2: EXTREN Mask */
#define EADC_SCTL2_EXTFEN_Pos (5) /*!< EADC_T::SCTL2: EXTFEN Position */
#define EADC_SCTL2_EXTFEN_Msk (0x1ul << EADC_SCTL2_EXTFEN_Pos) /*!< EADC_T::SCTL2: EXTFEN Mask */
#define EADC_SCTL2_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL2: TRGDLYDIV Position */
#define EADC_SCTL2_TRGDLYDIV_Msk (0x3ul << EADC_SCTL2_TRGDLYDIV_Pos) /*!< EADC_T::SCTL2: TRGDLYDIV Mask */
#define EADC_SCTL2_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL2: TRGDLYCNT Position */
#define EADC_SCTL2_TRGDLYCNT_Msk (0xfful << EADC_SCTL2_TRGDLYCNT_Pos) /*!< EADC_T::SCTL2: TRGDLYCNT Mask */
#define EADC_SCTL2_TRGSEL_Pos (16) /*!< EADC_T::SCTL2: TRGSEL Position */
#define EADC_SCTL2_TRGSEL_Msk (0x1ful << EADC_SCTL2_TRGSEL_Pos) /*!< EADC_T::SCTL2: TRGSEL Mask */
#define EADC_SCTL2_INTPOS_Pos (22) /*!< EADC_T::SCTL2: INTPOS Position */
#define EADC_SCTL2_INTPOS_Msk (0x1ul << EADC_SCTL2_INTPOS_Pos) /*!< EADC_T::SCTL2: INTPOS Mask */
#define EADC_SCTL2_DBMEN_Pos (23) /*!< EADC_T::SCTL2: DBMEN Position */
#define EADC_SCTL2_DBMEN_Msk (0x1ul << EADC_SCTL2_DBMEN_Pos) /*!< EADC_T::SCTL2: DBMEN Mask */
#define EADC_SCTL2_EXTSMPT_Pos (24) /*!< EADC_T::SCTL2: EXTSMPT Position */
#define EADC_SCTL2_EXTSMPT_Msk (0xfful << EADC_SCTL2_EXTSMPT_Pos) /*!< EADC_T::SCTL2: EXTSMPT Mask */
#define EADC_SCTL3_CHSEL_Pos (0) /*!< EADC_T::SCTL3: CHSEL Position */
#define EADC_SCTL3_CHSEL_Msk (0xful << EADC_SCTL3_CHSEL_Pos) /*!< EADC_T::SCTL3: CHSEL Mask */
#define EADC_SCTL3_EXTREN_Pos (4) /*!< EADC_T::SCTL3: EXTREN Position */
#define EADC_SCTL3_EXTREN_Msk (0x1ul << EADC_SCTL3_EXTREN_Pos) /*!< EADC_T::SCTL3: EXTREN Mask */
#define EADC_SCTL3_EXTFEN_Pos (5) /*!< EADC_T::SCTL3: EXTFEN Position */
#define EADC_SCTL3_EXTFEN_Msk (0x1ul << EADC_SCTL3_EXTFEN_Pos) /*!< EADC_T::SCTL3: EXTFEN Mask */
#define EADC_SCTL3_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL3: TRGDLYDIV Position */
#define EADC_SCTL3_TRGDLYDIV_Msk (0x3ul << EADC_SCTL3_TRGDLYDIV_Pos) /*!< EADC_T::SCTL3: TRGDLYDIV Mask */
#define EADC_SCTL3_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL3: TRGDLYCNT Position */
#define EADC_SCTL3_TRGDLYCNT_Msk (0xfful << EADC_SCTL3_TRGDLYCNT_Pos) /*!< EADC_T::SCTL3: TRGDLYCNT Mask */
#define EADC_SCTL3_TRGSEL_Pos (16) /*!< EADC_T::SCTL3: TRGSEL Position */
#define EADC_SCTL3_TRGSEL_Msk (0x1ful << EADC_SCTL3_TRGSEL_Pos) /*!< EADC_T::SCTL3: TRGSEL Mask */
#define EADC_SCTL3_INTPOS_Pos (22) /*!< EADC_T::SCTL3: INTPOS Position */
#define EADC_SCTL3_INTPOS_Msk (0x1ul << EADC_SCTL3_INTPOS_Pos) /*!< EADC_T::SCTL3: INTPOS Mask */
#define EADC_SCTL3_DBMEN_Pos (23) /*!< EADC_T::SCTL3: DBMEN Position */
#define EADC_SCTL3_DBMEN_Msk (0x1ul << EADC_SCTL3_DBMEN_Pos) /*!< EADC_T::SCTL3: DBMEN Mask */
#define EADC_SCTL3_EXTSMPT_Pos (24) /*!< EADC_T::SCTL3: EXTSMPT Position */
#define EADC_SCTL3_EXTSMPT_Msk (0xfful << EADC_SCTL3_EXTSMPT_Pos) /*!< EADC_T::SCTL3: EXTSMPT Mask */
#define EADC_SCTL4_CHSEL_Pos (0) /*!< EADC_T::SCTL4: CHSEL Position */
#define EADC_SCTL4_CHSEL_Msk (0xful << EADC_SCTL4_CHSEL_Pos) /*!< EADC_T::SCTL4: CHSEL Mask */
#define EADC_SCTL4_EXTREN_Pos (4) /*!< EADC_T::SCTL4: EXTREN Position */
#define EADC_SCTL4_EXTREN_Msk (0x1ul << EADC_SCTL4_EXTREN_Pos) /*!< EADC_T::SCTL4: EXTREN Mask */
#define EADC_SCTL4_EXTFEN_Pos (5) /*!< EADC_T::SCTL4: EXTFEN Position */
#define EADC_SCTL4_EXTFEN_Msk (0x1ul << EADC_SCTL4_EXTFEN_Pos) /*!< EADC_T::SCTL4: EXTFEN Mask */
#define EADC_SCTL4_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL4: TRGDLYDIV Position */
#define EADC_SCTL4_TRGDLYDIV_Msk (0x3ul << EADC_SCTL4_TRGDLYDIV_Pos) /*!< EADC_T::SCTL4: TRGDLYDIV Mask */
#define EADC_SCTL4_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL4: TRGDLYCNT Position */
#define EADC_SCTL4_TRGDLYCNT_Msk (0xfful << EADC_SCTL4_TRGDLYCNT_Pos) /*!< EADC_T::SCTL4: TRGDLYCNT Mask */
#define EADC_SCTL4_TRGSEL_Pos (16) /*!< EADC_T::SCTL4: TRGSEL Position */
#define EADC_SCTL4_TRGSEL_Msk (0x1ful << EADC_SCTL4_TRGSEL_Pos) /*!< EADC_T::SCTL4: TRGSEL Mask */
#define EADC_SCTL4_INTPOS_Pos (22) /*!< EADC_T::SCTL4: INTPOS Position */
#define EADC_SCTL4_INTPOS_Msk (0x1ul << EADC_SCTL4_INTPOS_Pos) /*!< EADC_T::SCTL4: INTPOS Mask */
#define EADC_SCTL4_EXTSMPT_Pos (24) /*!< EADC_T::SCTL4: EXTSMPT Position */
#define EADC_SCTL4_EXTSMPT_Msk (0xfful << EADC_SCTL4_EXTSMPT_Pos) /*!< EADC_T::SCTL4: EXTSMPT Mask */
#define EADC_SCTL5_CHSEL_Pos (0) /*!< EADC_T::SCTL5: CHSEL Position */
#define EADC_SCTL5_CHSEL_Msk (0xful << EADC_SCTL5_CHSEL_Pos) /*!< EADC_T::SCTL5: CHSEL Mask */
#define EADC_SCTL5_EXTREN_Pos (4) /*!< EADC_T::SCTL5: EXTREN Position */
#define EADC_SCTL5_EXTREN_Msk (0x1ul << EADC_SCTL5_EXTREN_Pos) /*!< EADC_T::SCTL5: EXTREN Mask */
#define EADC_SCTL5_EXTFEN_Pos (5) /*!< EADC_T::SCTL5: EXTFEN Position */
#define EADC_SCTL5_EXTFEN_Msk (0x1ul << EADC_SCTL5_EXTFEN_Pos) /*!< EADC_T::SCTL5: EXTFEN Mask */
#define EADC_SCTL5_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL5: TRGDLYDIV Position */
#define EADC_SCTL5_TRGDLYDIV_Msk (0x3ul << EADC_SCTL5_TRGDLYDIV_Pos) /*!< EADC_T::SCTL5: TRGDLYDIV Mask */
#define EADC_SCTL5_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL5: TRGDLYCNT Position */
#define EADC_SCTL5_TRGDLYCNT_Msk (0xfful << EADC_SCTL5_TRGDLYCNT_Pos) /*!< EADC_T::SCTL5: TRGDLYCNT Mask */
#define EADC_SCTL5_TRGSEL_Pos (16) /*!< EADC_T::SCTL5: TRGSEL Position */
#define EADC_SCTL5_TRGSEL_Msk (0x1ful << EADC_SCTL5_TRGSEL_Pos) /*!< EADC_T::SCTL5: TRGSEL Mask */
#define EADC_SCTL5_INTPOS_Pos (22) /*!< EADC_T::SCTL5: INTPOS Position */
#define EADC_SCTL5_INTPOS_Msk (0x1ul << EADC_SCTL5_INTPOS_Pos) /*!< EADC_T::SCTL5: INTPOS Mask */
#define EADC_SCTL5_EXTSMPT_Pos (24) /*!< EADC_T::SCTL5: EXTSMPT Position */
#define EADC_SCTL5_EXTSMPT_Msk (0xfful << EADC_SCTL5_EXTSMPT_Pos) /*!< EADC_T::SCTL5: EXTSMPT Mask */
#define EADC_SCTL6_CHSEL_Pos (0) /*!< EADC_T::SCTL6: CHSEL Position */
#define EADC_SCTL6_CHSEL_Msk (0xful << EADC_SCTL6_CHSEL_Pos) /*!< EADC_T::SCTL6: CHSEL Mask */
#define EADC_SCTL6_EXTREN_Pos (4) /*!< EADC_T::SCTL6: EXTREN Position */
#define EADC_SCTL6_EXTREN_Msk (0x1ul << EADC_SCTL6_EXTREN_Pos) /*!< EADC_T::SCTL6: EXTREN Mask */
#define EADC_SCTL6_EXTFEN_Pos (5) /*!< EADC_T::SCTL6: EXTFEN Position */
#define EADC_SCTL6_EXTFEN_Msk (0x1ul << EADC_SCTL6_EXTFEN_Pos) /*!< EADC_T::SCTL6: EXTFEN Mask */
#define EADC_SCTL6_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL6: TRGDLYDIV Position */
#define EADC_SCTL6_TRGDLYDIV_Msk (0x3ul << EADC_SCTL6_TRGDLYDIV_Pos) /*!< EADC_T::SCTL6: TRGDLYDIV Mask */
#define EADC_SCTL6_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL6: TRGDLYCNT Position */
#define EADC_SCTL6_TRGDLYCNT_Msk (0xfful << EADC_SCTL6_TRGDLYCNT_Pos) /*!< EADC_T::SCTL6: TRGDLYCNT Mask */
#define EADC_SCTL6_TRGSEL_Pos (16) /*!< EADC_T::SCTL6: TRGSEL Position */
#define EADC_SCTL6_TRGSEL_Msk (0x1ful << EADC_SCTL6_TRGSEL_Pos) /*!< EADC_T::SCTL6: TRGSEL Mask */
#define EADC_SCTL6_INTPOS_Pos (22) /*!< EADC_T::SCTL6: INTPOS Position */
#define EADC_SCTL6_INTPOS_Msk (0x1ul << EADC_SCTL6_INTPOS_Pos) /*!< EADC_T::SCTL6: INTPOS Mask */
#define EADC_SCTL6_EXTSMPT_Pos (24) /*!< EADC_T::SCTL6: EXTSMPT Position */
#define EADC_SCTL6_EXTSMPT_Msk (0xfful << EADC_SCTL6_EXTSMPT_Pos) /*!< EADC_T::SCTL6: EXTSMPT Mask */
#define EADC_SCTL7_CHSEL_Pos (0) /*!< EADC_T::SCTL7: CHSEL Position */
#define EADC_SCTL7_CHSEL_Msk (0xful << EADC_SCTL7_CHSEL_Pos) /*!< EADC_T::SCTL7: CHSEL Mask */
#define EADC_SCTL7_EXTREN_Pos (4) /*!< EADC_T::SCTL7: EXTREN Position */
#define EADC_SCTL7_EXTREN_Msk (0x1ul << EADC_SCTL7_EXTREN_Pos) /*!< EADC_T::SCTL7: EXTREN Mask */
#define EADC_SCTL7_EXTFEN_Pos (5) /*!< EADC_T::SCTL7: EXTFEN Position */
#define EADC_SCTL7_EXTFEN_Msk (0x1ul << EADC_SCTL7_EXTFEN_Pos) /*!< EADC_T::SCTL7: EXTFEN Mask */
#define EADC_SCTL7_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL7: TRGDLYDIV Position */
#define EADC_SCTL7_TRGDLYDIV_Msk (0x3ul << EADC_SCTL7_TRGDLYDIV_Pos) /*!< EADC_T::SCTL7: TRGDLYDIV Mask */
#define EADC_SCTL7_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL7: TRGDLYCNT Position */
#define EADC_SCTL7_TRGDLYCNT_Msk (0xfful << EADC_SCTL7_TRGDLYCNT_Pos) /*!< EADC_T::SCTL7: TRGDLYCNT Mask */
#define EADC_SCTL7_TRGSEL_Pos (16) /*!< EADC_T::SCTL7: TRGSEL Position */
#define EADC_SCTL7_TRGSEL_Msk (0x1ful << EADC_SCTL7_TRGSEL_Pos) /*!< EADC_T::SCTL7: TRGSEL Mask */
#define EADC_SCTL7_INTPOS_Pos (22) /*!< EADC_T::SCTL7: INTPOS Position */
#define EADC_SCTL7_INTPOS_Msk (0x1ul << EADC_SCTL7_INTPOS_Pos) /*!< EADC_T::SCTL7: INTPOS Mask */
#define EADC_SCTL7_EXTSMPT_Pos (24) /*!< EADC_T::SCTL7: EXTSMPT Position */
#define EADC_SCTL7_EXTSMPT_Msk (0xfful << EADC_SCTL7_EXTSMPT_Pos) /*!< EADC_T::SCTL7: EXTSMPT Mask */
#define EADC_SCTL8_CHSEL_Pos (0) /*!< EADC_T::SCTL8: CHSEL Position */
#define EADC_SCTL8_CHSEL_Msk (0xful << EADC_SCTL8_CHSEL_Pos) /*!< EADC_T::SCTL8: CHSEL Mask */
#define EADC_SCTL8_EXTREN_Pos (4) /*!< EADC_T::SCTL8: EXTREN Position */
#define EADC_SCTL8_EXTREN_Msk (0x1ul << EADC_SCTL8_EXTREN_Pos) /*!< EADC_T::SCTL8: EXTREN Mask */
#define EADC_SCTL8_EXTFEN_Pos (5) /*!< EADC_T::SCTL8: EXTFEN Position */
#define EADC_SCTL8_EXTFEN_Msk (0x1ul << EADC_SCTL8_EXTFEN_Pos) /*!< EADC_T::SCTL8: EXTFEN Mask */
#define EADC_SCTL8_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL8: TRGDLYDIV Position */
#define EADC_SCTL8_TRGDLYDIV_Msk (0x3ul << EADC_SCTL8_TRGDLYDIV_Pos) /*!< EADC_T::SCTL8: TRGDLYDIV Mask */
#define EADC_SCTL8_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL8: TRGDLYCNT Position */
#define EADC_SCTL8_TRGDLYCNT_Msk (0xfful << EADC_SCTL8_TRGDLYCNT_Pos) /*!< EADC_T::SCTL8: TRGDLYCNT Mask */
#define EADC_SCTL8_TRGSEL_Pos (16) /*!< EADC_T::SCTL8: TRGSEL Position */
#define EADC_SCTL8_TRGSEL_Msk (0x1ful << EADC_SCTL8_TRGSEL_Pos) /*!< EADC_T::SCTL8: TRGSEL Mask */
#define EADC_SCTL8_INTPOS_Pos (22) /*!< EADC_T::SCTL8: INTPOS Position */
#define EADC_SCTL8_INTPOS_Msk (0x1ul << EADC_SCTL8_INTPOS_Pos) /*!< EADC_T::SCTL8: INTPOS Mask */
#define EADC_SCTL8_EXTSMPT_Pos (24) /*!< EADC_T::SCTL8: EXTSMPT Position */
#define EADC_SCTL8_EXTSMPT_Msk (0xfful << EADC_SCTL8_EXTSMPT_Pos) /*!< EADC_T::SCTL8: EXTSMPT Mask */
#define EADC_SCTL9_CHSEL_Pos (0) /*!< EADC_T::SCTL9: CHSEL Position */
#define EADC_SCTL9_CHSEL_Msk (0xful << EADC_SCTL9_CHSEL_Pos) /*!< EADC_T::SCTL9: CHSEL Mask */
#define EADC_SCTL9_EXTREN_Pos (4) /*!< EADC_T::SCTL9: EXTREN Position */
#define EADC_SCTL9_EXTREN_Msk (0x1ul << EADC_SCTL9_EXTREN_Pos) /*!< EADC_T::SCTL9: EXTREN Mask */
#define EADC_SCTL9_EXTFEN_Pos (5) /*!< EADC_T::SCTL9: EXTFEN Position */
#define EADC_SCTL9_EXTFEN_Msk (0x1ul << EADC_SCTL9_EXTFEN_Pos) /*!< EADC_T::SCTL9: EXTFEN Mask */
#define EADC_SCTL9_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL9: TRGDLYDIV Position */
#define EADC_SCTL9_TRGDLYDIV_Msk (0x3ul << EADC_SCTL9_TRGDLYDIV_Pos) /*!< EADC_T::SCTL9: TRGDLYDIV Mask */
#define EADC_SCTL9_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL9: TRGDLYCNT Position */
#define EADC_SCTL9_TRGDLYCNT_Msk (0xfful << EADC_SCTL9_TRGDLYCNT_Pos) /*!< EADC_T::SCTL9: TRGDLYCNT Mask */
#define EADC_SCTL9_TRGSEL_Pos (16) /*!< EADC_T::SCTL9: TRGSEL Position */
#define EADC_SCTL9_TRGSEL_Msk (0x1ful << EADC_SCTL9_TRGSEL_Pos) /*!< EADC_T::SCTL9: TRGSEL Mask */
#define EADC_SCTL9_INTPOS_Pos (22) /*!< EADC_T::SCTL9: INTPOS Position */
#define EADC_SCTL9_INTPOS_Msk (0x1ul << EADC_SCTL9_INTPOS_Pos) /*!< EADC_T::SCTL9: INTPOS Mask */
#define EADC_SCTL9_EXTSMPT_Pos (24) /*!< EADC_T::SCTL9: EXTSMPT Position */
#define EADC_SCTL9_EXTSMPT_Msk (0xfful << EADC_SCTL9_EXTSMPT_Pos) /*!< EADC_T::SCTL9: EXTSMPT Mask */
#define EADC_SCTL10_CHSEL_Pos (0) /*!< EADC_T::SCTL10: CHSEL Position */
#define EADC_SCTL10_CHSEL_Msk (0xful << EADC_SCTL10_CHSEL_Pos) /*!< EADC_T::SCTL10: CHSEL Mask */
#define EADC_SCTL10_EXTREN_Pos (4) /*!< EADC_T::SCTL10: EXTREN Position */
#define EADC_SCTL10_EXTREN_Msk (0x1ul << EADC_SCTL10_EXTREN_Pos) /*!< EADC_T::SCTL10: EXTREN Mask */
#define EADC_SCTL10_EXTFEN_Pos (5) /*!< EADC_T::SCTL10: EXTFEN Position */
#define EADC_SCTL10_EXTFEN_Msk (0x1ul << EADC_SCTL10_EXTFEN_Pos) /*!< EADC_T::SCTL10: EXTFEN Mask */
#define EADC_SCTL10_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL10: TRGDLYDIV Position */
#define EADC_SCTL10_TRGDLYDIV_Msk (0x3ul << EADC_SCTL10_TRGDLYDIV_Pos) /*!< EADC_T::SCTL10: TRGDLYDIV Mask */
#define EADC_SCTL10_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL10: TRGDLYCNT Position */
#define EADC_SCTL10_TRGDLYCNT_Msk (0xfful << EADC_SCTL10_TRGDLYCNT_Pos) /*!< EADC_T::SCTL10: TRGDLYCNT Mask */
#define EADC_SCTL10_TRGSEL_Pos (16) /*!< EADC_T::SCTL10: TRGSEL Position */
#define EADC_SCTL10_TRGSEL_Msk (0x1ful << EADC_SCTL10_TRGSEL_Pos) /*!< EADC_T::SCTL10: TRGSEL Mask */
#define EADC_SCTL10_INTPOS_Pos (22) /*!< EADC_T::SCTL10: INTPOS Position */
#define EADC_SCTL10_INTPOS_Msk (0x1ul << EADC_SCTL10_INTPOS_Pos) /*!< EADC_T::SCTL10: INTPOS Mask */
#define EADC_SCTL10_EXTSMPT_Pos (24) /*!< EADC_T::SCTL10: EXTSMPT Position */
#define EADC_SCTL10_EXTSMPT_Msk (0xfful << EADC_SCTL10_EXTSMPT_Pos) /*!< EADC_T::SCTL10: EXTSMPT Mask */
#define EADC_SCTL11_CHSEL_Pos (0) /*!< EADC_T::SCTL11: CHSEL Position */
#define EADC_SCTL11_CHSEL_Msk (0xful << EADC_SCTL11_CHSEL_Pos) /*!< EADC_T::SCTL11: CHSEL Mask */
#define EADC_SCTL11_EXTREN_Pos (4) /*!< EADC_T::SCTL11: EXTREN Position */
#define EADC_SCTL11_EXTREN_Msk (0x1ul << EADC_SCTL11_EXTREN_Pos) /*!< EADC_T::SCTL11: EXTREN Mask */
#define EADC_SCTL11_EXTFEN_Pos (5) /*!< EADC_T::SCTL11: EXTFEN Position */
#define EADC_SCTL11_EXTFEN_Msk (0x1ul << EADC_SCTL11_EXTFEN_Pos) /*!< EADC_T::SCTL11: EXTFEN Mask */
#define EADC_SCTL11_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL11: TRGDLYDIV Position */
#define EADC_SCTL11_TRGDLYDIV_Msk (0x3ul << EADC_SCTL11_TRGDLYDIV_Pos) /*!< EADC_T::SCTL11: TRGDLYDIV Mask */
#define EADC_SCTL11_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL11: TRGDLYCNT Position */
#define EADC_SCTL11_TRGDLYCNT_Msk (0xfful << EADC_SCTL11_TRGDLYCNT_Pos) /*!< EADC_T::SCTL11: TRGDLYCNT Mask */
#define EADC_SCTL11_TRGSEL_Pos (16) /*!< EADC_T::SCTL11: TRGSEL Position */
#define EADC_SCTL11_TRGSEL_Msk (0x1ful << EADC_SCTL11_TRGSEL_Pos) /*!< EADC_T::SCTL11: TRGSEL Mask */
#define EADC_SCTL11_INTPOS_Pos (22) /*!< EADC_T::SCTL11: INTPOS Position */
#define EADC_SCTL11_INTPOS_Msk (0x1ul << EADC_SCTL11_INTPOS_Pos) /*!< EADC_T::SCTL11: INTPOS Mask */
#define EADC_SCTL11_EXTSMPT_Pos (24) /*!< EADC_T::SCTL11: EXTSMPT Position */
#define EADC_SCTL11_EXTSMPT_Msk (0xfful << EADC_SCTL11_EXTSMPT_Pos) /*!< EADC_T::SCTL11: EXTSMPT Mask */
#define EADC_SCTL12_CHSEL_Pos (0) /*!< EADC_T::SCTL12: CHSEL Position */
#define EADC_SCTL12_CHSEL_Msk (0xful << EADC_SCTL12_CHSEL_Pos) /*!< EADC_T::SCTL12: CHSEL Mask */
#define EADC_SCTL12_EXTREN_Pos (4) /*!< EADC_T::SCTL12: EXTREN Position */
#define EADC_SCTL12_EXTREN_Msk (0x1ul << EADC_SCTL12_EXTREN_Pos) /*!< EADC_T::SCTL12: EXTREN Mask */
#define EADC_SCTL12_EXTFEN_Pos (5) /*!< EADC_T::SCTL12: EXTFEN Position */
#define EADC_SCTL12_EXTFEN_Msk (0x1ul << EADC_SCTL12_EXTFEN_Pos) /*!< EADC_T::SCTL12: EXTFEN Mask */
#define EADC_SCTL12_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL12: TRGDLYDIV Position */
#define EADC_SCTL12_TRGDLYDIV_Msk (0x3ul << EADC_SCTL12_TRGDLYDIV_Pos) /*!< EADC_T::SCTL12: TRGDLYDIV Mask */
#define EADC_SCTL12_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL12: TRGDLYCNT Position */
#define EADC_SCTL12_TRGDLYCNT_Msk (0xfful << EADC_SCTL12_TRGDLYCNT_Pos) /*!< EADC_T::SCTL12: TRGDLYCNT Mask */
#define EADC_SCTL12_TRGSEL_Pos (16) /*!< EADC_T::SCTL12: TRGSEL Position */
#define EADC_SCTL12_TRGSEL_Msk (0x1ful << EADC_SCTL12_TRGSEL_Pos) /*!< EADC_T::SCTL12: TRGSEL Mask */
#define EADC_SCTL12_INTPOS_Pos (22) /*!< EADC_T::SCTL12: INTPOS Position */
#define EADC_SCTL12_INTPOS_Msk (0x1ul << EADC_SCTL12_INTPOS_Pos) /*!< EADC_T::SCTL12: INTPOS Mask */
#define EADC_SCTL12_EXTSMPT_Pos (24) /*!< EADC_T::SCTL12: EXTSMPT Position */
#define EADC_SCTL12_EXTSMPT_Msk (0xfful << EADC_SCTL12_EXTSMPT_Pos) /*!< EADC_T::SCTL12: EXTSMPT Mask */
#define EADC_SCTL13_CHSEL_Pos (0) /*!< EADC_T::SCTL13: CHSEL Position */
#define EADC_SCTL13_CHSEL_Msk (0xful << EADC_SCTL13_CHSEL_Pos) /*!< EADC_T::SCTL13: CHSEL Mask */
#define EADC_SCTL13_EXTREN_Pos (4) /*!< EADC_T::SCTL13: EXTREN Position */
#define EADC_SCTL13_EXTREN_Msk (0x1ul << EADC_SCTL13_EXTREN_Pos) /*!< EADC_T::SCTL13: EXTREN Mask */
#define EADC_SCTL13_EXTFEN_Pos (5) /*!< EADC_T::SCTL13: EXTFEN Position */
#define EADC_SCTL13_EXTFEN_Msk (0x1ul << EADC_SCTL13_EXTFEN_Pos) /*!< EADC_T::SCTL13: EXTFEN Mask */
#define EADC_SCTL13_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL13: TRGDLYDIV Position */
#define EADC_SCTL13_TRGDLYDIV_Msk (0x3ul << EADC_SCTL13_TRGDLYDIV_Pos) /*!< EADC_T::SCTL13: TRGDLYDIV Mask */
#define EADC_SCTL13_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL13: TRGDLYCNT Position */
#define EADC_SCTL13_TRGDLYCNT_Msk (0xfful << EADC_SCTL13_TRGDLYCNT_Pos) /*!< EADC_T::SCTL13: TRGDLYCNT Mask */
#define EADC_SCTL13_TRGSEL_Pos (16) /*!< EADC_T::SCTL13: TRGSEL Position */
#define EADC_SCTL13_TRGSEL_Msk (0x1ful << EADC_SCTL13_TRGSEL_Pos) /*!< EADC_T::SCTL13: TRGSEL Mask */
#define EADC_SCTL13_INTPOS_Pos (22) /*!< EADC_T::SCTL13: INTPOS Position */
#define EADC_SCTL13_INTPOS_Msk (0x1ul << EADC_SCTL13_INTPOS_Pos) /*!< EADC_T::SCTL13: INTPOS Mask */
#define EADC_SCTL13_EXTSMPT_Pos (24) /*!< EADC_T::SCTL13: EXTSMPT Position */
#define EADC_SCTL13_EXTSMPT_Msk (0xfful << EADC_SCTL13_EXTSMPT_Pos) /*!< EADC_T::SCTL13: EXTSMPT Mask */
#define EADC_SCTL14_CHSEL_Pos (0) /*!< EADC_T::SCTL14: CHSEL Position */
#define EADC_SCTL14_CHSEL_Msk (0xful << EADC_SCTL14_CHSEL_Pos) /*!< EADC_T::SCTL14: CHSEL Mask */
#define EADC_SCTL14_EXTREN_Pos (4) /*!< EADC_T::SCTL14: EXTREN Position */
#define EADC_SCTL14_EXTREN_Msk (0x1ul << EADC_SCTL14_EXTREN_Pos) /*!< EADC_T::SCTL14: EXTREN Mask */
#define EADC_SCTL14_EXTFEN_Pos (5) /*!< EADC_T::SCTL14: EXTFEN Position */
#define EADC_SCTL14_EXTFEN_Msk (0x1ul << EADC_SCTL14_EXTFEN_Pos) /*!< EADC_T::SCTL14: EXTFEN Mask */
#define EADC_SCTL14_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL14: TRGDLYDIV Position */
#define EADC_SCTL14_TRGDLYDIV_Msk (0x3ul << EADC_SCTL14_TRGDLYDIV_Pos) /*!< EADC_T::SCTL14: TRGDLYDIV Mask */
#define EADC_SCTL14_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL14: TRGDLYCNT Position */
#define EADC_SCTL14_TRGDLYCNT_Msk (0xfful << EADC_SCTL14_TRGDLYCNT_Pos) /*!< EADC_T::SCTL14: TRGDLYCNT Mask */
#define EADC_SCTL14_TRGSEL_Pos (16) /*!< EADC_T::SCTL14: TRGSEL Position */
#define EADC_SCTL14_TRGSEL_Msk (0x1ful << EADC_SCTL14_TRGSEL_Pos) /*!< EADC_T::SCTL14: TRGSEL Mask */
#define EADC_SCTL14_INTPOS_Pos (22) /*!< EADC_T::SCTL14: INTPOS Position */
#define EADC_SCTL14_INTPOS_Msk (0x1ul << EADC_SCTL14_INTPOS_Pos) /*!< EADC_T::SCTL14: INTPOS Mask */
#define EADC_SCTL14_EXTSMPT_Pos (24) /*!< EADC_T::SCTL14: EXTSMPT Position */
#define EADC_SCTL14_EXTSMPT_Msk (0xfful << EADC_SCTL14_EXTSMPT_Pos) /*!< EADC_T::SCTL14: EXTSMPT Mask */
#define EADC_SCTL15_CHSEL_Pos (0) /*!< EADC_T::SCTL15: CHSEL Position */
#define EADC_SCTL15_CHSEL_Msk (0xful << EADC_SCTL15_CHSEL_Pos) /*!< EADC_T::SCTL15: CHSEL Mask */
#define EADC_SCTL15_EXTREN_Pos (4) /*!< EADC_T::SCTL15: EXTREN Position */
#define EADC_SCTL15_EXTREN_Msk (0x1ul << EADC_SCTL15_EXTREN_Pos) /*!< EADC_T::SCTL15: EXTREN Mask */
#define EADC_SCTL15_EXTFEN_Pos (5) /*!< EADC_T::SCTL15: EXTFEN Position */
#define EADC_SCTL15_EXTFEN_Msk (0x1ul << EADC_SCTL15_EXTFEN_Pos) /*!< EADC_T::SCTL15: EXTFEN Mask */
#define EADC_SCTL15_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL15: TRGDLYDIV Position */
#define EADC_SCTL15_TRGDLYDIV_Msk (0x3ul << EADC_SCTL15_TRGDLYDIV_Pos) /*!< EADC_T::SCTL15: TRGDLYDIV Mask */
#define EADC_SCTL15_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL15: TRGDLYCNT Position */
#define EADC_SCTL15_TRGDLYCNT_Msk (0xfful << EADC_SCTL15_TRGDLYCNT_Pos) /*!< EADC_T::SCTL15: TRGDLYCNT Mask */
#define EADC_SCTL15_TRGSEL_Pos (16) /*!< EADC_T::SCTL15: TRGSEL Position */
#define EADC_SCTL15_TRGSEL_Msk (0x1ful << EADC_SCTL15_TRGSEL_Pos) /*!< EADC_T::SCTL15: TRGSEL Mask */
#define EADC_SCTL15_INTPOS_Pos (22) /*!< EADC_T::SCTL15: INTPOS Position */
#define EADC_SCTL15_INTPOS_Msk (0x1ul << EADC_SCTL15_INTPOS_Pos) /*!< EADC_T::SCTL15: INTPOS Mask */
#define EADC_SCTL15_EXTSMPT_Pos (24) /*!< EADC_T::SCTL15: EXTSMPT Position */
#define EADC_SCTL15_EXTSMPT_Msk (0xfful << EADC_SCTL15_EXTSMPT_Pos) /*!< EADC_T::SCTL15: EXTSMPT Mask */
#define EADC_SCTL16_EXTSMPT_Pos (24) /*!< EADC_T::SCTL16: EXTSMPT Position */
#define EADC_SCTL16_EXTSMPT_Msk (0xfful << EADC_SCTL16_EXTSMPT_Pos) /*!< EADC_T::SCTL16: EXTSMPT Mask */
#define EADC_SCTL17_EXTSMPT_Pos (24) /*!< EADC_T::SCTL17: EXTSMPT Position */
#define EADC_SCTL17_EXTSMPT_Msk (0xfful << EADC_SCTL17_EXTSMPT_Pos) /*!< EADC_T::SCTL17: EXTSMPT Mask */
#define EADC_SCTL18_EXTSMPT_Pos (24) /*!< EADC_T::SCTL18: EXTSMPT Position */
#define EADC_SCTL18_EXTSMPT_Msk (0xfful << EADC_SCTL18_EXTSMPT_Pos) /*!< EADC_T::SCTL18: EXTSMPT Mask */
#define EADC_INTSRC0_SPLIE0_Pos (0) /*!< EADC_T::INTSRC0: SPLIE0 Position */
#define EADC_INTSRC0_SPLIE0_Msk (0x1ul << EADC_INTSRC0_SPLIE0_Pos) /*!< EADC_T::INTSRC0: SPLIE0 Mask */
#define EADC_INTSRC0_SPLIE1_Pos (1) /*!< EADC_T::INTSRC0: SPLIE1 Position */
#define EADC_INTSRC0_SPLIE1_Msk (0x1ul << EADC_INTSRC0_SPLIE1_Pos) /*!< EADC_T::INTSRC0: SPLIE1 Mask */
#define EADC_INTSRC0_SPLIE2_Pos (2) /*!< EADC_T::INTSRC0: SPLIE2 Position */
#define EADC_INTSRC0_SPLIE2_Msk (0x1ul << EADC_INTSRC0_SPLIE2_Pos) /*!< EADC_T::INTSRC0: SPLIE2 Mask */
#define EADC_INTSRC0_SPLIE3_Pos (3) /*!< EADC_T::INTSRC0: SPLIE3 Position */
#define EADC_INTSRC0_SPLIE3_Msk (0x1ul << EADC_INTSRC0_SPLIE3_Pos) /*!< EADC_T::INTSRC0: SPLIE3 Mask */
#define EADC_INTSRC0_SPLIE4_Pos (4) /*!< EADC_T::INTSRC0: SPLIE4 Position */
#define EADC_INTSRC0_SPLIE4_Msk (0x1ul << EADC_INTSRC0_SPLIE4_Pos) /*!< EADC_T::INTSRC0: SPLIE4 Mask */
#define EADC_INTSRC0_SPLIE5_Pos (5) /*!< EADC_T::INTSRC0: SPLIE5 Position */
#define EADC_INTSRC0_SPLIE5_Msk (0x1ul << EADC_INTSRC0_SPLIE5_Pos) /*!< EADC_T::INTSRC0: SPLIE5 Mask */
#define EADC_INTSRC0_SPLIE6_Pos (6) /*!< EADC_T::INTSRC0: SPLIE6 Position */
#define EADC_INTSRC0_SPLIE6_Msk (0x1ul << EADC_INTSRC0_SPLIE6_Pos) /*!< EADC_T::INTSRC0: SPLIE6 Mask */
#define EADC_INTSRC0_SPLIE7_Pos (7) /*!< EADC_T::INTSRC0: SPLIE7 Position */
#define EADC_INTSRC0_SPLIE7_Msk (0x1ul << EADC_INTSRC0_SPLIE7_Pos) /*!< EADC_T::INTSRC0: SPLIE7 Mask */
#define EADC_INTSRC0_SPLIE8_Pos (8) /*!< EADC_T::INTSRC0: SPLIE8 Position */
#define EADC_INTSRC0_SPLIE8_Msk (0x1ul << EADC_INTSRC0_SPLIE8_Pos) /*!< EADC_T::INTSRC0: SPLIE8 Mask */
#define EADC_INTSRC0_SPLIE9_Pos (9) /*!< EADC_T::INTSRC0: SPLIE9 Position */
#define EADC_INTSRC0_SPLIE9_Msk (0x1ul << EADC_INTSRC0_SPLIE9_Pos) /*!< EADC_T::INTSRC0: SPLIE9 Mask */
#define EADC_INTSRC0_SPLIE10_Pos (10) /*!< EADC_T::INTSRC0: SPLIE10 Position */
#define EADC_INTSRC0_SPLIE10_Msk (0x1ul << EADC_INTSRC0_SPLIE10_Pos) /*!< EADC_T::INTSRC0: SPLIE10 Mask */
#define EADC_INTSRC0_SPLIE11_Pos (11) /*!< EADC_T::INTSRC0: SPLIE11 Position */
#define EADC_INTSRC0_SPLIE11_Msk (0x1ul << EADC_INTSRC0_SPLIE11_Pos) /*!< EADC_T::INTSRC0: SPLIE11 Mask */
#define EADC_INTSRC0_SPLIE12_Pos (12) /*!< EADC_T::INTSRC0: SPLIE12 Position */
#define EADC_INTSRC0_SPLIE12_Msk (0x1ul << EADC_INTSRC0_SPLIE12_Pos) /*!< EADC_T::INTSRC0: SPLIE12 Mask */
#define EADC_INTSRC0_SPLIE13_Pos (13) /*!< EADC_T::INTSRC0: SPLIE13 Position */
#define EADC_INTSRC0_SPLIE13_Msk (0x1ul << EADC_INTSRC0_SPLIE13_Pos) /*!< EADC_T::INTSRC0: SPLIE13 Mask */
#define EADC_INTSRC0_SPLIE14_Pos (14) /*!< EADC_T::INTSRC0: SPLIE14 Position */
#define EADC_INTSRC0_SPLIE14_Msk (0x1ul << EADC_INTSRC0_SPLIE14_Pos) /*!< EADC_T::INTSRC0: SPLIE14 Mask */
#define EADC_INTSRC0_SPLIE15_Pos (15) /*!< EADC_T::INTSRC0: SPLIE15 Position */
#define EADC_INTSRC0_SPLIE15_Msk (0x1ul << EADC_INTSRC0_SPLIE15_Pos) /*!< EADC_T::INTSRC0: SPLIE15 Mask */
#define EADC_INTSRC0_SPLIE16_Pos (16) /*!< EADC_T::INTSRC0: SPLIE16 Position */
#define EADC_INTSRC0_SPLIE16_Msk (0x1ul << EADC_INTSRC0_SPLIE16_Pos) /*!< EADC_T::INTSRC0: SPLIE16 Mask */
#define EADC_INTSRC0_SPLIE17_Pos (17) /*!< EADC_T::INTSRC0: SPLIE17 Position */
#define EADC_INTSRC0_SPLIE17_Msk (0x1ul << EADC_INTSRC0_SPLIE17_Pos) /*!< EADC_T::INTSRC0: SPLIE17 Mask */
#define EADC_INTSRC0_SPLIE18_Pos (18) /*!< EADC_T::INTSRC0: SPLIE18 Position */
#define EADC_INTSRC0_SPLIE18_Msk (0x1ul << EADC_INTSRC0_SPLIE18_Pos) /*!< EADC_T::INTSRC0: SPLIE18 Mask */
#define EADC_INTSRC1_SPLIE0_Pos (0) /*!< EADC_T::INTSRC1: SPLIE0 Position */
#define EADC_INTSRC1_SPLIE0_Msk (0x1ul << EADC_INTSRC1_SPLIE0_Pos) /*!< EADC_T::INTSRC1: SPLIE0 Mask */
#define EADC_INTSRC1_SPLIE1_Pos (1) /*!< EADC_T::INTSRC1: SPLIE1 Position */
#define EADC_INTSRC1_SPLIE1_Msk (0x1ul << EADC_INTSRC1_SPLIE1_Pos) /*!< EADC_T::INTSRC1: SPLIE1 Mask */
#define EADC_INTSRC1_SPLIE2_Pos (2) /*!< EADC_T::INTSRC1: SPLIE2 Position */
#define EADC_INTSRC1_SPLIE2_Msk (0x1ul << EADC_INTSRC1_SPLIE2_Pos) /*!< EADC_T::INTSRC1: SPLIE2 Mask */
#define EADC_INTSRC1_SPLIE3_Pos (3) /*!< EADC_T::INTSRC1: SPLIE3 Position */
#define EADC_INTSRC1_SPLIE3_Msk (0x1ul << EADC_INTSRC1_SPLIE3_Pos) /*!< EADC_T::INTSRC1: SPLIE3 Mask */
#define EADC_INTSRC1_SPLIE4_Pos (4) /*!< EADC_T::INTSRC1: SPLIE4 Position */
#define EADC_INTSRC1_SPLIE4_Msk (0x1ul << EADC_INTSRC1_SPLIE4_Pos) /*!< EADC_T::INTSRC1: SPLIE4 Mask */
#define EADC_INTSRC1_SPLIE5_Pos (5) /*!< EADC_T::INTSRC1: SPLIE5 Position */
#define EADC_INTSRC1_SPLIE5_Msk (0x1ul << EADC_INTSRC1_SPLIE5_Pos) /*!< EADC_T::INTSRC1: SPLIE5 Mask */
#define EADC_INTSRC1_SPLIE6_Pos (6) /*!< EADC_T::INTSRC1: SPLIE6 Position */
#define EADC_INTSRC1_SPLIE6_Msk (0x1ul << EADC_INTSRC1_SPLIE6_Pos) /*!< EADC_T::INTSRC1: SPLIE6 Mask */
#define EADC_INTSRC1_SPLIE7_Pos (7) /*!< EADC_T::INTSRC1: SPLIE7 Position */
#define EADC_INTSRC1_SPLIE7_Msk (0x1ul << EADC_INTSRC1_SPLIE7_Pos) /*!< EADC_T::INTSRC1: SPLIE7 Mask */
#define EADC_INTSRC1_SPLIE8_Pos (8) /*!< EADC_T::INTSRC1: SPLIE8 Position */
#define EADC_INTSRC1_SPLIE8_Msk (0x1ul << EADC_INTSRC1_SPLIE8_Pos) /*!< EADC_T::INTSRC1: SPLIE8 Mask */
#define EADC_INTSRC1_SPLIE9_Pos (9) /*!< EADC_T::INTSRC1: SPLIE9 Position */
#define EADC_INTSRC1_SPLIE9_Msk (0x1ul << EADC_INTSRC1_SPLIE9_Pos) /*!< EADC_T::INTSRC1: SPLIE9 Mask */
#define EADC_INTSRC1_SPLIE10_Pos (10) /*!< EADC_T::INTSRC1: SPLIE10 Position */
#define EADC_INTSRC1_SPLIE10_Msk (0x1ul << EADC_INTSRC1_SPLIE10_Pos) /*!< EADC_T::INTSRC1: SPLIE10 Mask */
#define EADC_INTSRC1_SPLIE11_Pos (11) /*!< EADC_T::INTSRC1: SPLIE11 Position */
#define EADC_INTSRC1_SPLIE11_Msk (0x1ul << EADC_INTSRC1_SPLIE11_Pos) /*!< EADC_T::INTSRC1: SPLIE11 Mask */
#define EADC_INTSRC1_SPLIE12_Pos (12) /*!< EADC_T::INTSRC1: SPLIE12 Position */
#define EADC_INTSRC1_SPLIE12_Msk (0x1ul << EADC_INTSRC1_SPLIE12_Pos) /*!< EADC_T::INTSRC1: SPLIE12 Mask */
#define EADC_INTSRC1_SPLIE13_Pos (13) /*!< EADC_T::INTSRC1: SPLIE13 Position */
#define EADC_INTSRC1_SPLIE13_Msk (0x1ul << EADC_INTSRC1_SPLIE13_Pos) /*!< EADC_T::INTSRC1: SPLIE13 Mask */
#define EADC_INTSRC1_SPLIE14_Pos (14) /*!< EADC_T::INTSRC1: SPLIE14 Position */
#define EADC_INTSRC1_SPLIE14_Msk (0x1ul << EADC_INTSRC1_SPLIE14_Pos) /*!< EADC_T::INTSRC1: SPLIE14 Mask */
#define EADC_INTSRC1_SPLIE15_Pos (15) /*!< EADC_T::INTSRC1: SPLIE15 Position */
#define EADC_INTSRC1_SPLIE15_Msk (0x1ul << EADC_INTSRC1_SPLIE15_Pos) /*!< EADC_T::INTSRC1: SPLIE15 Mask */
#define EADC_INTSRC1_SPLIE16_Pos (16) /*!< EADC_T::INTSRC1: SPLIE16 Position */
#define EADC_INTSRC1_SPLIE16_Msk (0x1ul << EADC_INTSRC1_SPLIE16_Pos) /*!< EADC_T::INTSRC1: SPLIE16 Mask */
#define EADC_INTSRC1_SPLIE17_Pos (17) /*!< EADC_T::INTSRC1: SPLIE17 Position */
#define EADC_INTSRC1_SPLIE17_Msk (0x1ul << EADC_INTSRC1_SPLIE17_Pos) /*!< EADC_T::INTSRC1: SPLIE17 Mask */
#define EADC_INTSRC1_SPLIE18_Pos (18) /*!< EADC_T::INTSRC1: SPLIE18 Position */
#define EADC_INTSRC1_SPLIE18_Msk (0x1ul << EADC_INTSRC1_SPLIE18_Pos) /*!< EADC_T::INTSRC1: SPLIE18 Mask */
#define EADC_INTSRC2_SPLIE0_Pos (0) /*!< EADC_T::INTSRC2: SPLIE0 Position */
#define EADC_INTSRC2_SPLIE0_Msk (0x1ul << EADC_INTSRC2_SPLIE0_Pos) /*!< EADC_T::INTSRC2: SPLIE0 Mask */
#define EADC_INTSRC2_SPLIE1_Pos (1) /*!< EADC_T::INTSRC2: SPLIE1 Position */
#define EADC_INTSRC2_SPLIE1_Msk (0x1ul << EADC_INTSRC2_SPLIE1_Pos) /*!< EADC_T::INTSRC2: SPLIE1 Mask */
#define EADC_INTSRC2_SPLIE2_Pos (2) /*!< EADC_T::INTSRC2: SPLIE2 Position */
#define EADC_INTSRC2_SPLIE2_Msk (0x1ul << EADC_INTSRC2_SPLIE2_Pos) /*!< EADC_T::INTSRC2: SPLIE2 Mask */
#define EADC_INTSRC2_SPLIE3_Pos (3) /*!< EADC_T::INTSRC2: SPLIE3 Position */
#define EADC_INTSRC2_SPLIE3_Msk (0x1ul << EADC_INTSRC2_SPLIE3_Pos) /*!< EADC_T::INTSRC2: SPLIE3 Mask */
#define EADC_INTSRC2_SPLIE4_Pos (4) /*!< EADC_T::INTSRC2: SPLIE4 Position */
#define EADC_INTSRC2_SPLIE4_Msk (0x1ul << EADC_INTSRC2_SPLIE4_Pos) /*!< EADC_T::INTSRC2: SPLIE4 Mask */
#define EADC_INTSRC2_SPLIE5_Pos (5) /*!< EADC_T::INTSRC2: SPLIE5 Position */
#define EADC_INTSRC2_SPLIE5_Msk (0x1ul << EADC_INTSRC2_SPLIE5_Pos) /*!< EADC_T::INTSRC2: SPLIE5 Mask */
#define EADC_INTSRC2_SPLIE6_Pos (6) /*!< EADC_T::INTSRC2: SPLIE6 Position */
#define EADC_INTSRC2_SPLIE6_Msk (0x1ul << EADC_INTSRC2_SPLIE6_Pos) /*!< EADC_T::INTSRC2: SPLIE6 Mask */
#define EADC_INTSRC2_SPLIE7_Pos (7) /*!< EADC_T::INTSRC2: SPLIE7 Position */
#define EADC_INTSRC2_SPLIE7_Msk (0x1ul << EADC_INTSRC2_SPLIE7_Pos) /*!< EADC_T::INTSRC2: SPLIE7 Mask */
#define EADC_INTSRC2_SPLIE8_Pos (8) /*!< EADC_T::INTSRC2: SPLIE8 Position */
#define EADC_INTSRC2_SPLIE8_Msk (0x1ul << EADC_INTSRC2_SPLIE8_Pos) /*!< EADC_T::INTSRC2: SPLIE8 Mask */
#define EADC_INTSRC2_SPLIE9_Pos (9) /*!< EADC_T::INTSRC2: SPLIE9 Position */
#define EADC_INTSRC2_SPLIE9_Msk (0x1ul << EADC_INTSRC2_SPLIE9_Pos) /*!< EADC_T::INTSRC2: SPLIE9 Mask */
#define EADC_INTSRC2_SPLIE10_Pos (10) /*!< EADC_T::INTSRC2: SPLIE10 Position */
#define EADC_INTSRC2_SPLIE10_Msk (0x1ul << EADC_INTSRC2_SPLIE10_Pos) /*!< EADC_T::INTSRC2: SPLIE10 Mask */
#define EADC_INTSRC2_SPLIE11_Pos (11) /*!< EADC_T::INTSRC2: SPLIE11 Position */
#define EADC_INTSRC2_SPLIE11_Msk (0x1ul << EADC_INTSRC2_SPLIE11_Pos) /*!< EADC_T::INTSRC2: SPLIE11 Mask */
#define EADC_INTSRC2_SPLIE12_Pos (12) /*!< EADC_T::INTSRC2: SPLIE12 Position */
#define EADC_INTSRC2_SPLIE12_Msk (0x1ul << EADC_INTSRC2_SPLIE12_Pos) /*!< EADC_T::INTSRC2: SPLIE12 Mask */
#define EADC_INTSRC2_SPLIE13_Pos (13) /*!< EADC_T::INTSRC2: SPLIE13 Position */
#define EADC_INTSRC2_SPLIE13_Msk (0x1ul << EADC_INTSRC2_SPLIE13_Pos) /*!< EADC_T::INTSRC2: SPLIE13 Mask */
#define EADC_INTSRC2_SPLIE14_Pos (14) /*!< EADC_T::INTSRC2: SPLIE14 Position */
#define EADC_INTSRC2_SPLIE14_Msk (0x1ul << EADC_INTSRC2_SPLIE14_Pos) /*!< EADC_T::INTSRC2: SPLIE14 Mask */
#define EADC_INTSRC2_SPLIE15_Pos (15) /*!< EADC_T::INTSRC2: SPLIE15 Position */
#define EADC_INTSRC2_SPLIE15_Msk (0x1ul << EADC_INTSRC2_SPLIE15_Pos) /*!< EADC_T::INTSRC2: SPLIE15 Mask */
#define EADC_INTSRC2_SPLIE16_Pos (16) /*!< EADC_T::INTSRC2: SPLIE16 Position */
#define EADC_INTSRC2_SPLIE16_Msk (0x1ul << EADC_INTSRC2_SPLIE16_Pos) /*!< EADC_T::INTSRC2: SPLIE16 Mask */
#define EADC_INTSRC2_SPLIE17_Pos (17) /*!< EADC_T::INTSRC2: SPLIE17 Position */
#define EADC_INTSRC2_SPLIE17_Msk (0x1ul << EADC_INTSRC2_SPLIE17_Pos) /*!< EADC_T::INTSRC2: SPLIE17 Mask */
#define EADC_INTSRC2_SPLIE18_Pos (18) /*!< EADC_T::INTSRC2: SPLIE18 Position */
#define EADC_INTSRC2_SPLIE18_Msk (0x1ul << EADC_INTSRC2_SPLIE18_Pos) /*!< EADC_T::INTSRC2: SPLIE18 Mask */
#define EADC_INTSRC3_SPLIE0_Pos (0) /*!< EADC_T::INTSRC3: SPLIE0 Position */
#define EADC_INTSRC3_SPLIE0_Msk (0x1ul << EADC_INTSRC3_SPLIE0_Pos) /*!< EADC_T::INTSRC3: SPLIE0 Mask */
#define EADC_INTSRC3_SPLIE1_Pos (1) /*!< EADC_T::INTSRC3: SPLIE1 Position */
#define EADC_INTSRC3_SPLIE1_Msk (0x1ul << EADC_INTSRC3_SPLIE1_Pos) /*!< EADC_T::INTSRC3: SPLIE1 Mask */
#define EADC_INTSRC3_SPLIE2_Pos (2) /*!< EADC_T::INTSRC3: SPLIE2 Position */
#define EADC_INTSRC3_SPLIE2_Msk (0x1ul << EADC_INTSRC3_SPLIE2_Pos) /*!< EADC_T::INTSRC3: SPLIE2 Mask */
#define EADC_INTSRC3_SPLIE3_Pos (3) /*!< EADC_T::INTSRC3: SPLIE3 Position */
#define EADC_INTSRC3_SPLIE3_Msk (0x1ul << EADC_INTSRC3_SPLIE3_Pos) /*!< EADC_T::INTSRC3: SPLIE3 Mask */
#define EADC_INTSRC3_SPLIE4_Pos (4) /*!< EADC_T::INTSRC3: SPLIE4 Position */
#define EADC_INTSRC3_SPLIE4_Msk (0x1ul << EADC_INTSRC3_SPLIE4_Pos) /*!< EADC_T::INTSRC3: SPLIE4 Mask */
#define EADC_INTSRC3_SPLIE5_Pos (5) /*!< EADC_T::INTSRC3: SPLIE5 Position */
#define EADC_INTSRC3_SPLIE5_Msk (0x1ul << EADC_INTSRC3_SPLIE5_Pos) /*!< EADC_T::INTSRC3: SPLIE5 Mask */
#define EADC_INTSRC3_SPLIE6_Pos (6) /*!< EADC_T::INTSRC3: SPLIE6 Position */
#define EADC_INTSRC3_SPLIE6_Msk (0x1ul << EADC_INTSRC3_SPLIE6_Pos) /*!< EADC_T::INTSRC3: SPLIE6 Mask */
#define EADC_INTSRC3_SPLIE7_Pos (7) /*!< EADC_T::INTSRC3: SPLIE7 Position */
#define EADC_INTSRC3_SPLIE7_Msk (0x1ul << EADC_INTSRC3_SPLIE7_Pos) /*!< EADC_T::INTSRC3: SPLIE7 Mask */
#define EADC_INTSRC3_SPLIE8_Pos (8) /*!< EADC_T::INTSRC3: SPLIE8 Position */
#define EADC_INTSRC3_SPLIE8_Msk (0x1ul << EADC_INTSRC3_SPLIE8_Pos) /*!< EADC_T::INTSRC3: SPLIE8 Mask */
#define EADC_INTSRC3_SPLIE9_Pos (9) /*!< EADC_T::INTSRC3: SPLIE9 Position */
#define EADC_INTSRC3_SPLIE9_Msk (0x1ul << EADC_INTSRC3_SPLIE9_Pos) /*!< EADC_T::INTSRC3: SPLIE9 Mask */
#define EADC_INTSRC3_SPLIE10_Pos (10) /*!< EADC_T::INTSRC3: SPLIE10 Position */
#define EADC_INTSRC3_SPLIE10_Msk (0x1ul << EADC_INTSRC3_SPLIE10_Pos) /*!< EADC_T::INTSRC3: SPLIE10 Mask */
#define EADC_INTSRC3_SPLIE11_Pos (11) /*!< EADC_T::INTSRC3: SPLIE11 Position */
#define EADC_INTSRC3_SPLIE11_Msk (0x1ul << EADC_INTSRC3_SPLIE11_Pos) /*!< EADC_T::INTSRC3: SPLIE11 Mask */
#define EADC_INTSRC3_SPLIE12_Pos (12) /*!< EADC_T::INTSRC3: SPLIE12 Position */
#define EADC_INTSRC3_SPLIE12_Msk (0x1ul << EADC_INTSRC3_SPLIE12_Pos) /*!< EADC_T::INTSRC3: SPLIE12 Mask */
#define EADC_INTSRC3_SPLIE13_Pos (13) /*!< EADC_T::INTSRC3: SPLIE13 Position */
#define EADC_INTSRC3_SPLIE13_Msk (0x1ul << EADC_INTSRC3_SPLIE13_Pos) /*!< EADC_T::INTSRC3: SPLIE13 Mask */
#define EADC_INTSRC3_SPLIE14_Pos (14) /*!< EADC_T::INTSRC3: SPLIE14 Position */
#define EADC_INTSRC3_SPLIE14_Msk (0x1ul << EADC_INTSRC3_SPLIE14_Pos) /*!< EADC_T::INTSRC3: SPLIE14 Mask */
#define EADC_INTSRC3_SPLIE15_Pos (15) /*!< EADC_T::INTSRC3: SPLIE15 Position */
#define EADC_INTSRC3_SPLIE15_Msk (0x1ul << EADC_INTSRC3_SPLIE15_Pos) /*!< EADC_T::INTSRC3: SPLIE15 Mask */
#define EADC_INTSRC3_SPLIE16_Pos (16) /*!< EADC_T::INTSRC3: SPLIE16 Position */
#define EADC_INTSRC3_SPLIE16_Msk (0x1ul << EADC_INTSRC3_SPLIE16_Pos) /*!< EADC_T::INTSRC3: SPLIE16 Mask */
#define EADC_INTSRC3_SPLIE17_Pos (17) /*!< EADC_T::INTSRC3: SPLIE17 Position */
#define EADC_INTSRC3_SPLIE17_Msk (0x1ul << EADC_INTSRC3_SPLIE17_Pos) /*!< EADC_T::INTSRC3: SPLIE17 Mask */
#define EADC_INTSRC3_SPLIE18_Pos (18) /*!< EADC_T::INTSRC3: SPLIE18 Position */
#define EADC_INTSRC3_SPLIE18_Msk (0x1ul << EADC_INTSRC3_SPLIE18_Pos) /*!< EADC_T::INTSRC3: SPLIE18 Mask */
#define EADC_CMP_ADCMPEN_Pos (0) /*!< EADC_T::CMP: ADCMPEN Position */
#define EADC_CMP_ADCMPEN_Msk (0x1ul << EADC_CMP_ADCMPEN_Pos) /*!< EADC_T::CMP: ADCMPEN Mask */
#define EADC_CMP_ADCMPIE_Pos (1) /*!< EADC_T::CMP: ADCMPIE Position */
#define EADC_CMP_ADCMPIE_Msk (0x1ul << EADC_CMP_ADCMPIE_Pos) /*!< EADC_T::CMP: ADCMPIE Mask */
#define EADC_CMP_CMPCOND_Pos (2) /*!< EADC_T::CMP: CMPCOND Position */
#define EADC_CMP_CMPCOND_Msk (0x1ul << EADC_CMP_CMPCOND_Pos) /*!< EADC_T::CMP: CMPCOND Mask */
#define EADC_CMP_CMPSPL_Pos (3) /*!< EADC_T::CMP: CMPSPL Position */
#define EADC_CMP_CMPSPL_Msk (0x1ful << EADC_CMP_CMPSPL_Pos) /*!< EADC_T::CMP: CMPSPL Mask */
#define EADC_CMP_CMPMCNT_Pos (8) /*!< EADC_T::CMP: CMPMCNT Position */
#define EADC_CMP_CMPMCNT_Msk (0xful << EADC_CMP_CMPMCNT_Pos) /*!< EADC_T::CMP: CMPMCNT Mask */
#define EADC_CMP_CMPWEN_Pos (15) /*!< EADC_T::CMP: CMPWEN Position */
#define EADC_CMP_CMPWEN_Msk (0x1ul << EADC_CMP_CMPWEN_Pos) /*!< EADC_T::CMP: CMPWEN Mask */
#define EADC_CMP_CMPDAT_Pos (16) /*!< EADC_T::CMP: CMPDAT Position */
#define EADC_CMP_CMPDAT_Msk (0xffful << EADC_CMP_CMPDAT_Pos) /*!< EADC_T::CMP: CMPDAT Mask */
#define EADC_CMP0_ADCMPEN_Pos (0) /*!< EADC_T::CMP0: ADCMPEN Position */
#define EADC_CMP0_ADCMPEN_Msk (0x1ul << EADC_CMP0_ADCMPEN_Pos) /*!< EADC_T::CMP0: ADCMPEN Mask */
#define EADC_CMP0_ADCMPIE_Pos (1) /*!< EADC_T::CMP0: ADCMPIE Position */
#define EADC_CMP0_ADCMPIE_Msk (0x1ul << EADC_CMP0_ADCMPIE_Pos) /*!< EADC_T::CMP0: ADCMPIE Mask */
#define EADC_CMP0_CMPCOND_Pos (2) /*!< EADC_T::CMP0: CMPCOND Position */
#define EADC_CMP0_CMPCOND_Msk (0x1ul << EADC_CMP0_CMPCOND_Pos) /*!< EADC_T::CMP0: CMPCOND Mask */
#define EADC_CMP0_CMPSPL_Pos (3) /*!< EADC_T::CMP0: CMPSPL Position */
#define EADC_CMP0_CMPSPL_Msk (0x1ful << EADC_CMP0_CMPSPL_Pos) /*!< EADC_T::CMP0: CMPSPL Mask */
#define EADC_CMP0_CMPMCNT_Pos (8) /*!< EADC_T::CMP0: CMPMCNT Position */
#define EADC_CMP0_CMPMCNT_Msk (0xful << EADC_CMP0_CMPMCNT_Pos) /*!< EADC_T::CMP0: CMPMCNT Mask */
#define EADC_CMP0_CMPWEN_Pos (15) /*!< EADC_T::CMP0: CMPWEN Position */
#define EADC_CMP0_CMPWEN_Msk (0x1ul << EADC_CMP0_CMPWEN_Pos) /*!< EADC_T::CMP0: CMPWEN Mask */
#define EADC_CMP0_CMPDAT_Pos (16) /*!< EADC_T::CMP0: CMPDAT Position */
#define EADC_CMP0_CMPDAT_Msk (0xffful << EADC_CMP0_CMPDAT_Pos) /*!< EADC_T::CMP0: CMPDAT Mask */
#define EADC_CMP1_ADCMPEN_Pos (0) /*!< EADC_T::CMP1: ADCMPEN Position */
#define EADC_CMP1_ADCMPEN_Msk (0x1ul << EADC_CMP1_ADCMPEN_Pos) /*!< EADC_T::CMP1: ADCMPEN Mask */
#define EADC_CMP1_ADCMPIE_Pos (1) /*!< EADC_T::CMP1: ADCMPIE Position */
#define EADC_CMP1_ADCMPIE_Msk (0x1ul << EADC_CMP1_ADCMPIE_Pos) /*!< EADC_T::CMP1: ADCMPIE Mask */
#define EADC_CMP1_CMPCOND_Pos (2) /*!< EADC_T::CMP1: CMPCOND Position */
#define EADC_CMP1_CMPCOND_Msk (0x1ul << EADC_CMP1_CMPCOND_Pos) /*!< EADC_T::CMP1: CMPCOND Mask */
#define EADC_CMP1_CMPSPL_Pos (3) /*!< EADC_T::CMP1: CMPSPL Position */
#define EADC_CMP1_CMPSPL_Msk (0x1ful << EADC_CMP1_CMPSPL_Pos) /*!< EADC_T::CMP1: CMPSPL Mask */
#define EADC_CMP1_CMPMCNT_Pos (8) /*!< EADC_T::CMP1: CMPMCNT Position */
#define EADC_CMP1_CMPMCNT_Msk (0xful << EADC_CMP1_CMPMCNT_Pos) /*!< EADC_T::CMP1: CMPMCNT Mask */
#define EADC_CMP1_CMPWEN_Pos (15) /*!< EADC_T::CMP1: CMPWEN Position */
#define EADC_CMP1_CMPWEN_Msk (0x1ul << EADC_CMP1_CMPWEN_Pos) /*!< EADC_T::CMP1: CMPWEN Mask */
#define EADC_CMP1_CMPDAT_Pos (16) /*!< EADC_T::CMP1: CMPDAT Position */
#define EADC_CMP1_CMPDAT_Msk (0xffful << EADC_CMP1_CMPDAT_Pos) /*!< EADC_T::CMP1: CMPDAT Mask */
#define EADC_CMP2_ADCMPEN_Pos (0) /*!< EADC_T::CMP2: ADCMPEN Position */
#define EADC_CMP2_ADCMPEN_Msk (0x1ul << EADC_CMP2_ADCMPEN_Pos) /*!< EADC_T::CMP2: ADCMPEN Mask */
#define EADC_CMP2_ADCMPIE_Pos (1) /*!< EADC_T::CMP2: ADCMPIE Position */
#define EADC_CMP2_ADCMPIE_Msk (0x1ul << EADC_CMP2_ADCMPIE_Pos) /*!< EADC_T::CMP2: ADCMPIE Mask */
#define EADC_CMP2_CMPCOND_Pos (2) /*!< EADC_T::CMP2: CMPCOND Position */
#define EADC_CMP2_CMPCOND_Msk (0x1ul << EADC_CMP2_CMPCOND_Pos) /*!< EADC_T::CMP2: CMPCOND Mask */
#define EADC_CMP2_CMPSPL_Pos (3) /*!< EADC_T::CMP2: CMPSPL Position */
#define EADC_CMP2_CMPSPL_Msk (0x1ful << EADC_CMP2_CMPSPL_Pos) /*!< EADC_T::CMP2: CMPSPL Mask */
#define EADC_CMP2_CMPMCNT_Pos (8) /*!< EADC_T::CMP2: CMPMCNT Position */
#define EADC_CMP2_CMPMCNT_Msk (0xful << EADC_CMP2_CMPMCNT_Pos) /*!< EADC_T::CMP2: CMPMCNT Mask */
#define EADC_CMP2_CMPWEN_Pos (15) /*!< EADC_T::CMP2: CMPWEN Position */
#define EADC_CMP2_CMPWEN_Msk (0x1ul << EADC_CMP2_CMPWEN_Pos) /*!< EADC_T::CMP2: CMPWEN Mask */
#define EADC_CMP2_CMPDAT_Pos (16) /*!< EADC_T::CMP2: CMPDAT Position */
#define EADC_CMP2_CMPDAT_Msk (0xffful << EADC_CMP2_CMPDAT_Pos) /*!< EADC_T::CMP2: CMPDAT Mask */
#define EADC_CMP3_ADCMPEN_Pos (0) /*!< EADC_T::CMP3: ADCMPEN Position */
#define EADC_CMP3_ADCMPEN_Msk (0x1ul << EADC_CMP3_ADCMPEN_Pos) /*!< EADC_T::CMP3: ADCMPEN Mask */
#define EADC_CMP3_ADCMPIE_Pos (1) /*!< EADC_T::CMP3: ADCMPIE Position */
#define EADC_CMP3_ADCMPIE_Msk (0x1ul << EADC_CMP3_ADCMPIE_Pos) /*!< EADC_T::CMP3: ADCMPIE Mask */
#define EADC_CMP3_CMPCOND_Pos (2) /*!< EADC_T::CMP3: CMPCOND Position */
#define EADC_CMP3_CMPCOND_Msk (0x1ul << EADC_CMP3_CMPCOND_Pos) /*!< EADC_T::CMP3: CMPCOND Mask */
#define EADC_CMP3_CMPSPL_Pos (3) /*!< EADC_T::CMP3: CMPSPL Position */
#define EADC_CMP3_CMPSPL_Msk (0x1ful << EADC_CMP3_CMPSPL_Pos) /*!< EADC_T::CMP3: CMPSPL Mask */
#define EADC_CMP3_CMPMCNT_Pos (8) /*!< EADC_T::CMP3: CMPMCNT Position */
#define EADC_CMP3_CMPMCNT_Msk (0xful << EADC_CMP3_CMPMCNT_Pos) /*!< EADC_T::CMP3: CMPMCNT Mask */
#define EADC_CMP3_CMPWEN_Pos (15) /*!< EADC_T::CMP3: CMPWEN Position */
#define EADC_CMP3_CMPWEN_Msk (0x1ul << EADC_CMP3_CMPWEN_Pos) /*!< EADC_T::CMP3: CMPWEN Mask */
#define EADC_CMP3_CMPDAT_Pos (16) /*!< EADC_T::CMP3: CMPDAT Position */
#define EADC_CMP3_CMPDAT_Msk (0xffful << EADC_CMP3_CMPDAT_Pos) /*!< EADC_T::CMP3: CMPDAT Mask */
#define EADC_STATUS0_VALID_Pos (0) /*!< EADC_T::STATUS0: VALID Position */
#define EADC_STATUS0_VALID_Msk (0xfffful << EADC_STATUS0_VALID_Pos) /*!< EADC_T::STATUS0: VALID Mask */
#define EADC_STATUS0_OV_Pos (16) /*!< EADC_T::STATUS0: OV Position */
#define EADC_STATUS0_OV_Msk (0xfffful << EADC_STATUS0_OV_Pos) /*!< EADC_T::STATUS0: OV Mask */
#define EADC_STATUS1_VALID_Pos (0) /*!< EADC_T::STATUS1: VALID Position */
#define EADC_STATUS1_VALID_Msk (0x7ul << EADC_STATUS1_VALID_Pos) /*!< EADC_T::STATUS1: VALID Mask */
#define EADC_STATUS1_OV_Pos (16) /*!< EADC_T::STATUS1: OV Position */
#define EADC_STATUS1_OV_Msk (0x7ul << EADC_STATUS1_OV_Pos) /*!< EADC_T::STATUS1: OV Mask */
#define EADC_STATUS2_ADIF0_Pos (0) /*!< EADC_T::STATUS2: ADIF0 Position */
#define EADC_STATUS2_ADIF0_Msk (0x1ul << EADC_STATUS2_ADIF0_Pos) /*!< EADC_T::STATUS2: ADIF0 Mask */
#define EADC_STATUS2_ADIF1_Pos (1) /*!< EADC_T::STATUS2: ADIF1 Position */
#define EADC_STATUS2_ADIF1_Msk (0x1ul << EADC_STATUS2_ADIF1_Pos) /*!< EADC_T::STATUS2: ADIF1 Mask */
#define EADC_STATUS2_ADIF2_Pos (2) /*!< EADC_T::STATUS2: ADIF2 Position */
#define EADC_STATUS2_ADIF2_Msk (0x1ul << EADC_STATUS2_ADIF2_Pos) /*!< EADC_T::STATUS2: ADIF2 Mask */
#define EADC_STATUS2_ADIF3_Pos (3) /*!< EADC_T::STATUS2: ADIF3 Position */
#define EADC_STATUS2_ADIF3_Msk (0x1ul << EADC_STATUS2_ADIF3_Pos) /*!< EADC_T::STATUS2: ADIF3 Mask */
#define EADC_STATUS2_ADCMPF0_Pos (4) /*!< EADC_T::STATUS2: ADCMPF0 Position */
#define EADC_STATUS2_ADCMPF0_Msk (0x1ul << EADC_STATUS2_ADCMPF0_Pos) /*!< EADC_T::STATUS2: ADCMPF0 Mask */
#define EADC_STATUS2_ADCMPF1_Pos (5) /*!< EADC_T::STATUS2: ADCMPF1 Position */
#define EADC_STATUS2_ADCMPF1_Msk (0x1ul << EADC_STATUS2_ADCMPF1_Pos) /*!< EADC_T::STATUS2: ADCMPF1 Mask */
#define EADC_STATUS2_ADCMPF2_Pos (6) /*!< EADC_T::STATUS2: ADCMPF2 Position */
#define EADC_STATUS2_ADCMPF2_Msk (0x1ul << EADC_STATUS2_ADCMPF2_Pos) /*!< EADC_T::STATUS2: ADCMPF2 Mask */
#define EADC_STATUS2_ADCMPF3_Pos (7) /*!< EADC_T::STATUS2: ADCMPF3 Position */
#define EADC_STATUS2_ADCMPF3_Msk (0x1ul << EADC_STATUS2_ADCMPF3_Pos) /*!< EADC_T::STATUS2: ADCMPF3 Mask */
#define EADC_STATUS2_ADOVIF0_Pos (8) /*!< EADC_T::STATUS2: ADOVIF0 Position */
#define EADC_STATUS2_ADOVIF0_Msk (0x1ul << EADC_STATUS2_ADOVIF0_Pos) /*!< EADC_T::STATUS2: ADOVIF0 Mask */
#define EADC_STATUS2_ADOVIF1_Pos (9) /*!< EADC_T::STATUS2: ADOVIF1 Position */
#define EADC_STATUS2_ADOVIF1_Msk (0x1ul << EADC_STATUS2_ADOVIF1_Pos) /*!< EADC_T::STATUS2: ADOVIF1 Mask */
#define EADC_STATUS2_ADOVIF2_Pos (10) /*!< EADC_T::STATUS2: ADOVIF2 Position */
#define EADC_STATUS2_ADOVIF2_Msk (0x1ul << EADC_STATUS2_ADOVIF2_Pos) /*!< EADC_T::STATUS2: ADOVIF2 Mask */
#define EADC_STATUS2_ADOVIF3_Pos (11) /*!< EADC_T::STATUS2: ADOVIF3 Position */
#define EADC_STATUS2_ADOVIF3_Msk (0x1ul << EADC_STATUS2_ADOVIF3_Pos) /*!< EADC_T::STATUS2: ADOVIF3 Mask */
#define EADC_STATUS2_ADCMPO0_Pos (12) /*!< EADC_T::STATUS2: ADCMPO0 Position */
#define EADC_STATUS2_ADCMPO0_Msk (0x1ul << EADC_STATUS2_ADCMPO0_Pos) /*!< EADC_T::STATUS2: ADCMPO0 Mask */
#define EADC_STATUS2_ADCMPO1_Pos (13) /*!< EADC_T::STATUS2: ADCMPO1 Position */
#define EADC_STATUS2_ADCMPO1_Msk (0x1ul << EADC_STATUS2_ADCMPO1_Pos) /*!< EADC_T::STATUS2: ADCMPO1 Mask */
#define EADC_STATUS2_ADCMPO2_Pos (14) /*!< EADC_T::STATUS2: ADCMPO2 Position */
#define EADC_STATUS2_ADCMPO2_Msk (0x1ul << EADC_STATUS2_ADCMPO2_Pos) /*!< EADC_T::STATUS2: ADCMPO2 Mask */
#define EADC_STATUS2_ADCMPO3_Pos (15) /*!< EADC_T::STATUS2: ADCMPO3 Position */
#define EADC_STATUS2_ADCMPO3_Msk (0x1ul << EADC_STATUS2_ADCMPO3_Pos) /*!< EADC_T::STATUS2: ADCMPO3 Mask */
#define EADC_STATUS2_CHANNEL_Pos (16) /*!< EADC_T::STATUS2: CHANNEL Position */
#define EADC_STATUS2_CHANNEL_Msk (0x1ful << EADC_STATUS2_CHANNEL_Pos) /*!< EADC_T::STATUS2: CHANNEL Mask */
#define EADC_STATUS2_BUSY_Pos (23) /*!< EADC_T::STATUS2: BUSY Position */
#define EADC_STATUS2_BUSY_Msk (0x1ul << EADC_STATUS2_BUSY_Pos) /*!< EADC_T::STATUS2: BUSY Mask */
#define EADC_STATUS2_ADOVIF_Pos (24) /*!< EADC_T::STATUS2: ADOVIF Position */
#define EADC_STATUS2_ADOVIF_Msk (0x1ul << EADC_STATUS2_ADOVIF_Pos) /*!< EADC_T::STATUS2: ADOVIF Mask */
#define EADC_STATUS2_STOVF_Pos (25) /*!< EADC_T::STATUS2: STOVF Position */
#define EADC_STATUS2_STOVF_Msk (0x1ul << EADC_STATUS2_STOVF_Pos) /*!< EADC_T::STATUS2: STOVF Mask */
#define EADC_STATUS2_AVALID_Pos (26) /*!< EADC_T::STATUS2: AVALID Position */
#define EADC_STATUS2_AVALID_Msk (0x1ul << EADC_STATUS2_AVALID_Pos) /*!< EADC_T::STATUS2: AVALID Mask */
#define EADC_STATUS2_AOV_Pos (27) /*!< EADC_T::STATUS2: AOV Position */
#define EADC_STATUS2_AOV_Msk (0x1ul << EADC_STATUS2_AOV_Pos) /*!< EADC_T::STATUS2: AOV Mask */
#define EADC_STATUS3_CURSPL_Pos (0) /*!< EADC_T::STATUS3: CURSPL Position */
#define EADC_STATUS3_CURSPL_Msk (0x1ful << EADC_STATUS3_CURSPL_Pos) /*!< EADC_T::STATUS3: CURSPL Mask */
#define EADC_DDAT0_RESULT_Pos (0) /*!< EADC_T::DDAT0: RESULT Position */
#define EADC_DDAT0_RESULT_Msk (0xfffful << EADC_DDAT0_RESULT_Pos) /*!< EADC_T::DDAT0: RESULT Mask */
#define EADC_DDAT0_OV_Pos (16) /*!< EADC_T::DDAT0: OV Position */
#define EADC_DDAT0_OV_Msk (0x1ul << EADC_DDAT0_OV_Pos) /*!< EADC_T::DDAT0: OV Mask */
#define EADC_DDAT0_VALID_Pos (17) /*!< EADC_T::DDAT0: VALID Position */
#define EADC_DDAT0_VALID_Msk (0x1ul << EADC_DDAT0_VALID_Pos) /*!< EADC_T::DDAT0: VALID Mask */
#define EADC_DDAT1_RESULT_Pos (0) /*!< EADC_T::DDAT1: RESULT Position */
#define EADC_DDAT1_RESULT_Msk (0xfffful << EADC_DDAT1_RESULT_Pos) /*!< EADC_T::DDAT1: RESULT Mask */
#define EADC_DDAT1_OV_Pos (16) /*!< EADC_T::DDAT1: OV Position */
#define EADC_DDAT1_OV_Msk (0x1ul << EADC_DDAT1_OV_Pos) /*!< EADC_T::DDAT1: OV Mask */
#define EADC_DDAT1_VALID_Pos (17) /*!< EADC_T::DDAT1: VALID Position */
#define EADC_DDAT1_VALID_Msk (0x1ul << EADC_DDAT1_VALID_Pos) /*!< EADC_T::DDAT1: VALID Mask */
#define EADC_DDAT2_RESULT_Pos (0) /*!< EADC_T::DDAT2: RESULT Position */
#define EADC_DDAT2_RESULT_Msk (0xfffful << EADC_DDAT2_RESULT_Pos) /*!< EADC_T::DDAT2: RESULT Mask */
#define EADC_DDAT2_OV_Pos (16) /*!< EADC_T::DDAT2: OV Position */
#define EADC_DDAT2_OV_Msk (0x1ul << EADC_DDAT2_OV_Pos) /*!< EADC_T::DDAT2: OV Mask */
#define EADC_DDAT2_VALID_Pos (17) /*!< EADC_T::DDAT2: VALID Position */
#define EADC_DDAT2_VALID_Msk (0x1ul << EADC_DDAT2_VALID_Pos) /*!< EADC_T::DDAT2: VALID Mask */
#define EADC_DDAT3_RESULT_Pos (0) /*!< EADC_T::DDAT3: RESULT Position */
#define EADC_DDAT3_RESULT_Msk (0xfffful << EADC_DDAT3_RESULT_Pos) /*!< EADC_T::DDAT3: RESULT Mask */
#define EADC_DDAT3_OV_Pos (16) /*!< EADC_T::DDAT3: OV Position */
#define EADC_DDAT3_OV_Msk (0x1ul << EADC_DDAT3_OV_Pos) /*!< EADC_T::DDAT3: OV Mask */
#define EADC_DDAT3_VALID_Pos (17) /*!< EADC_T::DDAT3: VALID Position */
#define EADC_DDAT3_VALID_Msk (0x1ul << EADC_DDAT3_VALID_Pos) /*!< EADC_T::DDAT3: VALID Mask */
#define EADC_PWRM_PWUPRDY_Pos (0) /*!< EADC_T::PWRM: PWUPRDY Position */
#define EADC_PWRM_PWUPRDY_Msk (0x1ul << EADC_PWRM_PWUPRDY_Pos) /*!< EADC_T::PWRM: PWUPRDY Mask */
#define EADC_PWRM_PWUCALEN_Pos (1) /*!< EADC_T::PWRM: PWUCALEN Position */
#define EADC_PWRM_PWUCALEN_Msk (0x1ul << EADC_PWRM_PWUCALEN_Pos) /*!< EADC_T::PWRM: PWUCALEN Mask */
#define EADC_PWRM_PWDMOD_Pos (2) /*!< EADC_T::PWRM: PWDMOD Position */
#define EADC_PWRM_PWDMOD_Msk (0x3ul << EADC_PWRM_PWDMOD_Pos) /*!< EADC_T::PWRM: PWDMOD Mask */
#define EADC_PWRM_LDOSUT_Pos (8) /*!< EADC_T::PWRM: LDOSUT Position */
#define EADC_PWRM_LDOSUT_Msk (0xffful << EADC_PWRM_LDOSUT_Pos) /*!< EADC_T::PWRM: LDOSUT Mask */
#define EADC_CALCTL_CALSTART_Pos (1) /*!< EADC_T::CALCTL: CALSTART Position */
#define EADC_CALCTL_CALSTART_Msk (0x1ul << EADC_CALCTL_CALSTART_Pos) /*!< EADC_T::CALCTL: CALSTART Mask */
#define EADC_CALCTL_CALDONE_Pos (2) /*!< EADC_T::CALCTL: CALDONE Position */
#define EADC_CALCTL_CALDONE_Msk (0x1ul << EADC_CALCTL_CALDONE_Pos) /*!< EADC_T::CALCTL: CALDONE Mask */
#define EADC_CALCTL_CALSEL_Pos (3) /*!< EADC_T::CALCTL: CALSEL Position */
#define EADC_CALCTL_CALSEL_Msk (0x1ul << EADC_CALCTL_CALSEL_Pos) /*!< EADC_T::CALCTL: CALSEL Mask */
#define EADC_CALDWRD_CALWORD_Pos (0) /*!< EADC_T::CALDWRD: CALWORD Position */
#define EADC_CALDWRD_CALWORD_Msk (0x7ful << EADC_CALDWRD_CALWORD_Pos) /*!< EADC_T::CALDWRD: CALWORD Mask */
/**@}*/ /* EADC_CONST */
/**@}*/ /* end of EADC register group */
/*---------------------- Digital to Analog Converter -------------------------*/
/**
@addtogroup DAC Digital to Analog Converter(DAC)
Memory Mapped Structure for DAC Controller
@{ */
typedef struct {
/**
* @var DAC_T::CTL
* Offset: 0x00 DAC Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |DACEN |DAC Enable Bit
* | | |0 = DAC is Disabled.
* | | |1 = DAC is Enabled.
* |[1] |DACIEN |DAC Interrupt Enable Bit
* | | |0 = Interrupt is Disabled.
* | | |1 = Interrupt is Enabled.
* |[2] |DMAEN |DMA Mode Enable Bit
* | | |0 = DMA mode Disabled.
* | | |1 = DMA mode Enabled.
* |[3] |DMAURIEN |DMA Under-run Interrupt Enable Bit
* | | |0 = DMA under-run interrupt Disabled.
* | | |1 = DMA under-run interrupt Enabled.
* |[4] |TRGEN |Trigger Mode Enable Bit
* | | |0 = DAC event trigger mode Disabled.
* | | |1 = DAC event trigger mode Enabled.
* |[7:5] |TRGSEL |Trigger Source Selection
* | | |000 = Software trigger.
* | | |001 = External pin DAC0_ST trigger.
* | | |010 = Timer 0 trigger.
* | | |011 = Timer 1 trigger.
* | | |100 = Timer 2 trigger.
* | | |101 = Timer 3 trigger.
* | | |110 = EPWM0 trigger.
* | | |111 = EPWM1 trigger.
* |[8] |BYPASS |Bypass Buffer Mode
* | | |0 = Output voltage buffer Enabled.
* | | |1 = Output voltage buffer Disabled.
* |[10] |LALIGN |DAC Data Left-aligned Enabled Control
* | | |0 = Right alignment.
* | | |1 = Left alignment.
* |[13:12] |ETRGSEL |External Pin Trigger Selection
* | | |00 = Low level trigger.
* | | |01 = High level trigger.
* | | |10 = Falling edge trigger.
* | | |11 = Rising edge trigger.
* |[15:14] |BWSEL |DAC Data Bit-width Selection
* | | |00 = data is 12 bits.
* | | |01 = data is 8 bits.
* | | |Others = reserved.
* |[16] |GRPEN |DAC Group Mode Enable Bit
* | | |0 = DAC0 and DAC1 are not grouped.
* | | |1 = DAC0 and DAC1 are grouped.
* @var DAC_T::SWTRG
* Offset: 0x04 DAC Software Trigger Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SWTRG |Software Trigger
* | | |0 = Software trigger Disabled.
* | | |1 = Software trigger Enabled.
* | | |User writes this bit to generate one shot pulse and it is cleared to 0 by hardware automatically; Reading this bit will always get 0.
* @var DAC_T::DAT
* Offset: 0x08 DAC Data Holding Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |DACDAT |DAC 12-bit Holding Data
* | | |These bits are written by user software which specifies 12-bit conversion data for DAC output
* | | |The unused bits (DAC_DAT[3:0] in left-alignment mode and DAC_DAT[15:12] in right alignment mode) are ignored by DAC controller hardware.
* | | |12 bit left alignment: user has to load data into DAC_DAT[15:4] bits.
* | | |12 bit right alignment: user has to load data into DAC_DAT[11:0] bits.
* @var DAC_T::DATOUT
* Offset: 0x0C DAC Data Output Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[11:0] |DATOUT |DAC 12-bit Output Data
* | | |These bits are current digital data for DAC output conversion.
* | | |It is loaded from DAC_DAT register and user cannot write it directly.
* @var DAC_T::STATUS
* Offset: 0x10 DAC Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |FINISH |DAC Conversion Complete Finish Flag
* | | |0 = DAC is in conversion state.
* | | |1 = DAC conversion finish.
* | | |This bit set to 1 when conversion time counter counts to SETTLET
* | | |It is cleared to 0 when DAC starts a new conversion
* | | |User writes 1 to clear this bit to 0.
* |[1] |DMAUDR |DMA Under-run Interrupt Flag
* | | |0 = No DMA under-run error condition occurred.
* | | |1 = DMA under-run error condition occurred.
* | | |User writes 1 to clear this bit.
* |[8] |BUSY |DAC Busy Flag (Read Only)
* | | |0 = DAC is ready for next conversion.
* | | |1 = DAC is busy in conversion.
* | | |This is read only bit.
* @var DAC_T::TCTL
* Offset: 0x14 DAC Timing Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[9:0] |SETTLET |DAC Output Settling Time
* | | |User software needs to write appropriate value to these bits to meet DAC conversion settling time base on PCLK (APB clock) speed.
* | | |For example, DAC controller clock speed is 80MHz and DAC conversion settling time is 1 us, SETTLETvalue must be greater than 0x50.
* | | |SELTTLET = DAC controller clock speed x settling time.
*/
__IO uint32_t CTL; /*!< [0x0000] DAC Control Register */
__IO uint32_t SWTRG; /*!< [0x0004] DAC Software Trigger Control Register */
__IO uint32_t DAT; /*!< [0x0008] DAC Data Holding Register */
__I uint32_t DATOUT; /*!< [0x000c] DAC Data Output Register */
__IO uint32_t STATUS; /*!< [0x0010] DAC Status Register */
__IO uint32_t TCTL; /*!< [0x0014] DAC Timing Control Register */
} DAC_T;
/**
@addtogroup DAC_CONST DAC Bit Field Definition
Constant Definitions for DAC Controller
@{ */
#define DAC_CTL_DACEN_Pos (0) /*!< DAC_T::CTL: DACEN Position */
#define DAC_CTL_DACEN_Msk (0x1ul << DAC_CTL_DACEN_Pos) /*!< DAC_T::CTL: DACEN Mask */
#define DAC_CTL_DACIEN_Pos (1) /*!< DAC_T::CTL: DACIEN Position */
#define DAC_CTL_DACIEN_Msk (0x1ul << DAC_CTL_DACIEN_Pos) /*!< DAC_T::CTL: DACIEN Mask */
#define DAC_CTL_DMAEN_Pos (2) /*!< DAC_T::CTL: DMAEN Position */
#define DAC_CTL_DMAEN_Msk (0x1ul << DAC_CTL_DMAEN_Pos) /*!< DAC_T::CTL: DMAEN Mask */
#define DAC_CTL_DMAURIEN_Pos (3) /*!< DAC_T::CTL: DMAURIEN Position */
#define DAC_CTL_DMAURIEN_Msk (0x1ul << DAC_CTL_DMAURIEN_Pos) /*!< DAC_T::CTL: DMAURIEN Mask */
#define DAC_CTL_TRGEN_Pos (4) /*!< DAC_T::CTL: TRGEN Position */
#define DAC_CTL_TRGEN_Msk (0x1ul << DAC_CTL_TRGEN_Pos) /*!< DAC_T::CTL: TRGEN Mask */
#define DAC_CTL_TRGSEL_Pos (5) /*!< DAC_T::CTL: TRGSEL Position */
#define DAC_CTL_TRGSEL_Msk (0x7ul << DAC_CTL_TRGSEL_Pos) /*!< DAC_T::CTL: TRGSEL Mask */
#define DAC_CTL_BYPASS_Pos (8) /*!< DAC_T::CTL: BYPASS Position */
#define DAC_CTL_BYPASS_Msk (0x1ul << DAC_CTL_BYPASS_Pos) /*!< DAC_T::CTL: BYPASS Mask */
#define DAC_CTL_LALIGN_Pos (10) /*!< DAC_T::CTL: LALIGN Position */
#define DAC_CTL_LALIGN_Msk (0x1ul << DAC_CTL_LALIGN_Pos) /*!< DAC_T::CTL: LALIGN Mask */
#define DAC_CTL_ETRGSEL_Pos (12) /*!< DAC_T::CTL: ETRGSEL Position */
#define DAC_CTL_ETRGSEL_Msk (0x3ul << DAC_CTL_ETRGSEL_Pos) /*!< DAC_T::CTL: ETRGSEL Mask */
#define DAC_CTL_BWSEL_Pos (14) /*!< DAC_T::CTL: BWSEL Position */
#define DAC_CTL_BWSEL_Msk (0x3ul << DAC_CTL_BWSEL_Pos) /*!< DAC_T::CTL: BWSEL Mask */
#define DAC_CTL_GRPEN_Pos (16) /*!< DAC_T::CTL: GRPEN Position */
#define DAC_CTL_GRPEN_Msk (0x1ul << DAC_CTL_GRPEN_Pos) /*!< DAC_T::CTL: GRPEN Mask */
#define DAC_SWTRG_SWTRG_Pos (0) /*!< DAC_T::SWTRG: SWTRG Position */
#define DAC_SWTRG_SWTRG_Msk (0x1ul << DAC_SWTRG_SWTRG_Pos) /*!< DAC_T::SWTRG: SWTRG Mask */
#define DAC_DAT_DACDAT_Pos (0) /*!< DAC_T::DAT: DACDAT Position */
#define DAC_DAT_DACDAT_Msk (0xfffful << DAC_DAT_DACDAT_Pos) /*!< DAC_T::DAT: DACDAT Mask */
#define DAC_DATOUT_DATOUT_Pos (0) /*!< DAC_T::DATOUT: DATOUT Position */
#define DAC_DATOUT_DATOUT_Msk (0xffful << DAC_DATOUT_DATOUT_Pos) /*!< DAC_T::DATOUT: DATOUT Mask */
#define DAC_STATUS_FINISH_Pos (0) /*!< DAC_T::STATUS: FINISH Position */
#define DAC_STATUS_FINISH_Msk (0x1ul << DAC_STATUS_FINISH_Pos) /*!< DAC_T::STATUS: FINISH Mask */
#define DAC_STATUS_DMAUDR_Pos (1) /*!< DAC_T::STATUS: DMAUDR Position */
#define DAC_STATUS_DMAUDR_Msk (0x1ul << DAC_STATUS_DMAUDR_Pos) /*!< DAC_T::STATUS: DMAUDR Mask */
#define DAC_STATUS_BUSY_Pos (8) /*!< DAC_T::STATUS: BUSY Position */
#define DAC_STATUS_BUSY_Msk (0x1ul << DAC_STATUS_BUSY_Pos) /*!< DAC_T::STATUS: BUSY Mask */
#define DAC_TCTL_SETTLET_Pos (0) /*!< DAC_T::TCTL: SETTLET Position */
#define DAC_TCTL_SETTLET_Msk (0x3fful << DAC_TCTL_SETTLET_Pos) /*!< DAC_T::TCTL: SETTLET Mask */
/**@}*/ /* DAC_CONST */
/**@}*/ /* end of DAC register group */
/*---------------------- Analog Comparator Controller -------------------------*/
/**
@addtogroup ACMP Analog Comparator Controller(ACMP)
Memory Mapped Structure for ACMP Controller
@{ */
typedef struct {
/**
* @var ACMP_T::CTL
* Offset: 0x00~0x04 Analog Comparator 0/1 Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ACMPEN |Comparator Enable Bit
* | | |0 = Comparator x Disabled.
* | | |1 = Comparator x Enabled.
* |[1] |ACMPIE |Comparator Interrupt Enable Bit
* | | |0 = Comparator x interrupt Disabled.
* | | |1 = Comparator x interrupt Enabled
* | | |If WKEN (ACMP_CTL0[16]) is set to 1, the wake-up interrupt function will be enabled as well.
* |[3] |ACMPOINV |Comparator Output Inverse
* | | |0 = Comparator x output inverse Disabled.
* | | |1 = Comparator x output inverse Enabled.
* |[5:4] |NEGSEL |Comparator Negative Input Selection
* | | |00 = ACMPx_N pin.
* | | |01 = Internal comparator reference voltage (CRV).
* | | |10 = Band-gap voltage.
* | | |11 = DAC output.
* |[7:6] |POSSEL |Comparator Positive Input Selection
* | | |00 = Input from ACMPx_P0.
* | | |01 = Input from ACMPx_P1.
* | | |10 = Input from ACMPx_P2.
* | | |11 = Input from ACMPx_P3.
* |[9:8] |INTPOL |Interrupt Condition Polarity Selection
* | | |ACMPIFx will be set to 1 when comparator output edge condition is detected.
* | | |00 = Rising edge or falling edge.
* | | |01 = Rising edge.
* | | |10 = Falling edge.
* | | |11 = Reserved.
* |[12] |OUTSEL |Comparator Output Select
* | | |0 = Comparator x output to ACMPx_O pin is unfiltered comparator output.
* | | |1 = Comparator x output to ACMPx_O pin is from filter output.
* |[15:13] |FILTSEL |Comparator Output Filter Count Selection
* | | |000 = Filter function is Disabled.
* | | |001 = ACMPx output is sampled 1 consecutive PCLK.
* | | |010 = ACMPx output is sampled 2 consecutive PCLKs.
* | | |011 = ACMPx output is sampled 4 consecutive PCLKs.
* | | |100 = ACMPx output is sampled 8 consecutive PCLKs.
* | | |101 = ACMPx output is sampled 16 consecutive PCLKs.
* | | |110 = ACMPx output is sampled 32 consecutive PCLKs.
* | | |111 = ACMPx output is sampled 64 consecutive PCLKs.
* |[16] |WKEN |Power-down Wake-up Enable Bit
* | | |0 = Wake-up function Disabled.
* | | |1 = Wake-up function Enabled.
* |[17] |WLATEN |Window Latch Mode Enable Bit
* | | |0 = Window Latch Mode Disabled.
* | | |1 = Window Latch Mode Enabled.
* |[18] |WCMPSEL |Window Compare Mode Selection
* | | |0 = Window Compare Mode Disabled.
* | | |1 = Window Compare Mode is Selected.
* |[25:24] |HYSSEL |Hysteresis Mode Selection
* | | |00 = Hysteresis is 0mV.
* | | |01 = Hysteresis is 10mV.
* | | |10 = Hysteresis is 20mV.
* | | |11 = Hysteresis is 30mV.
* |[29:28] |MODESEL |Propagation Delay Mode Selection
* | | |00 = Max propagation delay is 4.5uS, operation current is 1.2uA.
* | | |01 = Max propagation delay is 2uS, operation current is 3uA.
* | | |10 = Max propagation delay is 600nS, operation current is 10uA.
* | | |11 = Max propagation delay is 200nS, operation current is 75uA.
* @var ACMP_T::STATUS
* Offset: 0x08 Analog Comparator Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ACMPIF0 |Comparator 0 Interrupt Flag
* | | |This bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL0[9:8])
* | | |is detected on comparator 0 output.
* | | |This will generate an interrupt if ACMPIE (ACMP_CTL0[1]) is set to 1.
* | | |Note: Write 1 to clear this bit to 0.
* |[1] |ACMPIF1 |Comparator 1 Interrupt Flag
* | | |This bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL1[9:8])
* | | |is detected on comparator 1 output.
* | | |This will cause an interrupt if ACMPIE (ACMP_CTL1[1]) is set to 1.
* | | |Note: Write 1 to clear this bit to 0.
* |[4] |ACMPO0 |Comparator 0 Output
* | | |Synchronized to the PCLK to allow reading by software
* | | |Cleared when the comparator 0 is disabled, i.e.
* | | |ACMPEN (ACMP_CTL0[0]) is cleared to 0.
* |[5] |ACMPO1 |Comparator 1 Output
* | | |Synchronized to the PCLK to allow reading by software.
* | | |Cleared when the comparator 1 is disabled, i.e.
* | | |ACMPEN (ACMP_CTL1[0]) is cleared to 0.
* |[8] |WKIF0 |Comparator 0 Power-down Wake-up Interrupt Flag
* | | |This bit will be set to 1 when ACMP0 wake-up interrupt event occurs.
* | | |0 = No power-down wake-up occurred.
* | | |1 = Power-down wake-up occurred.
* | | |Note: Write 1 to clear this bit to 0.
* |[9] |WKIF1 |Comparator 1 Power-down Wake-up Interrupt Flag
* | | |This bit will be set to 1 when ACMP1 wake-up interrupt event occurs.
* | | |0 = No power-down wake-up occurred.
* | | |1 = Power-down wake-up occurred.
* | | |Note: Write 1 to clear this bit to 0.
* |[12] |ACMPS0 |Comparator 0 Status
* | | |Synchronized to the PCLK to allow reading by software
* | | |Cleared when the comparator 0 is disabled, i.e.
* | | |ACMPEN (ACMP_CTL0[0]) is cleared to 0.
* |[13] |ACMPS1 |Comparator 1 Status
* | | |Synchronized to the PCLK to allow reading by software
* | | |Cleared when the comparator 1 is disabled, i.e.
* | | |ACMPEN (ACMP_CTL1[0]) is cleared to 0.
* |[16] |ACMPWO |Comparator Window Output
* | | |This bit shows the output status of window compare mode
* | | |0 = The positive input voltage is outside the window.
* | | |1 = The positive input voltage is in the window.
* @var ACMP_T::VREF
* Offset: 0x0C Analog Comparator Reference Voltage Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |CRVCTL |Comparator Reference Voltage Setting
* | | |CRV = CRV source voltage * (1/6+CRVCTL/24).
* |[6] |CRVSSEL |CRV Source Voltage Selection
* | | |0 = VDDA is selected as CRV source voltage.
* | | |1 = The reference voltage defined by SYS_VREFCTL register is selected as CRV source voltage.
*/
__IO uint32_t CTL[2]; /*!< [0x0000~0x0004] Analog Comparator 0/1 Control Register */
__IO uint32_t STATUS; /*!< [0x0008] Analog Comparator Status Register */
__IO uint32_t VREF; /*!< [0x000c] Analog Comparator Reference Voltage Control Register */
} ACMP_T;
/**
@addtogroup ACMP_CONST ACMP Bit Field Definition
Constant Definitions for ACMP Controller
@{ */
#define ACMP_CTL_ACMPEN_Pos (0) /*!< ACMP_T::CTL: ACMPEN Position */
#define ACMP_CTL_ACMPEN_Msk (0x1ul << ACMP_CTL_ACMPEN_Pos) /*!< ACMP_T::CTL: ACMPEN Mask */
#define ACMP_CTL_ACMPIE_Pos (1) /*!< ACMP_T::CTL: ACMPIE Position */
#define ACMP_CTL_ACMPIE_Msk (0x1ul << ACMP_CTL_ACMPIE_Pos) /*!< ACMP_T::CTL: ACMPIE Mask */
#define ACMP_CTL_ACMPOINV_Pos (3) /*!< ACMP_T::CTL: ACMPOINV Position */
#define ACMP_CTL_ACMPOINV_Msk (0x1ul << ACMP_CTL_ACMPOINV_Pos) /*!< ACMP_T::CTL: ACMPOINV Mask */
#define ACMP_CTL_NEGSEL_Pos (4) /*!< ACMP_T::CTL: NEGSEL Position */
#define ACMP_CTL_NEGSEL_Msk (0x3ul << ACMP_CTL_NEGSEL_Pos) /*!< ACMP_T::CTL: NEGSEL Mask */
#define ACMP_CTL_POSSEL_Pos (6) /*!< ACMP_T::CTL: POSSEL Position */
#define ACMP_CTL_POSSEL_Msk (0x3ul << ACMP_CTL_POSSEL_Pos) /*!< ACMP_T::CTL: POSSEL Mask */
#define ACMP_CTL_INTPOL_Pos (8) /*!< ACMP_T::CTL: INTPOL Position */
#define ACMP_CTL_INTPOL_Msk (0x3ul << ACMP_CTL_INTPOL_Pos) /*!< ACMP_T::CTL: INTPOL Mask */
#define ACMP_CTL_OUTSEL_Pos (12) /*!< ACMP_T::CTL: OUTSEL Position */
#define ACMP_CTL_OUTSEL_Msk (0x1ul << ACMP_CTL_OUTSEL_Pos) /*!< ACMP_T::CTL: OUTSEL Mask */
#define ACMP_CTL_FILTSEL_Pos (13) /*!< ACMP_T::CTL: FILTSEL Position */
#define ACMP_CTL_FILTSEL_Msk (0x7ul << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_T::CTL: FILTSEL Mask */
#define ACMP_CTL_WKEN_Pos (16) /*!< ACMP_T::CTL: WKEN Position */
#define ACMP_CTL_WKEN_Msk (0x1ul << ACMP_CTL_WKEN_Pos) /*!< ACMP_T::CTL: WKEN Mask */
#define ACMP_CTL_WLATEN_Pos (17) /*!< ACMP_T::CTL: WLATEN Position */
#define ACMP_CTL_WLATEN_Msk (0x1ul << ACMP_CTL_WLATEN_Pos) /*!< ACMP_T::CTL: WLATEN Mask */
#define ACMP_CTL_WCMPSEL_Pos (18) /*!< ACMP_T::CTL: WCMPSEL Position */
#define ACMP_CTL_WCMPSEL_Msk (0x1ul << ACMP_CTL_WCMPSEL_Pos) /*!< ACMP_T::CTL: WCMPSEL Mask */
#define ACMP_CTL_HYSSEL_Pos (24) /*!< ACMP_T::CTL: HYSSEL Position */
#define ACMP_CTL_HYSSEL_Msk (0x3ul << ACMP_CTL_HYSSEL_Pos) /*!< ACMP_T::CTL: HYSSEL Mask */
#define ACMP_CTL_MODESEL_Pos (28) /*!< ACMP_T::CTL: MODESEL Position */
#define ACMP_CTL_MODESEL_Msk (0x3ul << ACMP_CTL_MODESEL_Pos) /*!< ACMP_T::CTL: MODESEL Mask */
#define ACMP_STATUS_ACMPIF0_Pos (0) /*!< ACMP_T::STATUS: ACMPIF0 Position */
#define ACMP_STATUS_ACMPIF0_Msk (0x1ul << ACMP_STATUS_ACMPIF0_Pos) /*!< ACMP_T::STATUS: ACMPIF0 Mask */
#define ACMP_STATUS_ACMPIF1_Pos (1) /*!< ACMP_T::STATUS: ACMPIF1 Position */
#define ACMP_STATUS_ACMPIF1_Msk (0x1ul << ACMP_STATUS_ACMPIF1_Pos) /*!< ACMP_T::STATUS: ACMPIF1 Mask */
#define ACMP_STATUS_ACMPO0_Pos (4) /*!< ACMP_T::STATUS: ACMPO0 Position */
#define ACMP_STATUS_ACMPO0_Msk (0x1ul << ACMP_STATUS_ACMPO0_Pos) /*!< ACMP_T::STATUS: ACMPO0 Mask */
#define ACMP_STATUS_ACMPO1_Pos (5) /*!< ACMP_T::STATUS: ACMPO1 Position */
#define ACMP_STATUS_ACMPO1_Msk (0x1ul << ACMP_STATUS_ACMPO1_Pos) /*!< ACMP_T::STATUS: ACMPO1 Mask */
#define ACMP_STATUS_WKIF0_Pos (8) /*!< ACMP_T::STATUS: WKIF0 Position */
#define ACMP_STATUS_WKIF0_Msk (0x1ul << ACMP_STATUS_WKIF0_Pos) /*!< ACMP_T::STATUS: WKIF0 Mask */
#define ACMP_STATUS_WKIF1_Pos (9) /*!< ACMP_T::STATUS: WKIF1 Position */
#define ACMP_STATUS_WKIF1_Msk (0x1ul << ACMP_STATUS_WKIF1_Pos) /*!< ACMP_T::STATUS: WKIF1 Mask */
#define ACMP_STATUS_ACMPS0_Pos (12) /*!< ACMP_T::STATUS: ACMPS0 Position */
#define ACMP_STATUS_ACMPS0_Msk (0x1ul << ACMP_STATUS_ACMPS0_Pos) /*!< ACMP_T::STATUS: ACMPS0 Mask */
#define ACMP_STATUS_ACMPS1_Pos (13) /*!< ACMP_T::STATUS: ACMPS1 Position */
#define ACMP_STATUS_ACMPS1_Msk (0x1ul << ACMP_STATUS_ACMPS1_Pos) /*!< ACMP_T::STATUS: ACMPS1 Mask */
#define ACMP_STATUS_ACMPWO_Pos (16) /*!< ACMP_T::STATUS: ACMPWO Position */
#define ACMP_STATUS_ACMPWO_Msk (0x1ul << ACMP_STATUS_ACMPWO_Pos) /*!< ACMP_T::STATUS: ACMPWO Mask */
#define ACMP_VREF_CRVCTL_Pos (0) /*!< ACMP_T::VREF: CRVCTL Position */
#define ACMP_VREF_CRVCTL_Msk (0xful << ACMP_VREF_CRVCTL_Pos) /*!< ACMP_T::VREF: CRVCTL Mask */
#define ACMP_VREF_CRVSSEL_Pos (6) /*!< ACMP_T::VREF: CRVSSEL Position */
#define ACMP_VREF_CRVSSEL_Msk (0x1ul << ACMP_VREF_CRVSSEL_Pos) /*!< ACMP_T::VREF: CRVSSEL Mask */
/**@}*/ /* ACMP_CONST */
/**@}*/ /* end of ACMP register group */
/*---------------------- OP Amplifier -------------------------*/
/**
@addtogroup OPA OP Amplifier(OPA)
Memory Mapped Structure for OPA Controller
@{ */
typedef struct {
/**
* @var OPA_T::CTL
* Offset: 0x00 OP Amplifier Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |OPEN0 |OP Amplifier 0 Enable Bit
* | | |0 = OP amplifier0 Disabled.
* | | |1 = OP amplifier0 Enabled.
* | | |Note: OP Amplifier 0 output needs wait stable 20u03BCs after OPEN0 is set.
* |[1] |OPEN1 |OP Amplifier 1 Enable Bit
* | | |0 = OP amplifier1 Disabled.
* | | |1 = OP amplifier1 Enabled.
* | | |Note: OP Amplifier 1 output needs wait stable 20u03BCs after OPEN1 is set.
* |[2] |OPEN2 |OP Amplifier 2 Enable Bit
* | | |0 = OP amplifier2 Disabled.
* | | |1 = OP amplifier2 Enabled.
* | | |Note: OP Amplifier 2 output needs wait stable 20u03BCs after OPEN2 is set.
* |[4] |OPDOEN0 |OP Amplifier 0 Schmitt Trigger Non-inverting Buffer Enable Bit
* | | |0 = OP amplifier0 Schmitt Trigger non-invert buffer Disabled.
* | | |1 = OP amplifier0 Schmitt Trigger non-invert buffer Enabled.
* |[5] |OPDOEN1 |OP Amplifier 1 Schmitt Trigger Non-inverting Buffer Enable Bit
* | | |0 = OP amplifier1 Schmitt Trigger non-invert buffer Disabled.
* | | |1 = OP amplifier1 Schmitt Trigger non-invert buffer Enabled.
* |[6] |OPDOEN2 |OP Amplifier 2 Schmitt Trigger Non-inverting Buffer Enable Bit
* | | |0 = OP amplifier2 Schmitt Trigger non-invert buffer Disabled.
* | | |1 = OP amplifier2 Schmitt Trigger non-invert buffer Enabled.
* |[8] |OPDOIEN0 |OP Amplifier 0 Schmitt Trigger Digital Output Interrupt Enable Bit
* | | |0 = OP Amplifier 0 digital output interrupt function Disabled.
* | | |1 = OP Amplifier 0 digital output interrupt function Enabled.
* | | |The OPDOIF0 interrupt flag is set by hardware whenever the OP amplifier 0 Schmitt Trigger non-inverting buffer digital output changes state, in the meanwhile, if OPDOIEN0 is set to 1, a comparator interrupt request is generated.
* |[9] |OPDOIEN1 |OP Amplifier 1 Schmitt Trigger Digital Output Interrupt Enable Bit
* | | |0 = OP Amplifier 1 digital output interrupt function Disabled.
* | | |1 = OP Amplifier 1 digital output interrupt function Enabled.
* | | |OPDOIF1 interrupt flag is set by hardware whenever the OP amplifier 1 Schmitt trigger non-inverting buffer digital output changes state, in the meanwhile, if OPDOIEN1 is set to 1, a comparator interrupt request is generated.
* |[10] |OPDOIEN2 |OP Amplifier 2 Schmitt Trigger Digital Output Interrupt Enable Bit
* | | |0 = OP Amplifier 2 digital output interrupt function Disabled.
* | | |1 = OP Amplifier 2 digital output interrupt function Enabled.
* | | |OPDOIF2 interrupt flag is set by hardware whenever the OP amplifier 2 Schmitt Trigger non-inverting buffer digital output changes state, in the meanwhile, if OPDOIEN2 is set to 1, a comparator interrupt request is generated.
* @var OPA_T::STATUS
* Offset: 0x04 OP Amplifier Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |OPDO0 |OP Amplifier 0 Digital Output
* | | |Synchronized to the APB clock to allow reading by software
* | | |Cleared when the Schmitt Trigger buffer is disabled (OPDOEN0 = 0)
* |[1] |OPDO1 |OP Amplifier 1 Digital Output
* | | |Synchronized to the APB clock to allow reading by software
* | | |Cleared when the Schmitt Trigger buffer is disabled (OPDOEN1 = 0)
* |[2] |OPDO2 |OP Amplifier 2 Digital Output
* | | |Synchronized to the APB clock to allow reading by software
* | | |Cleared when the Schmitt Trigger buffer is disabled (OPDOEN2 = 0)
* |[4] |OPDOIF0 |OP Amplifier 0 Schmitt Trigger Digital Output Interrupt Flag
* | | |OPDOIF0 interrupt flag is set by hardware whenever the OP amplifier 0 Schmitt Trigger non-inverting buffer digital output changes state
* | | |This bit is cleared by writing 1 to it.
* |[5] |OPDOIF1 |OP Amplifier 1 Schmitt Trigger Digital Output Interrupt Flag
* | | |OPDOIF1 interrupt flag is set by hardware whenever the OP amplifier 1 Schmitt Trigger non-inverting buffer digital output changes state
* | | |This bit is cleared by writing 1 to it.
* |[6] |OPDOIF2 |OP Amplifier 2 Schmitt Trigger Digital Output Interrupt Flag
* | | |OPDOIF2 interrupt flag is set by hardware whenever the OP amplifier 2 Schmitt Trigger non-inverting buffer digital output changes state
* | | |This bit is cleared by writing 1 to it.
* @var OPA_T::CALCTL
* Offset: 0x08 OP Amplifier Calibration Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CALTRG0 |OP Amplifier 0 Calibration Trigger Bit
* | | |0 = Stop, hardware auto clear.
* | | |1 = Start. Note: Before enable this bit, it should set OPEN0 in advance.
* |[1] |CALTRG1 |OP Amplifier 1 Calibration Trigger Bit
* | | |0 = Stop, hardware auto clear.
* | | |1 = Start. Note: Before enable this bit, it should set OPEN1 in advance.
* |[2] |CALTRG2 |OP Amplifier 2 Calibration Trigger Bit
* | | |0 = Stop, hardware auto clear.
* | | |1 = Start. Note: Before enable this bit, it should set OPEN2 in advance.
* |[16] |CALRVS0 |OPA0 Calibration Reference Voltage Selection
* | | |0 = VREF is AVDD.
* | | |1 = VREF from high vcm to low vcm.
* |[17] |CALRVS1 |OPA1 Calibration Reference Voltage Selection
* | | |0 = VREF is AVDD.
* | | |1 = VREF from high vcm to low vcm.
* |[18] |CALRVS2 |OPA2 Calibration Reference Voltage Selection
* | | |0 = VREF is AVDD.
* | | |1 = VREF from high vcm to low vcm.
* @var OPA_T::CALST
* Offset: 0x0C OP Amplifier Calibration Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |DONE0 |OP Amplifier 0 Calibration Done Status
* | | |0 = Calibrating.
* | | |1 = Calibration Done.
* |[1] |CALNS0 |OP Amplifier 0 Calibration Result Status for NMOS
* | | |0 = Pass.
* | | |1 = Fail.
* |[2] |CALPS0 |OP Amplifier 0 Calibration Result Status for PMOS
* | | |0 = Pass.
* | | |1 = Fail.
* |[4] |DONE1 |OP Amplifier 1 Calibration Done Status
* | | |0 = Calibrating.
* | | |1 = Calibration Done.
* |[5] |CALNS1 |OP Amplifier 1 Calibration Result Status for NMOS
* | | |0 = Pass.
* | | |1 = Fail.
* |[6] |CALPS1 |OP Amplifier 1 Calibration Result Status for PMOS
* | | |0 = Pass.
* | | |1 = Fail.
* |[8] |DONE2 |OP Amplifier 2 Calibration Done Status
* | | |0 = Calibrating.
* | | |1 = Calibration Done.
* |[9] |CALNS2 |OP Amplifier 2 Calibration Result Status for NMOS
* | | |0 = Pass.
* | | |1 = Fail.
* |[10] |CALPS2 |OP Amplifier 2 Calibration Result Status for PMOS
* | | |0 = Pass.
* | | |1 = Fail.
*/
__IO uint32_t CTL; /*!< [0x0000] OP Amplifier Control Register */
__IO uint32_t STATUS; /*!< [0x0004] OP Amplifier Status Register */
__IO uint32_t CALCTL; /*!< [0x0008] OP Amplifier Calibration Control Register */
__I uint32_t CALST; /*!< [0x000c] OP Amplifier Calibration Status Register */
} OPA_T;
/**
@addtogroup OPA_CONST OPA Bit Field Definition
Constant Definitions for OPA Controller
@{ */
#define OPA_CTL_OPEN0_Pos (0) /*!< OPA_T::CTL: OPEN0 Position */
#define OPA_CTL_OPEN0_Msk (0x1ul << OPA_CTL_OPEN0_Pos) /*!< OPA_T::CTL: OPEN0 Mask */
#define OPA_CTL_OPEN1_Pos (1) /*!< OPA_T::CTL: OPEN1 Position */
#define OPA_CTL_OPEN1_Msk (0x1ul << OPA_CTL_OPEN1_Pos) /*!< OPA_T::CTL: OPEN1 Mask */
#define OPA_CTL_OPEN2_Pos (2) /*!< OPA_T::CTL: OPEN2 Position */
#define OPA_CTL_OPEN2_Msk (0x1ul << OPA_CTL_OPEN2_Pos) /*!< OPA_T::CTL: OPEN2 Mask */
#define OPA_CTL_OPDOEN0_Pos (4) /*!< OPA_T::CTL: OPDOEN0 Position */
#define OPA_CTL_OPDOEN0_Msk (0x1ul << OPA_CTL_OPDOEN0_Pos) /*!< OPA_T::CTL: OPDOEN0 Mask */
#define OPA_CTL_OPDOEN1_Pos (5) /*!< OPA_T::CTL: OPDOEN1 Position */
#define OPA_CTL_OPDOEN1_Msk (0x1ul << OPA_CTL_OPDOEN1_Pos) /*!< OPA_T::CTL: OPDOEN1 Mask */
#define OPA_CTL_OPDOEN2_Pos (6) /*!< OPA_T::CTL: OPDOEN2 Position */
#define OPA_CTL_OPDOEN2_Msk (0x1ul << OPA_CTL_OPDOEN2_Pos) /*!< OPA_T::CTL: OPDOEN2 Mask */
#define OPA_CTL_OPDOIEN0_Pos (8) /*!< OPA_T::CTL: OPDOIEN0 Position */
#define OPA_CTL_OPDOIEN0_Msk (0x1ul << OPA_CTL_OPDOIEN0_Pos) /*!< OPA_T::CTL: OPDOIEN0 Mask */
#define OPA_CTL_OPDOIEN1_Pos (9) /*!< OPA_T::CTL: OPDOIEN1 Position */
#define OPA_CTL_OPDOIEN1_Msk (0x1ul << OPA_CTL_OPDOIEN1_Pos) /*!< OPA_T::CTL: OPDOIEN1 Mask */
#define OPA_CTL_OPDOIEN2_Pos (10) /*!< OPA_T::CTL: OPDOIEN2 Position */
#define OPA_CTL_OPDOIEN2_Msk (0x1ul << OPA_CTL_OPDOIEN2_Pos) /*!< OPA_T::CTL: OPDOIEN2 Mask */
#define OPA_STATUS_OPDO0_Pos (0) /*!< OPA_T::STATUS: OPDO0 Position */
#define OPA_STATUS_OPDO0_Msk (0x1ul << OPA_STATUS_OPDO0_Pos) /*!< OPA_T::STATUS: OPDO0 Mask */
#define OPA_STATUS_OPDO1_Pos (1) /*!< OPA_T::STATUS: OPDO1 Position */
#define OPA_STATUS_OPDO1_Msk (0x1ul << OPA_STATUS_OPDO1_Pos) /*!< OPA_T::STATUS: OPDO1 Mask */
#define OPA_STATUS_OPDO2_Pos (2) /*!< OPA_T::STATUS: OPDO2 Position */
#define OPA_STATUS_OPDO2_Msk (0x1ul << OPA_STATUS_OPDO2_Pos) /*!< OPA_T::STATUS: OPDO2 Mask */
#define OPA_STATUS_OPDOIF0_Pos (4) /*!< OPA_T::STATUS: OPDOIF0 Position */
#define OPA_STATUS_OPDOIF0_Msk (0x1ul << OPA_STATUS_OPDOIF0_Pos) /*!< OPA_T::STATUS: OPDOIF0 Mask */
#define OPA_STATUS_OPDOIF1_Pos (5) /*!< OPA_T::STATUS: OPDOIF1 Position */
#define OPA_STATUS_OPDOIF1_Msk (0x1ul << OPA_STATUS_OPDOIF1_Pos) /*!< OPA_T::STATUS: OPDOIF1 Mask */
#define OPA_STATUS_OPDOIF2_Pos (6) /*!< OPA_T::STATUS: OPDOIF2 Position */
#define OPA_STATUS_OPDOIF2_Msk (0x1ul << OPA_STATUS_OPDOIF2_Pos) /*!< OPA_T::STATUS: OPDOIF2 Mask */
#define OPA_CALCTL_CALTRG0_Pos (0) /*!< OPA_T::CALCTL: CALTRG0 Position */
#define OPA_CALCTL_CALTRG0_Msk (0x1ul << OPA_CALCTL_CALTRG0_Pos) /*!< OPA_T::CALCTL: CALTRG0 Mask */
#define OPA_CALCTL_CALTRG1_Pos (1) /*!< OPA_T::CALCTL: CALTRG1 Position */
#define OPA_CALCTL_CALTRG1_Msk (0x1ul << OPA_CALCTL_CALTRG1_Pos) /*!< OPA_T::CALCTL: CALTRG1 Mask */
#define OPA_CALCTL_CALTRG2_Pos (2) /*!< OPA_T::CALCTL: CALTRG2 Position */
#define OPA_CALCTL_CALTRG2_Msk (0x1ul << OPA_CALCTL_CALTRG2_Pos) /*!< OPA_T::CALCTL: CALTRG2 Mask */
#define OPA_CALCTL_CALCLK0_Pos (4) /*!< OPA_T::CALCTL: CALCLK0 Position */
#define OPA_CALCTL_CALCLK0_Msk (0x3ul << OPA_CALCTL_CALCLK0_Pos) /*!< OPA_T::CALCTL: CALCLK0 Mask */
#define OPA_CALCTL_CALCLK1_Pos (6) /*!< OPA_T::CALCTL: CALCLK1 Position */
#define OPA_CALCTL_CALCLK1_Msk (0x3ul << OPA_CALCTL_CALCLK1_Pos) /*!< OPA_T::CALCTL: CALCLK1 Mask */
#define OPA_CALCTL_CALCLK2_Pos (8) /*!< OPA_T::CALCTL: CALCLK2 Position */
#define OPA_CALCTL_CALCLK2_Msk (0x3ul << OPA_CALCTL_CALCLK2_Pos) /*!< OPA_T::CALCTL: CALCLK2 Mask */
#define OPA_CALCTL_CALRVS0_Pos (16) /*!< OPA_T::CALCTL: CALRVS0 Position */
#define OPA_CALCTL_CALRVS0_Msk (0x1ul << OPA_CALCTL_CALRVS0_Pos) /*!< OPA_T::CALCTL: CALRVS0 Mask */
#define OPA_CALCTL_CALRVS1_Pos (17) /*!< OPA_T::CALCTL: CALRVS1 Position */
#define OPA_CALCTL_CALRVS1_Msk (0x1ul << OPA_CALCTL_CALRVS1_Pos) /*!< OPA_T::CALCTL: CALRVS1 Mask */
#define OPA_CALCTL_CALRVS2_Pos (18) /*!< OPA_T::CALCTL: CALRVS2 Position */
#define OPA_CALCTL_CALRVS2_Msk (0x1ul << OPA_CALCTL_CALRVS2_Pos) /*!< OPA_T::CALCTL: CALRVS2 Mask */
#define OPA_CALST_DONE0_Pos (0) /*!< OPA_T::CALST: DONE0 Position */
#define OPA_CALST_DONE0_Msk (0x1ul << OPA_CALST_DONE0_Pos) /*!< OPA_T::CALST: DONE0 Mask */
#define OPA_CALST_CALNS0_Pos (1) /*!< OPA_T::CALST: CALNS0 Position */
#define OPA_CALST_CALNS0_Msk (0x1ul << OPA_CALST_CALNS0_Pos) /*!< OPA_T::CALST: CALNS0 Mask */
#define OPA_CALST_CALPS0_Pos (2) /*!< OPA_T::CALST: CALPS0 Position */
#define OPA_CALST_CALPS0_Msk (0x1ul << OPA_CALST_CALPS0_Pos) /*!< OPA_T::CALST: CALPS0 Mask */
#define OPA_CALST_DONE1_Pos (4) /*!< OPA_T::CALST: DONE1 Position */
#define OPA_CALST_DONE1_Msk (0x1ul << OPA_CALST_DONE1_Pos) /*!< OPA_T::CALST: DONE1 Mask */
#define OPA_CALST_CALNS1_Pos (5) /*!< OPA_T::CALST: CALNS1 Position */
#define OPA_CALST_CALNS1_Msk (0x1ul << OPA_CALST_CALNS1_Pos) /*!< OPA_T::CALST: CALNS1 Mask */
#define OPA_CALST_CALPS1_Pos (6) /*!< OPA_T::CALST: CALPS1 Position */
#define OPA_CALST_CALPS1_Msk (0x1ul << OPA_CALST_CALPS1_Pos) /*!< OPA_T::CALST: CALPS1 Mask */
#define OPA_CALST_DONE2_Pos (8) /*!< OPA_T::CALST: DONE2 Position */
#define OPA_CALST_DONE2_Msk (0x1ul << OPA_CALST_DONE2_Pos) /*!< OPA_T::CALST: DONE2 Mask */
#define OPA_CALST_CALNS2_Pos (9) /*!< OPA_T::CALST: CALNS2 Position */
#define OPA_CALST_CALNS2_Msk (0x1ul << OPA_CALST_CALNS2_Pos) /*!< OPA_T::CALST: CALNS2 Mask */
#define OPA_CALST_CALPS2_Pos (10) /*!< OPA_T::CALST: CALPS2 Position */
#define OPA_CALST_CALPS2_Msk (0x1ul << OPA_CALST_CALPS2_Pos) /*!< OPA_T::CALST: CALPS2 Mask */
/**@}*/ /* OPA_CONST */
/**@}*/ /* end of OPA register group */
/**@}*/ /* end of REGISTER group */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
/*@}*/ /* end of group M480_Peripherals */
/** @addtogroup M480_PERIPHERAL_MEM_MAP M480 Peripheral Memory Base
Memory Mapped Structure for M480 Peripheral
@{
*/
/* Peripheral and SRAM base address */
#define FLASH_BASE ((uint32_t)0x00000000) /*!< Flash base address */
#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM Base Address */
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral Base Address */
#define AHBPERIPH_BASE PERIPH_BASE /*!< AHB Base Address */
#define APBPERIPH_BASE (PERIPH_BASE + (uint32_t)0x00040000) /*!< APB Base Address */
/*!< AHB peripherals */
#define SYS_BASE (AHBPERIPH_BASE + 0x00000UL)
#define CLK_BASE (AHBPERIPH_BASE + 0x00200UL)
#define GPIOA_BASE (AHBPERIPH_BASE + 0x04000UL)
#define GPIOB_BASE (AHBPERIPH_BASE + 0x04040UL)
#define GPIOC_BASE (AHBPERIPH_BASE + 0x04080UL)
#define GPIOD_BASE (AHBPERIPH_BASE + 0x040C0UL)
#define GPIOE_BASE (AHBPERIPH_BASE + 0x04100UL)
#define GPIOF_BASE (AHBPERIPH_BASE + 0x04140UL)
#define GPIOG_BASE (AHBPERIPH_BASE + 0x04180UL)
#define GPIOH_BASE (AHBPERIPH_BASE + 0x041C0UL)
#define GPIOI_BASE (AHBPERIPH_BASE + 0x04200UL)
#define GPIO_DBCTL_BASE (AHBPERIPH_BASE + 0x04440UL)
#define GPIO_PIN_DATA_BASE (AHBPERIPH_BASE + 0x04800UL)
#define PDMA_BASE (AHBPERIPH_BASE + 0x08000UL)
#define USBH_BASE (AHBPERIPH_BASE + 0x09000UL)
#define HSUSBH_BASE (AHBPERIPH_BASE + 0x1A000UL)
#define EMAC_BASE (AHBPERIPH_BASE + 0x0B000UL)
#define FMC_BASE (AHBPERIPH_BASE + 0x0C000UL)
#define SDH0_BASE (AHBPERIPH_BASE + 0x0D000UL)
#define SDH1_BASE (AHBPERIPH_BASE + 0x0E000UL)
#define EBI_BASE (AHBPERIPH_BASE + 0x10000UL)
#define HSUSBD_BASE (AHBPERIPH_BASE + 0x19000UL)
#define CRC_BASE (AHBPERIPH_BASE + 0x31000UL)
#define TAMPER_BASE (AHBPERIPH_BASE + 0xE1000UL)
/*!< APB2 peripherals */
#define WDT_BASE (APBPERIPH_BASE + 0x00000UL)
#define WWDT_BASE (APBPERIPH_BASE + 0x00100UL)
#define OPA_BASE (APBPERIPH_BASE + 0x06000UL)
#define I2S_BASE (APBPERIPH_BASE + 0x08000UL)
#define TIMER0_BASE (APBPERIPH_BASE + 0x10000UL)
#define TIMER1_BASE (APBPERIPH_BASE + 0x10100UL)
#define EPWM0_BASE (APBPERIPH_BASE + 0x18000UL)
#define BPWM0_BASE (APBPERIPH_BASE + 0x1A000UL)
#define SPI0_BASE (APBPERIPH_BASE + 0x20000UL)
#define SPI2_BASE (APBPERIPH_BASE + 0x22000UL)
#define SPI4_BASE (APBPERIPH_BASE + 0x24000UL)
#define UART0_BASE (APBPERIPH_BASE + 0x30000UL)
#define UART2_BASE (APBPERIPH_BASE + 0x32000UL)
#define UART4_BASE (APBPERIPH_BASE + 0x34000UL)
#define I2C0_BASE (APBPERIPH_BASE + 0x40000UL)
#define I2C2_BASE (APBPERIPH_BASE + 0x42000UL)
#define CAN0_BASE (APBPERIPH_BASE + 0x60000UL)
#define QEI0_BASE (APBPERIPH_BASE + 0x70000UL)
#define ECAP0_BASE (APBPERIPH_BASE + 0x74000UL)
#define USCI0_BASE (APBPERIPH_BASE + 0x90000UL)
/*!< APB1 peripherals */
#define RTC_BASE (APBPERIPH_BASE + 0x01000UL)
#define EADC_BASE (APBPERIPH_BASE + 0x03000UL)
#define ACMP_BASE (APBPERIPH_BASE + 0x05000UL)
#define USBD_BASE (APBPERIPH_BASE + 0x80000UL)
#define OTG_BASE (APBPERIPH_BASE + 0x0D000UL)
#define HSOTG_BASE (APBPERIPH_BASE + 0x0F000UL)
#define TIMER2_BASE (APBPERIPH_BASE + 0x11000UL)
#define TIMER3_BASE (APBPERIPH_BASE + 0x11100UL)
#define EPWM1_BASE (APBPERIPH_BASE + 0x19000UL)
#define BPWM1_BASE (APBPERIPH_BASE + 0x1B000UL)
#define SPI1_BASE (APBPERIPH_BASE + 0x21000UL)
#define SPI3_BASE (APBPERIPH_BASE + 0x23000UL)
#define UART1_BASE (APBPERIPH_BASE + 0x31000UL)
#define UART3_BASE (APBPERIPH_BASE + 0x33000UL)
#define UART5_BASE (APBPERIPH_BASE + 0x35000UL)
#define I2C1_BASE (APBPERIPH_BASE + 0x41000UL)
#define CAN1_BASE (APBPERIPH_BASE + 0x61000UL)
#define QEI1_BASE (APBPERIPH_BASE + 0x71000UL)
#define ECAP1_BASE (APBPERIPH_BASE + 0x75000UL)
#define USCI1_BASE (APBPERIPH_BASE + 0x91000UL)
#define CRPT_BASE (0x50080000UL)
#define SPIM_BASE (0x40007000UL)
#define SC0_BASE (APBPERIPH_BASE + 0x50000UL)
#define SC1_BASE (APBPERIPH_BASE + 0x51000UL)
#define SC2_BASE (APBPERIPH_BASE + 0x52000UL)
#define DAC0_BASE (APBPERIPH_BASE + 0x07000UL)
#define DAC1_BASE (APBPERIPH_BASE + 0x07040UL)
#define DACDBG_BASE (APBPERIPH_BASE + 0x07FECUL)
#define OPA0_BASE (APBPERIPH_BASE + 0x06000UL)
/*@}*/ /* end of group M480_PERIPHERAL_MEM_MAP */
/** @addtogroup M480_PERIPHERAL_DECLARATION M480 Peripheral Pointer
The Declaration of M480 Peripheral
@{
*/
#define SYS ((SYS_T *) SYS_BASE)
#define CLK ((CLK_T *) CLK_BASE)
#define PA ((GPIO_T *) GPIOA_BASE)
#define PB ((GPIO_T *) GPIOB_BASE)
#define PC ((GPIO_T *) GPIOC_BASE)
#define PD ((GPIO_T *) GPIOD_BASE)
#define PE ((GPIO_T *) GPIOE_BASE)
#define PF ((GPIO_T *) GPIOF_BASE)
#define PG ((GPIO_T *) GPIOG_BASE)
#define PH ((GPIO_T *) GPIOH_BASE)
#define GPA ((GPIO_T *) GPIOA_BASE)
#define GPB ((GPIO_T *) GPIOB_BASE)
#define GPC ((GPIO_T *) GPIOC_BASE)
#define GPD ((GPIO_T *) GPIOD_BASE)
#define GPE ((GPIO_T *) GPIOE_BASE)
#define GPF ((GPIO_T *) GPIOF_BASE)
#define GPG ((GPIO_T *) GPIOG_BASE)
#define GPH ((GPIO_T *) GPIOH_BASE)
#define GPIO ((GPIO_DBCTL_T *) GPIO_DBCTL_BASE)
#define PDMA ((PDMA_T *) PDMA_BASE)
#define USBH ((USBH_T *) USBH_BASE)
#define HSUSBH ((HSUSBH_T *) HSUSBH_BASE)
#define EMAC ((EMAC_T *) EMAC_BASE)
#define FMC ((FMC_T *) FMC_BASE)
#define SDH0 ((SDH_T *) SDH0_BASE)
#define SDH1 ((SDH_T *) SDH1_BASE)
#define EBI ((EBI_T *) EBI_BASE)
#define CRC ((CRC_T *) CRC_BASE)
#define TAMPER ((TAMPER_T *) TAMPER_BASE)
#define WDT ((WDT_T *) WDT_BASE)
#define WWDT ((WWDT_T *) WWDT_BASE)
#define RTC ((RTC_T *) RTC_BASE)
#define EADC ((EADC_T *) EADC_BASE)
#define ACMP ((ACMP_T *) ACMP_BASE)
#define I2S0 ((I2S_T *) I2S_BASE)
#define USBD ((USBD_T *) USBD_BASE)
#define OTG ((OTG_T *) OTG_BASE)
#define HSUSBD ((HSUSBD_T *)HSUSBD_BASE)
#define HSOTG ((HSOTG_T *) HSOTG_BASE)
#define TIMER0 ((TIMER_T *) TIMER0_BASE)
#define TIMER1 ((TIMER_T *) TIMER1_BASE)
#define TIMER2 ((TIMER_T *) TIMER2_BASE)
#define TIMER3 ((TIMER_T *) TIMER3_BASE)
#define EPWM0 ((EPWM_T *) EPWM0_BASE)
#define EPWM1 ((EPWM_T *) EPWM1_BASE)
#define BPWM0 ((BPWM_T *) BPWM0_BASE)
#define BPWM1 ((BPWM_T *) BPWM1_BASE)
#define ECAP0 ((ECAP_T *) ECAP0_BASE)
#define ECAP1 ((ECAP_T *) ECAP1_BASE)
#define QEI0 ((QEI_T *) QEI0_BASE)
#define QEI1 ((QEI_T *) QEI1_BASE)
#define SPI0 ((SPI_T *) SPI0_BASE)
#define SPI1 ((SPI_T *) SPI1_BASE)
#define SPI2 ((SPI_T *) SPI2_BASE)
#define SPI3 ((SPI_T *) SPI3_BASE)
#define SPI4 ((SPI_T *) SPI4_BASE)
#define UART0 ((UART_T *) UART0_BASE)
#define UART1 ((UART_T *) UART1_BASE)
#define UART2 ((UART_T *) UART2_BASE)
#define UART3 ((UART_T *) UART3_BASE)
#define UART4 ((UART_T *) UART4_BASE)
#define UART5 ((UART_T *) UART5_BASE)
#define I2C0 ((I2C_T *) I2C0_BASE)
#define I2C1 ((I2C_T *) I2C1_BASE)
#define I2C2 ((I2C_T *) I2C2_BASE)
#define SC0 ((SC_T *) SC0_BASE)
#define SC1 ((SC_T *) SC1_BASE)
#define SC2 ((SC_T *) SC2_BASE)
#define CAN0 ((CAN_T *) CAN0_BASE)
#define CAN1 ((CAN_T *) CAN1_BASE)
#define CRPT ((CRPT_T *) CRPT_BASE)
#define SPIM ((volatile SPIM_T *) SPIM_BASE)
#define DAC0 ((DAC_T *) DAC0_BASE)
#define DAC1 ((DAC_T *) DAC1_BASE)
#define USPI0 ((USPI_T *) USCI0_BASE) /*!< USPI0 Configuration Struct */
#define USPI1 ((USPI_T *) USCI1_BASE) /*!< USPI1 Configuration Struct */
#define OPA ((OPA_T *) OPA_BASE)
#define UI2C0 ((UI2C_T *) USCI0_BASE) /*!< UI2C0 Configuration Struct */
#define UI2C1 ((UI2C_T *) USCI1_BASE) /*!< UI2C1 Configuration Struct */
#define UUART0 ((UUART_T *) USCI0_BASE) /*!< UUART0 Configuration Struct */
#define UUART1 ((UUART_T *) USCI1_BASE) /*!< UUART1 Configuration Struct */
/*@}*/ /* end of group M480_PERIPHERAL_DECLARATION */
/** @addtogroup M480_IO_ROUTINE M480 I/O Routines
The Declaration of M480 I/O Routines
@{
*/
typedef volatile unsigned char vu8; ///< Define 8-bit unsigned volatile data type
typedef volatile unsigned short vu16; ///< Define 16-bit unsigned volatile data type
typedef volatile unsigned long vu32; ///< Define 32-bit unsigned volatile data type
/**
* @brief Get a 8-bit unsigned value from specified address
* @param[in] addr Address to get 8-bit data from
* @return 8-bit unsigned value stored in specified address
*/
#define M8(addr) (*((vu8 *) (addr)))
/**
* @brief Get a 16-bit unsigned value from specified address
* @param[in] addr Address to get 16-bit data from
* @return 16-bit unsigned value stored in specified address
* @note The input address must be 16-bit aligned
*/
#define M16(addr) (*((vu16 *) (addr)))
/**
* @brief Get a 32-bit unsigned value from specified address
* @param[in] addr Address to get 32-bit data from
* @return 32-bit unsigned value stored in specified address
* @note The input address must be 32-bit aligned
*/
#define M32(addr) (*((vu32 *) (addr)))
/**
* @brief Set a 32-bit unsigned value to specified I/O port
* @param[in] port Port address to set 32-bit data
* @param[in] value Value to write to I/O port
* @return None
* @note The output port must be 32-bit aligned
*/
#define outpw(port,value) *((volatile unsigned int *)(port)) = (value)
/**
* @brief Get a 32-bit unsigned value from specified I/O port
* @param[in] port Port address to get 32-bit data from
* @return 32-bit unsigned value stored in specified I/O port
* @note The input port must be 32-bit aligned
*/
#define inpw(port) (*((volatile unsigned int *)(port)))
/**
* @brief Set a 16-bit unsigned value to specified I/O port
* @param[in] port Port address to set 16-bit data
* @param[in] value Value to write to I/O port
* @return None
* @note The output port must be 16-bit aligned
*/
#define outps(port,value) *((volatile unsigned short *)(port)) = (value)
/**
* @brief Get a 16-bit unsigned value from specified I/O port
* @param[in] port Port address to get 16-bit data from
* @return 16-bit unsigned value stored in specified I/O port
* @note The input port must be 16-bit aligned
*/
#define inps(port) (*((volatile unsigned short *)(port)))
/**
* @brief Set a 8-bit unsigned value to specified I/O port
* @param[in] port Port address to set 8-bit data
* @param[in] value Value to write to I/O port
* @return None
*/
#define outpb(port,value) *((volatile unsigned char *)(port)) = (value)
/**
* @brief Get a 8-bit unsigned value from specified I/O port
* @param[in] port Port address to get 8-bit data from
* @return 8-bit unsigned value stored in specified I/O port
*/
#define inpb(port) (*((volatile unsigned char *)(port)))
/**
* @brief Set a 32-bit unsigned value to specified I/O port
* @param[in] port Port address to set 32-bit data
* @param[in] value Value to write to I/O port
* @return None
* @note The output port must be 32-bit aligned
*/
#define outp32(port,value) *((volatile unsigned int *)(port)) = (value)
/**
* @brief Get a 32-bit unsigned value from specified I/O port
* @param[in] port Port address to get 32-bit data from
* @return 32-bit unsigned value stored in specified I/O port
* @note The input port must be 32-bit aligned
*/
#define inp32(port) (*((volatile unsigned int *)(port)))
/**
* @brief Set a 16-bit unsigned value to specified I/O port
* @param[in] port Port address to set 16-bit data
* @param[in] value Value to write to I/O port
* @return None
* @note The output port must be 16-bit aligned
*/
#define outp16(port,value) *((volatile unsigned short *)(port)) = (value)
/**
* @brief Get a 16-bit unsigned value from specified I/O port
* @param[in] port Port address to get 16-bit data from
* @return 16-bit unsigned value stored in specified I/O port
* @note The input port must be 16-bit aligned
*/
#define inp16(port) (*((volatile unsigned short *)(port)))
/**
* @brief Set a 8-bit unsigned value to specified I/O port
* @param[in] port Port address to set 8-bit data
* @param[in] value Value to write to I/O port
* @return None
*/
#define outp8(port,value) *((volatile unsigned char *)(port)) = (value)
/**
* @brief Get a 8-bit unsigned value from specified I/O port
* @param[in] port Port address to get 8-bit data from
* @return 8-bit unsigned value stored in specified I/O port
*/
#define inp8(port) (*((volatile unsigned char *)(port)))
/*@}*/ /* end of group M480_IO_ROUTINE */
/******************************************************************************/
/* Legacy Constants */
/******************************************************************************/
/** @addtogroup M480_legacy_Constants M480 Legacy Constants
M480 Legacy Constants
@{
*/
#ifndef NULL
#define NULL (0) ///< NULL pointer
#endif
#ifndef TRUE
#define TRUE (1UL) ///< Boolean true, define to use in API parameters or return value
#endif
#ifndef FALSE
#define FALSE (0UL) ///< Boolean false, define to use in API parameters or return value
#endif
#define ENABLE (1UL) ///< Enable, define to use in API parameters
#define DISABLE (0UL) ///< Disable, define to use in API parameters
/* Define one bit mask */
#define BIT0 (0x00000001UL) ///< Bit 0 mask of an 32 bit integer
#define BIT1 (0x00000002UL) ///< Bit 1 mask of an 32 bit integer
#define BIT2 (0x00000004UL) ///< Bit 2 mask of an 32 bit integer
#define BIT3 (0x00000008UL) ///< Bit 3 mask of an 32 bit integer
#define BIT4 (0x00000010UL) ///< Bit 4 mask of an 32 bit integer
#define BIT5 (0x00000020UL) ///< Bit 5 mask of an 32 bit integer
#define BIT6 (0x00000040UL) ///< Bit 6 mask of an 32 bit integer
#define BIT7 (0x00000080UL) ///< Bit 7 mask of an 32 bit integer
#define BIT8 (0x00000100UL) ///< Bit 8 mask of an 32 bit integer
#define BIT9 (0x00000200UL) ///< Bit 9 mask of an 32 bit integer
#define BIT10 (0x00000400UL) ///< Bit 10 mask of an 32 bit integer
#define BIT11 (0x00000800UL) ///< Bit 11 mask of an 32 bit integer
#define BIT12 (0x00001000UL) ///< Bit 12 mask of an 32 bit integer
#define BIT13 (0x00002000UL) ///< Bit 13 mask of an 32 bit integer
#define BIT14 (0x00004000UL) ///< Bit 14 mask of an 32 bit integer
#define BIT15 (0x00008000UL) ///< Bit 15 mask of an 32 bit integer
#define BIT16 (0x00010000UL) ///< Bit 16 mask of an 32 bit integer
#define BIT17 (0x00020000UL) ///< Bit 17 mask of an 32 bit integer
#define BIT18 (0x00040000UL) ///< Bit 18 mask of an 32 bit integer
#define BIT19 (0x00080000UL) ///< Bit 19 mask of an 32 bit integer
#define BIT20 (0x00100000UL) ///< Bit 20 mask of an 32 bit integer
#define BIT21 (0x00200000UL) ///< Bit 21 mask of an 32 bit integer
#define BIT22 (0x00400000UL) ///< Bit 22 mask of an 32 bit integer
#define BIT23 (0x00800000UL) ///< Bit 23 mask of an 32 bit integer
#define BIT24 (0x01000000UL) ///< Bit 24 mask of an 32 bit integer
#define BIT25 (0x02000000UL) ///< Bit 25 mask of an 32 bit integer
#define BIT26 (0x04000000UL) ///< Bit 26 mask of an 32 bit integer
#define BIT27 (0x08000000UL) ///< Bit 27 mask of an 32 bit integer
#define BIT28 (0x10000000UL) ///< Bit 28 mask of an 32 bit integer
#define BIT29 (0x20000000UL) ///< Bit 29 mask of an 32 bit integer
#define BIT30 (0x40000000UL) ///< Bit 30 mask of an 32 bit integer
#define BIT31 (0x80000000UL) ///< Bit 31 mask of an 32 bit integer
/* Byte Mask Definitions */
#define BYTE0_Msk (0x000000FFUL) ///< Mask to get bit0~bit7 from a 32 bit integer
#define BYTE1_Msk (0x0000FF00UL) ///< Mask to get bit8~bit15 from a 32 bit integer
#define BYTE2_Msk (0x00FF0000UL) ///< Mask to get bit16~bit23 from a 32 bit integer
#define BYTE3_Msk (0xFF000000UL) ///< Mask to get bit24~bit31 from a 32 bit integer
#define GET_BYTE0(u32Param) (((u32Param) & BYTE0_Msk) ) /*!< Extract Byte 0 (Bit 0~ 7) from parameter u32Param */
#define GET_BYTE1(u32Param) (((u32Param) & BYTE1_Msk) >> 8) /*!< Extract Byte 1 (Bit 8~15) from parameter u32Param */
#define GET_BYTE2(u32Param) (((u32Param) & BYTE2_Msk) >> 16) /*!< Extract Byte 2 (Bit 16~23) from parameter u32Param */
#define GET_BYTE3(u32Param) (((u32Param) & BYTE3_Msk) >> 24) /*!< Extract Byte 3 (Bit 24~31) from parameter u32Param */
/*@}*/ /* end of group M480_legacy_Constants */
/******************************************************************************/
/* Peripheral header files */
/******************************************************************************/
#include "m480_sys.h"
#include "m480_clk.h"
#include "m480_acmp.h"
#include "m480_dac.h"
#include "m480_emac.h"
#include "m480_uart.h"
#include "m480_usci_spi.h"
#include "m480_gpio.h"
#include "m480_ecap.h"
#include "m480_qei.h"
#include "m480_timer.h"
#include "m480_timer_pwm.h"
#include "m480_pdma.h"
#include "m480_crypto.h"
#include "m480_fmc.h"
#include "m480_spim.h"
#include "m480_i2c.h"
#include "m480_i2s.h"
#include "m480_epwm.h"
#include "m480_eadc.h"
#include "m480_bpwm.h"
#include "m480_wdt.h"
#include "m480_wwdt.h"
#include "m480_opa.h"
#include "m480_crc.h"
#include "m480_ebi.h"
#include "m480_usci_i2c.h"
#include "m480_scuart.h"
#include "m480_sc.h"
#include "m480_spi.h"
#include "m480_can.h"
#include "m480_rtc.h"
#include "m480_usci_uart.h"
#include "m480_sdh.h"
#include "m480_usbd.h"
#include "m480_hsusbd.h"
#include "m480_otg.h"
#include "m480_hsotg.h"
#ifdef __cplusplus
}
#endif
#endif /* __M480_H__ */
/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/