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targets/TARGET_NUVOTON/TARGET_NANO100/lp_ticker.c@175:b96e65c34a4d, 2017-10-02 (annotated)

Committer:
AnnaBridge
Date:
Mon Oct 02 15:33:19 2017 +0100
Revision:
175:b96e65c34a4d
Child:
177:447f873cad2f
This updates the lib to the mbed lib v 152

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 175:b96e65c34a4d 1 /* mbed Microcontroller Library
AnnaBridge 175:b96e65c34a4d 2 * Copyright (c) 2015-2017 Nuvoton
AnnaBridge 175:b96e65c34a4d 3 *
AnnaBridge 175:b96e65c34a4d 4 * Licensed under the Apache License, Version 2.0 (the "License");
AnnaBridge 175:b96e65c34a4d 5 * you may not use this file except in compliance with the License.
AnnaBridge 175:b96e65c34a4d 6 * You may obtain a copy of the License at
AnnaBridge 175:b96e65c34a4d 7 *
AnnaBridge 175:b96e65c34a4d 8 * http://www.apache.org/licenses/LICENSE-2.0
AnnaBridge 175:b96e65c34a4d 9 *
AnnaBridge 175:b96e65c34a4d 10 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 175:b96e65c34a4d 11 * distributed under the License is distributed on an "AS IS" BASIS,
AnnaBridge 175:b96e65c34a4d 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 175:b96e65c34a4d 13 * See the License for the specific language governing permissions and
AnnaBridge 175:b96e65c34a4d 14 * limitations under the License.
AnnaBridge 175:b96e65c34a4d 15 */
AnnaBridge 175:b96e65c34a4d 16
AnnaBridge 175:b96e65c34a4d 17 #include "lp_ticker_api.h"
AnnaBridge 175:b96e65c34a4d 18
AnnaBridge 175:b96e65c34a4d 19 #if DEVICE_LOWPOWERTIMER
AnnaBridge 175:b96e65c34a4d 20
AnnaBridge 175:b96e65c34a4d 21 #include "sleep_api.h"
AnnaBridge 175:b96e65c34a4d 22 #include "nu_modutil.h"
AnnaBridge 175:b96e65c34a4d 23 #include "nu_miscutil.h"
AnnaBridge 175:b96e65c34a4d 24 #include "mbed_critical.h"
AnnaBridge 175:b96e65c34a4d 25 #include "mbed_wait_api.h"
AnnaBridge 175:b96e65c34a4d 26
AnnaBridge 175:b96e65c34a4d 27 // lp_ticker tick = us = timestamp
AnnaBridge 175:b96e65c34a4d 28 #define US_PER_TICK (1)
AnnaBridge 175:b96e65c34a4d 29 #define US_PER_SEC (1000 * 1000)
AnnaBridge 175:b96e65c34a4d 30
AnnaBridge 175:b96e65c34a4d 31 #define US_PER_TMR2_INT (US_PER_SEC * 10)
AnnaBridge 175:b96e65c34a4d 32 #define TMR2_CLK_PER_SEC (__LXT)
AnnaBridge 175:b96e65c34a4d 33 #define TMR2_CLK_PER_TMR2_INT ((uint32_t) ((uint64_t) US_PER_TMR2_INT * TMR2_CLK_PER_SEC / US_PER_SEC))
AnnaBridge 175:b96e65c34a4d 34 #define TMR3_CLK_PER_SEC (__LXT)
AnnaBridge 175:b96e65c34a4d 35
AnnaBridge 175:b96e65c34a4d 36 void TMR2_IRQHandler(void);
AnnaBridge 175:b96e65c34a4d 37 void TMR3_IRQHandler(void);
AnnaBridge 175:b96e65c34a4d 38 static void lp_ticker_arm_cd(void);
AnnaBridge 175:b96e65c34a4d 39
AnnaBridge 175:b96e65c34a4d 40 static int lp_ticker_inited = 0;
AnnaBridge 175:b96e65c34a4d 41 static volatile uint32_t counter_major = 0;
AnnaBridge 175:b96e65c34a4d 42 static volatile uint32_t cd_major_minor_clks = 0;
AnnaBridge 175:b96e65c34a4d 43 static volatile uint32_t cd_minor_clks = 0;
AnnaBridge 175:b96e65c34a4d 44 static volatile uint32_t wakeup_tick = (uint32_t) -1;
AnnaBridge 175:b96e65c34a4d 45
AnnaBridge 175:b96e65c34a4d 46 // NOTE: To wake the system from power down mode, timer clock source must be ether LXT or LIRC.
AnnaBridge 175:b96e65c34a4d 47 // NOTE: TIMER_2 for normal counting and TIMER_3 for scheduled wakeup
AnnaBridge 175:b96e65c34a4d 48 static const struct nu_modinit_s timer2_modinit = {TIMER_2, TMR2_MODULE, CLK_CLKSEL2_TMR2_S_LXT, 0, TMR2_RST, TMR2_IRQn, (void *) TMR2_IRQHandler};
AnnaBridge 175:b96e65c34a4d 49 static const struct nu_modinit_s timer3_modinit = {TIMER_3, TMR3_MODULE, CLK_CLKSEL2_TMR3_S_LXT, 0, TMR3_RST, TMR3_IRQn, (void *) TMR3_IRQHandler};
AnnaBridge 175:b96e65c34a4d 50
AnnaBridge 175:b96e65c34a4d 51 #define TMR_CMP_MIN 2
AnnaBridge 175:b96e65c34a4d 52 #define TMR_CMP_MAX 0xFFFFFFu
AnnaBridge 175:b96e65c34a4d 53
AnnaBridge 175:b96e65c34a4d 54 void lp_ticker_init(void)
AnnaBridge 175:b96e65c34a4d 55 {
AnnaBridge 175:b96e65c34a4d 56 if (lp_ticker_inited) {
AnnaBridge 175:b96e65c34a4d 57 return;
AnnaBridge 175:b96e65c34a4d 58 }
AnnaBridge 175:b96e65c34a4d 59 lp_ticker_inited = 1;
AnnaBridge 175:b96e65c34a4d 60
AnnaBridge 175:b96e65c34a4d 61 counter_major = 0;
AnnaBridge 175:b96e65c34a4d 62 cd_major_minor_clks = 0;
AnnaBridge 175:b96e65c34a4d 63 cd_minor_clks = 0;
AnnaBridge 175:b96e65c34a4d 64 wakeup_tick = (uint32_t) -1;
AnnaBridge 175:b96e65c34a4d 65
AnnaBridge 175:b96e65c34a4d 66 // Reset module
AnnaBridge 175:b96e65c34a4d 67 SYS_ResetModule(timer2_modinit.rsetidx);
AnnaBridge 175:b96e65c34a4d 68 SYS_ResetModule(timer3_modinit.rsetidx);
AnnaBridge 175:b96e65c34a4d 69
AnnaBridge 175:b96e65c34a4d 70 // Select IP clock source
AnnaBridge 175:b96e65c34a4d 71 CLK_SetModuleClock(timer2_modinit.clkidx, timer2_modinit.clksrc, timer2_modinit.clkdiv);
AnnaBridge 175:b96e65c34a4d 72 CLK_SetModuleClock(timer3_modinit.clkidx, timer3_modinit.clksrc, timer3_modinit.clkdiv);
AnnaBridge 175:b96e65c34a4d 73 // Enable IP clock
AnnaBridge 175:b96e65c34a4d 74 CLK_EnableModuleClock(timer2_modinit.clkidx);
AnnaBridge 175:b96e65c34a4d 75 CLK_EnableModuleClock(timer3_modinit.clkidx);
AnnaBridge 175:b96e65c34a4d 76
AnnaBridge 175:b96e65c34a4d 77 // Configure clock
AnnaBridge 175:b96e65c34a4d 78 uint32_t clk_timer2 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
AnnaBridge 175:b96e65c34a4d 79 uint32_t prescale_timer2 = clk_timer2 / TMR2_CLK_PER_SEC - 1;
AnnaBridge 175:b96e65c34a4d 80 MBED_ASSERT((prescale_timer2 != (uint32_t) -1) && prescale_timer2 <= 127);
AnnaBridge 175:b96e65c34a4d 81 MBED_ASSERT((clk_timer2 % TMR2_CLK_PER_SEC) == 0);
AnnaBridge 175:b96e65c34a4d 82 uint32_t cmp_timer2 = TMR2_CLK_PER_TMR2_INT;
AnnaBridge 175:b96e65c34a4d 83 MBED_ASSERT(cmp_timer2 >= TMR_CMP_MIN && cmp_timer2 <= TMR_CMP_MAX);
AnnaBridge 175:b96e65c34a4d 84 // Continuous mode
AnnaBridge 175:b96e65c34a4d 85 ((TIMER_T *) NU_MODBASE(timer2_modinit.modname))->CTL = TIMER_PERIODIC_MODE;
AnnaBridge 175:b96e65c34a4d 86 ((TIMER_T *) NU_MODBASE(timer2_modinit.modname))->PRECNT = prescale_timer2;
AnnaBridge 175:b96e65c34a4d 87 ((TIMER_T *) NU_MODBASE(timer2_modinit.modname))->CMPR = cmp_timer2;
AnnaBridge 175:b96e65c34a4d 88
AnnaBridge 175:b96e65c34a4d 89 // Set vector
AnnaBridge 175:b96e65c34a4d 90 NVIC_SetVector(timer2_modinit.irq_n, (uint32_t) timer2_modinit.var);
AnnaBridge 175:b96e65c34a4d 91 NVIC_SetVector(timer3_modinit.irq_n, (uint32_t) timer3_modinit.var);
AnnaBridge 175:b96e65c34a4d 92
AnnaBridge 175:b96e65c34a4d 93 NVIC_EnableIRQ(timer2_modinit.irq_n);
AnnaBridge 175:b96e65c34a4d 94 NVIC_EnableIRQ(timer3_modinit.irq_n);
AnnaBridge 175:b96e65c34a4d 95
AnnaBridge 175:b96e65c34a4d 96 TIMER_EnableInt((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
AnnaBridge 175:b96e65c34a4d 97 TIMER_EnableWakeup((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
AnnaBridge 175:b96e65c34a4d 98
AnnaBridge 175:b96e65c34a4d 99 // NOTE: TIMER_Start() first and then lp_ticker_set_interrupt(); otherwise, we may get stuck in lp_ticker_read() because
AnnaBridge 175:b96e65c34a4d 100 // timer is not running.
AnnaBridge 175:b96e65c34a4d 101
AnnaBridge 175:b96e65c34a4d 102 // Wait 3 cycles of engine clock to ensure previous CTL write action is finish
AnnaBridge 175:b96e65c34a4d 103 nu_nop(SystemCoreClock / __LXT * 3);
AnnaBridge 175:b96e65c34a4d 104 // Start timer
AnnaBridge 175:b96e65c34a4d 105 TIMER_Start((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
AnnaBridge 175:b96e65c34a4d 106
AnnaBridge 175:b96e65c34a4d 107 // Schedule wakeup to match semantics of lp_ticker_get_compare_match()
AnnaBridge 175:b96e65c34a4d 108 lp_ticker_set_interrupt(wakeup_tick);
AnnaBridge 175:b96e65c34a4d 109 }
AnnaBridge 175:b96e65c34a4d 110
AnnaBridge 175:b96e65c34a4d 111 timestamp_t lp_ticker_read()
AnnaBridge 175:b96e65c34a4d 112 {
AnnaBridge 175:b96e65c34a4d 113 if (! lp_ticker_inited) {
AnnaBridge 175:b96e65c34a4d 114 lp_ticker_init();
AnnaBridge 175:b96e65c34a4d 115 }
AnnaBridge 175:b96e65c34a4d 116
AnnaBridge 175:b96e65c34a4d 117 TIMER_T * timer2_base = (TIMER_T *) NU_MODBASE(timer2_modinit.modname);
AnnaBridge 175:b96e65c34a4d 118
AnnaBridge 175:b96e65c34a4d 119 do {
AnnaBridge 175:b96e65c34a4d 120 uint64_t major_minor_clks;
AnnaBridge 175:b96e65c34a4d 121 uint32_t minor_clks;
AnnaBridge 175:b96e65c34a4d 122
AnnaBridge 175:b96e65c34a4d 123 // NOTE: As TIMER_DR = TIMER_CMPR and counter_major has increased by one, TIMER_DR doesn't change to 0 for one tick time.
AnnaBridge 175:b96e65c34a4d 124 // NOTE: As TIMER_DR = TIMER_CMPR or TIMER_DR = 0, counter_major (ISR) may not sync with TIMER_DR. So skip and fetch stable one at the cost of 1 clock delay on this read.
AnnaBridge 175:b96e65c34a4d 125 do {
AnnaBridge 175:b96e65c34a4d 126 core_util_critical_section_enter();
AnnaBridge 175:b96e65c34a4d 127
AnnaBridge 175:b96e65c34a4d 128 // NOTE: Order of reading minor_us/carry here is significant.
AnnaBridge 175:b96e65c34a4d 129 minor_clks = TIMER_GetCounter(timer2_base);
AnnaBridge 175:b96e65c34a4d 130 uint32_t carry = (timer2_base->ISR & TIMER_ISR_TMR_IS_Msk) ? 1 : 0;
AnnaBridge 175:b96e65c34a4d 131 // When TIMER_DR approaches TIMER_CMPR and will wrap soon, we may get carry but TIMER_DR not wrapped. Hanlde carefully carry == 1 && TIMER_DR is near TIMER_CMPR.
AnnaBridge 175:b96e65c34a4d 132 if (carry && minor_clks > (TMR2_CLK_PER_TMR2_INT / 2)) {
AnnaBridge 175:b96e65c34a4d 133 major_minor_clks = (counter_major + 1) * TMR2_CLK_PER_TMR2_INT;
AnnaBridge 175:b96e65c34a4d 134 }
AnnaBridge 175:b96e65c34a4d 135 else {
AnnaBridge 175:b96e65c34a4d 136 major_minor_clks = (counter_major + carry) * TMR2_CLK_PER_TMR2_INT + minor_clks;
AnnaBridge 175:b96e65c34a4d 137 }
AnnaBridge 175:b96e65c34a4d 138
AnnaBridge 175:b96e65c34a4d 139 core_util_critical_section_exit();
AnnaBridge 175:b96e65c34a4d 140 }
AnnaBridge 175:b96e65c34a4d 141 while (minor_clks == 0 || minor_clks == TMR2_CLK_PER_TMR2_INT);
AnnaBridge 175:b96e65c34a4d 142
AnnaBridge 175:b96e65c34a4d 143 // Add power-down compensation
AnnaBridge 175:b96e65c34a4d 144 return ((uint64_t) major_minor_clks * US_PER_SEC / TMR3_CLK_PER_SEC / US_PER_TICK);
AnnaBridge 175:b96e65c34a4d 145 }
AnnaBridge 175:b96e65c34a4d 146 while (0);
AnnaBridge 175:b96e65c34a4d 147 }
AnnaBridge 175:b96e65c34a4d 148
AnnaBridge 175:b96e65c34a4d 149 void lp_ticker_set_interrupt(timestamp_t timestamp)
AnnaBridge 175:b96e65c34a4d 150 {
AnnaBridge 175:b96e65c34a4d 151 uint32_t delta = timestamp - lp_ticker_read();
AnnaBridge 175:b96e65c34a4d 152 wakeup_tick = timestamp;
AnnaBridge 175:b96e65c34a4d 153
AnnaBridge 175:b96e65c34a4d 154 TIMER_Stop((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
AnnaBridge 175:b96e65c34a4d 155 cd_major_minor_clks = (uint64_t) delta * US_PER_TICK * TMR3_CLK_PER_SEC / US_PER_SEC;
AnnaBridge 175:b96e65c34a4d 156 lp_ticker_arm_cd();
AnnaBridge 175:b96e65c34a4d 157
AnnaBridge 175:b96e65c34a4d 158 }
AnnaBridge 175:b96e65c34a4d 159
AnnaBridge 175:b96e65c34a4d 160 void lp_ticker_fire_interrupt(void)
AnnaBridge 175:b96e65c34a4d 161 {
AnnaBridge 175:b96e65c34a4d 162 cd_major_minor_clks = cd_minor_clks = 0;
AnnaBridge 175:b96e65c34a4d 163 /**
AnnaBridge 175:b96e65c34a4d 164 * This event was in the past. Set the interrupt as pending, but don't process it here.
AnnaBridge 175:b96e65c34a4d 165 * This prevents a recurive loop under heavy load which can lead to a stack overflow.
AnnaBridge 175:b96e65c34a4d 166 */
AnnaBridge 175:b96e65c34a4d 167 NVIC_SetPendingIRQ(timer3_modinit.irq_n);
AnnaBridge 175:b96e65c34a4d 168 }
AnnaBridge 175:b96e65c34a4d 169
AnnaBridge 175:b96e65c34a4d 170 void lp_ticker_disable_interrupt(void)
AnnaBridge 175:b96e65c34a4d 171 {
AnnaBridge 175:b96e65c34a4d 172 TIMER_DisableInt((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
AnnaBridge 175:b96e65c34a4d 173 }
AnnaBridge 175:b96e65c34a4d 174
AnnaBridge 175:b96e65c34a4d 175 void lp_ticker_clear_interrupt(void)
AnnaBridge 175:b96e65c34a4d 176 {
AnnaBridge 175:b96e65c34a4d 177 TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
AnnaBridge 175:b96e65c34a4d 178 }
AnnaBridge 175:b96e65c34a4d 179
AnnaBridge 175:b96e65c34a4d 180 void TMR2_IRQHandler(void)
AnnaBridge 175:b96e65c34a4d 181 {
AnnaBridge 175:b96e65c34a4d 182 TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
AnnaBridge 175:b96e65c34a4d 183 TIMER_ClearWakeupFlag((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
AnnaBridge 175:b96e65c34a4d 184 counter_major ++;
AnnaBridge 175:b96e65c34a4d 185 }
AnnaBridge 175:b96e65c34a4d 186
AnnaBridge 175:b96e65c34a4d 187 void TMR3_IRQHandler(void)
AnnaBridge 175:b96e65c34a4d 188 {
AnnaBridge 175:b96e65c34a4d 189 TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
AnnaBridge 175:b96e65c34a4d 190 TIMER_ClearWakeupFlag((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
AnnaBridge 175:b96e65c34a4d 191 cd_major_minor_clks = (cd_major_minor_clks > cd_minor_clks) ? (cd_major_minor_clks - cd_minor_clks) : 0;
AnnaBridge 175:b96e65c34a4d 192 if (cd_major_minor_clks == 0) {
AnnaBridge 175:b96e65c34a4d 193 // NOTE: lp_ticker_set_interrupt() may get called in lp_ticker_irq_handler();
AnnaBridge 175:b96e65c34a4d 194 lp_ticker_irq_handler();
AnnaBridge 175:b96e65c34a4d 195 }
AnnaBridge 175:b96e65c34a4d 196 else {
AnnaBridge 175:b96e65c34a4d 197 lp_ticker_arm_cd();
AnnaBridge 175:b96e65c34a4d 198 }
AnnaBridge 175:b96e65c34a4d 199 }
AnnaBridge 175:b96e65c34a4d 200
AnnaBridge 175:b96e65c34a4d 201 static void lp_ticker_arm_cd(void)
AnnaBridge 175:b96e65c34a4d 202 {
AnnaBridge 175:b96e65c34a4d 203 TIMER_T * timer3_base = (TIMER_T *) NU_MODBASE(timer3_modinit.modname);
AnnaBridge 175:b96e65c34a4d 204
AnnaBridge 175:b96e65c34a4d 205 // Reset Timer's pre-scale counter, internal 24-bit up-counter and TMR_CTL [TMR_EN] bit
AnnaBridge 175:b96e65c34a4d 206 timer3_base->CTL |= TIMER_CTL_SW_RST_Msk;
AnnaBridge 175:b96e65c34a4d 207 // One-shot mode, Clock = 1 KHz
AnnaBridge 175:b96e65c34a4d 208 uint32_t clk_timer3 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
AnnaBridge 175:b96e65c34a4d 209 uint32_t prescale_timer3 = clk_timer3 / TMR3_CLK_PER_SEC - 1;
AnnaBridge 175:b96e65c34a4d 210 MBED_ASSERT((prescale_timer3 != (uint32_t) -1) && prescale_timer3 <= 127);
AnnaBridge 175:b96e65c34a4d 211 MBED_ASSERT((clk_timer3 % TMR3_CLK_PER_SEC) == 0);
AnnaBridge 175:b96e65c34a4d 212 uint32_t ctl_timer3 = timer3_base->CTL;
AnnaBridge 175:b96e65c34a4d 213 ctl_timer3 &= ~TIMER_CTL_MODE_SEL_Msk;
AnnaBridge 175:b96e65c34a4d 214 ctl_timer3 |= TIMER_ONESHOT_MODE;
AnnaBridge 175:b96e65c34a4d 215 timer3_base->PRECNT = prescale_timer3;
AnnaBridge 175:b96e65c34a4d 216
AnnaBridge 175:b96e65c34a4d 217 cd_minor_clks = cd_major_minor_clks;
AnnaBridge 175:b96e65c34a4d 218 cd_minor_clks = NU_CLAMP(cd_minor_clks, TMR_CMP_MIN, TMR_CMP_MAX);
AnnaBridge 175:b96e65c34a4d 219 timer3_base->CMPR = cd_minor_clks;
AnnaBridge 175:b96e65c34a4d 220
AnnaBridge 175:b96e65c34a4d 221 TIMER_EnableInt(timer3_base);
AnnaBridge 175:b96e65c34a4d 222 TIMER_EnableWakeup((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
AnnaBridge 175:b96e65c34a4d 223 // Wait 2 cycles of engine clock to ensure previous CTL write action is finish
AnnaBridge 175:b96e65c34a4d 224 wait_us(30 * 2);
AnnaBridge 175:b96e65c34a4d 225 timer3_base->CTL = ctl_timer3 | TIMER_CTL_TMR_EN_Msk;
AnnaBridge 175:b96e65c34a4d 226 }
AnnaBridge 175:b96e65c34a4d 227 #endif