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targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_pm.h@15:a81a8d6c1dfe, 2015-11-04 (annotated)

Committer:
mbed_official
Date:
Wed Nov 04 16:30:11 2015 +0000
Revision:
15:a81a8d6c1dfe
Synchronized with git revision 46af745ef4405614c3fa49abbd9a706a362ea514



Full URL: https://github.com/mbedmicro/mbed/commit/46af745ef4405614c3fa49abbd9a706a362ea514/



Renamed TARGET_SAM_CortexM0+ to TARGET_SAM_CortexM0P for compatiblity with online compiler

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 15:a81a8d6c1dfe 1 /**
mbed_official 15:a81a8d6c1dfe 2 * \file
mbed_official 15:a81a8d6c1dfe 3 *
mbed_official 15:a81a8d6c1dfe 4 * \brief Component description for PM
mbed_official 15:a81a8d6c1dfe 5 *
mbed_official 15:a81a8d6c1dfe 6 * Copyright (c) 2015 Atmel Corporation. All rights reserved.
mbed_official 15:a81a8d6c1dfe 7 *
mbed_official 15:a81a8d6c1dfe 8 * \asf_license_start
mbed_official 15:a81a8d6c1dfe 9 *
mbed_official 15:a81a8d6c1dfe 10 * \page License
mbed_official 15:a81a8d6c1dfe 11 *
mbed_official 15:a81a8d6c1dfe 12 * Redistribution and use in source and binary forms, with or without
mbed_official 15:a81a8d6c1dfe 13 * modification, are permitted provided that the following conditions are met:
mbed_official 15:a81a8d6c1dfe 14 *
mbed_official 15:a81a8d6c1dfe 15 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 15:a81a8d6c1dfe 16 * this list of conditions and the following disclaimer.
mbed_official 15:a81a8d6c1dfe 17 *
mbed_official 15:a81a8d6c1dfe 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 15:a81a8d6c1dfe 19 * this list of conditions and the following disclaimer in the documentation
mbed_official 15:a81a8d6c1dfe 20 * and/or other materials provided with the distribution.
mbed_official 15:a81a8d6c1dfe 21 *
mbed_official 15:a81a8d6c1dfe 22 * 3. The name of Atmel may not be used to endorse or promote products derived
mbed_official 15:a81a8d6c1dfe 23 * from this software without specific prior written permission.
mbed_official 15:a81a8d6c1dfe 24 *
mbed_official 15:a81a8d6c1dfe 25 * 4. This software may only be redistributed and used in connection with an
mbed_official 15:a81a8d6c1dfe 26 * Atmel microcontroller product.
mbed_official 15:a81a8d6c1dfe 27 *
mbed_official 15:a81a8d6c1dfe 28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
mbed_official 15:a81a8d6c1dfe 29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
mbed_official 15:a81a8d6c1dfe 30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
mbed_official 15:a81a8d6c1dfe 31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
mbed_official 15:a81a8d6c1dfe 32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 15:a81a8d6c1dfe 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
mbed_official 15:a81a8d6c1dfe 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
mbed_official 15:a81a8d6c1dfe 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
mbed_official 15:a81a8d6c1dfe 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
mbed_official 15:a81a8d6c1dfe 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
mbed_official 15:a81a8d6c1dfe 38 * POSSIBILITY OF SUCH DAMAGE.
mbed_official 15:a81a8d6c1dfe 39 *
mbed_official 15:a81a8d6c1dfe 40 * \asf_license_stop
mbed_official 15:a81a8d6c1dfe 41 *
mbed_official 15:a81a8d6c1dfe 42 */
mbed_official 15:a81a8d6c1dfe 43
mbed_official 15:a81a8d6c1dfe 44 #ifndef _SAMR21_PM_COMPONENT_
mbed_official 15:a81a8d6c1dfe 45 #define _SAMR21_PM_COMPONENT_
mbed_official 15:a81a8d6c1dfe 46
mbed_official 15:a81a8d6c1dfe 47 /* ========================================================================== */
mbed_official 15:a81a8d6c1dfe 48 /** SOFTWARE API DEFINITION FOR PM */
mbed_official 15:a81a8d6c1dfe 49 /* ========================================================================== */
mbed_official 15:a81a8d6c1dfe 50 /** \addtogroup SAMR21_PM Power Manager */
mbed_official 15:a81a8d6c1dfe 51 /*@{*/
mbed_official 15:a81a8d6c1dfe 52
mbed_official 15:a81a8d6c1dfe 53 #define PM_U2206
mbed_official 15:a81a8d6c1dfe 54 #define REV_PM 0x201
mbed_official 15:a81a8d6c1dfe 55
mbed_official 15:a81a8d6c1dfe 56 /* -------- PM_CTRL : (PM Offset: 0x00) (R/W 8) Control -------- */
mbed_official 15:a81a8d6c1dfe 57 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 58 typedef union {
mbed_official 15:a81a8d6c1dfe 59 uint8_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 60 } PM_CTRL_Type;
mbed_official 15:a81a8d6c1dfe 61 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 62
mbed_official 15:a81a8d6c1dfe 63 #define PM_CTRL_OFFSET 0x00 /**< \brief (PM_CTRL offset) Control */
mbed_official 15:a81a8d6c1dfe 64 #define PM_CTRL_RESETVALUE 0x00ul /**< \brief (PM_CTRL reset_value) Control */
mbed_official 15:a81a8d6c1dfe 65
mbed_official 15:a81a8d6c1dfe 66 #define PM_CTRL_MASK 0x00ul /**< \brief (PM_CTRL) MASK Register */
mbed_official 15:a81a8d6c1dfe 67
mbed_official 15:a81a8d6c1dfe 68 /* -------- PM_SLEEP : (PM Offset: 0x01) (R/W 8) Sleep Mode -------- */
mbed_official 15:a81a8d6c1dfe 69 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 70 typedef union {
mbed_official 15:a81a8d6c1dfe 71 struct {
mbed_official 15:a81a8d6c1dfe 72 uint8_t IDLE:2; /*!< bit: 0.. 1 Idle Mode Configuration */
mbed_official 15:a81a8d6c1dfe 73 uint8_t :6; /*!< bit: 2.. 7 Reserved */
mbed_official 15:a81a8d6c1dfe 74 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 75 uint8_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 76 } PM_SLEEP_Type;
mbed_official 15:a81a8d6c1dfe 77 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 78
mbed_official 15:a81a8d6c1dfe 79 #define PM_SLEEP_OFFSET 0x01 /**< \brief (PM_SLEEP offset) Sleep Mode */
mbed_official 15:a81a8d6c1dfe 80 #define PM_SLEEP_RESETVALUE 0x00ul /**< \brief (PM_SLEEP reset_value) Sleep Mode */
mbed_official 15:a81a8d6c1dfe 81
mbed_official 15:a81a8d6c1dfe 82 #define PM_SLEEP_IDLE_Pos 0 /**< \brief (PM_SLEEP) Idle Mode Configuration */
mbed_official 15:a81a8d6c1dfe 83 #define PM_SLEEP_IDLE_Msk (0x3ul << PM_SLEEP_IDLE_Pos)
mbed_official 15:a81a8d6c1dfe 84 #define PM_SLEEP_IDLE(value) (PM_SLEEP_IDLE_Msk & ((value) << PM_SLEEP_IDLE_Pos))
mbed_official 15:a81a8d6c1dfe 85 #define PM_SLEEP_IDLE_CPU_Val 0x0ul /**< \brief (PM_SLEEP) The CPU clock domain is stopped */
mbed_official 15:a81a8d6c1dfe 86 #define PM_SLEEP_IDLE_AHB_Val 0x1ul /**< \brief (PM_SLEEP) The CPU and AHB clock domains are stopped */
mbed_official 15:a81a8d6c1dfe 87 #define PM_SLEEP_IDLE_APB_Val 0x2ul /**< \brief (PM_SLEEP) The CPU, AHB and APB clock domains are stopped */
mbed_official 15:a81a8d6c1dfe 88 #define PM_SLEEP_IDLE_CPU (PM_SLEEP_IDLE_CPU_Val << PM_SLEEP_IDLE_Pos)
mbed_official 15:a81a8d6c1dfe 89 #define PM_SLEEP_IDLE_AHB (PM_SLEEP_IDLE_AHB_Val << PM_SLEEP_IDLE_Pos)
mbed_official 15:a81a8d6c1dfe 90 #define PM_SLEEP_IDLE_APB (PM_SLEEP_IDLE_APB_Val << PM_SLEEP_IDLE_Pos)
mbed_official 15:a81a8d6c1dfe 91 #define PM_SLEEP_MASK 0x03ul /**< \brief (PM_SLEEP) MASK Register */
mbed_official 15:a81a8d6c1dfe 92
mbed_official 15:a81a8d6c1dfe 93 /* -------- PM_CPUSEL : (PM Offset: 0x08) (R/W 8) CPU Clock Select -------- */
mbed_official 15:a81a8d6c1dfe 94 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 95 typedef union {
mbed_official 15:a81a8d6c1dfe 96 struct {
mbed_official 15:a81a8d6c1dfe 97 uint8_t CPUDIV:3; /*!< bit: 0.. 2 CPU Prescaler Selection */
mbed_official 15:a81a8d6c1dfe 98 uint8_t :5; /*!< bit: 3.. 7 Reserved */
mbed_official 15:a81a8d6c1dfe 99 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 100 uint8_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 101 } PM_CPUSEL_Type;
mbed_official 15:a81a8d6c1dfe 102 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 103
mbed_official 15:a81a8d6c1dfe 104 #define PM_CPUSEL_OFFSET 0x08 /**< \brief (PM_CPUSEL offset) CPU Clock Select */
mbed_official 15:a81a8d6c1dfe 105 #define PM_CPUSEL_RESETVALUE 0x00ul /**< \brief (PM_CPUSEL reset_value) CPU Clock Select */
mbed_official 15:a81a8d6c1dfe 106
mbed_official 15:a81a8d6c1dfe 107 #define PM_CPUSEL_CPUDIV_Pos 0 /**< \brief (PM_CPUSEL) CPU Prescaler Selection */
mbed_official 15:a81a8d6c1dfe 108 #define PM_CPUSEL_CPUDIV_Msk (0x7ul << PM_CPUSEL_CPUDIV_Pos)
mbed_official 15:a81a8d6c1dfe 109 #define PM_CPUSEL_CPUDIV(value) (PM_CPUSEL_CPUDIV_Msk & ((value) << PM_CPUSEL_CPUDIV_Pos))
mbed_official 15:a81a8d6c1dfe 110 #define PM_CPUSEL_CPUDIV_DIV1_Val 0x0ul /**< \brief (PM_CPUSEL) Divide by 1 */
mbed_official 15:a81a8d6c1dfe 111 #define PM_CPUSEL_CPUDIV_DIV2_Val 0x1ul /**< \brief (PM_CPUSEL) Divide by 2 */
mbed_official 15:a81a8d6c1dfe 112 #define PM_CPUSEL_CPUDIV_DIV4_Val 0x2ul /**< \brief (PM_CPUSEL) Divide by 4 */
mbed_official 15:a81a8d6c1dfe 113 #define PM_CPUSEL_CPUDIV_DIV8_Val 0x3ul /**< \brief (PM_CPUSEL) Divide by 8 */
mbed_official 15:a81a8d6c1dfe 114 #define PM_CPUSEL_CPUDIV_DIV16_Val 0x4ul /**< \brief (PM_CPUSEL) Divide by 16 */
mbed_official 15:a81a8d6c1dfe 115 #define PM_CPUSEL_CPUDIV_DIV32_Val 0x5ul /**< \brief (PM_CPUSEL) Divide by 32 */
mbed_official 15:a81a8d6c1dfe 116 #define PM_CPUSEL_CPUDIV_DIV64_Val 0x6ul /**< \brief (PM_CPUSEL) Divide by 64 */
mbed_official 15:a81a8d6c1dfe 117 #define PM_CPUSEL_CPUDIV_DIV128_Val 0x7ul /**< \brief (PM_CPUSEL) Divide by 128 */
mbed_official 15:a81a8d6c1dfe 118 #define PM_CPUSEL_CPUDIV_DIV1 (PM_CPUSEL_CPUDIV_DIV1_Val << PM_CPUSEL_CPUDIV_Pos)
mbed_official 15:a81a8d6c1dfe 119 #define PM_CPUSEL_CPUDIV_DIV2 (PM_CPUSEL_CPUDIV_DIV2_Val << PM_CPUSEL_CPUDIV_Pos)
mbed_official 15:a81a8d6c1dfe 120 #define PM_CPUSEL_CPUDIV_DIV4 (PM_CPUSEL_CPUDIV_DIV4_Val << PM_CPUSEL_CPUDIV_Pos)
mbed_official 15:a81a8d6c1dfe 121 #define PM_CPUSEL_CPUDIV_DIV8 (PM_CPUSEL_CPUDIV_DIV8_Val << PM_CPUSEL_CPUDIV_Pos)
mbed_official 15:a81a8d6c1dfe 122 #define PM_CPUSEL_CPUDIV_DIV16 (PM_CPUSEL_CPUDIV_DIV16_Val << PM_CPUSEL_CPUDIV_Pos)
mbed_official 15:a81a8d6c1dfe 123 #define PM_CPUSEL_CPUDIV_DIV32 (PM_CPUSEL_CPUDIV_DIV32_Val << PM_CPUSEL_CPUDIV_Pos)
mbed_official 15:a81a8d6c1dfe 124 #define PM_CPUSEL_CPUDIV_DIV64 (PM_CPUSEL_CPUDIV_DIV64_Val << PM_CPUSEL_CPUDIV_Pos)
mbed_official 15:a81a8d6c1dfe 125 #define PM_CPUSEL_CPUDIV_DIV128 (PM_CPUSEL_CPUDIV_DIV128_Val << PM_CPUSEL_CPUDIV_Pos)
mbed_official 15:a81a8d6c1dfe 126 #define PM_CPUSEL_MASK 0x07ul /**< \brief (PM_CPUSEL) MASK Register */
mbed_official 15:a81a8d6c1dfe 127
mbed_official 15:a81a8d6c1dfe 128 /* -------- PM_APBASEL : (PM Offset: 0x09) (R/W 8) APBA Clock Select -------- */
mbed_official 15:a81a8d6c1dfe 129 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 130 typedef union {
mbed_official 15:a81a8d6c1dfe 131 struct {
mbed_official 15:a81a8d6c1dfe 132 uint8_t APBADIV:3; /*!< bit: 0.. 2 APBA Prescaler Selection */
mbed_official 15:a81a8d6c1dfe 133 uint8_t :5; /*!< bit: 3.. 7 Reserved */
mbed_official 15:a81a8d6c1dfe 134 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 135 uint8_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 136 } PM_APBASEL_Type;
mbed_official 15:a81a8d6c1dfe 137 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 138
mbed_official 15:a81a8d6c1dfe 139 #define PM_APBASEL_OFFSET 0x09 /**< \brief (PM_APBASEL offset) APBA Clock Select */
mbed_official 15:a81a8d6c1dfe 140 #define PM_APBASEL_RESETVALUE 0x00ul /**< \brief (PM_APBASEL reset_value) APBA Clock Select */
mbed_official 15:a81a8d6c1dfe 141
mbed_official 15:a81a8d6c1dfe 142 #define PM_APBASEL_APBADIV_Pos 0 /**< \brief (PM_APBASEL) APBA Prescaler Selection */
mbed_official 15:a81a8d6c1dfe 143 #define PM_APBASEL_APBADIV_Msk (0x7ul << PM_APBASEL_APBADIV_Pos)
mbed_official 15:a81a8d6c1dfe 144 #define PM_APBASEL_APBADIV(value) (PM_APBASEL_APBADIV_Msk & ((value) << PM_APBASEL_APBADIV_Pos))
mbed_official 15:a81a8d6c1dfe 145 #define PM_APBASEL_APBADIV_DIV1_Val 0x0ul /**< \brief (PM_APBASEL) Divide by 1 */
mbed_official 15:a81a8d6c1dfe 146 #define PM_APBASEL_APBADIV_DIV2_Val 0x1ul /**< \brief (PM_APBASEL) Divide by 2 */
mbed_official 15:a81a8d6c1dfe 147 #define PM_APBASEL_APBADIV_DIV4_Val 0x2ul /**< \brief (PM_APBASEL) Divide by 4 */
mbed_official 15:a81a8d6c1dfe 148 #define PM_APBASEL_APBADIV_DIV8_Val 0x3ul /**< \brief (PM_APBASEL) Divide by 8 */
mbed_official 15:a81a8d6c1dfe 149 #define PM_APBASEL_APBADIV_DIV16_Val 0x4ul /**< \brief (PM_APBASEL) Divide by 16 */
mbed_official 15:a81a8d6c1dfe 150 #define PM_APBASEL_APBADIV_DIV32_Val 0x5ul /**< \brief (PM_APBASEL) Divide by 32 */
mbed_official 15:a81a8d6c1dfe 151 #define PM_APBASEL_APBADIV_DIV64_Val 0x6ul /**< \brief (PM_APBASEL) Divide by 64 */
mbed_official 15:a81a8d6c1dfe 152 #define PM_APBASEL_APBADIV_DIV128_Val 0x7ul /**< \brief (PM_APBASEL) Divide by 128 */
mbed_official 15:a81a8d6c1dfe 153 #define PM_APBASEL_APBADIV_DIV1 (PM_APBASEL_APBADIV_DIV1_Val << PM_APBASEL_APBADIV_Pos)
mbed_official 15:a81a8d6c1dfe 154 #define PM_APBASEL_APBADIV_DIV2 (PM_APBASEL_APBADIV_DIV2_Val << PM_APBASEL_APBADIV_Pos)
mbed_official 15:a81a8d6c1dfe 155 #define PM_APBASEL_APBADIV_DIV4 (PM_APBASEL_APBADIV_DIV4_Val << PM_APBASEL_APBADIV_Pos)
mbed_official 15:a81a8d6c1dfe 156 #define PM_APBASEL_APBADIV_DIV8 (PM_APBASEL_APBADIV_DIV8_Val << PM_APBASEL_APBADIV_Pos)
mbed_official 15:a81a8d6c1dfe 157 #define PM_APBASEL_APBADIV_DIV16 (PM_APBASEL_APBADIV_DIV16_Val << PM_APBASEL_APBADIV_Pos)
mbed_official 15:a81a8d6c1dfe 158 #define PM_APBASEL_APBADIV_DIV32 (PM_APBASEL_APBADIV_DIV32_Val << PM_APBASEL_APBADIV_Pos)
mbed_official 15:a81a8d6c1dfe 159 #define PM_APBASEL_APBADIV_DIV64 (PM_APBASEL_APBADIV_DIV64_Val << PM_APBASEL_APBADIV_Pos)
mbed_official 15:a81a8d6c1dfe 160 #define PM_APBASEL_APBADIV_DIV128 (PM_APBASEL_APBADIV_DIV128_Val << PM_APBASEL_APBADIV_Pos)
mbed_official 15:a81a8d6c1dfe 161 #define PM_APBASEL_MASK 0x07ul /**< \brief (PM_APBASEL) MASK Register */
mbed_official 15:a81a8d6c1dfe 162
mbed_official 15:a81a8d6c1dfe 163 /* -------- PM_APBBSEL : (PM Offset: 0x0A) (R/W 8) APBB Clock Select -------- */
mbed_official 15:a81a8d6c1dfe 164 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 165 typedef union {
mbed_official 15:a81a8d6c1dfe 166 struct {
mbed_official 15:a81a8d6c1dfe 167 uint8_t APBBDIV:3; /*!< bit: 0.. 2 APBB Prescaler Selection */
mbed_official 15:a81a8d6c1dfe 168 uint8_t :5; /*!< bit: 3.. 7 Reserved */
mbed_official 15:a81a8d6c1dfe 169 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 170 uint8_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 171 } PM_APBBSEL_Type;
mbed_official 15:a81a8d6c1dfe 172 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 173
mbed_official 15:a81a8d6c1dfe 174 #define PM_APBBSEL_OFFSET 0x0A /**< \brief (PM_APBBSEL offset) APBB Clock Select */
mbed_official 15:a81a8d6c1dfe 175 #define PM_APBBSEL_RESETVALUE 0x00ul /**< \brief (PM_APBBSEL reset_value) APBB Clock Select */
mbed_official 15:a81a8d6c1dfe 176
mbed_official 15:a81a8d6c1dfe 177 #define PM_APBBSEL_APBBDIV_Pos 0 /**< \brief (PM_APBBSEL) APBB Prescaler Selection */
mbed_official 15:a81a8d6c1dfe 178 #define PM_APBBSEL_APBBDIV_Msk (0x7ul << PM_APBBSEL_APBBDIV_Pos)
mbed_official 15:a81a8d6c1dfe 179 #define PM_APBBSEL_APBBDIV(value) (PM_APBBSEL_APBBDIV_Msk & ((value) << PM_APBBSEL_APBBDIV_Pos))
mbed_official 15:a81a8d6c1dfe 180 #define PM_APBBSEL_APBBDIV_DIV1_Val 0x0ul /**< \brief (PM_APBBSEL) Divide by 1 */
mbed_official 15:a81a8d6c1dfe 181 #define PM_APBBSEL_APBBDIV_DIV2_Val 0x1ul /**< \brief (PM_APBBSEL) Divide by 2 */
mbed_official 15:a81a8d6c1dfe 182 #define PM_APBBSEL_APBBDIV_DIV4_Val 0x2ul /**< \brief (PM_APBBSEL) Divide by 4 */
mbed_official 15:a81a8d6c1dfe 183 #define PM_APBBSEL_APBBDIV_DIV8_Val 0x3ul /**< \brief (PM_APBBSEL) Divide by 8 */
mbed_official 15:a81a8d6c1dfe 184 #define PM_APBBSEL_APBBDIV_DIV16_Val 0x4ul /**< \brief (PM_APBBSEL) Divide by 16 */
mbed_official 15:a81a8d6c1dfe 185 #define PM_APBBSEL_APBBDIV_DIV32_Val 0x5ul /**< \brief (PM_APBBSEL) Divide by 32 */
mbed_official 15:a81a8d6c1dfe 186 #define PM_APBBSEL_APBBDIV_DIV64_Val 0x6ul /**< \brief (PM_APBBSEL) Divide by 64 */
mbed_official 15:a81a8d6c1dfe 187 #define PM_APBBSEL_APBBDIV_DIV128_Val 0x7ul /**< \brief (PM_APBBSEL) Divide by 128 */
mbed_official 15:a81a8d6c1dfe 188 #define PM_APBBSEL_APBBDIV_DIV1 (PM_APBBSEL_APBBDIV_DIV1_Val << PM_APBBSEL_APBBDIV_Pos)
mbed_official 15:a81a8d6c1dfe 189 #define PM_APBBSEL_APBBDIV_DIV2 (PM_APBBSEL_APBBDIV_DIV2_Val << PM_APBBSEL_APBBDIV_Pos)
mbed_official 15:a81a8d6c1dfe 190 #define PM_APBBSEL_APBBDIV_DIV4 (PM_APBBSEL_APBBDIV_DIV4_Val << PM_APBBSEL_APBBDIV_Pos)
mbed_official 15:a81a8d6c1dfe 191 #define PM_APBBSEL_APBBDIV_DIV8 (PM_APBBSEL_APBBDIV_DIV8_Val << PM_APBBSEL_APBBDIV_Pos)
mbed_official 15:a81a8d6c1dfe 192 #define PM_APBBSEL_APBBDIV_DIV16 (PM_APBBSEL_APBBDIV_DIV16_Val << PM_APBBSEL_APBBDIV_Pos)
mbed_official 15:a81a8d6c1dfe 193 #define PM_APBBSEL_APBBDIV_DIV32 (PM_APBBSEL_APBBDIV_DIV32_Val << PM_APBBSEL_APBBDIV_Pos)
mbed_official 15:a81a8d6c1dfe 194 #define PM_APBBSEL_APBBDIV_DIV64 (PM_APBBSEL_APBBDIV_DIV64_Val << PM_APBBSEL_APBBDIV_Pos)
mbed_official 15:a81a8d6c1dfe 195 #define PM_APBBSEL_APBBDIV_DIV128 (PM_APBBSEL_APBBDIV_DIV128_Val << PM_APBBSEL_APBBDIV_Pos)
mbed_official 15:a81a8d6c1dfe 196 #define PM_APBBSEL_MASK 0x07ul /**< \brief (PM_APBBSEL) MASK Register */
mbed_official 15:a81a8d6c1dfe 197
mbed_official 15:a81a8d6c1dfe 198 /* -------- PM_APBCSEL : (PM Offset: 0x0B) (R/W 8) APBC Clock Select -------- */
mbed_official 15:a81a8d6c1dfe 199 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 200 typedef union {
mbed_official 15:a81a8d6c1dfe 201 struct {
mbed_official 15:a81a8d6c1dfe 202 uint8_t APBCDIV:3; /*!< bit: 0.. 2 APBC Prescaler Selection */
mbed_official 15:a81a8d6c1dfe 203 uint8_t :5; /*!< bit: 3.. 7 Reserved */
mbed_official 15:a81a8d6c1dfe 204 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 205 uint8_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 206 } PM_APBCSEL_Type;
mbed_official 15:a81a8d6c1dfe 207 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 208
mbed_official 15:a81a8d6c1dfe 209 #define PM_APBCSEL_OFFSET 0x0B /**< \brief (PM_APBCSEL offset) APBC Clock Select */
mbed_official 15:a81a8d6c1dfe 210 #define PM_APBCSEL_RESETVALUE 0x00ul /**< \brief (PM_APBCSEL reset_value) APBC Clock Select */
mbed_official 15:a81a8d6c1dfe 211
mbed_official 15:a81a8d6c1dfe 212 #define PM_APBCSEL_APBCDIV_Pos 0 /**< \brief (PM_APBCSEL) APBC Prescaler Selection */
mbed_official 15:a81a8d6c1dfe 213 #define PM_APBCSEL_APBCDIV_Msk (0x7ul << PM_APBCSEL_APBCDIV_Pos)
mbed_official 15:a81a8d6c1dfe 214 #define PM_APBCSEL_APBCDIV(value) (PM_APBCSEL_APBCDIV_Msk & ((value) << PM_APBCSEL_APBCDIV_Pos))
mbed_official 15:a81a8d6c1dfe 215 #define PM_APBCSEL_APBCDIV_DIV1_Val 0x0ul /**< \brief (PM_APBCSEL) Divide by 1 */
mbed_official 15:a81a8d6c1dfe 216 #define PM_APBCSEL_APBCDIV_DIV2_Val 0x1ul /**< \brief (PM_APBCSEL) Divide by 2 */
mbed_official 15:a81a8d6c1dfe 217 #define PM_APBCSEL_APBCDIV_DIV4_Val 0x2ul /**< \brief (PM_APBCSEL) Divide by 4 */
mbed_official 15:a81a8d6c1dfe 218 #define PM_APBCSEL_APBCDIV_DIV8_Val 0x3ul /**< \brief (PM_APBCSEL) Divide by 8 */
mbed_official 15:a81a8d6c1dfe 219 #define PM_APBCSEL_APBCDIV_DIV16_Val 0x4ul /**< \brief (PM_APBCSEL) Divide by 16 */
mbed_official 15:a81a8d6c1dfe 220 #define PM_APBCSEL_APBCDIV_DIV32_Val 0x5ul /**< \brief (PM_APBCSEL) Divide by 32 */
mbed_official 15:a81a8d6c1dfe 221 #define PM_APBCSEL_APBCDIV_DIV64_Val 0x6ul /**< \brief (PM_APBCSEL) Divide by 64 */
mbed_official 15:a81a8d6c1dfe 222 #define PM_APBCSEL_APBCDIV_DIV128_Val 0x7ul /**< \brief (PM_APBCSEL) Divide by 128 */
mbed_official 15:a81a8d6c1dfe 223 #define PM_APBCSEL_APBCDIV_DIV1 (PM_APBCSEL_APBCDIV_DIV1_Val << PM_APBCSEL_APBCDIV_Pos)
mbed_official 15:a81a8d6c1dfe 224 #define PM_APBCSEL_APBCDIV_DIV2 (PM_APBCSEL_APBCDIV_DIV2_Val << PM_APBCSEL_APBCDIV_Pos)
mbed_official 15:a81a8d6c1dfe 225 #define PM_APBCSEL_APBCDIV_DIV4 (PM_APBCSEL_APBCDIV_DIV4_Val << PM_APBCSEL_APBCDIV_Pos)
mbed_official 15:a81a8d6c1dfe 226 #define PM_APBCSEL_APBCDIV_DIV8 (PM_APBCSEL_APBCDIV_DIV8_Val << PM_APBCSEL_APBCDIV_Pos)
mbed_official 15:a81a8d6c1dfe 227 #define PM_APBCSEL_APBCDIV_DIV16 (PM_APBCSEL_APBCDIV_DIV16_Val << PM_APBCSEL_APBCDIV_Pos)
mbed_official 15:a81a8d6c1dfe 228 #define PM_APBCSEL_APBCDIV_DIV32 (PM_APBCSEL_APBCDIV_DIV32_Val << PM_APBCSEL_APBCDIV_Pos)
mbed_official 15:a81a8d6c1dfe 229 #define PM_APBCSEL_APBCDIV_DIV64 (PM_APBCSEL_APBCDIV_DIV64_Val << PM_APBCSEL_APBCDIV_Pos)
mbed_official 15:a81a8d6c1dfe 230 #define PM_APBCSEL_APBCDIV_DIV128 (PM_APBCSEL_APBCDIV_DIV128_Val << PM_APBCSEL_APBCDIV_Pos)
mbed_official 15:a81a8d6c1dfe 231 #define PM_APBCSEL_MASK 0x07ul /**< \brief (PM_APBCSEL) MASK Register */
mbed_official 15:a81a8d6c1dfe 232
mbed_official 15:a81a8d6c1dfe 233 /* -------- PM_AHBMASK : (PM Offset: 0x14) (R/W 32) AHB Mask -------- */
mbed_official 15:a81a8d6c1dfe 234 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 235 typedef union {
mbed_official 15:a81a8d6c1dfe 236 struct {
mbed_official 15:a81a8d6c1dfe 237 uint32_t HPB0_:1; /*!< bit: 0 HPB0 AHB Clock Mask */
mbed_official 15:a81a8d6c1dfe 238 uint32_t HPB1_:1; /*!< bit: 1 HPB1 AHB Clock Mask */
mbed_official 15:a81a8d6c1dfe 239 uint32_t HPB2_:1; /*!< bit: 2 HPB2 AHB Clock Mask */
mbed_official 15:a81a8d6c1dfe 240 uint32_t DSU_:1; /*!< bit: 3 DSU AHB Clock Mask */
mbed_official 15:a81a8d6c1dfe 241 uint32_t NVMCTRL_:1; /*!< bit: 4 NVMCTRL AHB Clock Mask */
mbed_official 15:a81a8d6c1dfe 242 uint32_t DMAC_:1; /*!< bit: 5 DMAC AHB Clock Mask */
mbed_official 15:a81a8d6c1dfe 243 uint32_t USB_:1; /*!< bit: 6 USB AHB Clock Mask */
mbed_official 15:a81a8d6c1dfe 244 uint32_t :25; /*!< bit: 7..31 Reserved */
mbed_official 15:a81a8d6c1dfe 245 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 246 uint32_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 247 } PM_AHBMASK_Type;
mbed_official 15:a81a8d6c1dfe 248 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 249
mbed_official 15:a81a8d6c1dfe 250 #define PM_AHBMASK_OFFSET 0x14 /**< \brief (PM_AHBMASK offset) AHB Mask */
mbed_official 15:a81a8d6c1dfe 251 #define PM_AHBMASK_RESETVALUE 0x0000007Ful /**< \brief (PM_AHBMASK reset_value) AHB Mask */
mbed_official 15:a81a8d6c1dfe 252
mbed_official 15:a81a8d6c1dfe 253 #define PM_AHBMASK_HPB0_Pos 0 /**< \brief (PM_AHBMASK) HPB0 AHB Clock Mask */
mbed_official 15:a81a8d6c1dfe 254 #define PM_AHBMASK_HPB0 (0x1ul << PM_AHBMASK_HPB0_Pos)
mbed_official 15:a81a8d6c1dfe 255 #define PM_AHBMASK_HPB1_Pos 1 /**< \brief (PM_AHBMASK) HPB1 AHB Clock Mask */
mbed_official 15:a81a8d6c1dfe 256 #define PM_AHBMASK_HPB1 (0x1ul << PM_AHBMASK_HPB1_Pos)
mbed_official 15:a81a8d6c1dfe 257 #define PM_AHBMASK_HPB2_Pos 2 /**< \brief (PM_AHBMASK) HPB2 AHB Clock Mask */
mbed_official 15:a81a8d6c1dfe 258 #define PM_AHBMASK_HPB2 (0x1ul << PM_AHBMASK_HPB2_Pos)
mbed_official 15:a81a8d6c1dfe 259 #define PM_AHBMASK_DSU_Pos 3 /**< \brief (PM_AHBMASK) DSU AHB Clock Mask */
mbed_official 15:a81a8d6c1dfe 260 #define PM_AHBMASK_DSU (0x1ul << PM_AHBMASK_DSU_Pos)
mbed_official 15:a81a8d6c1dfe 261 #define PM_AHBMASK_NVMCTRL_Pos 4 /**< \brief (PM_AHBMASK) NVMCTRL AHB Clock Mask */
mbed_official 15:a81a8d6c1dfe 262 #define PM_AHBMASK_NVMCTRL (0x1ul << PM_AHBMASK_NVMCTRL_Pos)
mbed_official 15:a81a8d6c1dfe 263 #define PM_AHBMASK_DMAC_Pos 5 /**< \brief (PM_AHBMASK) DMAC AHB Clock Mask */
mbed_official 15:a81a8d6c1dfe 264 #define PM_AHBMASK_DMAC (0x1ul << PM_AHBMASK_DMAC_Pos)
mbed_official 15:a81a8d6c1dfe 265 #define PM_AHBMASK_USB_Pos 6 /**< \brief (PM_AHBMASK) USB AHB Clock Mask */
mbed_official 15:a81a8d6c1dfe 266 #define PM_AHBMASK_USB (0x1ul << PM_AHBMASK_USB_Pos)
mbed_official 15:a81a8d6c1dfe 267 #define PM_AHBMASK_MASK 0x0000007Ful /**< \brief (PM_AHBMASK) MASK Register */
mbed_official 15:a81a8d6c1dfe 268
mbed_official 15:a81a8d6c1dfe 269 /* -------- PM_APBAMASK : (PM Offset: 0x18) (R/W 32) APBA Mask -------- */
mbed_official 15:a81a8d6c1dfe 270 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 271 typedef union {
mbed_official 15:a81a8d6c1dfe 272 struct {
mbed_official 15:a81a8d6c1dfe 273 uint32_t PAC0_:1; /*!< bit: 0 PAC0 APB Clock Enable */
mbed_official 15:a81a8d6c1dfe 274 uint32_t PM_:1; /*!< bit: 1 PM APB Clock Enable */
mbed_official 15:a81a8d6c1dfe 275 uint32_t SYSCTRL_:1; /*!< bit: 2 SYSCTRL APB Clock Enable */
mbed_official 15:a81a8d6c1dfe 276 uint32_t GCLK_:1; /*!< bit: 3 GCLK APB Clock Enable */
mbed_official 15:a81a8d6c1dfe 277 uint32_t WDT_:1; /*!< bit: 4 WDT APB Clock Enable */
mbed_official 15:a81a8d6c1dfe 278 uint32_t RTC_:1; /*!< bit: 5 RTC APB Clock Enable */
mbed_official 15:a81a8d6c1dfe 279 uint32_t EIC_:1; /*!< bit: 6 EIC APB Clock Enable */
mbed_official 15:a81a8d6c1dfe 280 uint32_t :25; /*!< bit: 7..31 Reserved */
mbed_official 15:a81a8d6c1dfe 281 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 282 uint32_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 283 } PM_APBAMASK_Type;
mbed_official 15:a81a8d6c1dfe 284 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 285
mbed_official 15:a81a8d6c1dfe 286 #define PM_APBAMASK_OFFSET 0x18 /**< \brief (PM_APBAMASK offset) APBA Mask */
mbed_official 15:a81a8d6c1dfe 287 #define PM_APBAMASK_RESETVALUE 0x0000007Ful /**< \brief (PM_APBAMASK reset_value) APBA Mask */
mbed_official 15:a81a8d6c1dfe 288
mbed_official 15:a81a8d6c1dfe 289 #define PM_APBAMASK_PAC0_Pos 0 /**< \brief (PM_APBAMASK) PAC0 APB Clock Enable */
mbed_official 15:a81a8d6c1dfe 290 #define PM_APBAMASK_PAC0 (0x1ul << PM_APBAMASK_PAC0_Pos)
mbed_official 15:a81a8d6c1dfe 291 #define PM_APBAMASK_PM_Pos 1 /**< \brief (PM_APBAMASK) PM APB Clock Enable */
mbed_official 15:a81a8d6c1dfe 292 #define PM_APBAMASK_PM (0x1ul << PM_APBAMASK_PM_Pos)
mbed_official 15:a81a8d6c1dfe 293 #define PM_APBAMASK_SYSCTRL_Pos 2 /**< \brief (PM_APBAMASK) SYSCTRL APB Clock Enable */
mbed_official 15:a81a8d6c1dfe 294 #define PM_APBAMASK_SYSCTRL (0x1ul << PM_APBAMASK_SYSCTRL_Pos)
mbed_official 15:a81a8d6c1dfe 295 #define PM_APBAMASK_GCLK_Pos 3 /**< \brief (PM_APBAMASK) GCLK APB Clock Enable */
mbed_official 15:a81a8d6c1dfe 296 #define PM_APBAMASK_GCLK (0x1ul << PM_APBAMASK_GCLK_Pos)
mbed_official 15:a81a8d6c1dfe 297 #define PM_APBAMASK_WDT_Pos 4 /**< \brief (PM_APBAMASK) WDT APB Clock Enable */
mbed_official 15:a81a8d6c1dfe 298 #define PM_APBAMASK_WDT (0x1ul << PM_APBAMASK_WDT_Pos)
mbed_official 15:a81a8d6c1dfe 299 #define PM_APBAMASK_RTC_Pos 5 /**< \brief (PM_APBAMASK) RTC APB Clock Enable */
mbed_official 15:a81a8d6c1dfe 300 #define PM_APBAMASK_RTC (0x1ul << PM_APBAMASK_RTC_Pos)
mbed_official 15:a81a8d6c1dfe 301 #define PM_APBAMASK_EIC_Pos 6 /**< \brief (PM_APBAMASK) EIC APB Clock Enable */
mbed_official 15:a81a8d6c1dfe 302 #define PM_APBAMASK_EIC (0x1ul << PM_APBAMASK_EIC_Pos)
mbed_official 15:a81a8d6c1dfe 303 #define PM_APBAMASK_MASK 0x0000007Ful /**< \brief (PM_APBAMASK) MASK Register */
mbed_official 15:a81a8d6c1dfe 304
mbed_official 15:a81a8d6c1dfe 305 /* -------- PM_APBBMASK : (PM Offset: 0x1C) (R/W 32) APBB Mask -------- */
mbed_official 15:a81a8d6c1dfe 306 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 307 typedef union {
mbed_official 15:a81a8d6c1dfe 308 struct {
mbed_official 15:a81a8d6c1dfe 309 uint32_t PAC1_:1; /*!< bit: 0 PAC1 APB Clock Enable */
mbed_official 15:a81a8d6c1dfe 310 uint32_t DSU_:1; /*!< bit: 1 DSU APB Clock Enable */
mbed_official 15:a81a8d6c1dfe 311 uint32_t NVMCTRL_:1; /*!< bit: 2 NVMCTRL APB Clock Enable */
mbed_official 15:a81a8d6c1dfe 312 uint32_t PORT_:1; /*!< bit: 3 PORT APB Clock Enable */
mbed_official 15:a81a8d6c1dfe 313 uint32_t DMAC_:1; /*!< bit: 4 DMAC APB Clock Enable */
mbed_official 15:a81a8d6c1dfe 314 uint32_t USB_:1; /*!< bit: 5 USB APB Clock Enable */
mbed_official 15:a81a8d6c1dfe 315 uint32_t HMATRIX_:1; /*!< bit: 6 HMATRIX APB Clock Enable */
mbed_official 15:a81a8d6c1dfe 316 uint32_t :25; /*!< bit: 7..31 Reserved */
mbed_official 15:a81a8d6c1dfe 317 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 318 uint32_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 319 } PM_APBBMASK_Type;
mbed_official 15:a81a8d6c1dfe 320 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 321
mbed_official 15:a81a8d6c1dfe 322 #define PM_APBBMASK_OFFSET 0x1C /**< \brief (PM_APBBMASK offset) APBB Mask */
mbed_official 15:a81a8d6c1dfe 323 #define PM_APBBMASK_RESETVALUE 0x0000007Ful /**< \brief (PM_APBBMASK reset_value) APBB Mask */
mbed_official 15:a81a8d6c1dfe 324
mbed_official 15:a81a8d6c1dfe 325 #define PM_APBBMASK_PAC1_Pos 0 /**< \brief (PM_APBBMASK) PAC1 APB Clock Enable */
mbed_official 15:a81a8d6c1dfe 326 #define PM_APBBMASK_PAC1 (0x1ul << PM_APBBMASK_PAC1_Pos)
mbed_official 15:a81a8d6c1dfe 327 #define PM_APBBMASK_DSU_Pos 1 /**< \brief (PM_APBBMASK) DSU APB Clock Enable */
mbed_official 15:a81a8d6c1dfe 328 #define PM_APBBMASK_DSU (0x1ul << PM_APBBMASK_DSU_Pos)
mbed_official 15:a81a8d6c1dfe 329 #define PM_APBBMASK_NVMCTRL_Pos 2 /**< \brief (PM_APBBMASK) NVMCTRL APB Clock Enable */
mbed_official 15:a81a8d6c1dfe 330 #define PM_APBBMASK_NVMCTRL (0x1ul << PM_APBBMASK_NVMCTRL_Pos)
mbed_official 15:a81a8d6c1dfe 331 #define PM_APBBMASK_PORT_Pos 3 /**< \brief (PM_APBBMASK) PORT APB Clock Enable */
mbed_official 15:a81a8d6c1dfe 332 #define PM_APBBMASK_PORT (0x1ul << PM_APBBMASK_PORT_Pos)
mbed_official 15:a81a8d6c1dfe 333 #define PM_APBBMASK_DMAC_Pos 4 /**< \brief (PM_APBBMASK) DMAC APB Clock Enable */
mbed_official 15:a81a8d6c1dfe 334 #define PM_APBBMASK_DMAC (0x1ul << PM_APBBMASK_DMAC_Pos)
mbed_official 15:a81a8d6c1dfe 335 #define PM_APBBMASK_USB_Pos 5 /**< \brief (PM_APBBMASK) USB APB Clock Enable */
mbed_official 15:a81a8d6c1dfe 336 #define PM_APBBMASK_USB (0x1ul << PM_APBBMASK_USB_Pos)
mbed_official 15:a81a8d6c1dfe 337 #define PM_APBBMASK_HMATRIX_Pos 6 /**< \brief (PM_APBBMASK) HMATRIX APB Clock Enable */
mbed_official 15:a81a8d6c1dfe 338 #define PM_APBBMASK_HMATRIX (0x1ul << PM_APBBMASK_HMATRIX_Pos)
mbed_official 15:a81a8d6c1dfe 339 #define PM_APBBMASK_MASK 0x0000007Ful /**< \brief (PM_APBBMASK) MASK Register */
mbed_official 15:a81a8d6c1dfe 340
mbed_official 15:a81a8d6c1dfe 341 /* -------- PM_APBCMASK : (PM Offset: 0x20) (R/W 32) APBC Mask -------- */
mbed_official 15:a81a8d6c1dfe 342 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 343 typedef union {
mbed_official 15:a81a8d6c1dfe 344 struct {
mbed_official 15:a81a8d6c1dfe 345 uint32_t PAC2_:1; /*!< bit: 0 PAC2 APB Clock Enable */
mbed_official 15:a81a8d6c1dfe 346 uint32_t EVSYS_:1; /*!< bit: 1 EVSYS APB Clock Enable */
mbed_official 15:a81a8d6c1dfe 347 uint32_t SERCOM0_:1; /*!< bit: 2 SERCOM0 APB Clock Enable */
mbed_official 15:a81a8d6c1dfe 348 uint32_t SERCOM1_:1; /*!< bit: 3 SERCOM1 APB Clock Enable */
mbed_official 15:a81a8d6c1dfe 349 uint32_t SERCOM2_:1; /*!< bit: 4 SERCOM2 APB Clock Enable */
mbed_official 15:a81a8d6c1dfe 350 uint32_t SERCOM3_:1; /*!< bit: 5 SERCOM3 APB Clock Enable */
mbed_official 15:a81a8d6c1dfe 351 uint32_t SERCOM4_:1; /*!< bit: 6 SERCOM4 APB Clock Enable */
mbed_official 15:a81a8d6c1dfe 352 uint32_t SERCOM5_:1; /*!< bit: 7 SERCOM5 APB Clock Enable */
mbed_official 15:a81a8d6c1dfe 353 uint32_t TCC0_:1; /*!< bit: 8 TCC0 APB Clock Enable */
mbed_official 15:a81a8d6c1dfe 354 uint32_t TCC1_:1; /*!< bit: 9 TCC1 APB Clock Enable */
mbed_official 15:a81a8d6c1dfe 355 uint32_t TCC2_:1; /*!< bit: 10 TCC2 APB Clock Enable */
mbed_official 15:a81a8d6c1dfe 356 uint32_t TC3_:1; /*!< bit: 11 TC3 APB Clock Enable */
mbed_official 15:a81a8d6c1dfe 357 uint32_t TC4_:1; /*!< bit: 12 TC4 APB Clock Enable */
mbed_official 15:a81a8d6c1dfe 358 uint32_t TC5_:1; /*!< bit: 13 TC5 APB Clock Enable */
mbed_official 15:a81a8d6c1dfe 359 uint32_t :2; /*!< bit: 14..15 Reserved */
mbed_official 15:a81a8d6c1dfe 360 uint32_t ADC_:1; /*!< bit: 16 ADC APB Clock Enable */
mbed_official 15:a81a8d6c1dfe 361 uint32_t AC_:1; /*!< bit: 17 AC APB Clock Enable */
mbed_official 15:a81a8d6c1dfe 362 uint32_t :1; /*!< bit: 18 Reserved */
mbed_official 15:a81a8d6c1dfe 363 uint32_t PTC_:1; /*!< bit: 19 PTC APB Clock Enable */
mbed_official 15:a81a8d6c1dfe 364 uint32_t :1; /*!< bit: 20 Reserved */
mbed_official 15:a81a8d6c1dfe 365 uint32_t RFCTRL_:1; /*!< bit: 21 RFCTRL APB Clock Enable */
mbed_official 15:a81a8d6c1dfe 366 uint32_t :10; /*!< bit: 22..31 Reserved */
mbed_official 15:a81a8d6c1dfe 367 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 368 uint32_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 369 } PM_APBCMASK_Type;
mbed_official 15:a81a8d6c1dfe 370 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 371
mbed_official 15:a81a8d6c1dfe 372 #define PM_APBCMASK_OFFSET 0x20 /**< \brief (PM_APBCMASK offset) APBC Mask */
mbed_official 15:a81a8d6c1dfe 373 #define PM_APBCMASK_RESETVALUE 0x00010000ul /**< \brief (PM_APBCMASK reset_value) APBC Mask */
mbed_official 15:a81a8d6c1dfe 374
mbed_official 15:a81a8d6c1dfe 375 #define PM_APBCMASK_PAC2_Pos 0 /**< \brief (PM_APBCMASK) PAC2 APB Clock Enable */
mbed_official 15:a81a8d6c1dfe 376 #define PM_APBCMASK_PAC2 (0x1ul << PM_APBCMASK_PAC2_Pos)
mbed_official 15:a81a8d6c1dfe 377 #define PM_APBCMASK_EVSYS_Pos 1 /**< \brief (PM_APBCMASK) EVSYS APB Clock Enable */
mbed_official 15:a81a8d6c1dfe 378 #define PM_APBCMASK_EVSYS (0x1ul << PM_APBCMASK_EVSYS_Pos)
mbed_official 15:a81a8d6c1dfe 379 #define PM_APBCMASK_SERCOM0_Pos 2 /**< \brief (PM_APBCMASK) SERCOM0 APB Clock Enable */
mbed_official 15:a81a8d6c1dfe 380 #define PM_APBCMASK_SERCOM0 (0x1ul << PM_APBCMASK_SERCOM0_Pos)
mbed_official 15:a81a8d6c1dfe 381 #define PM_APBCMASK_SERCOM1_Pos 3 /**< \brief (PM_APBCMASK) SERCOM1 APB Clock Enable */
mbed_official 15:a81a8d6c1dfe 382 #define PM_APBCMASK_SERCOM1 (0x1ul << PM_APBCMASK_SERCOM1_Pos)
mbed_official 15:a81a8d6c1dfe 383 #define PM_APBCMASK_SERCOM2_Pos 4 /**< \brief (PM_APBCMASK) SERCOM2 APB Clock Enable */
mbed_official 15:a81a8d6c1dfe 384 #define PM_APBCMASK_SERCOM2 (0x1ul << PM_APBCMASK_SERCOM2_Pos)
mbed_official 15:a81a8d6c1dfe 385 #define PM_APBCMASK_SERCOM3_Pos 5 /**< \brief (PM_APBCMASK) SERCOM3 APB Clock Enable */
mbed_official 15:a81a8d6c1dfe 386 #define PM_APBCMASK_SERCOM3 (0x1ul << PM_APBCMASK_SERCOM3_Pos)
mbed_official 15:a81a8d6c1dfe 387 #define PM_APBCMASK_SERCOM4_Pos 6 /**< \brief (PM_APBCMASK) SERCOM4 APB Clock Enable */
mbed_official 15:a81a8d6c1dfe 388 #define PM_APBCMASK_SERCOM4 (0x1ul << PM_APBCMASK_SERCOM4_Pos)
mbed_official 15:a81a8d6c1dfe 389 #define PM_APBCMASK_SERCOM5_Pos 7 /**< \brief (PM_APBCMASK) SERCOM5 APB Clock Enable */
mbed_official 15:a81a8d6c1dfe 390 #define PM_APBCMASK_SERCOM5 (0x1ul << PM_APBCMASK_SERCOM5_Pos)
mbed_official 15:a81a8d6c1dfe 391 #define PM_APBCMASK_TCC0_Pos 8 /**< \brief (PM_APBCMASK) TCC0 APB Clock Enable */
mbed_official 15:a81a8d6c1dfe 392 #define PM_APBCMASK_TCC0 (0x1ul << PM_APBCMASK_TCC0_Pos)
mbed_official 15:a81a8d6c1dfe 393 #define PM_APBCMASK_TCC1_Pos 9 /**< \brief (PM_APBCMASK) TCC1 APB Clock Enable */
mbed_official 15:a81a8d6c1dfe 394 #define PM_APBCMASK_TCC1 (0x1ul << PM_APBCMASK_TCC1_Pos)
mbed_official 15:a81a8d6c1dfe 395 #define PM_APBCMASK_TCC2_Pos 10 /**< \brief (PM_APBCMASK) TCC2 APB Clock Enable */
mbed_official 15:a81a8d6c1dfe 396 #define PM_APBCMASK_TCC2 (0x1ul << PM_APBCMASK_TCC2_Pos)
mbed_official 15:a81a8d6c1dfe 397 #define PM_APBCMASK_TC3_Pos 11 /**< \brief (PM_APBCMASK) TC3 APB Clock Enable */
mbed_official 15:a81a8d6c1dfe 398 #define PM_APBCMASK_TC3 (0x1ul << PM_APBCMASK_TC3_Pos)
mbed_official 15:a81a8d6c1dfe 399 #define PM_APBCMASK_TC4_Pos 12 /**< \brief (PM_APBCMASK) TC4 APB Clock Enable */
mbed_official 15:a81a8d6c1dfe 400 #define PM_APBCMASK_TC4 (0x1ul << PM_APBCMASK_TC4_Pos)
mbed_official 15:a81a8d6c1dfe 401 #define PM_APBCMASK_TC5_Pos 13 /**< \brief (PM_APBCMASK) TC5 APB Clock Enable */
mbed_official 15:a81a8d6c1dfe 402 #define PM_APBCMASK_TC5 (0x1ul << PM_APBCMASK_TC5_Pos)
mbed_official 15:a81a8d6c1dfe 403 #define PM_APBCMASK_ADC_Pos 16 /**< \brief (PM_APBCMASK) ADC APB Clock Enable */
mbed_official 15:a81a8d6c1dfe 404 #define PM_APBCMASK_ADC (0x1ul << PM_APBCMASK_ADC_Pos)
mbed_official 15:a81a8d6c1dfe 405 #define PM_APBCMASK_AC_Pos 17 /**< \brief (PM_APBCMASK) AC APB Clock Enable */
mbed_official 15:a81a8d6c1dfe 406 #define PM_APBCMASK_AC (0x1ul << PM_APBCMASK_AC_Pos)
mbed_official 15:a81a8d6c1dfe 407 #define PM_APBCMASK_PTC_Pos 19 /**< \brief (PM_APBCMASK) PTC APB Clock Enable */
mbed_official 15:a81a8d6c1dfe 408 #define PM_APBCMASK_PTC (0x1ul << PM_APBCMASK_PTC_Pos)
mbed_official 15:a81a8d6c1dfe 409 #define PM_APBCMASK_RFCTRL_Pos 21 /**< \brief (PM_APBCMASK) RFCTRL APB Clock Enable */
mbed_official 15:a81a8d6c1dfe 410 #define PM_APBCMASK_RFCTRL (0x1ul << PM_APBCMASK_RFCTRL_Pos)
mbed_official 15:a81a8d6c1dfe 411 #define PM_APBCMASK_MASK 0x002B3FFFul /**< \brief (PM_APBCMASK) MASK Register */
mbed_official 15:a81a8d6c1dfe 412
mbed_official 15:a81a8d6c1dfe 413 /* -------- PM_INTENCLR : (PM Offset: 0x34) (R/W 8) Interrupt Enable Clear -------- */
mbed_official 15:a81a8d6c1dfe 414 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 415 typedef union {
mbed_official 15:a81a8d6c1dfe 416 struct {
mbed_official 15:a81a8d6c1dfe 417 uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 418 uint8_t :7; /*!< bit: 1.. 7 Reserved */
mbed_official 15:a81a8d6c1dfe 419 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 420 uint8_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 421 } PM_INTENCLR_Type;
mbed_official 15:a81a8d6c1dfe 422 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 423
mbed_official 15:a81a8d6c1dfe 424 #define PM_INTENCLR_OFFSET 0x34 /**< \brief (PM_INTENCLR offset) Interrupt Enable Clear */
mbed_official 15:a81a8d6c1dfe 425 #define PM_INTENCLR_RESETVALUE 0x00ul /**< \brief (PM_INTENCLR reset_value) Interrupt Enable Clear */
mbed_official 15:a81a8d6c1dfe 426
mbed_official 15:a81a8d6c1dfe 427 #define PM_INTENCLR_CKRDY_Pos 0 /**< \brief (PM_INTENCLR) Clock Ready Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 428 #define PM_INTENCLR_CKRDY (0x1ul << PM_INTENCLR_CKRDY_Pos)
mbed_official 15:a81a8d6c1dfe 429 #define PM_INTENCLR_MASK 0x01ul /**< \brief (PM_INTENCLR) MASK Register */
mbed_official 15:a81a8d6c1dfe 430
mbed_official 15:a81a8d6c1dfe 431 /* -------- PM_INTENSET : (PM Offset: 0x35) (R/W 8) Interrupt Enable Set -------- */
mbed_official 15:a81a8d6c1dfe 432 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 433 typedef union {
mbed_official 15:a81a8d6c1dfe 434 struct {
mbed_official 15:a81a8d6c1dfe 435 uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 436 uint8_t :7; /*!< bit: 1.. 7 Reserved */
mbed_official 15:a81a8d6c1dfe 437 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 438 uint8_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 439 } PM_INTENSET_Type;
mbed_official 15:a81a8d6c1dfe 440 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 441
mbed_official 15:a81a8d6c1dfe 442 #define PM_INTENSET_OFFSET 0x35 /**< \brief (PM_INTENSET offset) Interrupt Enable Set */
mbed_official 15:a81a8d6c1dfe 443 #define PM_INTENSET_RESETVALUE 0x00ul /**< \brief (PM_INTENSET reset_value) Interrupt Enable Set */
mbed_official 15:a81a8d6c1dfe 444
mbed_official 15:a81a8d6c1dfe 445 #define PM_INTENSET_CKRDY_Pos 0 /**< \brief (PM_INTENSET) Clock Ready Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 446 #define PM_INTENSET_CKRDY (0x1ul << PM_INTENSET_CKRDY_Pos)
mbed_official 15:a81a8d6c1dfe 447 #define PM_INTENSET_MASK 0x01ul /**< \brief (PM_INTENSET) MASK Register */
mbed_official 15:a81a8d6c1dfe 448
mbed_official 15:a81a8d6c1dfe 449 /* -------- PM_INTFLAG : (PM Offset: 0x36) (R/W 8) Interrupt Flag Status and Clear -------- */
mbed_official 15:a81a8d6c1dfe 450 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 451 typedef union { // __I to avoid read-modify-write on write-to-clear register
mbed_official 15:a81a8d6c1dfe 452 struct {
mbed_official 15:a81a8d6c1dfe 453 __I uint8_t CKRDY:1; /*!< bit: 0 Clock Ready */
mbed_official 15:a81a8d6c1dfe 454 __I uint8_t :7; /*!< bit: 1.. 7 Reserved */
mbed_official 15:a81a8d6c1dfe 455 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 456 uint8_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 457 } PM_INTFLAG_Type;
mbed_official 15:a81a8d6c1dfe 458 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 459
mbed_official 15:a81a8d6c1dfe 460 #define PM_INTFLAG_OFFSET 0x36 /**< \brief (PM_INTFLAG offset) Interrupt Flag Status and Clear */
mbed_official 15:a81a8d6c1dfe 461 #define PM_INTFLAG_RESETVALUE 0x00ul /**< \brief (PM_INTFLAG reset_value) Interrupt Flag Status and Clear */
mbed_official 15:a81a8d6c1dfe 462
mbed_official 15:a81a8d6c1dfe 463 #define PM_INTFLAG_CKRDY_Pos 0 /**< \brief (PM_INTFLAG) Clock Ready */
mbed_official 15:a81a8d6c1dfe 464 #define PM_INTFLAG_CKRDY (0x1ul << PM_INTFLAG_CKRDY_Pos)
mbed_official 15:a81a8d6c1dfe 465 #define PM_INTFLAG_MASK 0x01ul /**< \brief (PM_INTFLAG) MASK Register */
mbed_official 15:a81a8d6c1dfe 466
mbed_official 15:a81a8d6c1dfe 467 /* -------- PM_RCAUSE : (PM Offset: 0x38) (R/ 8) Reset Cause -------- */
mbed_official 15:a81a8d6c1dfe 468 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 469 typedef union {
mbed_official 15:a81a8d6c1dfe 470 struct {
mbed_official 15:a81a8d6c1dfe 471 uint8_t POR:1; /*!< bit: 0 Power On Reset */
mbed_official 15:a81a8d6c1dfe 472 uint8_t BOD12:1; /*!< bit: 1 Brown Out 12 Detector Reset */
mbed_official 15:a81a8d6c1dfe 473 uint8_t BOD33:1; /*!< bit: 2 Brown Out 33 Detector Reset */
mbed_official 15:a81a8d6c1dfe 474 uint8_t :1; /*!< bit: 3 Reserved */
mbed_official 15:a81a8d6c1dfe 475 uint8_t EXT:1; /*!< bit: 4 External Reset */
mbed_official 15:a81a8d6c1dfe 476 uint8_t WDT:1; /*!< bit: 5 Watchdog Reset */
mbed_official 15:a81a8d6c1dfe 477 uint8_t SYST:1; /*!< bit: 6 System Reset Request */
mbed_official 15:a81a8d6c1dfe 478 uint8_t :1; /*!< bit: 7 Reserved */
mbed_official 15:a81a8d6c1dfe 479 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 480 uint8_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 481 } PM_RCAUSE_Type;
mbed_official 15:a81a8d6c1dfe 482 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 483
mbed_official 15:a81a8d6c1dfe 484 #define PM_RCAUSE_OFFSET 0x38 /**< \brief (PM_RCAUSE offset) Reset Cause */
mbed_official 15:a81a8d6c1dfe 485 #define PM_RCAUSE_RESETVALUE 0x01ul /**< \brief (PM_RCAUSE reset_value) Reset Cause */
mbed_official 15:a81a8d6c1dfe 486
mbed_official 15:a81a8d6c1dfe 487 #define PM_RCAUSE_POR_Pos 0 /**< \brief (PM_RCAUSE) Power On Reset */
mbed_official 15:a81a8d6c1dfe 488 #define PM_RCAUSE_POR (0x1ul << PM_RCAUSE_POR_Pos)
mbed_official 15:a81a8d6c1dfe 489 #define PM_RCAUSE_BOD12_Pos 1 /**< \brief (PM_RCAUSE) Brown Out 12 Detector Reset */
mbed_official 15:a81a8d6c1dfe 490 #define PM_RCAUSE_BOD12 (0x1ul << PM_RCAUSE_BOD12_Pos)
mbed_official 15:a81a8d6c1dfe 491 #define PM_RCAUSE_BOD33_Pos 2 /**< \brief (PM_RCAUSE) Brown Out 33 Detector Reset */
mbed_official 15:a81a8d6c1dfe 492 #define PM_RCAUSE_BOD33 (0x1ul << PM_RCAUSE_BOD33_Pos)
mbed_official 15:a81a8d6c1dfe 493 #define PM_RCAUSE_EXT_Pos 4 /**< \brief (PM_RCAUSE) External Reset */
mbed_official 15:a81a8d6c1dfe 494 #define PM_RCAUSE_EXT (0x1ul << PM_RCAUSE_EXT_Pos)
mbed_official 15:a81a8d6c1dfe 495 #define PM_RCAUSE_WDT_Pos 5 /**< \brief (PM_RCAUSE) Watchdog Reset */
mbed_official 15:a81a8d6c1dfe 496 #define PM_RCAUSE_WDT (0x1ul << PM_RCAUSE_WDT_Pos)
mbed_official 15:a81a8d6c1dfe 497 #define PM_RCAUSE_SYST_Pos 6 /**< \brief (PM_RCAUSE) System Reset Request */
mbed_official 15:a81a8d6c1dfe 498 #define PM_RCAUSE_SYST (0x1ul << PM_RCAUSE_SYST_Pos)
mbed_official 15:a81a8d6c1dfe 499 #define PM_RCAUSE_MASK 0x77ul /**< \brief (PM_RCAUSE) MASK Register */
mbed_official 15:a81a8d6c1dfe 500
mbed_official 15:a81a8d6c1dfe 501 /** \brief PM hardware registers */
mbed_official 15:a81a8d6c1dfe 502 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 503 typedef struct {
mbed_official 15:a81a8d6c1dfe 504 __IO PM_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 8) Control */
mbed_official 15:a81a8d6c1dfe 505 __IO PM_SLEEP_Type SLEEP; /**< \brief Offset: 0x01 (R/W 8) Sleep Mode */
mbed_official 15:a81a8d6c1dfe 506 RoReg8 Reserved1[0x6];
mbed_official 15:a81a8d6c1dfe 507 __IO PM_CPUSEL_Type CPUSEL; /**< \brief Offset: 0x08 (R/W 8) CPU Clock Select */
mbed_official 15:a81a8d6c1dfe 508 __IO PM_APBASEL_Type APBASEL; /**< \brief Offset: 0x09 (R/W 8) APBA Clock Select */
mbed_official 15:a81a8d6c1dfe 509 __IO PM_APBBSEL_Type APBBSEL; /**< \brief Offset: 0x0A (R/W 8) APBB Clock Select */
mbed_official 15:a81a8d6c1dfe 510 __IO PM_APBCSEL_Type APBCSEL; /**< \brief Offset: 0x0B (R/W 8) APBC Clock Select */
mbed_official 15:a81a8d6c1dfe 511 RoReg8 Reserved2[0x8];
mbed_official 15:a81a8d6c1dfe 512 __IO PM_AHBMASK_Type AHBMASK; /**< \brief Offset: 0x14 (R/W 32) AHB Mask */
mbed_official 15:a81a8d6c1dfe 513 __IO PM_APBAMASK_Type APBAMASK; /**< \brief Offset: 0x18 (R/W 32) APBA Mask */
mbed_official 15:a81a8d6c1dfe 514 __IO PM_APBBMASK_Type APBBMASK; /**< \brief Offset: 0x1C (R/W 32) APBB Mask */
mbed_official 15:a81a8d6c1dfe 515 __IO PM_APBCMASK_Type APBCMASK; /**< \brief Offset: 0x20 (R/W 32) APBC Mask */
mbed_official 15:a81a8d6c1dfe 516 RoReg8 Reserved3[0x10];
mbed_official 15:a81a8d6c1dfe 517 __IO PM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x34 (R/W 8) Interrupt Enable Clear */
mbed_official 15:a81a8d6c1dfe 518 __IO PM_INTENSET_Type INTENSET; /**< \brief Offset: 0x35 (R/W 8) Interrupt Enable Set */
mbed_official 15:a81a8d6c1dfe 519 __IO PM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x36 (R/W 8) Interrupt Flag Status and Clear */
mbed_official 15:a81a8d6c1dfe 520 RoReg8 Reserved4[0x1];
mbed_official 15:a81a8d6c1dfe 521 __I PM_RCAUSE_Type RCAUSE; /**< \brief Offset: 0x38 (R/ 8) Reset Cause */
mbed_official 15:a81a8d6c1dfe 522 } Pm;
mbed_official 15:a81a8d6c1dfe 523 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 524
mbed_official 15:a81a8d6c1dfe 525 /*@}*/
mbed_official 15:a81a8d6c1dfe 526
mbed_official 15:a81a8d6c1dfe 527 #endif /* _SAMR21_PM_COMPONENT_ */