John Karatka / mbed

mbed

Fork of mbed-dev by mbed official

targets/TARGET_STM/TARGET_STM32L0/i2c_device.h@182:57724642e740, 2018-02-16 (annotated)

Committer:
AnnaBridge
Date:
Fri Feb 16 16:09:33 2018 +0000
Revision:
182:57724642e740
Parent:
156:95d6b41a828b 
mbed-dev library. Release version 159.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 153:fa9ff456f731 1 /* mbed Microcontroller Library
<> 153:fa9ff456f731 2 *******************************************************************************
<> 153:fa9ff456f731 3 * Copyright (c) 2015, STMicroelectronics
<> 153:fa9ff456f731 4 * All rights reserved.
<> 153:fa9ff456f731 5 *
<> 153:fa9ff456f731 6 * Redistribution and use in source and binary forms, with or without
<> 153:fa9ff456f731 7 * modification, are permitted provided that the following conditions are met:
<> 153:fa9ff456f731 8 *
<> 153:fa9ff456f731 9 * 1. Redistributions of source code must retain the above copyright notice,
<> 153:fa9ff456f731 10 * this list of conditions and the following disclaimer.
<> 153:fa9ff456f731 11 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 153:fa9ff456f731 12 * this list of conditions and the following disclaimer in the documentation
<> 153:fa9ff456f731 13 * and/or other materials provided with the distribution.
<> 153:fa9ff456f731 14 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 153:fa9ff456f731 15 * may be used to endorse or promote products derived from this software
<> 153:fa9ff456f731 16 * without specific prior written permission.
<> 153:fa9ff456f731 17 *
<> 153:fa9ff456f731 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 153:fa9ff456f731 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 153:fa9ff456f731 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 153:fa9ff456f731 21 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 153:fa9ff456f731 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 153:fa9ff456f731 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 153:fa9ff456f731 24 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 153:fa9ff456f731 25 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 153:fa9ff456f731 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 153:fa9ff456f731 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 153:fa9ff456f731 28 *******************************************************************************
<> 153:fa9ff456f731 29 */
<> 153:fa9ff456f731 30 #ifndef MBED_I2C_DEVICE_H
<> 153:fa9ff456f731 31 #define MBED_I2C_DEVICE_H
<> 153:fa9ff456f731 32
<> 153:fa9ff456f731 33 #include "cmsis.h"
<> 153:fa9ff456f731 34
<> 153:fa9ff456f731 35 #ifdef __cplusplus
<> 153:fa9ff456f731 36 extern "C" {
<> 153:fa9ff456f731 37 #endif
<> 153:fa9ff456f731 38
<> 153:fa9ff456f731 39 #ifdef DEVICE_I2C
<> 153:fa9ff456f731 40
<> 153:fa9ff456f731 41 #define I2C_IP_VERSION_V2
<> 153:fa9ff456f731 42
<> 153:fa9ff456f731 43 #if defined I2C1_BASE
<> 153:fa9ff456f731 44 #define I2C1_EV_IRQn I2C1_IRQn
<> 153:fa9ff456f731 45 #define I2C1_ER_IRQn I2C1_IRQn
<> 153:fa9ff456f731 46 #endif
<> 153:fa9ff456f731 47 #if defined I2C2_BASE
<> 153:fa9ff456f731 48 #define I2C2_EV_IRQn I2C2_IRQn
<> 153:fa9ff456f731 49 #define I2C2_ER_IRQn I2C2_IRQn
<> 153:fa9ff456f731 50 #endif
<> 153:fa9ff456f731 51 #if defined I2C3_BASE
<> 153:fa9ff456f731 52 #define I2C3_EV_IRQn I2C3_IRQn
<> 153:fa9ff456f731 53 #define I2C3_ER_IRQn I2C3_IRQn
<> 153:fa9ff456f731 54 #endif
<> 153:fa9ff456f731 55
<> 153:fa9ff456f731 56 #define I2C_IT_ALL (I2C_IT_ERRI|I2C_IT_TCI|I2C_IT_STOPI|I2C_IT_NACKI|I2C_IT_ADDRI|I2C_IT_RXI|I2C_IT_TXI)
<> 153:fa9ff456f731 57
<> 153:fa9ff456f731 58 /* Family specifc settings for clock source */
<> 153:fa9ff456f731 59 #define I2CAPI_I2C1_CLKSRC RCC_I2C1CLKSOURCE_SYSCLK
<> 153:fa9ff456f731 60 #define I2CAPI_I2C3_CLKSRC RCC_I2C3CLKSOURCE_SYSCLK
<> 153:fa9ff456f731 61 #define I2CAPI_I2C4_CLKSRC RCC_I2C4CLKSOURCE_SYSCLK
<> 153:fa9ff456f731 62
<> 153:fa9ff456f731 63 /* Provide the suitable timing depending on requested frequencie */
<> 156:95d6b41a828b 64 static inline uint32_t get_i2c_timing(int hz)
<> 153:fa9ff456f731 65 {
<> 153:fa9ff456f731 66 uint32_t tim = 0;
<> 153:fa9ff456f731 67
<> 153:fa9ff456f731 68 switch (hz) {
<> 153:fa9ff456f731 69 case 100000:
<> 153:fa9ff456f731 70 tim = 0x20602938; // Standard mode with Rise Time = 400ns and Fall Time = 100ns
<> 153:fa9ff456f731 71 break;
<> 153:fa9ff456f731 72 case 400000:
<> 153:fa9ff456f731 73 tim = 0x00B0122A; // Fast mode with Rise Time = 250ns and Fall Time = 100ns
<> 153:fa9ff456f731 74 break;
<> 153:fa9ff456f731 75 case 1000000:
<> 153:fa9ff456f731 76 tim = 0x0030040E; // Fast mode Plus with Rise Time = 60ns and Fall Time = 100ns
<> 153:fa9ff456f731 77 break;
<> 153:fa9ff456f731 78 default:
<> 153:fa9ff456f731 79 break;
<> 153:fa9ff456f731 80 }
<> 153:fa9ff456f731 81 return tim;
<> 153:fa9ff456f731 82 }
<> 153:fa9ff456f731 83
<> 153:fa9ff456f731 84 #ifdef __cplusplus
<> 153:fa9ff456f731 85 }
<> 153:fa9ff456f731 86 #endif
<> 153:fa9ff456f731 87
<> 153:fa9ff456f731 88 #endif // DEVICE_I2C
<> 153:fa9ff456f731 89
<> 153:fa9ff456f731 90 #endif