John Karatka / mbed

mbed

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targets/TARGET_ONSEMI/TARGET_NCS36510/rtc_map.h@182:57724642e740, 2018-02-16 (annotated)

Committer:
AnnaBridge
Date:
Fri Feb 16 16:09:33 2018 +0000
Revision:
182:57724642e740
Parent:
150:02e0a0aed4ec 
mbed-dev library. Release version 159.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 149:156823d33999 1 /**
<> 149:156823d33999 2 ******************************************************************************
<> 149:156823d33999 3 * @file rtc_map.h
<> 149:156823d33999 4 * @brief Real Time Clock HW register map
<> 149:156823d33999 5 * @internal
<> 149:156823d33999 6 * @author ON Semiconductor.
<> 149:156823d33999 7 * $Rev: 3008 $
<> 149:156823d33999 8 * $Date: 2014-10-16 18:42:48 +0530 (Thu, 16 Oct 2014) $
<> 149:156823d33999 9 ******************************************************************************
<> 149:156823d33999 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
<> 149:156823d33999 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
<> 149:156823d33999 12 * under limited terms and conditions. The terms and conditions pertaining to the software
<> 149:156823d33999 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
<> 149:156823d33999 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
<> 149:156823d33999 15 * if applicable the software license agreement. Do not use this software and/or
<> 149:156823d33999 16 * documentation unless you have carefully read and you agree to the limited terms and
<> 149:156823d33999 17 * conditions. By using this software and/or documentation, you agree to the limited
<> 149:156823d33999 18 * terms and conditions.
<> 149:156823d33999 19 *
<> 149:156823d33999 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
<> 149:156823d33999 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
<> 149:156823d33999 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
<> 149:156823d33999 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
<> 149:156823d33999 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
<> 149:156823d33999 25 * @endinternal
<> 149:156823d33999 26 *
<> 149:156823d33999 27 * @ingroup rtc
<> 149:156823d33999 28 *
<> 149:156823d33999 29 * @details
<> 149:156823d33999 30 * <p>
<> 149:156823d33999 31 * Teal Time Clock HW register map description
<> 149:156823d33999 32 * </p>
<> 149:156823d33999 33 *
<> 149:156823d33999 34 * <h1> Reference document(s) </h1>
<> 149:156823d33999 35 * <p>
<> 149:156823d33999 36 * <a HOURef="../pdf/IPC7206_RTC_APB_DS_v1P0.pdf" target="_blank">
<> 149:156823d33999 37 * IPC7206 APB RTC Design Specification v1.0 </a>
<> 149:156823d33999 38 * </p>
<> 149:156823d33999 39 */
<> 149:156823d33999 40
<> 149:156823d33999 41 #ifndef RTC_MAP_H_
<> 149:156823d33999 42 #define RTC_MAP_H_
<> 149:156823d33999 43
<> 149:156823d33999 44 #include "architecture.h"
<> 149:156823d33999 45
<> 149:156823d33999 46 /** Real Time Clock Control HW Structure Overlay */
<> 149:156823d33999 47 typedef struct {
<> 149:156823d33999 48 __IO uint32_t SUB_SECOND_COUNTER; /**<SUB SECOND Counter */ /* 0x4000F000 */
<> 149:156823d33999 49 __IO uint32_t SECOND_COUNTER; /**<SECOND Counter */ /* 0x4000F004 */
<> 149:156823d33999 50 __IO uint32_t SUB_SECOND_ALARM; /**< SUB SECOND alarm */ /* 0x4000F008 */
<> 149:156823d33999 51 __IO uint32_t SECOND_ALARM; /**< SECOND alarm */ /* 0x4000F00c */
<> 149:156823d33999 52 union {
<> 149:156823d33999 53 struct {
<> 149:156823d33999 54 __IO uint32_t SUB_SEC_COUNTER_EN :1; /**<Sub-second counter enable. (1=count is enabled, 0=retain count value) */
<> 149:156823d33999 55 __IO uint32_t SEC_COUNTER_EN :1; /**<Second counter enable. (1=count is enabled, 0=retain count value) */
<> 149:156823d33999 56 __IO uint32_t SUB_SECOND_INT_EN :1; /**<Sub-second interrupt enable (1=interrupt enabled, 0=interrupt disabled) */
<> 149:156823d33999 57 __IO uint32_t SECOND_INT_EN :1; /**<Second interrupt enable (1=interrupt enabled, 0=interrupt disabled) */
<> 149:156823d33999 58 } BITS;
<> 149:156823d33999 59 __IO uint32_t WORD;
<> 149:156823d33999 60 } CONTROL; /* 0x4000F010 */
<> 149:156823d33999 61 union {
<> 149:156823d33999 62 struct {
<> 149:156823d33999 63 /**<Any write to the status register will clear the error bit. */
<> 149:156823d33999 64 __IO uint32_t SUB_SECOND_INT:1; /**<Sub-second interrupt status. (1=interrupt active, 0=no interrupt)*/
<> 149:156823d33999 65 __IO uint32_t SECOND_INT :1; /**<Second interrupt status. (1=interrupt active, 0=no interrupt)*/
<> 149:156823d33999 66 __IO uint32_t WRITE_ERROR :1; /**<Reads error bit which is set when a write occurs before a previous write to the same register has completed. */
<> 149:156823d33999 67 __IO uint32_t BSY_ANY_WRT :1; /**<Busy with any write.*/
<> 149:156823d33999 68 __IO uint32_t BSY_SUB_SEC_CNTR_REG_WRT :1; /**<Busy with a sub-second counter register write.*/
<> 149:156823d33999 69 __IO uint32_t BSY_SEC_CNTR_REG_WRT :1; /**<Busy with a second counter register write.*/
<> 149:156823d33999 70 __IO uint32_t BSY_SUB_SEC_ALRM_REG_WRT :1; /**<Busy with a sub-second alarm register write.*/
<> 149:156823d33999 71 __IO uint32_t BSY_SEC_ALRM_REG_WRT:1; /**<Busy with a second alarm register write.*/
<> 149:156823d33999 72 __IO uint32_t BSY_CTRL_REG_WRT :1; /**<Busy with a control register write.*/
<> 149:156823d33999 73 __IO uint32_t BSY_SUB_SEC_INT_CLR_WRT :1; /**<Busy with a sub-second interrupt clear write.*/
<> 149:156823d33999 74 __IO uint32_t BSY_SEC_INT_CLR_WRT :1; /**<Busy with a second interrupt clear write.*/
<> 149:156823d33999 75 } BITS;
<> 149:156823d33999 76 __IO uint32_t WORD;
<> 149:156823d33999 77 } STATUS; /* 0x4000F014 */
<> 149:156823d33999 78 union {
<> 149:156823d33999 79 struct {
<> 149:156823d33999 80 __O uint32_t SUB_SECOND :1; /**<Write 1 to this register to clear the sub-second interrupt.*/
<> 149:156823d33999 81 __O uint32_t SECOND :1; /**<Write 1 to this register to clear the second interrupt.*/
<> 149:156823d33999 82 } BITS;
<> 149:156823d33999 83 __O uint32_t WORD;
<> 149:156823d33999 84 } INT_CLEAR; /* 0x4000F018 */
<> 149:156823d33999 85 } RtcReg_t, *RtcReg_pt;
<> 149:156823d33999 86
<> 149:156823d33999 87 #endif /* RTC_MAP_H_ */