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targets/TARGET_NUVOTON/TARGET_NANO100/spi_api.c@182:57724642e740, 2018-02-16 (annotated)

Committer:
AnnaBridge
Date:
Fri Feb 16 16:09:33 2018 +0000
Revision:
182:57724642e740
Parent:
177:447f873cad2f 
mbed-dev library. Release version 159.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 175:b96e65c34a4d 1 /* mbed Microcontroller Library
AnnaBridge 175:b96e65c34a4d 2 * Copyright (c) 2015-2017 Nuvoton
AnnaBridge 175:b96e65c34a4d 3 *
AnnaBridge 175:b96e65c34a4d 4 * Licensed under the Apache License, Version 2.0 (the "License");
AnnaBridge 175:b96e65c34a4d 5 * you may not use this file except in compliance with the License.
AnnaBridge 175:b96e65c34a4d 6 * You may obtain a copy of the License at
AnnaBridge 175:b96e65c34a4d 7 *
AnnaBridge 175:b96e65c34a4d 8 * http://www.apache.org/licenses/LICENSE-2.0
AnnaBridge 175:b96e65c34a4d 9 *
AnnaBridge 175:b96e65c34a4d 10 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 175:b96e65c34a4d 11 * distributed under the License is distributed on an "AS IS" BASIS,
AnnaBridge 175:b96e65c34a4d 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 175:b96e65c34a4d 13 * See the License for the specific language governing permissions and
AnnaBridge 175:b96e65c34a4d 14 * limitations under the License.
AnnaBridge 175:b96e65c34a4d 15 */
AnnaBridge 175:b96e65c34a4d 16
AnnaBridge 175:b96e65c34a4d 17 #include "spi_api.h"
AnnaBridge 175:b96e65c34a4d 18
AnnaBridge 175:b96e65c34a4d 19 #if DEVICE_SPI
AnnaBridge 175:b96e65c34a4d 20
AnnaBridge 175:b96e65c34a4d 21 #include "cmsis.h"
AnnaBridge 175:b96e65c34a4d 22 #include "pinmap.h"
AnnaBridge 175:b96e65c34a4d 23 #include "PeripheralPins.h"
AnnaBridge 175:b96e65c34a4d 24 #include "nu_modutil.h"
AnnaBridge 175:b96e65c34a4d 25 #include "nu_miscutil.h"
AnnaBridge 175:b96e65c34a4d 26 #include "nu_bitutil.h"
AnnaBridge 175:b96e65c34a4d 27
AnnaBridge 175:b96e65c34a4d 28 #if DEVICE_SPI_ASYNCH
AnnaBridge 175:b96e65c34a4d 29 #include "dma_api.h"
AnnaBridge 175:b96e65c34a4d 30 #include "dma.h"
AnnaBridge 175:b96e65c34a4d 31 #endif
AnnaBridge 175:b96e65c34a4d 32
AnnaBridge 175:b96e65c34a4d 33 #define NU_SPI_FRAME_MIN 8
AnnaBridge 175:b96e65c34a4d 34 #define NU_SPI_FRAME_MAX 32
AnnaBridge 175:b96e65c34a4d 35 #define NU_SPI_FIFO_DEPTH 8
AnnaBridge 175:b96e65c34a4d 36
AnnaBridge 175:b96e65c34a4d 37 struct nu_spi_var {
AnnaBridge 175:b96e65c34a4d 38 spi_t * obj;
AnnaBridge 175:b96e65c34a4d 39 void (*vec)(void);
AnnaBridge 175:b96e65c34a4d 40 #if DEVICE_SPI_ASYNCH
AnnaBridge 175:b96e65c34a4d 41 uint8_t pdma_perp_tx;
AnnaBridge 175:b96e65c34a4d 42 uint8_t pdma_perp_rx;
AnnaBridge 175:b96e65c34a4d 43 #endif
AnnaBridge 175:b96e65c34a4d 44 };
AnnaBridge 175:b96e65c34a4d 45
AnnaBridge 175:b96e65c34a4d 46 // NOTE:
AnnaBridge 175:b96e65c34a4d 47 // NANO130: No support for relocating vector table. ISR vector passed into NVIC_SetVector() can only be weak symbol defined in startup_Nano100Series.c.
AnnaBridge 175:b96e65c34a4d 48 void SPI0_IRQHandler(void);
AnnaBridge 175:b96e65c34a4d 49 void SPI1_IRQHandler(void);
AnnaBridge 175:b96e65c34a4d 50 void SPI2_IRQHandler(void);
AnnaBridge 175:b96e65c34a4d 51 static void spi_irq(spi_t *obj);
AnnaBridge 175:b96e65c34a4d 52
AnnaBridge 175:b96e65c34a4d 53 static struct nu_spi_var spi0_var = {
AnnaBridge 175:b96e65c34a4d 54 .obj = NULL,
AnnaBridge 175:b96e65c34a4d 55 .vec = SPI0_IRQHandler,
AnnaBridge 175:b96e65c34a4d 56 #if DEVICE_SPI_ASYNCH
AnnaBridge 175:b96e65c34a4d 57 .pdma_perp_tx = PDMA_SPI0_TX,
AnnaBridge 175:b96e65c34a4d 58 .pdma_perp_rx = PDMA_SPI0_RX
AnnaBridge 175:b96e65c34a4d 59 #endif
AnnaBridge 175:b96e65c34a4d 60 };
AnnaBridge 175:b96e65c34a4d 61 static struct nu_spi_var spi1_var = {
AnnaBridge 175:b96e65c34a4d 62 .obj = NULL,
AnnaBridge 175:b96e65c34a4d 63 .vec = SPI1_IRQHandler,
AnnaBridge 175:b96e65c34a4d 64 #if DEVICE_SPI_ASYNCH
AnnaBridge 175:b96e65c34a4d 65 .pdma_perp_tx = PDMA_SPI1_TX,
AnnaBridge 175:b96e65c34a4d 66 .pdma_perp_rx = PDMA_SPI1_RX
AnnaBridge 175:b96e65c34a4d 67 #endif
AnnaBridge 175:b96e65c34a4d 68 };
AnnaBridge 175:b96e65c34a4d 69 static struct nu_spi_var spi2_var = {
AnnaBridge 175:b96e65c34a4d 70 .obj = NULL,
AnnaBridge 175:b96e65c34a4d 71 .vec = SPI2_IRQHandler,
AnnaBridge 175:b96e65c34a4d 72 #if DEVICE_SPI_ASYNCH
AnnaBridge 175:b96e65c34a4d 73 .pdma_perp_tx = PDMA_SPI2_TX,
AnnaBridge 175:b96e65c34a4d 74 .pdma_perp_rx = PDMA_SPI2_RX
AnnaBridge 175:b96e65c34a4d 75 #endif
AnnaBridge 175:b96e65c34a4d 76 };
AnnaBridge 175:b96e65c34a4d 77
AnnaBridge 175:b96e65c34a4d 78 #if DEVICE_SPI_ASYNCH
AnnaBridge 175:b96e65c34a4d 79 static void spi_enable_vector_interrupt(spi_t *obj, uint32_t handler, uint8_t enable);
AnnaBridge 175:b96e65c34a4d 80 static void spi_master_enable_interrupt(spi_t *obj, uint8_t enable, uint32_t mask);
AnnaBridge 175:b96e65c34a4d 81 static uint32_t spi_master_write_asynch(spi_t *obj, uint32_t tx_limit);
AnnaBridge 175:b96e65c34a4d 82 static uint32_t spi_master_read_asynch(spi_t *obj);
AnnaBridge 175:b96e65c34a4d 83 static uint32_t spi_event_check(spi_t *obj);
AnnaBridge 175:b96e65c34a4d 84 static void spi_enable_event(spi_t *obj, uint32_t event, uint8_t enable);
AnnaBridge 175:b96e65c34a4d 85 static void spi_buffer_set(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length);
AnnaBridge 175:b96e65c34a4d 86 static void spi_check_dma_usage(DMAUsage *dma_usage, int *dma_ch_tx, int *dma_ch_rx);
AnnaBridge 175:b96e65c34a4d 87 static uint8_t spi_get_data_width(spi_t *obj);
AnnaBridge 175:b96e65c34a4d 88 static int spi_is_tx_complete(spi_t *obj);
AnnaBridge 175:b96e65c34a4d 89 static int spi_is_rx_complete(spi_t *obj);
AnnaBridge 175:b96e65c34a4d 90 static int spi_writeable(spi_t * obj);
AnnaBridge 175:b96e65c34a4d 91 static int spi_readable(spi_t * obj);
AnnaBridge 175:b96e65c34a4d 92 static void spi_dma_handler_tx(uint32_t id, uint32_t event_dma);
AnnaBridge 175:b96e65c34a4d 93 static void spi_dma_handler_rx(uint32_t id, uint32_t event_dma);
AnnaBridge 175:b96e65c34a4d 94 #endif
AnnaBridge 175:b96e65c34a4d 95
AnnaBridge 175:b96e65c34a4d 96 static uint32_t spi_modinit_mask = 0;
AnnaBridge 175:b96e65c34a4d 97
AnnaBridge 175:b96e65c34a4d 98 static const struct nu_modinit_s spi_modinit_tab[] = {
AnnaBridge 175:b96e65c34a4d 99 {SPI_0, SPI0_MODULE, CLK_CLKSEL2_SPI0_S_HCLK, MODULE_NoMsk, SPI0_RST, SPI0_IRQn, &spi0_var},
AnnaBridge 175:b96e65c34a4d 100 {SPI_1, SPI1_MODULE, CLK_CLKSEL2_SPI1_S_HCLK, MODULE_NoMsk, SPI1_RST, SPI1_IRQn, &spi1_var},
AnnaBridge 175:b96e65c34a4d 101 {SPI_2, SPI2_MODULE, CLK_CLKSEL2_SPI2_S_HCLK, MODULE_NoMsk, SPI2_RST, SPI2_IRQn, &spi2_var},
AnnaBridge 175:b96e65c34a4d 102
AnnaBridge 175:b96e65c34a4d 103 {NC, 0, 0, 0, 0, (IRQn_Type) 0, NULL}
AnnaBridge 175:b96e65c34a4d 104 };
AnnaBridge 175:b96e65c34a4d 105
AnnaBridge 175:b96e65c34a4d 106 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
AnnaBridge 175:b96e65c34a4d 107 // Determine which SPI_x the pins are used for
AnnaBridge 175:b96e65c34a4d 108 uint32_t spi_mosi = pinmap_peripheral(mosi, PinMap_SPI_MOSI);
AnnaBridge 175:b96e65c34a4d 109 uint32_t spi_miso = pinmap_peripheral(miso, PinMap_SPI_MISO);
AnnaBridge 175:b96e65c34a4d 110 uint32_t spi_sclk = pinmap_peripheral(sclk, PinMap_SPI_SCLK);
AnnaBridge 175:b96e65c34a4d 111 uint32_t spi_ssel = pinmap_peripheral(ssel, PinMap_SPI_SSEL);
AnnaBridge 175:b96e65c34a4d 112 uint32_t spi_data = pinmap_merge(spi_mosi, spi_miso);
AnnaBridge 175:b96e65c34a4d 113 uint32_t spi_cntl = pinmap_merge(spi_sclk, spi_ssel);
AnnaBridge 175:b96e65c34a4d 114 // NOTE:
AnnaBridge 175:b96e65c34a4d 115 // NANO130: Support two-port SPI MOSI/MISO 0/1
AnnaBridge 175:b96e65c34a4d 116 if (NU_MODBASE(spi_data) == NU_MODBASE(spi_cntl)) {
AnnaBridge 175:b96e65c34a4d 117 // NOTE: spi_data has subindex(port) encoded but spi_cntl hasn't.
AnnaBridge 175:b96e65c34a4d 118 obj->spi.spi = (SPIName) spi_data;
AnnaBridge 175:b96e65c34a4d 119 }
AnnaBridge 175:b96e65c34a4d 120 else {
AnnaBridge 175:b96e65c34a4d 121 obj->spi.spi = (SPIName) NC;
AnnaBridge 175:b96e65c34a4d 122 }
AnnaBridge 175:b96e65c34a4d 123 MBED_ASSERT((int)obj->spi.spi != NC);
AnnaBridge 175:b96e65c34a4d 124
AnnaBridge 175:b96e65c34a4d 125 const struct nu_modinit_s *modinit = get_modinit(obj->spi.spi, spi_modinit_tab);
AnnaBridge 175:b96e65c34a4d 126 MBED_ASSERT(modinit != NULL);
AnnaBridge 175:b96e65c34a4d 127 MBED_ASSERT((SPIName) modinit->modname == obj->spi.spi);
AnnaBridge 175:b96e65c34a4d 128
AnnaBridge 175:b96e65c34a4d 129 // Reset this module
AnnaBridge 175:b96e65c34a4d 130 SYS_ResetModule(modinit->rsetidx);
AnnaBridge 175:b96e65c34a4d 131
AnnaBridge 175:b96e65c34a4d 132 // Select IP clock source
AnnaBridge 175:b96e65c34a4d 133 CLK_SetModuleClock(modinit->clkidx, modinit->clksrc, modinit->clkdiv);
AnnaBridge 175:b96e65c34a4d 134 // Enable IP clock
AnnaBridge 175:b96e65c34a4d 135 CLK_EnableModuleClock(modinit->clkidx);
AnnaBridge 175:b96e65c34a4d 136
AnnaBridge 175:b96e65c34a4d 137 pinmap_pinout(mosi, PinMap_SPI_MOSI);
AnnaBridge 175:b96e65c34a4d 138 pinmap_pinout(miso, PinMap_SPI_MISO);
AnnaBridge 175:b96e65c34a4d 139 pinmap_pinout(sclk, PinMap_SPI_SCLK);
AnnaBridge 175:b96e65c34a4d 140 pinmap_pinout(ssel, PinMap_SPI_SSEL);
AnnaBridge 175:b96e65c34a4d 141
AnnaBridge 175:b96e65c34a4d 142 obj->spi.pin_mosi = mosi;
AnnaBridge 175:b96e65c34a4d 143 obj->spi.pin_miso = miso;
AnnaBridge 175:b96e65c34a4d 144 obj->spi.pin_sclk = sclk;
AnnaBridge 175:b96e65c34a4d 145 obj->spi.pin_ssel = ssel;
AnnaBridge 175:b96e65c34a4d 146
AnnaBridge 175:b96e65c34a4d 147
AnnaBridge 175:b96e65c34a4d 148 #if DEVICE_SPI_ASYNCH
AnnaBridge 175:b96e65c34a4d 149 obj->spi.dma_usage = DMA_USAGE_NEVER;
AnnaBridge 175:b96e65c34a4d 150 obj->spi.event = 0;
AnnaBridge 175:b96e65c34a4d 151 obj->spi.dma_chn_id_tx = DMA_ERROR_OUT_OF_CHANNELS;
AnnaBridge 175:b96e65c34a4d 152 obj->spi.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS;
AnnaBridge 175:b96e65c34a4d 153 #endif
AnnaBridge 175:b96e65c34a4d 154
AnnaBridge 175:b96e65c34a4d 155 // Mark this module to be inited.
AnnaBridge 175:b96e65c34a4d 156 int i = modinit - spi_modinit_tab;
AnnaBridge 175:b96e65c34a4d 157 spi_modinit_mask |= 1 << i;
AnnaBridge 175:b96e65c34a4d 158 }
AnnaBridge 175:b96e65c34a4d 159
AnnaBridge 175:b96e65c34a4d 160 void spi_free(spi_t *obj)
AnnaBridge 175:b96e65c34a4d 161 {
AnnaBridge 175:b96e65c34a4d 162 #if DEVICE_SPI_ASYNCH
AnnaBridge 175:b96e65c34a4d 163 if (obj->spi.dma_chn_id_tx != DMA_ERROR_OUT_OF_CHANNELS) {
AnnaBridge 175:b96e65c34a4d 164 dma_channel_free(obj->spi.dma_chn_id_tx);
AnnaBridge 175:b96e65c34a4d 165 obj->spi.dma_chn_id_tx = DMA_ERROR_OUT_OF_CHANNELS;
AnnaBridge 175:b96e65c34a4d 166 }
AnnaBridge 175:b96e65c34a4d 167 if (obj->spi.dma_chn_id_rx != DMA_ERROR_OUT_OF_CHANNELS) {
AnnaBridge 175:b96e65c34a4d 168 dma_channel_free(obj->spi.dma_chn_id_rx);
AnnaBridge 175:b96e65c34a4d 169 obj->spi.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS;
AnnaBridge 175:b96e65c34a4d 170 }
AnnaBridge 175:b96e65c34a4d 171 #endif
AnnaBridge 175:b96e65c34a4d 172
AnnaBridge 175:b96e65c34a4d 173 SPI_Close((SPI_T *) NU_MODBASE(obj->spi.spi));
AnnaBridge 175:b96e65c34a4d 174
AnnaBridge 175:b96e65c34a4d 175 const struct nu_modinit_s *modinit = get_modinit(obj->spi.spi, spi_modinit_tab);
AnnaBridge 175:b96e65c34a4d 176 MBED_ASSERT(modinit != NULL);
AnnaBridge 175:b96e65c34a4d 177 MBED_ASSERT((SPIName) modinit->modname == obj->spi.spi);
AnnaBridge 175:b96e65c34a4d 178 SPI_DisableInt(((SPI_T *) NU_MODBASE(obj->spi.spi)), (SPI_FIFO_RXOVR_INTEN_MASK | SPI_FIFO_RX_INTEN_MASK | SPI_FIFO_TX_INTEN_MASK));
AnnaBridge 175:b96e65c34a4d 179 NVIC_DisableIRQ(modinit->irq_n);
AnnaBridge 175:b96e65c34a4d 180
AnnaBridge 175:b96e65c34a4d 181 // Disable IP clock
AnnaBridge 175:b96e65c34a4d 182 CLK_DisableModuleClock(modinit->clkidx);
AnnaBridge 175:b96e65c34a4d 183
AnnaBridge 175:b96e65c34a4d 184 // Mark this module to be deinited.
AnnaBridge 175:b96e65c34a4d 185 int i = modinit - spi_modinit_tab;
AnnaBridge 175:b96e65c34a4d 186 spi_modinit_mask &= ~(1 << i);
AnnaBridge 175:b96e65c34a4d 187 }
AnnaBridge 175:b96e65c34a4d 188 void spi_format(spi_t *obj, int bits, int mode, int slave)
AnnaBridge 175:b96e65c34a4d 189 {
AnnaBridge 175:b96e65c34a4d 190 MBED_ASSERT(bits >= NU_SPI_FRAME_MIN && bits <= NU_SPI_FRAME_MAX);
AnnaBridge 175:b96e65c34a4d 191
AnnaBridge 175:b96e65c34a4d 192 SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
AnnaBridge 175:b96e65c34a4d 193
AnnaBridge 175:b96e65c34a4d 194 // NOTE: All configurations should be ready before enabling SPI peripheral.
AnnaBridge 175:b96e65c34a4d 195 // NOTE: Re-configuration is allowed only as SPI peripheral is idle.
AnnaBridge 175:b96e65c34a4d 196 // NOTE:
AnnaBridge 175:b96e65c34a4d 197 // NANO130, SPI_CTL.GO_BUSY always reads as 1 in slave/FIFO mode. So disable FIFO first.
AnnaBridge 175:b96e65c34a4d 198 SPI_DisableFIFO(spi_base);
AnnaBridge 175:b96e65c34a4d 199 while (SPI_IS_BUSY(spi_base));
AnnaBridge 175:b96e65c34a4d 200
AnnaBridge 175:b96e65c34a4d 201
AnnaBridge 175:b96e65c34a4d 202 SPI_Open(spi_base,
AnnaBridge 175:b96e65c34a4d 203 slave ? SPI_SLAVE : SPI_MASTER,
AnnaBridge 175:b96e65c34a4d 204 (mode == 0) ? SPI_MODE_0 : (mode == 1) ? SPI_MODE_1 : (mode == 2) ? SPI_MODE_2 : SPI_MODE_3,
AnnaBridge 175:b96e65c34a4d 205 bits,
AnnaBridge 175:b96e65c34a4d 206 SPI_GetBusClock(spi_base));
AnnaBridge 175:b96e65c34a4d 207 // NOTE: Hardcode to be MSB first.
AnnaBridge 175:b96e65c34a4d 208 SPI_SET_MSB_FIRST(spi_base);
AnnaBridge 175:b96e65c34a4d 209
AnnaBridge 175:b96e65c34a4d 210 if (! slave) {
AnnaBridge 175:b96e65c34a4d 211 // Master
AnnaBridge 175:b96e65c34a4d 212 if (obj->spi.pin_ssel != NC) {
AnnaBridge 175:b96e65c34a4d 213 // Configure SS as low active.
AnnaBridge 175:b96e65c34a4d 214 switch (NU_MODSUBINDEX(obj->spi.spi)) {
AnnaBridge 175:b96e65c34a4d 215 case 0:
AnnaBridge 175:b96e65c34a4d 216 SPI_EnableAutoSS(spi_base, SPI_SS0, SPI_SS0_ACTIVE_LOW);
AnnaBridge 175:b96e65c34a4d 217 break;
AnnaBridge 175:b96e65c34a4d 218
AnnaBridge 175:b96e65c34a4d 219 case 1:
AnnaBridge 175:b96e65c34a4d 220 SPI_EnableAutoSS(spi_base, SPI_SS1, SPI_SS1_ACTIVE_LOW);
AnnaBridge 175:b96e65c34a4d 221 break;
AnnaBridge 175:b96e65c34a4d 222 }
AnnaBridge 175:b96e65c34a4d 223 }
AnnaBridge 175:b96e65c34a4d 224 else {
AnnaBridge 175:b96e65c34a4d 225 SPI_DisableAutoSS(spi_base);
AnnaBridge 175:b96e65c34a4d 226 }
AnnaBridge 175:b96e65c34a4d 227 }
AnnaBridge 175:b96e65c34a4d 228 else {
AnnaBridge 175:b96e65c34a4d 229 // Slave
AnnaBridge 175:b96e65c34a4d 230 // Configure SS as low active.
AnnaBridge 175:b96e65c34a4d 231 switch (NU_MODSUBINDEX(obj->spi.spi)) {
AnnaBridge 175:b96e65c34a4d 232 case 0:
AnnaBridge 175:b96e65c34a4d 233 spi_base->SSR &= ~SPI_SS0_ACTIVE_HIGH;
AnnaBridge 175:b96e65c34a4d 234 break;
AnnaBridge 175:b96e65c34a4d 235 case 1:
AnnaBridge 175:b96e65c34a4d 236 spi_base->SSR &= ~SPI_SS1_ACTIVE_HIGH;
AnnaBridge 175:b96e65c34a4d 237 break;
AnnaBridge 175:b96e65c34a4d 238 }
AnnaBridge 175:b96e65c34a4d 239 // NOTE:
AnnaBridge 175:b96e65c34a4d 240 // NANO130: Configure slave select signal to edge-trigger rather than level-trigger
AnnaBridge 175:b96e65c34a4d 241 spi_base->SSR |= SPI_SSR_SS_LTRIG_Msk;
AnnaBridge 175:b96e65c34a4d 242 }
AnnaBridge 175:b96e65c34a4d 243
AnnaBridge 175:b96e65c34a4d 244 // NOTE:
AnnaBridge 175:b96e65c34a4d 245 // NANO130: FIFO mode defaults to disabled.
AnnaBridge 175:b96e65c34a4d 246 SPI_EnableFIFO(spi_base, NU_SPI_FIFO_DEPTH / 2, NU_SPI_FIFO_DEPTH / 2);
AnnaBridge 175:b96e65c34a4d 247 }
AnnaBridge 175:b96e65c34a4d 248
AnnaBridge 175:b96e65c34a4d 249 void spi_frequency(spi_t *obj, int hz)
AnnaBridge 175:b96e65c34a4d 250 {
AnnaBridge 175:b96e65c34a4d 251 SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
AnnaBridge 175:b96e65c34a4d 252
AnnaBridge 175:b96e65c34a4d 253 // NANO130, SPI_CTL.GO_BUSY always reads as 1 in slave/FIFO mode. So disable FIFO first.
AnnaBridge 175:b96e65c34a4d 254 SPI_DisableFIFO(spi_base);
AnnaBridge 175:b96e65c34a4d 255 while (SPI_IS_BUSY(spi_base));
AnnaBridge 175:b96e65c34a4d 256
AnnaBridge 175:b96e65c34a4d 257 SPI_SetBusClock((SPI_T *) NU_MODBASE(obj->spi.spi), hz);
AnnaBridge 175:b96e65c34a4d 258
AnnaBridge 175:b96e65c34a4d 259 // NOTE:
AnnaBridge 175:b96e65c34a4d 260 // NANO130: FIFO mode defaults to disabled.
AnnaBridge 175:b96e65c34a4d 261 SPI_EnableFIFO(spi_base, NU_SPI_FIFO_DEPTH / 2, NU_SPI_FIFO_DEPTH / 2);
AnnaBridge 175:b96e65c34a4d 262 }
AnnaBridge 175:b96e65c34a4d 263
AnnaBridge 175:b96e65c34a4d 264
AnnaBridge 175:b96e65c34a4d 265 int spi_master_write(spi_t *obj, int value)
AnnaBridge 175:b96e65c34a4d 266 {
AnnaBridge 175:b96e65c34a4d 267 SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
AnnaBridge 175:b96e65c34a4d 268
AnnaBridge 175:b96e65c34a4d 269 // NOTE: Data in receive FIFO can be read out via ICE.
AnnaBridge 175:b96e65c34a4d 270 // NOTE:
AnnaBridge 175:b96e65c34a4d 271 // NUC472/M453/M487: SPI_CTL.SPIEN is controlled by software (in FIFO mode).
AnnaBridge 175:b96e65c34a4d 272 // NANO130: SPI_CTL.GO_BUSY is controlled by hardware in FIFO mode.
AnnaBridge 175:b96e65c34a4d 273
AnnaBridge 175:b96e65c34a4d 274 // Wait for tx buffer empty
AnnaBridge 175:b96e65c34a4d 275 while(! spi_writeable(obj));
AnnaBridge 175:b96e65c34a4d 276 uint32_t TX = (NU_MODSUBINDEX(obj->spi.spi) == 0) ? ((uint32_t) &spi_base->TX0) : ((uint32_t) &spi_base->TX1);
AnnaBridge 175:b96e65c34a4d 277 M32(TX) = value;
AnnaBridge 175:b96e65c34a4d 278
AnnaBridge 175:b96e65c34a4d 279 // Wait for rx buffer full
AnnaBridge 175:b96e65c34a4d 280 while (! spi_readable(obj));
AnnaBridge 175:b96e65c34a4d 281 uint32_t RX = (NU_MODSUBINDEX(obj->spi.spi) == 0) ? ((uint32_t) &spi_base->RX0) : ((uint32_t) &spi_base->RX1);
AnnaBridge 175:b96e65c34a4d 282 int value2 = M32(RX);
AnnaBridge 175:b96e65c34a4d 283
AnnaBridge 175:b96e65c34a4d 284 return value2;
AnnaBridge 175:b96e65c34a4d 285 }
AnnaBridge 175:b96e65c34a4d 286
AnnaBridge 175:b96e65c34a4d 287 int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
AnnaBridge 175:b96e65c34a4d 288 char *rx_buffer, int rx_length, char write_fill)
AnnaBridge 175:b96e65c34a4d 289 {
AnnaBridge 175:b96e65c34a4d 290 int total = (tx_length > rx_length) ? tx_length : rx_length;
AnnaBridge 175:b96e65c34a4d 291
AnnaBridge 175:b96e65c34a4d 292 for (int i = 0; i < total; i++) {
AnnaBridge 175:b96e65c34a4d 293 char out = (i < tx_length) ? tx_buffer[i] : write_fill;
AnnaBridge 175:b96e65c34a4d 294 char in = spi_master_write(obj, out);
AnnaBridge 175:b96e65c34a4d 295 if (i < rx_length) {
AnnaBridge 175:b96e65c34a4d 296 rx_buffer[i] = in;
AnnaBridge 175:b96e65c34a4d 297 }
AnnaBridge 175:b96e65c34a4d 298 }
AnnaBridge 175:b96e65c34a4d 299
AnnaBridge 175:b96e65c34a4d 300 return total;
AnnaBridge 175:b96e65c34a4d 301 }
AnnaBridge 175:b96e65c34a4d 302
AnnaBridge 175:b96e65c34a4d 303 #if DEVICE_SPISLAVE
AnnaBridge 175:b96e65c34a4d 304 int spi_slave_receive(spi_t *obj)
AnnaBridge 175:b96e65c34a4d 305 {
AnnaBridge 175:b96e65c34a4d 306 // NOTE:
AnnaBridge 175:b96e65c34a4d 307 // NUC472/M453/M487: SPI_CTL.SPIEN is controlled by software (in FIFO mode).
AnnaBridge 175:b96e65c34a4d 308 // NANO130: SPI_CTL.GO_BUSY is controlled by hardware in FIFO mode.
AnnaBridge 175:b96e65c34a4d 309
AnnaBridge 175:b96e65c34a4d 310 return spi_readable(obj);
AnnaBridge 175:b96e65c34a4d 311 };
AnnaBridge 175:b96e65c34a4d 312
AnnaBridge 175:b96e65c34a4d 313 int spi_slave_read(spi_t *obj)
AnnaBridge 175:b96e65c34a4d 314 {
AnnaBridge 175:b96e65c34a4d 315 SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
AnnaBridge 175:b96e65c34a4d 316
AnnaBridge 175:b96e65c34a4d 317 // NOTE:
AnnaBridge 175:b96e65c34a4d 318 // NUC472/M453/M487: SPI_CTL.SPIEN is controlled by software (in FIFO mode).
AnnaBridge 175:b96e65c34a4d 319 // NANO130: SPI_CTL.GO_BUSY is controlled by hardware in FIFO mode.
AnnaBridge 175:b96e65c34a4d 320
AnnaBridge 175:b96e65c34a4d 321 // Wait for rx buffer full
AnnaBridge 175:b96e65c34a4d 322 while (! spi_readable(obj));
AnnaBridge 175:b96e65c34a4d 323 uint32_t RX = (NU_MODSUBINDEX(obj->spi.spi) == 0) ? ((uint32_t) &spi_base->RX0) : ((uint32_t) &spi_base->RX1);
AnnaBridge 175:b96e65c34a4d 324 int value = M32(RX);
AnnaBridge 175:b96e65c34a4d 325 return value;
AnnaBridge 175:b96e65c34a4d 326 }
AnnaBridge 175:b96e65c34a4d 327
AnnaBridge 175:b96e65c34a4d 328 void spi_slave_write(spi_t *obj, int value)
AnnaBridge 175:b96e65c34a4d 329 {
AnnaBridge 175:b96e65c34a4d 330 SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
AnnaBridge 175:b96e65c34a4d 331
AnnaBridge 175:b96e65c34a4d 332 // NOTE:
AnnaBridge 175:b96e65c34a4d 333 // NUC472/M453/M487: SPI_CTL.SPIEN is controlled by software (in FIFO mode).
AnnaBridge 175:b96e65c34a4d 334 // NANO130: SPI_CTL.GO_BUSY is controlled by hardware in FIFO mode.
AnnaBridge 175:b96e65c34a4d 335
AnnaBridge 175:b96e65c34a4d 336 // Wait for tx buffer empty
AnnaBridge 175:b96e65c34a4d 337 while(! spi_writeable(obj));
AnnaBridge 175:b96e65c34a4d 338 uint32_t TX = (NU_MODSUBINDEX(obj->spi.spi) == 0) ? ((uint32_t) &spi_base->TX0) : ((uint32_t) &spi_base->TX1);
AnnaBridge 175:b96e65c34a4d 339 M32(TX) = value;
AnnaBridge 175:b96e65c34a4d 340 }
AnnaBridge 175:b96e65c34a4d 341 #endif
AnnaBridge 175:b96e65c34a4d 342
AnnaBridge 175:b96e65c34a4d 343 #if DEVICE_SPI_ASYNCH
AnnaBridge 175:b96e65c34a4d 344 void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint)
AnnaBridge 175:b96e65c34a4d 345 {
AnnaBridge 175:b96e65c34a4d 346 SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
AnnaBridge 175:b96e65c34a4d 347 SPI_SET_DATA_WIDTH(spi_base, bit_width);
AnnaBridge 175:b96e65c34a4d 348
AnnaBridge 175:b96e65c34a4d 349 obj->spi.dma_usage = hint;
AnnaBridge 175:b96e65c34a4d 350 spi_check_dma_usage(&obj->spi.dma_usage, &obj->spi.dma_chn_id_tx, &obj->spi.dma_chn_id_rx);
AnnaBridge 175:b96e65c34a4d 351 uint32_t data_width = spi_get_data_width(obj);
AnnaBridge 175:b96e65c34a4d 352 // Conditions to go DMA way:
AnnaBridge 175:b96e65c34a4d 353 // (1) No DMA support for non-8 multiple data width.
AnnaBridge 175:b96e65c34a4d 354 // (2) tx length >= rx length. Otherwise, as tx DMA is done, no bus activity for remaining rx.
AnnaBridge 175:b96e65c34a4d 355 if ((data_width % 8) ||
AnnaBridge 175:b96e65c34a4d 356 (tx_length < rx_length)) {
AnnaBridge 175:b96e65c34a4d 357 obj->spi.dma_usage = DMA_USAGE_NEVER;
AnnaBridge 175:b96e65c34a4d 358 dma_channel_free(obj->spi.dma_chn_id_tx);
AnnaBridge 175:b96e65c34a4d 359 obj->spi.dma_chn_id_tx = DMA_ERROR_OUT_OF_CHANNELS;
AnnaBridge 175:b96e65c34a4d 360 dma_channel_free(obj->spi.dma_chn_id_rx);
AnnaBridge 175:b96e65c34a4d 361 obj->spi.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS;
AnnaBridge 175:b96e65c34a4d 362 }
AnnaBridge 175:b96e65c34a4d 363
AnnaBridge 175:b96e65c34a4d 364 // SPI IRQ is necessary for both interrupt way and DMA way
AnnaBridge 175:b96e65c34a4d 365 spi_enable_event(obj, event, 1);
AnnaBridge 175:b96e65c34a4d 366 spi_buffer_set(obj, tx, tx_length, rx, rx_length);
AnnaBridge 175:b96e65c34a4d 367
AnnaBridge 175:b96e65c34a4d 368 // NOTE:
AnnaBridge 175:b96e65c34a4d 369 // NUC472/M453/M487: SPI_CTL.SPIEN is controlled by software (in FIFO mode).
AnnaBridge 175:b96e65c34a4d 370 // NANO130: SPI_CTL.GO_BUSY is controlled by hardware in FIFO mode.
AnnaBridge 175:b96e65c34a4d 371
AnnaBridge 175:b96e65c34a4d 372 if (obj->spi.dma_usage == DMA_USAGE_NEVER) {
AnnaBridge 175:b96e65c34a4d 373 // Interrupt way
AnnaBridge 175:b96e65c34a4d 374 spi_master_write_asynch(obj, NU_SPI_FIFO_DEPTH / 2);
AnnaBridge 175:b96e65c34a4d 375 spi_enable_vector_interrupt(obj, handler, 1);
AnnaBridge 175:b96e65c34a4d 376 spi_master_enable_interrupt(obj, 1, SPI_FIFO_RX_INTEN_MASK | SPI_FIFO_TX_INTEN_MASK);
AnnaBridge 175:b96e65c34a4d 377 } else {
AnnaBridge 175:b96e65c34a4d 378 // DMA way
AnnaBridge 175:b96e65c34a4d 379 const struct nu_modinit_s *modinit = get_modinit(obj->spi.spi, spi_modinit_tab);
AnnaBridge 175:b96e65c34a4d 380 MBED_ASSERT(modinit != NULL);
AnnaBridge 175:b96e65c34a4d 381 MBED_ASSERT((SPIName) modinit->modname == obj->spi.spi);
AnnaBridge 175:b96e65c34a4d 382
AnnaBridge 175:b96e65c34a4d 383 // Configure tx DMA
AnnaBridge 175:b96e65c34a4d 384 dma_enable(obj->spi.dma_chn_id_tx, 1); // Enable this DMA channel
AnnaBridge 175:b96e65c34a4d 385 PDMA_SetTransferMode(obj->spi.dma_chn_id_tx,
AnnaBridge 175:b96e65c34a4d 386 ((struct nu_spi_var *) modinit->var)->pdma_perp_tx, // Peripheral connected to this PDMA
AnnaBridge 175:b96e65c34a4d 387 0, // Scatter-gather disabled
AnnaBridge 175:b96e65c34a4d 388 0); // Scatter-gather descriptor address
AnnaBridge 175:b96e65c34a4d 389 PDMA_SetTransferCnt(obj->spi.dma_chn_id_tx,
AnnaBridge 175:b96e65c34a4d 390 (data_width == 8) ? PDMA_WIDTH_8 : (data_width == 16) ? PDMA_WIDTH_16 : PDMA_WIDTH_32,
AnnaBridge 175:b96e65c34a4d 391 tx_length);
AnnaBridge 175:b96e65c34a4d 392 PDMA_SetTransferAddr(obj->spi.dma_chn_id_tx,
AnnaBridge 175:b96e65c34a4d 393 (uint32_t) tx, // NOTE:
AnnaBridge 175:b96e65c34a4d 394 // NUC472: End of source address
AnnaBridge 175:b96e65c34a4d 395 // M451: Start of source address
AnnaBridge 175:b96e65c34a4d 396 // NANO130: Start of destination address
AnnaBridge 175:b96e65c34a4d 397 PDMA_SAR_INC, // Source address incremental
AnnaBridge 175:b96e65c34a4d 398 NU_MODSUBINDEX(obj->spi.spi) == 0 ? (uint32_t) &spi_base->TX0 : (uint32_t) &spi_base->TX1, // Destination address
AnnaBridge 175:b96e65c34a4d 399 PDMA_DAR_FIX); // Destination address fixed
AnnaBridge 175:b96e65c34a4d 400 PDMA_EnableInt(obj->spi.dma_chn_id_tx,
AnnaBridge 175:b96e65c34a4d 401 PDMA_IER_TD_IE_Msk); // Interrupt type
AnnaBridge 175:b96e65c34a4d 402 // Register DMA event handler
AnnaBridge 175:b96e65c34a4d 403 dma_set_handler(obj->spi.dma_chn_id_tx, (uint32_t) spi_dma_handler_tx, (uint32_t) obj, DMA_EVENT_ALL);
AnnaBridge 175:b96e65c34a4d 404
AnnaBridge 175:b96e65c34a4d 405 // Configure rx DMA
AnnaBridge 175:b96e65c34a4d 406 dma_enable(obj->spi.dma_chn_id_rx, 1); // Enable this DMA channel
AnnaBridge 175:b96e65c34a4d 407 PDMA_SetTransferMode(obj->spi.dma_chn_id_rx,
AnnaBridge 175:b96e65c34a4d 408 ((struct nu_spi_var *) modinit->var)->pdma_perp_rx, // Peripheral connected to this PDMA
AnnaBridge 175:b96e65c34a4d 409 0, // Scatter-gather disabled
AnnaBridge 175:b96e65c34a4d 410 0); // Scatter-gather descriptor address
AnnaBridge 175:b96e65c34a4d 411 PDMA_SetTransferCnt(obj->spi.dma_chn_id_rx,
AnnaBridge 175:b96e65c34a4d 412 (data_width == 8) ? PDMA_WIDTH_8 : (data_width == 16) ? PDMA_WIDTH_16 : PDMA_WIDTH_32,
AnnaBridge 175:b96e65c34a4d 413 rx_length);
AnnaBridge 175:b96e65c34a4d 414 PDMA_SetTransferAddr(obj->spi.dma_chn_id_rx,
AnnaBridge 175:b96e65c34a4d 415 NU_MODSUBINDEX(obj->spi.spi) == 0 ? (uint32_t) &spi_base->RX0 : (uint32_t) &spi_base->RX1, // Source address
AnnaBridge 175:b96e65c34a4d 416 PDMA_SAR_FIX, // Source address fixed
AnnaBridge 175:b96e65c34a4d 417 (uint32_t) rx, // NOTE:
AnnaBridge 175:b96e65c34a4d 418 // NUC472: End of destination address
AnnaBridge 175:b96e65c34a4d 419 // M451: Start of destination address
AnnaBridge 175:b96e65c34a4d 420 // NANO130: Start of destination address
AnnaBridge 175:b96e65c34a4d 421 PDMA_DAR_INC); // Destination address incremental
AnnaBridge 175:b96e65c34a4d 422 PDMA_EnableInt(obj->spi.dma_chn_id_rx,
AnnaBridge 175:b96e65c34a4d 423 PDMA_IER_TD_IE_Msk); // Interrupt type
AnnaBridge 175:b96e65c34a4d 424 // Register DMA event handler
AnnaBridge 175:b96e65c34a4d 425 dma_set_handler(obj->spi.dma_chn_id_rx, (uint32_t) spi_dma_handler_rx, (uint32_t) obj, DMA_EVENT_ALL);
AnnaBridge 175:b96e65c34a4d 426
AnnaBridge 175:b96e65c34a4d 427 // Start tx/rx DMA transfer
AnnaBridge 175:b96e65c34a4d 428 spi_enable_vector_interrupt(obj, handler, 1);
AnnaBridge 175:b96e65c34a4d 429 // No TX/RX FIFO threshold interrupt
AnnaBridge 175:b96e65c34a4d 430 spi_master_enable_interrupt(obj, 0, SPI_FIFO_RX_INTEN_MASK | SPI_FIFO_TX_INTEN_MASK);
AnnaBridge 175:b96e65c34a4d 431 // NOTE: It is safer to start rx DMA first and then tx DMA. Otherwise, receive FIFO is subject to overflow by tx DMA.
AnnaBridge 175:b96e65c34a4d 432 SPI_TRIGGER_RX_PDMA(((SPI_T *) NU_MODBASE(obj->spi.spi)));
AnnaBridge 175:b96e65c34a4d 433 SPI_TRIGGER_TX_PDMA(((SPI_T *) NU_MODBASE(obj->spi.spi)));
AnnaBridge 175:b96e65c34a4d 434 PDMA_Trigger(obj->spi.dma_chn_id_rx);
AnnaBridge 175:b96e65c34a4d 435 PDMA_Trigger(obj->spi.dma_chn_id_tx);
AnnaBridge 175:b96e65c34a4d 436 }
AnnaBridge 175:b96e65c34a4d 437 }
AnnaBridge 175:b96e65c34a4d 438
AnnaBridge 175:b96e65c34a4d 439 /**
AnnaBridge 175:b96e65c34a4d 440 * Abort an SPI transfer
AnnaBridge 175:b96e65c34a4d 441 * This is a helper function for event handling. When any of the events listed occurs, the HAL will abort any ongoing
AnnaBridge 175:b96e65c34a4d 442 * transfers
AnnaBridge 175:b96e65c34a4d 443 * @param[in] obj The SPI peripheral to stop
AnnaBridge 175:b96e65c34a4d 444 */
AnnaBridge 175:b96e65c34a4d 445 void spi_abort_asynch(spi_t *obj)
AnnaBridge 175:b96e65c34a4d 446 {
AnnaBridge 175:b96e65c34a4d 447 SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
AnnaBridge 175:b96e65c34a4d 448
AnnaBridge 175:b96e65c34a4d 449 if (obj->spi.dma_usage != DMA_USAGE_NEVER) {
AnnaBridge 175:b96e65c34a4d 450 // Receive FIFO Overrun in case of tx length > rx length on DMA way
AnnaBridge 175:b96e65c34a4d 451 if (spi_base->STATUS & SPI_STATUS_RX_OVER_RUN_Msk) {
AnnaBridge 175:b96e65c34a4d 452 spi_base->STATUS = SPI_STATUS_RX_OVER_RUN_Msk;
AnnaBridge 175:b96e65c34a4d 453 }
AnnaBridge 175:b96e65c34a4d 454
AnnaBridge 175:b96e65c34a4d 455 if (obj->spi.dma_chn_id_tx != DMA_ERROR_OUT_OF_CHANNELS) {
AnnaBridge 175:b96e65c34a4d 456 PDMA_DisableInt(obj->spi.dma_chn_id_tx, PDMA_IER_TD_IE_Msk);
AnnaBridge 175:b96e65c34a4d 457 // NOTE: On NUC472, next PDMA transfer will fail with PDMA_STOP() called.
AnnaBridge 175:b96e65c34a4d 458 dma_enable(obj->spi.dma_chn_id_tx, 0);
AnnaBridge 175:b96e65c34a4d 459 }
AnnaBridge 175:b96e65c34a4d 460 //SPI_DISABLE_TX_PDMA(((SPI_T *) NU_MODBASE(obj->spi.spi)));
AnnaBridge 175:b96e65c34a4d 461 spi_base->DMA &= ~SPI_DMA_TX_DMA_EN_Msk;
AnnaBridge 175:b96e65c34a4d 462
AnnaBridge 175:b96e65c34a4d 463 if (obj->spi.dma_chn_id_rx != DMA_ERROR_OUT_OF_CHANNELS) {
AnnaBridge 175:b96e65c34a4d 464 PDMA_DisableInt(obj->spi.dma_chn_id_rx, PDMA_IER_TD_IE_Msk);
AnnaBridge 175:b96e65c34a4d 465 // NOTE: On NUC472, next PDMA transfer will fail with PDMA_STOP() called.
AnnaBridge 175:b96e65c34a4d 466 dma_enable(obj->spi.dma_chn_id_rx, 0);
AnnaBridge 175:b96e65c34a4d 467 }
AnnaBridge 175:b96e65c34a4d 468 //SPI_DISABLE_RX_PDMA(((SPI_T *) NU_MODBASE(obj->spi.spi)));
AnnaBridge 175:b96e65c34a4d 469 spi_base->DMA &= ~SPI_DMA_RX_DMA_EN_Msk;
AnnaBridge 175:b96e65c34a4d 470 }
AnnaBridge 175:b96e65c34a4d 471
AnnaBridge 175:b96e65c34a4d 472 // Necessary for both interrupt way and DMA way
AnnaBridge 175:b96e65c34a4d 473 spi_enable_vector_interrupt(obj, 0, 0);
AnnaBridge 175:b96e65c34a4d 474 spi_master_enable_interrupt(obj, 0, SPI_FIFO_RX_INTEN_MASK | SPI_FIFO_TX_INTEN_MASK);
AnnaBridge 175:b96e65c34a4d 475
AnnaBridge 175:b96e65c34a4d 476 // NOTE: SPI H/W may get out of state without the busy check.
AnnaBridge 175:b96e65c34a4d 477 while (SPI_IS_BUSY(spi_base));
AnnaBridge 175:b96e65c34a4d 478
AnnaBridge 175:b96e65c34a4d 479 SPI_ClearRxFIFO(spi_base);
AnnaBridge 175:b96e65c34a4d 480 SPI_ClearTxFIFO(spi_base);
AnnaBridge 175:b96e65c34a4d 481 }
AnnaBridge 175:b96e65c34a4d 482
AnnaBridge 175:b96e65c34a4d 483 /**
AnnaBridge 175:b96e65c34a4d 484 * Handle the SPI interrupt
AnnaBridge 175:b96e65c34a4d 485 * Read frames until the RX FIFO is empty. Write at most as many frames as were read. This way,
AnnaBridge 175:b96e65c34a4d 486 * it is unlikely that the RX FIFO will overflow.
AnnaBridge 175:b96e65c34a4d 487 * @param[in] obj The SPI peripheral that generated the interrupt
AnnaBridge 175:b96e65c34a4d 488 * @return
AnnaBridge 175:b96e65c34a4d 489 */
AnnaBridge 175:b96e65c34a4d 490 uint32_t spi_irq_handler_asynch(spi_t *obj)
AnnaBridge 175:b96e65c34a4d 491 {
AnnaBridge 175:b96e65c34a4d 492 // Check for SPI events
AnnaBridge 175:b96e65c34a4d 493 uint32_t event = spi_event_check(obj);
AnnaBridge 175:b96e65c34a4d 494 if (event) {
AnnaBridge 175:b96e65c34a4d 495 spi_abort_asynch(obj);
AnnaBridge 175:b96e65c34a4d 496 }
AnnaBridge 175:b96e65c34a4d 497
AnnaBridge 175:b96e65c34a4d 498 return (obj->spi.event & event) | ((event & SPI_EVENT_COMPLETE) ? SPI_EVENT_INTERNAL_TRANSFER_COMPLETE : 0);
AnnaBridge 175:b96e65c34a4d 499 }
AnnaBridge 175:b96e65c34a4d 500
AnnaBridge 175:b96e65c34a4d 501 uint8_t spi_active(spi_t *obj)
AnnaBridge 175:b96e65c34a4d 502 {
AnnaBridge 175:b96e65c34a4d 503 SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
AnnaBridge 175:b96e65c34a4d 504
AnnaBridge 175:b96e65c34a4d 505 return SPI_IS_BUSY(spi_base);
AnnaBridge 175:b96e65c34a4d 506 }
AnnaBridge 175:b96e65c34a4d 507
AnnaBridge 175:b96e65c34a4d 508 void SPI0_IRQHandler(void)
AnnaBridge 175:b96e65c34a4d 509 {
AnnaBridge 175:b96e65c34a4d 510 spi_irq(spi0_var.obj);
AnnaBridge 175:b96e65c34a4d 511 }
AnnaBridge 175:b96e65c34a4d 512 void SPI1_IRQHandler(void)
AnnaBridge 175:b96e65c34a4d 513 {
AnnaBridge 175:b96e65c34a4d 514 spi_irq(spi1_var.obj);
AnnaBridge 175:b96e65c34a4d 515 }
AnnaBridge 175:b96e65c34a4d 516 void SPI2_IRQHandler(void)
AnnaBridge 175:b96e65c34a4d 517 {
AnnaBridge 175:b96e65c34a4d 518 spi_irq(spi2_var.obj);
AnnaBridge 175:b96e65c34a4d 519 }
AnnaBridge 175:b96e65c34a4d 520 static void spi_irq(spi_t *obj)
AnnaBridge 175:b96e65c34a4d 521 {
AnnaBridge 175:b96e65c34a4d 522 if (obj && obj->spi.hdlr_async) {
AnnaBridge 175:b96e65c34a4d 523 void (*hdlr_async)(void) = (void(*)(void))(obj->spi.hdlr_async);
AnnaBridge 175:b96e65c34a4d 524 hdlr_async();
AnnaBridge 175:b96e65c34a4d 525 }
AnnaBridge 175:b96e65c34a4d 526 }
AnnaBridge 175:b96e65c34a4d 527
AnnaBridge 175:b96e65c34a4d 528 static int spi_writeable(spi_t * obj)
AnnaBridge 175:b96e65c34a4d 529 {
AnnaBridge 175:b96e65c34a4d 530 // Receive FIFO must not be full to avoid receive FIFO overflow on next transmit/receive
AnnaBridge 175:b96e65c34a4d 531 return (! SPI_GET_TX_FIFO_FULL_FLAG(((SPI_T *) NU_MODBASE(obj->spi.spi))));
AnnaBridge 175:b96e65c34a4d 532 }
AnnaBridge 175:b96e65c34a4d 533
AnnaBridge 175:b96e65c34a4d 534 static int spi_readable(spi_t * obj)
AnnaBridge 175:b96e65c34a4d 535 {
AnnaBridge 175:b96e65c34a4d 536 return ! SPI_GET_RX_FIFO_EMPTY_FLAG(((SPI_T *) NU_MODBASE(obj->spi.spi)));
AnnaBridge 175:b96e65c34a4d 537 }
AnnaBridge 175:b96e65c34a4d 538
AnnaBridge 175:b96e65c34a4d 539 static void spi_enable_event(spi_t *obj, uint32_t event, uint8_t enable)
AnnaBridge 175:b96e65c34a4d 540 {
AnnaBridge 175:b96e65c34a4d 541 obj->spi.event &= ~SPI_EVENT_ALL;
AnnaBridge 175:b96e65c34a4d 542 obj->spi.event |= (event & SPI_EVENT_ALL);
AnnaBridge 175:b96e65c34a4d 543 if (event & SPI_EVENT_RX_OVERFLOW) {
AnnaBridge 175:b96e65c34a4d 544 SPI_EnableInt((SPI_T *) NU_MODBASE(obj->spi.spi), SPI_FIFO_RXOVR_INTEN_MASK);
AnnaBridge 175:b96e65c34a4d 545 }
AnnaBridge 175:b96e65c34a4d 546 }
AnnaBridge 175:b96e65c34a4d 547
AnnaBridge 175:b96e65c34a4d 548 static void spi_enable_vector_interrupt(spi_t *obj, uint32_t handler, uint8_t enable)
AnnaBridge 175:b96e65c34a4d 549 {
AnnaBridge 175:b96e65c34a4d 550 const struct nu_modinit_s *modinit = get_modinit(obj->spi.spi, spi_modinit_tab);
AnnaBridge 175:b96e65c34a4d 551 MBED_ASSERT(modinit != NULL);
AnnaBridge 175:b96e65c34a4d 552 MBED_ASSERT((SPIName) modinit->modname == obj->spi.spi);
AnnaBridge 175:b96e65c34a4d 553
AnnaBridge 175:b96e65c34a4d 554 struct nu_spi_var *var = (struct nu_spi_var *) modinit->var;
AnnaBridge 175:b96e65c34a4d 555
AnnaBridge 175:b96e65c34a4d 556 if (enable) {
AnnaBridge 175:b96e65c34a4d 557 var->obj = obj;
AnnaBridge 175:b96e65c34a4d 558 obj->spi.hdlr_async = handler;
AnnaBridge 175:b96e65c34a4d 559 NVIC_SetVector(modinit->irq_n, (uint32_t) var->vec);
AnnaBridge 175:b96e65c34a4d 560 NVIC_EnableIRQ(modinit->irq_n);
AnnaBridge 175:b96e65c34a4d 561 }
AnnaBridge 175:b96e65c34a4d 562 else {
AnnaBridge 175:b96e65c34a4d 563 NVIC_DisableIRQ(modinit->irq_n);
AnnaBridge 175:b96e65c34a4d 564 var->obj = NULL;
AnnaBridge 175:b96e65c34a4d 565 obj->spi.hdlr_async = handler;
AnnaBridge 175:b96e65c34a4d 566 }
AnnaBridge 175:b96e65c34a4d 567 }
AnnaBridge 175:b96e65c34a4d 568
AnnaBridge 175:b96e65c34a4d 569 static void spi_master_enable_interrupt(spi_t *obj, uint8_t enable, uint32_t mask)
AnnaBridge 175:b96e65c34a4d 570 {
AnnaBridge 175:b96e65c34a4d 571 SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
AnnaBridge 175:b96e65c34a4d 572
AnnaBridge 175:b96e65c34a4d 573 // NOTE:
AnnaBridge 175:b96e65c34a4d 574 // NANO130: SPI_IE_MASK/SPI_STATUS_INTSTS_Msk are for unit transfer IE/EF. Don't get confused.
AnnaBridge 175:b96e65c34a4d 575 if (enable) {
AnnaBridge 175:b96e65c34a4d 576 // Enable tx/rx FIFO threshold interrupt
AnnaBridge 175:b96e65c34a4d 577 SPI_EnableInt(spi_base, mask);
AnnaBridge 175:b96e65c34a4d 578 }
AnnaBridge 175:b96e65c34a4d 579 else {
AnnaBridge 175:b96e65c34a4d 580 SPI_DisableInt(spi_base, mask);
AnnaBridge 175:b96e65c34a4d 581 }
AnnaBridge 175:b96e65c34a4d 582 }
AnnaBridge 175:b96e65c34a4d 583
AnnaBridge 175:b96e65c34a4d 584 static uint32_t spi_event_check(spi_t *obj)
AnnaBridge 175:b96e65c34a4d 585 {
AnnaBridge 175:b96e65c34a4d 586 SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
AnnaBridge 175:b96e65c34a4d 587 uint32_t event = 0;
AnnaBridge 175:b96e65c34a4d 588
AnnaBridge 175:b96e65c34a4d 589 if (obj->spi.dma_usage == DMA_USAGE_NEVER) {
AnnaBridge 175:b96e65c34a4d 590 uint32_t n_rec = spi_master_read_asynch(obj);
AnnaBridge 175:b96e65c34a4d 591 spi_master_write_asynch(obj, n_rec);
AnnaBridge 175:b96e65c34a4d 592 }
AnnaBridge 175:b96e65c34a4d 593
AnnaBridge 175:b96e65c34a4d 594 if (spi_is_tx_complete(obj) && spi_is_rx_complete(obj)) {
AnnaBridge 175:b96e65c34a4d 595 event |= SPI_EVENT_COMPLETE;
AnnaBridge 175:b96e65c34a4d 596 }
AnnaBridge 175:b96e65c34a4d 597
AnnaBridge 175:b96e65c34a4d 598 // Receive FIFO Overrun
AnnaBridge 175:b96e65c34a4d 599 if (spi_base->STATUS & SPI_STATUS_RX_OVER_RUN_Msk) {
AnnaBridge 175:b96e65c34a4d 600 spi_base->STATUS = SPI_STATUS_RX_OVER_RUN_Msk;
AnnaBridge 175:b96e65c34a4d 601 // In case of tx length > rx length on DMA way
AnnaBridge 175:b96e65c34a4d 602 if (obj->spi.dma_usage == DMA_USAGE_NEVER) {
AnnaBridge 175:b96e65c34a4d 603 event |= SPI_EVENT_RX_OVERFLOW;
AnnaBridge 175:b96e65c34a4d 604 }
AnnaBridge 175:b96e65c34a4d 605 }
AnnaBridge 175:b96e65c34a4d 606
AnnaBridge 175:b96e65c34a4d 607 // Receive Time-Out
AnnaBridge 175:b96e65c34a4d 608 if (spi_base->STATUS & SPI_STATUS_TIME_OUT_STS_Msk) {
AnnaBridge 175:b96e65c34a4d 609 spi_base->STATUS = SPI_STATUS_TIME_OUT_STS_Msk;
AnnaBridge 175:b96e65c34a4d 610 }
AnnaBridge 175:b96e65c34a4d 611
AnnaBridge 175:b96e65c34a4d 612 return event;
AnnaBridge 175:b96e65c34a4d 613 }
AnnaBridge 175:b96e65c34a4d 614
AnnaBridge 175:b96e65c34a4d 615 /**
AnnaBridge 175:b96e65c34a4d 616 * Send words from the SPI TX buffer until the send limit is reached or the TX FIFO is full
AnnaBridge 175:b96e65c34a4d 617 * tx_limit is provided to ensure that the number of SPI frames (words) in flight can be managed.
AnnaBridge 175:b96e65c34a4d 618 * @param[in] obj The SPI object on which to operate
AnnaBridge 175:b96e65c34a4d 619 * @param[in] tx_limit The maximum number of words to send
AnnaBridge 175:b96e65c34a4d 620 * @return The number of SPI words that have been transfered
AnnaBridge 175:b96e65c34a4d 621 */
AnnaBridge 175:b96e65c34a4d 622 static uint32_t spi_master_write_asynch(spi_t *obj, uint32_t tx_limit)
AnnaBridge 175:b96e65c34a4d 623 {
AnnaBridge 175:b96e65c34a4d 624 uint32_t n_words = 0;
AnnaBridge 175:b96e65c34a4d 625 uint32_t tx_rmn = obj->tx_buff.length - obj->tx_buff.pos;
AnnaBridge 175:b96e65c34a4d 626 uint32_t rx_rmn = obj->rx_buff.length - obj->rx_buff.pos;
AnnaBridge 175:b96e65c34a4d 627 uint32_t max_tx = NU_MAX(tx_rmn, rx_rmn);
AnnaBridge 175:b96e65c34a4d 628 max_tx = NU_MIN(max_tx, tx_limit);
AnnaBridge 175:b96e65c34a4d 629 uint8_t data_width = spi_get_data_width(obj);
AnnaBridge 175:b96e65c34a4d 630 uint8_t bytes_per_word = (data_width + 7) / 8;
AnnaBridge 175:b96e65c34a4d 631 uint8_t *tx = (uint8_t *)(obj->tx_buff.buffer) + bytes_per_word * obj->tx_buff.pos;
AnnaBridge 175:b96e65c34a4d 632 SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
AnnaBridge 175:b96e65c34a4d 633 uint32_t TX = (NU_MODSUBINDEX(obj->spi.spi) == 0) ? ((uint32_t) &spi_base->TX0) : ((uint32_t) &spi_base->TX1);
AnnaBridge 175:b96e65c34a4d 634
AnnaBridge 175:b96e65c34a4d 635 while ((n_words < max_tx) && spi_writeable(obj)) {
AnnaBridge 175:b96e65c34a4d 636 if (spi_is_tx_complete(obj)) {
AnnaBridge 175:b96e65c34a4d 637 // Transmit dummy as transmit buffer is empty
AnnaBridge 175:b96e65c34a4d 638 M32(TX) = 0;
AnnaBridge 175:b96e65c34a4d 639 }
AnnaBridge 175:b96e65c34a4d 640 else {
AnnaBridge 175:b96e65c34a4d 641 switch (bytes_per_word) {
AnnaBridge 175:b96e65c34a4d 642 case 4:
AnnaBridge 175:b96e65c34a4d 643 M32(TX) = nu_get32_le(tx);
AnnaBridge 175:b96e65c34a4d 644 tx += 4;
AnnaBridge 175:b96e65c34a4d 645 break;
AnnaBridge 175:b96e65c34a4d 646 case 2:
AnnaBridge 175:b96e65c34a4d 647 M32(TX) = nu_get16_le(tx);
AnnaBridge 175:b96e65c34a4d 648 tx += 2;
AnnaBridge 175:b96e65c34a4d 649 break;
AnnaBridge 175:b96e65c34a4d 650 case 1:
AnnaBridge 175:b96e65c34a4d 651 M32(TX) = *((uint8_t *) tx);
AnnaBridge 175:b96e65c34a4d 652 tx += 1;
AnnaBridge 175:b96e65c34a4d 653 break;
AnnaBridge 175:b96e65c34a4d 654 }
AnnaBridge 175:b96e65c34a4d 655
AnnaBridge 175:b96e65c34a4d 656 obj->tx_buff.pos ++;
AnnaBridge 175:b96e65c34a4d 657 }
AnnaBridge 175:b96e65c34a4d 658 n_words ++;
AnnaBridge 175:b96e65c34a4d 659 }
AnnaBridge 175:b96e65c34a4d 660
AnnaBridge 175:b96e65c34a4d 661 //Return the number of words that have been sent
AnnaBridge 175:b96e65c34a4d 662 return n_words;
AnnaBridge 175:b96e65c34a4d 663 }
AnnaBridge 175:b96e65c34a4d 664
AnnaBridge 175:b96e65c34a4d 665 /**
AnnaBridge 175:b96e65c34a4d 666 * Read SPI words out of the RX FIFO
AnnaBridge 175:b96e65c34a4d 667 * Continues reading words out of the RX FIFO until the following condition is met:
AnnaBridge 175:b96e65c34a4d 668 * o There are no more words in the FIFO
AnnaBridge 175:b96e65c34a4d 669 * OR BOTH OF:
AnnaBridge 175:b96e65c34a4d 670 * o At least as many words as the TX buffer have been received
AnnaBridge 175:b96e65c34a4d 671 * o At least as many words as the RX buffer have been received
AnnaBridge 175:b96e65c34a4d 672 * This way, RX overflows are not generated when the TX buffer size exceeds the RX buffer size
AnnaBridge 175:b96e65c34a4d 673 * @param[in] obj The SPI object on which to operate
AnnaBridge 175:b96e65c34a4d 674 * @return Returns the number of words extracted from the RX FIFO
AnnaBridge 175:b96e65c34a4d 675 */
AnnaBridge 175:b96e65c34a4d 676 static uint32_t spi_master_read_asynch(spi_t *obj)
AnnaBridge 175:b96e65c34a4d 677 {
AnnaBridge 175:b96e65c34a4d 678 uint32_t n_words = 0;
AnnaBridge 175:b96e65c34a4d 679 uint32_t tx_rmn = obj->tx_buff.length - obj->tx_buff.pos;
AnnaBridge 175:b96e65c34a4d 680 uint32_t rx_rmn = obj->rx_buff.length - obj->rx_buff.pos;
AnnaBridge 175:b96e65c34a4d 681 uint32_t max_rx = NU_MAX(tx_rmn, rx_rmn);
AnnaBridge 175:b96e65c34a4d 682 uint8_t data_width = spi_get_data_width(obj);
AnnaBridge 175:b96e65c34a4d 683 uint8_t bytes_per_word = (data_width + 7) / 8;
AnnaBridge 175:b96e65c34a4d 684 uint8_t *rx = (uint8_t *)(obj->rx_buff.buffer) + bytes_per_word * obj->rx_buff.pos;
AnnaBridge 175:b96e65c34a4d 685 SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
AnnaBridge 175:b96e65c34a4d 686 uint32_t RX = (NU_MODSUBINDEX(obj->spi.spi) == 0) ? ((uint32_t) &spi_base->RX0) : ((uint32_t) &spi_base->RX1);
AnnaBridge 175:b96e65c34a4d 687
AnnaBridge 175:b96e65c34a4d 688 while ((n_words < max_rx) && spi_readable(obj)) {
AnnaBridge 175:b96e65c34a4d 689 if (spi_is_rx_complete(obj)) {
AnnaBridge 175:b96e65c34a4d 690 // Disregard as receive buffer is full
AnnaBridge 175:b96e65c34a4d 691 M32(RX);
AnnaBridge 175:b96e65c34a4d 692 }
AnnaBridge 175:b96e65c34a4d 693 else {
AnnaBridge 175:b96e65c34a4d 694 switch (bytes_per_word) {
AnnaBridge 175:b96e65c34a4d 695 case 4: {
AnnaBridge 175:b96e65c34a4d 696 uint32_t val = M32(RX);
AnnaBridge 175:b96e65c34a4d 697 nu_set32_le(rx, val);
AnnaBridge 175:b96e65c34a4d 698 rx += 4;
AnnaBridge 175:b96e65c34a4d 699 break;
AnnaBridge 175:b96e65c34a4d 700 }
AnnaBridge 175:b96e65c34a4d 701 case 2: {
AnnaBridge 175:b96e65c34a4d 702 uint16_t val = M32(RX);
AnnaBridge 175:b96e65c34a4d 703 nu_set16_le(rx, val);
AnnaBridge 175:b96e65c34a4d 704 rx += 2;
AnnaBridge 175:b96e65c34a4d 705 break;
AnnaBridge 175:b96e65c34a4d 706 }
AnnaBridge 175:b96e65c34a4d 707 case 1:
AnnaBridge 175:b96e65c34a4d 708 *rx ++ = M32(RX);
AnnaBridge 175:b96e65c34a4d 709 break;
AnnaBridge 175:b96e65c34a4d 710 }
AnnaBridge 175:b96e65c34a4d 711
AnnaBridge 175:b96e65c34a4d 712 obj->rx_buff.pos ++;
AnnaBridge 175:b96e65c34a4d 713 }
AnnaBridge 175:b96e65c34a4d 714 n_words ++;
AnnaBridge 175:b96e65c34a4d 715 }
AnnaBridge 175:b96e65c34a4d 716
AnnaBridge 175:b96e65c34a4d 717 // Return the number of words received
AnnaBridge 175:b96e65c34a4d 718 return n_words;
AnnaBridge 175:b96e65c34a4d 719 }
AnnaBridge 175:b96e65c34a4d 720
AnnaBridge 175:b96e65c34a4d 721 static void spi_buffer_set(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length)
AnnaBridge 175:b96e65c34a4d 722 {
AnnaBridge 175:b96e65c34a4d 723 obj->tx_buff.buffer = (void *) tx;
AnnaBridge 175:b96e65c34a4d 724 obj->tx_buff.length = tx_length;
AnnaBridge 175:b96e65c34a4d 725 obj->tx_buff.pos = 0;
AnnaBridge 175:b96e65c34a4d 726 obj->tx_buff.width = spi_get_data_width(obj);
AnnaBridge 175:b96e65c34a4d 727 obj->rx_buff.buffer = rx;
AnnaBridge 175:b96e65c34a4d 728 obj->rx_buff.length = rx_length;
AnnaBridge 175:b96e65c34a4d 729 obj->rx_buff.pos = 0;
AnnaBridge 175:b96e65c34a4d 730 obj->rx_buff.width = spi_get_data_width(obj);
AnnaBridge 175:b96e65c34a4d 731 }
AnnaBridge 175:b96e65c34a4d 732
AnnaBridge 175:b96e65c34a4d 733 static void spi_check_dma_usage(DMAUsage *dma_usage, int *dma_ch_tx, int *dma_ch_rx)
AnnaBridge 175:b96e65c34a4d 734 {
AnnaBridge 175:b96e65c34a4d 735 if (*dma_usage != DMA_USAGE_NEVER) {
AnnaBridge 175:b96e65c34a4d 736 if (*dma_ch_tx == DMA_ERROR_OUT_OF_CHANNELS) {
AnnaBridge 175:b96e65c34a4d 737 *dma_ch_tx = dma_channel_allocate(DMA_CAP_NONE);
AnnaBridge 175:b96e65c34a4d 738 }
AnnaBridge 175:b96e65c34a4d 739 if (*dma_ch_rx == DMA_ERROR_OUT_OF_CHANNELS) {
AnnaBridge 175:b96e65c34a4d 740 *dma_ch_rx = dma_channel_allocate(DMA_CAP_NONE);
AnnaBridge 175:b96e65c34a4d 741 }
AnnaBridge 175:b96e65c34a4d 742
AnnaBridge 175:b96e65c34a4d 743 if (*dma_ch_tx == DMA_ERROR_OUT_OF_CHANNELS || *dma_ch_rx == DMA_ERROR_OUT_OF_CHANNELS) {
AnnaBridge 175:b96e65c34a4d 744 *dma_usage = DMA_USAGE_NEVER;
AnnaBridge 175:b96e65c34a4d 745 }
AnnaBridge 175:b96e65c34a4d 746 }
AnnaBridge 175:b96e65c34a4d 747
AnnaBridge 175:b96e65c34a4d 748 if (*dma_usage == DMA_USAGE_NEVER) {
AnnaBridge 175:b96e65c34a4d 749 dma_channel_free(*dma_ch_tx);
AnnaBridge 175:b96e65c34a4d 750 *dma_ch_tx = DMA_ERROR_OUT_OF_CHANNELS;
AnnaBridge 175:b96e65c34a4d 751 dma_channel_free(*dma_ch_rx);
AnnaBridge 175:b96e65c34a4d 752 *dma_ch_rx = DMA_ERROR_OUT_OF_CHANNELS;
AnnaBridge 175:b96e65c34a4d 753 }
AnnaBridge 175:b96e65c34a4d 754 }
AnnaBridge 175:b96e65c34a4d 755
AnnaBridge 175:b96e65c34a4d 756 static uint8_t spi_get_data_width(spi_t *obj)
AnnaBridge 175:b96e65c34a4d 757 {
AnnaBridge 175:b96e65c34a4d 758 SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
AnnaBridge 175:b96e65c34a4d 759
AnnaBridge 175:b96e65c34a4d 760 uint32_t data_width = ((spi_base->CTL & SPI_CTL_TX_BIT_LEN_Msk) >> SPI_CTL_TX_BIT_LEN_Pos);
AnnaBridge 175:b96e65c34a4d 761 if (data_width == 0) {
AnnaBridge 175:b96e65c34a4d 762 data_width = 32;
AnnaBridge 175:b96e65c34a4d 763 }
AnnaBridge 175:b96e65c34a4d 764
AnnaBridge 175:b96e65c34a4d 765 return data_width;
AnnaBridge 175:b96e65c34a4d 766 }
AnnaBridge 175:b96e65c34a4d 767
AnnaBridge 175:b96e65c34a4d 768 static int spi_is_tx_complete(spi_t *obj)
AnnaBridge 175:b96e65c34a4d 769 {
AnnaBridge 175:b96e65c34a4d 770 return (obj->tx_buff.pos == obj->tx_buff.length);
AnnaBridge 175:b96e65c34a4d 771 }
AnnaBridge 175:b96e65c34a4d 772
AnnaBridge 175:b96e65c34a4d 773 static int spi_is_rx_complete(spi_t *obj)
AnnaBridge 175:b96e65c34a4d 774 {
AnnaBridge 175:b96e65c34a4d 775 return (obj->rx_buff.pos == obj->rx_buff.length);
AnnaBridge 175:b96e65c34a4d 776 }
AnnaBridge 175:b96e65c34a4d 777
AnnaBridge 175:b96e65c34a4d 778 static void spi_dma_handler_tx(uint32_t id, uint32_t event_dma)
AnnaBridge 175:b96e65c34a4d 779 {
AnnaBridge 175:b96e65c34a4d 780 spi_t *obj = (spi_t *) id;
AnnaBridge 175:b96e65c34a4d 781
AnnaBridge 175:b96e65c34a4d 782 // TODO: Pass this error to caller
AnnaBridge 175:b96e65c34a4d 783 if (event_dma & DMA_EVENT_ABORT) {
AnnaBridge 175:b96e65c34a4d 784 }
AnnaBridge 175:b96e65c34a4d 785 // Expect SPI IRQ will catch this transfer done event
AnnaBridge 175:b96e65c34a4d 786 if (event_dma & DMA_EVENT_TRANSFER_DONE) {
AnnaBridge 175:b96e65c34a4d 787 obj->tx_buff.pos = obj->tx_buff.length;
AnnaBridge 175:b96e65c34a4d 788 }
AnnaBridge 175:b96e65c34a4d 789 // TODO: Pass this error to caller
AnnaBridge 175:b96e65c34a4d 790 if (event_dma & DMA_EVENT_TIMEOUT) {
AnnaBridge 175:b96e65c34a4d 791 }
AnnaBridge 175:b96e65c34a4d 792
AnnaBridge 175:b96e65c34a4d 793 const struct nu_modinit_s *modinit = get_modinit(obj->spi.spi, spi_modinit_tab);
AnnaBridge 175:b96e65c34a4d 794 MBED_ASSERT(modinit != NULL);
AnnaBridge 175:b96e65c34a4d 795 MBED_ASSERT((SPIName) modinit->modname == obj->spi.spi);
AnnaBridge 175:b96e65c34a4d 796
AnnaBridge 175:b96e65c34a4d 797 void (*vec)(void) = (void (*)(void)) NVIC_GetVector(modinit->irq_n);
AnnaBridge 175:b96e65c34a4d 798 vec();
AnnaBridge 175:b96e65c34a4d 799 }
AnnaBridge 175:b96e65c34a4d 800
AnnaBridge 175:b96e65c34a4d 801 static void spi_dma_handler_rx(uint32_t id, uint32_t event_dma)
AnnaBridge 175:b96e65c34a4d 802 {
AnnaBridge 175:b96e65c34a4d 803 spi_t *obj = (spi_t *) id;
AnnaBridge 175:b96e65c34a4d 804
AnnaBridge 175:b96e65c34a4d 805 // TODO: Pass this error to caller
AnnaBridge 175:b96e65c34a4d 806 if (event_dma & DMA_EVENT_ABORT) {
AnnaBridge 175:b96e65c34a4d 807 }
AnnaBridge 175:b96e65c34a4d 808 // Expect SPI IRQ will catch this transfer done event
AnnaBridge 175:b96e65c34a4d 809 if (event_dma & DMA_EVENT_TRANSFER_DONE) {
AnnaBridge 175:b96e65c34a4d 810 obj->rx_buff.pos = obj->rx_buff.length;
AnnaBridge 175:b96e65c34a4d 811 }
AnnaBridge 175:b96e65c34a4d 812 // TODO: Pass this error to caller
AnnaBridge 175:b96e65c34a4d 813 if (event_dma & DMA_EVENT_TIMEOUT) {
AnnaBridge 175:b96e65c34a4d 814 }
AnnaBridge 175:b96e65c34a4d 815
AnnaBridge 175:b96e65c34a4d 816 const struct nu_modinit_s *modinit = get_modinit(obj->spi.spi, spi_modinit_tab);
AnnaBridge 175:b96e65c34a4d 817 MBED_ASSERT(modinit != NULL);
AnnaBridge 175:b96e65c34a4d 818 MBED_ASSERT((SPIName) modinit->modname == obj->spi.spi);
AnnaBridge 175:b96e65c34a4d 819
AnnaBridge 175:b96e65c34a4d 820 void (*vec)(void) = (void (*)(void)) NVIC_GetVector(modinit->irq_n);
AnnaBridge 175:b96e65c34a4d 821 vec();
AnnaBridge 175:b96e65c34a4d 822 }
AnnaBridge 175:b96e65c34a4d 823
AnnaBridge 175:b96e65c34a4d 824 #endif
AnnaBridge 175:b96e65c34a4d 825
AnnaBridge 175:b96e65c34a4d 826 #endif