John Karatka / mbed

mbed

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targets/TARGET_Freescale/TARGET_KLXX/rtc_api.c@182:57724642e740, 2018-02-16 (annotated)

Committer:
AnnaBridge
Date:
Fri Feb 16 16:09:33 2018 +0000
Revision:
182:57724642e740
Parent:
176:af195413fb11 
mbed-dev library. Release version 159.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /* mbed Microcontroller Library
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2006-2013 ARM Limited
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Licensed under the Apache License, Version 2.0 (the "License");
<> 144:ef7eb2e8f9f7 5 * you may not use this file except in compliance with the License.
<> 144:ef7eb2e8f9f7 6 * You may obtain a copy of the License at
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * http://www.apache.org/licenses/LICENSE-2.0
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * Unless required by applicable law or agreed to in writing, software
<> 144:ef7eb2e8f9f7 11 * distributed under the License is distributed on an "AS IS" BASIS,
<> 144:ef7eb2e8f9f7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<> 144:ef7eb2e8f9f7 13 * See the License for the specific language governing permissions and
<> 144:ef7eb2e8f9f7 14 * limitations under the License.
<> 144:ef7eb2e8f9f7 15 */
<> 144:ef7eb2e8f9f7 16
<> 144:ef7eb2e8f9f7 17 #if DEVICE_RTC
<> 144:ef7eb2e8f9f7 18
<> 144:ef7eb2e8f9f7 19 #include "rtc_api.h"
<> 144:ef7eb2e8f9f7 20 #include "PeripheralPins.h"
<> 144:ef7eb2e8f9f7 21 #include "clk_freqs.h"
<> 144:ef7eb2e8f9f7 22
<> 144:ef7eb2e8f9f7 23 static void init(void) {
<> 144:ef7eb2e8f9f7 24 // enable RTC clock
<> 144:ef7eb2e8f9f7 25 SIM->SCGC6 |= SIM_SCGC6_RTC_MASK;
<> 144:ef7eb2e8f9f7 26
<> 144:ef7eb2e8f9f7 27 // select RTC clock source
<> 144:ef7eb2e8f9f7 28 SIM->SOPT1 &= ~SIM_SOPT1_OSC32KSEL_MASK;
AnnaBridge 176:af195413fb11 29
<> 144:ef7eb2e8f9f7 30 // Enable external crystal source if clock source is 32KHz
<> 144:ef7eb2e8f9f7 31 if (extosc_frequency()==32768) {
<> 144:ef7eb2e8f9f7 32 SIM->SOPT1 |= SIM_SOPT1_OSC32KSEL(OSC32KCLK);
<> 144:ef7eb2e8f9f7 33 }
<> 144:ef7eb2e8f9f7 34 else{
<> 144:ef7eb2e8f9f7 35 // If main clock is NOT 32KHz crystal, use external 32KHz clock source defined in PeripheralPins.c
<> 144:ef7eb2e8f9f7 36 SIM->SOPT1 |= SIM_SOPT1_OSC32KSEL(PinMap_RTC[0].peripheral);
<> 144:ef7eb2e8f9f7 37 pinmap_pinout(PinMap_RTC[0].pin, PinMap_RTC); //Map RTC clk input (if not NC)
<> 144:ef7eb2e8f9f7 38 }
<> 144:ef7eb2e8f9f7 39 }
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 void rtc_init(void) {
<> 144:ef7eb2e8f9f7 42 init();
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 // Configure the TSR. default value: 1
<> 144:ef7eb2e8f9f7 45 RTC->TSR = 1;
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 // Configure Time Compensation Register to calibrate RTC accuracy
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 // dissable LRL lock
<> 144:ef7eb2e8f9f7 50 RTC->LR &= ~RTC_LR_LRL_MASK;
<> 144:ef7eb2e8f9f7 51 // RTC->TCR: RTC_TCR_CIR_MASK,RTC_TCR_CIR(x)=0,RTC_TCR_TCR(x)=0 Default no correction
<> 144:ef7eb2e8f9f7 52 RTC->TCR = RTC_TCR_CIR(0) | RTC_TCR_TCR(0);
<> 144:ef7eb2e8f9f7 53 /*
<> 144:ef7eb2e8f9f7 54 RTC_TCR_CIR(x) sets the compensation interval in seconds from 1 to 256.
<> 144:ef7eb2e8f9f7 55 0x05 will apply the compensation once every 4 seconds.
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 RTC_TCR_TCR(x) sets the Register Overflow
<> 144:ef7eb2e8f9f7 58 0x80 Time Prescaler Register overflows every 32896 clock cycles. (+128)
<> 144:ef7eb2e8f9f7 59 ... ... RTC runs slower
<> 144:ef7eb2e8f9f7 60 0xFF Time Prescaler Register overflows every 32769 clock cycles.
<> 144:ef7eb2e8f9f7 61 0x00 Time Prescaler Register overflows every 32768 clock cycles, Default.
<> 144:ef7eb2e8f9f7 62 0x01 Time Prescaler Register overflows every 32767 clock cycles.
<> 144:ef7eb2e8f9f7 63 ... ... RTC runs faster
<> 144:ef7eb2e8f9f7 64 0x7F Time Prescaler Register overflows every 32641 clock cycles. (-128)
<> 144:ef7eb2e8f9f7 65 */
<> 144:ef7eb2e8f9f7 66 // enable TCL lock
<> 144:ef7eb2e8f9f7 67 RTC->LR |= RTC_LR_TCL_MASK;
<> 144:ef7eb2e8f9f7 68 // enable LRL lock
<> 144:ef7eb2e8f9f7 69 RTC->LR |= RTC_LR_LRL_MASK;
<> 144:ef7eb2e8f9f7 70
<> 144:ef7eb2e8f9f7 71 // enable counter
<> 144:ef7eb2e8f9f7 72 RTC->SR |= RTC_SR_TCE_MASK;
<> 144:ef7eb2e8f9f7 73 }
<> 144:ef7eb2e8f9f7 74
<> 144:ef7eb2e8f9f7 75 void rtc_free(void) {
<> 144:ef7eb2e8f9f7 76 // [TODO]
<> 144:ef7eb2e8f9f7 77 }
<> 144:ef7eb2e8f9f7 78
<> 144:ef7eb2e8f9f7 79 /*
<> 144:ef7eb2e8f9f7 80 * Little check routine to see if the RTC has been enabled
<> 144:ef7eb2e8f9f7 81 * 0 = Disabled, 1 = Enabled
<> 144:ef7eb2e8f9f7 82 */
<> 144:ef7eb2e8f9f7 83 int rtc_isenabled(void) {
<> 144:ef7eb2e8f9f7 84 // even if the RTC module is enabled,
<> 144:ef7eb2e8f9f7 85 // as we use RTC_CLKIN and an external clock,
<> 144:ef7eb2e8f9f7 86 // we need to reconfigure the pins. That is why we
<> 144:ef7eb2e8f9f7 87 // call init() if the rtc is enabled
<> 144:ef7eb2e8f9f7 88
<> 144:ef7eb2e8f9f7 89 // if RTC not enabled return 0
<> 144:ef7eb2e8f9f7 90 SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK;
<> 144:ef7eb2e8f9f7 91 SIM->SCGC6 |= SIM_SCGC6_RTC_MASK;
<> 144:ef7eb2e8f9f7 92 if ((RTC->SR & RTC_SR_TCE_MASK) == 0)
<> 144:ef7eb2e8f9f7 93 return 0;
<> 144:ef7eb2e8f9f7 94
<> 144:ef7eb2e8f9f7 95 init();
<> 144:ef7eb2e8f9f7 96 return 1;
<> 144:ef7eb2e8f9f7 97 }
<> 144:ef7eb2e8f9f7 98
<> 144:ef7eb2e8f9f7 99 time_t rtc_read(void) {
<> 144:ef7eb2e8f9f7 100 return RTC->TSR;
<> 144:ef7eb2e8f9f7 101 }
<> 144:ef7eb2e8f9f7 102
<> 144:ef7eb2e8f9f7 103 void rtc_write(time_t t) {
<> 144:ef7eb2e8f9f7 104 // disable counter
<> 144:ef7eb2e8f9f7 105 RTC->SR &= ~RTC_SR_TCE_MASK;
<> 144:ef7eb2e8f9f7 106
<> 144:ef7eb2e8f9f7 107 // write seconds
<> 144:ef7eb2e8f9f7 108 RTC->TSR = t;
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110 // re-enable counter
<> 144:ef7eb2e8f9f7 111 RTC->SR |= RTC_SR_TCE_MASK;
<> 144:ef7eb2e8f9f7 112 }
<> 144:ef7eb2e8f9f7 113
<> 144:ef7eb2e8f9f7 114 #endif