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targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_pwr.h@154:37f96f9d4de2, 2017-01-04 (annotated)

Committer:
<>
Date:
Wed Jan 04 16:58:05 2017 +0000
Revision:
154:37f96f9d4de2
Child:
165:e614a9f1c9e2
This updates the lib to the mbed lib v133

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 154:37f96f9d4de2 1 /**
<> 154:37f96f9d4de2 2 ******************************************************************************
<> 154:37f96f9d4de2 3 * @file stm32f1xx_ll_pwr.h
<> 154:37f96f9d4de2 4 * @author MCD Application Team
<> 154:37f96f9d4de2 5 * @version $VERSION$
<> 154:37f96f9d4de2 6 * @date $DATE$
<> 154:37f96f9d4de2 7 * @brief Header file of PWR LL module.
<> 154:37f96f9d4de2 8 ******************************************************************************
<> 154:37f96f9d4de2 9 * @attention
<> 154:37f96f9d4de2 10 *
<> 154:37f96f9d4de2 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 154:37f96f9d4de2 12 *
<> 154:37f96f9d4de2 13 * Redistribution and use in source and binary forms, with or without modification,
<> 154:37f96f9d4de2 14 * are permitted provided that the following conditions are met:
<> 154:37f96f9d4de2 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 154:37f96f9d4de2 16 * this list of conditions and the following disclaimer.
<> 154:37f96f9d4de2 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 154:37f96f9d4de2 18 * this list of conditions and the following disclaimer in the documentation
<> 154:37f96f9d4de2 19 * and/or other materials provided with the distribution.
<> 154:37f96f9d4de2 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 154:37f96f9d4de2 21 * may be used to endorse or promote products derived from this software
<> 154:37f96f9d4de2 22 * without specific prior written permission.
<> 154:37f96f9d4de2 23 *
<> 154:37f96f9d4de2 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 154:37f96f9d4de2 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 154:37f96f9d4de2 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 154:37f96f9d4de2 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 154:37f96f9d4de2 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 154:37f96f9d4de2 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 154:37f96f9d4de2 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 154:37f96f9d4de2 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 154:37f96f9d4de2 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 154:37f96f9d4de2 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 154:37f96f9d4de2 34 *
<> 154:37f96f9d4de2 35 ******************************************************************************
<> 154:37f96f9d4de2 36 */
<> 154:37f96f9d4de2 37
<> 154:37f96f9d4de2 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 154:37f96f9d4de2 39 #ifndef __STM32F1xx_LL_PWR_H
<> 154:37f96f9d4de2 40 #define __STM32F1xx_LL_PWR_H
<> 154:37f96f9d4de2 41
<> 154:37f96f9d4de2 42 #ifdef __cplusplus
<> 154:37f96f9d4de2 43 extern "C" {
<> 154:37f96f9d4de2 44 #endif
<> 154:37f96f9d4de2 45
<> 154:37f96f9d4de2 46 /* Includes ------------------------------------------------------------------*/
<> 154:37f96f9d4de2 47 #include "stm32f1xx.h"
<> 154:37f96f9d4de2 48
<> 154:37f96f9d4de2 49 /** @addtogroup STM32F1xx_LL_Driver
<> 154:37f96f9d4de2 50 * @{
<> 154:37f96f9d4de2 51 */
<> 154:37f96f9d4de2 52
<> 154:37f96f9d4de2 53 #if defined(PWR)
<> 154:37f96f9d4de2 54
<> 154:37f96f9d4de2 55 /** @defgroup PWR_LL PWR
<> 154:37f96f9d4de2 56 * @{
<> 154:37f96f9d4de2 57 */
<> 154:37f96f9d4de2 58
<> 154:37f96f9d4de2 59 /* Private types -------------------------------------------------------------*/
<> 154:37f96f9d4de2 60 /* Private variables ---------------------------------------------------------*/
<> 154:37f96f9d4de2 61 /* Private constants ---------------------------------------------------------*/
<> 154:37f96f9d4de2 62 /* Private macros ------------------------------------------------------------*/
<> 154:37f96f9d4de2 63 /* Exported types ------------------------------------------------------------*/
<> 154:37f96f9d4de2 64 /* Exported constants --------------------------------------------------------*/
<> 154:37f96f9d4de2 65 /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
<> 154:37f96f9d4de2 66 * @{
<> 154:37f96f9d4de2 67 */
<> 154:37f96f9d4de2 68
<> 154:37f96f9d4de2 69 /** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
<> 154:37f96f9d4de2 70 * @brief Flags defines which can be used with LL_PWR_WriteReg function
<> 154:37f96f9d4de2 71 * @{
<> 154:37f96f9d4de2 72 */
<> 154:37f96f9d4de2 73 #define LL_PWR_CR_CSBF PWR_CR_CSBF /*!< Clear standby flag */
<> 154:37f96f9d4de2 74 #define LL_PWR_CR_CWUF PWR_CR_CWUF /*!< Clear wakeup flag */
<> 154:37f96f9d4de2 75 /**
<> 154:37f96f9d4de2 76 * @}
<> 154:37f96f9d4de2 77 */
<> 154:37f96f9d4de2 78
<> 154:37f96f9d4de2 79 /** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
<> 154:37f96f9d4de2 80 * @brief Flags defines which can be used with LL_PWR_ReadReg function
<> 154:37f96f9d4de2 81 * @{
<> 154:37f96f9d4de2 82 */
<> 154:37f96f9d4de2 83 #define LL_PWR_CSR_WUF PWR_CSR_WUF /*!< Wakeup flag */
<> 154:37f96f9d4de2 84 #define LL_PWR_CSR_SBF PWR_CSR_SBF /*!< Standby flag */
<> 154:37f96f9d4de2 85 #define LL_PWR_CSR_PVDO PWR_CSR_PVDO /*!< Power voltage detector output flag */
<> 154:37f96f9d4de2 86 #define LL_PWR_CSR_EWUP1 PWR_CSR_EWUP /*!< Enable WKUP pin 1 */
<> 154:37f96f9d4de2 87 /**
<> 154:37f96f9d4de2 88 * @}
<> 154:37f96f9d4de2 89 */
<> 154:37f96f9d4de2 90
<> 154:37f96f9d4de2 91
<> 154:37f96f9d4de2 92 /** @defgroup PWR_LL_EC_MODE_PWR Mode Power
<> 154:37f96f9d4de2 93 * @{
<> 154:37f96f9d4de2 94 */
<> 154:37f96f9d4de2 95 #define LL_PWR_MODE_STOP_MAINREGU 0x00000000U /*!< Enter Stop mode when the CPU enters deepsleep */
<> 154:37f96f9d4de2 96 #define LL_PWR_MODE_STOP_LPREGU (PWR_CR_LPDS) /*!< Enter Stop mode (ith low power regulator ON) when the CPU enters deepsleep */
<> 154:37f96f9d4de2 97 #define LL_PWR_MODE_STANDBY (PWR_CR_PDDS) /*!< Enter Standby mode when the CPU enters deepsleep */
<> 154:37f96f9d4de2 98 /**
<> 154:37f96f9d4de2 99 * @}
<> 154:37f96f9d4de2 100 */
<> 154:37f96f9d4de2 101
<> 154:37f96f9d4de2 102 /** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE Regulator Mode In Deep Sleep Mode
<> 154:37f96f9d4de2 103 * @{
<> 154:37f96f9d4de2 104 */
<> 154:37f96f9d4de2 105 #define LL_PWR_REGU_DSMODE_MAIN 0x00000000U /*!< Voltage regulator in main mode during deepsleep mode */
<> 154:37f96f9d4de2 106 #define LL_PWR_REGU_DSMODE_LOW_POWER (PWR_CR_LPDS) /*!< Voltage regulator in low-power mode during deepsleep mode */
<> 154:37f96f9d4de2 107 /**
<> 154:37f96f9d4de2 108 * @}
<> 154:37f96f9d4de2 109 */
<> 154:37f96f9d4de2 110
<> 154:37f96f9d4de2 111 /** @defgroup PWR_LL_EC_PVDLEVEL Power Voltage Detector Level
<> 154:37f96f9d4de2 112 * @{
<> 154:37f96f9d4de2 113 */
<> 154:37f96f9d4de2 114 #define LL_PWR_PVDLEVEL_0 (PWR_CR_PLS_LEV0) /*!< Voltage threshold detected by PVD 2.2 V */
<> 154:37f96f9d4de2 115 #define LL_PWR_PVDLEVEL_1 (PWR_CR_PLS_LEV1) /*!< Voltage threshold detected by PVD 2.3 V */
<> 154:37f96f9d4de2 116 #define LL_PWR_PVDLEVEL_2 (PWR_CR_PLS_LEV2) /*!< Voltage threshold detected by PVD 2.4 V */
<> 154:37f96f9d4de2 117 #define LL_PWR_PVDLEVEL_3 (PWR_CR_PLS_LEV3) /*!< Voltage threshold detected by PVD 2.5 V */
<> 154:37f96f9d4de2 118 #define LL_PWR_PVDLEVEL_4 (PWR_CR_PLS_LEV4) /*!< Voltage threshold detected by PVD 2.6 V */
<> 154:37f96f9d4de2 119 #define LL_PWR_PVDLEVEL_5 (PWR_CR_PLS_LEV5) /*!< Voltage threshold detected by PVD 2.7 V */
<> 154:37f96f9d4de2 120 #define LL_PWR_PVDLEVEL_6 (PWR_CR_PLS_LEV6) /*!< Voltage threshold detected by PVD 2.8 V */
<> 154:37f96f9d4de2 121 #define LL_PWR_PVDLEVEL_7 (PWR_CR_PLS_LEV7) /*!< Voltage threshold detected by PVD 2.9 V */
<> 154:37f96f9d4de2 122 /**
<> 154:37f96f9d4de2 123 * @}
<> 154:37f96f9d4de2 124 */
<> 154:37f96f9d4de2 125 /** @defgroup PWR_LL_EC_WAKEUP_PIN Wakeup Pins
<> 154:37f96f9d4de2 126 * @{
<> 154:37f96f9d4de2 127 */
<> 154:37f96f9d4de2 128 #define LL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP) /*!< WKUP pin 1 : PA0 */
<> 154:37f96f9d4de2 129 /**
<> 154:37f96f9d4de2 130 * @}
<> 154:37f96f9d4de2 131 */
<> 154:37f96f9d4de2 132
<> 154:37f96f9d4de2 133 /**
<> 154:37f96f9d4de2 134 * @}
<> 154:37f96f9d4de2 135 */
<> 154:37f96f9d4de2 136
<> 154:37f96f9d4de2 137
<> 154:37f96f9d4de2 138 /* Exported macro ------------------------------------------------------------*/
<> 154:37f96f9d4de2 139 /** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
<> 154:37f96f9d4de2 140 * @{
<> 154:37f96f9d4de2 141 */
<> 154:37f96f9d4de2 142
<> 154:37f96f9d4de2 143 /** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros
<> 154:37f96f9d4de2 144 * @{
<> 154:37f96f9d4de2 145 */
<> 154:37f96f9d4de2 146
<> 154:37f96f9d4de2 147 /**
<> 154:37f96f9d4de2 148 * @brief Write a value in PWR register
<> 154:37f96f9d4de2 149 * @param __REG__ Register to be written
<> 154:37f96f9d4de2 150 * @param __VALUE__ Value to be written in the register
<> 154:37f96f9d4de2 151 * @retval None
<> 154:37f96f9d4de2 152 */
<> 154:37f96f9d4de2 153 #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
<> 154:37f96f9d4de2 154
<> 154:37f96f9d4de2 155 /**
<> 154:37f96f9d4de2 156 * @brief Read a value in PWR register
<> 154:37f96f9d4de2 157 * @param __REG__ Register to be read
<> 154:37f96f9d4de2 158 * @retval Register value
<> 154:37f96f9d4de2 159 */
<> 154:37f96f9d4de2 160 #define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
<> 154:37f96f9d4de2 161 /**
<> 154:37f96f9d4de2 162 * @}
<> 154:37f96f9d4de2 163 */
<> 154:37f96f9d4de2 164
<> 154:37f96f9d4de2 165 /**
<> 154:37f96f9d4de2 166 * @}
<> 154:37f96f9d4de2 167 */
<> 154:37f96f9d4de2 168
<> 154:37f96f9d4de2 169 /* Exported functions --------------------------------------------------------*/
<> 154:37f96f9d4de2 170 /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
<> 154:37f96f9d4de2 171 * @{
<> 154:37f96f9d4de2 172 */
<> 154:37f96f9d4de2 173
<> 154:37f96f9d4de2 174 /** @defgroup PWR_LL_EF_Configuration Configuration
<> 154:37f96f9d4de2 175 * @{
<> 154:37f96f9d4de2 176 */
<> 154:37f96f9d4de2 177
<> 154:37f96f9d4de2 178 /**
<> 154:37f96f9d4de2 179 * @brief Enable access to the backup domain
<> 154:37f96f9d4de2 180 * @rmtoll CR DBP LL_PWR_EnableBkUpAccess
<> 154:37f96f9d4de2 181 * @retval None
<> 154:37f96f9d4de2 182 */
<> 154:37f96f9d4de2 183 __STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
<> 154:37f96f9d4de2 184 {
<> 154:37f96f9d4de2 185 SET_BIT(PWR->CR, PWR_CR_DBP);
<> 154:37f96f9d4de2 186 }
<> 154:37f96f9d4de2 187
<> 154:37f96f9d4de2 188 /**
<> 154:37f96f9d4de2 189 * @brief Disable access to the backup domain
<> 154:37f96f9d4de2 190 * @rmtoll CR DBP LL_PWR_DisableBkUpAccess
<> 154:37f96f9d4de2 191 * @retval None
<> 154:37f96f9d4de2 192 */
<> 154:37f96f9d4de2 193 __STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
<> 154:37f96f9d4de2 194 {
<> 154:37f96f9d4de2 195 CLEAR_BIT(PWR->CR, PWR_CR_DBP);
<> 154:37f96f9d4de2 196 }
<> 154:37f96f9d4de2 197
<> 154:37f96f9d4de2 198 /**
<> 154:37f96f9d4de2 199 * @brief Check if the backup domain is enabled
<> 154:37f96f9d4de2 200 * @rmtoll CR DBP LL_PWR_IsEnabledBkUpAccess
<> 154:37f96f9d4de2 201 * @retval State of bit (1 or 0).
<> 154:37f96f9d4de2 202 */
<> 154:37f96f9d4de2 203 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
<> 154:37f96f9d4de2 204 {
<> 154:37f96f9d4de2 205 return (READ_BIT(PWR->CR, PWR_CR_DBP) == (PWR_CR_DBP));
<> 154:37f96f9d4de2 206 }
<> 154:37f96f9d4de2 207
<> 154:37f96f9d4de2 208 /**
<> 154:37f96f9d4de2 209 * @brief Set voltage regulator mode during deep sleep mode
<> 154:37f96f9d4de2 210 * @rmtoll CR LPDS LL_PWR_SetRegulModeDS
<> 154:37f96f9d4de2 211 * @param RegulMode This parameter can be one of the following values:
<> 154:37f96f9d4de2 212 * @arg @ref LL_PWR_REGU_DSMODE_MAIN
<> 154:37f96f9d4de2 213 * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
<> 154:37f96f9d4de2 214 * @retval None
<> 154:37f96f9d4de2 215 */
<> 154:37f96f9d4de2 216 __STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode)
<> 154:37f96f9d4de2 217 {
<> 154:37f96f9d4de2 218 MODIFY_REG(PWR->CR, PWR_CR_LPDS, RegulMode);
<> 154:37f96f9d4de2 219 }
<> 154:37f96f9d4de2 220
<> 154:37f96f9d4de2 221 /**
<> 154:37f96f9d4de2 222 * @brief Get voltage regulator mode during deep sleep mode
<> 154:37f96f9d4de2 223 * @rmtoll CR LPDS LL_PWR_GetRegulModeDS
<> 154:37f96f9d4de2 224 * @retval Returned value can be one of the following values:
<> 154:37f96f9d4de2 225 * @arg @ref LL_PWR_REGU_DSMODE_MAIN
<> 154:37f96f9d4de2 226 * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
<> 154:37f96f9d4de2 227 */
<> 154:37f96f9d4de2 228 __STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void)
<> 154:37f96f9d4de2 229 {
<> 154:37f96f9d4de2 230 return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_LPDS));
<> 154:37f96f9d4de2 231 }
<> 154:37f96f9d4de2 232
<> 154:37f96f9d4de2 233 /**
<> 154:37f96f9d4de2 234 * @brief Set power down mode when CPU enters deepsleep
<> 154:37f96f9d4de2 235 * @rmtoll CR PDDS LL_PWR_SetPowerMode\n
<> 154:37f96f9d4de2 236 * @rmtoll CR LPDS LL_PWR_SetPowerMode
<> 154:37f96f9d4de2 237 * @param PDMode This parameter can be one of the following values:
<> 154:37f96f9d4de2 238 * @arg @ref LL_PWR_MODE_STOP_MAINREGU
<> 154:37f96f9d4de2 239 * @arg @ref LL_PWR_MODE_STOP_LPREGU
<> 154:37f96f9d4de2 240 * @arg @ref LL_PWR_MODE_STANDBY
<> 154:37f96f9d4de2 241 * @retval None
<> 154:37f96f9d4de2 242 */
<> 154:37f96f9d4de2 243 __STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t PDMode)
<> 154:37f96f9d4de2 244 {
<> 154:37f96f9d4de2 245 MODIFY_REG(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS), PDMode);
<> 154:37f96f9d4de2 246 }
<> 154:37f96f9d4de2 247
<> 154:37f96f9d4de2 248 /**
<> 154:37f96f9d4de2 249 * @brief Get power down mode when CPU enters deepsleep
<> 154:37f96f9d4de2 250 * @rmtoll CR PDDS LL_PWR_GetPowerMode\n
<> 154:37f96f9d4de2 251 * @rmtoll CR LPDS LL_PWR_GetPowerMode
<> 154:37f96f9d4de2 252 * @retval Returned value can be one of the following values:
<> 154:37f96f9d4de2 253 * @arg @ref LL_PWR_MODE_STOP_MAINREGU
<> 154:37f96f9d4de2 254 * @arg @ref LL_PWR_MODE_STOP_LPREGU
<> 154:37f96f9d4de2 255 * @arg @ref LL_PWR_MODE_STANDBY
<> 154:37f96f9d4de2 256 */
<> 154:37f96f9d4de2 257 __STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
<> 154:37f96f9d4de2 258 {
<> 154:37f96f9d4de2 259 return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS)));
<> 154:37f96f9d4de2 260 }
<> 154:37f96f9d4de2 261
<> 154:37f96f9d4de2 262 /**
<> 154:37f96f9d4de2 263 * @brief Configure the voltage threshold detected by the Power Voltage Detector
<> 154:37f96f9d4de2 264 * @rmtoll CR PLS LL_PWR_SetPVDLevel
<> 154:37f96f9d4de2 265 * @param PVDLevel This parameter can be one of the following values:
<> 154:37f96f9d4de2 266 * @arg @ref LL_PWR_PVDLEVEL_0
<> 154:37f96f9d4de2 267 * @arg @ref LL_PWR_PVDLEVEL_1
<> 154:37f96f9d4de2 268 * @arg @ref LL_PWR_PVDLEVEL_2
<> 154:37f96f9d4de2 269 * @arg @ref LL_PWR_PVDLEVEL_3
<> 154:37f96f9d4de2 270 * @arg @ref LL_PWR_PVDLEVEL_4
<> 154:37f96f9d4de2 271 * @arg @ref LL_PWR_PVDLEVEL_5
<> 154:37f96f9d4de2 272 * @arg @ref LL_PWR_PVDLEVEL_6
<> 154:37f96f9d4de2 273 * @arg @ref LL_PWR_PVDLEVEL_7
<> 154:37f96f9d4de2 274 * @retval None
<> 154:37f96f9d4de2 275 */
<> 154:37f96f9d4de2 276 __STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
<> 154:37f96f9d4de2 277 {
<> 154:37f96f9d4de2 278 MODIFY_REG(PWR->CR, PWR_CR_PLS, PVDLevel);
<> 154:37f96f9d4de2 279 }
<> 154:37f96f9d4de2 280
<> 154:37f96f9d4de2 281 /**
<> 154:37f96f9d4de2 282 * @brief Get the voltage threshold detection
<> 154:37f96f9d4de2 283 * @rmtoll CR PLS LL_PWR_GetPVDLevel
<> 154:37f96f9d4de2 284 * @retval Returned value can be one of the following values:
<> 154:37f96f9d4de2 285 * @arg @ref LL_PWR_PVDLEVEL_0
<> 154:37f96f9d4de2 286 * @arg @ref LL_PWR_PVDLEVEL_1
<> 154:37f96f9d4de2 287 * @arg @ref LL_PWR_PVDLEVEL_2
<> 154:37f96f9d4de2 288 * @arg @ref LL_PWR_PVDLEVEL_3
<> 154:37f96f9d4de2 289 * @arg @ref LL_PWR_PVDLEVEL_4
<> 154:37f96f9d4de2 290 * @arg @ref LL_PWR_PVDLEVEL_5
<> 154:37f96f9d4de2 291 * @arg @ref LL_PWR_PVDLEVEL_6
<> 154:37f96f9d4de2 292 * @arg @ref LL_PWR_PVDLEVEL_7
<> 154:37f96f9d4de2 293 */
<> 154:37f96f9d4de2 294 __STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
<> 154:37f96f9d4de2 295 {
<> 154:37f96f9d4de2 296 return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_PLS));
<> 154:37f96f9d4de2 297 }
<> 154:37f96f9d4de2 298
<> 154:37f96f9d4de2 299 /**
<> 154:37f96f9d4de2 300 * @brief Enable Power Voltage Detector
<> 154:37f96f9d4de2 301 * @rmtoll CR PVDE LL_PWR_EnablePVD
<> 154:37f96f9d4de2 302 * @retval None
<> 154:37f96f9d4de2 303 */
<> 154:37f96f9d4de2 304 __STATIC_INLINE void LL_PWR_EnablePVD(void)
<> 154:37f96f9d4de2 305 {
<> 154:37f96f9d4de2 306 SET_BIT(PWR->CR, PWR_CR_PVDE);
<> 154:37f96f9d4de2 307 }
<> 154:37f96f9d4de2 308
<> 154:37f96f9d4de2 309 /**
<> 154:37f96f9d4de2 310 * @brief Disable Power Voltage Detector
<> 154:37f96f9d4de2 311 * @rmtoll CR PVDE LL_PWR_DisablePVD
<> 154:37f96f9d4de2 312 * @retval None
<> 154:37f96f9d4de2 313 */
<> 154:37f96f9d4de2 314 __STATIC_INLINE void LL_PWR_DisablePVD(void)
<> 154:37f96f9d4de2 315 {
<> 154:37f96f9d4de2 316 CLEAR_BIT(PWR->CR, PWR_CR_PVDE);
<> 154:37f96f9d4de2 317 }
<> 154:37f96f9d4de2 318
<> 154:37f96f9d4de2 319 /**
<> 154:37f96f9d4de2 320 * @brief Check if Power Voltage Detector is enabled
<> 154:37f96f9d4de2 321 * @rmtoll CR PVDE LL_PWR_IsEnabledPVD
<> 154:37f96f9d4de2 322 * @retval State of bit (1 or 0).
<> 154:37f96f9d4de2 323 */
<> 154:37f96f9d4de2 324 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
<> 154:37f96f9d4de2 325 {
<> 154:37f96f9d4de2 326 return (READ_BIT(PWR->CR, PWR_CR_PVDE) == (PWR_CR_PVDE));
<> 154:37f96f9d4de2 327 }
<> 154:37f96f9d4de2 328
<> 154:37f96f9d4de2 329 /**
<> 154:37f96f9d4de2 330 * @brief Enable the WakeUp PINx functionality
<> 154:37f96f9d4de2 331 * @rmtoll CSR EWUP LL_PWR_EnableWakeUpPin
<> 154:37f96f9d4de2 332 * @param WakeUpPin This parameter can be one of the following values:
<> 154:37f96f9d4de2 333 * @arg @ref LL_PWR_WAKEUP_PIN1
<> 154:37f96f9d4de2 334 * @retval None
<> 154:37f96f9d4de2 335 */
<> 154:37f96f9d4de2 336 __STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
<> 154:37f96f9d4de2 337 {
<> 154:37f96f9d4de2 338 SET_BIT(PWR->CSR, WakeUpPin);
<> 154:37f96f9d4de2 339 }
<> 154:37f96f9d4de2 340
<> 154:37f96f9d4de2 341 /**
<> 154:37f96f9d4de2 342 * @brief Disable the WakeUp PINx functionality
<> 154:37f96f9d4de2 343 * @rmtoll CSR EWUP LL_PWR_DisableWakeUpPin
<> 154:37f96f9d4de2 344 * @param WakeUpPin This parameter can be one of the following values:
<> 154:37f96f9d4de2 345 * @arg @ref LL_PWR_WAKEUP_PIN1
<> 154:37f96f9d4de2 346 * @retval None
<> 154:37f96f9d4de2 347 */
<> 154:37f96f9d4de2 348 __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
<> 154:37f96f9d4de2 349 {
<> 154:37f96f9d4de2 350 CLEAR_BIT(PWR->CSR, WakeUpPin);
<> 154:37f96f9d4de2 351 }
<> 154:37f96f9d4de2 352
<> 154:37f96f9d4de2 353 /**
<> 154:37f96f9d4de2 354 * @brief Check if the WakeUp PINx functionality is enabled
<> 154:37f96f9d4de2 355 * @rmtoll CSR EWUP LL_PWR_IsEnabledWakeUpPin
<> 154:37f96f9d4de2 356 * @param WakeUpPin This parameter can be one of the following values:
<> 154:37f96f9d4de2 357 * @arg @ref LL_PWR_WAKEUP_PIN1
<> 154:37f96f9d4de2 358 * @retval State of bit (1 or 0).
<> 154:37f96f9d4de2 359 */
<> 154:37f96f9d4de2 360 __STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
<> 154:37f96f9d4de2 361 {
<> 154:37f96f9d4de2 362 return (READ_BIT(PWR->CSR, WakeUpPin) == (WakeUpPin));
<> 154:37f96f9d4de2 363 }
<> 154:37f96f9d4de2 364
<> 154:37f96f9d4de2 365
<> 154:37f96f9d4de2 366 /**
<> 154:37f96f9d4de2 367 * @}
<> 154:37f96f9d4de2 368 */
<> 154:37f96f9d4de2 369
<> 154:37f96f9d4de2 370 /** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
<> 154:37f96f9d4de2 371 * @{
<> 154:37f96f9d4de2 372 */
<> 154:37f96f9d4de2 373
<> 154:37f96f9d4de2 374 /**
<> 154:37f96f9d4de2 375 * @brief Get Wake-up Flag
<> 154:37f96f9d4de2 376 * @rmtoll CSR WUF LL_PWR_IsActiveFlag_WU
<> 154:37f96f9d4de2 377 * @retval State of bit (1 or 0).
<> 154:37f96f9d4de2 378 */
<> 154:37f96f9d4de2 379 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU(void)
<> 154:37f96f9d4de2 380 {
<> 154:37f96f9d4de2 381 return (READ_BIT(PWR->CSR, PWR_CSR_WUF) == (PWR_CSR_WUF));
<> 154:37f96f9d4de2 382 }
<> 154:37f96f9d4de2 383
<> 154:37f96f9d4de2 384 /**
<> 154:37f96f9d4de2 385 * @brief Get Standby Flag
<> 154:37f96f9d4de2 386 * @rmtoll CSR SBF LL_PWR_IsActiveFlag_SB
<> 154:37f96f9d4de2 387 * @retval State of bit (1 or 0).
<> 154:37f96f9d4de2 388 */
<> 154:37f96f9d4de2 389 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void)
<> 154:37f96f9d4de2 390 {
<> 154:37f96f9d4de2 391 return (READ_BIT(PWR->CSR, PWR_CSR_SBF) == (PWR_CSR_SBF));
<> 154:37f96f9d4de2 392 }
<> 154:37f96f9d4de2 393
<> 154:37f96f9d4de2 394 /**
<> 154:37f96f9d4de2 395 * @brief Indicate whether VDD voltage is below the selected PVD threshold
<> 154:37f96f9d4de2 396 * @rmtoll CSR PVDO LL_PWR_IsActiveFlag_PVDO
<> 154:37f96f9d4de2 397 * @retval State of bit (1 or 0).
<> 154:37f96f9d4de2 398 */
<> 154:37f96f9d4de2 399 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
<> 154:37f96f9d4de2 400 {
<> 154:37f96f9d4de2 401 return (READ_BIT(PWR->CSR, PWR_CSR_PVDO) == (PWR_CSR_PVDO));
<> 154:37f96f9d4de2 402 }
<> 154:37f96f9d4de2 403
<> 154:37f96f9d4de2 404 /**
<> 154:37f96f9d4de2 405 * @brief Clear Standby Flag
<> 154:37f96f9d4de2 406 * @rmtoll CR CSBF LL_PWR_ClearFlag_SB
<> 154:37f96f9d4de2 407 * @retval None
<> 154:37f96f9d4de2 408 */
<> 154:37f96f9d4de2 409 __STATIC_INLINE void LL_PWR_ClearFlag_SB(void)
<> 154:37f96f9d4de2 410 {
<> 154:37f96f9d4de2 411 SET_BIT(PWR->CR, PWR_CR_CSBF);
<> 154:37f96f9d4de2 412 }
<> 154:37f96f9d4de2 413
<> 154:37f96f9d4de2 414 /**
<> 154:37f96f9d4de2 415 * @brief Clear Wake-up Flags
<> 154:37f96f9d4de2 416 * @rmtoll CR CWUF LL_PWR_ClearFlag_WU
<> 154:37f96f9d4de2 417 * @retval None
<> 154:37f96f9d4de2 418 */
<> 154:37f96f9d4de2 419 __STATIC_INLINE void LL_PWR_ClearFlag_WU(void)
<> 154:37f96f9d4de2 420 {
<> 154:37f96f9d4de2 421 SET_BIT(PWR->CR, PWR_CR_CWUF);
<> 154:37f96f9d4de2 422 }
<> 154:37f96f9d4de2 423 #if defined(USE_FULL_LL_DRIVER)
<> 154:37f96f9d4de2 424 /** @defgroup PWR_LL_EF_Init De-initialization function
<> 154:37f96f9d4de2 425 * @{
<> 154:37f96f9d4de2 426 */
<> 154:37f96f9d4de2 427 ErrorStatus LL_PWR_DeInit(void);
<> 154:37f96f9d4de2 428 /**
<> 154:37f96f9d4de2 429 * @}
<> 154:37f96f9d4de2 430 */
<> 154:37f96f9d4de2 431 #endif /* USE_FULL_LL_DRIVER */
<> 154:37f96f9d4de2 432
<> 154:37f96f9d4de2 433 /**
<> 154:37f96f9d4de2 434 * @}
<> 154:37f96f9d4de2 435 */
<> 154:37f96f9d4de2 436
<> 154:37f96f9d4de2 437 /**
<> 154:37f96f9d4de2 438 * @}
<> 154:37f96f9d4de2 439 */
<> 154:37f96f9d4de2 440
<> 154:37f96f9d4de2 441 /**
<> 154:37f96f9d4de2 442 * @}
<> 154:37f96f9d4de2 443 */
<> 154:37f96f9d4de2 444
<> 154:37f96f9d4de2 445 #endif /* defined(PWR) */
<> 154:37f96f9d4de2 446
<> 154:37f96f9d4de2 447 /**
<> 154:37f96f9d4de2 448 * @}
<> 154:37f96f9d4de2 449 */
<> 154:37f96f9d4de2 450
<> 154:37f96f9d4de2 451 #ifdef __cplusplus
<> 154:37f96f9d4de2 452 }
<> 154:37f96f9d4de2 453 #endif
<> 154:37f96f9d4de2 454
<> 154:37f96f9d4de2 455 #endif /* __STM32F1xx_LL_PWR_H */
<> 154:37f96f9d4de2 456
<> 154:37f96f9d4de2 457 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/