John Karatka / mbed

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targets/TARGET_ONSEMI/TARGET_NCS36510/macHw_map.h@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
Child:
150:02e0a0aed4ec
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 149:156823d33999 1 /**
<> 149:156823d33999 2 ******************************************************************************
<> 149:156823d33999 3 * @file macHw_map.h
<> 149:156823d33999 4 * @brief MACHW hw module register map
<> 149:156823d33999 5 * @internal
<> 149:156823d33999 6 * @author ON Semiconductor
<> 149:156823d33999 7 * $Rev: 3390 $
<> 149:156823d33999 8 * $Date: 2015-05-13 17:21:05 +0530 (Wed, 13 May 2015) $
<> 149:156823d33999 9 ******************************************************************************
<> 149:156823d33999 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
<> 149:156823d33999 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
<> 149:156823d33999 12 * under limited terms and conditions. The terms and conditions pertaining to the software
<> 149:156823d33999 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
<> 149:156823d33999 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
<> 149:156823d33999 15 * if applicable the software license agreement. Do not use this software and/or
<> 149:156823d33999 16 * documentation unless you have carefully read and you agree to the limited terms and
<> 149:156823d33999 17 * conditions. By using this software and/or documentation, you agree to the limited
<> 149:156823d33999 18 * terms and conditions.
<> 149:156823d33999 19 *
<> 149:156823d33999 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
<> 149:156823d33999 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
<> 149:156823d33999 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
<> 149:156823d33999 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
<> 149:156823d33999 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
<> 149:156823d33999 25 * @endinternal
<> 149:156823d33999 26 *
<> 149:156823d33999 27 * @ingroup macHw
<> 149:156823d33999 28 *
<> 149:156823d33999 29 * @details
<> 149:156823d33999 30 */
<> 149:156823d33999 31
<> 149:156823d33999 32 #ifndef MACHW_MAP_H_
<> 149:156823d33999 33 #define MACHW_MAP_H_
<> 149:156823d33999 34
<> 149:156823d33999 35 /*************************************************************************************************
<> 149:156823d33999 36 * *
<> 149:156823d33999 37 * Header files *
<> 149:156823d33999 38 * *
<> 149:156823d33999 39 *************************************************************************************************/
<> 149:156823d33999 40
<> 149:156823d33999 41 #include "architecture.h"
<> 149:156823d33999 42
<> 149:156823d33999 43 /**************************************************************************************************
<> 149:156823d33999 44 * *
<> 149:156823d33999 45 * Type definitions *
<> 149:156823d33999 46 * *
<> 149:156823d33999 47 **************************************************************************************************/
<> 149:156823d33999 48
<> 149:156823d33999 49 /** macHw register map (phy, mac and agc parts) */
<> 149:156823d33999 50 typedef struct {
<> 149:156823d33999 51 __O uint32_t SEQUENCER; /**< 0x40014000 */
<> 149:156823d33999 52 union {
<> 149:156823d33999 53 struct {
<> 149:156823d33999 54 __IO uint32_t MODE:2;
<> 149:156823d33999 55 __IO uint32_t NOACK:1;
<> 149:156823d33999 56 __IO uint32_t FT:1;
<> 149:156823d33999 57 __IO uint32_t PAD0:3;
<> 149:156823d33999 58 __IO uint32_t AUTO:1;
<> 149:156823d33999 59 __IO uint32_t PAD1:1;
<> 149:156823d33999 60 __IO uint32_t NOW:1;
<> 149:156823d33999 61 __IO uint32_t PAD2:1;
<> 149:156823d33999 62 __IO uint32_t PRM:1;
<> 149:156823d33999 63 __IO uint32_t NFCS:1;
<> 149:156823d33999 64 __IO uint32_t PAN:1;
<> 149:156823d33999 65 __IO uint32_t RSTT:1;
<> 149:156823d33999 66 __IO uint32_t RSTR:1;
<> 149:156823d33999 67 __IO uint32_t ACK_ENABLE:1;
<> 149:156823d33999 68 __IO uint32_t BEA_ENABLE:1;
<> 149:156823d33999 69 __IO uint32_t CMD_ENABLE:1;
<> 149:156823d33999 70 __IO uint32_t DATA_ENABLE:1;
<> 149:156823d33999 71 __IO uint32_t RES_ENABLE:1;
<> 149:156823d33999 72 } BITS;
<> 149:156823d33999 73 __IO uint32_t WORD;
<> 149:156823d33999 74 } SEQ_OPTIONS; /**< 0x40014004 */
<> 149:156823d33999 75 union {
<> 149:156823d33999 76 struct {
<> 149:156823d33999 77 __IO uint32_t SRST:1;
<> 149:156823d33999 78 __IO uint32_t ON:1;
<> 149:156823d33999 79 __IO uint32_t CLKDIV:1;
<> 149:156823d33999 80 } BITS;
<> 149:156823d33999 81 __IO uint32_t WORD;
<> 149:156823d33999 82 } CONTROL; /**< 0x40014008 */
<> 149:156823d33999 83 __O uint32_t PAD0; /**< 0x4001400C */
<> 149:156823d33999 84 union {
<> 149:156823d33999 85 struct {
<> 149:156823d33999 86 __I uint32_t CODE:4;
<> 149:156823d33999 87 __I uint32_t PAD0:8;
<> 149:156823d33999 88 __I uint32_t MSO:1;
<> 149:156823d33999 89 __I uint32_t CB:1;
<> 149:156823d33999 90 __I uint32_t PAD1:1;
<> 149:156823d33999 91 __I uint32_t MST:1;
<> 149:156823d33999 92 } BITS;
<> 149:156823d33999 93 __I uint32_t WORD;
<> 149:156823d33999 94 } STATUS; /**< 0x40014010 */
<> 149:156823d33999 95 union {
<> 149:156823d33999 96 struct {
<> 149:156823d33999 97 __IO uint32_t TFP:1;
<> 149:156823d33999 98 __IO uint32_t SDC:1;
<> 149:156823d33999 99 __IO uint32_t IC:1;
<> 149:156823d33999 100 __IO uint32_t SDB:1;
<> 149:156823d33999 101 __IO uint32_t SSP:1;
<> 149:156823d33999 102 __IO uint32_t TFPO:1;
<> 149:156823d33999 103 } BITS;
<> 149:156823d33999 104 __IO uint32_t WORD;
<> 149:156823d33999 105 } OPTIONS; /**< 0x40014014 */
<> 149:156823d33999 106 __IO uint32_t PANID; /**< 0x40014018 */
<> 149:156823d33999 107 __IO uint32_t SHORT_ADDRESS; /**< 0x4001401C */
<> 149:156823d33999 108 __IO uint32_t LONG_ADDRESS_HIGH; /**< 0x40014020 */
<> 149:156823d33999 109 __IO uint32_t LONG_ADDRESS_LOW; /**< 0x40014024 */
<> 149:156823d33999 110 union {
<> 149:156823d33999 111 struct {
<> 149:156823d33999 112 __IO uint32_t BIT_CLOCK_DIVIDER:8;
<> 149:156823d33999 113 __IO uint32_t SYSTEM_CLOCK_DIVIDER:8;
<> 149:156823d33999 114 __IO uint32_t CHIP_CLOCK_DIVIDER:8;
<> 149:156823d33999 115 } BITS;
<> 149:156823d33999 116 __IO uint32_t WORD;
<> 149:156823d33999 117 } DIVIDER; /**< 0x40014028 */
<> 149:156823d33999 118 union {
<> 149:156823d33999 119 struct {
<> 149:156823d33999 120 __IO uint32_t RECEIVE_WARMPUP:12;
<> 149:156823d33999 121 __IO uint32_t PAD0:4;
<> 149:156823d33999 122 __IO uint32_t TRANSMIT_WARMPUP:12;
<> 149:156823d33999 123 } BITS;
<> 149:156823d33999 124 __IO uint32_t WORD;
<> 149:156823d33999 125 } RX_TX_WARMPUPS; /**< 0x4001402c */
<> 149:156823d33999 126 union {
<> 149:156823d33999 127 struct {
<> 149:156823d33999 128 __O uint32_t EC:1;
<> 149:156823d33999 129 __O uint32_t ES:1;
<> 149:156823d33999 130 __O uint32_t DATA:1;
<> 149:156823d33999 131 __O uint32_t FS:1;
<> 149:156823d33999 132 __O uint32_t FP:1;
<> 149:156823d33999 133 __O uint32_t FMD:1;
<> 149:156823d33999 134 #ifdef REVD
<> 149:156823d33999 135 __I uint32_t PC:1;
<> 149:156823d33999 136 #endif /* REVD */
<> 149:156823d33999 137 } BITS;
<> 149:156823d33999 138 __O uint32_t WORD;
<> 149:156823d33999 139 } CLEAR_IRQ; /**< 0x40014030 */
<> 149:156823d33999 140 union {
<> 149:156823d33999 141 struct {
<> 149:156823d33999 142 __IO uint32_t EC:1;
<> 149:156823d33999 143 __IO uint32_t ES:1;
<> 149:156823d33999 144 __IO uint32_t DATA:1;
<> 149:156823d33999 145 __IO uint32_t FS:1;
<> 149:156823d33999 146 __IO uint32_t FP:1;
<> 149:156823d33999 147 __IO uint32_t FM:1;
<> 149:156823d33999 148 #ifdef REVD
<> 149:156823d33999 149 __I uint32_t PC:1;
<> 149:156823d33999 150 #endif /* REVD */
<> 149:156823d33999 151 } BITS;
<> 149:156823d33999 152 __IO uint32_t WORD;
<> 149:156823d33999 153 } MASK_IRQ; /**< 0x40014034 */
<> 149:156823d33999 154 union {
<> 149:156823d33999 155 struct {
<> 149:156823d33999 156 __I uint32_t EC:1;
<> 149:156823d33999 157 __I uint32_t ES:1;
<> 149:156823d33999 158 __I uint32_t DATA:1;
<> 149:156823d33999 159 __I uint32_t FS:1;
<> 149:156823d33999 160 __I uint32_t FP:1;
<> 149:156823d33999 161 __I uint32_t FM:1;
<> 149:156823d33999 162 #ifdef REVD
<> 149:156823d33999 163 __I uint32_t PC:1;
<> 149:156823d33999 164 #endif /* REVD */
<> 149:156823d33999 165 } BITS;
<> 149:156823d33999 166 __I uint32_t WORD;
<> 149:156823d33999 167 } IRQ_STATUS; /**< 0x40014038 */
<> 149:156823d33999 168 __O uint32_t PAD1; /**< 0x4001403C */
<> 149:156823d33999 169 union {
<> 149:156823d33999 170 struct {
<> 149:156823d33999 171 __IO uint32_t START:1;
<> 149:156823d33999 172 __IO uint32_t STOP:1;
<> 149:156823d33999 173 } BITS;
<> 149:156823d33999 174 __IO uint32_t WORD;
<> 149:156823d33999 175 } TIMER_ENABLE; /**< 0x40014040 */
<> 149:156823d33999 176 union {
<> 149:156823d33999 177 struct {
<> 149:156823d33999 178 __IO uint32_t START:1;
<> 149:156823d33999 179 __IO uint32_t STOP:1;
<> 149:156823d33999 180 } BITS;
<> 149:156823d33999 181 __IO uint32_t WORD;
<> 149:156823d33999 182 } TIMER_DISABLE; /**< 0x40014044 */
<> 149:156823d33999 183 __IO uint32_t TIMER; /**< 0x40014048 */
<> 149:156823d33999 184 __IO uint32_t START_TIME; /**< 0x4001404C */
<> 149:156823d33999 185 __IO uint32_t STOP_TIME; /**< 0x40014050 */
<> 149:156823d33999 186 union {
<> 149:156823d33999 187 struct {
<> 149:156823d33999 188 __I uint32_t START:1;
<> 149:156823d33999 189 __I uint32_t STOP:1;
<> 149:156823d33999 190 } BITS;
<> 149:156823d33999 191 __I uint32_t WORD;
<> 149:156823d33999 192 } TIMER_STATUS; /**< 0x40014054 */
<> 149:156823d33999 193 __I uint32_t PROTOCOL_TIMER; /**< 0x40014058 */
<> 149:156823d33999 194 __O uint32_t PAD4; /**< 0x4001405C */
<> 149:156823d33999 195 __I uint32_t FINISH_TIME; /**< 0x40014060 */
<> 149:156823d33999 196 union {
<> 149:156823d33999 197 struct {
<> 149:156823d33999 198 __IO uint32_t TX_SLOT_OFFSET:12;
<> 149:156823d33999 199 __IO uint32_t PAD0:4;
<> 149:156823d33999 200 __IO uint32_t RX_SLOT_OFFSET:12;
<> 149:156823d33999 201 } BITS;
<> 149:156823d33999 202 __IO uint32_t WORD;
<> 149:156823d33999 203 } SLOT_OFFSET; /**< 0x40014064 */
<> 149:156823d33999 204 __I uint32_t TIME_STAMP; /**< 0x40014068 */
<> 149:156823d33999 205 #ifdef REVB
<> 149:156823d33999 206 __O uint32_t PAD5; /**< 0x4001406C */
<> 149:156823d33999 207 #endif /* REVB */
<> 149:156823d33999 208 union {
<> 149:156823d33999 209 struct {
<> 149:156823d33999 210 __IO uint32_t CRD_SHORT_ADDRESS:16;
<> 149:156823d33999 211 __IO uint32_t PAD0:13;
<> 149:156823d33999 212 __IO uint32_t ASSOC_PAN_COORD:1;
<> 149:156823d33999 213 __IO uint32_t PAN_COORD_ADDR_L:1;
<> 149:156823d33999 214 __IO uint32_t PAN_COORD_ADDR_S:1;
<> 149:156823d33999 215 } BITS;
<> 149:156823d33999 216 __IO uint32_t WORD;
<> 149:156823d33999 217 #ifdef REVB
<> 149:156823d33999 218 } CRD_SHORT_ADDR; /**< 0x40014070 */
<> 149:156823d33999 219 __IO uint32_t CRD_LONG_ADDR_HI; /**< 0x40014074 */
<> 149:156823d33999 220 __IO uint32_t CRD_LONG_ADDR_LO; /**< 0x40014078 */
<> 149:156823d33999 221 #endif /* REVB */
<> 149:156823d33999 222 #ifdef REVD
<> 149:156823d33999 223 } CRD_SHORT_ADDR; /**< 0x4001406C */
<> 149:156823d33999 224 __IO uint32_t CRD_LONG_ADDR_HI; /**< 0x40014070 */
<> 149:156823d33999 225 __IO uint32_t CRD_LONG_ADDR_LO; /**< 0x40014074 */
<> 149:156823d33999 226 __O uint32_t PAD5; /**< 0x40014078 */
<> 149:156823d33999 227 #endif /* REVD */
<> 149:156823d33999 228 __O uint32_t PAD9; /**< 0x4001407C */
<> 149:156823d33999 229 __O uint32_t PAD10; /**< 0x40014080 */
<> 149:156823d33999 230 __O uint32_t PAD11; /**< 0x40014084 */
<> 149:156823d33999 231 __IO uint32_t RX_LENGTH; /**< 0x40014088 */
<> 149:156823d33999 232 union {
<> 149:156823d33999 233 struct {
<> 149:156823d33999 234 __IO uint32_t TXLENGTH:7;
<> 149:156823d33999 235 __O uint32_t PAD0:1;
<> 149:156823d33999 236 __IO uint32_t TX_PRE_CHIPS:4;
<> 149:156823d33999 237 } BITS;
<> 149:156823d33999 238 __IO uint32_t WORD;
<> 149:156823d33999 239 } TX_LENGTH; /**< 0x4001408C */
<> 149:156823d33999 240 __IO uint32_t TX_SEQ_NUMBER; /**< 0x40014090 */
<> 149:156823d33999 241 __IO uint32_t TX_ACK_DELAY; /**< 0x40014094 */
<> 149:156823d33999 242 union {
<> 149:156823d33999 243 struct {
<> 149:156823d33999 244 __IO uint32_t RXACKDELAY:12;
<> 149:156823d33999 245 __IO uint32_t PAD0:4;
<> 149:156823d33999 246 __IO uint32_t RXAUTODELAY:12;
<> 149:156823d33999 247 } BITS;
<> 149:156823d33999 248 __IO uint32_t WORD;
<> 149:156823d33999 249 } RX_ACK_DELAY; /**< 0x40014098 */
<> 149:156823d33999 250 __IO uint32_t TX_FLUSH; /**< 0x4001409C */
<> 149:156823d33999 251 union {
<> 149:156823d33999 252 struct {
<> 149:156823d33999 253 __IO uint32_t CCA_DELAY:12;
<> 149:156823d33999 254 __IO uint32_t PAD0:4;
<> 149:156823d33999 255 __IO uint32_t CCA_LENGTH:12;
<> 149:156823d33999 256 } BITS;
<> 149:156823d33999 257 __IO uint32_t WORD;
<> 149:156823d33999 258 } CCA; /**< 0x400140A0 */
<> 149:156823d33999 259 union {
<> 149:156823d33999 260 struct {
<> 149:156823d33999 261 __IO uint32_t RXACK_END:12;
<> 149:156823d33999 262 __IO uint32_t PAD0:4;
<> 149:156823d33999 263 __IO uint32_t RXSLOTTED_END:12;
<> 149:156823d33999 264 } BITS;
<> 149:156823d33999 265 __IO uint32_t WORD;
<> 149:156823d33999 266 } ACK_STOP; /**< 0x400140A4 */
<> 149:156823d33999 267 __IO uint32_t TXCCA; /**< 0x400140A8 */
<> 149:156823d33999 268 __IO uint32_t ADDR_L_LOC; /**< 0x400140AC */
<> 149:156823d33999 269 __IO uint32_t ADDR_S_LOC; /**< 0x400140B0 */
<> 149:156823d33999 270 __IO uint32_t FRAME_MATCH_RESULT; /**< 0x400140B4 */
<> 149:156823d33999 271 __IO uint32_t FRAME_MATCH_ADDR_L; /**< 0x400140B8 */
<> 149:156823d33999 272 __IO uint32_t FRAME_MATCH_ADDR_S; /**< 0x400140BC */
<> 149:156823d33999 273 union {
<> 149:156823d33999 274 struct {
<> 149:156823d33999 275 __IO uint32_t AA:1;
<> 149:156823d33999 276 __IO uint32_t AFA:1;
<> 149:156823d33999 277 __IO uint32_t PRE:1;
<> 149:156823d33999 278 __IO uint32_t PAD0:25;
<> 149:156823d33999 279 __IO uint32_t GAIN_START:4;
<> 149:156823d33999 280 } BITS;
<> 149:156823d33999 281 __IO uint32_t WORD;
<> 149:156823d33999 282 } AGC_CONTROL; /**< 0x400140C0 */
<> 149:156823d33999 283 union {
<> 149:156823d33999 284 struct {
<> 149:156823d33999 285 __IO uint32_t SETTLE_DELAY:8;
<> 149:156823d33999 286 __IO uint32_t MEASURE_DELAY:8;
<> 149:156823d33999 287 __IO uint32_t DIVIDER:8;
<> 149:156823d33999 288 __IO uint32_t HIGH_THRESHOLD:4;
<> 149:156823d33999 289 __IO uint32_t LOW_THRESHOLD:4;
<> 149:156823d33999 290 } BITS;
<> 149:156823d33999 291 __IO uint32_t WORD;
<> 149:156823d33999 292 } AGC_SETTINGS; /**< 0x400140C4 */
<> 149:156823d33999 293 union {
<> 149:156823d33999 294 struct {
<> 149:156823d33999 295 __IO uint32_t GC1:3;
<> 149:156823d33999 296 __IO uint32_t GC2:3;
<> 149:156823d33999 297 __IO uint32_t GC3:1;
<> 149:156823d33999 298 __IO uint32_t PAD:1;
<> 149:156823d33999 299 __IO uint32_t AGC_STATE:4;
<> 149:156823d33999 300 } BITS;
<> 149:156823d33999 301 __IO uint32_t WORD;
<> 149:156823d33999 302 } AGC_STATUS; /**< 0x400140C8 */
<> 149:156823d33999 303 union {
<> 149:156823d33999 304 struct {
<> 149:156823d33999 305 __IO uint32_t GAIN3:7;
<> 149:156823d33999 306 __IO uint32_t PAD0:1;
<> 149:156823d33999 307 __IO uint32_t GAIN2:7;
<> 149:156823d33999 308 __IO uint32_t PAD1:1;
<> 149:156823d33999 309 __IO uint32_t GAIN1:7;
<> 149:156823d33999 310 __IO uint32_t PAD2:1;
<> 149:156823d33999 311 __IO uint32_t GAIN0:7;
<> 149:156823d33999 312 __IO uint32_t PAD3:1;
<> 149:156823d33999 313 } BITS;
<> 149:156823d33999 314 __IO uint32_t WORD;
<> 149:156823d33999 315 } AGC_GAIN_TABLE0; /**< 0x400140CC */
<> 149:156823d33999 316 union {
<> 149:156823d33999 317 struct {
<> 149:156823d33999 318 __IO uint32_t GAIN7:7;
<> 149:156823d33999 319 __IO uint32_t PAD0:1;
<> 149:156823d33999 320 __IO uint32_t GAIN6:7;
<> 149:156823d33999 321 __IO uint32_t PAD1:1;
<> 149:156823d33999 322 __IO uint32_t GAIN5:7;
<> 149:156823d33999 323 __IO uint32_t PAD2:1;
<> 149:156823d33999 324 __IO uint32_t GAIN4:7;
<> 149:156823d33999 325 __IO uint32_t PAD3:1;
<> 149:156823d33999 326 } BITS;
<> 149:156823d33999 327 __IO uint32_t WORD;
<> 149:156823d33999 328 } AGC_GAIN_TABLE1; /**< 0x400140D0 */
<> 149:156823d33999 329 union {
<> 149:156823d33999 330 struct {
<> 149:156823d33999 331 __IO uint32_t GAIN11:7;
<> 149:156823d33999 332 __IO uint32_t PAD0:1;
<> 149:156823d33999 333 __IO uint32_t GAIN10:7;
<> 149:156823d33999 334 __IO uint32_t PAD1:1;
<> 149:156823d33999 335 __IO uint32_t GAIN9:7;
<> 149:156823d33999 336 __IO uint32_t PAD2:1;
<> 149:156823d33999 337 __IO uint32_t GAIN8:7;
<> 149:156823d33999 338 __IO uint32_t PAD3:1;
<> 149:156823d33999 339 } BITS;
<> 149:156823d33999 340 __IO uint32_t WORD;
<> 149:156823d33999 341 } AGC_GAIN_TABLE2; /**< 0x400140D4 */
<> 149:156823d33999 342 union {
<> 149:156823d33999 343 struct {
<> 149:156823d33999 344 __IO uint32_t GAIN15:7;
<> 149:156823d33999 345 __IO uint32_t PAD0:1;
<> 149:156823d33999 346 __IO uint32_t GAIN14:7;
<> 149:156823d33999 347 __IO uint32_t PAD1:1;
<> 149:156823d33999 348 __IO uint32_t GAIN13:7;
<> 149:156823d33999 349 __IO uint32_t PAD2:1;
<> 149:156823d33999 350 __IO uint32_t GAIN12:7;
<> 149:156823d33999 351 __IO uint32_t PAD3:1;
<> 149:156823d33999 352 } BITS;
<> 149:156823d33999 353 __IO uint32_t WORD;
<> 149:156823d33999 354 } AGC_GAIN_TABLE3; /**< 0x400140D8 */
<> 149:156823d33999 355 } MacHwReg_t, *MacHwReg_pt;
<> 149:156823d33999 356
<> 149:156823d33999 357 /** macHw register map (demodulator part) */
<> 149:156823d33999 358 typedef struct {
<> 149:156823d33999 359 union {
<> 149:156823d33999 360 struct {
<> 149:156823d33999 361 __IO uint32_t DRC:1; /**< Reserved */
<> 149:156823d33999 362 __IO uint32_t SWIQ:1; /**< Compensation for quadrature polarity. (set to 1 for RevB) */
<> 149:156823d33999 363 __IO uint32_t LIF:1; /**< Allows the receiver to use a low-IF frequency of +1.23 MHz (0) or -1.23 MHz (1). */
<> 149:156823d33999 364 __IO uint32_t PM:1; /**< Preamble Mode: Mode 0 (high sensitivity) – Preamble detection is based on observation of a regular pattern of correlation peaks over a span of 5 consecutive symbol periods. Each symbol period produces a time index and frequency index corresponding to the largest correlation peak. If 4 out of 5 symbol periods produce time/frequency index values that meet a set of similarity criteria, then preamble detection is declared. This mode improves preamble detection rate by tolerating one corrupt correlation result in the span of 5 symbols. However, the relaxed detection rule allows a higher rate of false preamble detection when no signal is present. Mode 1 (low false detection) – Preamble detection is based on a span of 4 consecutive symbol periods. Each symbol period produces a time index and frequency index corresponding to the largest correlation peak. If all four symbol periods produce time/frequency index values that meet a set of similarity criteria, then preamble detection is declared. This mode enforces a more strict detection rule and therefore offers lower rate of false preamble detection at the expense of higher missed detection. */
<> 149:156823d33999 365 __IO uint32_t ASM:1; /**< This bit determines whether antenna selection is automatic (1) or manual (0). For applications that do not use antenna diversity, this bit should be set to 0. */
<> 149:156823d33999 366 __IO uint32_t AS:1; /**< If automatic antenna selection mode is used, this bit determines the initial antenna selection. If manual antenna selection mode is used, this bit determines the antenna selection, 0 or 1. */
<> 149:156823d33999 367 __IO uint32_t DTC:1; /**< Sets the decay time constant used in the RSSI calculation and Digital Gain Control functions. 0: Time constant set to 1 symbol period. This produces a slower response time but more stable RSSI values. Not recommended for use with antenna diversity. 1: Time constant set to 1/4th of a symbol period. This produces a faster response with slightly more variance in the RSSI calculation. Recommended for most cases. */
<> 149:156823d33999 368 __IO uint32_t PAD1:9;
<> 149:156823d33999 369 __IO uint32_t DFR:16; /**<Selectively enables individual frequency offsets used during preamble search. Each of the 15 bits in this field corresponds to one of 15 different frequency offsets. A bit value of 0 removes a specific frequency offset from the search, while a bit value of 1 includes the frequency offset in the search. */
<> 149:156823d33999 370 } BITS;
<> 149:156823d33999 371 __IO uint32_t WORD;
<> 149:156823d33999 372 } DMD_CONTROL0; /**< 0x40014100 */
<> 149:156823d33999 373 union {
<> 149:156823d33999 374 struct {
<> 149:156823d33999 375 __IO uint32_t DST:4; /**< This value specifies the SFD search period in symbols. After preamble detection, the demodulator begins symbol recovery and searches for the start-of-frame delimiter (SFD). If the SFD is not found within the number of symbols specified, the preamble detection flag is cleared and a new preamble search is initiated. The default value of 8 symbols should be sufficient for 802.15.4 compliant applications. Default 8 */
<> 149:156823d33999 376 __IO uint32_t PAD0:4;
<> 149:156823d33999 377 __IO uint32_t DPT:6; /**< The similarity criteria used for preamble detection includes a rule that all time index values must occupy a span equal to or less than this value. The default span of 0011 means that the correlation peaks must span a range of 3Ts, where Ts is the sample period = 0.25 µs. This value is recommended for typical multipath conditions. Very long-range applications may benefit from a higher value. Default 3 */
<> 149:156823d33999 378 __IO uint32_t PAD1:2;
<> 149:156823d33999 379 __IO uint32_t DPF:4; /**< The similarity criteria used for preamble detection includes a rule that all frequency index values must occupy a span equal to or less than this value. The default span of 0001 means that the difference between largest frequency index and smallest frequency index must be less than or equal to 1. Default 1 */
<> 149:156823d33999 380 __IO uint32_t PAD2:4;
<> 149:156823d33999 381 __IO uint32_t DCT:4; /**< In order for preamble detection to be declared, the correlation peaks must exceed a threshold. The threshold is computed dynamically and includes a programmable scale factor: 1 + bit[27]/2 + bit[26]/4 + bit[25]/8 + bit[24]/16 The default value of 1.5 is recommended for manual-antenna selection, while a value of 1.75 is recommended for automatic antenna selection. */
<> 149:156823d33999 382
<> 149:156823d33999 383 } BITS;
<> 149:156823d33999 384 __IO uint32_t WORD;
<> 149:156823d33999 385 } DMD_CONTROL1; /**< 0x40014104 */
<> 149:156823d33999 386 union {
<> 149:156823d33999 387 struct {
<> 149:156823d33999 388 __IO uint32_t RSSI_THRESHOLD:8; /**< Threshold value used to determine clear channel assessment (CCA) result. The channel is declared busy if RSSI > threshold. Default 0xFF */
<> 149:156823d33999 389 __IO uint32_t RSSI_OFFSET:6; /**< Calibration constant added to the RSSI calculation. The 6-bit field is treated as a signed value in two’s complement format with values from -32 to +31 dB. */
<> 149:156823d33999 390 } BITS;
<> 149:156823d33999 391 __IO uint32_t WORD;
<> 149:156823d33999 392 } DMD_CONTROL2; /**< 0x40014108 */
<> 149:156823d33999 393 union {
<> 149:156823d33999 394 struct {
<> 149:156823d33999 395 __I uint32_t RSSI_VALUE:8; /**< The value is captured at the end of packet reception or at the end of ED/CCA measurements and is interpreted in dBm as follows: 00000000 -> 0127dBm (or below) ... 01111111 -> 0dBm (or above) */
<> 149:156823d33999 396 __I uint32_t FREQUENCY_OFFSET:4; /**< Frequency correction applied to the received packet. The value is captured at the end of packet reception or at the end of ED/CCA measurements. */
<> 149:156823d33999 397 __I uint32_t ANT:1; /**< Antenna used for reception. The value is captured at the end of packet reception or at the end of ED/CCA measurements. */
<> 149:156823d33999 398 __I uint32_t PAD0:3;
<> 149:156823d33999 399 __I uint32_t RSSI_COMPONENT:4; /**< Magnitude of the baseband digital signal (units are dB relative to A/D saturation). The value is updated until AGC is frozen. The value is captured at the end of packet reception or at the end of ED/CCA measurements. */
<> 149:156823d33999 400 } BITS;
<> 149:156823d33999 401 __I uint32_t WORD;
<> 149:156823d33999 402 } DMD_STATUS; /**< 0x4001410C */
<> 149:156823d33999 403 } DmdReg_t, *DmdReg_pt;
<> 149:156823d33999 404
<> 149:156823d33999 405 #endif /* MACHW_MAP_H_ */