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targets/TARGET_NUVOTON/TARGET_M451/serial_api.c@149:156823d33999, 2016-10-28 (annotated)
- Committer:
- <>
- Date:
- Fri Oct 28 11:17:30 2016 +0100
- Revision:
- 149:156823d33999
- Child:
- 151:5eaa88a5bcc7
This updates the lib to the mbed lib v128
NOTE: This release includes a restructuring of the file and directory locations and thus some
include paths in your code may need updating accordingly.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 149:156823d33999 | 1 | /* mbed Microcontroller Library |
<> | 149:156823d33999 | 2 | * Copyright (c) 2015-2016 Nuvoton |
<> | 149:156823d33999 | 3 | * |
<> | 149:156823d33999 | 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
<> | 149:156823d33999 | 5 | * you may not use this file except in compliance with the License. |
<> | 149:156823d33999 | 6 | * You may obtain a copy of the License at |
<> | 149:156823d33999 | 7 | * |
<> | 149:156823d33999 | 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
<> | 149:156823d33999 | 9 | * |
<> | 149:156823d33999 | 10 | * Unless required by applicable law or agreed to in writing, software |
<> | 149:156823d33999 | 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
<> | 149:156823d33999 | 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
<> | 149:156823d33999 | 13 | * See the License for the specific language governing permissions and |
<> | 149:156823d33999 | 14 | * limitations under the License. |
<> | 149:156823d33999 | 15 | */ |
<> | 149:156823d33999 | 16 | |
<> | 149:156823d33999 | 17 | #include "serial_api.h" |
<> | 149:156823d33999 | 18 | |
<> | 149:156823d33999 | 19 | #if DEVICE_SERIAL |
<> | 149:156823d33999 | 20 | |
<> | 149:156823d33999 | 21 | #include "cmsis.h" |
<> | 149:156823d33999 | 22 | #include "mbed_error.h" |
<> | 149:156823d33999 | 23 | #include "mbed_assert.h" |
<> | 149:156823d33999 | 24 | #include "PeripheralPins.h" |
<> | 149:156823d33999 | 25 | #include "nu_modutil.h" |
<> | 149:156823d33999 | 26 | #include "nu_bitutil.h" |
<> | 149:156823d33999 | 27 | |
<> | 149:156823d33999 | 28 | #if DEVICE_SERIAL_ASYNCH |
<> | 149:156823d33999 | 29 | #include "dma_api.h" |
<> | 149:156823d33999 | 30 | #include "dma.h" |
<> | 149:156823d33999 | 31 | #endif |
<> | 149:156823d33999 | 32 | |
<> | 149:156823d33999 | 33 | struct nu_uart_var { |
<> | 149:156823d33999 | 34 | serial_t * obj; |
<> | 149:156823d33999 | 35 | uint32_t fifo_size_tx; |
<> | 149:156823d33999 | 36 | uint32_t fifo_size_rx; |
<> | 149:156823d33999 | 37 | void (*vec)(void); |
<> | 149:156823d33999 | 38 | #if DEVICE_SERIAL_ASYNCH |
<> | 149:156823d33999 | 39 | void (*vec_async)(void); |
<> | 149:156823d33999 | 40 | uint8_t pdma_perp_tx; |
<> | 149:156823d33999 | 41 | uint8_t pdma_perp_rx; |
<> | 149:156823d33999 | 42 | #endif |
<> | 149:156823d33999 | 43 | }; |
<> | 149:156823d33999 | 44 | |
<> | 149:156823d33999 | 45 | static void uart0_vec(void); |
<> | 149:156823d33999 | 46 | static void uart1_vec(void); |
<> | 149:156823d33999 | 47 | static void uart2_vec(void); |
<> | 149:156823d33999 | 48 | static void uart3_vec(void); |
<> | 149:156823d33999 | 49 | static void uart_irq(serial_t *obj); |
<> | 149:156823d33999 | 50 | |
<> | 149:156823d33999 | 51 | #if DEVICE_SERIAL_ASYNCH |
<> | 149:156823d33999 | 52 | static void uart0_vec_async(void); |
<> | 149:156823d33999 | 53 | static void uart1_vec_async(void); |
<> | 149:156823d33999 | 54 | static void uart2_vec_async(void); |
<> | 149:156823d33999 | 55 | static void uart3_vec_async(void); |
<> | 149:156823d33999 | 56 | static void uart_irq_async(serial_t *obj); |
<> | 149:156823d33999 | 57 | |
<> | 149:156823d33999 | 58 | static void uart_dma_handler_tx(uint32_t id, uint32_t event); |
<> | 149:156823d33999 | 59 | static void uart_dma_handler_rx(uint32_t id, uint32_t event); |
<> | 149:156823d33999 | 60 | |
<> | 149:156823d33999 | 61 | static void serial_tx_enable_interrupt(serial_t *obj, uint32_t address, uint8_t enable); |
<> | 149:156823d33999 | 62 | static void serial_rx_enable_interrupt(serial_t *obj, uint32_t address, uint8_t enable); |
<> | 149:156823d33999 | 63 | static int serial_write_async(serial_t *obj); |
<> | 149:156823d33999 | 64 | static int serial_read_async(serial_t *obj); |
<> | 149:156823d33999 | 65 | |
<> | 149:156823d33999 | 66 | static uint32_t serial_rx_event_check(serial_t *obj); |
<> | 149:156823d33999 | 67 | static uint32_t serial_tx_event_check(serial_t *obj); |
<> | 149:156823d33999 | 68 | |
<> | 149:156823d33999 | 69 | static int serial_is_tx_complete(serial_t *obj); |
<> | 149:156823d33999 | 70 | static void serial_tx_enable_event(serial_t *obj, int event, uint8_t enable); |
<> | 149:156823d33999 | 71 | |
<> | 149:156823d33999 | 72 | static void serial_tx_buffer_set(serial_t *obj, const void *tx, size_t length, uint8_t width); |
<> | 149:156823d33999 | 73 | static void serial_rx_buffer_set(serial_t *obj, void *rx, size_t length, uint8_t width); |
<> | 149:156823d33999 | 74 | static void serial_rx_set_char_match(serial_t *obj, uint8_t char_match); |
<> | 149:156823d33999 | 75 | static void serial_rx_enable_event(serial_t *obj, int event, uint8_t enable); |
<> | 149:156823d33999 | 76 | static int serial_is_rx_complete(serial_t *obj); |
<> | 149:156823d33999 | 77 | |
<> | 149:156823d33999 | 78 | static void serial_check_dma_usage(DMAUsage *dma_usage, int *dma_ch); |
<> | 149:156823d33999 | 79 | static int serial_is_irq_en(serial_t *obj, SerialIrq irq); |
<> | 149:156823d33999 | 80 | #endif |
<> | 149:156823d33999 | 81 | |
<> | 149:156823d33999 | 82 | static struct nu_uart_var uart0_var = { |
<> | 149:156823d33999 | 83 | .obj = NULL, |
<> | 149:156823d33999 | 84 | .fifo_size_tx = 16, |
<> | 149:156823d33999 | 85 | .fifo_size_rx = 16, |
<> | 149:156823d33999 | 86 | .vec = uart0_vec, |
<> | 149:156823d33999 | 87 | #if DEVICE_SERIAL_ASYNCH |
<> | 149:156823d33999 | 88 | .vec_async = uart0_vec_async, |
<> | 149:156823d33999 | 89 | .pdma_perp_tx = PDMA_UART0_TX, |
<> | 149:156823d33999 | 90 | .pdma_perp_rx = PDMA_UART0_RX |
<> | 149:156823d33999 | 91 | #endif |
<> | 149:156823d33999 | 92 | }; |
<> | 149:156823d33999 | 93 | static struct nu_uart_var uart1_var = { |
<> | 149:156823d33999 | 94 | .obj = NULL, |
<> | 149:156823d33999 | 95 | .fifo_size_tx = 16, |
<> | 149:156823d33999 | 96 | .fifo_size_rx = 16, |
<> | 149:156823d33999 | 97 | .vec = uart1_vec, |
<> | 149:156823d33999 | 98 | #if DEVICE_SERIAL_ASYNCH |
<> | 149:156823d33999 | 99 | .vec_async = uart1_vec_async, |
<> | 149:156823d33999 | 100 | .pdma_perp_tx = PDMA_UART1_TX, |
<> | 149:156823d33999 | 101 | .pdma_perp_rx = PDMA_UART1_RX |
<> | 149:156823d33999 | 102 | #endif |
<> | 149:156823d33999 | 103 | }; |
<> | 149:156823d33999 | 104 | static struct nu_uart_var uart2_var = { |
<> | 149:156823d33999 | 105 | .obj = NULL, |
<> | 149:156823d33999 | 106 | .fifo_size_tx = 16, |
<> | 149:156823d33999 | 107 | .fifo_size_rx = 16, |
<> | 149:156823d33999 | 108 | .vec = uart2_vec, |
<> | 149:156823d33999 | 109 | #if DEVICE_SERIAL_ASYNCH |
<> | 149:156823d33999 | 110 | .vec_async = uart2_vec_async, |
<> | 149:156823d33999 | 111 | .pdma_perp_tx = PDMA_UART2_TX, |
<> | 149:156823d33999 | 112 | .pdma_perp_rx = PDMA_UART2_RX |
<> | 149:156823d33999 | 113 | #endif |
<> | 149:156823d33999 | 114 | }; |
<> | 149:156823d33999 | 115 | static struct nu_uart_var uart3_var = { |
<> | 149:156823d33999 | 116 | .obj = NULL, |
<> | 149:156823d33999 | 117 | .fifo_size_tx = 16, |
<> | 149:156823d33999 | 118 | .fifo_size_rx = 16, |
<> | 149:156823d33999 | 119 | .vec = uart3_vec, |
<> | 149:156823d33999 | 120 | #if DEVICE_SERIAL_ASYNCH |
<> | 149:156823d33999 | 121 | .vec_async = uart3_vec_async, |
<> | 149:156823d33999 | 122 | .pdma_perp_tx = PDMA_UART3_TX, |
<> | 149:156823d33999 | 123 | .pdma_perp_rx = PDMA_UART3_RX |
<> | 149:156823d33999 | 124 | #endif |
<> | 149:156823d33999 | 125 | }; |
<> | 149:156823d33999 | 126 | |
<> | 149:156823d33999 | 127 | |
<> | 149:156823d33999 | 128 | int stdio_uart_inited = 0; |
<> | 149:156823d33999 | 129 | serial_t stdio_uart; |
<> | 149:156823d33999 | 130 | static uint32_t uart_modinit_mask = 0; |
<> | 149:156823d33999 | 131 | |
<> | 149:156823d33999 | 132 | static const struct nu_modinit_s uart_modinit_tab[] = { |
<> | 149:156823d33999 | 133 | {UART_0, UART0_MODULE, CLK_CLKSEL1_UARTSEL_HIRC, CLK_CLKDIV0_UART(1), UART0_RST, UART0_IRQn, &uart0_var}, |
<> | 149:156823d33999 | 134 | {UART_1, UART1_MODULE, CLK_CLKSEL1_UARTSEL_HIRC, CLK_CLKDIV0_UART(1), UART1_RST, UART1_IRQn, &uart1_var}, |
<> | 149:156823d33999 | 135 | {UART_2, UART2_MODULE, CLK_CLKSEL1_UARTSEL_HIRC, CLK_CLKDIV0_UART(1), UART2_RST, UART2_IRQn, &uart2_var}, |
<> | 149:156823d33999 | 136 | {UART_3, UART3_MODULE, CLK_CLKSEL1_UARTSEL_HIRC, CLK_CLKDIV0_UART(1), UART3_RST, UART3_IRQn, &uart3_var}, |
<> | 149:156823d33999 | 137 | |
<> | 149:156823d33999 | 138 | {NC, 0, 0, 0, 0, (IRQn_Type) 0, NULL} |
<> | 149:156823d33999 | 139 | }; |
<> | 149:156823d33999 | 140 | |
<> | 149:156823d33999 | 141 | extern void mbed_sdk_init(void); |
<> | 149:156823d33999 | 142 | |
<> | 149:156823d33999 | 143 | void serial_init(serial_t *obj, PinName tx, PinName rx) |
<> | 149:156823d33999 | 144 | { |
<> | 149:156823d33999 | 145 | // NOTE: serial_init() gets called from _sys_open() timing of which is before main()/mbed_hal_init(). |
<> | 149:156823d33999 | 146 | mbed_sdk_init(); |
<> | 149:156823d33999 | 147 | |
<> | 149:156823d33999 | 148 | // Determine which UART_x the pins are used for |
<> | 149:156823d33999 | 149 | uint32_t uart_tx = pinmap_peripheral(tx, PinMap_UART_TX); |
<> | 149:156823d33999 | 150 | uint32_t uart_rx = pinmap_peripheral(rx, PinMap_UART_RX); |
<> | 149:156823d33999 | 151 | // Get the peripheral name (UART_x) from the pins and assign it to the object |
<> | 149:156823d33999 | 152 | obj->serial.uart = (UARTName) pinmap_merge(uart_tx, uart_rx); |
<> | 149:156823d33999 | 153 | MBED_ASSERT((int)obj->serial.uart != NC); |
<> | 149:156823d33999 | 154 | |
<> | 149:156823d33999 | 155 | const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab); |
<> | 149:156823d33999 | 156 | MBED_ASSERT(modinit != NULL); |
<> | 149:156823d33999 | 157 | MBED_ASSERT(modinit->modname == obj->serial.uart); |
<> | 149:156823d33999 | 158 | |
<> | 149:156823d33999 | 159 | // Reset this module |
<> | 149:156823d33999 | 160 | SYS_ResetModule(modinit->rsetidx); |
<> | 149:156823d33999 | 161 | |
<> | 149:156823d33999 | 162 | // Select IP clock source |
<> | 149:156823d33999 | 163 | CLK_SetModuleClock(modinit->clkidx, modinit->clksrc, modinit->clkdiv); |
<> | 149:156823d33999 | 164 | // Enable IP clock |
<> | 149:156823d33999 | 165 | CLK_EnableModuleClock(modinit->clkidx); |
<> | 149:156823d33999 | 166 | |
<> | 149:156823d33999 | 167 | pinmap_pinout(tx, PinMap_UART_TX); |
<> | 149:156823d33999 | 168 | pinmap_pinout(rx, PinMap_UART_RX); |
<> | 149:156823d33999 | 169 | // FIXME: Why PullUp? |
<> | 149:156823d33999 | 170 | //if (tx != NC) { |
<> | 149:156823d33999 | 171 | // pin_mode(tx, PullUp); |
<> | 149:156823d33999 | 172 | //} |
<> | 149:156823d33999 | 173 | //if (rx != NC) { |
<> | 149:156823d33999 | 174 | // pin_mode(rx, PullUp); |
<> | 149:156823d33999 | 175 | //} |
<> | 149:156823d33999 | 176 | obj->serial.pin_tx = tx; |
<> | 149:156823d33999 | 177 | obj->serial.pin_rx = rx; |
<> | 149:156823d33999 | 178 | |
<> | 149:156823d33999 | 179 | // Configure the UART module and set its baudrate |
<> | 149:156823d33999 | 180 | serial_baud(obj, 9600); |
<> | 149:156823d33999 | 181 | // Configure data bits, parity, and stop bits |
<> | 149:156823d33999 | 182 | serial_format(obj, 8, ParityNone, 1); |
<> | 149:156823d33999 | 183 | |
<> | 149:156823d33999 | 184 | obj->serial.vec = ((struct nu_uart_var *) modinit->var)->vec; |
<> | 149:156823d33999 | 185 | |
<> | 149:156823d33999 | 186 | #if DEVICE_SERIAL_ASYNCH |
<> | 149:156823d33999 | 187 | obj->serial.dma_usage_tx = DMA_USAGE_NEVER; |
<> | 149:156823d33999 | 188 | obj->serial.dma_usage_rx = DMA_USAGE_NEVER; |
<> | 149:156823d33999 | 189 | obj->serial.event = 0; |
<> | 149:156823d33999 | 190 | obj->serial.dma_chn_id_tx = DMA_ERROR_OUT_OF_CHANNELS; |
<> | 149:156823d33999 | 191 | obj->serial.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS; |
<> | 149:156823d33999 | 192 | #endif |
<> | 149:156823d33999 | 193 | |
<> | 149:156823d33999 | 194 | // For stdio management |
<> | 149:156823d33999 | 195 | if (obj == &stdio_uart) { |
<> | 149:156823d33999 | 196 | stdio_uart_inited = 1; |
<> | 149:156823d33999 | 197 | /* NOTE: Not required anymore because stdio_uart will be manually initialized in mbed-drivers/source/retarget.cpp from mbed beta */ |
<> | 149:156823d33999 | 198 | //memcpy(&stdio_uart, obj, sizeof(serial_t)); |
<> | 149:156823d33999 | 199 | } |
<> | 149:156823d33999 | 200 | |
<> | 149:156823d33999 | 201 | // Mark this module to be inited. |
<> | 149:156823d33999 | 202 | int i = modinit - uart_modinit_tab; |
<> | 149:156823d33999 | 203 | uart_modinit_mask |= 1 << i; |
<> | 149:156823d33999 | 204 | } |
<> | 149:156823d33999 | 205 | |
<> | 149:156823d33999 | 206 | void serial_free(serial_t *obj) |
<> | 149:156823d33999 | 207 | { |
<> | 149:156823d33999 | 208 | #if DEVICE_SERIAL_ASYNCH |
<> | 149:156823d33999 | 209 | if (obj->serial.dma_chn_id_tx != DMA_ERROR_OUT_OF_CHANNELS) { |
<> | 149:156823d33999 | 210 | dma_channel_free(obj->serial.dma_chn_id_tx); |
<> | 149:156823d33999 | 211 | obj->serial.dma_chn_id_tx = DMA_ERROR_OUT_OF_CHANNELS; |
<> | 149:156823d33999 | 212 | } |
<> | 149:156823d33999 | 213 | if (obj->serial.dma_chn_id_rx != DMA_ERROR_OUT_OF_CHANNELS) { |
<> | 149:156823d33999 | 214 | dma_channel_free(obj->serial.dma_chn_id_rx); |
<> | 149:156823d33999 | 215 | obj->serial.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS; |
<> | 149:156823d33999 | 216 | } |
<> | 149:156823d33999 | 217 | #endif |
<> | 149:156823d33999 | 218 | |
<> | 149:156823d33999 | 219 | UART_Close((UART_T *) NU_MODBASE(obj->serial.uart)); |
<> | 149:156823d33999 | 220 | |
<> | 149:156823d33999 | 221 | const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab); |
<> | 149:156823d33999 | 222 | MBED_ASSERT(modinit != NULL); |
<> | 149:156823d33999 | 223 | MBED_ASSERT(modinit->modname == obj->serial.uart); |
<> | 149:156823d33999 | 224 | |
<> | 149:156823d33999 | 225 | UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_THREIEN_Msk | UART_INTEN_RXTOIEN_Msk)); |
<> | 149:156823d33999 | 226 | NVIC_DisableIRQ(modinit->irq_n); |
<> | 149:156823d33999 | 227 | |
<> | 149:156823d33999 | 228 | // Disable IP clock |
<> | 149:156823d33999 | 229 | CLK_DisableModuleClock(modinit->clkidx); |
<> | 149:156823d33999 | 230 | |
<> | 149:156823d33999 | 231 | ((struct nu_uart_var *) modinit->var)->obj = NULL; |
<> | 149:156823d33999 | 232 | |
<> | 149:156823d33999 | 233 | if (obj == &stdio_uart) { |
<> | 149:156823d33999 | 234 | stdio_uart_inited = 0; |
<> | 149:156823d33999 | 235 | } |
<> | 149:156823d33999 | 236 | |
<> | 149:156823d33999 | 237 | // Mark this module to be deinited. |
<> | 149:156823d33999 | 238 | int i = modinit - uart_modinit_tab; |
<> | 149:156823d33999 | 239 | uart_modinit_mask &= ~(1 << i); |
<> | 149:156823d33999 | 240 | } |
<> | 149:156823d33999 | 241 | |
<> | 149:156823d33999 | 242 | void serial_baud(serial_t *obj, int baudrate) { |
<> | 149:156823d33999 | 243 | // Flush Tx FIFO. Otherwise, output data may get lost on this change. |
<> | 149:156823d33999 | 244 | while (! UART_IS_TX_EMPTY(((UART_T *) obj->serial.uart))); |
<> | 149:156823d33999 | 245 | |
<> | 149:156823d33999 | 246 | obj->serial.baudrate = baudrate; |
<> | 149:156823d33999 | 247 | UART_Open((UART_T *) NU_MODBASE(obj->serial.uart), baudrate); |
<> | 149:156823d33999 | 248 | } |
<> | 149:156823d33999 | 249 | |
<> | 149:156823d33999 | 250 | void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) { |
<> | 149:156823d33999 | 251 | // Flush Tx FIFO. Otherwise, output data may get lost on this change. |
<> | 149:156823d33999 | 252 | while (! UART_IS_TX_EMPTY(((UART_T *) obj->serial.uart))); |
<> | 149:156823d33999 | 253 | |
<> | 149:156823d33999 | 254 | // TODO: Assert for not supported parity and data bits |
<> | 149:156823d33999 | 255 | obj->serial.databits = data_bits; |
<> | 149:156823d33999 | 256 | obj->serial.parity = parity; |
<> | 149:156823d33999 | 257 | obj->serial.stopbits = stop_bits; |
<> | 149:156823d33999 | 258 | |
<> | 149:156823d33999 | 259 | uint32_t databits_intern = (data_bits == 5) ? UART_WORD_LEN_5 : |
<> | 149:156823d33999 | 260 | (data_bits == 6) ? UART_WORD_LEN_6 : |
<> | 149:156823d33999 | 261 | (data_bits == 7) ? UART_WORD_LEN_7 : |
<> | 149:156823d33999 | 262 | UART_WORD_LEN_8; |
<> | 149:156823d33999 | 263 | uint32_t parity_intern = (parity == ParityOdd || parity == ParityForced1) ? UART_PARITY_ODD : |
<> | 149:156823d33999 | 264 | (parity == ParityEven || parity == ParityForced0) ? UART_PARITY_EVEN : |
<> | 149:156823d33999 | 265 | UART_PARITY_NONE; |
<> | 149:156823d33999 | 266 | uint32_t stopbits_intern = (stop_bits == 2) ? UART_STOP_BIT_2 : UART_STOP_BIT_1; |
<> | 149:156823d33999 | 267 | UART_SetLine_Config((UART_T *) NU_MODBASE(obj->serial.uart), |
<> | 149:156823d33999 | 268 | 0, // Don't change baudrate |
<> | 149:156823d33999 | 269 | databits_intern, |
<> | 149:156823d33999 | 270 | parity_intern, |
<> | 149:156823d33999 | 271 | stopbits_intern); |
<> | 149:156823d33999 | 272 | } |
<> | 149:156823d33999 | 273 | |
<> | 149:156823d33999 | 274 | #if DEVICE_SERIAL_FC |
<> | 149:156823d33999 | 275 | |
<> | 149:156823d33999 | 276 | void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) |
<> | 149:156823d33999 | 277 | { |
<> | 149:156823d33999 | 278 | UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart); |
<> | 149:156823d33999 | 279 | |
<> | 149:156823d33999 | 280 | // First, disable flow control completely. |
<> | 149:156823d33999 | 281 | uart_base->INTEN &= ~(UART_INTEN_ATORTSEN_Msk | UART_INTEN_ATOCTSEN_Msk); |
<> | 149:156823d33999 | 282 | |
<> | 149:156823d33999 | 283 | if ((type == FlowControlRTS || type == FlowControlRTSCTS) && rxflow != NC) { |
<> | 149:156823d33999 | 284 | // Check if RTS pin matches. |
<> | 149:156823d33999 | 285 | uint32_t uart_rts = pinmap_peripheral(rxflow, PinMap_UART_RTS); |
<> | 149:156823d33999 | 286 | MBED_ASSERT(uart_rts == obj->serial.uart); |
<> | 149:156823d33999 | 287 | // Enable the pin for RTS function |
<> | 149:156823d33999 | 288 | pinmap_pinout(rxflow, PinMap_UART_RTS); |
<> | 149:156823d33999 | 289 | // nRTS pin output is high level active |
<> | 149:156823d33999 | 290 | uart_base->MODEM = (uart_base->MODEM & ~UART_MODEM_RTSACTLV_Msk); |
<> | 149:156823d33999 | 291 | uart_base->FIFO = (uart_base->FIFO & ~UART_FIFO_RTSTRGLV_Msk) | UART_FIFO_RTSTRGLV_8BYTES; |
<> | 149:156823d33999 | 292 | // Enable RTS |
<> | 149:156823d33999 | 293 | uart_base->INTEN |= UART_INTEN_ATORTSEN_Msk; |
<> | 149:156823d33999 | 294 | } |
<> | 149:156823d33999 | 295 | |
<> | 149:156823d33999 | 296 | if ((type == FlowControlCTS || type == FlowControlRTSCTS) && txflow != NC) { |
<> | 149:156823d33999 | 297 | // Check if CTS pin matches. |
<> | 149:156823d33999 | 298 | uint32_t uart_cts = pinmap_peripheral(txflow, PinMap_UART_CTS); |
<> | 149:156823d33999 | 299 | MBED_ASSERT(uart_cts == obj->serial.uart); |
<> | 149:156823d33999 | 300 | // Enable the pin for CTS function |
<> | 149:156823d33999 | 301 | pinmap_pinout(txflow, PinMap_UART_CTS); |
<> | 149:156823d33999 | 302 | // nCTS pin input is high level active |
<> | 149:156823d33999 | 303 | uart_base->MODEMSTS = (uart_base->MODEMSTS & ~UART_MODEMSTS_CTSACTLV_Msk); |
<> | 149:156823d33999 | 304 | // Enable CTS |
<> | 149:156823d33999 | 305 | uart_base->INTEN |= UART_INTEN_ATOCTSEN_Msk; |
<> | 149:156823d33999 | 306 | } |
<> | 149:156823d33999 | 307 | } |
<> | 149:156823d33999 | 308 | |
<> | 149:156823d33999 | 309 | #endif //DEVICE_SERIAL_FC |
<> | 149:156823d33999 | 310 | |
<> | 149:156823d33999 | 311 | void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) |
<> | 149:156823d33999 | 312 | { |
<> | 149:156823d33999 | 313 | // Flush Tx FIFO. Otherwise, output data may get lost on this change. |
<> | 149:156823d33999 | 314 | while (! UART_IS_TX_EMPTY(((UART_T *) obj->serial.uart))); |
<> | 149:156823d33999 | 315 | |
<> | 149:156823d33999 | 316 | const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab); |
<> | 149:156823d33999 | 317 | MBED_ASSERT(modinit != NULL); |
<> | 149:156823d33999 | 318 | MBED_ASSERT(modinit->modname == obj->serial.uart); |
<> | 149:156823d33999 | 319 | |
<> | 149:156823d33999 | 320 | ((struct nu_uart_var *) modinit->var)->obj = obj; |
<> | 149:156823d33999 | 321 | obj->serial.irq_handler = (uint32_t) handler; |
<> | 149:156823d33999 | 322 | obj->serial.irq_id = id; |
<> | 149:156823d33999 | 323 | |
<> | 149:156823d33999 | 324 | // Restore sync-mode vector |
<> | 149:156823d33999 | 325 | obj->serial.vec = ((struct nu_uart_var *) modinit->var)->vec; |
<> | 149:156823d33999 | 326 | } |
<> | 149:156823d33999 | 327 | |
<> | 149:156823d33999 | 328 | void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) |
<> | 149:156823d33999 | 329 | { |
<> | 149:156823d33999 | 330 | if (enable) { |
<> | 149:156823d33999 | 331 | const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab); |
<> | 149:156823d33999 | 332 | MBED_ASSERT(modinit != NULL); |
<> | 149:156823d33999 | 333 | MBED_ASSERT(modinit->modname == obj->serial.uart); |
<> | 149:156823d33999 | 334 | |
<> | 149:156823d33999 | 335 | NVIC_SetVector(modinit->irq_n, (uint32_t) obj->serial.vec); |
<> | 149:156823d33999 | 336 | NVIC_EnableIRQ(modinit->irq_n); |
<> | 149:156823d33999 | 337 | |
<> | 149:156823d33999 | 338 | switch (irq) { |
<> | 149:156823d33999 | 339 | // NOTE: Setting inten_msk first to avoid race condition |
<> | 149:156823d33999 | 340 | case RxIrq: |
<> | 149:156823d33999 | 341 | obj->serial.inten_msk = obj->serial.inten_msk | (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk); |
<> | 149:156823d33999 | 342 | UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)); |
<> | 149:156823d33999 | 343 | break; |
<> | 149:156823d33999 | 344 | case TxIrq: |
<> | 149:156823d33999 | 345 | obj->serial.inten_msk = obj->serial.inten_msk | UART_INTEN_THREIEN_Msk; |
<> | 149:156823d33999 | 346 | UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk); |
<> | 149:156823d33999 | 347 | break; |
<> | 149:156823d33999 | 348 | } |
<> | 149:156823d33999 | 349 | } else { // disable |
<> | 149:156823d33999 | 350 | switch (irq) { |
<> | 149:156823d33999 | 351 | case RxIrq: |
<> | 149:156823d33999 | 352 | UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)); |
<> | 149:156823d33999 | 353 | obj->serial.inten_msk = obj->serial.inten_msk & ~(UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk); |
<> | 149:156823d33999 | 354 | break; |
<> | 149:156823d33999 | 355 | case TxIrq: |
<> | 149:156823d33999 | 356 | UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk); |
<> | 149:156823d33999 | 357 | obj->serial.inten_msk = obj->serial.inten_msk & ~UART_INTEN_THREIEN_Msk; |
<> | 149:156823d33999 | 358 | break; |
<> | 149:156823d33999 | 359 | } |
<> | 149:156823d33999 | 360 | } |
<> | 149:156823d33999 | 361 | } |
<> | 149:156823d33999 | 362 | |
<> | 149:156823d33999 | 363 | int serial_getc(serial_t *obj) |
<> | 149:156823d33999 | 364 | { |
<> | 149:156823d33999 | 365 | // TODO: Fix every byte access requires accompaniness of one interrupt. This degrades performance much. |
<> | 149:156823d33999 | 366 | while (! serial_readable(obj)); |
<> | 149:156823d33999 | 367 | int c = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart))); |
<> | 149:156823d33999 | 368 | |
<> | 149:156823d33999 | 369 | // Simulate clear of the interrupt flag |
<> | 149:156823d33999 | 370 | if (obj->serial.inten_msk & (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)) { |
<> | 149:156823d33999 | 371 | UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)); |
<> | 149:156823d33999 | 372 | } |
<> | 149:156823d33999 | 373 | |
<> | 149:156823d33999 | 374 | return c; |
<> | 149:156823d33999 | 375 | } |
<> | 149:156823d33999 | 376 | |
<> | 149:156823d33999 | 377 | void serial_putc(serial_t *obj, int c) |
<> | 149:156823d33999 | 378 | { |
<> | 149:156823d33999 | 379 | // TODO: Fix every byte access requires accompaniness of one interrupt. This degrades performance much. |
<> | 149:156823d33999 | 380 | while (! serial_writable(obj)); |
<> | 149:156823d33999 | 381 | UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), c); |
<> | 149:156823d33999 | 382 | |
<> | 149:156823d33999 | 383 | // Simulate clear of the interrupt flag |
<> | 149:156823d33999 | 384 | if (obj->serial.inten_msk & UART_INTEN_THREIEN_Msk) { |
<> | 149:156823d33999 | 385 | UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk); |
<> | 149:156823d33999 | 386 | } |
<> | 149:156823d33999 | 387 | } |
<> | 149:156823d33999 | 388 | |
<> | 149:156823d33999 | 389 | int serial_readable(serial_t *obj) |
<> | 149:156823d33999 | 390 | { |
<> | 149:156823d33999 | 391 | //return UART_IS_RX_READY(((UART_T *) NU_MODBASE(obj->serial.uart))); |
<> | 149:156823d33999 | 392 | return ! UART_GET_RX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart))); |
<> | 149:156823d33999 | 393 | } |
<> | 149:156823d33999 | 394 | |
<> | 149:156823d33999 | 395 | int serial_writable(serial_t *obj) |
<> | 149:156823d33999 | 396 | { |
<> | 149:156823d33999 | 397 | return ! UART_IS_TX_FULL(((UART_T *) NU_MODBASE(obj->serial.uart))); |
<> | 149:156823d33999 | 398 | } |
<> | 149:156823d33999 | 399 | |
<> | 149:156823d33999 | 400 | void serial_pinout_tx(PinName tx) |
<> | 149:156823d33999 | 401 | { |
<> | 149:156823d33999 | 402 | pinmap_pinout(tx, PinMap_UART_TX); |
<> | 149:156823d33999 | 403 | } |
<> | 149:156823d33999 | 404 | |
<> | 149:156823d33999 | 405 | void serial_break_set(serial_t *obj) |
<> | 149:156823d33999 | 406 | { |
<> | 149:156823d33999 | 407 | ((UART_T *) NU_MODBASE(obj->serial.uart))->LINE |= UART_LINE_BCB_Msk; |
<> | 149:156823d33999 | 408 | } |
<> | 149:156823d33999 | 409 | |
<> | 149:156823d33999 | 410 | void serial_break_clear(serial_t *obj) |
<> | 149:156823d33999 | 411 | { |
<> | 149:156823d33999 | 412 | ((UART_T *) NU_MODBASE(obj->serial.uart))->LINE &= ~UART_LINE_BCB_Msk; |
<> | 149:156823d33999 | 413 | } |
<> | 149:156823d33999 | 414 | |
<> | 149:156823d33999 | 415 | static void uart0_vec(void) |
<> | 149:156823d33999 | 416 | { |
<> | 149:156823d33999 | 417 | uart_irq(uart0_var.obj); |
<> | 149:156823d33999 | 418 | } |
<> | 149:156823d33999 | 419 | |
<> | 149:156823d33999 | 420 | static void uart1_vec(void) |
<> | 149:156823d33999 | 421 | { |
<> | 149:156823d33999 | 422 | uart_irq(uart1_var.obj); |
<> | 149:156823d33999 | 423 | } |
<> | 149:156823d33999 | 424 | |
<> | 149:156823d33999 | 425 | static void uart2_vec(void) |
<> | 149:156823d33999 | 426 | { |
<> | 149:156823d33999 | 427 | uart_irq(uart2_var.obj); |
<> | 149:156823d33999 | 428 | } |
<> | 149:156823d33999 | 429 | |
<> | 149:156823d33999 | 430 | static void uart3_vec(void) |
<> | 149:156823d33999 | 431 | { |
<> | 149:156823d33999 | 432 | uart_irq(uart3_var.obj); |
<> | 149:156823d33999 | 433 | } |
<> | 149:156823d33999 | 434 | |
<> | 149:156823d33999 | 435 | static void uart_irq(serial_t *obj) |
<> | 149:156823d33999 | 436 | { |
<> | 149:156823d33999 | 437 | UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart); |
<> | 149:156823d33999 | 438 | |
<> | 149:156823d33999 | 439 | if (uart_base->INTSTS & (UART_INTSTS_RDAINT_Msk | UART_INTSTS_RXTOINT_Msk)) { |
<> | 149:156823d33999 | 440 | // Simulate clear of the interrupt flag. Temporarily disable the interrupt here and to be recovered on next read. |
<> | 149:156823d33999 | 441 | UART_DISABLE_INT(uart_base, (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)); |
<> | 149:156823d33999 | 442 | if (obj->serial.irq_handler) { |
<> | 149:156823d33999 | 443 | ((uart_irq_handler) obj->serial.irq_handler)(obj->serial.irq_id, RxIrq); |
<> | 149:156823d33999 | 444 | } |
<> | 149:156823d33999 | 445 | } |
<> | 149:156823d33999 | 446 | |
<> | 149:156823d33999 | 447 | if (uart_base->INTSTS & UART_INTSTS_THREINT_Msk) { |
<> | 149:156823d33999 | 448 | // Simulate clear of the interrupt flag. Temporarily disable the interrupt here and to be recovered on next write. |
<> | 149:156823d33999 | 449 | UART_DISABLE_INT(uart_base, UART_INTEN_THREIEN_Msk); |
<> | 149:156823d33999 | 450 | if (obj->serial.irq_handler) { |
<> | 149:156823d33999 | 451 | ((uart_irq_handler) obj->serial.irq_handler)(obj->serial.irq_id, TxIrq); |
<> | 149:156823d33999 | 452 | } |
<> | 149:156823d33999 | 453 | } |
<> | 149:156823d33999 | 454 | |
<> | 149:156823d33999 | 455 | // FIXME: Ignore all other interrupt flags. Clear them. Otherwise, program will get stuck in interrupt. |
<> | 149:156823d33999 | 456 | uart_base->INTSTS = uart_base->INTSTS; |
<> | 149:156823d33999 | 457 | uart_base->FIFOSTS = uart_base->FIFOSTS; |
<> | 149:156823d33999 | 458 | } |
<> | 149:156823d33999 | 459 | |
<> | 149:156823d33999 | 460 | |
<> | 149:156823d33999 | 461 | #if DEVICE_SERIAL_ASYNCH |
<> | 149:156823d33999 | 462 | int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint) |
<> | 149:156823d33999 | 463 | { |
<> | 149:156823d33999 | 464 | // NOTE: tx_width is deprecated. Assume its value is databits ceiled to the nearest number among 8, 16, and 32. |
<> | 149:156823d33999 | 465 | tx_width = (obj->serial.databits <= 8) ? 8 : (obj->serial.databits <= 16) ? 16 : 32; |
<> | 149:156823d33999 | 466 | |
<> | 149:156823d33999 | 467 | MBED_ASSERT(tx_width == 8 || tx_width == 16 || tx_width == 32); |
<> | 149:156823d33999 | 468 | |
<> | 149:156823d33999 | 469 | obj->serial.dma_usage_tx = hint; |
<> | 149:156823d33999 | 470 | serial_check_dma_usage(&obj->serial.dma_usage_tx, &obj->serial.dma_chn_id_tx); |
<> | 149:156823d33999 | 471 | |
<> | 149:156823d33999 | 472 | // UART IRQ is necessary for both interrupt way and DMA way |
<> | 149:156823d33999 | 473 | serial_tx_enable_event(obj, event, 1); |
<> | 149:156823d33999 | 474 | serial_tx_buffer_set(obj, tx, tx_length, tx_width); |
<> | 149:156823d33999 | 475 | //UART_HAL_DisableTransmitter(obj->serial.address); |
<> | 149:156823d33999 | 476 | //UART_HAL_FlushTxFifo(obj->serial.address); |
<> | 149:156823d33999 | 477 | //UART_HAL_EnableTransmitter(obj->serial.address); |
<> | 149:156823d33999 | 478 | |
<> | 149:156823d33999 | 479 | int n_word = 0; |
<> | 149:156823d33999 | 480 | if (obj->serial.dma_usage_tx == DMA_USAGE_NEVER) { |
<> | 149:156823d33999 | 481 | // Interrupt way |
<> | 149:156823d33999 | 482 | n_word = serial_write_async(obj); |
<> | 149:156823d33999 | 483 | serial_tx_enable_interrupt(obj, handler, 1); |
<> | 149:156823d33999 | 484 | } else { |
<> | 149:156823d33999 | 485 | // DMA way |
<> | 149:156823d33999 | 486 | const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab); |
<> | 149:156823d33999 | 487 | MBED_ASSERT(modinit != NULL); |
<> | 149:156823d33999 | 488 | MBED_ASSERT(modinit->modname == obj->serial.uart); |
<> | 149:156823d33999 | 489 | |
<> | 149:156823d33999 | 490 | PDMA->CHCTL |= 1 << obj->serial.dma_chn_id_tx; // Enable this DMA channel |
<> | 149:156823d33999 | 491 | PDMA_SetTransferMode(obj->serial.dma_chn_id_tx, |
<> | 149:156823d33999 | 492 | ((struct nu_uart_var *) modinit->var)->pdma_perp_tx, // Peripheral connected to this PDMA |
<> | 149:156823d33999 | 493 | 0, // Scatter-gather disabled |
<> | 149:156823d33999 | 494 | 0); // Scatter-gather descriptor address |
<> | 149:156823d33999 | 495 | PDMA_SetTransferCnt(obj->serial.dma_chn_id_tx, |
<> | 149:156823d33999 | 496 | (tx_width == 8) ? PDMA_WIDTH_8 : (tx_width == 16) ? PDMA_WIDTH_16 : PDMA_WIDTH_32, |
<> | 149:156823d33999 | 497 | tx_length); |
<> | 149:156823d33999 | 498 | PDMA_SetTransferAddr(obj->serial.dma_chn_id_tx, |
<> | 149:156823d33999 | 499 | (uint32_t) tx, // NOTE: |
<> | 149:156823d33999 | 500 | // NUC472: End of source address |
<> | 149:156823d33999 | 501 | // M451: Start of source address |
<> | 149:156823d33999 | 502 | PDMA_SAR_INC, // Source address incremental |
<> | 149:156823d33999 | 503 | (uint32_t) obj->serial.uart, // Destination address |
<> | 149:156823d33999 | 504 | PDMA_DAR_FIX); // Destination address fixed |
<> | 149:156823d33999 | 505 | PDMA_SetBurstType(obj->serial.dma_chn_id_tx, |
<> | 149:156823d33999 | 506 | PDMA_REQ_SINGLE, // Single mode |
<> | 149:156823d33999 | 507 | 0); // Burst size |
<> | 149:156823d33999 | 508 | PDMA_EnableInt(obj->serial.dma_chn_id_tx, |
<> | 149:156823d33999 | 509 | PDMA_INT_TRANS_DONE); // Interrupt type |
<> | 149:156823d33999 | 510 | // Register DMA event handler |
<> | 149:156823d33999 | 511 | dma_set_handler(obj->serial.dma_chn_id_tx, (uint32_t) uart_dma_handler_tx, (uint32_t) obj, DMA_EVENT_ALL); |
<> | 149:156823d33999 | 512 | serial_tx_enable_interrupt(obj, handler, 1); |
<> | 149:156823d33999 | 513 | ((UART_T *) NU_MODBASE(obj->serial.uart))->INTEN |= UART_INTEN_TXPDMAEN_Msk; // Start DMA transfer |
<> | 149:156823d33999 | 514 | } |
<> | 149:156823d33999 | 515 | |
<> | 149:156823d33999 | 516 | return n_word; |
<> | 149:156823d33999 | 517 | } |
<> | 149:156823d33999 | 518 | |
<> | 149:156823d33999 | 519 | void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_width, uint32_t handler, uint32_t event, uint8_t char_match, DMAUsage hint) |
<> | 149:156823d33999 | 520 | { |
<> | 149:156823d33999 | 521 | // NOTE: rx_width is deprecated. Assume its value is databits ceiled to the nearest number among 8, 16, and 32. |
<> | 149:156823d33999 | 522 | rx_width = (obj->serial.databits <= 8) ? 8 : (obj->serial.databits <= 16) ? 16 : 32; |
<> | 149:156823d33999 | 523 | |
<> | 149:156823d33999 | 524 | MBED_ASSERT(rx_width == 8 || rx_width == 16 || rx_width == 32); |
<> | 149:156823d33999 | 525 | |
<> | 149:156823d33999 | 526 | obj->serial.dma_usage_rx = hint; |
<> | 149:156823d33999 | 527 | serial_check_dma_usage(&obj->serial.dma_usage_rx, &obj->serial.dma_chn_id_rx); |
<> | 149:156823d33999 | 528 | // DMA doesn't support char match, so fall back to IRQ if it is requested. |
<> | 149:156823d33999 | 529 | if (obj->serial.dma_usage_rx != DMA_USAGE_NEVER && |
<> | 149:156823d33999 | 530 | (event & SERIAL_EVENT_RX_CHARACTER_MATCH) && |
<> | 149:156823d33999 | 531 | char_match != SERIAL_RESERVED_CHAR_MATCH) { |
<> | 149:156823d33999 | 532 | obj->serial.dma_usage_rx = DMA_USAGE_NEVER; |
<> | 149:156823d33999 | 533 | dma_channel_free(obj->serial.dma_chn_id_rx); |
<> | 149:156823d33999 | 534 | obj->serial.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS; |
<> | 149:156823d33999 | 535 | } |
<> | 149:156823d33999 | 536 | |
<> | 149:156823d33999 | 537 | // UART IRQ is necessary for both interrupt way and DMA way |
<> | 149:156823d33999 | 538 | serial_rx_enable_event(obj, event, 1); |
<> | 149:156823d33999 | 539 | serial_rx_buffer_set(obj, rx, rx_length, rx_width); |
<> | 149:156823d33999 | 540 | serial_rx_set_char_match(obj, char_match); |
<> | 149:156823d33999 | 541 | //UART_HAL_DisableReceiver(obj->serial.address); |
<> | 149:156823d33999 | 542 | //UART_HAL_FlushRxFifo(obj->serial.address); |
<> | 149:156823d33999 | 543 | //UART_HAL_EnableReceiver(obj->serial.address); |
<> | 149:156823d33999 | 544 | |
<> | 149:156823d33999 | 545 | if (obj->serial.dma_usage_rx == DMA_USAGE_NEVER) { |
<> | 149:156823d33999 | 546 | // Interrupt way |
<> | 149:156823d33999 | 547 | serial_rx_enable_interrupt(obj, handler, 1); |
<> | 149:156823d33999 | 548 | } else { |
<> | 149:156823d33999 | 549 | // DMA way |
<> | 149:156823d33999 | 550 | const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab); |
<> | 149:156823d33999 | 551 | MBED_ASSERT(modinit != NULL); |
<> | 149:156823d33999 | 552 | MBED_ASSERT(modinit->modname == obj->serial.uart); |
<> | 149:156823d33999 | 553 | |
<> | 149:156823d33999 | 554 | PDMA->CHCTL |= 1 << obj->serial.dma_chn_id_rx; // Enable this DMA channel |
<> | 149:156823d33999 | 555 | PDMA_SetTransferMode(obj->serial.dma_chn_id_rx, |
<> | 149:156823d33999 | 556 | ((struct nu_uart_var *) modinit->var)->pdma_perp_rx, // Peripheral connected to this PDMA |
<> | 149:156823d33999 | 557 | 0, // Scatter-gather disabled |
<> | 149:156823d33999 | 558 | 0); // Scatter-gather descriptor address |
<> | 149:156823d33999 | 559 | PDMA_SetTransferCnt(obj->serial.dma_chn_id_rx, |
<> | 149:156823d33999 | 560 | (rx_width == 8) ? PDMA_WIDTH_8 : (rx_width == 16) ? PDMA_WIDTH_16 : PDMA_WIDTH_32, |
<> | 149:156823d33999 | 561 | rx_length); |
<> | 149:156823d33999 | 562 | PDMA_SetTransferAddr(obj->serial.dma_chn_id_rx, |
<> | 149:156823d33999 | 563 | (uint32_t) obj->serial.uart, // Source address |
<> | 149:156823d33999 | 564 | PDMA_SAR_FIX, // Source address fixed |
<> | 149:156823d33999 | 565 | (uint32_t) rx, // NOTE: |
<> | 149:156823d33999 | 566 | // NUC472: End of destination address |
<> | 149:156823d33999 | 567 | // M451: Start of destination address |
<> | 149:156823d33999 | 568 | PDMA_DAR_INC); // Destination address incremental |
<> | 149:156823d33999 | 569 | PDMA_SetBurstType(obj->serial.dma_chn_id_rx, |
<> | 149:156823d33999 | 570 | PDMA_REQ_SINGLE, // Single mode |
<> | 149:156823d33999 | 571 | 0); // Burst size |
<> | 149:156823d33999 | 572 | PDMA_EnableInt(obj->serial.dma_chn_id_rx, |
<> | 149:156823d33999 | 573 | PDMA_INT_TRANS_DONE); // Interrupt type |
<> | 149:156823d33999 | 574 | // Register DMA event handler |
<> | 149:156823d33999 | 575 | dma_set_handler(obj->serial.dma_chn_id_rx, (uint32_t) uart_dma_handler_rx, (uint32_t) obj, DMA_EVENT_ALL); |
<> | 149:156823d33999 | 576 | serial_rx_enable_interrupt(obj, handler, 1); |
<> | 149:156823d33999 | 577 | ((UART_T *) NU_MODBASE(obj->serial.uart))->INTEN |= UART_INTEN_RXPDMAEN_Msk; // Start DMA transfer |
<> | 149:156823d33999 | 578 | } |
<> | 149:156823d33999 | 579 | } |
<> | 149:156823d33999 | 580 | |
<> | 149:156823d33999 | 581 | void serial_tx_abort_asynch(serial_t *obj) |
<> | 149:156823d33999 | 582 | { |
<> | 149:156823d33999 | 583 | // Flush Tx FIFO. Otherwise, output data may get lost on this change. |
<> | 149:156823d33999 | 584 | while (! UART_IS_TX_EMPTY(((UART_T *) obj->serial.uart))); |
<> | 149:156823d33999 | 585 | |
<> | 149:156823d33999 | 586 | if (obj->serial.dma_usage_tx != DMA_USAGE_NEVER) { |
<> | 149:156823d33999 | 587 | if (obj->serial.dma_chn_id_tx != DMA_ERROR_OUT_OF_CHANNELS) { |
<> | 149:156823d33999 | 588 | PDMA_DisableInt(obj->serial.dma_chn_id_tx, PDMA_INT_TRANS_DONE); |
<> | 149:156823d33999 | 589 | // FIXME: On NUC472, next PDMA transfer will fail with PDMA_STOP() called. Cause is unknown. |
<> | 149:156823d33999 | 590 | //PDMA_STOP(obj->serial.dma_chn_id_tx); |
<> | 149:156823d33999 | 591 | PDMA->CHCTL &= ~(1 << obj->serial.dma_chn_id_tx); |
<> | 149:156823d33999 | 592 | } |
<> | 149:156823d33999 | 593 | UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_TXPDMAEN_Msk); |
<> | 149:156823d33999 | 594 | } |
<> | 149:156823d33999 | 595 | |
<> | 149:156823d33999 | 596 | // Necessary for both interrupt way and DMA way |
<> | 149:156823d33999 | 597 | serial_irq_set(obj, TxIrq, 0); |
<> | 149:156823d33999 | 598 | // FIXME: more complete abort operation |
<> | 149:156823d33999 | 599 | //UART_HAL_DisableTransmitter(obj->serial.serial.address); |
<> | 149:156823d33999 | 600 | //UART_HAL_FlushTxFifo(obj->serial.serial.address); |
<> | 149:156823d33999 | 601 | } |
<> | 149:156823d33999 | 602 | |
<> | 149:156823d33999 | 603 | void serial_rx_abort_asynch(serial_t *obj) |
<> | 149:156823d33999 | 604 | { |
<> | 149:156823d33999 | 605 | if (obj->serial.dma_usage_rx != DMA_USAGE_NEVER) { |
<> | 149:156823d33999 | 606 | if (obj->serial.dma_chn_id_rx != DMA_ERROR_OUT_OF_CHANNELS) { |
<> | 149:156823d33999 | 607 | PDMA_DisableInt(obj->serial.dma_chn_id_rx, PDMA_INT_TRANS_DONE); |
<> | 149:156823d33999 | 608 | // FIXME: On NUC472, next PDMA transfer will fail with PDMA_STOP() called. Cause is unknown. |
<> | 149:156823d33999 | 609 | //PDMA_STOP(obj->serial.dma_chn_id_rx); |
<> | 149:156823d33999 | 610 | PDMA->CHCTL &= ~(1 << obj->serial.dma_chn_id_rx); |
<> | 149:156823d33999 | 611 | } |
<> | 149:156823d33999 | 612 | UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_RXPDMAEN_Msk); |
<> | 149:156823d33999 | 613 | } |
<> | 149:156823d33999 | 614 | |
<> | 149:156823d33999 | 615 | // Necessary for both interrupt way and DMA way |
<> | 149:156823d33999 | 616 | serial_irq_set(obj, RxIrq, 0); |
<> | 149:156823d33999 | 617 | // FIXME: more complete abort operation |
<> | 149:156823d33999 | 618 | //UART_HAL_DisableReceiver(obj->serial.serial.address); |
<> | 149:156823d33999 | 619 | //UART_HAL_FlushRxFifo(obj->serial.serial.address); |
<> | 149:156823d33999 | 620 | } |
<> | 149:156823d33999 | 621 | |
<> | 149:156823d33999 | 622 | uint8_t serial_tx_active(serial_t *obj) |
<> | 149:156823d33999 | 623 | { |
<> | 149:156823d33999 | 624 | return serial_is_irq_en(obj, TxIrq); |
<> | 149:156823d33999 | 625 | } |
<> | 149:156823d33999 | 626 | |
<> | 149:156823d33999 | 627 | uint8_t serial_rx_active(serial_t *obj) |
<> | 149:156823d33999 | 628 | { |
<> | 149:156823d33999 | 629 | return serial_is_irq_en(obj, RxIrq); |
<> | 149:156823d33999 | 630 | } |
<> | 149:156823d33999 | 631 | |
<> | 149:156823d33999 | 632 | int serial_irq_handler_asynch(serial_t *obj) |
<> | 149:156823d33999 | 633 | { |
<> | 149:156823d33999 | 634 | int event_rx = 0; |
<> | 149:156823d33999 | 635 | int event_tx = 0; |
<> | 149:156823d33999 | 636 | |
<> | 149:156823d33999 | 637 | // Necessary for both interrup way and DMA way |
<> | 149:156823d33999 | 638 | if (serial_is_irq_en(obj, RxIrq)) { |
<> | 149:156823d33999 | 639 | event_rx = serial_rx_event_check(obj); |
<> | 149:156823d33999 | 640 | if (event_rx) { |
<> | 149:156823d33999 | 641 | serial_rx_abort_asynch(obj); |
<> | 149:156823d33999 | 642 | } |
<> | 149:156823d33999 | 643 | } |
<> | 149:156823d33999 | 644 | |
<> | 149:156823d33999 | 645 | if (serial_is_irq_en(obj, TxIrq)) { |
<> | 149:156823d33999 | 646 | event_tx = serial_tx_event_check(obj); |
<> | 149:156823d33999 | 647 | if (event_tx) { |
<> | 149:156823d33999 | 648 | serial_tx_abort_asynch(obj); |
<> | 149:156823d33999 | 649 | } |
<> | 149:156823d33999 | 650 | } |
<> | 149:156823d33999 | 651 | |
<> | 149:156823d33999 | 652 | return (obj->serial.event & (event_rx | event_tx)); |
<> | 149:156823d33999 | 653 | } |
<> | 149:156823d33999 | 654 | |
<> | 149:156823d33999 | 655 | int serial_allow_powerdown(void) |
<> | 149:156823d33999 | 656 | { |
<> | 149:156823d33999 | 657 | uint32_t modinit_mask = uart_modinit_mask; |
<> | 149:156823d33999 | 658 | while (modinit_mask) { |
<> | 149:156823d33999 | 659 | int uart_idx = nu_ctz(modinit_mask); |
<> | 149:156823d33999 | 660 | const struct nu_modinit_s *modinit = uart_modinit_tab + uart_idx; |
<> | 149:156823d33999 | 661 | if (modinit->modname != NC) { |
<> | 149:156823d33999 | 662 | UART_T *uart_base = (UART_T *) NU_MODBASE(modinit->modname); |
<> | 149:156823d33999 | 663 | // Disallow entering power-down mode if Tx FIFO has data to flush |
<> | 149:156823d33999 | 664 | if (! UART_IS_TX_EMPTY((uart_base))) { |
<> | 149:156823d33999 | 665 | return 0; |
<> | 149:156823d33999 | 666 | } |
<> | 149:156823d33999 | 667 | // Disallow entering power-down mode if async Rx transfer (not PDMA) is on-going |
<> | 149:156823d33999 | 668 | if (uart_base->INTEN & (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)) { |
<> | 149:156823d33999 | 669 | return 0; |
<> | 149:156823d33999 | 670 | } |
<> | 149:156823d33999 | 671 | // Disallow entering power-down mode if async Rx transfer (PDMA) is on-going |
<> | 149:156823d33999 | 672 | if (uart_base->INTEN & UART_INTEN_RXPDMAEN_Msk) { |
<> | 149:156823d33999 | 673 | return 0; |
<> | 149:156823d33999 | 674 | } |
<> | 149:156823d33999 | 675 | } |
<> | 149:156823d33999 | 676 | modinit_mask &= ~(1 << uart_idx); |
<> | 149:156823d33999 | 677 | } |
<> | 149:156823d33999 | 678 | |
<> | 149:156823d33999 | 679 | return 1; |
<> | 149:156823d33999 | 680 | } |
<> | 149:156823d33999 | 681 | |
<> | 149:156823d33999 | 682 | static void uart0_vec_async(void) |
<> | 149:156823d33999 | 683 | { |
<> | 149:156823d33999 | 684 | uart_irq_async(uart0_var.obj); |
<> | 149:156823d33999 | 685 | } |
<> | 149:156823d33999 | 686 | |
<> | 149:156823d33999 | 687 | static void uart1_vec_async(void) |
<> | 149:156823d33999 | 688 | { |
<> | 149:156823d33999 | 689 | uart_irq_async(uart1_var.obj); |
<> | 149:156823d33999 | 690 | } |
<> | 149:156823d33999 | 691 | |
<> | 149:156823d33999 | 692 | static void uart2_vec_async(void) |
<> | 149:156823d33999 | 693 | { |
<> | 149:156823d33999 | 694 | uart_irq_async(uart2_var.obj); |
<> | 149:156823d33999 | 695 | } |
<> | 149:156823d33999 | 696 | |
<> | 149:156823d33999 | 697 | static void uart3_vec_async(void) |
<> | 149:156823d33999 | 698 | { |
<> | 149:156823d33999 | 699 | uart_irq_async(uart3_var.obj); |
<> | 149:156823d33999 | 700 | } |
<> | 149:156823d33999 | 701 | |
<> | 149:156823d33999 | 702 | static void uart_irq_async(serial_t *obj) |
<> | 149:156823d33999 | 703 | { |
<> | 149:156823d33999 | 704 | if (serial_is_irq_en(obj, RxIrq)) { |
<> | 149:156823d33999 | 705 | (*obj->serial.irq_handler_rx_async)(); |
<> | 149:156823d33999 | 706 | } |
<> | 149:156823d33999 | 707 | if (serial_is_irq_en(obj, TxIrq)) { |
<> | 149:156823d33999 | 708 | (*obj->serial.irq_handler_tx_async)(); |
<> | 149:156823d33999 | 709 | } |
<> | 149:156823d33999 | 710 | } |
<> | 149:156823d33999 | 711 | |
<> | 149:156823d33999 | 712 | static void serial_rx_set_char_match(serial_t *obj, uint8_t char_match) |
<> | 149:156823d33999 | 713 | { |
<> | 149:156823d33999 | 714 | obj->char_match = char_match; |
<> | 149:156823d33999 | 715 | obj->char_found = 0; |
<> | 149:156823d33999 | 716 | } |
<> | 149:156823d33999 | 717 | |
<> | 149:156823d33999 | 718 | static void serial_tx_enable_event(serial_t *obj, int event, uint8_t enable) |
<> | 149:156823d33999 | 719 | { |
<> | 149:156823d33999 | 720 | obj->serial.event &= ~SERIAL_EVENT_TX_MASK; |
<> | 149:156823d33999 | 721 | obj->serial.event |= (event & SERIAL_EVENT_TX_MASK); |
<> | 149:156823d33999 | 722 | |
<> | 149:156823d33999 | 723 | //if (event & SERIAL_EVENT_TX_COMPLETE) { |
<> | 149:156823d33999 | 724 | //} |
<> | 149:156823d33999 | 725 | } |
<> | 149:156823d33999 | 726 | |
<> | 149:156823d33999 | 727 | static void serial_rx_enable_event(serial_t *obj, int event, uint8_t enable) |
<> | 149:156823d33999 | 728 | { |
<> | 149:156823d33999 | 729 | obj->serial.event &= ~SERIAL_EVENT_RX_MASK; |
<> | 149:156823d33999 | 730 | obj->serial.event |= (event & SERIAL_EVENT_RX_MASK); |
<> | 149:156823d33999 | 731 | |
<> | 149:156823d33999 | 732 | //if (event & SERIAL_EVENT_RX_COMPLETE) { |
<> | 149:156823d33999 | 733 | //} |
<> | 149:156823d33999 | 734 | //if (event & SERIAL_EVENT_RX_OVERRUN_ERROR) { |
<> | 149:156823d33999 | 735 | //} |
<> | 149:156823d33999 | 736 | if (event & SERIAL_EVENT_RX_FRAMING_ERROR) { |
<> | 149:156823d33999 | 737 | UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_RLSIEN_Msk); |
<> | 149:156823d33999 | 738 | } |
<> | 149:156823d33999 | 739 | if (event & SERIAL_EVENT_RX_PARITY_ERROR) { |
<> | 149:156823d33999 | 740 | UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_RLSIEN_Msk); |
<> | 149:156823d33999 | 741 | } |
<> | 149:156823d33999 | 742 | if (event & SERIAL_EVENT_RX_OVERFLOW) { |
<> | 149:156823d33999 | 743 | UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_BUFERRIEN_Msk); |
<> | 149:156823d33999 | 744 | } |
<> | 149:156823d33999 | 745 | //if (event & SERIAL_EVENT_RX_CHARACTER_MATCH) { |
<> | 149:156823d33999 | 746 | //} |
<> | 149:156823d33999 | 747 | } |
<> | 149:156823d33999 | 748 | |
<> | 149:156823d33999 | 749 | static int serial_is_tx_complete(serial_t *obj) |
<> | 149:156823d33999 | 750 | { |
<> | 149:156823d33999 | 751 | // NOTE: Exclude tx fifo empty check due to no such interrupt on DMA way |
<> | 149:156823d33999 | 752 | //return (obj->tx_buff.pos == obj->tx_buff.length) && UART_GET_TX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart))); |
<> | 149:156823d33999 | 753 | // FIXME: Premature abort??? |
<> | 149:156823d33999 | 754 | return (obj->tx_buff.pos == obj->tx_buff.length); |
<> | 149:156823d33999 | 755 | } |
<> | 149:156823d33999 | 756 | |
<> | 149:156823d33999 | 757 | static int serial_is_rx_complete(serial_t *obj) |
<> | 149:156823d33999 | 758 | { |
<> | 149:156823d33999 | 759 | //return (obj->rx_buff.pos == obj->rx_buff.length) && UART_GET_RX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart))); |
<> | 149:156823d33999 | 760 | return (obj->rx_buff.pos == obj->rx_buff.length); |
<> | 149:156823d33999 | 761 | } |
<> | 149:156823d33999 | 762 | |
<> | 149:156823d33999 | 763 | static uint32_t serial_tx_event_check(serial_t *obj) |
<> | 149:156823d33999 | 764 | { |
<> | 149:156823d33999 | 765 | UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart); |
<> | 149:156823d33999 | 766 | |
<> | 149:156823d33999 | 767 | if (uart_base->INTSTS & UART_INTSTS_THREINT_Msk) { |
<> | 149:156823d33999 | 768 | // Simulate clear of the interrupt flag. Temporarily disable the interrupt here and to be recovered on next write. |
<> | 149:156823d33999 | 769 | UART_DISABLE_INT(uart_base, UART_INTEN_THREIEN_Msk); |
<> | 149:156823d33999 | 770 | } |
<> | 149:156823d33999 | 771 | |
<> | 149:156823d33999 | 772 | uint32_t event = 0; |
<> | 149:156823d33999 | 773 | |
<> | 149:156823d33999 | 774 | if (obj->serial.dma_usage_tx == DMA_USAGE_NEVER) { |
<> | 149:156823d33999 | 775 | serial_write_async(obj); |
<> | 149:156823d33999 | 776 | } |
<> | 149:156823d33999 | 777 | |
<> | 149:156823d33999 | 778 | if (serial_is_tx_complete(obj)) { |
<> | 149:156823d33999 | 779 | event |= SERIAL_EVENT_TX_COMPLETE; |
<> | 149:156823d33999 | 780 | } |
<> | 149:156823d33999 | 781 | |
<> | 149:156823d33999 | 782 | return event; |
<> | 149:156823d33999 | 783 | } |
<> | 149:156823d33999 | 784 | |
<> | 149:156823d33999 | 785 | static uint32_t serial_rx_event_check(serial_t *obj) |
<> | 149:156823d33999 | 786 | { |
<> | 149:156823d33999 | 787 | UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart); |
<> | 149:156823d33999 | 788 | |
<> | 149:156823d33999 | 789 | if (uart_base->INTSTS & (UART_INTSTS_RDAINT_Msk | UART_INTSTS_RXTOINT_Msk)) { |
<> | 149:156823d33999 | 790 | // Simulate clear of the interrupt flag. Temporarily disable the interrupt here and to be recovered on next read. |
<> | 149:156823d33999 | 791 | UART_DISABLE_INT(uart_base, (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)); |
<> | 149:156823d33999 | 792 | } |
<> | 149:156823d33999 | 793 | |
<> | 149:156823d33999 | 794 | uint32_t event = 0; |
<> | 149:156823d33999 | 795 | |
<> | 149:156823d33999 | 796 | if (uart_base->FIFOSTS & UART_FIFOSTS_BIF_Msk) { |
<> | 149:156823d33999 | 797 | uart_base->FIFOSTS = UART_FIFOSTS_BIF_Msk; |
<> | 149:156823d33999 | 798 | } |
<> | 149:156823d33999 | 799 | if (uart_base->FIFOSTS & UART_FIFOSTS_FEF_Msk) { |
<> | 149:156823d33999 | 800 | uart_base->FIFOSTS = UART_FIFOSTS_FEF_Msk; |
<> | 149:156823d33999 | 801 | event |= SERIAL_EVENT_RX_FRAMING_ERROR; |
<> | 149:156823d33999 | 802 | } |
<> | 149:156823d33999 | 803 | if (uart_base->FIFOSTS & UART_FIFOSTS_PEF_Msk) { |
<> | 149:156823d33999 | 804 | uart_base->FIFOSTS = UART_FIFOSTS_PEF_Msk; |
<> | 149:156823d33999 | 805 | event |= SERIAL_EVENT_RX_PARITY_ERROR; |
<> | 149:156823d33999 | 806 | } |
<> | 149:156823d33999 | 807 | |
<> | 149:156823d33999 | 808 | if (uart_base->FIFOSTS & UART_FIFOSTS_RXOVIF_Msk) { |
<> | 149:156823d33999 | 809 | uart_base->FIFOSTS = UART_FIFOSTS_RXOVIF_Msk; |
<> | 149:156823d33999 | 810 | event |= SERIAL_EVENT_RX_OVERFLOW; |
<> | 149:156823d33999 | 811 | } |
<> | 149:156823d33999 | 812 | |
<> | 149:156823d33999 | 813 | if (obj->serial.dma_usage_rx == DMA_USAGE_NEVER) { |
<> | 149:156823d33999 | 814 | serial_read_async(obj); |
<> | 149:156823d33999 | 815 | } |
<> | 149:156823d33999 | 816 | |
<> | 149:156823d33999 | 817 | if (serial_is_rx_complete(obj)) { |
<> | 149:156823d33999 | 818 | event |= SERIAL_EVENT_RX_COMPLETE; |
<> | 149:156823d33999 | 819 | } |
<> | 149:156823d33999 | 820 | if ((obj->char_match != SERIAL_RESERVED_CHAR_MATCH) && obj->char_found) { |
<> | 149:156823d33999 | 821 | event |= SERIAL_EVENT_RX_CHARACTER_MATCH; |
<> | 149:156823d33999 | 822 | // FIXME: Timing to reset char_found? |
<> | 149:156823d33999 | 823 | //obj->char_found = 0; |
<> | 149:156823d33999 | 824 | } |
<> | 149:156823d33999 | 825 | |
<> | 149:156823d33999 | 826 | return event; |
<> | 149:156823d33999 | 827 | } |
<> | 149:156823d33999 | 828 | |
<> | 149:156823d33999 | 829 | static void uart_dma_handler_tx(uint32_t id, uint32_t event_dma) |
<> | 149:156823d33999 | 830 | { |
<> | 149:156823d33999 | 831 | serial_t *obj = (serial_t *) id; |
<> | 149:156823d33999 | 832 | |
<> | 149:156823d33999 | 833 | // FIXME: Pass this error to caller |
<> | 149:156823d33999 | 834 | if (event_dma & DMA_EVENT_ABORT) { |
<> | 149:156823d33999 | 835 | } |
<> | 149:156823d33999 | 836 | // Expect UART IRQ will catch this transfer done event |
<> | 149:156823d33999 | 837 | if (event_dma & DMA_EVENT_TRANSFER_DONE) { |
<> | 149:156823d33999 | 838 | obj->tx_buff.pos = obj->tx_buff.length; |
<> | 149:156823d33999 | 839 | } |
<> | 149:156823d33999 | 840 | // FIXME: Pass this error to caller |
<> | 149:156823d33999 | 841 | if (event_dma & DMA_EVENT_TIMEOUT) { |
<> | 149:156823d33999 | 842 | } |
<> | 149:156823d33999 | 843 | |
<> | 149:156823d33999 | 844 | uart_irq_async(obj); |
<> | 149:156823d33999 | 845 | } |
<> | 149:156823d33999 | 846 | |
<> | 149:156823d33999 | 847 | static void uart_dma_handler_rx(uint32_t id, uint32_t event_dma) |
<> | 149:156823d33999 | 848 | { |
<> | 149:156823d33999 | 849 | serial_t *obj = (serial_t *) id; |
<> | 149:156823d33999 | 850 | |
<> | 149:156823d33999 | 851 | // FIXME: Pass this error to caller |
<> | 149:156823d33999 | 852 | if (event_dma & DMA_EVENT_ABORT) { |
<> | 149:156823d33999 | 853 | } |
<> | 149:156823d33999 | 854 | // Expect UART IRQ will catch this transfer done event |
<> | 149:156823d33999 | 855 | if (event_dma & DMA_EVENT_TRANSFER_DONE) { |
<> | 149:156823d33999 | 856 | obj->rx_buff.pos = obj->rx_buff.length; |
<> | 149:156823d33999 | 857 | } |
<> | 149:156823d33999 | 858 | // FIXME: Pass this error to caller |
<> | 149:156823d33999 | 859 | if (event_dma & DMA_EVENT_TIMEOUT) { |
<> | 149:156823d33999 | 860 | } |
<> | 149:156823d33999 | 861 | |
<> | 149:156823d33999 | 862 | uart_irq_async(obj); |
<> | 149:156823d33999 | 863 | } |
<> | 149:156823d33999 | 864 | |
<> | 149:156823d33999 | 865 | static int serial_write_async(serial_t *obj) |
<> | 149:156823d33999 | 866 | { |
<> | 149:156823d33999 | 867 | const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab); |
<> | 149:156823d33999 | 868 | MBED_ASSERT(modinit != NULL); |
<> | 149:156823d33999 | 869 | MBED_ASSERT(modinit->modname == obj->serial.uart); |
<> | 149:156823d33999 | 870 | |
<> | 149:156823d33999 | 871 | UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart); |
<> | 149:156823d33999 | 872 | |
<> | 149:156823d33999 | 873 | uint32_t tx_fifo_max = ((struct nu_uart_var *) modinit->var)->fifo_size_tx; |
<> | 149:156823d33999 | 874 | uint32_t tx_fifo_busy = (uart_base->FIFOSTS & UART_FIFOSTS_TXPTR_Msk) >> UART_FIFOSTS_TXPTR_Pos; |
<> | 149:156823d33999 | 875 | if (uart_base->FIFOSTS & UART_FIFOSTS_TXFULL_Msk) { |
<> | 149:156823d33999 | 876 | tx_fifo_busy = tx_fifo_max; |
<> | 149:156823d33999 | 877 | } |
<> | 149:156823d33999 | 878 | uint32_t tx_fifo_free = tx_fifo_max - tx_fifo_busy; |
<> | 149:156823d33999 | 879 | if (tx_fifo_free == 0) { |
<> | 149:156823d33999 | 880 | // Simulate clear of the interrupt flag |
<> | 149:156823d33999 | 881 | if (obj->serial.inten_msk & UART_INTEN_THREIEN_Msk) { |
<> | 149:156823d33999 | 882 | UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk); |
<> | 149:156823d33999 | 883 | } |
<> | 149:156823d33999 | 884 | return 0; |
<> | 149:156823d33999 | 885 | } |
<> | 149:156823d33999 | 886 | |
<> | 149:156823d33999 | 887 | uint32_t bytes_per_word = obj->tx_buff.width / 8; |
<> | 149:156823d33999 | 888 | |
<> | 149:156823d33999 | 889 | uint8_t *tx = (uint8_t *)(obj->tx_buff.buffer) + bytes_per_word * obj->tx_buff.pos; |
<> | 149:156823d33999 | 890 | int n_words = 0; |
<> | 149:156823d33999 | 891 | while (obj->tx_buff.pos < obj->tx_buff.length && tx_fifo_free >= bytes_per_word) { |
<> | 149:156823d33999 | 892 | switch (bytes_per_word) { |
<> | 149:156823d33999 | 893 | case 4: |
<> | 149:156823d33999 | 894 | UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), *tx ++); |
<> | 149:156823d33999 | 895 | UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), *tx ++); |
<> | 149:156823d33999 | 896 | case 2: |
<> | 149:156823d33999 | 897 | UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), *tx ++); |
<> | 149:156823d33999 | 898 | case 1: |
<> | 149:156823d33999 | 899 | UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), *tx ++); |
<> | 149:156823d33999 | 900 | } |
<> | 149:156823d33999 | 901 | |
<> | 149:156823d33999 | 902 | n_words ++; |
<> | 149:156823d33999 | 903 | tx_fifo_free -= bytes_per_word; |
<> | 149:156823d33999 | 904 | obj->tx_buff.pos ++; |
<> | 149:156823d33999 | 905 | } |
<> | 149:156823d33999 | 906 | |
<> | 149:156823d33999 | 907 | if (n_words) { |
<> | 149:156823d33999 | 908 | // Simulate clear of the interrupt flag |
<> | 149:156823d33999 | 909 | if (obj->serial.inten_msk & UART_INTEN_THREIEN_Msk) { |
<> | 149:156823d33999 | 910 | UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk); |
<> | 149:156823d33999 | 911 | } |
<> | 149:156823d33999 | 912 | } |
<> | 149:156823d33999 | 913 | |
<> | 149:156823d33999 | 914 | return n_words; |
<> | 149:156823d33999 | 915 | } |
<> | 149:156823d33999 | 916 | |
<> | 149:156823d33999 | 917 | static int serial_read_async(serial_t *obj) |
<> | 149:156823d33999 | 918 | { |
<> | 149:156823d33999 | 919 | const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab); |
<> | 149:156823d33999 | 920 | MBED_ASSERT(modinit != NULL); |
<> | 149:156823d33999 | 921 | MBED_ASSERT(modinit->modname == obj->serial.uart); |
<> | 149:156823d33999 | 922 | |
<> | 149:156823d33999 | 923 | uint32_t rx_fifo_busy = (((UART_T *) NU_MODBASE(obj->serial.uart))->FIFOSTS & UART_FIFOSTS_RXPTR_Msk) >> UART_FIFOSTS_RXPTR_Pos; |
<> | 149:156823d33999 | 924 | //uint32_t rx_fifo_free = ((struct nu_uart_var *) modinit->var)->fifo_size_rx - rx_fifo_busy; |
<> | 149:156823d33999 | 925 | //if (rx_fifo_free == 0) { |
<> | 149:156823d33999 | 926 | // return 0; |
<> | 149:156823d33999 | 927 | //} |
<> | 149:156823d33999 | 928 | |
<> | 149:156823d33999 | 929 | uint32_t bytes_per_word = obj->rx_buff.width / 8; |
<> | 149:156823d33999 | 930 | |
<> | 149:156823d33999 | 931 | uint8_t *rx = (uint8_t *)(obj->rx_buff.buffer) + bytes_per_word * obj->rx_buff.pos; |
<> | 149:156823d33999 | 932 | int n_words = 0; |
<> | 149:156823d33999 | 933 | while (obj->rx_buff.pos < obj->rx_buff.length && rx_fifo_busy >= bytes_per_word) { |
<> | 149:156823d33999 | 934 | switch (bytes_per_word) { |
<> | 149:156823d33999 | 935 | case 4: |
<> | 149:156823d33999 | 936 | *rx ++ = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart))); |
<> | 149:156823d33999 | 937 | *rx ++ = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart))); |
<> | 149:156823d33999 | 938 | case 2: |
<> | 149:156823d33999 | 939 | *rx ++ = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart))); |
<> | 149:156823d33999 | 940 | case 1: |
<> | 149:156823d33999 | 941 | *rx ++ = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart))); |
<> | 149:156823d33999 | 942 | } |
<> | 149:156823d33999 | 943 | |
<> | 149:156823d33999 | 944 | n_words ++; |
<> | 149:156823d33999 | 945 | rx_fifo_busy -= bytes_per_word; |
<> | 149:156823d33999 | 946 | obj->rx_buff.pos ++; |
<> | 149:156823d33999 | 947 | |
<> | 149:156823d33999 | 948 | if ((obj->serial.event & SERIAL_EVENT_RX_CHARACTER_MATCH) && |
<> | 149:156823d33999 | 949 | obj->char_match != SERIAL_RESERVED_CHAR_MATCH) { |
<> | 149:156823d33999 | 950 | uint8_t *rx_cmp = rx; |
<> | 149:156823d33999 | 951 | switch (bytes_per_word) { |
<> | 149:156823d33999 | 952 | case 4: |
<> | 149:156823d33999 | 953 | rx_cmp -= 2; |
<> | 149:156823d33999 | 954 | case 2: |
<> | 149:156823d33999 | 955 | rx_cmp --; |
<> | 149:156823d33999 | 956 | case 1: |
<> | 149:156823d33999 | 957 | rx_cmp --; |
<> | 149:156823d33999 | 958 | } |
<> | 149:156823d33999 | 959 | if (*rx_cmp == obj->char_match) { |
<> | 149:156823d33999 | 960 | obj->char_found = 1; |
<> | 149:156823d33999 | 961 | break; |
<> | 149:156823d33999 | 962 | } |
<> | 149:156823d33999 | 963 | } |
<> | 149:156823d33999 | 964 | } |
<> | 149:156823d33999 | 965 | |
<> | 149:156823d33999 | 966 | if (n_words) { |
<> | 149:156823d33999 | 967 | // Simulate clear of the interrupt flag |
<> | 149:156823d33999 | 968 | if (obj->serial.inten_msk & (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)) { |
<> | 149:156823d33999 | 969 | UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)); |
<> | 149:156823d33999 | 970 | } |
<> | 149:156823d33999 | 971 | } |
<> | 149:156823d33999 | 972 | |
<> | 149:156823d33999 | 973 | return n_words; |
<> | 149:156823d33999 | 974 | } |
<> | 149:156823d33999 | 975 | |
<> | 149:156823d33999 | 976 | static void serial_tx_buffer_set(serial_t *obj, const void *tx, size_t length, uint8_t width) |
<> | 149:156823d33999 | 977 | { |
<> | 149:156823d33999 | 978 | obj->tx_buff.buffer = (void *) tx; |
<> | 149:156823d33999 | 979 | obj->tx_buff.length = length; |
<> | 149:156823d33999 | 980 | obj->tx_buff.pos = 0; |
<> | 149:156823d33999 | 981 | obj->tx_buff.width = width; |
<> | 149:156823d33999 | 982 | } |
<> | 149:156823d33999 | 983 | |
<> | 149:156823d33999 | 984 | static void serial_rx_buffer_set(serial_t *obj, void *rx, size_t length, uint8_t width) |
<> | 149:156823d33999 | 985 | { |
<> | 149:156823d33999 | 986 | obj->rx_buff.buffer = rx; |
<> | 149:156823d33999 | 987 | obj->rx_buff.length = length; |
<> | 149:156823d33999 | 988 | obj->rx_buff.pos = 0; |
<> | 149:156823d33999 | 989 | obj->rx_buff.width = width; |
<> | 149:156823d33999 | 990 | } |
<> | 149:156823d33999 | 991 | |
<> | 149:156823d33999 | 992 | static void serial_tx_enable_interrupt(serial_t *obj, uint32_t handler, uint8_t enable) |
<> | 149:156823d33999 | 993 | { |
<> | 149:156823d33999 | 994 | const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab); |
<> | 149:156823d33999 | 995 | MBED_ASSERT(modinit != NULL); |
<> | 149:156823d33999 | 996 | MBED_ASSERT(modinit->modname == obj->serial.uart); |
<> | 149:156823d33999 | 997 | |
<> | 149:156823d33999 | 998 | // Necessary for both interrupt way and DMA way |
<> | 149:156823d33999 | 999 | ((struct nu_uart_var *) modinit->var)->obj = obj; |
<> | 149:156823d33999 | 1000 | // With our own async vector, tx/rx handlers can be different. |
<> | 149:156823d33999 | 1001 | obj->serial.vec = ((struct nu_uart_var *) modinit->var)->vec_async; |
<> | 149:156823d33999 | 1002 | obj->serial.irq_handler_tx_async = (void (*)(void)) handler; |
<> | 149:156823d33999 | 1003 | serial_irq_set(obj, TxIrq, enable); |
<> | 149:156823d33999 | 1004 | } |
<> | 149:156823d33999 | 1005 | |
<> | 149:156823d33999 | 1006 | static void serial_rx_enable_interrupt(serial_t *obj, uint32_t handler, uint8_t enable) |
<> | 149:156823d33999 | 1007 | { |
<> | 149:156823d33999 | 1008 | const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab); |
<> | 149:156823d33999 | 1009 | MBED_ASSERT(modinit != NULL); |
<> | 149:156823d33999 | 1010 | MBED_ASSERT(modinit->modname == obj->serial.uart); |
<> | 149:156823d33999 | 1011 | |
<> | 149:156823d33999 | 1012 | // Necessary for both interrupt way and DMA way |
<> | 149:156823d33999 | 1013 | ((struct nu_uart_var *) modinit->var)->obj = obj; |
<> | 149:156823d33999 | 1014 | // With our own async vector, tx/rx handlers can be different. |
<> | 149:156823d33999 | 1015 | obj->serial.vec = ((struct nu_uart_var *) modinit->var)->vec_async; |
<> | 149:156823d33999 | 1016 | obj->serial.irq_handler_rx_async = (void (*) (void)) handler; |
<> | 149:156823d33999 | 1017 | serial_irq_set(obj, RxIrq, enable); |
<> | 149:156823d33999 | 1018 | } |
<> | 149:156823d33999 | 1019 | |
<> | 149:156823d33999 | 1020 | static void serial_check_dma_usage(DMAUsage *dma_usage, int *dma_ch) |
<> | 149:156823d33999 | 1021 | { |
<> | 149:156823d33999 | 1022 | if (*dma_usage != DMA_USAGE_NEVER) { |
<> | 149:156823d33999 | 1023 | if (*dma_ch == DMA_ERROR_OUT_OF_CHANNELS) { |
<> | 149:156823d33999 | 1024 | *dma_ch = dma_channel_allocate(DMA_CAP_NONE); |
<> | 149:156823d33999 | 1025 | } |
<> | 149:156823d33999 | 1026 | if (*dma_ch == DMA_ERROR_OUT_OF_CHANNELS) { |
<> | 149:156823d33999 | 1027 | *dma_usage = DMA_USAGE_NEVER; |
<> | 149:156823d33999 | 1028 | } |
<> | 149:156823d33999 | 1029 | } |
<> | 149:156823d33999 | 1030 | else { |
<> | 149:156823d33999 | 1031 | dma_channel_free(*dma_ch); |
<> | 149:156823d33999 | 1032 | *dma_ch = DMA_ERROR_OUT_OF_CHANNELS; |
<> | 149:156823d33999 | 1033 | } |
<> | 149:156823d33999 | 1034 | } |
<> | 149:156823d33999 | 1035 | |
<> | 149:156823d33999 | 1036 | static int serial_is_irq_en(serial_t *obj, SerialIrq irq) |
<> | 149:156823d33999 | 1037 | { |
<> | 149:156823d33999 | 1038 | int inten_msk = 0; |
<> | 149:156823d33999 | 1039 | |
<> | 149:156823d33999 | 1040 | switch (irq) { |
<> | 149:156823d33999 | 1041 | case RxIrq: |
<> | 149:156823d33999 | 1042 | inten_msk = obj->serial.inten_msk & (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk); |
<> | 149:156823d33999 | 1043 | break; |
<> | 149:156823d33999 | 1044 | case TxIrq: |
<> | 149:156823d33999 | 1045 | inten_msk = obj->serial.inten_msk & UART_INTEN_THREIEN_Msk; |
<> | 149:156823d33999 | 1046 | break; |
<> | 149:156823d33999 | 1047 | } |
<> | 149:156823d33999 | 1048 | |
<> | 149:156823d33999 | 1049 | return !! inten_msk; |
<> | 149:156823d33999 | 1050 | } |
<> | 149:156823d33999 | 1051 | |
<> | 149:156823d33999 | 1052 | #endif // #if DEVICE_SERIAL_ASYNCH |
<> | 149:156823d33999 | 1053 | #endif // #if DEVICE_SERIAL |