John Karatka / mbed

mbed

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targets/TARGET_ONSEMI/TARGET_NCS36510/rfAna.c@150:02e0a0aed4ec, 2016-11-08 (annotated)

Committer:
<>
Date:
Tue Nov 08 17:45:16 2016 +0000
Revision:
150:02e0a0aed4ec
Parent:
149:156823d33999 
This updates the lib to the mbed lib v129

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 149:156823d33999 1 /**
<> 149:156823d33999 2 ******************************************************************************
<> 149:156823d33999 3 * @file rfAna.c
<> 149:156823d33999 4 * @brief Implementation of rfAna hw module functions
<> 149:156823d33999 5 * @internal
<> 149:156823d33999 6 * @author ON Semiconductor
<> 149:156823d33999 7 * $Rev: 3445 $
<> 149:156823d33999 8 * $Date: 2015-06-22 13:51:24 +0530 (Mon, 22 Jun 2015) $
<> 149:156823d33999 9 ******************************************************************************
<> 149:156823d33999 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
<> 149:156823d33999 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
<> 149:156823d33999 12 * under limited terms and conditions. The terms and conditions pertaining to the software
<> 149:156823d33999 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
<> 149:156823d33999 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
<> 149:156823d33999 15 * if applicable the software license agreement. Do not use this software and/or
<> 149:156823d33999 16 * documentation unless you have carefully read and you agree to the limited terms and
<> 149:156823d33999 17 * conditions. By using this software and/or documentation, you agree to the limited
<> 149:156823d33999 18 * terms and conditions.
<> 149:156823d33999 19 *
<> 149:156823d33999 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
<> 149:156823d33999 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
<> 149:156823d33999 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
<> 149:156823d33999 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
<> 149:156823d33999 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
<> 149:156823d33999 25 * @endinternal
<> 149:156823d33999 26 *
<> 149:156823d33999 27 * @ingroup rfAna
<> 149:156823d33999 28 *
<> 149:156823d33999 29 * @details
<> 149:156823d33999 30 *
<> 149:156823d33999 31 * <h1> Reference document(s) </h1>
<> 149:156823d33999 32 */
<> 149:156823d33999 33
<> 149:156823d33999 34 /*************************************************************************************************
<> 149:156823d33999 35 * *
<> 149:156823d33999 36 * Header files *
<> 149:156823d33999 37 * *
<> 149:156823d33999 38 *************************************************************************************************/
<> 149:156823d33999 39
<> 149:156823d33999 40 #include "memory_map.h"
<> 149:156823d33999 41 #include "rfAna.h"
<> 149:156823d33999 42 #include "clock.h"
<> 149:156823d33999 43
<> 149:156823d33999 44 /*************************************************************************************************
<> 149:156823d33999 45 * *
<> 149:156823d33999 46 * Global variables *
<> 149:156823d33999 47 * *
<> 149:156823d33999 48 *************************************************************************************************/
<> 149:156823d33999 49
<> 149:156823d33999 50 /** Rf channel and tx power lookup tables (constant)
<> 149:156823d33999 51 * @details
<> 149:156823d33999 52 *
<> 149:156823d33999 53 * The rf channel table is used to program internal hardware register for different 15.4 rf channels.
<> 149:156823d33999 54 * It has 16 entries corresponding to 16 15.4 channels.
<> 149:156823d33999 55 * Entry 1 <-> Channel 11
<> 149:156823d33999 56 * ...
<> 149:156823d33999 57 * Entry 16 <-> Channel 26
<> 149:156823d33999 58 *
<> 149:156823d33999 59 * Each entry is compound of 4 items.
<> 149:156823d33999 60 * Item 0: Rx Frequency integer divide portion
<> 149:156823d33999 61 * Item 1: Rx Frequency fractional divide portion
<> 149:156823d33999 62 * Item 2: Tx Frequency integer divide portion
<> 149:156823d33999 63 * Item 3: Tx Frequency fractional divide portion
<> 149:156823d33999 64 *
<> 149:156823d33999 65 * The tx power table is used to program internal hardware register for different 15.4 tx power levels.
<> 149:156823d33999 66 * It has 43 entries corresponding to tx power levels from -32dBm to +10dBm.
<> 149:156823d33999 67 * Entry 1 <-> -32dB
<> 149:156823d33999 68 * Entry 2 <-> -31dB
<> 149:156823d33999 69 * ...
<> 149:156823d33999 70 * Entry 2 <-> 9dB
<> 149:156823d33999 71 * Entry 43 <-> +10dB
<> 149:156823d33999 72 *
<> 149:156823d33999 73 * Each entry is compound of 1 byte.
<> 149:156823d33999 74 */
<> 149:156823d33999 75
<> 149:156823d33999 76 // RR: Making high side injection changes to RevD
<> 149:156823d33999 77
<> 149:156823d33999 78 /** This rf LUT is built for high side injection, using low side injection
<> 149:156823d33999 79 * would requiere to change this LUT. */
<> 149:156823d33999 80 const uint32_t rfLut[16][4] = {{0x50,0x00D4A7,0x4B,0x00A000},
<> 149:156823d33999 81 {0x50,0x017F52,0x4B,0x014001},
<> 149:156823d33999 82 {0x51,0xFE29FB,0x4B,0x01E001},
<> 149:156823d33999 83 {0x51,0xFED4A6,0x4C,0xFE7FFF},
<> 149:156823d33999 84 {0x51,0xFF7F51,0x4C,0xFF1FFF},
<> 149:156823d33999 85 {0x51,0x0029FC,0x4C,0xFFC000},
<> 149:156823d33999 86 {0x51,0x00D4A7,0x4C,0x006000},
<> 149:156823d33999 87 {0x51,0x017F52,0x4C,0x010001},
<> 149:156823d33999 88 {0x52,0xFE29FB,0x4C,0x01A001},
<> 149:156823d33999 89 {0x52,0xFED4A6,0x4D,0xFE3FFF},
<> 149:156823d33999 90 {0x52,0xFF7F51,0x4D,0xFEDFFF},
<> 149:156823d33999 91 {0x52,0x0029FC,0x4D,0xFF8000},
<> 149:156823d33999 92 {0x52,0x00D4A7,0x4D,0x002000},
<> 149:156823d33999 93 {0x52,0x017F52,0x4D,0x00C001},
<> 149:156823d33999 94 {0x53,0xFE29FB,0x4D,0x016001},
<> 149:156823d33999 95 {0x53,0xFED4A6,0x4E,0xFDFFFE}
<> 149:156823d33999 96 };
<> 149:156823d33999 97
<> 149:156823d33999 98 const uint8_t txPowerLut[43] = {0,0,0, // -32dBm to -30dBm
<> 149:156823d33999 99 0,0,0,0,0,0,0,0,0,0, // -29dBm to -20dBm
<> 149:156823d33999 100 0,0,0,0,0,0,0,0,1,2, // -19dBm to -10dBm
<> 149:156823d33999 101 3,4,5,6,7,8,9,10,11,12, // -9dBm to 0dBm
<> 149:156823d33999 102 13,14,15,16,17,18,19,20,20,20
<> 149:156823d33999 103 }; // +1dBm to +10 dBm
<> 149:156823d33999 104
<> 149:156823d33999 105 /*************************************************************************************************
<> 149:156823d33999 106 * *
<> 149:156823d33999 107 * Functions *
<> 149:156823d33999 108 * *
<> 149:156823d33999 109 *************************************************************************************************/
<> 149:156823d33999 110
<> 149:156823d33999 111 void fRfAnaInit()
<> 149:156823d33999 112 {
<> 149:156823d33999 113 // Enable rfana clock
<> 149:156823d33999 114 CLOCK_ENABLE(CLOCK_RFANA);
<> 149:156823d33999 115
<> 149:156823d33999 116 // Set PLL timing
<> 149:156823d33999 117 RFANAREG->PLL_TIMING.BITS.PLL_RESET_TIME = 0x1E; // 30us
<> 149:156823d33999 118 RFANAREG->PLL_TIMING.BITS.PLL_LOCK_TIME = 0x2F; // 47us
<> 149:156823d33999 119
<> 149:156823d33999 120 // Set other parameters
<> 149:156823d33999 121 RFANAREG->RX_CONTROL.BITS.LNA_GAIN_MODE = 0x1; // High Gain mode
<> 149:156823d33999 122 RFANAREG->RX_CONTROL.BITS.ADC_DITHER_MODE = 0x0; // Dither mode disabled
<> 149:156823d33999 123 }
<> 149:156823d33999 124
<> 149:156823d33999 125 boolean fRfAnaIoctl (uint32_t request, void *argument)
<> 149:156823d33999 126 {
<> 149:156823d33999 127 uint8_t channel, txPower;
<> 149:156823d33999 128
<> 149:156823d33999 129 // Enable rfana clock (in case fRfAnaIoctl is used before call of fRfAnaInit)
<> 149:156823d33999 130 CLOCK_ENABLE(CLOCK_RFANA);
<> 149:156823d33999 131
<> 149:156823d33999 132 switch(request) {
<> 149:156823d33999 133 case SET_RF_CHANNEL:
<> 149:156823d33999 134 channel = *(uint8_t*)argument;
<> 149:156823d33999 135
<> 149:156823d33999 136 // Set tx/rx integer/fractional divide portions
<> 149:156823d33999 137 RFANAREG->TX_LO_CONTROL.BITS.FRACT_WORD = rfLut[channel - 11][3];
<> 149:156823d33999 138 RFANAREG->TX_LO_CONTROL.BITS.INT_WORD = rfLut[channel - 11][2];
<> 149:156823d33999 139 RFANAREG->RX_LO_CONTROL.BITS.FRACT_WORD = rfLut[channel - 11][1];
<> 149:156823d33999 140 RFANAREG->RX_LO_CONTROL.BITS.INT_WORD = rfLut[channel - 11][0];
<> 149:156823d33999 141
<> 149:156823d33999 142 // Set tx/rx vco trims
<> 149:156823d33999 143 /** REVD is requiering to adjust tx/rx vco trims each time a new 15.4 channel is used, in revB it is done
<> 149:156823d33999 144 * from trims stored in dedicated registers available in digital.*/
<> 149:156823d33999 145 if (channel < 19) {
<> 149:156823d33999 146 RFANATRIMREG->PLL_TRIM.BITS.TX_VCO_TRIM = (RFANATRIMREG->TX_VCO_TRIM_LUT1) >> ((channel - 11) * 4);
<> 149:156823d33999 147 RFANATRIMREG->PLL_TRIM.BITS.RX_VCO_TRIM = (RFANATRIMREG->RX_VCO_TRIM_LUT1) >> ((channel - 11) * 4);
<> 149:156823d33999 148 } else {
<> 149:156823d33999 149 RFANATRIMREG->PLL_TRIM.BITS.TX_VCO_TRIM = (RFANATRIMREG->TX_VCO_TRIM_LUT2) >> ((channel - 19) * 4);
<> 149:156823d33999 150 RFANATRIMREG->PLL_TRIM.BITS.RX_VCO_TRIM = (RFANATRIMREG->RX_VCO_TRIM_LUT2) >> ((channel - 19) * 4);
<> 149:156823d33999 151 }
<> 149:156823d33999 152 break;
<> 149:156823d33999 153 case SET_TX_POWER:
<> 149:156823d33999 154 txPower = *(uint8_t*)argument;
<> 149:156823d33999 155
<> 149:156823d33999 156 // Set tx power register
<> 149:156823d33999 157 if ((txPower & 0x20) == 0) {
<> 149:156823d33999 158 RFANAREG->TX_POWER = (txPowerLut[txPower + 32] & 0xFF);
<> 149:156823d33999 159 } else {
<> 149:156823d33999 160 RFANAREG->TX_POWER = (txPowerLut[txPower - 32] & 0xFF);
<> 149:156823d33999 161 }
<> 149:156823d33999 162
<> 149:156823d33999 163 break;
<> 149:156823d33999 164 default:
<> 149:156823d33999 165 return False;
<> 149:156823d33999 166 }
<> 149:156823d33999 167 return True;
<> 149:156823d33999 168 }