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rfal_rf.cpp@0:75fc82583a41, 2019-11-14 (annotated)

Committer:: DiegoOstuni
Date:: Thu Nov 14 14:34:50 2019 +0000
Revision:: 0:75fc82583a41

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DiegoOstuni	0:75fc82583a41	1
DiegoOstuni	0:75fc82583a41	2	/******************************************************************************
DiegoOstuni	0:75fc82583a41	3	* @attention
DiegoOstuni	0:75fc82583a41	4	*
DiegoOstuni	0:75fc82583a41	5	* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
DiegoOstuni	0:75fc82583a41	6	*
DiegoOstuni	0:75fc82583a41	7	* Licensed under ST MYLIBERTY SOFTWARE LICENSE AGREEMENT (the "License");
DiegoOstuni	0:75fc82583a41	8	* You may not use this file except in compliance with the License.
DiegoOstuni	0:75fc82583a41	9	* You may obtain a copy of the License at:
DiegoOstuni	0:75fc82583a41	10	*
DiegoOstuni	0:75fc82583a41	11	* http://www.st.com/myliberty
DiegoOstuni	0:75fc82583a41	12	*
DiegoOstuni	0:75fc82583a41	13	* Unless required by applicable law or agreed to in writing, software
DiegoOstuni	0:75fc82583a41	14	* distributed under the License is distributed on an "AS IS" BASIS,
DiegoOstuni	0:75fc82583a41	15	* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied,
DiegoOstuni	0:75fc82583a41	16	* AND SPECIFICALLY DISCLAIMING THE IMPLIED WARRANTIES OF MERCHANTABILITY,
DiegoOstuni	0:75fc82583a41	17	* FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT.
DiegoOstuni	0:75fc82583a41	18	* See the License for the specific language governing permissions and
DiegoOstuni	0:75fc82583a41	19	* limitations under the License.
DiegoOstuni	0:75fc82583a41	20	*
DiegoOstuni	0:75fc82583a41	21	******************************************************************************/
DiegoOstuni	0:75fc82583a41	22
DiegoOstuni	0:75fc82583a41	23
DiegoOstuni	0:75fc82583a41	24	/*
DiegoOstuni	0:75fc82583a41	25	* PROJECT: ST25R3911 firmware
DiegoOstuni	0:75fc82583a41	26	* $Revision: $
DiegoOstuni	0:75fc82583a41	27	* LANGUAGE: ISO C99
DiegoOstuni	0:75fc82583a41	28	*/
DiegoOstuni	0:75fc82583a41	29
DiegoOstuni	0:75fc82583a41	30	/*! \file
DiegoOstuni	0:75fc82583a41	31	*
DiegoOstuni	0:75fc82583a41	32	* \author Gustavo Patricio
DiegoOstuni	0:75fc82583a41	33	*
DiegoOstuni	0:75fc82583a41	34	* \brief RF Abstraction Layer (RFAL)
DiegoOstuni	0:75fc82583a41	35	*
DiegoOstuni	0:75fc82583a41	36	* RFAL implementation for ST25R3911
DiegoOstuni	0:75fc82583a41	37	*/
DiegoOstuni	0:75fc82583a41	38
DiegoOstuni	0:75fc82583a41	39
DiegoOstuni	0:75fc82583a41	40	/*
DiegoOstuni	0:75fc82583a41	41	******************************************************************************
DiegoOstuni	0:75fc82583a41	42	* INCLUDES
DiegoOstuni	0:75fc82583a41	43	******************************************************************************
DiegoOstuni	0:75fc82583a41	44	*/
DiegoOstuni	0:75fc82583a41	45
DiegoOstuni	0:75fc82583a41	46
DiegoOstuni	0:75fc82583a41	47	#include "rfal_rf.h"
DiegoOstuni	0:75fc82583a41	48
DiegoOstuni	0:75fc82583a41	49	#include <rfal_rf.h>
DiegoOstuni	0:75fc82583a41	50	#include "utils.h"
DiegoOstuni	0:75fc82583a41	51	#include "ST25R3911.h"
DiegoOstuni	0:75fc82583a41	52	#include "st25r3911_com.h"
DiegoOstuni	0:75fc82583a41	53	#include "st25r3911_interrupt.h"
DiegoOstuni	0:75fc82583a41	54	#include "rfal_AnalogConfig.h"
DiegoOstuni	0:75fc82583a41	55	#include "rfal_iso15693_2.h"
DiegoOstuni	0:75fc82583a41	56	#include "rfal_chip.h"
DiegoOstuni	0:75fc82583a41	57	#include "platform1.h"
DiegoOstuni	0:75fc82583a41	58	#include <stdint.h>
DiegoOstuni	0:75fc82583a41	59
DiegoOstuni	0:75fc82583a41	60	/*
DiegoOstuni	0:75fc82583a41	61	******************************************************************************
DiegoOstuni	0:75fc82583a41	62	* GLOBAL TYPES
DiegoOstuni	0:75fc82583a41	63	******************************************************************************
DiegoOstuni	0:75fc82583a41	64	*/
DiegoOstuni	0:75fc82583a41	65
DiegoOstuni	0:75fc82583a41	66
DiegoOstuni	0:75fc82583a41	67
DiegoOstuni	0:75fc82583a41	68	/! Struct that holds all involved on a Transceive including the context passed by the caller /
DiegoOstuni	0:75fc82583a41	69	typedef struct{
DiegoOstuni	0:75fc82583a41	70	rfalTransceiveState state; /!< Current transceive state /
DiegoOstuni	0:75fc82583a41	71	rfalTransceiveState lastState; /!< Last transceive state (debug purposes) /
DiegoOstuni	0:75fc82583a41	72	ReturnCode status; /!< Current status/error of the transceive /
DiegoOstuni	0:75fc82583a41	73	bool rxse; /!< Flag indicating if RXE was received with RXS /
DiegoOstuni	0:75fc82583a41	74
DiegoOstuni	0:75fc82583a41	75	rfalTransceiveContext ctx; /!< The transceive context given by the caller /
DiegoOstuni	0:75fc82583a41	76	} rfalTxRx;
DiegoOstuni	0:75fc82583a41	77
DiegoOstuni	0:75fc82583a41	78
DiegoOstuni	0:75fc82583a41	79	/! Struct that holds all context for the Listen Mode /
DiegoOstuni	0:75fc82583a41	80	typedef struct{
DiegoOstuni	0:75fc82583a41	81	rfalLmState state; /!< Current Listen Mode state /
DiegoOstuni	0:75fc82583a41	82	rfalBitRate brDetected; /!< Last bit rate detected /
DiegoOstuni	0:75fc82583a41	83
DiegoOstuni	0:75fc82583a41	84	uint8_t* rxBuf; /!< Location to store incoming data in Listen Mode /
DiegoOstuni	0:75fc82583a41	85	uint16_t rxBufLen; /!< Length of rxBuf /
DiegoOstuni	0:75fc82583a41	86	uint16_t* rxLen; /!< Pointer to write the data length placed into rxBuf /
DiegoOstuni	0:75fc82583a41	87	bool dataFlag; /!< Listen Mode current Data Flag /
DiegoOstuni	0:75fc82583a41	88	} rfalLm;
DiegoOstuni	0:75fc82583a41	89
DiegoOstuni	0:75fc82583a41	90
DiegoOstuni	0:75fc82583a41	91	/! Struct that holds all context for the Wake-Up Mode /
DiegoOstuni	0:75fc82583a41	92	typedef struct{
DiegoOstuni	0:75fc82583a41	93	rfalWumState state; /!< Current Wake-Up Mode state /
DiegoOstuni	0:75fc82583a41	94	st25r3911WakeUpConfig cfg; /!< Current Wake-Up Mode context /
DiegoOstuni	0:75fc82583a41	95	} rfalWum;
DiegoOstuni	0:75fc82583a41	96
DiegoOstuni	0:75fc82583a41	97
DiegoOstuni	0:75fc82583a41	98	/! Struct that holds the timings GT and FDTs /
DiegoOstuni	0:75fc82583a41	99	typedef struct{
DiegoOstuni	0:75fc82583a41	100	uint32_t GT; /!< GT in 1/fc /
DiegoOstuni	0:75fc82583a41	101	uint32_t FDTListen; /!< FDTListen in 1/fc /
DiegoOstuni	0:75fc82583a41	102	uint32_t FDTPoll; /!< FDTPoll in 1/fc /
DiegoOstuni	0:75fc82583a41	103	} rfalTimings;
DiegoOstuni	0:75fc82583a41	104
DiegoOstuni	0:75fc82583a41	105
DiegoOstuni	0:75fc82583a41	106	/! Struct that holds the software timers /
DiegoOstuni	0:75fc82583a41	107	typedef struct{
DiegoOstuni	0:75fc82583a41	108	uint32_t GT; /!< RFAL's GT timer /
DiegoOstuni	0:75fc82583a41	109	uint32_t FWT; /!< FWT/RWT timer for Active P2P/
DiegoOstuni	0:75fc82583a41	110	uint32_t RXE; /!< Timer between RXS and RXE /
DiegoOstuni	0:75fc82583a41	111	} rfalTimers;
DiegoOstuni	0:75fc82583a41	112
DiegoOstuni	0:75fc82583a41	113
DiegoOstuni	0:75fc82583a41	114	/! Struct that holds the RFAL's callbacks /
DiegoOstuni	0:75fc82583a41	115	typedef struct{
DiegoOstuni	0:75fc82583a41	116	rfalPreTxRxCallback preTxRx; /!< RFAL's Pre TxRx callback /
DiegoOstuni	0:75fc82583a41	117	rfalPostTxRxCallback postTxRx; /!< RFAL's Post TxRx callback /
DiegoOstuni	0:75fc82583a41	118	} rfalCallbacks;
DiegoOstuni	0:75fc82583a41	119
DiegoOstuni	0:75fc82583a41	120
DiegoOstuni	0:75fc82583a41	121	/! Struct that holds counters to control the FIFO on Tx and Rx /
DiegoOstuni	0:75fc82583a41	122	typedef struct{
DiegoOstuni	0:75fc82583a41	123	uint16_t expWL; /!< The amount of bytes expected to be Tx when a WL interrupt occours /
DiegoOstuni	0:75fc82583a41	124	uint16_t bytesTotal; /!< Total bytes to be transmitted OR the total bytes received /
DiegoOstuni	0:75fc82583a41	125	uint16_t bytesWritten;/!< Amount of bytes already written on FIFO (Tx) OR read (RX) from FIFO and written on rxBuffer/
DiegoOstuni	0:75fc82583a41	126	uint8_t status[ST25R3911_FIFO_STATUS_LEN]; /!< FIFO Status Registers /
DiegoOstuni	0:75fc82583a41	127	} rfalFIFO;
DiegoOstuni	0:75fc82583a41	128
DiegoOstuni	0:75fc82583a41	129
DiegoOstuni	0:75fc82583a41	130	/! Struct that holds RFAL's configuration settings /
DiegoOstuni	0:75fc82583a41	131	typedef struct{
DiegoOstuni	0:75fc82583a41	132	uint8_t obsvModeTx; /!< RFAL's config of the ST25R3911's observation mode while Tx /
DiegoOstuni	0:75fc82583a41	133	uint8_t obsvModeRx; /!< RFAL's config of the ST25R3911's observation mode while Rx /
DiegoOstuni	0:75fc82583a41	134	rfalEHandling eHandling; /!< RFAL's error handling config/mode /
DiegoOstuni	0:75fc82583a41	135	} rfalConfigs;
DiegoOstuni	0:75fc82583a41	136
DiegoOstuni	0:75fc82583a41	137
DiegoOstuni	0:75fc82583a41	138	/! Struct that holds NFC-F data - Used only inside rfalFelicaPoll() (static to avoid adding it into stack) /
DiegoOstuni	0:75fc82583a41	139	typedef struct{
DiegoOstuni	0:75fc82583a41	140	rfalFeliCaPollRes pollResponses[RFAL_FELICA_POLL_MAX_SLOTS]; /* FeliCa Poll response container for 16 slots */
DiegoOstuni	0:75fc82583a41	141	} rfalNfcfWorkingData;
DiegoOstuni	0:75fc82583a41	142
DiegoOstuni	0:75fc82583a41	143
DiegoOstuni	0:75fc82583a41	144	/*! Struct that holds NFC-V current context
DiegoOstuni	0:75fc82583a41	145	*
DiegoOstuni	0:75fc82583a41	146	* 96 bytes is FIFO size of ST25R3911, codingBuffer has to be big enough for coping with maximum response size (Manchester coded)
DiegoOstuni	0:75fc82583a41	147	* - current implementation expects it be written in one bulk into FIFO
DiegoOstuni	0:75fc82583a41	148	* - needs to be above FIFO water level of ST25R3911 (64)
DiegoOstuni	0:75fc82583a41	149	* - 65 is actually 1 byte too much, but ~75us in 1of256 another byte is already gone
DiegoOstuni	0:75fc82583a41	150	*
DiegoOstuni	0:75fc82583a41	151	* - inventory requests responses: 14 bytes
DiegoOstuni	0:75fc82583a41	152	* - Max read single block responses: 32 bytes
DiegoOstuni	0:75fc82583a41	153	* - Read multiple block responses: variable
DiegoOstuni	0:75fc82583a41	154	*
DiegoOstuni	0:75fc82583a41	155	* ISO15693 frame: SOF + Flags + Data + CRC + EOF
DiegoOstuni	0:75fc82583a41	156	*/
DiegoOstuni	0:75fc82583a41	157	typedef struct{
DiegoOstuni	0:75fc82583a41	158	uint8_t codingBuffer[((2 + 255 + 3)2)];/!< Coding buffer, length MUST be above 64: [65; ...] */
DiegoOstuni	0:75fc82583a41	159	uint16_t nfcvOffset; /!< Offset needed for ISO15693 coding function /
DiegoOstuni	0:75fc82583a41	160	rfalTransceiveContext origCtx; /!< Context provided by user /
DiegoOstuni	0:75fc82583a41	161	uint16_t ignoreBits; /!< Number of bits at the beginning of a frame to be ignored when decoding /
DiegoOstuni	0:75fc82583a41	162	} rfalNfcvWorkingData;
DiegoOstuni	0:75fc82583a41	163
DiegoOstuni	0:75fc82583a41	164
DiegoOstuni	0:75fc82583a41	165	/! RFAL instance /
DiegoOstuni	0:75fc82583a41	166	typedef struct{
DiegoOstuni	0:75fc82583a41	167	rfalState state; /!< RFAL's current state /
DiegoOstuni	0:75fc82583a41	168	rfalMode mode; /!< RFAL's current mode /
DiegoOstuni	0:75fc82583a41	169	rfalBitRate txBR; /!< RFAL's current Tx Bit Rate /
DiegoOstuni	0:75fc82583a41	170	rfalBitRate rxBR; /!< RFAL's current Rx Bit Rate /
DiegoOstuni	0:75fc82583a41	171	bool field; /!< Current field state (On / Off) /
DiegoOstuni	0:75fc82583a41	172
DiegoOstuni	0:75fc82583a41	173	rfalConfigs conf; /!< RFAL's configuration settings /
DiegoOstuni	0:75fc82583a41	174	rfalTimings timings; /!< RFAL's timing setting /
DiegoOstuni	0:75fc82583a41	175	rfalTxRx TxRx; /!< RFAL's transceive management /
DiegoOstuni	0:75fc82583a41	176	rfalLm Lm; /!< RFAL's listen mode management /
DiegoOstuni	0:75fc82583a41	177	rfalWum wum; /!< RFAL's Wake-Up mode management /
DiegoOstuni	0:75fc82583a41	178
DiegoOstuni	0:75fc82583a41	179	rfalFIFO fifo; /!< RFAL's FIFO management /
DiegoOstuni	0:75fc82583a41	180	rfalTimers tmr; /!< RFAL's Software timers /
DiegoOstuni	0:75fc82583a41	181	rfalCallbacks callbacks; /!< RFAL's callbacks /
DiegoOstuni	0:75fc82583a41	182
DiegoOstuni	0:75fc82583a41	183	#if RFAL_FEATURE_NFCF
DiegoOstuni	0:75fc82583a41	184	rfalNfcfWorkingData nfcfData; /!< RFAL's working data when supporting NFC-F /
DiegoOstuni	0:75fc82583a41	185	#endif /* RFAL_FEATURE_NFCF */
DiegoOstuni	0:75fc82583a41	186
DiegoOstuni	0:75fc82583a41	187	#if RFAL_FEATURE_NFCV
DiegoOstuni	0:75fc82583a41	188	rfalNfcvWorkingData nfcvData; /!< RFAL's working data when supporting NFC-V /
DiegoOstuni	0:75fc82583a41	189	#endif /* RFAL_FEATURE_NFCV */
DiegoOstuni	0:75fc82583a41	190
DiegoOstuni	0:75fc82583a41	191	} rfal;
DiegoOstuni	0:75fc82583a41	192
DiegoOstuni	0:75fc82583a41	193
DiegoOstuni	0:75fc82583a41	194
DiegoOstuni	0:75fc82583a41	195	/! Felica's command set /
DiegoOstuni	0:75fc82583a41	196	typedef enum
DiegoOstuni	0:75fc82583a41	197	{
DiegoOstuni	0:75fc82583a41	198	FELICA_CMD_POLLING = 0x00, /!< Felica Poll/REQC command (aka SENSF_REQ) to identify a card /
DiegoOstuni	0:75fc82583a41	199	FELICA_CMD_POLLING_RES = 0x01, /!< Felica Poll/REQC command (aka SENSF_RES) response /
DiegoOstuni	0:75fc82583a41	200	FELICA_CMD_REQUEST_SERVICE = 0x02, /!< verify the existence of Area and Service /
DiegoOstuni	0:75fc82583a41	201	FELICA_CMD_REQUEST_RESPONSE = 0x04, /!< verify the existence of a card /
DiegoOstuni	0:75fc82583a41	202	FELICA_CMD_READ_WITHOUT_ENCRYPTION = 0x06, /!< read Block Data from a Service that requires no authentication /
DiegoOstuni	0:75fc82583a41	203	FELICA_CMD_WRITE_WITHOUT_ENCRYPTION = 0x08, /!< write Block Data to a Service that requires no authentication /
DiegoOstuni	0:75fc82583a41	204	FELICA_CMD_REQUEST_SYSTEM_CODE = 0x0c, /!< acquire the System Code registered to a card /
DiegoOstuni	0:75fc82583a41	205	FELICA_CMD_AUTHENTICATION1 = 0x10, /!< authenticate a card /
DiegoOstuni	0:75fc82583a41	206	FELICA_CMD_AUTHENTICATION2 = 0x12, /!< allow a card to authenticate a Reader/Writer /
DiegoOstuni	0:75fc82583a41	207	FELICA_CMD_READ = 0x14, /!< read Block Data from a Service that requires authentication /
DiegoOstuni	0:75fc82583a41	208	FELICA_CMD_WRITE = 0x16, /!< write Block Data to a Service that requires authentication /
DiegoOstuni	0:75fc82583a41	209	}t_rfalFeliCaCmd;
DiegoOstuni	0:75fc82583a41	210
DiegoOstuni	0:75fc82583a41	211	/*
DiegoOstuni	0:75fc82583a41	212	******************************************************************************
DiegoOstuni	0:75fc82583a41	213	* GLOBAL DEFINES
DiegoOstuni	0:75fc82583a41	214	******************************************************************************
DiegoOstuni	0:75fc82583a41	215	*/
DiegoOstuni	0:75fc82583a41	216
DiegoOstuni	0:75fc82583a41	217	#define RFAL_TIMING_NONE 0x00 /!< Timing disable \| Don't apply /
DiegoOstuni	0:75fc82583a41	218
DiegoOstuni	0:75fc82583a41	219	#define RFAL_FIFO_IN_LT_32 32 /!< Number of bytes in the FIFO when WL interrupt occurs while Tx ( fifo_lt: 0 ) /
DiegoOstuni	0:75fc82583a41	220	#define RFAL_FIFO_IN_LT_16 16 /!< Number of bytes in the FIFO when WL interrupt occurs while Tx ( fifo_lt: 1 ) /
DiegoOstuni	0:75fc82583a41	221
DiegoOstuni	0:75fc82583a41	222	#define RFAL_FIFO_OUT_LT_32 (ST25R3911_FIFO_DEPTH - RFAL_FIFO_IN_LT_32) /!< Number of bytes sent/out of the FIFO when WL interrupt occurs while Tx ( fifo_lt: 0 ) /
DiegoOstuni	0:75fc82583a41	223	#define RFAL_FIFO_OUT_LT_16 (ST25R3911_FIFO_DEPTH - RFAL_FIFO_IN_LT_16) /!< Number of bytes sent/out of the FIFO when WL interrupt occurs while Tx ( fifo_lt: 1 ) /
DiegoOstuni	0:75fc82583a41	224
DiegoOstuni	0:75fc82583a41	225	#define RFAL_FIFO_STATUS_REG1 0 /!< Location of FIFO status register 1 in local copy /
DiegoOstuni	0:75fc82583a41	226	#define RFAL_FIFO_STATUS_REG2 1 /!< Location of FIFO status register 2 in local copy /
DiegoOstuni	0:75fc82583a41	227	#define RFAL_FIFO_STATUS_INVALID 0xFF /!< Value indicating that the local FIFO status in invalid\|cleared /
DiegoOstuni	0:75fc82583a41	228
DiegoOstuni	0:75fc82583a41	229	#define RFAL_ST25R3911_GPT_MAX_1FC rfalConv8fcTo1fc( 0xFFFF ) /!< Max GPT steps in 1fc (0xFFFF steps of 8/fc => 0xFFFF 590ns = 38,7ms) */
DiegoOstuni	0:75fc82583a41	230	#define RFAL_ST25R3911_NRT_MAX_1FC rfalConv4096fcTo1fc( 0xFFFF ) /!< Max NRT steps in 1fc (0xFFFF steps of 4096/fc => 0xFFFF 302us = 19.8s ) */
DiegoOstuni	0:75fc82583a41	231	#define RFAL_ST25R3911_NRT_DISABLED 0 /!< NRT Disabled: All 0 No-response timer is not started, wait forever /
DiegoOstuni	0:75fc82583a41	232	#define RFAL_ST25R3911_MRT_MAX_1FC rfalConv64fcTo1fc( 0x00FF ) /!< Max MRT steps in 1fc (0x00FF steps of 64/fc => 0x00FF 4.72us = 1.2ms ) */
DiegoOstuni	0:75fc82583a41	233	#define RFAL_ST25R3911_MRT_MIN_1FC rfalConv64fcTo1fc( 0x0004 ) /!< Min MRT steps in 1fc ( 0<=mrt<=4 ; 4 (64/fc) => 0x0004 4.72us = 18.88us ) */
DiegoOstuni	0:75fc82583a41	234	#define RFAL_ST25R3911_GT_MAX_1FC rfalConvMsTo1fc( 5000 ) /!< Max GT value allowed in 1/fc /
DiegoOstuni	0:75fc82583a41	235	#define RFAL_ST25R3911_GT_MIN_1FC rfalConvMsTo1fc(RFAL_ST25R3911_SW_TMR_MIN_1MS)/!< Min GT value allowed in 1/fc /
DiegoOstuni	0:75fc82583a41	236	#define RFAL_ST25R3911_SW_TMR_MIN_1MS 1 /!< Min value of a SW timer in ms /
DiegoOstuni	0:75fc82583a41	237
DiegoOstuni	0:75fc82583a41	238	#define RFAL_OBSMODE_DISABLE 0x00 /!< Observation Mode disabled /
DiegoOstuni	0:75fc82583a41	239
DiegoOstuni	0:75fc82583a41	240	#define RFAL_NFC_RX_INCOMPLETE_LEN 1 /!< Threshold value where incoming rx may be considered as incomplete in NFC /
DiegoOstuni	0:75fc82583a41	241	#define RFAL_EMVCO_RX_MAXLEN 4 /!< Maximum value where EMVCo to apply special error handling /
DiegoOstuni	0:75fc82583a41	242	#define RFAL_EMVCO_RX_MINLEN 2 /!< Minimum value where EMVCo to apply special error handling /
DiegoOstuni	0:75fc82583a41	243
DiegoOstuni	0:75fc82583a41	244	#define RFAL_NORXE_TOUT 10 /!< Timeout to be used on a potential missing RXE - Silicon ST25R3911B Errata #1.1 /
DiegoOstuni	0:75fc82583a41	245
DiegoOstuni	0:75fc82583a41	246	#define RFAL_ISO14443A_SDD_RES_LEN 5 /!< SDD_RES \| Anticollision (UID CLn) length - rfalNfcaSddRes /
DiegoOstuni	0:75fc82583a41	247
DiegoOstuni	0:75fc82583a41	248	#define RFAL_FELICA_POLL_DELAY_TIME 512 /!< FeliCa Poll Processing time is 2.417 ms ~51264/fc Digital 1.1 A4 */
DiegoOstuni	0:75fc82583a41	249	#define RFAL_FELICA_POLL_SLOT_TIME 256 /!< FeliCa Poll Time Slot duration is 1.208 ms ~25664/fc Digital 1.1 A4 */
DiegoOstuni	0:75fc82583a41	250
DiegoOstuni	0:75fc82583a41	251	#define RFAL_ISO15693_IGNORE_BITS rfalConvBytesToBits(2) /!< Ignore collisions before the UID (RES_FLAG + DSFID) /
DiegoOstuni	0:75fc82583a41	252
DiegoOstuni	0:75fc82583a41	253
DiegoOstuni	0:75fc82583a41	254	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	255
DiegoOstuni	0:75fc82583a41	256	#define RFAL_LM_GT rfalConvUsTo1fc(100) /!< Listen Mode Guard Time enforced (GT - Passive; TIRFG - Active) /
DiegoOstuni	0:75fc82583a41	257	#define RFAL_FDT_POLL_ADJUSTMENT rfalConvUsTo1fc(80) /!< FDT Poll adjustment: Time between the expiration of GPT to the actual Tx /
DiegoOstuni	0:75fc82583a41	258	#define RFAL_FDT_LISTEN_MRT_ADJUSTMENT 64 /!< MRT jitter adjustment: timeout will be between [ tout ; tout + 64 cycles ] /
DiegoOstuni	0:75fc82583a41	259	#define RFAL_AP2P_FIELDOFF_TRFW rfalConv8fcTo1fc(64) /!< Time after TXE and Field Off in AP2P Trfw: 37.76us -> 64 (8/fc) /
DiegoOstuni	0:75fc82583a41	260
DiegoOstuni	0:75fc82583a41	261
DiegoOstuni	0:75fc82583a41	262	/*! FWT adjustment:
DiegoOstuni	0:75fc82583a41	263	* 64 : NRT jitter between TXE and NRT start */
DiegoOstuni	0:75fc82583a41	264	#define RFAL_FWT_ADJUSTMENT 64
DiegoOstuni	0:75fc82583a41	265
DiegoOstuni	0:75fc82583a41	266	/*! FWT ISO14443A adjustment:
DiegoOstuni	0:75fc82583a41	267	* 512 : Initial 4bit length */
DiegoOstuni	0:75fc82583a41	268	#define RFAL_FWT_A_ADJUSTMENT 512
DiegoOstuni	0:75fc82583a41	269
DiegoOstuni	0:75fc82583a41	270	/*! FWT ISO14443B adjustment:
DiegoOstuni	0:75fc82583a41	271	* 2784 : Adjustment for the SOF and initial byte */
DiegoOstuni	0:75fc82583a41	272	#define RFAL_FWT_B_ADJUSTMENT 2784
DiegoOstuni	0:75fc82583a41	273
DiegoOstuni	0:75fc82583a41	274
DiegoOstuni	0:75fc82583a41	275	/*! FWT FeliCa 212 adjustment:
DiegoOstuni	0:75fc82583a41	276	* 1024 : Length of the two Sync bytes at 212kbps */
DiegoOstuni	0:75fc82583a41	277	#define RFAL_FWT_F_212_ADJUSTMENT 1024
DiegoOstuni	0:75fc82583a41	278
DiegoOstuni	0:75fc82583a41	279	/*! FWT FeliCa 424 adjustment:
DiegoOstuni	0:75fc82583a41	280	* 512 : Length of the two Sync bytes at 424kbps */
DiegoOstuni	0:75fc82583a41	281	#define RFAL_FWT_F_424_ADJUSTMENT 512
DiegoOstuni	0:75fc82583a41	282
DiegoOstuni	0:75fc82583a41	283
DiegoOstuni	0:75fc82583a41	284	/*! Time between our field Off and other peer field On : Tadt + (n x Trfw)
DiegoOstuni	0:75fc82583a41	285	* Ecma 340 11.1.2 - Tadt: [56.64 , 188.72] us ; n: [0 , 3] ; Trfw = 37.76 us
DiegoOstuni	0:75fc82583a41	286	* Should be: 189 + (338) = 303us ; we'll use a more relaxed setting: 605 us /
DiegoOstuni	0:75fc82583a41	287	#define RFAL_AP2P_FIELDON_TADTTRFW rfalConvUsTo1fc(605)
DiegoOstuni	0:75fc82583a41	288
DiegoOstuni	0:75fc82583a41	289
DiegoOstuni	0:75fc82583a41	290	/*! FDT Poll adjustment for ISO14443A EMVCo 2.6 4.8.1.3 ; Digital 1.1 6.10
DiegoOstuni	0:75fc82583a41	291	*
DiegoOstuni	0:75fc82583a41	292	* 276: Time from the rising pulse of the pause of the logic '1' (i.e. the time point to measure the deaftime from),
DiegoOstuni	0:75fc82583a41	293	* to the actual end of the EOF sequence (the point where the MRT starts). Please note that the ST25R391x uses the
DiegoOstuni	0:75fc82583a41	294	* ISO14443-2 definition where the EOF consists of logic '0' followed by sequence Y.
DiegoOstuni	0:75fc82583a41	295	*/
DiegoOstuni	0:75fc82583a41	296	#define RFAL_FDT_LISTEN_A_ADJUSTMENT 276
DiegoOstuni	0:75fc82583a41	297
DiegoOstuni	0:75fc82583a41	298
DiegoOstuni	0:75fc82583a41	299	/*! FDT Poll adjustment for ISO14443B EMVCo 2.6 4.8.1.6 ; Digital 1.1 7.9
DiegoOstuni	0:75fc82583a41	300	*
DiegoOstuni	0:75fc82583a41	301	* 340: Time from the rising edge of the EoS to the starting point of the MRT timer (sometime after the final high
DiegoOstuni	0:75fc82583a41	302	* part of the EoS is completed).
DiegoOstuni	0:75fc82583a41	303	*
DiegoOstuni	0:75fc82583a41	304	* -64: Adjustment for the TR1PUTMIN.
DiegoOstuni	0:75fc82583a41	305	* The TR1PUTMIN of the ST25R3911 is 1152/fc (72/fs). The EMVCo test case TB0000 measures the TR1PUTMIN.
DiegoOstuni	0:75fc82583a41	306	* It takes the default value of TR1PUTMIN (79/fs) and reduces it by 128/fc in every iteration.
DiegoOstuni	0:75fc82583a41	307	* This results in a TR1PUTMIN of 1136/fc (71/fs) for the second iteration. The ST25R3911 sends a NAK because
DiegoOstuni	0:75fc82583a41	308	* the TR1PUTMIN of the ST25R3911 (72/fs) is higher than 71/fs.
DiegoOstuni	0:75fc82583a41	309	* Therefore the test suite assumes TR1PUTMIN of 1264/fc (79/fs).
DiegoOstuni	0:75fc82583a41	310	* The test cases TB340.0 and TB435.0 uses the TR1PUTMIN to send frames too early. In order to correctly
DiegoOstuni	0:75fc82583a41	311	* recognise these frames as being sent too early (starting inside reader deaf time), the MRT has to be
DiegoOstuni	0:75fc82583a41	312	* increased by at least 64/fc (8/fs).
DiegoOstuni	0:75fc82583a41	313	*/
DiegoOstuni	0:75fc82583a41	314	#define RFAL_FDT_LISTEN_B_ADJUSTMENT (340 - 64)
DiegoOstuni	0:75fc82583a41	315
DiegoOstuni	0:75fc82583a41	316
DiegoOstuni	0:75fc82583a41	317
DiegoOstuni	0:75fc82583a41	318	/*
DiegoOstuni	0:75fc82583a41	319	******************************************************************************
DiegoOstuni	0:75fc82583a41	320	* GLOBAL MACROS
DiegoOstuni	0:75fc82583a41	321	******************************************************************************
DiegoOstuni	0:75fc82583a41	322	*/
DiegoOstuni	0:75fc82583a41	323
DiegoOstuni	0:75fc82583a41	324	#define rfalCalcNumBytes( nBits ) (uint32_t)( (nBits + 7) / 8 ) /!< Returns the number of bytes required to fit given the number of bits /
DiegoOstuni	0:75fc82583a41	325
DiegoOstuni	0:75fc82583a41	326	#define rfalTimerStart( timer, time_ms ) timer = platformTimerCreate(time_ms) /!< Configures and starts the RTOX timer /
DiegoOstuni	0:75fc82583a41	327	#define rfalTimerisExpired( timer ) platformTimerIsExpired( timer ) /!< Checks if timer has expired /
DiegoOstuni	0:75fc82583a41	328
DiegoOstuni	0:75fc82583a41	329	#define rfalST25R3911ObsModeDisable() st25r3911WriteTestRegister(0x01, 0x00, mST25, mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) /!< Disable ST25R3911 Observation mode /
DiegoOstuni	0:75fc82583a41	330	#define rfalST25R3911ObsModeTx() st25r3911WriteTestRegister(0x01, gRFAL.conf.obsvModeTx, mST25, mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) /!< Enable Observation mode 0x0A CSI: Digital TX modulation signal CSO: none /
DiegoOstuni	0:75fc82583a41	331	#define rfalST25R3911ObsModeRx() st25r3911WriteTestRegister(0x01, gRFAL.conf.obsvModeRx, mST25, mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) /!< Enable Observation mode 0x04 CSI: Digital output of AM channel CSO: Digital output of PM channel /
DiegoOstuni	0:75fc82583a41	332
DiegoOstuni	0:75fc82583a41	333
DiegoOstuni	0:75fc82583a41	334	#define rfalCheckDisableObsMode() if(gRFAL.conf.obsvModeRx){ rfalST25R3911ObsModeDisable(); } /!< Checks if the observation mode is enabled, and applies on ST25R3911 /
DiegoOstuni	0:75fc82583a41	335	#define rfalCheckEnableObsModeTx() if(gRFAL.conf.obsvModeTx){ rfalST25R3911ObsModeTx(); } /!< Checks if the observation mode is enabled, and applies on ST25R3911 /
DiegoOstuni	0:75fc82583a41	336	#define rfalCheckEnableObsModeRx() if(gRFAL.conf.obsvModeRx){ rfalST25R3911ObsModeRx(); } /!< Checks if the observation mode is enabled, and applies on ST25R3911 /
DiegoOstuni	0:75fc82583a41	337
DiegoOstuni	0:75fc82583a41	338
DiegoOstuni	0:75fc82583a41	339	#define rfalGetIncmplBits( FIFOStatus2 ) (( FIFOStatus2 >> 1) & 0x07) /!< Returns the number of bits from fifo status /
DiegoOstuni	0:75fc82583a41	340	#define rfalIsIncompleteByteError( error ) ((error >= ERR_INCOMPLETE_BYTE) && (error <= ERR_INCOMPLETE_BYTE_07)) /!< Checks if given error is a Incomplete error /
DiegoOstuni	0:75fc82583a41	341
DiegoOstuni	0:75fc82583a41	342	#define rfalConvBR2ACBR( b ) (((b+1)<<RFAL_ANALOG_CONFIG_BITRATE_SHIFT) & RFAL_ANALOG_CONFIG_BITRATE_MASK) /!< Converts ST25R391x Bit rate to Analog Configuration bit rate id /
DiegoOstuni	0:75fc82583a41	343
DiegoOstuni	0:75fc82583a41	344
DiegoOstuni	0:75fc82583a41	345	#define rfalIsModeActiveComm( md ) ( (md == RFAL_MODE_POLL_ACTIVE_P2P) \|\| (md == RFAL_MODE_LISTEN_ACTIVE_P2P) ) /!< Checks if mode md is Active Communication /
DiegoOstuni	0:75fc82583a41	346	#define rfalIsModePassiveComm( md ) ( !rfalIsModeActiveComm(md) ) /!< Checks if mode md is Passive Communication/
DiegoOstuni	0:75fc82583a41	347	#define rfalIsModePassiveListen( md ) ( (md == RFAL_MODE_LISTEN_NFCA) \|\| (md == RFAL_MODE_LISTEN_NFCB) \|\| (md == RFAL_MODE_LISTEN_NFCF) ) /!< Checks if mode md is Passive Listen /
DiegoOstuni	0:75fc82583a41	348	#define rfalIsModePassivePoll( md ) ( rfalIsModePassiveComm(md) && !rfalIsModePassiveListen(md) ) /!< Checks if mode md is Passive Poll /
DiegoOstuni	0:75fc82583a41	349
DiegoOstuni	0:75fc82583a41	350	/*
DiegoOstuni	0:75fc82583a41	351	******************************************************************************
DiegoOstuni	0:75fc82583a41	352	* LOCAL VARIABLES
DiegoOstuni	0:75fc82583a41	353	******************************************************************************
DiegoOstuni	0:75fc82583a41	354	*/
DiegoOstuni	0:75fc82583a41	355
DiegoOstuni	0:75fc82583a41	356	static rfal gRFAL; /!< RFAL module instance /
DiegoOstuni	0:75fc82583a41	357
DiegoOstuni	0:75fc82583a41	358	/*
DiegoOstuni	0:75fc82583a41	359	******************************************************************************
DiegoOstuni	0:75fc82583a41	360	* LOCAL FUNCTION PROTOTYPES
DiegoOstuni	0:75fc82583a41	361	******************************************************************************
DiegoOstuni	0:75fc82583a41	362	*/
DiegoOstuni	0:75fc82583a41	363
DiegoOstuni	0:75fc82583a41	364	static void rfalTransceiveTx( SPI* mspiChannel, ST25R3911* mST25, DigitalOut* gpio_cs, InterruptIn* IRQ, DigitalOut* fieldLED_01, DigitalOut* fieldLED_02, DigitalOut* fieldLED_03, DigitalOut* fieldLED_04, DigitalOut* fieldLED_05, DigitalOut* fieldLED_06 );
DiegoOstuni	0:75fc82583a41	365	static void rfalTransceiveRx( SPI* mspiChannel, ST25R3911* mST25, DigitalOut* gpio_cs, InterruptIn* IRQ, DigitalOut* fieldLED_01, DigitalOut* fieldLED_02, DigitalOut* fieldLED_03, DigitalOut* fieldLED_04, DigitalOut* fieldLED_05, DigitalOut* fieldLED_06 );
DiegoOstuni	0:75fc82583a41	366	static ReturnCode rfalTransceiveRunBlockingTx( SPI* mspiChannel, ST25R3911* mST25, DigitalOut* gpio_cs, InterruptIn* IRQ, DigitalOut* fieldLED_01, DigitalOut* fieldLED_02, DigitalOut* fieldLED_03, DigitalOut* fieldLED_04, DigitalOut* fieldLED_05, DigitalOut* fieldLED_06 );
DiegoOstuni	0:75fc82583a41	367	static void rfalPrepareTransceive( SPI* mspiChannel, ST25R3911* mST25, DigitalOut* gpio_cs, InterruptIn* IRQ, DigitalOut* fieldLED_01, DigitalOut* fieldLED_02, DigitalOut* fieldLED_03, DigitalOut* fieldLED_04, DigitalOut* fieldLED_05, DigitalOut* fieldLED_06 );
DiegoOstuni	0:75fc82583a41	368	static void rfalCleanupTransceive( SPI* mspiChannel, ST25R3911* mST25, DigitalOut* gpio_cs, InterruptIn* IRQ, DigitalOut* fieldLED_01, DigitalOut* fieldLED_02, DigitalOut* fieldLED_03, DigitalOut* fieldLED_04, DigitalOut* fieldLED_05, DigitalOut* fieldLED_06 );
DiegoOstuni	0:75fc82583a41	369	static void rfalErrorHandling( ST25R3911* mST25, SPI * mspiChannel, DigitalOut* gpio_cs, InterruptIn* IRQ, DigitalOut* fieldLED_01, DigitalOut* fieldLED_02, DigitalOut* fieldLED_03, DigitalOut* fieldLED_04, DigitalOut* fieldLED_05, DigitalOut* fieldLED_06 );
DiegoOstuni	0:75fc82583a41	370	static ReturnCode rfalRunTransceiveWorker( SPI* mspiChannel, ST25R3911* mST25, DigitalOut* gpio_cs, InterruptIn* IRQ, DigitalOut* fieldLED_01, DigitalOut* fieldLED_02, DigitalOut* fieldLED_03, DigitalOut* fieldLED_04, DigitalOut* fieldLED_05, DigitalOut* fieldLED_06 );
DiegoOstuni	0:75fc82583a41	371	static ReturnCode rfalRunListenModeWorker( SPI* mspiChannel, ST25R3911* mST25, DigitalOut* gpio_cs, InterruptIn* IRQ, DigitalOut* fieldLED_01, DigitalOut* fieldLED_02, DigitalOut* fieldLED_03, DigitalOut* fieldLED_04, DigitalOut* fieldLED_05, DigitalOut* fieldLED_06 );
DiegoOstuni	0:75fc82583a41	372	static void rfalRunWakeUpModeWorker( SPI* mspiChannel, ST25R3911* mST25, DigitalOut* gpio_cs, InterruptIn* IRQ, DigitalOut* fieldLED_01, DigitalOut* fieldLED_02, DigitalOut* fieldLED_03, DigitalOut* fieldLED_04, DigitalOut* fieldLED_05, DigitalOut* fieldLED_06 );
DiegoOstuni	0:75fc82583a41	373
DiegoOstuni	0:75fc82583a41	374	static void rfalFIFOStatusUpdate( ST25R3911* mST25, SPI * mspiChannel, DigitalOut* gpio_cs, InterruptIn* IRQ, DigitalOut* fieldLED_01, DigitalOut* fieldLED_02, DigitalOut* fieldLED_03, DigitalOut* fieldLED_04, DigitalOut* fieldLED_05, DigitalOut* fieldLED_06 );
DiegoOstuni	0:75fc82583a41	375	static void rfalFIFOStatusClear( void );
DiegoOstuni	0:75fc82583a41	376	static bool rfalFIFOStatusIsMissingPar( ST25R3911* mST25, SPI * mspiChannel, DigitalOut* gpio_cs, InterruptIn* IRQ, DigitalOut* fieldLED_01, DigitalOut* fieldLED_02, DigitalOut* fieldLED_03, DigitalOut* fieldLED_04, DigitalOut* fieldLED_05, DigitalOut* fieldLED_06 );
DiegoOstuni	0:75fc82583a41	377	static bool rfalFIFOStatusIsIncompleteByte( ST25R3911* mST25, SPI * mspiChannel, DigitalOut* gpio_cs, InterruptIn* IRQ, DigitalOut* fieldLED_01, DigitalOut* fieldLED_02, DigitalOut* fieldLED_03, DigitalOut* fieldLED_04, DigitalOut* fieldLED_05, DigitalOut* fieldLED_06 );
DiegoOstuni	0:75fc82583a41	378	static uint8_t rfalFIFOStatusGetNumBytes( ST25R3911* mST25, SPI * mspiChannel, DigitalOut* gpio_cs, InterruptIn* IRQ, DigitalOut* fieldLED_01, DigitalOut* fieldLED_02, DigitalOut* fieldLED_03, DigitalOut* fieldLED_04, DigitalOut* fieldLED_05, DigitalOut* fieldLED_06 );
DiegoOstuni	0:75fc82583a41	379	static uint8_t rfalFIFOGetNumIncompleteBits( ST25R3911* mST25, SPI * mspiChannel, DigitalOut* gpio_cs, InterruptIn* IRQ, DigitalOut* fieldLED_01, DigitalOut* fieldLED_02, DigitalOut* fieldLED_03, DigitalOut* fieldLED_04, DigitalOut* fieldLED_05, DigitalOut* fieldLED_06 );
DiegoOstuni	0:75fc82583a41	380
DiegoOstuni	0:75fc82583a41	381
DiegoOstuni	0:75fc82583a41	382	/*
DiegoOstuni	0:75fc82583a41	383	******************************************************************************
DiegoOstuni	0:75fc82583a41	384	* GLOBAL FUNCTIONS
DiegoOstuni	0:75fc82583a41	385	******************************************************************************
DiegoOstuni	0:75fc82583a41	386	*/
DiegoOstuni	0:75fc82583a41	387
DiegoOstuni	0:75fc82583a41	388	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	389	ReturnCode rfalInitialize( SPI* mspiChannel, ST25R3911* mST25, DigitalOut* gpio_cs, InterruptIn* IRQ, DigitalOut* fieldLED_01,
DiegoOstuni	0:75fc82583a41	390	DigitalOut* fieldLED_02, DigitalOut* fieldLED_03,
DiegoOstuni	0:75fc82583a41	391	DigitalOut* fieldLED_04, DigitalOut* fieldLED_05, DigitalOut* fieldLED_06 )
DiegoOstuni	0:75fc82583a41	392	{
DiegoOstuni	0:75fc82583a41	393
DiegoOstuni	0:75fc82583a41	394	st25r3911InitInterrupts( fieldLED_06 );
DiegoOstuni	0:75fc82583a41	395
DiegoOstuni	0:75fc82583a41	396	/* Initialize chip */
DiegoOstuni	0:75fc82583a41	397	st25r3911Initialize( mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	398
DiegoOstuni	0:75fc82583a41	399	/* Check expected chip: ST25R3911 */
DiegoOstuni	0:75fc82583a41	400	if( !st25r3911CheckChipID( NULL, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) )
DiegoOstuni	0:75fc82583a41	401	{
DiegoOstuni	0:75fc82583a41	402	return ERR_HW_MISMATCH;
DiegoOstuni	0:75fc82583a41	403	}
DiegoOstuni	0:75fc82583a41	404
DiegoOstuni	0:75fc82583a41	405	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	406	/* Apply RF Chip general initialization */
DiegoOstuni	0:75fc82583a41	407	rfalSetAnalogConfig( RFAL_ANALOG_CONFIG_TECH_CHIP, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	408
DiegoOstuni	0:75fc82583a41	409	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	410	/* Set FIFO Water Levels to be used */
DiegoOstuni	0:75fc82583a41	411	st25r3911ChangeRegisterBits( ST25R3911_REG_IO_CONF1, (ST25R3911_REG_IO_CONF1_fifo_lt \| ST25R3911_REG_IO_CONF1_fifo_lr), (ST25R3911_REG_IO_CONF1_fifo_lt_32bytes \| ST25R3911_REG_IO_CONF1_fifo_lr_64bytes), mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	412
DiegoOstuni	0:75fc82583a41	413	/* Always have CRC in FIFO upon reception */
DiegoOstuni	0:75fc82583a41	414	st25r3911SetRegisterBits( ST25R3911_REG_AUX, ST25R3911_REG_AUX_crc_2_fifo, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	415
DiegoOstuni	0:75fc82583a41	416	/* Enable External Field Detector */
DiegoOstuni	0:75fc82583a41	417	st25r3911SetRegisterBits( ST25R3911_REG_AUX, ST25R3911_REG_AUX_en_fd, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	418
DiegoOstuni	0:75fc82583a41	419	/* Disable any previous observation mode */
DiegoOstuni	0:75fc82583a41	420	rfalST25R3911ObsModeDisable();
DiegoOstuni	0:75fc82583a41	421
DiegoOstuni	0:75fc82583a41	422	/* Clear FIFO status local copy */
DiegoOstuni	0:75fc82583a41	423	rfalFIFOStatusClear();
DiegoOstuni	0:75fc82583a41	424
DiegoOstuni	0:75fc82583a41	425
DiegoOstuni	0:75fc82583a41	426	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	427	/* Debug purposes */
DiegoOstuni	0:75fc82583a41	428	/logSetLevel( LOG_MODULE_DEFAULT, LOG_LEVEL_INFO ); !!!!!!!!!!!!!!! /
DiegoOstuni	0:75fc82583a41	429	/* rfalSetObsvMode( 0x0A, 0x04 ); */
DiegoOstuni	0:75fc82583a41	430
DiegoOstuni	0:75fc82583a41	431	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	432	gRFAL.state = RFAL_STATE_INIT;
DiegoOstuni	0:75fc82583a41	433	gRFAL.mode = RFAL_MODE_NONE;
DiegoOstuni	0:75fc82583a41	434	gRFAL.field = false;
DiegoOstuni	0:75fc82583a41	435
DiegoOstuni	0:75fc82583a41	436	/* Set RFAL default configs */
DiegoOstuni	0:75fc82583a41	437	gRFAL.conf.obsvModeTx = RFAL_OBSMODE_DISABLE;
DiegoOstuni	0:75fc82583a41	438	gRFAL.conf.obsvModeRx = RFAL_OBSMODE_DISABLE;
DiegoOstuni	0:75fc82583a41	439	gRFAL.conf.eHandling = RFAL_ERRORHANDLING_NONE;
DiegoOstuni	0:75fc82583a41	440
DiegoOstuni	0:75fc82583a41	441	/* Transceive set to IDLE */
DiegoOstuni	0:75fc82583a41	442	gRFAL.TxRx.lastState = RFAL_TXRX_STATE_IDLE;
DiegoOstuni	0:75fc82583a41	443	gRFAL.TxRx.state = RFAL_TXRX_STATE_IDLE;
DiegoOstuni	0:75fc82583a41	444
DiegoOstuni	0:75fc82583a41	445	/* Disable all timings */
DiegoOstuni	0:75fc82583a41	446	gRFAL.timings.FDTListen = RFAL_TIMING_NONE;
DiegoOstuni	0:75fc82583a41	447	gRFAL.timings.FDTPoll = RFAL_TIMING_NONE;
DiegoOstuni	0:75fc82583a41	448	gRFAL.timings.GT = RFAL_TIMING_NONE;
DiegoOstuni	0:75fc82583a41	449
DiegoOstuni	0:75fc82583a41	450	gRFAL.tmr.GT = RFAL_TIMING_NONE;
DiegoOstuni	0:75fc82583a41	451
DiegoOstuni	0:75fc82583a41	452	gRFAL.callbacks.preTxRx = NULL;
DiegoOstuni	0:75fc82583a41	453	gRFAL.callbacks.postTxRx = NULL;
DiegoOstuni	0:75fc82583a41	454
DiegoOstuni	0:75fc82583a41	455	#if RFAL_FEATURE_NFCV
DiegoOstuni	0:75fc82583a41	456	/* Initialize NFC-V Data */
DiegoOstuni	0:75fc82583a41	457	gRFAL.nfcvData.ignoreBits = 0;
DiegoOstuni	0:75fc82583a41	458	#endif /* RFAL_FEATURE_NFCV */
DiegoOstuni	0:75fc82583a41	459
DiegoOstuni	0:75fc82583a41	460	/* Initialize Listen Mode */
DiegoOstuni	0:75fc82583a41	461	gRFAL.Lm.state = RFAL_LM_STATE_NOT_INIT;
DiegoOstuni	0:75fc82583a41	462	gRFAL.Lm.brDetected = RFAL_BR_KEEP;
DiegoOstuni	0:75fc82583a41	463
DiegoOstuni	0:75fc82583a41	464	/* Initialize Wake-Up Mode */
DiegoOstuni	0:75fc82583a41	465	gRFAL.wum.state = RFAL_WUM_STATE_NOT_INIT;
DiegoOstuni	0:75fc82583a41	466
DiegoOstuni	0:75fc82583a41	467
DiegoOstuni	0:75fc82583a41	468	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	469	/* Perform Automatic Calibration (if configured to do so). *
DiegoOstuni	0:75fc82583a41	470	* Registers set by rfalSetAnalogConfig will tell rfalCalibrate what to perform*/
DiegoOstuni	0:75fc82583a41	471	rfalCalibrate( mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	472
DiegoOstuni	0:75fc82583a41	473	return ERR_NONE;
DiegoOstuni	0:75fc82583a41	474	}
DiegoOstuni	0:75fc82583a41	475
DiegoOstuni	0:75fc82583a41	476
DiegoOstuni	0:75fc82583a41	477	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	478	ReturnCode rfalCalibrate( SPI* mspiChannel, ST25R3911* mST25, DigitalOut* gpio_cs, InterruptIn* IRQ, DigitalOut* fieldLED_01, DigitalOut* fieldLED_02, DigitalOut* fieldLED_03, DigitalOut* fieldLED_04, DigitalOut* fieldLED_05, DigitalOut* fieldLED_06 )
DiegoOstuni	0:75fc82583a41	479	{
DiegoOstuni	0:75fc82583a41	480	uint16_t resValue;
DiegoOstuni	0:75fc82583a41	481
DiegoOstuni	0:75fc82583a41	482	/* Check if RFAL is not initialized */
DiegoOstuni	0:75fc82583a41	483	if( gRFAL.state == RFAL_STATE_IDLE )
DiegoOstuni	0:75fc82583a41	484	{
DiegoOstuni	0:75fc82583a41	485	return ERR_WRONG_STATE;
DiegoOstuni	0:75fc82583a41	486	}
DiegoOstuni	0:75fc82583a41	487
DiegoOstuni	0:75fc82583a41	488	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	489	/* Perform ST25R3911 regulators and antenna calibration */
DiegoOstuni	0:75fc82583a41	490	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	491
DiegoOstuni	0:75fc82583a41	492	/* Automatic regulator adjustment only performed if not set manually on Analog Configs */
DiegoOstuni	0:75fc82583a41	493	if( st25r3911CheckReg( ST25R3911_REG_REGULATOR_CONTROL, ST25R3911_REG_REGULATOR_CONTROL_reg_s, 0x00, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) )
DiegoOstuni	0:75fc82583a41	494	{
DiegoOstuni	0:75fc82583a41	495	/* Adjust the regulators so that Antenna Calibrate has better Regulator values */
DiegoOstuni	0:75fc82583a41	496	st25r3911AdjustRegulators( &resValue, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	497	}
DiegoOstuni	0:75fc82583a41	498
DiegoOstuni	0:75fc82583a41	499	/* Automatic Antenna calibration only performed if not set manually on Analog Configs */
DiegoOstuni	0:75fc82583a41	500	if( st25r3911CheckReg( ST25R3911_REG_ANT_CAL_CONTROL, ST25R3911_REG_ANT_CAL_CONTROL_trim_s, 0x00, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) )
DiegoOstuni	0:75fc82583a41	501	{
DiegoOstuni	0:75fc82583a41	502	st25r3911CalibrateAntenna( (uint8_t*) &resValue, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	503
DiegoOstuni	0:75fc82583a41	504	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	505	/* REMARK: Silicon workaround ST25R3911 Errata #1.5 */
DiegoOstuni	0:75fc82583a41	506	/* Always run the command Calibrate Antenna twice */
DiegoOstuni	0:75fc82583a41	507	st25r3911CalibrateAntenna( (uint8_t*) &resValue, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	508	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	509
DiegoOstuni	0:75fc82583a41	510	}
DiegoOstuni	0:75fc82583a41	511	else
DiegoOstuni	0:75fc82583a41	512	{
DiegoOstuni	0:75fc82583a41	513	/* If no antenna calibration is performed there is no need to perform second regulator adjustment again */
DiegoOstuni	0:75fc82583a41	514	return ERR_NONE;
DiegoOstuni	0:75fc82583a41	515	}
DiegoOstuni	0:75fc82583a41	516
DiegoOstuni	0:75fc82583a41	517	if( st25r3911CheckReg( ST25R3911_REG_REGULATOR_CONTROL, ST25R3911_REG_REGULATOR_CONTROL_reg_s, 0x00, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) )
DiegoOstuni	0:75fc82583a41	518	{
DiegoOstuni	0:75fc82583a41	519	/* Adjust the regulators again with the Antenna calibrated */
DiegoOstuni	0:75fc82583a41	520	st25r3911AdjustRegulators( &resValue, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	521	}
DiegoOstuni	0:75fc82583a41	522
DiegoOstuni	0:75fc82583a41	523	return ERR_NONE;
DiegoOstuni	0:75fc82583a41	524	}
DiegoOstuni	0:75fc82583a41	525
DiegoOstuni	0:75fc82583a41	526
DiegoOstuni	0:75fc82583a41	527	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	528	ReturnCode rfalAdjustRegulators( uint16_t* result, SPI mspiChannel, ST25R3911 mST25, DigitalOut* gpio_cs, InterruptIn* IRQ, DigitalOut* fieldLED_01, DigitalOut* fieldLED_02, DigitalOut* fieldLED_03, DigitalOut* fieldLED_04, DigitalOut* fieldLED_05, DigitalOut* fieldLED_06 )
DiegoOstuni	0:75fc82583a41	529	{
DiegoOstuni	0:75fc82583a41	530	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	531	/* Make use of the Automatic Adjust */
DiegoOstuni	0:75fc82583a41	532	st25r3911ClrRegisterBits( ST25R3911_REG_REGULATOR_CONTROL, ST25R3911_REG_REGULATOR_CONTROL_reg_s, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	533
DiegoOstuni	0:75fc82583a41	534	return st25r3911AdjustRegulators( result, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	535	}
DiegoOstuni	0:75fc82583a41	536
DiegoOstuni	0:75fc82583a41	537
DiegoOstuni	0:75fc82583a41	538	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	539	void rfalSetUpperLayerCallback( rfalUpperLayerCallback pFunc )
DiegoOstuni	0:75fc82583a41	540	{
DiegoOstuni	0:75fc82583a41	541	st25r3911IRQCallbackSet( pFunc );
DiegoOstuni	0:75fc82583a41	542	}
DiegoOstuni	0:75fc82583a41	543
DiegoOstuni	0:75fc82583a41	544
DiegoOstuni	0:75fc82583a41	545	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	546	void rfalSetPreTxRxCallback( rfalPreTxRxCallback pFunc )
DiegoOstuni	0:75fc82583a41	547	{
DiegoOstuni	0:75fc82583a41	548	gRFAL.callbacks.preTxRx = pFunc;
DiegoOstuni	0:75fc82583a41	549	}
DiegoOstuni	0:75fc82583a41	550
DiegoOstuni	0:75fc82583a41	551
DiegoOstuni	0:75fc82583a41	552	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	553	void rfalSetPostTxRxCallback( rfalPostTxRxCallback pFunc )
DiegoOstuni	0:75fc82583a41	554	{
DiegoOstuni	0:75fc82583a41	555	gRFAL.callbacks.postTxRx = pFunc;
DiegoOstuni	0:75fc82583a41	556	}
DiegoOstuni	0:75fc82583a41	557
DiegoOstuni	0:75fc82583a41	558
DiegoOstuni	0:75fc82583a41	559	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	560	ReturnCode rfalDeinitialize( SPI* mspiChannel, ST25R3911* mST25, DigitalOut* gpio_cs, InterruptIn* IRQ, DigitalOut* fieldLED_01, DigitalOut* fieldLED_02, DigitalOut* fieldLED_03, DigitalOut* fieldLED_04, DigitalOut* fieldLED_05, DigitalOut* fieldLED_06 )
DiegoOstuni	0:75fc82583a41	561	{
DiegoOstuni	0:75fc82583a41	562	/* Deinitialize chip */
DiegoOstuni	0:75fc82583a41	563	st25r3911Deinitialize(mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	564
DiegoOstuni	0:75fc82583a41	565	gRFAL.state = RFAL_STATE_IDLE;
DiegoOstuni	0:75fc82583a41	566	return ERR_NONE;
DiegoOstuni	0:75fc82583a41	567	}
DiegoOstuni	0:75fc82583a41	568
DiegoOstuni	0:75fc82583a41	569
DiegoOstuni	0:75fc82583a41	570	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	571	void rfalSetObsvMode( uint8_t txMode, uint8_t rxMode )
DiegoOstuni	0:75fc82583a41	572	{
DiegoOstuni	0:75fc82583a41	573	gRFAL.conf.obsvModeTx = txMode;
DiegoOstuni	0:75fc82583a41	574	gRFAL.conf.obsvModeRx = rxMode;
DiegoOstuni	0:75fc82583a41	575	}
DiegoOstuni	0:75fc82583a41	576
DiegoOstuni	0:75fc82583a41	577
DiegoOstuni	0:75fc82583a41	578	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	579	void rfalGetObsvMode( uint8_t* txMode, uint8_t* rxMode )
DiegoOstuni	0:75fc82583a41	580	{
DiegoOstuni	0:75fc82583a41	581	if(txMode != NULL)
DiegoOstuni	0:75fc82583a41	582	{
DiegoOstuni	0:75fc82583a41	583	*txMode = gRFAL.conf.obsvModeTx;
DiegoOstuni	0:75fc82583a41	584	}
DiegoOstuni	0:75fc82583a41	585
DiegoOstuni	0:75fc82583a41	586	if(rxMode != NULL)
DiegoOstuni	0:75fc82583a41	587	{
DiegoOstuni	0:75fc82583a41	588	*rxMode = gRFAL.conf.obsvModeRx;
DiegoOstuni	0:75fc82583a41	589	}
DiegoOstuni	0:75fc82583a41	590	}
DiegoOstuni	0:75fc82583a41	591
DiegoOstuni	0:75fc82583a41	592
DiegoOstuni	0:75fc82583a41	593	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	594	void rfalDisableObsvMode( void )
DiegoOstuni	0:75fc82583a41	595	{
DiegoOstuni	0:75fc82583a41	596	gRFAL.conf.obsvModeTx = RFAL_OBSMODE_DISABLE;
DiegoOstuni	0:75fc82583a41	597	gRFAL.conf.obsvModeRx = RFAL_OBSMODE_DISABLE;
DiegoOstuni	0:75fc82583a41	598	}
DiegoOstuni	0:75fc82583a41	599
DiegoOstuni	0:75fc82583a41	600
DiegoOstuni	0:75fc82583a41	601	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	602	ReturnCode rfalSetMode( rfalMode mode, rfalBitRate txBR, rfalBitRate rxBR,SPI* mspiChannel, ST25R3911* mST25, DigitalOut* gpio_cs, InterruptIn* IRQ, DigitalOut* fieldLED_01, DigitalOut* fieldLED_02, DigitalOut* fieldLED_03, DigitalOut* fieldLED_04, DigitalOut* fieldLED_05, DigitalOut* fieldLED_06 )
DiegoOstuni	0:75fc82583a41	603	{
DiegoOstuni	0:75fc82583a41	604
DiegoOstuni	0:75fc82583a41	605	/* Check if RFAL is not initialized */
DiegoOstuni	0:75fc82583a41	606	if( gRFAL.state == RFAL_STATE_IDLE )
DiegoOstuni	0:75fc82583a41	607	{
DiegoOstuni	0:75fc82583a41	608	return ERR_WRONG_STATE;
DiegoOstuni	0:75fc82583a41	609	}
DiegoOstuni	0:75fc82583a41	610
DiegoOstuni	0:75fc82583a41	611	/* Check allowed bit rate value */
DiegoOstuni	0:75fc82583a41	612	if( (txBR == RFAL_BR_KEEP) \|\| (rxBR == RFAL_BR_KEEP) )
DiegoOstuni	0:75fc82583a41	613	{
DiegoOstuni	0:75fc82583a41	614	return ERR_PARAM;
DiegoOstuni	0:75fc82583a41	615	}
DiegoOstuni	0:75fc82583a41	616
DiegoOstuni	0:75fc82583a41	617	switch( mode )
DiegoOstuni	0:75fc82583a41	618	{
DiegoOstuni	0:75fc82583a41	619	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	620	case RFAL_MODE_POLL_NFCA:
DiegoOstuni	0:75fc82583a41	621
DiegoOstuni	0:75fc82583a41	622	/* Disable wake up mode, if set */
DiegoOstuni	0:75fc82583a41	623	st25r3911ClrRegisterBits( ST25R3911_REG_OP_CONTROL, ST25R3911_REG_OP_CONTROL_wu, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	624
DiegoOstuni	0:75fc82583a41	625	/* Enable ISO14443A mode */
DiegoOstuni	0:75fc82583a41	626	mST25 -> writeRegister(ST25R3911_REG_MODE, ST25R3911_REG_MODE_om_iso14443a, mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	627
DiegoOstuni	0:75fc82583a41	628	/* Set Analog configurations for this mode and bit rate */
DiegoOstuni	0:75fc82583a41	629	rfalSetAnalogConfig( (RFAL_ANALOG_CONFIG_POLL \| RFAL_ANALOG_CONFIG_TECH_NFCA \| RFAL_ANALOG_CONFIG_BITRATE_COMMON \| RFAL_ANALOG_CONFIG_TX), mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	630	rfalSetAnalogConfig( (RFAL_ANALOG_CONFIG_POLL \| RFAL_ANALOG_CONFIG_TECH_NFCA \| RFAL_ANALOG_CONFIG_BITRATE_COMMON \| RFAL_ANALOG_CONFIG_RX), mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	631	break;
DiegoOstuni	0:75fc82583a41	632
DiegoOstuni	0:75fc82583a41	633	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	634	case RFAL_MODE_POLL_NFCA_T1T:
DiegoOstuni	0:75fc82583a41	635	/* Disable wake up mode, if set */
DiegoOstuni	0:75fc82583a41	636	st25r3911ClrRegisterBits( ST25R3911_REG_OP_CONTROL, ST25R3911_REG_OP_CONTROL_wu, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	637
DiegoOstuni	0:75fc82583a41	638	/* Enable Topaz mode */
DiegoOstuni	0:75fc82583a41	639	mST25 ->writeRegister( ST25R3911_REG_MODE, ST25R3911_REG_MODE_om_topaz, mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	640
DiegoOstuni	0:75fc82583a41	641	/* Set Analog configurations for this mode and bit rate */
DiegoOstuni	0:75fc82583a41	642	rfalSetAnalogConfig( (RFAL_ANALOG_CONFIG_POLL \| RFAL_ANALOG_CONFIG_TECH_NFCA \| RFAL_ANALOG_CONFIG_BITRATE_COMMON \| RFAL_ANALOG_CONFIG_TX), mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	643	rfalSetAnalogConfig( (RFAL_ANALOG_CONFIG_POLL \| RFAL_ANALOG_CONFIG_TECH_NFCA \| RFAL_ANALOG_CONFIG_BITRATE_COMMON \| RFAL_ANALOG_CONFIG_RX), mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	644	break;
DiegoOstuni	0:75fc82583a41	645
DiegoOstuni	0:75fc82583a41	646	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	647	case RFAL_MODE_POLL_NFCB:
DiegoOstuni	0:75fc82583a41	648
DiegoOstuni	0:75fc82583a41	649	/* Disable wake up mode, if set */
DiegoOstuni	0:75fc82583a41	650	st25r3911ClrRegisterBits( ST25R3911_REG_OP_CONTROL, ST25R3911_REG_OP_CONTROL_wu, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	651
DiegoOstuni	0:75fc82583a41	652	/* Enable ISO14443B mode */
DiegoOstuni	0:75fc82583a41	653	mST25 -> writeRegister(ST25R3911_REG_MODE, ST25R3911_REG_MODE_om_iso14443b, mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	654
DiegoOstuni	0:75fc82583a41	655	/* Set the EGT, SOF, EOF and EOF */
DiegoOstuni	0:75fc82583a41	656	st25r3911ChangeRegisterBits( ST25R3911_REG_ISO14443B_1,
DiegoOstuni	0:75fc82583a41	657	(ST25R3911_REG_ISO14443B_1_mask_egt \| ST25R3911_REG_ISO14443B_1_mask_sof \| ST25R3911_REG_ISO14443B_1_mask_eof),
DiegoOstuni	0:75fc82583a41	658	( (0<<ST25R3911_REG_ISO14443B_1_shift_egt) \| ST25R3911_REG_ISO14443B_1_sof_0_10etu \| ST25R3911_REG_ISO14443B_1_sof_1_2etu),
DiegoOstuni	0:75fc82583a41	659	mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	660
DiegoOstuni	0:75fc82583a41	661	/* Set the minimum TR1, SOF, EOF and EOF12 */
DiegoOstuni	0:75fc82583a41	662	st25r3911ChangeRegisterBits( ST25R3911_REG_ISO14443B_2,
DiegoOstuni	0:75fc82583a41	663	(ST25R3911_REG_ISO14443B_2_mask_tr1 \| ST25R3911_REG_ISO14443B_2_no_sof \| ST25R3911_REG_ISO14443B_2_no_eof \|ST25R3911_REG_ISO14443B_2_eof_12),
DiegoOstuni	0:75fc82583a41	664	(ST25R3911_REG_ISO14443B_2_tr1_80fs80fs \| ST25R3911_REG_ISO14443B_2_eof_12_10to11etu ),
DiegoOstuni	0:75fc82583a41	665	mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	666
DiegoOstuni	0:75fc82583a41	667
DiegoOstuni	0:75fc82583a41	668	/* Set Analog configurations for this mode and bit rate */
DiegoOstuni	0:75fc82583a41	669	rfalSetAnalogConfig( (RFAL_ANALOG_CONFIG_POLL \| RFAL_ANALOG_CONFIG_TECH_NFCB \| RFAL_ANALOG_CONFIG_BITRATE_COMMON \| RFAL_ANALOG_CONFIG_TX), mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	670	rfalSetAnalogConfig( (RFAL_ANALOG_CONFIG_POLL \| RFAL_ANALOG_CONFIG_TECH_NFCB \| RFAL_ANALOG_CONFIG_BITRATE_COMMON \| RFAL_ANALOG_CONFIG_RX), mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	671	break;
DiegoOstuni	0:75fc82583a41	672
DiegoOstuni	0:75fc82583a41	673	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	674	case RFAL_MODE_POLL_B_PRIME:
DiegoOstuni	0:75fc82583a41	675
DiegoOstuni	0:75fc82583a41	676	/* Disable wake up mode, if set */
DiegoOstuni	0:75fc82583a41	677	st25r3911ClrRegisterBits( ST25R3911_REG_OP_CONTROL, ST25R3911_REG_OP_CONTROL_wu, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	678
DiegoOstuni	0:75fc82583a41	679	/* Enable ISO14443B mode */
DiegoOstuni	0:75fc82583a41	680	mST25->writeRegister(ST25R3911_REG_MODE, ST25R3911_REG_MODE_om_iso14443b, mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 );
DiegoOstuni	0:75fc82583a41	681
DiegoOstuni	0:75fc82583a41	682	/* Set the EGT, SOF, EOF and EOF */
DiegoOstuni	0:75fc82583a41	683	st25r3911ChangeRegisterBits( ST25R3911_REG_ISO14443B_1,
DiegoOstuni	0:75fc82583a41	684	(ST25R3911_REG_ISO14443B_1_mask_egt \| ST25R3911_REG_ISO14443B_1_mask_sof \| ST25R3911_REG_ISO14443B_1_mask_eof),
DiegoOstuni	0:75fc82583a41	685	( (0<<ST25R3911_REG_ISO14443B_1_shift_egt) \| ST25R3911_REG_ISO14443B_1_sof_0_10etu \| ST25R3911_REG_ISO14443B_1_sof_1_2etu),
DiegoOstuni	0:75fc82583a41	686	mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	687
DiegoOstuni	0:75fc82583a41	688	/* Set the minimum TR1, EOF and EOF12 */
DiegoOstuni	0:75fc82583a41	689	st25r3911ChangeRegisterBits( ST25R3911_REG_ISO14443B_2,
DiegoOstuni	0:75fc82583a41	690	(ST25R3911_REG_ISO14443B_2_mask_tr1 \| ST25R3911_REG_ISO14443B_2_no_sof \| ST25R3911_REG_ISO14443B_2_no_eof \|ST25R3911_REG_ISO14443B_2_eof_12),
DiegoOstuni	0:75fc82583a41	691	(ST25R3911_REG_ISO14443B_2_tr1_80fs80fs \| ST25R3911_REG_ISO14443B_2_no_sof \| ST25R3911_REG_ISO14443B_2_eof_12_10to12etu ),
DiegoOstuni	0:75fc82583a41	692	mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	693
DiegoOstuni	0:75fc82583a41	694
DiegoOstuni	0:75fc82583a41	695	/* Set Analog configurations for this mode and bit rate */
DiegoOstuni	0:75fc82583a41	696	rfalSetAnalogConfig( (RFAL_ANALOG_CONFIG_POLL \| RFAL_ANALOG_CONFIG_TECH_NFCB \| RFAL_ANALOG_CONFIG_BITRATE_COMMON \| RFAL_ANALOG_CONFIG_TX), mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	697	rfalSetAnalogConfig( (RFAL_ANALOG_CONFIG_POLL \| RFAL_ANALOG_CONFIG_TECH_NFCB \| RFAL_ANALOG_CONFIG_BITRATE_COMMON \| RFAL_ANALOG_CONFIG_RX), mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	698	break;
DiegoOstuni	0:75fc82583a41	699
DiegoOstuni	0:75fc82583a41	700	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	701	case RFAL_MODE_POLL_B_CTS:
DiegoOstuni	0:75fc82583a41	702
DiegoOstuni	0:75fc82583a41	703	/* Disable wake up mode, if set */
DiegoOstuni	0:75fc82583a41	704	st25r3911ClrRegisterBits( ST25R3911_REG_OP_CONTROL, ST25R3911_REG_OP_CONTROL_wu, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	705
DiegoOstuni	0:75fc82583a41	706	/* Enable ISO14443B mode */
DiegoOstuni	0:75fc82583a41	707	mST25->writeRegister(ST25R3911_REG_MODE, ST25R3911_REG_MODE_om_iso14443b, mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	708
DiegoOstuni	0:75fc82583a41	709	/* Set the EGT, SOF, EOF and EOF */
DiegoOstuni	0:75fc82583a41	710	st25r3911ChangeRegisterBits( ST25R3911_REG_ISO14443B_1,
DiegoOstuni	0:75fc82583a41	711	(ST25R3911_REG_ISO14443B_1_mask_egt \| ST25R3911_REG_ISO14443B_1_mask_sof \| ST25R3911_REG_ISO14443B_1_mask_eof),
DiegoOstuni	0:75fc82583a41	712	( (0<<ST25R3911_REG_ISO14443B_1_shift_egt) \| ST25R3911_REG_ISO14443B_1_sof_0_10etu \| ST25R3911_REG_ISO14443B_1_sof_1_2etu),
DiegoOstuni	0:75fc82583a41	713	mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	714
DiegoOstuni	0:75fc82583a41	715	/* Set the minimum TR1, clear SOF, EOF and EOF12 */
DiegoOstuni	0:75fc82583a41	716	st25r3911ChangeRegisterBits( ST25R3911_REG_ISO14443B_2,
DiegoOstuni	0:75fc82583a41	717	(ST25R3911_REG_ISO14443B_2_mask_tr1 \| ST25R3911_REG_ISO14443B_2_no_sof \| ST25R3911_REG_ISO14443B_2_no_eof \|ST25R3911_REG_ISO14443B_2_eof_12),
DiegoOstuni	0:75fc82583a41	718	(ST25R3911_REG_ISO14443B_2_tr1_80fs80fs \| ST25R3911_REG_ISO14443B_2_no_sof \| ST25R3911_REG_ISO14443B_2_no_eof ),
DiegoOstuni	0:75fc82583a41	719	mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	720
DiegoOstuni	0:75fc82583a41	721
DiegoOstuni	0:75fc82583a41	722	/* Set Analog configurations for this mode and bit rate */
DiegoOstuni	0:75fc82583a41	723	rfalSetAnalogConfig( (RFAL_ANALOG_CONFIG_POLL \| RFAL_ANALOG_CONFIG_TECH_NFCB \| RFAL_ANALOG_CONFIG_BITRATE_COMMON \| RFAL_ANALOG_CONFIG_TX), mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	724	rfalSetAnalogConfig( (RFAL_ANALOG_CONFIG_POLL \| RFAL_ANALOG_CONFIG_TECH_NFCB \| RFAL_ANALOG_CONFIG_BITRATE_COMMON \| RFAL_ANALOG_CONFIG_RX), mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	725	break;
DiegoOstuni	0:75fc82583a41	726
DiegoOstuni	0:75fc82583a41	727	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	728	case RFAL_MODE_POLL_NFCF:
DiegoOstuni	0:75fc82583a41	729
DiegoOstuni	0:75fc82583a41	730	/* Disable wake up mode, if set */
DiegoOstuni	0:75fc82583a41	731	st25r3911ClrRegisterBits( ST25R3911_REG_OP_CONTROL, ST25R3911_REG_OP_CONTROL_wu, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	732
DiegoOstuni	0:75fc82583a41	733	/* Enable FeliCa mode */
DiegoOstuni	0:75fc82583a41	734	mST25->writeRegister( ST25R3911_REG_MODE, ST25R3911_REG_MODE_om_felica, mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	735
DiegoOstuni	0:75fc82583a41	736	/* Set Analog configurations for this mode and bit rate */
DiegoOstuni	0:75fc82583a41	737	rfalSetAnalogConfig( (RFAL_ANALOG_CONFIG_POLL \| RFAL_ANALOG_CONFIG_TECH_NFCF \| RFAL_ANALOG_CONFIG_BITRATE_COMMON \| RFAL_ANALOG_CONFIG_TX), mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	738	rfalSetAnalogConfig( (RFAL_ANALOG_CONFIG_POLL \| RFAL_ANALOG_CONFIG_TECH_NFCF \| RFAL_ANALOG_CONFIG_BITRATE_COMMON \| RFAL_ANALOG_CONFIG_RX), mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	739	break;
DiegoOstuni	0:75fc82583a41	740
DiegoOstuni	0:75fc82583a41	741	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	742	case RFAL_MODE_POLL_NFCV:
DiegoOstuni	0:75fc82583a41	743	case RFAL_MODE_POLL_PICOPASS:
DiegoOstuni	0:75fc82583a41	744
DiegoOstuni	0:75fc82583a41	745	/* Disable wake up mode, if set */
DiegoOstuni	0:75fc82583a41	746	st25r3911ClrRegisterBits( ST25R3911_REG_OP_CONTROL, ST25R3911_REG_OP_CONTROL_wu, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	747
DiegoOstuni	0:75fc82583a41	748	/* Set Analog configurations for this mode and bit rate */
DiegoOstuni	0:75fc82583a41	749	rfalSetAnalogConfig( (RFAL_ANALOG_CONFIG_POLL \| RFAL_ANALOG_CONFIG_TECH_NFCV \| RFAL_ANALOG_CONFIG_BITRATE_COMMON \| RFAL_ANALOG_CONFIG_TX), mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	750	rfalSetAnalogConfig( (RFAL_ANALOG_CONFIG_POLL \| RFAL_ANALOG_CONFIG_TECH_NFCV \| RFAL_ANALOG_CONFIG_BITRATE_COMMON \| RFAL_ANALOG_CONFIG_RX), mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	751	break;
DiegoOstuni	0:75fc82583a41	752
DiegoOstuni	0:75fc82583a41	753	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	754	case RFAL_MODE_POLL_ACTIVE_P2P:
DiegoOstuni	0:75fc82583a41	755
DiegoOstuni	0:75fc82583a41	756	/* Set NFCIP1 active communication initiator mode and Enable NFC Automatic Response RF Collision Avoidance */
DiegoOstuni	0:75fc82583a41	757	mST25->writeRegister(ST25R3911_REG_MODE, (ST25R3911_REG_MODE_targ_init \| ST25R3911_REG_MODE_om_nfc \| ST25R3911_REG_MODE_nfc_ar),
DiegoOstuni	0:75fc82583a41	758	mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	759
DiegoOstuni	0:75fc82583a41	760	/* Set GPT to start after end of TX, as GPT is used in active communication mode to timeout the field switching off */
DiegoOstuni	0:75fc82583a41	761	/* The field is turned off 37.76us after the end of the transmission Trfw */
DiegoOstuni	0:75fc82583a41	762	st25r3911StartGPTimer_8fcs( rfalConv1fcTo8fc( RFAL_AP2P_FIELDOFF_TRFW ), ST25R3911_REG_GPT_CONTROL_gptc_etx_nfc,
DiegoOstuni	0:75fc82583a41	763	mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	764
DiegoOstuni	0:75fc82583a41	765	/* Enable External Field Detector */
DiegoOstuni	0:75fc82583a41	766	st25r3911SetRegisterBits( ST25R3911_REG_AUX, ST25R3911_REG_AUX_en_fd, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	767
DiegoOstuni	0:75fc82583a41	768	/* Set Analog configurations for this mode and bit rate */
DiegoOstuni	0:75fc82583a41	769	rfalSetAnalogConfig( (RFAL_ANALOG_CONFIG_POLL \| RFAL_ANALOG_CONFIG_TECH_AP2P \| RFAL_ANALOG_CONFIG_BITRATE_COMMON \| RFAL_ANALOG_CONFIG_TX), mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	770	rfalSetAnalogConfig( (RFAL_ANALOG_CONFIG_POLL \| RFAL_ANALOG_CONFIG_TECH_AP2P \| RFAL_ANALOG_CONFIG_BITRATE_COMMON \| RFAL_ANALOG_CONFIG_RX), mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	771	break;
DiegoOstuni	0:75fc82583a41	772
DiegoOstuni	0:75fc82583a41	773	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	774	case RFAL_MODE_LISTEN_ACTIVE_P2P:
DiegoOstuni	0:75fc82583a41	775
DiegoOstuni	0:75fc82583a41	776	/* Set NFCIP1 active communication initiator mode and Enable NFC Automatic Response RF Collision Avoidance */
DiegoOstuni	0:75fc82583a41	777	mST25-> writeRegister(ST25R3911_REG_MODE, (ST25R3911_REG_MODE_targ_targ \| ST25R3911_REG_MODE_om_nfcip1_normal_mode \| ST25R3911_REG_MODE_nfc_ar),
DiegoOstuni	0:75fc82583a41	778	mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	779
DiegoOstuni	0:75fc82583a41	780	/* Set GPT to start after end of TX, as GPT is used in active communication mode to timeout the field switching off */
DiegoOstuni	0:75fc82583a41	781	/* The field is turned off 37.76us after the end of the transmission Trfw */
DiegoOstuni	0:75fc82583a41	782	st25r3911StartGPTimer_8fcs( rfalConv1fcTo8fc( RFAL_AP2P_FIELDOFF_TRFW ), ST25R3911_REG_GPT_CONTROL_gptc_etx_nfc, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 );
DiegoOstuni	0:75fc82583a41	783
DiegoOstuni	0:75fc82583a41	784	/* Enable External Field Detector */
DiegoOstuni	0:75fc82583a41	785	st25r3911SetRegisterBits( ST25R3911_REG_AUX, ST25R3911_REG_AUX_en_fd, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	786
DiegoOstuni	0:75fc82583a41	787	/* Set Analog configurations for this mode and bit rate */
DiegoOstuni	0:75fc82583a41	788	rfalSetAnalogConfig( (RFAL_ANALOG_CONFIG_LISTEN \| RFAL_ANALOG_CONFIG_TECH_AP2P \| RFAL_ANALOG_CONFIG_BITRATE_COMMON \| RFAL_ANALOG_CONFIG_TX), mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	789	rfalSetAnalogConfig( (RFAL_ANALOG_CONFIG_LISTEN \| RFAL_ANALOG_CONFIG_TECH_AP2P \| RFAL_ANALOG_CONFIG_BITRATE_COMMON \| RFAL_ANALOG_CONFIG_RX), mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	790	break;
DiegoOstuni	0:75fc82583a41	791
DiegoOstuni	0:75fc82583a41	792	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	793	case RFAL_MODE_LISTEN_NFCA:
DiegoOstuni	0:75fc82583a41	794	case RFAL_MODE_LISTEN_NFCB:
DiegoOstuni	0:75fc82583a41	795	case RFAL_MODE_LISTEN_NFCF:
DiegoOstuni	0:75fc82583a41	796	return ERR_NOTSUPP;
DiegoOstuni	0:75fc82583a41	797
DiegoOstuni	0:75fc82583a41	798	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	799	default:
DiegoOstuni	0:75fc82583a41	800	return ERR_NOT_IMPLEMENTED;
DiegoOstuni	0:75fc82583a41	801	}
DiegoOstuni	0:75fc82583a41	802
DiegoOstuni	0:75fc82583a41	803	/* Set state as STATE_MODE_SET only if not initialized yet (PSL) */
DiegoOstuni	0:75fc82583a41	804	gRFAL.state = ((gRFAL.state < RFAL_STATE_MODE_SET) ? RFAL_STATE_MODE_SET : gRFAL.state);
DiegoOstuni	0:75fc82583a41	805	gRFAL.mode = mode;
DiegoOstuni	0:75fc82583a41	806
DiegoOstuni	0:75fc82583a41	807	/* Apply the given bit rate */
DiegoOstuni	0:75fc82583a41	808	return rfalSetBitRate(txBR, rxBR, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	809	}
DiegoOstuni	0:75fc82583a41	810
DiegoOstuni	0:75fc82583a41	811
DiegoOstuni	0:75fc82583a41	812	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	813	rfalMode rfalGetMode( void )
DiegoOstuni	0:75fc82583a41	814	{
DiegoOstuni	0:75fc82583a41	815	return gRFAL.mode;
DiegoOstuni	0:75fc82583a41	816	}
DiegoOstuni	0:75fc82583a41	817
DiegoOstuni	0:75fc82583a41	818
DiegoOstuni	0:75fc82583a41	819	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	820	ReturnCode rfalSetBitRate( rfalBitRate txBR, rfalBitRate rxBR, SPI* mspiChannel, ST25R3911* mST25, DigitalOut* gpio_cs, InterruptIn* IRQ, DigitalOut* fieldLED_01, DigitalOut* fieldLED_02, DigitalOut* fieldLED_03, DigitalOut* fieldLED_04, DigitalOut* fieldLED_05, DigitalOut* fieldLED_06 )
DiegoOstuni	0:75fc82583a41	821	{
DiegoOstuni	0:75fc82583a41	822	ReturnCode ret;
DiegoOstuni	0:75fc82583a41	823
DiegoOstuni	0:75fc82583a41	824	/* Check if RFAL is not initialized */
DiegoOstuni	0:75fc82583a41	825	if( gRFAL.state == RFAL_STATE_IDLE )
DiegoOstuni	0:75fc82583a41	826	{
DiegoOstuni	0:75fc82583a41	827	return ERR_WRONG_STATE;
DiegoOstuni	0:75fc82583a41	828	}
DiegoOstuni	0:75fc82583a41	829
DiegoOstuni	0:75fc82583a41	830	/* Store the new Bit Rates */
DiegoOstuni	0:75fc82583a41	831	gRFAL.txBR = ((txBR == RFAL_BR_KEEP) ? gRFAL.txBR : txBR);
DiegoOstuni	0:75fc82583a41	832	gRFAL.rxBR = ((rxBR == RFAL_BR_KEEP) ? gRFAL.rxBR : rxBR);
DiegoOstuni	0:75fc82583a41	833
DiegoOstuni	0:75fc82583a41	834	/* Update the bitrate reg if not in NFCV mode (streaming) */
DiegoOstuni	0:75fc82583a41	835	if( (RFAL_MODE_POLL_NFCV != gRFAL.mode) && (RFAL_MODE_POLL_PICOPASS != gRFAL.mode) )
DiegoOstuni	0:75fc82583a41	836	{
DiegoOstuni	0:75fc82583a41	837	EXIT_ON_ERR( ret, st25r3911SetBitrate( gRFAL.txBR, gRFAL.rxBR, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) );
DiegoOstuni	0:75fc82583a41	838	}
DiegoOstuni	0:75fc82583a41	839
DiegoOstuni	0:75fc82583a41	840
DiegoOstuni	0:75fc82583a41	841	switch( gRFAL.mode )
DiegoOstuni	0:75fc82583a41	842	{
DiegoOstuni	0:75fc82583a41	843	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	844	case RFAL_MODE_POLL_NFCA:
DiegoOstuni	0:75fc82583a41	845	case RFAL_MODE_POLL_NFCA_T1T:
DiegoOstuni	0:75fc82583a41	846
DiegoOstuni	0:75fc82583a41	847	/* Set Analog configurations for this bit rate */
DiegoOstuni	0:75fc82583a41	848	rfalSetAnalogConfig( (RFAL_ANALOG_CONFIG_POLL \| RFAL_ANALOG_CONFIG_TECH_NFCA \| rfalConvBR2ACBR(gRFAL.txBR) \| RFAL_ANALOG_CONFIG_TX ), mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	849	rfalSetAnalogConfig( (RFAL_ANALOG_CONFIG_POLL \| RFAL_ANALOG_CONFIG_TECH_NFCA \| rfalConvBR2ACBR(gRFAL.rxBR) \| RFAL_ANALOG_CONFIG_RX ), mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	850	break;
DiegoOstuni	0:75fc82583a41	851
DiegoOstuni	0:75fc82583a41	852	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	853	case RFAL_MODE_POLL_NFCB:
DiegoOstuni	0:75fc82583a41	854	case RFAL_MODE_POLL_B_PRIME:
DiegoOstuni	0:75fc82583a41	855	case RFAL_MODE_POLL_B_CTS:
DiegoOstuni	0:75fc82583a41	856
DiegoOstuni	0:75fc82583a41	857	/* Set Analog configurations for this bit rate */
DiegoOstuni	0:75fc82583a41	858	rfalSetAnalogConfig( (RFAL_ANALOG_CONFIG_POLL \| RFAL_ANALOG_CONFIG_TECH_NFCB \| rfalConvBR2ACBR(gRFAL.txBR) \| RFAL_ANALOG_CONFIG_TX ), mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	859	rfalSetAnalogConfig( (RFAL_ANALOG_CONFIG_POLL \| RFAL_ANALOG_CONFIG_TECH_NFCB \| rfalConvBR2ACBR(gRFAL.rxBR) \| RFAL_ANALOG_CONFIG_RX ), mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	860	break;
DiegoOstuni	0:75fc82583a41	861
DiegoOstuni	0:75fc82583a41	862	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	863	case RFAL_MODE_POLL_NFCF:
DiegoOstuni	0:75fc82583a41	864
DiegoOstuni	0:75fc82583a41	865	/* Set Analog configurations for this bit rate */
DiegoOstuni	0:75fc82583a41	866	rfalSetAnalogConfig( (RFAL_ANALOG_CONFIG_POLL \| RFAL_ANALOG_CONFIG_TECH_NFCF \| rfalConvBR2ACBR(gRFAL.txBR) \| RFAL_ANALOG_CONFIG_TX ), mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	867	rfalSetAnalogConfig( (RFAL_ANALOG_CONFIG_POLL \| RFAL_ANALOG_CONFIG_TECH_NFCF \| rfalConvBR2ACBR(gRFAL.rxBR) \| RFAL_ANALOG_CONFIG_RX ), mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	868	break;
DiegoOstuni	0:75fc82583a41	869
DiegoOstuni	0:75fc82583a41	870	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	871	case RFAL_MODE_POLL_NFCV:
DiegoOstuni	0:75fc82583a41	872	case RFAL_MODE_POLL_PICOPASS:
DiegoOstuni	0:75fc82583a41	873
DiegoOstuni	0:75fc82583a41	874	#if !RFAL_FEATURE_NFCV
DiegoOstuni	0:75fc82583a41	875	return ERR_DISABLED;
DiegoOstuni	0:75fc82583a41	876	#else
DiegoOstuni	0:75fc82583a41	877
DiegoOstuni	0:75fc82583a41	878	if( ((gRFAL.rxBR != RFAL_BR_26p48) && (gRFAL.rxBR != RFAL_BR_52p97)) \|\| ((gRFAL.txBR != RFAL_BR_1p66) && (gRFAL.txBR != RFAL_BR_26p48)) )
DiegoOstuni	0:75fc82583a41	879	{
DiegoOstuni	0:75fc82583a41	880	return ERR_PARAM;
DiegoOstuni	0:75fc82583a41	881	}
DiegoOstuni	0:75fc82583a41	882
DiegoOstuni	0:75fc82583a41	883	{
DiegoOstuni	0:75fc82583a41	884	const struct iso15693StreamConfig *stream_config;
DiegoOstuni	0:75fc82583a41	885	iso15693PhyConfig_t config;
DiegoOstuni	0:75fc82583a41	886
DiegoOstuni	0:75fc82583a41	887	config.coding = (( gRFAL.txBR == RFAL_BR_1p66 ) ? ISO15693_VCD_CODING_1_256 : ISO15693_VCD_CODING_1_4);
DiegoOstuni	0:75fc82583a41	888	config.fastMode = (( gRFAL.rxBR == RFAL_BR_52p97 ) ? true : false);
DiegoOstuni	0:75fc82583a41	889
DiegoOstuni	0:75fc82583a41	890	iso15693PhyConfigure(&config, &stream_config);
DiegoOstuni	0:75fc82583a41	891	st25r3911StreamConfigure((struct st25r3911StreamConfig*)stream_config, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	892	}
DiegoOstuni	0:75fc82583a41	893
DiegoOstuni	0:75fc82583a41	894	/* Set Analog configurations for this bit rate */
DiegoOstuni	0:75fc82583a41	895	rfalSetAnalogConfig( (RFAL_ANALOG_CONFIG_POLL \| RFAL_ANALOG_CONFIG_TECH_NFCV \| rfalConvBR2ACBR(gRFAL.txBR) \| RFAL_ANALOG_CONFIG_TX ), mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	896	rfalSetAnalogConfig( (RFAL_ANALOG_CONFIG_POLL \| RFAL_ANALOG_CONFIG_TECH_NFCV \| rfalConvBR2ACBR(gRFAL.rxBR) \| RFAL_ANALOG_CONFIG_RX ), mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	897	break;
DiegoOstuni	0:75fc82583a41	898
DiegoOstuni	0:75fc82583a41	899	#endif /* RFAL_FEATURE_NFCV */
DiegoOstuni	0:75fc82583a41	900
DiegoOstuni	0:75fc82583a41	901
DiegoOstuni	0:75fc82583a41	902	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	903	case RFAL_MODE_POLL_ACTIVE_P2P:
DiegoOstuni	0:75fc82583a41	904
DiegoOstuni	0:75fc82583a41	905	/* Set Analog configurations for this bit rate */
DiegoOstuni	0:75fc82583a41	906	rfalSetAnalogConfig( (RFAL_ANALOG_CONFIG_POLL \| RFAL_ANALOG_CONFIG_TECH_AP2P \| rfalConvBR2ACBR(gRFAL.txBR) \| RFAL_ANALOG_CONFIG_TX ), mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	907	rfalSetAnalogConfig( (RFAL_ANALOG_CONFIG_POLL \| RFAL_ANALOG_CONFIG_TECH_AP2P \| rfalConvBR2ACBR(gRFAL.rxBR) \| RFAL_ANALOG_CONFIG_RX ), mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	908	break;
DiegoOstuni	0:75fc82583a41	909
DiegoOstuni	0:75fc82583a41	910	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	911	case RFAL_MODE_LISTEN_ACTIVE_P2P:
DiegoOstuni	0:75fc82583a41	912
DiegoOstuni	0:75fc82583a41	913	/* Set Analog configurations for this bit rate */
DiegoOstuni	0:75fc82583a41	914	rfalSetAnalogConfig( (RFAL_ANALOG_CONFIG_LISTEN \| RFAL_ANALOG_CONFIG_TECH_AP2P \| rfalConvBR2ACBR(gRFAL.txBR) \| RFAL_ANALOG_CONFIG_TX ), mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	915	rfalSetAnalogConfig( (RFAL_ANALOG_CONFIG_LISTEN \| RFAL_ANALOG_CONFIG_TECH_AP2P \| rfalConvBR2ACBR(gRFAL.rxBR) \| RFAL_ANALOG_CONFIG_RX ), mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	916	break;
DiegoOstuni	0:75fc82583a41	917
DiegoOstuni	0:75fc82583a41	918	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	919	case RFAL_MODE_LISTEN_NFCA:
DiegoOstuni	0:75fc82583a41	920	case RFAL_MODE_LISTEN_NFCB:
DiegoOstuni	0:75fc82583a41	921	case RFAL_MODE_LISTEN_NFCF:
DiegoOstuni	0:75fc82583a41	922	case RFAL_MODE_NONE:
DiegoOstuni	0:75fc82583a41	923	return ERR_WRONG_STATE;
DiegoOstuni	0:75fc82583a41	924
DiegoOstuni	0:75fc82583a41	925	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	926	default:
DiegoOstuni	0:75fc82583a41	927	return ERR_NOT_IMPLEMENTED;
DiegoOstuni	0:75fc82583a41	928	}
DiegoOstuni	0:75fc82583a41	929
DiegoOstuni	0:75fc82583a41	930	return ERR_NONE;
DiegoOstuni	0:75fc82583a41	931	}
DiegoOstuni	0:75fc82583a41	932
DiegoOstuni	0:75fc82583a41	933
DiegoOstuni	0:75fc82583a41	934	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	935	ReturnCode rfalGetBitRate( rfalBitRate txBR, rfalBitRate rxBR )
DiegoOstuni	0:75fc82583a41	936	{
DiegoOstuni	0:75fc82583a41	937	if( (gRFAL.state == RFAL_STATE_IDLE) \|\| (gRFAL.mode == RFAL_MODE_NONE) )
DiegoOstuni	0:75fc82583a41	938	{
DiegoOstuni	0:75fc82583a41	939	return ERR_WRONG_STATE;
DiegoOstuni	0:75fc82583a41	940	}
DiegoOstuni	0:75fc82583a41	941
DiegoOstuni	0:75fc82583a41	942	if( txBR != NULL )
DiegoOstuni	0:75fc82583a41	943	{
DiegoOstuni	0:75fc82583a41	944	*txBR = gRFAL.txBR;
DiegoOstuni	0:75fc82583a41	945	}
DiegoOstuni	0:75fc82583a41	946
DiegoOstuni	0:75fc82583a41	947	if( rxBR != NULL )
DiegoOstuni	0:75fc82583a41	948	{
DiegoOstuni	0:75fc82583a41	949	*rxBR = gRFAL.rxBR;
DiegoOstuni	0:75fc82583a41	950	}
DiegoOstuni	0:75fc82583a41	951
DiegoOstuni	0:75fc82583a41	952	return ERR_NONE;
DiegoOstuni	0:75fc82583a41	953	}
DiegoOstuni	0:75fc82583a41	954
DiegoOstuni	0:75fc82583a41	955
DiegoOstuni	0:75fc82583a41	956	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	957	ReturnCode rfalSetModulatedRFO( uint8_t rfo, SPI* mspiChannel, ST25R3911* mST25, DigitalOut* gpio_cs, InterruptIn* IRQ, DigitalOut* fieldLED_01, DigitalOut* fieldLED_02, DigitalOut* fieldLED_03, DigitalOut* fieldLED_04, DigitalOut* fieldLED_05, DigitalOut* fieldLED_06 )
DiegoOstuni	0:75fc82583a41	958	{
DiegoOstuni	0:75fc82583a41	959	mST25->writeRegister( ST25R3911_REG_RFO_AM_ON_LEVEL, rfo, mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	960
DiegoOstuni	0:75fc82583a41	961	return ERR_NONE;
DiegoOstuni	0:75fc82583a41	962	}
DiegoOstuni	0:75fc82583a41	963
DiegoOstuni	0:75fc82583a41	964
DiegoOstuni	0:75fc82583a41	965	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	966	uint8_t rfalGetModulatedRFO( SPI* mspiChannel, ST25R3911* mST25, DigitalOut* gpio_cs, InterruptIn* IRQ, DigitalOut* fieldLED_01, DigitalOut* fieldLED_02, DigitalOut* fieldLED_03, DigitalOut* fieldLED_04, DigitalOut* fieldLED_05, DigitalOut* fieldLED_06 )
DiegoOstuni	0:75fc82583a41	967	{
DiegoOstuni	0:75fc82583a41	968	uint8_t ret;
DiegoOstuni	0:75fc82583a41	969
DiegoOstuni	0:75fc82583a41	970	mST25->readRegister(ST25R3911_REG_RFO_AM_ON_LEVEL, &ret, mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	971
DiegoOstuni	0:75fc82583a41	972	return ret;
DiegoOstuni	0:75fc82583a41	973	}
DiegoOstuni	0:75fc82583a41	974
DiegoOstuni	0:75fc82583a41	975
DiegoOstuni	0:75fc82583a41	976	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	977	ReturnCode rfalMeasureRF( uint8_t* result, SPI* mspiChannel, ST25R3911* mST25, DigitalOut* gpio_cs, InterruptIn* IRQ, DigitalOut* fieldLED_01, DigitalOut* fieldLED_02, DigitalOut* fieldLED_03, DigitalOut* fieldLED_04, DigitalOut* fieldLED_05, DigitalOut* fieldLED_06 )
DiegoOstuni	0:75fc82583a41	978	{
DiegoOstuni	0:75fc82583a41	979	st25r3911MeasureRF( result, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	980
DiegoOstuni	0:75fc82583a41	981	return ERR_NONE;
DiegoOstuni	0:75fc82583a41	982	}
DiegoOstuni	0:75fc82583a41	983
DiegoOstuni	0:75fc82583a41	984
DiegoOstuni	0:75fc82583a41	985	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	986	void rfalSetErrorHandling( rfalEHandling eHandling )
DiegoOstuni	0:75fc82583a41	987	{
DiegoOstuni	0:75fc82583a41	988	gRFAL.conf.eHandling = eHandling;
DiegoOstuni	0:75fc82583a41	989	}
DiegoOstuni	0:75fc82583a41	990
DiegoOstuni	0:75fc82583a41	991
DiegoOstuni	0:75fc82583a41	992	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	993	rfalEHandling rfalGetErrorHandling( void )
DiegoOstuni	0:75fc82583a41	994	{
DiegoOstuni	0:75fc82583a41	995	return gRFAL.conf.eHandling;
DiegoOstuni	0:75fc82583a41	996	}
DiegoOstuni	0:75fc82583a41	997
DiegoOstuni	0:75fc82583a41	998
DiegoOstuni	0:75fc82583a41	999	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	1000	void rfalSetFDTPoll( uint32_t FDTPoll )
DiegoOstuni	0:75fc82583a41	1001	{
DiegoOstuni	0:75fc82583a41	1002	gRFAL.timings.FDTPoll = MIN( FDTPoll, RFAL_ST25R3911_GPT_MAX_1FC );
DiegoOstuni	0:75fc82583a41	1003	}
DiegoOstuni	0:75fc82583a41	1004
DiegoOstuni	0:75fc82583a41	1005
DiegoOstuni	0:75fc82583a41	1006	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	1007	uint32_t rfalGetFDTPoll( void )
DiegoOstuni	0:75fc82583a41	1008	{
DiegoOstuni	0:75fc82583a41	1009	return gRFAL.timings.FDTPoll;
DiegoOstuni	0:75fc82583a41	1010	}
DiegoOstuni	0:75fc82583a41	1011
DiegoOstuni	0:75fc82583a41	1012
DiegoOstuni	0:75fc82583a41	1013	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	1014	void rfalSetFDTListen( uint32_t FDTListen )
DiegoOstuni	0:75fc82583a41	1015	{
DiegoOstuni	0:75fc82583a41	1016	gRFAL.timings.FDTListen = MIN( FDTListen, RFAL_ST25R3911_MRT_MAX_1FC);
DiegoOstuni	0:75fc82583a41	1017	}
DiegoOstuni	0:75fc82583a41	1018
DiegoOstuni	0:75fc82583a41	1019	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	1020	uint32_t rfalGetFDTListen( void )
DiegoOstuni	0:75fc82583a41	1021	{
DiegoOstuni	0:75fc82583a41	1022	return gRFAL.timings.FDTListen;
DiegoOstuni	0:75fc82583a41	1023	}
DiegoOstuni	0:75fc82583a41	1024
DiegoOstuni	0:75fc82583a41	1025	void rfalSetGT( uint32_t GT )
DiegoOstuni	0:75fc82583a41	1026	{
DiegoOstuni	0:75fc82583a41	1027	gRFAL.timings.GT = MIN( GT, RFAL_ST25R3911_GT_MAX_1FC );
DiegoOstuni	0:75fc82583a41	1028	}
DiegoOstuni	0:75fc82583a41	1029
DiegoOstuni	0:75fc82583a41	1030	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	1031	uint32_t rfalGetGT( void )
DiegoOstuni	0:75fc82583a41	1032	{
DiegoOstuni	0:75fc82583a41	1033	return gRFAL.timings.GT;
DiegoOstuni	0:75fc82583a41	1034	}
DiegoOstuni	0:75fc82583a41	1035
DiegoOstuni	0:75fc82583a41	1036	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	1037	bool rfalIsGTExpired( void )//check here the platform time
DiegoOstuni	0:75fc82583a41	1038	{
DiegoOstuni	0:75fc82583a41	1039	if( gRFAL.tmr.GT != RFAL_TIMING_NONE )
DiegoOstuni	0:75fc82583a41	1040	{
DiegoOstuni	0:75fc82583a41	1041	if( !rfalTimerisExpired( gRFAL.tmr.GT ) )
DiegoOstuni	0:75fc82583a41	1042	{
DiegoOstuni	0:75fc82583a41	1043	return false;
DiegoOstuni	0:75fc82583a41	1044	}
DiegoOstuni	0:75fc82583a41	1045	}
DiegoOstuni	0:75fc82583a41	1046	return true;
DiegoOstuni	0:75fc82583a41	1047	}
DiegoOstuni	0:75fc82583a41	1048
DiegoOstuni	0:75fc82583a41	1049	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	1050	ReturnCode rfalFieldOnAndStartGT( SPI mspiChannel, ST25R3911 mST25, DigitalOut* gpio_cs, InterruptIn* IRQ, DigitalOut* fieldLED_01, DigitalOut* fieldLED_02, DigitalOut* fieldLED_03, DigitalOut* fieldLED_04, DigitalOut* fieldLED_05, DigitalOut* fieldLED_06 )
DiegoOstuni	0:75fc82583a41	1051	{
DiegoOstuni	0:75fc82583a41	1052	ReturnCode ret;
DiegoOstuni	0:75fc82583a41	1053
DiegoOstuni	0:75fc82583a41	1054	/* Check if RFAL has been initialized (Oscillator should be running) and also
DiegoOstuni	0:75fc82583a41	1055	* if a direct register access has been performed and left the Oscillator Off */
DiegoOstuni	0:75fc82583a41	1056	if( (gRFAL.state < RFAL_STATE_INIT) \|\| !st25r3911CheckReg( ST25R3911_REG_OP_CONTROL, ST25R3911_REG_OP_CONTROL_en, ST25R3911_REG_OP_CONTROL_en, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) )
DiegoOstuni	0:75fc82583a41	1057	{
DiegoOstuni	0:75fc82583a41	1058	return ERR_WRONG_STATE;
DiegoOstuni	0:75fc82583a41	1059	}
DiegoOstuni	0:75fc82583a41	1060
DiegoOstuni	0:75fc82583a41	1061	ret = ERR_NONE;
DiegoOstuni	0:75fc82583a41	1062
DiegoOstuni	0:75fc82583a41	1063	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	1064	/* Perform collision avoidance and turn field On if not already On */
DiegoOstuni	0:75fc82583a41	1065	if( !gRFAL.field \|\| !( st25r3911CheckReg(ST25R3911_REG_OP_CONTROL, ST25R3911_REG_OP_CONTROL_tx_en, ST25R3911_REG_OP_CONTROL_tx_en, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ) )
DiegoOstuni	0:75fc82583a41	1066	{
DiegoOstuni	0:75fc82583a41	1067	/* Use Thresholds set by AnalogConfig */
DiegoOstuni	0:75fc82583a41	1068	ret = st25r3911PerformCollisionAvoidance( ST25R3911_CMD_RESPONSE_RF_COLLISION_0, ST25R3911_THRESHOLD_DO_NOT_SET, ST25R3911_THRESHOLD_DO_NOT_SET, 0, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	1069
DiegoOstuni	0:75fc82583a41	1070	gRFAL.field = ( st25r3911CheckReg(ST25R3911_REG_OP_CONTROL, ST25R3911_REG_OP_CONTROL_tx_en, ST25R3911_REG_OP_CONTROL_tx_en, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) );
DiegoOstuni	0:75fc82583a41	1071
DiegoOstuni	0:75fc82583a41	1072	/* Only turn on Receiver and Transmitter if field was successfully turned On */
DiegoOstuni	0:75fc82583a41	1073	if(gRFAL.field)
DiegoOstuni	0:75fc82583a41	1074	{
DiegoOstuni	0:75fc82583a41	1075	st25r3911TxRxOn( mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ; /* Enable Tx and Rx (Tx is already On) */
DiegoOstuni	0:75fc82583a41	1076	}
DiegoOstuni	0:75fc82583a41	1077	}
DiegoOstuni	0:75fc82583a41	1078
DiegoOstuni	0:75fc82583a41	1079	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	1080	/* Start GT timer in case the GT value is set */
DiegoOstuni	0:75fc82583a41	1081	if( (gRFAL.timings.GT != RFAL_TIMING_NONE) )
DiegoOstuni	0:75fc82583a41	1082	{
DiegoOstuni	0:75fc82583a41	1083	/* Ensure that a SW timer doesn't have a lower value then the minimum */
DiegoOstuni	0:75fc82583a41	1084	rfalTimerStart( gRFAL.tmr.GT, rfalConv1fcToMs( MAX( (gRFAL.timings.GT), RFAL_ST25R3911_GT_MIN_1FC) ) );
DiegoOstuni	0:75fc82583a41	1085	}
DiegoOstuni	0:75fc82583a41	1086
DiegoOstuni	0:75fc82583a41	1087	return ret;
DiegoOstuni	0:75fc82583a41	1088	}
DiegoOstuni	0:75fc82583a41	1089
DiegoOstuni	0:75fc82583a41	1090
DiegoOstuni	0:75fc82583a41	1091	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	1092	ReturnCode rfalFieldOff( SPI* mspiChannel, ST25R3911* mST25, DigitalOut* gpio_cs, InterruptIn* IRQ, DigitalOut* fieldLED_01, DigitalOut* fieldLED_02, DigitalOut* fieldLED_03, DigitalOut* fieldLED_04, DigitalOut* fieldLED_05, DigitalOut* fieldLED_06 )
DiegoOstuni	0:75fc82583a41	1093	{
DiegoOstuni	0:75fc82583a41	1094	/* Check whether a TxRx is not yet finished */
DiegoOstuni	0:75fc82583a41	1095	if( gRFAL.TxRx.state != RFAL_TXRX_STATE_IDLE )
DiegoOstuni	0:75fc82583a41	1096	{
DiegoOstuni	0:75fc82583a41	1097	rfalCleanupTransceive(mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	1098	}
DiegoOstuni	0:75fc82583a41	1099
DiegoOstuni	0:75fc82583a41	1100	/* Disable Tx and Rx */
DiegoOstuni	0:75fc82583a41	1101	st25r3911TxRxOff( mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	1102	gRFAL.field = false;
DiegoOstuni	0:75fc82583a41	1103
DiegoOstuni	0:75fc82583a41	1104	return ERR_NONE;
DiegoOstuni	0:75fc82583a41	1105	}
DiegoOstuni	0:75fc82583a41	1106
DiegoOstuni	0:75fc82583a41	1107
DiegoOstuni	0:75fc82583a41	1108	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	1109	ReturnCode rfalStartTransceive( rfalTransceiveContext ctx,SPI mspiChannel, ST25R3911* mST25, DigitalOut* gpio_cs, InterruptIn* IRQ, DigitalOut* fieldLED_01, DigitalOut* fieldLED_02, DigitalOut* fieldLED_03, DigitalOut* fieldLED_04, DigitalOut* fieldLED_05, DigitalOut* fieldLED_06 )
DiegoOstuni	0:75fc82583a41	1110	{
DiegoOstuni	0:75fc82583a41	1111	uint32_t FxTAdj; /* FWT or FDT adjustment calculation */
DiegoOstuni	0:75fc82583a41	1112
DiegoOstuni	0:75fc82583a41	1113	/* Ensure that RFAL is already Initialized and the mode has been set */
DiegoOstuni	0:75fc82583a41	1114	if( (gRFAL.state >= RFAL_STATE_MODE_SET) /&& (gRFAL.TxRx.state == RFAL_TXRX_STATE_INIT )/ )
DiegoOstuni	0:75fc82583a41	1115	{
DiegoOstuni	0:75fc82583a41	1116	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	1117	/* Check whether the field is already On, otherwise no TXE will be received */
DiegoOstuni	0:75fc82583a41	1118	if( !( st25r3911CheckReg(ST25R3911_REG_OP_CONTROL, ST25R3911_REG_OP_CONTROL_tx_en, ST25R3911_REG_OP_CONTROL_tx_en, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) )
DiegoOstuni	0:75fc82583a41	1119	&& (!rfalIsModePassiveListen( gRFAL.mode ) && (ctx->txBuf != NULL)) )
DiegoOstuni	0:75fc82583a41	1120	{
DiegoOstuni	0:75fc82583a41	1121	return ERR_WRONG_STATE;
DiegoOstuni	0:75fc82583a41	1122	}
DiegoOstuni	0:75fc82583a41	1123
DiegoOstuni	0:75fc82583a41	1124	gRFAL.TxRx.ctx = *ctx;
DiegoOstuni	0:75fc82583a41	1125
DiegoOstuni	0:75fc82583a41	1126	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	1127	if( gRFAL.timings.FDTListen != RFAL_TIMING_NONE )
DiegoOstuni	0:75fc82583a41	1128	{
DiegoOstuni	0:75fc82583a41	1129	/* Calculate MRT adjustment accordingly to the current mode */
DiegoOstuni	0:75fc82583a41	1130	FxTAdj = RFAL_FDT_LISTEN_MRT_ADJUSTMENT;
DiegoOstuni	0:75fc82583a41	1131	if(gRFAL.mode == RFAL_MODE_POLL_NFCA) FxTAdj += RFAL_FDT_LISTEN_A_ADJUSTMENT;
DiegoOstuni	0:75fc82583a41	1132	else if(gRFAL.mode == RFAL_MODE_POLL_NFCA_T1T) FxTAdj += RFAL_FDT_LISTEN_A_ADJUSTMENT;
DiegoOstuni	0:75fc82583a41	1133	else if(gRFAL.mode == RFAL_MODE_POLL_NFCB) FxTAdj += RFAL_FDT_LISTEN_B_ADJUSTMENT;
DiegoOstuni	0:75fc82583a41	1134
DiegoOstuni	0:75fc82583a41	1135
DiegoOstuni	0:75fc82583a41	1136	/* Set Minimum FDT(Listen) in which PICC is not allowed to send a response */
DiegoOstuni	0:75fc82583a41	1137	mST25 -> writeRegister( ST25R3911_REG_MASK_RX_TIMER, rfalConv1fcTo64fc( (FxTAdj > gRFAL.timings.FDTListen) ? RFAL_ST25R3911_MRT_MIN_1FC : (gRFAL.timings.FDTListen - FxTAdj) ), mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 );
DiegoOstuni	0:75fc82583a41	1138	}
DiegoOstuni	0:75fc82583a41	1139
DiegoOstuni	0:75fc82583a41	1140	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	1141	/* FDT Poll will be loaded in rfalPrepareTransceive() once the previous was expired */
DiegoOstuni	0:75fc82583a41	1142
DiegoOstuni	0:75fc82583a41	1143	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	1144	if( rfalIsModePassiveComm( gRFAL.mode ) ) /* Passive Comms */
DiegoOstuni	0:75fc82583a41	1145	{
DiegoOstuni	0:75fc82583a41	1146	if( (gRFAL.TxRx.ctx.fwt != RFAL_FWT_NONE) && (gRFAL.TxRx.ctx.fwt != 0) )
DiegoOstuni	0:75fc82583a41	1147	{
DiegoOstuni	0:75fc82583a41	1148	FxTAdj = RFAL_FWT_ADJUSTMENT;
DiegoOstuni	0:75fc82583a41	1149	if(gRFAL.mode == RFAL_MODE_POLL_NFCA) FxTAdj += RFAL_FWT_A_ADJUSTMENT;
DiegoOstuni	0:75fc82583a41	1150	else if(gRFAL.mode == RFAL_MODE_POLL_NFCA_T1T) FxTAdj += RFAL_FWT_A_ADJUSTMENT;
DiegoOstuni	0:75fc82583a41	1151	else if(gRFAL.mode == RFAL_MODE_POLL_NFCB) FxTAdj += RFAL_FWT_B_ADJUSTMENT;
DiegoOstuni	0:75fc82583a41	1152	else if(gRFAL.mode == RFAL_MODE_POLL_NFCF)
DiegoOstuni	0:75fc82583a41	1153	{
DiegoOstuni	0:75fc82583a41	1154	FxTAdj += ((gRFAL.txBR == RFAL_BR_212) ? RFAL_FWT_F_212_ADJUSTMENT : RFAL_FWT_F_424_ADJUSTMENT );
DiegoOstuni	0:75fc82583a41	1155	}
DiegoOstuni	0:75fc82583a41	1156
DiegoOstuni	0:75fc82583a41	1157	/* Ensure that the given FWT doesn't exceed NRT maximum */
DiegoOstuni	0:75fc82583a41	1158	gRFAL.TxRx.ctx.fwt = MIN( (gRFAL.TxRx.ctx.fwt + FxTAdj), RFAL_ST25R3911_NRT_MAX_1FC );
DiegoOstuni	0:75fc82583a41	1159
DiegoOstuni	0:75fc82583a41	1160	/* Set FWT in the NRT */
DiegoOstuni	0:75fc82583a41	1161	st25r3911SetNoResponseTime_64fcs( rfalConv1fcTo64fc( gRFAL.TxRx.ctx.fwt ), mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	1162	}
DiegoOstuni	0:75fc82583a41	1163	else
DiegoOstuni	0:75fc82583a41	1164	{
DiegoOstuni	0:75fc82583a41	1165	/* Disable NRT, no NRE will be triggered, therefore wait endlessly for Rx */
DiegoOstuni	0:75fc82583a41	1166	st25r3911SetNoResponseTime_64fcs( RFAL_ST25R3911_NRT_DISABLED, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	1167	}
DiegoOstuni	0:75fc82583a41	1168	}
DiegoOstuni	0:75fc82583a41	1169	else /* Active Comms */
DiegoOstuni	0:75fc82583a41	1170	{
DiegoOstuni	0:75fc82583a41	1171	/* Setup NRT timer for rf response RF collision timeout. */
DiegoOstuni	0:75fc82583a41	1172	st25r3911SetNoResponseTime_64fcs( rfalConv1fcTo64fc(RFAL_AP2P_FIELDON_TADTTRFW), mspiChannel, mST25, gpio_cs, IRQ , fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 );
DiegoOstuni	0:75fc82583a41	1173
DiegoOstuni	0:75fc82583a41	1174	/* In Active Mode No Response Timer cannot be used to measure FWT a SW timer is used instead */
DiegoOstuni	0:75fc82583a41	1175	}
DiegoOstuni	0:75fc82583a41	1176
DiegoOstuni	0:75fc82583a41	1177	gRFAL.state = RFAL_STATE_TXRX;
DiegoOstuni	0:75fc82583a41	1178	gRFAL.TxRx.state = RFAL_TXRX_STATE_TX_IDLE;
DiegoOstuni	0:75fc82583a41	1179	gRFAL.TxRx.status = ERR_BUSY;
DiegoOstuni	0:75fc82583a41	1180	gRFAL.TxRx.rxse = false;
DiegoOstuni	0:75fc82583a41	1181
DiegoOstuni	0:75fc82583a41	1182	#if RFAL_FEATURE_NFCV
DiegoOstuni	0:75fc82583a41	1183	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	1184	if( (RFAL_MODE_POLL_NFCV == gRFAL.mode) \|\| (RFAL_MODE_POLL_PICOPASS == gRFAL.mode) )
DiegoOstuni	0:75fc82583a41	1185	{ /* Exchange receive buffer with internal buffer */
DiegoOstuni	0:75fc82583a41	1186	gRFAL.nfcvData.origCtx = gRFAL.TxRx.ctx;
DiegoOstuni	0:75fc82583a41	1187
DiegoOstuni	0:75fc82583a41	1188	gRFAL.TxRx.ctx.rxBuf = ((gRFAL.nfcvData.origCtx.rxBuf != NULL) ? gRFAL.nfcvData.codingBuffer : NULL);
DiegoOstuni	0:75fc82583a41	1189	gRFAL.TxRx.ctx.rxBufLen = rfalConvBytesToBits(sizeof(gRFAL.nfcvData.codingBuffer));
DiegoOstuni	0:75fc82583a41	1190	gRFAL.TxRx.ctx.flags = RFAL_TXRX_FLAGS_CRC_TX_MANUAL
DiegoOstuni	0:75fc82583a41	1191	\| RFAL_TXRX_FLAGS_CRC_RX_KEEP
DiegoOstuni	0:75fc82583a41	1192	\| RFAL_TXRX_FLAGS_NFCIP1_OFF
DiegoOstuni	0:75fc82583a41	1193	\| (gRFAL.nfcvData.origCtx.flags & RFAL_TXRX_FLAGS_AGC_OFF)
DiegoOstuni	0:75fc82583a41	1194	\| RFAL_TXRX_FLAGS_PAR_RX_KEEP
DiegoOstuni	0:75fc82583a41	1195	\| RFAL_TXRX_FLAGS_PAR_TX_NONE;
DiegoOstuni	0:75fc82583a41	1196	/* In NFCV a transceive with valid txBuf and txBufSize==0 should send first an EOF.
DiegoOstuni	0:75fc82583a41	1197	In this case avoid below code for going directly into receive. */
DiegoOstuni	0:75fc82583a41	1198	if (gRFAL.TxRx.ctx.txBuf) return ERR_NONE;
DiegoOstuni	0:75fc82583a41	1199	}
DiegoOstuni	0:75fc82583a41	1200	#endif /* RFAL_FEATURE_NFCV */
DiegoOstuni	0:75fc82583a41	1201
DiegoOstuni	0:75fc82583a41	1202
DiegoOstuni	0:75fc82583a41	1203	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	1204	/* Check if the Transceive start performing Tx or goes directly to Rx */
DiegoOstuni	0:75fc82583a41	1205	if( (gRFAL.TxRx.ctx.txBuf == NULL) \|\| (gRFAL.TxRx.ctx.txBufLen == 0) )
DiegoOstuni	0:75fc82583a41	1206	{
DiegoOstuni	0:75fc82583a41	1207	/* Disable our field upon a Rx reEnable on AP2P */
DiegoOstuni	0:75fc82583a41	1208	if( rfalIsModeActiveComm(gRFAL.mode) )
DiegoOstuni	0:75fc82583a41	1209	{
DiegoOstuni	0:75fc82583a41	1210	st25r3911ClrRegisterBits((unsigned char)(ST25R3911_REG_OP_CONTROL),(unsigned char)(ST25R3911_REG_OP_CONTROL_tx_en), mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	1211	}
DiegoOstuni	0:75fc82583a41	1212
DiegoOstuni	0:75fc82583a41	1213	/* Clear FIFO, Clear and Enable the Interrupts */
DiegoOstuni	0:75fc82583a41	1214	rfalPrepareTransceive( mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	1215
DiegoOstuni	0:75fc82583a41	1216	/* No Tx done, enable the Receiver */
DiegoOstuni	0:75fc82583a41	1217	mST25 -> executeCommand( ST25R3911_CMD_UNMASK_RECEIVE_DATA, mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	1218
DiegoOstuni	0:75fc82583a41	1219	/* Start NRT manually, if FWT = 0 (wait endlessly for Rx) chip will ignore anyhow */
DiegoOstuni	0:75fc82583a41	1220	mST25 -> executeCommand( ST25R3911_CMD_START_NO_RESPONSE_TIMER, mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	1221
DiegoOstuni	0:75fc82583a41	1222	gRFAL.TxRx.state = RFAL_TXRX_STATE_RX_IDLE;
DiegoOstuni	0:75fc82583a41	1223	}
DiegoOstuni	0:75fc82583a41	1224
DiegoOstuni	0:75fc82583a41	1225	return ERR_NONE;
DiegoOstuni	0:75fc82583a41	1226	}
DiegoOstuni	0:75fc82583a41	1227
DiegoOstuni	0:75fc82583a41	1228	return ERR_WRONG_STATE;
DiegoOstuni	0:75fc82583a41	1229	}
DiegoOstuni	0:75fc82583a41	1230
DiegoOstuni	0:75fc82583a41	1231
DiegoOstuni	0:75fc82583a41	1232	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	1233	ReturnCode rfalTransceiveBlockingTx( uint8_t* txBuf, uint16_t txBufLen, uint8_t* rxBuf, uint16_t rxBufLen, uint16_t* actLen, uint32_t flags, uint32_t fwt, SPI* mspiChannel, ST25R3911* mST25, DigitalOut* gpio_cs, InterruptIn* IRQ, DigitalOut* fieldLED_01, DigitalOut* fieldLED_02, DigitalOut* fieldLED_03, DigitalOut* fieldLED_04, DigitalOut* fieldLED_05, DigitalOut* fieldLED_06 )
DiegoOstuni	0:75fc82583a41	1234	{
DiegoOstuni	0:75fc82583a41	1235	ReturnCode ret;
DiegoOstuni	0:75fc82583a41	1236	rfalTransceiveContext ctx;
DiegoOstuni	0:75fc82583a41	1237
DiegoOstuni	0:75fc82583a41	1238	rfalCreateByteFlagsTxRxContext( ctx, txBuf, txBufLen, rxBuf, rxBufLen, actLen, flags, fwt );
DiegoOstuni	0:75fc82583a41	1239	EXIT_ON_ERR( ret, rfalStartTransceive( &ctx, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) );
DiegoOstuni	0:75fc82583a41	1240
DiegoOstuni	0:75fc82583a41	1241	return rfalTransceiveRunBlockingTx( mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	1242	}
DiegoOstuni	0:75fc82583a41	1243
DiegoOstuni	0:75fc82583a41	1244
DiegoOstuni	0:75fc82583a41	1245	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	1246	static ReturnCode rfalTransceiveRunBlockingTx( SPI* mspiChannel, ST25R3911* mST25, DigitalOut* gpio_cs, InterruptIn* IRQ, DigitalOut* fieldLED_01, DigitalOut* fieldLED_02, DigitalOut* fieldLED_03, DigitalOut* fieldLED_04, DigitalOut* fieldLED_05, DigitalOut* fieldLED_06 )
DiegoOstuni	0:75fc82583a41	1247	{
DiegoOstuni	0:75fc82583a41	1248	ReturnCode ret;
DiegoOstuni	0:75fc82583a41	1249
DiegoOstuni	0:75fc82583a41	1250	do{
DiegoOstuni	0:75fc82583a41	1251	rfalWorker(mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	1252	}
DiegoOstuni	0:75fc82583a41	1253	while( ((ret = rfalGetTransceiveStatus() ) == ERR_BUSY) && rfalIsTransceiveInTx() );
DiegoOstuni	0:75fc82583a41	1254
DiegoOstuni	0:75fc82583a41	1255	if( rfalIsTransceiveInRx() )
DiegoOstuni	0:75fc82583a41	1256	{
DiegoOstuni	0:75fc82583a41	1257	return ERR_NONE;
DiegoOstuni	0:75fc82583a41	1258	}
DiegoOstuni	0:75fc82583a41	1259
DiegoOstuni	0:75fc82583a41	1260	return ret;
DiegoOstuni	0:75fc82583a41	1261	}
DiegoOstuni	0:75fc82583a41	1262
DiegoOstuni	0:75fc82583a41	1263
DiegoOstuni	0:75fc82583a41	1264	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	1265	ReturnCode rfalTransceiveBlockingRx( SPI* mspiChannel, ST25R3911* mST25, DigitalOut* gpio_cs, InterruptIn* IRQ, DigitalOut* fieldLED_01, DigitalOut* fieldLED_02, DigitalOut* fieldLED_03, DigitalOut* fieldLED_04, DigitalOut* fieldLED_05, DigitalOut* fieldLED_06 )
DiegoOstuni	0:75fc82583a41	1266	{
DiegoOstuni	0:75fc82583a41	1267	ReturnCode ret;
DiegoOstuni	0:75fc82583a41	1268
DiegoOstuni	0:75fc82583a41	1269	do{
DiegoOstuni	0:75fc82583a41	1270	rfalWorker( mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	1271	}
DiegoOstuni	0:75fc82583a41	1272	while( ((ret = rfalGetTransceiveStatus() ) == ERR_BUSY) && rfalIsTransceiveInRx() );
DiegoOstuni	0:75fc82583a41	1273
DiegoOstuni	0:75fc82583a41	1274	return ret;
DiegoOstuni	0:75fc82583a41	1275	}
DiegoOstuni	0:75fc82583a41	1276
DiegoOstuni	0:75fc82583a41	1277
DiegoOstuni	0:75fc82583a41	1278	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	1279	ReturnCode rfalTransceiveBlockingTxRx( uint8_t* txBuf, uint16_t txBufLen,
DiegoOstuni	0:75fc82583a41	1280	uint8_t* rxBuf, uint16_t rxBufLen, uint16_t* actLen, uint32_t flags,
DiegoOstuni	0:75fc82583a41	1281	uint32_t fwt, SPI* mspiChannel, ST25R3911* mST25, DigitalOut* gpio_cs, InterruptIn* IRQ, DigitalOut* fieldLED_01, DigitalOut* fieldLED_02, DigitalOut* fieldLED_03, DigitalOut* fieldLED_04, DigitalOut* fieldLED_05, DigitalOut* fieldLED_06 )
DiegoOstuni	0:75fc82583a41	1282	{
DiegoOstuni	0:75fc82583a41	1283	ReturnCode ret;
DiegoOstuni	0:75fc82583a41	1284
DiegoOstuni	0:75fc82583a41	1285	EXIT_ON_ERR( ret, rfalTransceiveBlockingTx( txBuf, txBufLen, rxBuf, rxBufLen, actLen, flags, fwt, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) );
DiegoOstuni	0:75fc82583a41	1286	ret = rfalTransceiveBlockingRx( mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 );
DiegoOstuni	0:75fc82583a41	1287
DiegoOstuni	0:75fc82583a41	1288	/* Convert received bits to bytes */
DiegoOstuni	0:75fc82583a41	1289	if( actLen != NULL )
DiegoOstuni	0:75fc82583a41	1290	{
DiegoOstuni	0:75fc82583a41	1291	actLen = rfalConvBitsToBytes(actLen);
DiegoOstuni	0:75fc82583a41	1292	}
DiegoOstuni	0:75fc82583a41	1293
DiegoOstuni	0:75fc82583a41	1294	return ret;
DiegoOstuni	0:75fc82583a41	1295	}
DiegoOstuni	0:75fc82583a41	1296
DiegoOstuni	0:75fc82583a41	1297
DiegoOstuni	0:75fc82583a41	1298	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	1299	static ReturnCode rfalRunTransceiveWorker( SPI* mspiChannel, ST25R3911* mST25, DigitalOut* gpio_cs, InterruptIn* IRQ, DigitalOut* fieldLED_01, DigitalOut* fieldLED_02, DigitalOut* fieldLED_03, DigitalOut* fieldLED_04, DigitalOut* fieldLED_05, DigitalOut* fieldLED_06 )
DiegoOstuni	0:75fc82583a41	1300	{
DiegoOstuni	0:75fc82583a41	1301	if( gRFAL.state == RFAL_STATE_TXRX )
DiegoOstuni	0:75fc82583a41	1302	{
DiegoOstuni	0:75fc82583a41	1303	/* Run Tx or Rx state machines */
DiegoOstuni	0:75fc82583a41	1304	if( rfalIsTransceiveInTx() )
DiegoOstuni	0:75fc82583a41	1305	{
DiegoOstuni	0:75fc82583a41	1306	rfalTransceiveTx( mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	1307	return rfalGetTransceiveStatus();
DiegoOstuni	0:75fc82583a41	1308	}
DiegoOstuni	0:75fc82583a41	1309	else if( rfalIsTransceiveInRx() )
DiegoOstuni	0:75fc82583a41	1310	{
DiegoOstuni	0:75fc82583a41	1311	rfalTransceiveRx( mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	1312	return rfalGetTransceiveStatus();
DiegoOstuni	0:75fc82583a41	1313	}
DiegoOstuni	0:75fc82583a41	1314	}
DiegoOstuni	0:75fc82583a41	1315	return ERR_WRONG_STATE;
DiegoOstuni	0:75fc82583a41	1316	}
DiegoOstuni	0:75fc82583a41	1317
DiegoOstuni	0:75fc82583a41	1318	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	1319	rfalTransceiveState rfalGetTransceiveState( void )
DiegoOstuni	0:75fc82583a41	1320	{
DiegoOstuni	0:75fc82583a41	1321	return gRFAL.TxRx.state;
DiegoOstuni	0:75fc82583a41	1322	}
DiegoOstuni	0:75fc82583a41	1323
DiegoOstuni	0:75fc82583a41	1324	ReturnCode rfalGetTransceiveStatus( void )
DiegoOstuni	0:75fc82583a41	1325	{
DiegoOstuni	0:75fc82583a41	1326	uint16_t ERR = uint16_t(ERR_BUSY);
DiegoOstuni	0:75fc82583a41	1327	return ((gRFAL.TxRx.state == RFAL_TXRX_STATE_IDLE) ? gRFAL.TxRx.status : ERR);
DiegoOstuni	0:75fc82583a41	1328	}
DiegoOstuni	0:75fc82583a41	1329
DiegoOstuni	0:75fc82583a41	1330
DiegoOstuni	0:75fc82583a41	1331	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	1332	void rfalWorker( SPI* mspiChannel, ST25R3911* mST25, DigitalOut* gpio_cs, InterruptIn* IRQ, DigitalOut* fieldLED_01, DigitalOut* fieldLED_02, DigitalOut* fieldLED_03, DigitalOut* fieldLED_04, DigitalOut* fieldLED_05, DigitalOut* fieldLED_06 )
DiegoOstuni	0:75fc82583a41	1333	{
DiegoOstuni	0:75fc82583a41	1334	switch( gRFAL.state )
DiegoOstuni	0:75fc82583a41	1335	{
DiegoOstuni	0:75fc82583a41	1336	case RFAL_STATE_TXRX:
DiegoOstuni	0:75fc82583a41	1337	rfalRunTransceiveWorker( mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	1338	break;
DiegoOstuni	0:75fc82583a41	1339
DiegoOstuni	0:75fc82583a41	1340	case RFAL_STATE_LM:
DiegoOstuni	0:75fc82583a41	1341	rfalRunListenModeWorker( mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	1342	break;
DiegoOstuni	0:75fc82583a41	1343
DiegoOstuni	0:75fc82583a41	1344	case RFAL_STATE_WUM:
DiegoOstuni	0:75fc82583a41	1345	rfalRunWakeUpModeWorker(mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	1346	break;
DiegoOstuni	0:75fc82583a41	1347
DiegoOstuni	0:75fc82583a41	1348	/* Nothing to be done */
DiegoOstuni	0:75fc82583a41	1349	default:
DiegoOstuni	0:75fc82583a41	1350	break;
DiegoOstuni	0:75fc82583a41	1351	}
DiegoOstuni	0:75fc82583a41	1352	}
DiegoOstuni	0:75fc82583a41	1353
DiegoOstuni	0:75fc82583a41	1354
DiegoOstuni	0:75fc82583a41	1355	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	1356	static void rfalErrorHandling( ST25R3911* mST25, SPI * mspiChannel, DigitalOut* gpio_cs, InterruptIn* IRQ, DigitalOut* fieldLED_01, DigitalOut* fieldLED_02, DigitalOut* fieldLED_03, DigitalOut* fieldLED_04, DigitalOut* fieldLED_05, DigitalOut* fieldLED_06 )
DiegoOstuni	0:75fc82583a41	1357	{
DiegoOstuni	0:75fc82583a41	1358	uint8_t fifoBytesToRead;
DiegoOstuni	0:75fc82583a41	1359	uint8_t reEnRx[] = { ST25R3911_CMD_CLEAR_FIFO, ST25R3911_CMD_UNMASK_RECEIVE_DATA };
DiegoOstuni	0:75fc82583a41	1360
DiegoOstuni	0:75fc82583a41	1361
DiegoOstuni	0:75fc82583a41	1362	fifoBytesToRead = rfalFIFOStatusGetNumBytes(mST25, mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	1363
DiegoOstuni	0:75fc82583a41	1364
DiegoOstuni	0:75fc82583a41	1365	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	1366	/* EMVCo */
DiegoOstuni	0:75fc82583a41	1367	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	1368	if( gRFAL.conf.eHandling == RFAL_ERRORHANDLING_EMVCO )
DiegoOstuni	0:75fc82583a41	1369	{
DiegoOstuni	0:75fc82583a41	1370	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	1371	/* EMD Handling - NFC Forum Digital 1.1 4.1.1.1 ; EMVCo 2.6 4.9.2 */
DiegoOstuni	0:75fc82583a41	1372	/* ReEnable the receiver on frames with a length < 4 bytes, upon: */
DiegoOstuni	0:75fc82583a41	1373	/* - Collision or Framing error detected */
DiegoOstuni	0:75fc82583a41	1374	/* - Residual bits are detected (hard framing error) */
DiegoOstuni	0:75fc82583a41	1375	/* - Parity error */
DiegoOstuni	0:75fc82583a41	1376	/* - CRC error */
DiegoOstuni	0:75fc82583a41	1377	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	1378
DiegoOstuni	0:75fc82583a41	1379	/* In case there are residual bits decrement FIFO bytes */
DiegoOstuni	0:75fc82583a41	1380	if( rfalFIFOStatusIsIncompleteByte(mST25, mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) \|\| rfalFIFOStatusIsMissingPar(mST25, mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) )
DiegoOstuni	0:75fc82583a41	1381	{
DiegoOstuni	0:75fc82583a41	1382	fifoBytesToRead--;
DiegoOstuni	0:75fc82583a41	1383	}
DiegoOstuni	0:75fc82583a41	1384
DiegoOstuni	0:75fc82583a41	1385	if( ( (gRFAL.fifo.bytesTotal + fifoBytesToRead) < RFAL_EMVCO_RX_MAXLEN ) &&
DiegoOstuni	0:75fc82583a41	1386	( (gRFAL.TxRx.status == ERR_RF_COLLISION) \|\| (gRFAL.TxRx.status == ERR_FRAMING) \|\|
DiegoOstuni	0:75fc82583a41	1387	(gRFAL.TxRx.status == ERR_PAR) \|\| (gRFAL.TxRx.status == ERR_CRC) \|\|
DiegoOstuni	0:75fc82583a41	1388	rfalFIFOStatusIsIncompleteByte(mST25, mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) \|\| rfalFIFOStatusIsMissingPar(mST25, mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ) )
DiegoOstuni	0:75fc82583a41	1389	{
DiegoOstuni	0:75fc82583a41	1390	/* Ignore this reception, ReEnable receiver */
DiegoOstuni	0:75fc82583a41	1391	mST25 -> executeCommands( reEnRx, sizeof(reEnRx), mST25, mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	1392
DiegoOstuni	0:75fc82583a41	1393	rfalFIFOStatusClear();
DiegoOstuni	0:75fc82583a41	1394	gRFAL.fifo.bytesTotal = 0;
DiegoOstuni	0:75fc82583a41	1395	gRFAL.TxRx.status = ERR_BUSY;
DiegoOstuni	0:75fc82583a41	1396	gRFAL.TxRx.state = RFAL_TXRX_STATE_RX_WAIT_RXS;
DiegoOstuni	0:75fc82583a41	1397	}
DiegoOstuni	0:75fc82583a41	1398	return;
DiegoOstuni	0:75fc82583a41	1399	}
DiegoOstuni	0:75fc82583a41	1400
DiegoOstuni	0:75fc82583a41	1401	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	1402	/* ISO14443A Mode */
DiegoOstuni	0:75fc82583a41	1403	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	1404	if( gRFAL.mode == RFAL_MODE_POLL_NFCA )
DiegoOstuni	0:75fc82583a41	1405	{
DiegoOstuni	0:75fc82583a41	1406
DiegoOstuni	0:75fc82583a41	1407	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	1408	/* If we received one incomplete byte (not a block and a incomplete byte at *
DiegoOstuni	0:75fc82583a41	1409	* the end) we`ll raise a specific error ( support for T2T 4 bit ACK / NAK ) *
DiegoOstuni	0:75fc82583a41	1410	* Otherwise just leave it as an CRC/FRAMING/PAR error */
DiegoOstuni	0:75fc82583a41	1411	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	1412	if( (gRFAL.TxRx.status == ERR_PAR) \|\| (gRFAL.TxRx.status == ERR_CRC) )
DiegoOstuni	0:75fc82583a41	1413	{
DiegoOstuni	0:75fc82583a41	1414	if( rfalFIFOStatusIsIncompleteByte(mST25, mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) && (fifoBytesToRead == RFAL_NFC_RX_INCOMPLETE_LEN) )
DiegoOstuni	0:75fc82583a41	1415	{
DiegoOstuni	0:75fc82583a41	1416	mST25 -> readFifo( (uint8_t*)(gRFAL.TxRx.ctx.rxBuf), fifoBytesToRead, mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	1417	if( gRFAL.TxRx.ctx.rxRcvdLen ) *gRFAL.TxRx.ctx.rxRcvdLen = rfalFIFOGetNumIncompleteBits(mST25, mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	1418
DiegoOstuni	0:75fc82583a41	1419	gRFAL.TxRx.status = ERR_INCOMPLETE_BYTE;
DiegoOstuni	0:75fc82583a41	1420	gRFAL.TxRx.state = RFAL_TXRX_STATE_RX_FAIL;
DiegoOstuni	0:75fc82583a41	1421	}
DiegoOstuni	0:75fc82583a41	1422	}
DiegoOstuni	0:75fc82583a41	1423	}
DiegoOstuni	0:75fc82583a41	1424
DiegoOstuni	0:75fc82583a41	1425	}
DiegoOstuni	0:75fc82583a41	1426
DiegoOstuni	0:75fc82583a41	1427
DiegoOstuni	0:75fc82583a41	1428	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	1429	static void rfalCleanupTransceive( SPI* mspiChannel, ST25R3911* mST25, DigitalOut* gpio_cs, InterruptIn* IRQ, DigitalOut* fieldLED_01, DigitalOut* fieldLED_02, DigitalOut* fieldLED_03, DigitalOut* fieldLED_04, DigitalOut* fieldLED_05, DigitalOut* fieldLED_06 )
DiegoOstuni	0:75fc82583a41	1430	{
DiegoOstuni	0:75fc82583a41	1431	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	1432	/* Transceive flags */
DiegoOstuni	0:75fc82583a41	1433	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	1434
DiegoOstuni	0:75fc82583a41	1435	/* Restore default settings on NFCIP1 mode, Receiving parity + CRC bits and manual Tx Parity*/
DiegoOstuni	0:75fc82583a41	1436	st25r3911ClrRegisterBits( ST25R3911_REG_ISO14443A_NFC, (ST25R3911_REG_ISO14443A_NFC_no_tx_par \| ST25R3911_REG_ISO14443A_NFC_no_rx_par \| ST25R3911_REG_ISO14443A_NFC_nfc_f0),mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	1437
DiegoOstuni	0:75fc82583a41	1438	/* Restore AGC enabled */
DiegoOstuni	0:75fc82583a41	1439	st25r3911SetRegisterBits( ST25R3911_REG_RX_CONF2, ST25R3911_REG_RX_CONF2_agc_en, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	1440
DiegoOstuni	0:75fc82583a41	1441	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	1442
DiegoOstuni	0:75fc82583a41	1443
DiegoOstuni	0:75fc82583a41	1444
DiegoOstuni	0:75fc82583a41	1445	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	1446	/* Execute Post Transceive Callback */
DiegoOstuni	0:75fc82583a41	1447	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	1448	if( gRFAL.callbacks.postTxRx != NULL )
DiegoOstuni	0:75fc82583a41	1449	{
DiegoOstuni	0:75fc82583a41	1450	gRFAL.callbacks.postTxRx();
DiegoOstuni	0:75fc82583a41	1451	}
DiegoOstuni	0:75fc82583a41	1452	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	1453
DiegoOstuni	0:75fc82583a41	1454	}
DiegoOstuni	0:75fc82583a41	1455
DiegoOstuni	0:75fc82583a41	1456
DiegoOstuni	0:75fc82583a41	1457	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	1458	static void rfalPrepareTransceive( SPI* mspiChannel, ST25R3911* mST25, DigitalOut* gpio_cs, InterruptIn* IRQ, DigitalOut* fieldLED_01, DigitalOut* fieldLED_02, DigitalOut* fieldLED_03, DigitalOut* fieldLED_04, DigitalOut* fieldLED_05, DigitalOut* fieldLED_06 )
DiegoOstuni	0:75fc82583a41	1459	{
DiegoOstuni	0:75fc82583a41	1460	uint32_t maskInterrupts;
DiegoOstuni	0:75fc82583a41	1461	uint8_t reg;
DiegoOstuni	0:75fc82583a41	1462
DiegoOstuni	0:75fc82583a41	1463	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	1464	/* In the EMVCo mode the NRT will continue to run. *
DiegoOstuni	0:75fc82583a41	1465	* For the clear to stop it, the EMV mode has to be disabled before */
DiegoOstuni	0:75fc82583a41	1466	st25r3911ClrRegisterBits( ST25R3911_REG_GPT_CONTROL, ST25R3911_REG_GPT_CONTROL_nrt_emv, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	1467
DiegoOstuni	0:75fc82583a41	1468	/* Reset receive logic */
DiegoOstuni	0:75fc82583a41	1469	mST25 -> executeCommand( ST25R3911_CMD_CLEAR_FIFO, mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	1470
DiegoOstuni	0:75fc82583a41	1471	/* Reset Rx Gain */
DiegoOstuni	0:75fc82583a41	1472	mST25 -> executeCommand( ST25R3911_CMD_CLEAR_SQUELCH, mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	1473
DiegoOstuni	0:75fc82583a41	1474
DiegoOstuni	0:75fc82583a41	1475	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	1476	/* FDT Poll */
DiegoOstuni	0:75fc82583a41	1477	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	1478	if( rfalIsModePassiveComm( gRFAL.mode ) ) /* Passive Comms */
DiegoOstuni	0:75fc82583a41	1479	{
DiegoOstuni	0:75fc82583a41	1480	/* In Passive communications General Purpose Timer is used to measure FDT Poll */
DiegoOstuni	0:75fc82583a41	1481	if( gRFAL.timings.FDTPoll != RFAL_TIMING_NONE )
DiegoOstuni	0:75fc82583a41	1482	{
DiegoOstuni	0:75fc82583a41	1483	/* Configure GPT to start at RX end */
DiegoOstuni	0:75fc82583a41	1484	st25r3911StartGPTimer_8fcs( rfalConv1fcTo8fc( MIN( gRFAL.timings.FDTPoll, (gRFAL.timings.FDTPoll - RFAL_FDT_POLL_ADJUSTMENT) ) ), ST25R3911_REG_GPT_CONTROL_gptc_erx,
DiegoOstuni	0:75fc82583a41	1485	mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	1486	}
DiegoOstuni	0:75fc82583a41	1487	}
DiegoOstuni	0:75fc82583a41	1488
DiegoOstuni	0:75fc82583a41	1489
DiegoOstuni	0:75fc82583a41	1490	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	1491	/* Execute Pre Transceive Callback */
DiegoOstuni	0:75fc82583a41	1492	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	1493	if( gRFAL.callbacks.preTxRx != NULL )
DiegoOstuni	0:75fc82583a41	1494	{
DiegoOstuni	0:75fc82583a41	1495	gRFAL.callbacks.preTxRx();
DiegoOstuni	0:75fc82583a41	1496	}
DiegoOstuni	0:75fc82583a41	1497	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	1498
DiegoOstuni	0:75fc82583a41	1499	maskInterrupts = ( ST25R3911_IRQ_MASK_FWL \| ST25R3911_IRQ_MASK_TXE \|
DiegoOstuni	0:75fc82583a41	1500	ST25R3911_IRQ_MASK_RXS \| ST25R3911_IRQ_MASK_RXE \|
DiegoOstuni	0:75fc82583a41	1501	ST25R3911_IRQ_MASK_FWL \| ST25R3911_IRQ_MASK_NRE \|
DiegoOstuni	0:75fc82583a41	1502	ST25R3911_IRQ_MASK_PAR \| ST25R3911_IRQ_MASK_CRC \|
DiegoOstuni	0:75fc82583a41	1503	ST25R3911_IRQ_MASK_ERR1 \| ST25R3911_IRQ_MASK_ERR2 );
DiegoOstuni	0:75fc82583a41	1504
DiegoOstuni	0:75fc82583a41	1505
DiegoOstuni	0:75fc82583a41	1506	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	1507	/* Transceive flags */
DiegoOstuni	0:75fc82583a41	1508	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	1509
DiegoOstuni	0:75fc82583a41	1510	reg = (ST25R3911_REG_ISO14443A_NFC_no_tx_par_off \| ST25R3911_REG_ISO14443A_NFC_no_rx_par_off \| ST25R3911_REG_ISO14443A_NFC_nfc_f0_off);
DiegoOstuni	0:75fc82583a41	1511
DiegoOstuni	0:75fc82583a41	1512	/* Check if NFCIP1 mode is to be enabled */
DiegoOstuni	0:75fc82583a41	1513	if( (gRFAL.TxRx.ctx.flags & RFAL_TXRX_FLAGS_NFCIP1_ON) )
DiegoOstuni	0:75fc82583a41	1514	{
DiegoOstuni	0:75fc82583a41	1515	reg \|= ST25R3911_REG_ISO14443A_NFC_nfc_f0;
DiegoOstuni	0:75fc82583a41	1516	}
DiegoOstuni	0:75fc82583a41	1517
DiegoOstuni	0:75fc82583a41	1518	/* Check if Parity check is to be skipped and to keep the parity + CRC bits in FIFO */
DiegoOstuni	0:75fc82583a41	1519	if( (gRFAL.TxRx.ctx.flags & RFAL_TXRX_FLAGS_PAR_RX_KEEP) )
DiegoOstuni	0:75fc82583a41	1520	{
DiegoOstuni	0:75fc82583a41	1521	reg \|= ST25R3911_REG_ISO14443A_NFC_no_rx_par;
DiegoOstuni	0:75fc82583a41	1522	}
DiegoOstuni	0:75fc82583a41	1523
DiegoOstuni	0:75fc82583a41	1524	/* Check if automatic Parity bits is to be disabled */
DiegoOstuni	0:75fc82583a41	1525	if( (gRFAL.TxRx.ctx.flags & RFAL_TXRX_FLAGS_PAR_TX_NONE) )
DiegoOstuni	0:75fc82583a41	1526	{
DiegoOstuni	0:75fc82583a41	1527	reg \|= ST25R3911_REG_ISO14443A_NFC_no_tx_par;
DiegoOstuni	0:75fc82583a41	1528	}
DiegoOstuni	0:75fc82583a41	1529
DiegoOstuni	0:75fc82583a41	1530	/* Apply current TxRx flags on ISO14443A and NFC 106kb/s Settings Register */
DiegoOstuni	0:75fc82583a41	1531	st25r3911ChangeRegisterBits( ST25R3911_REG_ISO14443A_NFC, (ST25R3911_REG_ISO14443A_NFC_no_tx_par \| ST25R3911_REG_ISO14443A_NFC_no_rx_par \| ST25R3911_REG_ISO14443A_NFC_nfc_f0),
DiegoOstuni	0:75fc82583a41	1532	reg, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	1533
DiegoOstuni	0:75fc82583a41	1534
DiegoOstuni	0:75fc82583a41	1535	/* Check if AGC is to be disabled */
DiegoOstuni	0:75fc82583a41	1536	if( (gRFAL.TxRx.ctx.flags & RFAL_TXRX_FLAGS_AGC_OFF) )
DiegoOstuni	0:75fc82583a41	1537	{
DiegoOstuni	0:75fc82583a41	1538	st25r3911ClrRegisterBits( ST25R3911_REG_RX_CONF2, ST25R3911_REG_RX_CONF2_agc_en, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	1539	}
DiegoOstuni	0:75fc82583a41	1540	else
DiegoOstuni	0:75fc82583a41	1541	{
DiegoOstuni	0:75fc82583a41	1542	st25r3911SetRegisterBits( ST25R3911_REG_RX_CONF2, ST25R3911_REG_RX_CONF2_agc_en, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	1543	}
DiegoOstuni	0:75fc82583a41	1544	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	1545
DiegoOstuni	0:75fc82583a41	1546
DiegoOstuni	0:75fc82583a41	1547
DiegoOstuni	0:75fc82583a41	1548	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	1549	/* EMVCo NRT mode */
DiegoOstuni	0:75fc82583a41	1550	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	1551	if( gRFAL.conf.eHandling == RFAL_ERRORHANDLING_EMVCO )
DiegoOstuni	0:75fc82583a41	1552	{
DiegoOstuni	0:75fc82583a41	1553	st25r3911SetRegisterBits( ST25R3911_REG_GPT_CONTROL, ST25R3911_REG_GPT_CONTROL_nrt_emv, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	1554	}
DiegoOstuni	0:75fc82583a41	1555	else
DiegoOstuni	0:75fc82583a41	1556	{
DiegoOstuni	0:75fc82583a41	1557	st25r3911ClrRegisterBits( ST25R3911_REG_GPT_CONTROL, ST25R3911_REG_GPT_CONTROL_nrt_emv, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	1558	}
DiegoOstuni	0:75fc82583a41	1559	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	1560
DiegoOstuni	0:75fc82583a41	1561
DiegoOstuni	0:75fc82583a41	1562
DiegoOstuni	0:75fc82583a41	1563	/* In Active comms enable also External Field interrupts */
DiegoOstuni	0:75fc82583a41	1564	if( rfalIsModeActiveComm( gRFAL.mode ) )
DiegoOstuni	0:75fc82583a41	1565	{
DiegoOstuni	0:75fc82583a41	1566	maskInterrupts \|= ( ST25R3911_IRQ_MASK_EOF \| ST25R3911_IRQ_MASK_EON \| ST25R3911_IRQ_MASK_CAT \| ST25R3911_IRQ_MASK_CAC );
DiegoOstuni	0:75fc82583a41	1567	}
DiegoOstuni	0:75fc82583a41	1568
DiegoOstuni	0:75fc82583a41	1569
DiegoOstuni	0:75fc82583a41	1570	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	1571	/* clear and enable these interrupts */
DiegoOstuni	0:75fc82583a41	1572	st25r3911GetInterrupt( maskInterrupts, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	1573	st25r3911EnableInterrupts( maskInterrupts, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	1574
DiegoOstuni	0:75fc82583a41	1575	/* Clear FIFO status local copy */
DiegoOstuni	0:75fc82583a41	1576	rfalFIFOStatusClear();
DiegoOstuni	0:75fc82583a41	1577	}
DiegoOstuni	0:75fc82583a41	1578
DiegoOstuni	0:75fc82583a41	1579	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	1580	static void rfalTransceiveTx( SPI* mspiChannel, ST25R3911* mST25, DigitalOut* gpio_cs, InterruptIn* IRQ, DigitalOut* fieldLED_01, DigitalOut* fieldLED_02, DigitalOut* fieldLED_03, DigitalOut* fieldLED_04, DigitalOut* fieldLED_05, DigitalOut* fieldLED_06 )
DiegoOstuni	0:75fc82583a41	1581	{
DiegoOstuni	0:75fc82583a41	1582	volatile uint32_t irqs;
DiegoOstuni	0:75fc82583a41	1583	uint16_t tmp;
DiegoOstuni	0:75fc82583a41	1584	ReturnCode ret;
DiegoOstuni	0:75fc82583a41	1585
DiegoOstuni	0:75fc82583a41	1586	/* NO_WARNING(ret); */
DiegoOstuni	0:75fc82583a41	1587
DiegoOstuni	0:75fc82583a41	1588	irqs = ST25R3911_IRQ_MASK_NONE;
DiegoOstuni	0:75fc82583a41	1589
DiegoOstuni	0:75fc82583a41	1590	if( gRFAL.TxRx.state != gRFAL.TxRx.lastState )
DiegoOstuni	0:75fc82583a41	1591	{
DiegoOstuni	0:75fc82583a41	1592	/* rfalLogD( "RFAL: lastSt: %d curSt: %d \r\n", gRFAL.TxRx.lastState, gRFAL.TxRx.state ); */
DiegoOstuni	0:75fc82583a41	1593	gRFAL.TxRx.lastState = gRFAL.TxRx.state;
DiegoOstuni	0:75fc82583a41	1594	}
DiegoOstuni	0:75fc82583a41	1595
DiegoOstuni	0:75fc82583a41	1596	switch( gRFAL.TxRx.state )
DiegoOstuni	0:75fc82583a41	1597	{
DiegoOstuni	0:75fc82583a41	1598	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	1599	case RFAL_TXRX_STATE_TX_IDLE:
DiegoOstuni	0:75fc82583a41	1600
DiegoOstuni	0:75fc82583a41	1601	/* Nothing to do */
DiegoOstuni	0:75fc82583a41	1602
DiegoOstuni	0:75fc82583a41	1603	gRFAL.TxRx.state = RFAL_TXRX_STATE_TX_WAIT_GT ;
DiegoOstuni	0:75fc82583a41	1604	/* fall through */
DiegoOstuni	0:75fc82583a41	1605
DiegoOstuni	0:75fc82583a41	1606
DiegoOstuni	0:75fc82583a41	1607	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	1608	case RFAL_TXRX_STATE_TX_WAIT_GT:
DiegoOstuni	0:75fc82583a41	1609
DiegoOstuni	0:75fc82583a41	1610	if( !rfalIsGTExpired() )
DiegoOstuni	0:75fc82583a41	1611	{
DiegoOstuni	0:75fc82583a41	1612	break;
DiegoOstuni	0:75fc82583a41	1613	}
DiegoOstuni	0:75fc82583a41	1614
DiegoOstuni	0:75fc82583a41	1615	gRFAL.tmr.GT = RFAL_TIMING_NONE;
DiegoOstuni	0:75fc82583a41	1616
DiegoOstuni	0:75fc82583a41	1617	gRFAL.TxRx.state = RFAL_TXRX_STATE_TX_WAIT_FDT;
DiegoOstuni	0:75fc82583a41	1618	/* fall through */
DiegoOstuni	0:75fc82583a41	1619
DiegoOstuni	0:75fc82583a41	1620
DiegoOstuni	0:75fc82583a41	1621	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	1622	case RFAL_TXRX_STATE_TX_WAIT_FDT:
DiegoOstuni	0:75fc82583a41	1623
DiegoOstuni	0:75fc82583a41	1624	/* Only in Passive communications GPT is used to measure FDT Poll */
DiegoOstuni	0:75fc82583a41	1625	if( rfalIsModePassiveComm( gRFAL.mode ) )
DiegoOstuni	0:75fc82583a41	1626	{
DiegoOstuni	0:75fc82583a41	1627	if( ( st25r3911CheckReg(ST25R3911_REG_REGULATOR_RESULT, ST25R3911_REG_REGULATOR_RESULT_gpt_on, ST25R3911_REG_REGULATOR_RESULT_gpt_on, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ) )
DiegoOstuni	0:75fc82583a41	1628	{
DiegoOstuni	0:75fc82583a41	1629	break;
DiegoOstuni	0:75fc82583a41	1630	}
DiegoOstuni	0:75fc82583a41	1631	}
DiegoOstuni	0:75fc82583a41	1632
DiegoOstuni	0:75fc82583a41	1633	gRFAL.TxRx.state = RFAL_TXRX_STATE_TX_TRANSMIT;
DiegoOstuni	0:75fc82583a41	1634	/* fall through */
DiegoOstuni	0:75fc82583a41	1635
DiegoOstuni	0:75fc82583a41	1636
DiegoOstuni	0:75fc82583a41	1637	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	1638	case RFAL_TXRX_STATE_TX_TRANSMIT:
DiegoOstuni	0:75fc82583a41	1639
DiegoOstuni	0:75fc82583a41	1640	/* Clear FIFO, Clear and Enable the Interrupts */
DiegoOstuni	0:75fc82583a41	1641	rfalPrepareTransceive( mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	1642
DiegoOstuni	0:75fc82583a41	1643	/* Calculate when Water Level Interrupt will be triggered */
DiegoOstuni	0:75fc82583a41	1644	gRFAL.fifo.expWL = ( st25r3911CheckReg( ST25R3911_REG_IO_CONF1, ST25R3911_REG_IO_CONF1_fifo_lt, ST25R3911_REG_IO_CONF1_fifo_lt_16bytes, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ? RFAL_FIFO_OUT_LT_16 : RFAL_FIFO_OUT_LT_32);
DiegoOstuni	0:75fc82583a41	1645
DiegoOstuni	0:75fc82583a41	1646	#if RFAL_FEATURE_NFCV
DiegoOstuni	0:75fc82583a41	1647	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	1648	/* In NFC-V streaming mode, the FIFO needs to be loaded with the coded bits */
DiegoOstuni	0:75fc82583a41	1649	if( (RFAL_MODE_POLL_NFCV == gRFAL.mode) \|\| (RFAL_MODE_POLL_PICOPASS == gRFAL.mode) )
DiegoOstuni	0:75fc82583a41	1650	{
DiegoOstuni	0:75fc82583a41	1651	#if 0
DiegoOstuni	0:75fc82583a41	1652	/* Debugging code: output the payload bits by writing into the FIFO and subsequent clearing */
DiegoOstuni	0:75fc82583a41	1653	mST25 -> writeFifo(gRFAL.TxRx.ctx.txBuf, rfalConvBitsToBytes(gRFAL.TxRx.ctx.txBufLen));
DiegoOstuni	0:75fc82583a41	1654	mST25 -> executeCommand( ST25R3911_CMD_CLEAR_FIFO, mspiChannel );
DiegoOstuni	0:75fc82583a41	1655	#endif
DiegoOstuni	0:75fc82583a41	1656	/* Calculate the bytes needed to be Written into FIFO (a incomplete byte will be added as 1byte) */
DiegoOstuni	0:75fc82583a41	1657	gRFAL.nfcvData.nfcvOffset = 0;
DiegoOstuni	0:75fc82583a41	1658	ret = iso15693VCDCode(gRFAL.TxRx.ctx.txBuf, rfalConvBitsToBytes(gRFAL.TxRx.ctx.txBufLen), ((gRFAL.nfcvData.origCtx.flags & RFAL_TXRX_FLAGS_CRC_TX_MANUAL)?false:true),((gRFAL.nfcvData.origCtx.flags & RFAL_TXRX_FLAGS_NFCV_FLAG_MANUAL)?false:true), (RFAL_MODE_POLL_PICOPASS == gRFAL.mode),
DiegoOstuni	0:75fc82583a41	1659	&gRFAL.fifo.bytesTotal, &gRFAL.nfcvData.nfcvOffset, gRFAL.nfcvData.codingBuffer, MIN( ST25R3911_FIFO_DEPTH, sizeof(gRFAL.nfcvData.codingBuffer) ), &gRFAL.fifo.bytesWritten);
DiegoOstuni	0:75fc82583a41	1660
DiegoOstuni	0:75fc82583a41	1661	if( (ret != ERR_NONE) && (ret != ERR_AGAIN) )
DiegoOstuni	0:75fc82583a41	1662	{
DiegoOstuni	0:75fc82583a41	1663	gRFAL.TxRx.status = ret;
DiegoOstuni	0:75fc82583a41	1664	gRFAL.TxRx.state = RFAL_TXRX_STATE_TX_FAIL;
DiegoOstuni	0:75fc82583a41	1665	break;
DiegoOstuni	0:75fc82583a41	1666	}
DiegoOstuni	0:75fc82583a41	1667	/* Set the number of full bytes and bits to be transmitted */
DiegoOstuni	0:75fc82583a41	1668	st25r3911SetNumTxBits( rfalConvBytesToBits(gRFAL.fifo.bytesTotal), mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	1669
DiegoOstuni	0:75fc82583a41	1670	/* Load FIFO with coded bytes */
DiegoOstuni	0:75fc82583a41	1671	mST25 -> writeFifo( gRFAL.nfcvData.codingBuffer, gRFAL.fifo.bytesWritten, mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	1672
DiegoOstuni	0:75fc82583a41	1673	}
DiegoOstuni	0:75fc82583a41	1674	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	1675	else
DiegoOstuni	0:75fc82583a41	1676	#endif /* RFAL_FEATURE_NFCV */
DiegoOstuni	0:75fc82583a41	1677	{
DiegoOstuni	0:75fc82583a41	1678	/* Calculate the bytes needed to be Written into FIFO (a incomplete byte will be added as 1byte) */
DiegoOstuni	0:75fc82583a41	1679	gRFAL.fifo.bytesTotal = rfalCalcNumBytes(gRFAL.TxRx.ctx.txBufLen);
DiegoOstuni	0:75fc82583a41	1680
DiegoOstuni	0:75fc82583a41	1681	/* Set the number of full bytes and bits to be transmitted */
DiegoOstuni	0:75fc82583a41	1682	st25r3911SetNumTxBits( gRFAL.TxRx.ctx.txBufLen, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	1683
DiegoOstuni	0:75fc82583a41	1684	/* Load FIFO with total length or FIFO's maximum */
DiegoOstuni	0:75fc82583a41	1685	gRFAL.fifo.bytesWritten = MIN( gRFAL.fifo.bytesTotal, ST25R3911_FIFO_DEPTH );
DiegoOstuni	0:75fc82583a41	1686	mST25 -> writeFifo( gRFAL.TxRx.ctx.txBuf, gRFAL.fifo.bytesWritten, mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	1687	}
DiegoOstuni	0:75fc82583a41	1688
DiegoOstuni	0:75fc82583a41	1689	/Check if Observation Mode is enabled and set it on ST25R391x /
DiegoOstuni	0:75fc82583a41	1690	rfalCheckEnableObsModeTx();
DiegoOstuni	0:75fc82583a41	1691
DiegoOstuni	0:75fc82583a41	1692	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	1693	/* Trigger/Start transmission */
DiegoOstuni	0:75fc82583a41	1694	if( gRFAL.TxRx.ctx.flags & RFAL_TXRX_FLAGS_CRC_TX_MANUAL )
DiegoOstuni	0:75fc82583a41	1695	{
DiegoOstuni	0:75fc82583a41	1696	mST25 -> executeCommand( ST25R3911_CMD_TRANSMIT_WITHOUT_CRC, mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	1697	}
DiegoOstuni	0:75fc82583a41	1698	else
DiegoOstuni	0:75fc82583a41	1699	{
DiegoOstuni	0:75fc82583a41	1700	mST25 -> executeCommand( ST25R3911_CMD_TRANSMIT_WITH_CRC, mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	1701	}
DiegoOstuni	0:75fc82583a41	1702
DiegoOstuni	0:75fc82583a41	1703	/* Check if a WL level is expected or TXE should come */
DiegoOstuni	0:75fc82583a41	1704	gRFAL.TxRx.state = (( gRFAL.fifo.bytesWritten < gRFAL.fifo.bytesTotal ) ? RFAL_TXRX_STATE_TX_WAIT_WL : RFAL_TXRX_STATE_TX_WAIT_TXE);
DiegoOstuni	0:75fc82583a41	1705	break;
DiegoOstuni	0:75fc82583a41	1706
DiegoOstuni	0:75fc82583a41	1707	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	1708	case RFAL_TXRX_STATE_TX_WAIT_WL:
DiegoOstuni	0:75fc82583a41	1709
DiegoOstuni	0:75fc82583a41	1710	irqs = st25r3911GetInterrupt( (ST25R3911_IRQ_MASK_FWL \| ST25R3911_IRQ_MASK_TXE), mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	1711	if( irqs == ST25R3911_IRQ_MASK_NONE )
DiegoOstuni	0:75fc82583a41	1712	{
DiegoOstuni	0:75fc82583a41	1713	break; /* No interrupt to process */
DiegoOstuni	0:75fc82583a41	1714	}
DiegoOstuni	0:75fc82583a41	1715
DiegoOstuni	0:75fc82583a41	1716	if( (irqs & ST25R3911_IRQ_MASK_FWL) && !(irqs & ST25R3911_IRQ_MASK_TXE) )
DiegoOstuni	0:75fc82583a41	1717	{
DiegoOstuni	0:75fc82583a41	1718	gRFAL.TxRx.state = RFAL_TXRX_STATE_TX_RELOAD_FIFO;
DiegoOstuni	0:75fc82583a41	1719	}
DiegoOstuni	0:75fc82583a41	1720	else
DiegoOstuni	0:75fc82583a41	1721	{
DiegoOstuni	0:75fc82583a41	1722	gRFAL.TxRx.status = ERR_IO;
DiegoOstuni	0:75fc82583a41	1723	gRFAL.TxRx.state = RFAL_TXRX_STATE_TX_FAIL;
DiegoOstuni	0:75fc82583a41	1724	break;
DiegoOstuni	0:75fc82583a41	1725	}
DiegoOstuni	0:75fc82583a41	1726
DiegoOstuni	0:75fc82583a41	1727	/* fall through */
DiegoOstuni	0:75fc82583a41	1728
DiegoOstuni	0:75fc82583a41	1729	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	1730	case RFAL_TXRX_STATE_TX_RELOAD_FIFO:
DiegoOstuni	0:75fc82583a41	1731
DiegoOstuni	0:75fc82583a41	1732	#if RFAL_FEATURE_NFCV
DiegoOstuni	0:75fc82583a41	1733	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	1734	/* In NFC-V streaming mode, the FIFO needs to be loaded with the coded bits */
DiegoOstuni	0:75fc82583a41	1735	if( (RFAL_MODE_POLL_NFCV == gRFAL.mode) \|\| (RFAL_MODE_POLL_PICOPASS == gRFAL.mode) )
DiegoOstuni	0:75fc82583a41	1736	{
DiegoOstuni	0:75fc82583a41	1737	uint16_t maxLen;
DiegoOstuni	0:75fc82583a41	1738
DiegoOstuni	0:75fc82583a41	1739	/* Load FIFO with the remaining length or maximum available (which fit on the coding buffer) */
DiegoOstuni	0:75fc82583a41	1740	maxLen = MIN( (gRFAL.fifo.bytesTotal - gRFAL.fifo.bytesWritten), gRFAL.fifo.expWL);
DiegoOstuni	0:75fc82583a41	1741	maxLen = MIN( maxLen, sizeof(gRFAL.nfcvData.codingBuffer) );
DiegoOstuni	0:75fc82583a41	1742	tmp = 0;
DiegoOstuni	0:75fc82583a41	1743
DiegoOstuni	0:75fc82583a41	1744	/* Calculate the bytes needed to be Written into FIFO (a incomplete byte will be added as 1byte) */
DiegoOstuni	0:75fc82583a41	1745	ret = iso15693VCDCode(gRFAL.TxRx.ctx.txBuf, rfalConvBitsToBytes(gRFAL.TxRx.ctx.txBufLen), ((gRFAL.nfcvData.origCtx.flags & RFAL_TXRX_FLAGS_CRC_TX_MANUAL)?false:true), ((gRFAL.nfcvData.origCtx.flags & RFAL_TXRX_FLAGS_NFCV_FLAG_MANUAL)?false:true), (RFAL_MODE_POLL_PICOPASS == gRFAL.mode),
DiegoOstuni	0:75fc82583a41	1746	&gRFAL.fifo.bytesTotal, &gRFAL.nfcvData.nfcvOffset, gRFAL.nfcvData.codingBuffer, maxLen, &tmp);
DiegoOstuni	0:75fc82583a41	1747
DiegoOstuni	0:75fc82583a41	1748	if( (ret != ERR_NONE) && (ret != ERR_AGAIN) )
DiegoOstuni	0:75fc82583a41	1749	{
DiegoOstuni	0:75fc82583a41	1750	gRFAL.TxRx.status = ret;
DiegoOstuni	0:75fc82583a41	1751	gRFAL.TxRx.state = RFAL_TXRX_STATE_TX_FAIL;
DiegoOstuni	0:75fc82583a41	1752	break;
DiegoOstuni	0:75fc82583a41	1753	}
DiegoOstuni	0:75fc82583a41	1754
DiegoOstuni	0:75fc82583a41	1755	/* Load FIFO with coded bytes */
DiegoOstuni	0:75fc82583a41	1756	mST25 -> writeFifo( gRFAL.nfcvData.codingBuffer, tmp, mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	1757	}
DiegoOstuni	0:75fc82583a41	1758	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	1759	else
DiegoOstuni	0:75fc82583a41	1760	#endif /* RFAL_FEATURE_NFCV */
DiegoOstuni	0:75fc82583a41	1761	{
DiegoOstuni	0:75fc82583a41	1762	/* Load FIFO with the remaining length or maximum available */
DiegoOstuni	0:75fc82583a41	1763	tmp = MIN( (gRFAL.fifo.bytesTotal - gRFAL.fifo.bytesWritten), gRFAL.fifo.expWL); /* tmp holds the number of bytes written on this iteration */
DiegoOstuni	0:75fc82583a41	1764	mST25 -> writeFifo( gRFAL.TxRx.ctx.txBuf + gRFAL.fifo.bytesWritten, tmp, mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	1765	}
DiegoOstuni	0:75fc82583a41	1766
DiegoOstuni	0:75fc82583a41	1767	/* Update total written bytes to FIFO */
DiegoOstuni	0:75fc82583a41	1768	gRFAL.fifo.bytesWritten += tmp;
DiegoOstuni	0:75fc82583a41	1769
DiegoOstuni	0:75fc82583a41	1770	/* Check if a WL level is expected or TXE should come */
DiegoOstuni	0:75fc82583a41	1771	gRFAL.TxRx.state = (( gRFAL.fifo.bytesWritten < gRFAL.fifo.bytesTotal ) ? RFAL_TXRX_STATE_TX_WAIT_WL : RFAL_TXRX_STATE_TX_WAIT_TXE);
DiegoOstuni	0:75fc82583a41	1772	break;
DiegoOstuni	0:75fc82583a41	1773
DiegoOstuni	0:75fc82583a41	1774
DiegoOstuni	0:75fc82583a41	1775	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	1776	case RFAL_TXRX_STATE_TX_WAIT_TXE:
DiegoOstuni	0:75fc82583a41	1777
DiegoOstuni	0:75fc82583a41	1778	irqs = st25r3911GetInterrupt( (ST25R3911_IRQ_MASK_FWL \| ST25R3911_IRQ_MASK_TXE), mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	1779	if( irqs == ST25R3911_IRQ_MASK_NONE )
DiegoOstuni	0:75fc82583a41	1780	{
DiegoOstuni	0:75fc82583a41	1781	break; /* No interrupt to process */
DiegoOstuni	0:75fc82583a41	1782	}
DiegoOstuni	0:75fc82583a41	1783
DiegoOstuni	0:75fc82583a41	1784
DiegoOstuni	0:75fc82583a41	1785	if( (irqs & ST25R3911_IRQ_MASK_TXE) )
DiegoOstuni	0:75fc82583a41	1786	{
DiegoOstuni	0:75fc82583a41	1787	/* In Active comm start SW timer to measure FWT */
DiegoOstuni	0:75fc82583a41	1788	if( rfalIsModeActiveComm( gRFAL.mode) && (gRFAL.TxRx.ctx.fwt != RFAL_FWT_NONE) && (gRFAL.TxRx.ctx.fwt != 0) )
DiegoOstuni	0:75fc82583a41	1789	{
DiegoOstuni	0:75fc82583a41	1790	rfalTimerStart( gRFAL.tmr.FWT, rfalConv1fcToMs( gRFAL.TxRx.ctx.fwt ) );
DiegoOstuni	0:75fc82583a41	1791	}
DiegoOstuni	0:75fc82583a41	1792
DiegoOstuni	0:75fc82583a41	1793	gRFAL.TxRx.state = RFAL_TXRX_STATE_TX_DONE;
DiegoOstuni	0:75fc82583a41	1794	}
DiegoOstuni	0:75fc82583a41	1795	else if( (irqs & ST25R3911_IRQ_MASK_FWL) )
DiegoOstuni	0:75fc82583a41	1796	{
DiegoOstuni	0:75fc82583a41	1797	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	1798	/* REMARK: Silicon workaround ST25R3911 Errata #TBD */
DiegoOstuni	0:75fc82583a41	1799	/* ST25R3911 may send a WL even when all bytes have been written to FIFO */
DiegoOstuni	0:75fc82583a41	1800	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	1801	break; /* Ignore ST25R3911 FIFO WL if total TxLen is already on the FIFO */
DiegoOstuni	0:75fc82583a41	1802	}
DiegoOstuni	0:75fc82583a41	1803	else
DiegoOstuni	0:75fc82583a41	1804	{
DiegoOstuni	0:75fc82583a41	1805	gRFAL.TxRx.status = ERR_IO;
DiegoOstuni	0:75fc82583a41	1806	gRFAL.TxRx.state = RFAL_TXRX_STATE_TX_FAIL;
DiegoOstuni	0:75fc82583a41	1807	break;
DiegoOstuni	0:75fc82583a41	1808	} // @suppress("No break at end of case")
DiegoOstuni	0:75fc82583a41	1809
DiegoOstuni	0:75fc82583a41	1810	/* fall through */
DiegoOstuni	0:75fc82583a41	1811
DiegoOstuni	0:75fc82583a41	1812
DiegoOstuni	0:75fc82583a41	1813	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	1814	case RFAL_TXRX_STATE_TX_DONE:
DiegoOstuni	0:75fc82583a41	1815
DiegoOstuni	0:75fc82583a41	1816	/* If no rxBuf is provided do not wait/expect Rx */
DiegoOstuni	0:75fc82583a41	1817	if( gRFAL.TxRx.ctx.rxBuf == NULL )
DiegoOstuni	0:75fc82583a41	1818	{
DiegoOstuni	0:75fc82583a41	1819	/Check if Observation Mode was enabled and disable it on ST25R391x /
DiegoOstuni	0:75fc82583a41	1820	rfalCheckDisableObsMode();
DiegoOstuni	0:75fc82583a41	1821
DiegoOstuni	0:75fc82583a41	1822	/* Clean up Transceive */
DiegoOstuni	0:75fc82583a41	1823	rfalCleanupTransceive( mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	1824
DiegoOstuni	0:75fc82583a41	1825	gRFAL.TxRx.status = ERR_NONE;
DiegoOstuni	0:75fc82583a41	1826	gRFAL.TxRx.state = RFAL_TXRX_STATE_IDLE;
DiegoOstuni	0:75fc82583a41	1827	break;
DiegoOstuni	0:75fc82583a41	1828	}
DiegoOstuni	0:75fc82583a41	1829
DiegoOstuni	0:75fc82583a41	1830	rfalCheckEnableObsModeRx();
DiegoOstuni	0:75fc82583a41	1831
DiegoOstuni	0:75fc82583a41	1832	/* Goto Rx */
DiegoOstuni	0:75fc82583a41	1833	gRFAL.TxRx.state = RFAL_TXRX_STATE_RX_IDLE;
DiegoOstuni	0:75fc82583a41	1834	break;
DiegoOstuni	0:75fc82583a41	1835
DiegoOstuni	0:75fc82583a41	1836	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	1837	case RFAL_TXRX_STATE_TX_FAIL:
DiegoOstuni	0:75fc82583a41	1838
DiegoOstuni	0:75fc82583a41	1839	/* Error should be assigned by previous state */
DiegoOstuni	0:75fc82583a41	1840	if( gRFAL.TxRx.status == ERR_BUSY )
DiegoOstuni	0:75fc82583a41	1841	{
DiegoOstuni	0:75fc82583a41	1842	gRFAL.TxRx.status = ERR_SYSTEM;
DiegoOstuni	0:75fc82583a41	1843	}
DiegoOstuni	0:75fc82583a41	1844
DiegoOstuni	0:75fc82583a41	1845	/Check if Observation Mode was enabled and disable it on ST25R391x /
DiegoOstuni	0:75fc82583a41	1846	rfalCheckDisableObsMode();
DiegoOstuni	0:75fc82583a41	1847
DiegoOstuni	0:75fc82583a41	1848	/* Clean up Transceive */
DiegoOstuni	0:75fc82583a41	1849	rfalCleanupTransceive( mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	1850
DiegoOstuni	0:75fc82583a41	1851	gRFAL.TxRx.state = RFAL_TXRX_STATE_IDLE;
DiegoOstuni	0:75fc82583a41	1852	break;
DiegoOstuni	0:75fc82583a41	1853
DiegoOstuni	0:75fc82583a41	1854	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	1855	default:
DiegoOstuni	0:75fc82583a41	1856	gRFAL.TxRx.status = ERR_SYSTEM;
DiegoOstuni	0:75fc82583a41	1857	gRFAL.TxRx.state = RFAL_TXRX_STATE_TX_FAIL;
DiegoOstuni	0:75fc82583a41	1858	break;
DiegoOstuni	0:75fc82583a41	1859	}
DiegoOstuni	0:75fc82583a41	1860	}
DiegoOstuni	0:75fc82583a41	1861
DiegoOstuni	0:75fc82583a41	1862
DiegoOstuni	0:75fc82583a41	1863	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	1864	static void rfalTransceiveRx( SPI* mspiChannel, ST25R3911* mST25, DigitalOut* gpio_cs, InterruptIn* IRQ, DigitalOut* fieldLED_01, DigitalOut* fieldLED_02, DigitalOut* fieldLED_03, DigitalOut* fieldLED_04, DigitalOut* fieldLED_05, DigitalOut* fieldLED_06 )
DiegoOstuni	0:75fc82583a41	1865	{
DiegoOstuni	0:75fc82583a41	1866	volatile uint32_t irqs;
DiegoOstuni	0:75fc82583a41	1867	uint8_t tmp;
DiegoOstuni	0:75fc82583a41	1868	uint8_t aux;
DiegoOstuni	0:75fc82583a41	1869
DiegoOstuni	0:75fc82583a41	1870	irqs = ST25R3911_IRQ_MASK_NONE;
DiegoOstuni	0:75fc82583a41	1871
DiegoOstuni	0:75fc82583a41	1872	if( gRFAL.TxRx.state != gRFAL.TxRx.lastState )
DiegoOstuni	0:75fc82583a41	1873	{
DiegoOstuni	0:75fc82583a41	1874	/* rfalLogD( "RFAL: lastSt: %d curSt: %d \r\n", gRFAL.TxRx.lastState, gRFAL.TxRx.state ); */
DiegoOstuni	0:75fc82583a41	1875	gRFAL.TxRx.lastState = gRFAL.TxRx.state;
DiegoOstuni	0:75fc82583a41	1876	}
DiegoOstuni	0:75fc82583a41	1877
DiegoOstuni	0:75fc82583a41	1878	switch( gRFAL.TxRx.state )
DiegoOstuni	0:75fc82583a41	1879	{
DiegoOstuni	0:75fc82583a41	1880	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	1881	case RFAL_TXRX_STATE_RX_IDLE:
DiegoOstuni	0:75fc82583a41	1882
DiegoOstuni	0:75fc82583a41	1883	/* Clear rx counters */
DiegoOstuni	0:75fc82583a41	1884	gRFAL.fifo.bytesWritten = 0; /* Total bytes written on RxBuffer */
DiegoOstuni	0:75fc82583a41	1885	gRFAL.fifo.bytesTotal = 0; /* Total bytes in FIFO will now be from Rx */
DiegoOstuni	0:75fc82583a41	1886	if( gRFAL.TxRx.ctx.rxRcvdLen ) *gRFAL.TxRx.ctx.rxRcvdLen = 0;
DiegoOstuni	0:75fc82583a41	1887
DiegoOstuni	0:75fc82583a41	1888	gRFAL.TxRx.state = ( rfalIsModeActiveComm( gRFAL.mode ) ? RFAL_TXRX_STATE_RX_WAIT_EON : RFAL_TXRX_STATE_RX_WAIT_RXS );
DiegoOstuni	0:75fc82583a41	1889	break;
DiegoOstuni	0:75fc82583a41	1890
DiegoOstuni	0:75fc82583a41	1891
DiegoOstuni	0:75fc82583a41	1892	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	1893	case RFAL_TXRX_STATE_RX_WAIT_RXS:
DiegoOstuni	0:75fc82583a41	1894
DiegoOstuni	0:75fc82583a41	1895	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	1896	/* If in Active comm, Check if FWT SW timer has expired */
DiegoOstuni	0:75fc82583a41	1897	if( rfalIsModeActiveComm( gRFAL.mode ) && (gRFAL.TxRx.ctx.fwt != RFAL_FWT_NONE) && (gRFAL.TxRx.ctx.fwt != 0) )
DiegoOstuni	0:75fc82583a41	1898	{
DiegoOstuni	0:75fc82583a41	1899	if( rfalTimerisExpired( gRFAL.tmr.FWT ) )
DiegoOstuni	0:75fc82583a41	1900	{
DiegoOstuni	0:75fc82583a41	1901	gRFAL.TxRx.status = ERR_TIMEOUT;
DiegoOstuni	0:75fc82583a41	1902	gRFAL.TxRx.state = RFAL_TXRX_STATE_RX_FAIL;
DiegoOstuni	0:75fc82583a41	1903	break;
DiegoOstuni	0:75fc82583a41	1904	}
DiegoOstuni	0:75fc82583a41	1905	}
DiegoOstuni	0:75fc82583a41	1906
DiegoOstuni	0:75fc82583a41	1907	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	1908	irqs = st25r3911GetInterrupt( ( ST25R3911_IRQ_MASK_RXS \| ST25R3911_IRQ_MASK_NRE \| ST25R3911_IRQ_MASK_EOF \| ST25R3911_IRQ_MASK_RXE), mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	1909	if( irqs == ST25R3911_IRQ_MASK_NONE )
DiegoOstuni	0:75fc82583a41	1910	{
DiegoOstuni	0:75fc82583a41	1911	break; /* No interrupt to process */
DiegoOstuni	0:75fc82583a41	1912	}
DiegoOstuni	0:75fc82583a41	1913
DiegoOstuni	0:75fc82583a41	1914
DiegoOstuni	0:75fc82583a41	1915	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	1916	/* REMARK: Silicon workaround ST25R3911 Errata #1.7 */
DiegoOstuni	0:75fc82583a41	1917	/* NRE interrupt may be triggered twice */
DiegoOstuni	0:75fc82583a41	1918	/* Ignore NRE if is detected together with no Rx Start */
DiegoOstuni	0:75fc82583a41	1919	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	1920
DiegoOstuni	0:75fc82583a41	1921	/* Only raise Timeout if NRE is detected with no Rx Start (NRT EMV mode) */
DiegoOstuni	0:75fc82583a41	1922	if( (irqs & ST25R3911_IRQ_MASK_NRE) && !(irqs & ST25R3911_IRQ_MASK_RXS) )
DiegoOstuni	0:75fc82583a41	1923	{
DiegoOstuni	0:75fc82583a41	1924	gRFAL.TxRx.status = ERR_TIMEOUT;
DiegoOstuni	0:75fc82583a41	1925	gRFAL.TxRx.state = RFAL_TXRX_STATE_RX_FAIL;
DiegoOstuni	0:75fc82583a41	1926	break;
DiegoOstuni	0:75fc82583a41	1927	}
DiegoOstuni	0:75fc82583a41	1928
DiegoOstuni	0:75fc82583a41	1929	/* Only raise Link Loss if EOF is detected with no Rx Start */
DiegoOstuni	0:75fc82583a41	1930	if( (irqs & ST25R3911_IRQ_MASK_EOF) && !(irqs & ST25R3911_IRQ_MASK_RXS) )
DiegoOstuni	0:75fc82583a41	1931	{
DiegoOstuni	0:75fc82583a41	1932	gRFAL.TxRx.status = ERR_LINK_LOSS;
DiegoOstuni	0:75fc82583a41	1933	gRFAL.TxRx.state = RFAL_TXRX_STATE_RX_FAIL;
DiegoOstuni	0:75fc82583a41	1934	break;
DiegoOstuni	0:75fc82583a41	1935	}
DiegoOstuni	0:75fc82583a41	1936
DiegoOstuni	0:75fc82583a41	1937	if( (irqs & ST25R3911_IRQ_MASK_RXS) )
DiegoOstuni	0:75fc82583a41	1938	{
DiegoOstuni	0:75fc82583a41	1939	/* If we got RXS + RXE together, jump directly into RFAL_TXRX_STATE_RX_ERR_CHECK */
DiegoOstuni	0:75fc82583a41	1940	if( (irqs & ST25R3911_IRQ_MASK_RXE) )
DiegoOstuni	0:75fc82583a41	1941	{
DiegoOstuni	0:75fc82583a41	1942	gRFAL.TxRx.rxse = true;
DiegoOstuni	0:75fc82583a41	1943	gRFAL.TxRx.state = RFAL_TXRX_STATE_RX_ERR_CHECK;
DiegoOstuni	0:75fc82583a41	1944	break;
DiegoOstuni	0:75fc82583a41	1945	}
DiegoOstuni	0:75fc82583a41	1946	else
DiegoOstuni	0:75fc82583a41	1947	{
DiegoOstuni	0:75fc82583a41	1948	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	1949	/* REMARK: Silicon workaround ST25R3911 Errata #1.1 */
DiegoOstuni	0:75fc82583a41	1950	/* Rarely on corrupted frames I_rxs gets signaled but I_rxe is not signaled */
DiegoOstuni	0:75fc82583a41	1951	/* Use a SW timer to handle an eventual missing RXE */
DiegoOstuni	0:75fc82583a41	1952	rfalTimerStart( gRFAL.tmr.RXE, RFAL_NORXE_TOUT );
DiegoOstuni	0:75fc82583a41	1953	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	1954
DiegoOstuni	0:75fc82583a41	1955	gRFAL.TxRx.state = RFAL_TXRX_STATE_RX_WAIT_RXE;
DiegoOstuni	0:75fc82583a41	1956	}
DiegoOstuni	0:75fc82583a41	1957	}
DiegoOstuni	0:75fc82583a41	1958	else if( (irqs & ST25R3911_IRQ_MASK_RXE) )
DiegoOstuni	0:75fc82583a41	1959	{
DiegoOstuni	0:75fc82583a41	1960	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	1961	/* REMARK: Silicon workaround ST25R3911 Errata #1.9 */
DiegoOstuni	0:75fc82583a41	1962	/* ST25R3911 may indicate RXE without RXS previously, this happens upon some */
DiegoOstuni	0:75fc82583a41	1963	/* noise or incomplete byte frames with less than 4 bits */
DiegoOstuni	0:75fc82583a41	1964	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	1965
DiegoOstuni	0:75fc82583a41	1966	gRFAL.TxRx.status = ERR_IO;
DiegoOstuni	0:75fc82583a41	1967	gRFAL.TxRx.state = RFAL_TXRX_STATE_RX_FAIL;
DiegoOstuni	0:75fc82583a41	1968
DiegoOstuni	0:75fc82583a41	1969	rfalErrorHandling(mST25, mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	1970	break;
DiegoOstuni	0:75fc82583a41	1971	}
DiegoOstuni	0:75fc82583a41	1972	else
DiegoOstuni	0:75fc82583a41	1973	{
DiegoOstuni	0:75fc82583a41	1974	gRFAL.TxRx.status = ERR_IO;
DiegoOstuni	0:75fc82583a41	1975	gRFAL.TxRx.state = RFAL_TXRX_STATE_RX_FAIL;
DiegoOstuni	0:75fc82583a41	1976	break;
DiegoOstuni	0:75fc82583a41	1977	}
DiegoOstuni	0:75fc82583a41	1978
DiegoOstuni	0:75fc82583a41	1979	/* fall through */
DiegoOstuni	0:75fc82583a41	1980
DiegoOstuni	0:75fc82583a41	1981
DiegoOstuni	0:75fc82583a41	1982	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	1983	case RFAL_TXRX_STATE_RX_WAIT_RXE:
DiegoOstuni	0:75fc82583a41	1984
DiegoOstuni	0:75fc82583a41	1985	irqs = st25r3911GetInterrupt( (ST25R3911_IRQ_MASK_RXE \| ST25R3911_IRQ_MASK_FWL \| ST25R3911_IRQ_MASK_EOF), mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	1986	if( irqs == ST25R3911_IRQ_MASK_NONE )
DiegoOstuni	0:75fc82583a41	1987	{
DiegoOstuni	0:75fc82583a41	1988	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	1989	/* REMARK: Silicon workaround ST25R3911B Errata #1.1 */
DiegoOstuni	0:75fc82583a41	1990	/* ST25R3911 may indicate RXS without RXE afterwards, this happens rarely on */
DiegoOstuni	0:75fc82583a41	1991	/* corrupted frames. */
DiegoOstuni	0:75fc82583a41	1992	/* SW timer is used to timeout upon a missing RXE */
DiegoOstuni	0:75fc82583a41	1993	if( rfalTimerisExpired( gRFAL.tmr.RXE ) )
DiegoOstuni	0:75fc82583a41	1994	{
DiegoOstuni	0:75fc82583a41	1995	gRFAL.TxRx.status = ERR_FRAMING;
DiegoOstuni	0:75fc82583a41	1996	gRFAL.TxRx.state = RFAL_TXRX_STATE_RX_FAIL;
DiegoOstuni	0:75fc82583a41	1997	}
DiegoOstuni	0:75fc82583a41	1998	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	1999
DiegoOstuni	0:75fc82583a41	2000	break; /* No interrupt to process */
DiegoOstuni	0:75fc82583a41	2001	}
DiegoOstuni	0:75fc82583a41	2002
DiegoOstuni	0:75fc82583a41	2003	if( (irqs & ST25R3911_IRQ_MASK_FWL) && !(irqs & ST25R3911_IRQ_MASK_RXE) )
DiegoOstuni	0:75fc82583a41	2004	{
DiegoOstuni	0:75fc82583a41	2005	gRFAL.TxRx.state = RFAL_TXRX_STATE_RX_READ_FIFO;
DiegoOstuni	0:75fc82583a41	2006	break;
DiegoOstuni	0:75fc82583a41	2007	}
DiegoOstuni	0:75fc82583a41	2008
DiegoOstuni	0:75fc82583a41	2009	gRFAL.TxRx.state = RFAL_TXRX_STATE_RX_ERR_CHECK;
DiegoOstuni	0:75fc82583a41	2010	/* fall through */
DiegoOstuni	0:75fc82583a41	2011
DiegoOstuni	0:75fc82583a41	2012
DiegoOstuni	0:75fc82583a41	2013	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	2014	case RFAL_TXRX_STATE_RX_ERR_CHECK:
DiegoOstuni	0:75fc82583a41	2015
DiegoOstuni	0:75fc82583a41	2016	/* Retrieve and check for any error irqs */
DiegoOstuni	0:75fc82583a41	2017	irqs \|= st25r3911GetInterrupt( (ST25R3911_IRQ_MASK_CRC \| ST25R3911_IRQ_MASK_PAR \| ST25R3911_IRQ_MASK_ERR1 \| ST25R3911_IRQ_MASK_ERR2 \| ST25R3911_IRQ_MASK_COL), mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	2018
DiegoOstuni	0:75fc82583a41	2019	if( (irqs & ST25R3911_IRQ_MASK_ERR1) )
DiegoOstuni	0:75fc82583a41	2020	{
DiegoOstuni	0:75fc82583a41	2021	gRFAL.TxRx.status = ERR_FRAMING;
DiegoOstuni	0:75fc82583a41	2022	gRFAL.TxRx.state = RFAL_TXRX_STATE_RX_READ_DATA;
DiegoOstuni	0:75fc82583a41	2023
DiegoOstuni	0:75fc82583a41	2024	/* Check if there's a specific error handling for this */
DiegoOstuni	0:75fc82583a41	2025	rfalErrorHandling(mST25, mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	2026	break;
DiegoOstuni	0:75fc82583a41	2027	}
DiegoOstuni	0:75fc82583a41	2028	/* Discard Soft Framing errors if not in EMVCo error handling */
DiegoOstuni	0:75fc82583a41	2029	else if( (irqs & ST25R3911_IRQ_MASK_ERR2) && (gRFAL.conf.eHandling == RFAL_ERRORHANDLING_EMVCO) )
DiegoOstuni	0:75fc82583a41	2030	{
DiegoOstuni	0:75fc82583a41	2031	gRFAL.TxRx.status = ERR_FRAMING;
DiegoOstuni	0:75fc82583a41	2032	gRFAL.TxRx.state = RFAL_TXRX_STATE_RX_READ_DATA;
DiegoOstuni	0:75fc82583a41	2033
DiegoOstuni	0:75fc82583a41	2034	/* Check if there's a specific error handling for this */
DiegoOstuni	0:75fc82583a41	2035	rfalErrorHandling(mST25, mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	2036	break;
DiegoOstuni	0:75fc82583a41	2037	}
DiegoOstuni	0:75fc82583a41	2038	else if( (irqs & ST25R3911_IRQ_MASK_PAR) )
DiegoOstuni	0:75fc82583a41	2039	{
DiegoOstuni	0:75fc82583a41	2040	gRFAL.TxRx.status = ERR_PAR;
DiegoOstuni	0:75fc82583a41	2041	gRFAL.TxRx.state = RFAL_TXRX_STATE_RX_READ_DATA;
DiegoOstuni	0:75fc82583a41	2042
DiegoOstuni	0:75fc82583a41	2043	/* Check if there's a specific error handling for this */
DiegoOstuni	0:75fc82583a41	2044	rfalErrorHandling(mST25, mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	2045	break;
DiegoOstuni	0:75fc82583a41	2046	}
DiegoOstuni	0:75fc82583a41	2047	else if( (irqs & ST25R3911_IRQ_MASK_CRC) )
DiegoOstuni	0:75fc82583a41	2048	{
DiegoOstuni	0:75fc82583a41	2049	gRFAL.TxRx.status = ERR_CRC;
DiegoOstuni	0:75fc82583a41	2050	gRFAL.TxRx.state = RFAL_TXRX_STATE_RX_READ_DATA;
DiegoOstuni	0:75fc82583a41	2051
DiegoOstuni	0:75fc82583a41	2052	/* Check if there's a specific error handling for this */
DiegoOstuni	0:75fc82583a41	2053	rfalErrorHandling(mST25, mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	2054	break;
DiegoOstuni	0:75fc82583a41	2055	}
DiegoOstuni	0:75fc82583a41	2056	else if( (irqs & ST25R3911_IRQ_MASK_COL) )
DiegoOstuni	0:75fc82583a41	2057	{
DiegoOstuni	0:75fc82583a41	2058	gRFAL.TxRx.status = ERR_RF_COLLISION;
DiegoOstuni	0:75fc82583a41	2059	gRFAL.TxRx.state = RFAL_TXRX_STATE_RX_READ_DATA;
DiegoOstuni	0:75fc82583a41	2060
DiegoOstuni	0:75fc82583a41	2061	/* Check if there's a specific error handling for this */
DiegoOstuni	0:75fc82583a41	2062	rfalErrorHandling(mST25, mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	2063	break;
DiegoOstuni	0:75fc82583a41	2064	}
DiegoOstuni	0:75fc82583a41	2065	else if( (irqs & ST25R3911_IRQ_MASK_EOF) && !(irqs & ST25R3911_IRQ_MASK_RXE) )
DiegoOstuni	0:75fc82583a41	2066	{
DiegoOstuni	0:75fc82583a41	2067	gRFAL.TxRx.status = ERR_LINK_LOSS;
DiegoOstuni	0:75fc82583a41	2068	gRFAL.TxRx.state = RFAL_TXRX_STATE_RX_FAIL;
DiegoOstuni	0:75fc82583a41	2069	break;
DiegoOstuni	0:75fc82583a41	2070	}
DiegoOstuni	0:75fc82583a41	2071	else if( (irqs & ST25R3911_IRQ_MASK_RXE) \|\| gRFAL.TxRx.rxse )
DiegoOstuni	0:75fc82583a41	2072	{
DiegoOstuni	0:75fc82583a41	2073	/* Reception ended without any error indication, *
DiegoOstuni	0:75fc82583a41	2074	* check FIFO status for malformed or incomplete frames */
DiegoOstuni	0:75fc82583a41	2075
DiegoOstuni	0:75fc82583a41	2076	/* Check if the reception ends with an incomplete byte (residual bits) */
DiegoOstuni	0:75fc82583a41	2077	if( rfalFIFOStatusIsIncompleteByte(mST25, mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) )
DiegoOstuni	0:75fc82583a41	2078	{
DiegoOstuni	0:75fc82583a41	2079	gRFAL.TxRx.status = ERR_INCOMPLETE_BYTE;
DiegoOstuni	0:75fc82583a41	2080	}
DiegoOstuni	0:75fc82583a41	2081	/* Check if the reception ends with missing parity bit */
DiegoOstuni	0:75fc82583a41	2082	else if( rfalFIFOStatusIsMissingPar(mST25, mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) )
DiegoOstuni	0:75fc82583a41	2083	{
DiegoOstuni	0:75fc82583a41	2084	gRFAL.TxRx.status = ERR_FRAMING;
DiegoOstuni	0:75fc82583a41	2085	}
DiegoOstuni	0:75fc82583a41	2086
DiegoOstuni	0:75fc82583a41	2087	gRFAL.TxRx.state = RFAL_TXRX_STATE_RX_READ_DATA;
DiegoOstuni	0:75fc82583a41	2088	}
DiegoOstuni	0:75fc82583a41	2089	else
DiegoOstuni	0:75fc82583a41	2090	{
DiegoOstuni	0:75fc82583a41	2091	gRFAL.TxRx.status = ERR_IO;
DiegoOstuni	0:75fc82583a41	2092	gRFAL.TxRx.state = RFAL_TXRX_STATE_RX_FAIL;
DiegoOstuni	0:75fc82583a41	2093	break;
DiegoOstuni	0:75fc82583a41	2094	}
DiegoOstuni	0:75fc82583a41	2095
DiegoOstuni	0:75fc82583a41	2096	/* fall through */
DiegoOstuni	0:75fc82583a41	2097
DiegoOstuni	0:75fc82583a41	2098
DiegoOstuni	0:75fc82583a41	2099	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	2100	case RFAL_TXRX_STATE_RX_READ_DATA:
DiegoOstuni	0:75fc82583a41	2101
DiegoOstuni	0:75fc82583a41	2102	tmp = rfalFIFOStatusGetNumBytes(mST25, mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	2103
DiegoOstuni	0:75fc82583a41	2104	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	2105	/* Check if CRC should not be placed in rxBuf */
DiegoOstuni	0:75fc82583a41	2106	if( !(gRFAL.TxRx.ctx.flags & RFAL_TXRX_FLAGS_CRC_RX_KEEP) )
DiegoOstuni	0:75fc82583a41	2107	{
DiegoOstuni	0:75fc82583a41	2108	/* Check if CRC is being placed into the FIFO and if received frame was bigger than CRC */
DiegoOstuni	0:75fc82583a41	2109	if( ( st25r3911CheckReg(ST25R3911_REG_AUX, ST25R3911_REG_AUX_crc_2_fifo, ST25R3911_REG_AUX_crc_2_fifo, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) )
DiegoOstuni	0:75fc82583a41	2110	&& ( gRFAL.fifo.bytesTotal + tmp) )
DiegoOstuni	0:75fc82583a41	2111	{
DiegoOstuni	0:75fc82583a41	2112	/* By default CRC will not be placed into the rxBuffer */
DiegoOstuni	0:75fc82583a41	2113	if( ( tmp > RFAL_CRC_LEN) )
DiegoOstuni	0:75fc82583a41	2114	{
DiegoOstuni	0:75fc82583a41	2115	tmp -= RFAL_CRC_LEN;
DiegoOstuni	0:75fc82583a41	2116	}
DiegoOstuni	0:75fc82583a41	2117	/* If the CRC was already placed into rxBuffer (due to WL interrupt where CRC was already in FIFO Read)
DiegoOstuni	0:75fc82583a41	2118	* cannot remove it from rxBuf. Can only remove it from rxBufLen not indicate the presence of CRC */
DiegoOstuni	0:75fc82583a41	2119	else if(gRFAL.fifo.bytesTotal > RFAL_CRC_LEN)
DiegoOstuni	0:75fc82583a41	2120	{
DiegoOstuni	0:75fc82583a41	2121	gRFAL.fifo.bytesTotal -= RFAL_CRC_LEN;
DiegoOstuni	0:75fc82583a41	2122	}
DiegoOstuni	0:75fc82583a41	2123	}
DiegoOstuni	0:75fc82583a41	2124	}
DiegoOstuni	0:75fc82583a41	2125
DiegoOstuni	0:75fc82583a41	2126	gRFAL.fifo.bytesTotal += tmp; /* add to total bytes counter */
DiegoOstuni	0:75fc82583a41	2127
DiegoOstuni	0:75fc82583a41	2128	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	2129	/* Check if remaining bytes fit on the rxBuf available */
DiegoOstuni	0:75fc82583a41	2130	if( gRFAL.fifo.bytesTotal > rfalConvBitsToBytes(gRFAL.TxRx.ctx.rxBufLen) )
DiegoOstuni	0:75fc82583a41	2131	{
DiegoOstuni	0:75fc82583a41	2132	tmp = ( rfalConvBitsToBytes(gRFAL.TxRx.ctx.rxBufLen) - gRFAL.fifo.bytesWritten);
DiegoOstuni	0:75fc82583a41	2133
DiegoOstuni	0:75fc82583a41	2134	gRFAL.TxRx.status = ERR_NOMEM;
DiegoOstuni	0:75fc82583a41	2135	gRFAL.TxRx.state = RFAL_TXRX_STATE_RX_FAIL;
DiegoOstuni	0:75fc82583a41	2136	}
DiegoOstuni	0:75fc82583a41	2137
DiegoOstuni	0:75fc82583a41	2138	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	2139	/* Retrieve remaining bytes from FIFO to rxBuf, and assign total length rcvd */
DiegoOstuni	0:75fc82583a41	2140	mST25 -> readFifo( (uint8_t*)(gRFAL.TxRx.ctx.rxBuf + gRFAL.fifo.bytesWritten), tmp, mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	2141	if( gRFAL.TxRx.ctx.rxRcvdLen )
DiegoOstuni	0:75fc82583a41	2142	{
DiegoOstuni	0:75fc82583a41	2143	(*gRFAL.TxRx.ctx.rxRcvdLen) = rfalConvBytesToBits( gRFAL.fifo.bytesTotal );
DiegoOstuni	0:75fc82583a41	2144	if( rfalFIFOStatusIsIncompleteByte(mST25, mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) )
DiegoOstuni	0:75fc82583a41	2145	{
DiegoOstuni	0:75fc82583a41	2146	(*gRFAL.TxRx.ctx.rxRcvdLen) -= (RFAL_BITS_IN_BYTE - rfalFIFOGetNumIncompleteBits(mST25, mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) );
DiegoOstuni	0:75fc82583a41	2147	}
DiegoOstuni	0:75fc82583a41	2148	}
DiegoOstuni	0:75fc82583a41	2149
DiegoOstuni	0:75fc82583a41	2150	#if RFAL_FEATURE_NFCV
DiegoOstuni	0:75fc82583a41	2151	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	2152	/* Decode sub bit stream into payload bits for NFCV, if no error found so far */
DiegoOstuni	0:75fc82583a41	2153	if( ((RFAL_MODE_POLL_NFCV == gRFAL.mode) \|\| (RFAL_MODE_POLL_PICOPASS == gRFAL.mode)) && (gRFAL.TxRx.status == ERR_BUSY) )
DiegoOstuni	0:75fc82583a41	2154	{
DiegoOstuni	0:75fc82583a41	2155	ReturnCode ret;
DiegoOstuni	0:75fc82583a41	2156	uint16_t offset = 0;
DiegoOstuni	0:75fc82583a41	2157
DiegoOstuni	0:75fc82583a41	2158	ret = iso15693VICCDecode(gRFAL.TxRx.ctx.rxBuf, gRFAL.fifo.bytesTotal,
DiegoOstuni	0:75fc82583a41	2159	gRFAL.nfcvData.origCtx.rxBuf, rfalConvBitsToBytes(gRFAL.nfcvData.origCtx.rxBufLen), &offset, gRFAL.nfcvData.origCtx.rxRcvdLen, gRFAL.nfcvData.ignoreBits, (RFAL_MODE_POLL_PICOPASS == gRFAL.mode) );
DiegoOstuni	0:75fc82583a41	2160
DiegoOstuni	0:75fc82583a41	2161	if( ((ERR_NONE == ret) \|\| (ERR_CRC == ret))
DiegoOstuni	0:75fc82583a41	2162	&& !(RFAL_TXRX_FLAGS_CRC_RX_KEEP & gRFAL.nfcvData.origCtx.flags)
DiegoOstuni	0:75fc82583a41	2163	&& ((*gRFAL.nfcvData.origCtx.rxRcvdLen % RFAL_BITS_IN_BYTE) == 0)
DiegoOstuni	0:75fc82583a41	2164	&& (*gRFAL.nfcvData.origCtx.rxRcvdLen >= rfalConvBytesToBits(RFAL_CRC_LEN) )
DiegoOstuni	0:75fc82583a41	2165	)
DiegoOstuni	0:75fc82583a41	2166	{
DiegoOstuni	0:75fc82583a41	2167	gRFAL.nfcvData.origCtx.rxRcvdLen -= rfalConvBytesToBits(RFAL_CRC_LEN); / Remove CRC */
DiegoOstuni	0:75fc82583a41	2168	}
DiegoOstuni	0:75fc82583a41	2169
DiegoOstuni	0:75fc82583a41	2170	/* Restore original ctx */
DiegoOstuni	0:75fc82583a41	2171	gRFAL.TxRx.ctx = gRFAL.nfcvData.origCtx;
DiegoOstuni	0:75fc82583a41	2172	gRFAL.TxRx.status = ret;
DiegoOstuni	0:75fc82583a41	2173
DiegoOstuni	0:75fc82583a41	2174	if(gRFAL.TxRx.status)
DiegoOstuni	0:75fc82583a41	2175	{
DiegoOstuni	0:75fc82583a41	2176	gRFAL.TxRx.state = RFAL_TXRX_STATE_RX_FAIL;
DiegoOstuni	0:75fc82583a41	2177	break;
DiegoOstuni	0:75fc82583a41	2178	}
DiegoOstuni	0:75fc82583a41	2179	}
DiegoOstuni	0:75fc82583a41	2180	#endif /* RFAL_FEATURE_NFCV */
DiegoOstuni	0:75fc82583a41	2181
DiegoOstuni	0:75fc82583a41	2182	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	2183	/* If an error as been marked/detected don't fall into to RX_DONE */
DiegoOstuni	0:75fc82583a41	2184	if( gRFAL.TxRx.status != ERR_BUSY )
DiegoOstuni	0:75fc82583a41	2185	{
DiegoOstuni	0:75fc82583a41	2186	gRFAL.TxRx.state = RFAL_TXRX_STATE_RX_FAIL;
DiegoOstuni	0:75fc82583a41	2187	break;
DiegoOstuni	0:75fc82583a41	2188	}
DiegoOstuni	0:75fc82583a41	2189
DiegoOstuni	0:75fc82583a41	2190	if( rfalIsModeActiveComm( gRFAL.mode ) )
DiegoOstuni	0:75fc82583a41	2191	{
DiegoOstuni	0:75fc82583a41	2192	gRFAL.TxRx.state = RFAL_TXRX_STATE_RX_WAIT_EOF;
DiegoOstuni	0:75fc82583a41	2193	break;
DiegoOstuni	0:75fc82583a41	2194	}
DiegoOstuni	0:75fc82583a41	2195
DiegoOstuni	0:75fc82583a41	2196	gRFAL.TxRx.state = RFAL_TXRX_STATE_RX_DONE;
DiegoOstuni	0:75fc82583a41	2197	/* fall through */
DiegoOstuni	0:75fc82583a41	2198
DiegoOstuni	0:75fc82583a41	2199
DiegoOstuni	0:75fc82583a41	2200	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	2201	case RFAL_TXRX_STATE_RX_DONE:
DiegoOstuni	0:75fc82583a41	2202
DiegoOstuni	0:75fc82583a41	2203	/Check if Observation Mode was enabled and disable it on ST25R391x /
DiegoOstuni	0:75fc82583a41	2204	rfalCheckDisableObsMode();
DiegoOstuni	0:75fc82583a41	2205
DiegoOstuni	0:75fc82583a41	2206	/* Clean up Transceive */
DiegoOstuni	0:75fc82583a41	2207	rfalCleanupTransceive( mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	2208
DiegoOstuni	0:75fc82583a41	2209
DiegoOstuni	0:75fc82583a41	2210	gRFAL.TxRx.status = ERR_NONE;
DiegoOstuni	0:75fc82583a41	2211	gRFAL.TxRx.state = RFAL_TXRX_STATE_IDLE;
DiegoOstuni	0:75fc82583a41	2212	break;
DiegoOstuni	0:75fc82583a41	2213
DiegoOstuni	0:75fc82583a41	2214
DiegoOstuni	0:75fc82583a41	2215	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	2216	case RFAL_TXRX_STATE_RX_READ_FIFO:
DiegoOstuni	0:75fc82583a41	2217
DiegoOstuni	0:75fc82583a41	2218	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	2219	/* REMARK: Silicon workaround ST25R3911B Errata #1.1 */
DiegoOstuni	0:75fc82583a41	2220	/* ST25R3911 may indicate RXS without RXE afterwards, this happens rarely on */
DiegoOstuni	0:75fc82583a41	2221	/* corrupted frames. */
DiegoOstuni	0:75fc82583a41	2222	/* Re-Start SW timer to handle an eventual missing RXE */
DiegoOstuni	0:75fc82583a41	2223	rfalTimerStart( gRFAL.tmr.RXE, RFAL_NORXE_TOUT );
DiegoOstuni	0:75fc82583a41	2224	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	2225
DiegoOstuni	0:75fc82583a41	2226
DiegoOstuni	0:75fc82583a41	2227	tmp = rfalFIFOStatusGetNumBytes(mST25, mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	2228	gRFAL.fifo.bytesTotal += tmp;
DiegoOstuni	0:75fc82583a41	2229
DiegoOstuni	0:75fc82583a41	2230	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	2231	/* Calculate the amount of bytes that still fits in rxBuf */
DiegoOstuni	0:75fc82583a41	2232	aux = (( gRFAL.fifo.bytesTotal > rfalConvBitsToBytes(gRFAL.TxRx.ctx.rxBufLen) ) ? (rfalConvBitsToBytes(gRFAL.TxRx.ctx.rxBufLen) - gRFAL.fifo.bytesWritten) : tmp);
DiegoOstuni	0:75fc82583a41	2233
DiegoOstuni	0:75fc82583a41	2234	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	2235	/* Retrieve incoming bytes from FIFO to rxBuf, and store already read amount */
DiegoOstuni	0:75fc82583a41	2236	mST25 -> readFifo( (uint8_t*)(gRFAL.TxRx.ctx.rxBuf + gRFAL.fifo.bytesWritten), aux, mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	2237	gRFAL.fifo.bytesWritten += aux;
DiegoOstuni	0:75fc82583a41	2238
DiegoOstuni	0:75fc82583a41	2239	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	2240	/* If the bytes already read were not the full FIFO WL, dump the remaining *
DiegoOstuni	0:75fc82583a41	2241	* FIFO so that ST25R391x can continue with reception */
DiegoOstuni	0:75fc82583a41	2242	if( aux < tmp )
DiegoOstuni	0:75fc82583a41	2243	{
DiegoOstuni	0:75fc82583a41	2244	mST25 -> readFifo( NULL, (tmp - aux), mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	2245	}
DiegoOstuni	0:75fc82583a41	2246
DiegoOstuni	0:75fc82583a41	2247	rfalFIFOStatusClear();
DiegoOstuni	0:75fc82583a41	2248	gRFAL.TxRx.state = RFAL_TXRX_STATE_RX_WAIT_RXE;
DiegoOstuni	0:75fc82583a41	2249	break;
DiegoOstuni	0:75fc82583a41	2250
DiegoOstuni	0:75fc82583a41	2251
DiegoOstuni	0:75fc82583a41	2252	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	2253	case RFAL_TXRX_STATE_RX_FAIL:
DiegoOstuni	0:75fc82583a41	2254
DiegoOstuni	0:75fc82583a41	2255	/Check if Observation Mode was enabled and disable it on ST25R391x /
DiegoOstuni	0:75fc82583a41	2256	rfalCheckDisableObsMode();
DiegoOstuni	0:75fc82583a41	2257
DiegoOstuni	0:75fc82583a41	2258	/* Clean up Transceive */
DiegoOstuni	0:75fc82583a41	2259	rfalCleanupTransceive( mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	2260
DiegoOstuni	0:75fc82583a41	2261	/* Error should be assigned by previous state */
DiegoOstuni	0:75fc82583a41	2262	if( gRFAL.TxRx.status == ERR_BUSY )
DiegoOstuni	0:75fc82583a41	2263	{
DiegoOstuni	0:75fc82583a41	2264	gRFAL.TxRx.status = ERR_SYSTEM;
DiegoOstuni	0:75fc82583a41	2265	}
DiegoOstuni	0:75fc82583a41	2266
DiegoOstuni	0:75fc82583a41	2267	/rfalLogD( "RFAL: curSt: %d Error: %d \r\n", gRFAL.TxRx.state, gRFAL.TxRx.status );/
DiegoOstuni	0:75fc82583a41	2268	gRFAL.TxRx.state = RFAL_TXRX_STATE_IDLE;
DiegoOstuni	0:75fc82583a41	2269	break;
DiegoOstuni	0:75fc82583a41	2270
DiegoOstuni	0:75fc82583a41	2271
DiegoOstuni	0:75fc82583a41	2272	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	2273	case RFAL_TXRX_STATE_RX_WAIT_EON:
DiegoOstuni	0:75fc82583a41	2274
DiegoOstuni	0:75fc82583a41	2275	irqs = st25r3911GetInterrupt( (ST25R3911_IRQ_MASK_EON \| ST25R3911_IRQ_MASK_NRE), mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	2276	if( irqs == ST25R3911_IRQ_MASK_NONE )
DiegoOstuni	0:75fc82583a41	2277	{
DiegoOstuni	0:75fc82583a41	2278	break; /* No interrupt to process */
DiegoOstuni	0:75fc82583a41	2279	}
DiegoOstuni	0:75fc82583a41	2280
DiegoOstuni	0:75fc82583a41	2281	if( (irqs & ST25R3911_IRQ_MASK_EON) )
DiegoOstuni	0:75fc82583a41	2282	{
DiegoOstuni	0:75fc82583a41	2283	gRFAL.TxRx.state = RFAL_TXRX_STATE_RX_WAIT_RXS;
DiegoOstuni	0:75fc82583a41	2284	}
DiegoOstuni	0:75fc82583a41	2285
DiegoOstuni	0:75fc82583a41	2286	if( (irqs & ST25R3911_IRQ_MASK_NRE) )
DiegoOstuni	0:75fc82583a41	2287	{
DiegoOstuni	0:75fc82583a41	2288	/* ST25R3911 uses the NRT to measure other device's Field On max time: Tadt + (n x Trfw) */
DiegoOstuni	0:75fc82583a41	2289	gRFAL.TxRx.status = ERR_LINK_LOSS;
DiegoOstuni	0:75fc82583a41	2290	gRFAL.TxRx.state = RFAL_TXRX_STATE_RX_FAIL;
DiegoOstuni	0:75fc82583a41	2291	}
DiegoOstuni	0:75fc82583a41	2292	break;
DiegoOstuni	0:75fc82583a41	2293
DiegoOstuni	0:75fc82583a41	2294
DiegoOstuni	0:75fc82583a41	2295	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	2296	case RFAL_TXRX_STATE_RX_WAIT_EOF:
DiegoOstuni	0:75fc82583a41	2297
DiegoOstuni	0:75fc82583a41	2298	irqs = st25r3911GetInterrupt( (ST25R3911_IRQ_MASK_CAT \| ST25R3911_IRQ_MASK_CAC), mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	2299	if( irqs == ST25R3911_IRQ_MASK_NONE )
DiegoOstuni	0:75fc82583a41	2300	{
DiegoOstuni	0:75fc82583a41	2301	break; /* No interrupt to process */
DiegoOstuni	0:75fc82583a41	2302	}
DiegoOstuni	0:75fc82583a41	2303
DiegoOstuni	0:75fc82583a41	2304	if( (irqs & ST25R3911_IRQ_MASK_CAT) )
DiegoOstuni	0:75fc82583a41	2305	{
DiegoOstuni	0:75fc82583a41	2306	gRFAL.TxRx.state = RFAL_TXRX_STATE_RX_DONE;
DiegoOstuni	0:75fc82583a41	2307	}
DiegoOstuni	0:75fc82583a41	2308	else if( (irqs & ST25R3911_IRQ_MASK_CAC) )
DiegoOstuni	0:75fc82583a41	2309	{
DiegoOstuni	0:75fc82583a41	2310	gRFAL.TxRx.status = ERR_RF_COLLISION;
DiegoOstuni	0:75fc82583a41	2311	gRFAL.TxRx.state = RFAL_TXRX_STATE_RX_FAIL;
DiegoOstuni	0:75fc82583a41	2312	}
DiegoOstuni	0:75fc82583a41	2313	else
DiegoOstuni	0:75fc82583a41	2314	{
DiegoOstuni	0:75fc82583a41	2315	gRFAL.TxRx.status = ERR_IO;
DiegoOstuni	0:75fc82583a41	2316	gRFAL.TxRx.state = RFAL_TXRX_STATE_RX_FAIL;
DiegoOstuni	0:75fc82583a41	2317	}
DiegoOstuni	0:75fc82583a41	2318	break;
DiegoOstuni	0:75fc82583a41	2319
DiegoOstuni	0:75fc82583a41	2320
DiegoOstuni	0:75fc82583a41	2321	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	2322	default:
DiegoOstuni	0:75fc82583a41	2323	gRFAL.TxRx.status = ERR_SYSTEM;
DiegoOstuni	0:75fc82583a41	2324	gRFAL.TxRx.state = RFAL_TXRX_STATE_RX_FAIL;
DiegoOstuni	0:75fc82583a41	2325	break;
DiegoOstuni	0:75fc82583a41	2326	}
DiegoOstuni	0:75fc82583a41	2327	}
DiegoOstuni	0:75fc82583a41	2328
DiegoOstuni	0:75fc82583a41	2329	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	2330	static void rfalFIFOStatusUpdate( ST25R3911* mST25, SPI * mspiChannel, DigitalOut* gpio_cs, InterruptIn* IRQ, DigitalOut* fieldLED_01, DigitalOut* fieldLED_02, DigitalOut* fieldLED_03, DigitalOut* fieldLED_04, DigitalOut* fieldLED_05, DigitalOut* fieldLED_06 )
DiegoOstuni	0:75fc82583a41	2331	{
DiegoOstuni	0:75fc82583a41	2332	if(gRFAL.fifo.status[RFAL_FIFO_STATUS_REG2] == RFAL_FIFO_STATUS_INVALID)
DiegoOstuni	0:75fc82583a41	2333	{
DiegoOstuni	0:75fc82583a41	2334	mST25 -> readMultipleRegisters( ST25R3911_REG_FIFO_RX_STATUS1, gRFAL.fifo.status, ST25R3911_FIFO_STATUS_LEN, mspiChannel,mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	2335	}
DiegoOstuni	0:75fc82583a41	2336	}
DiegoOstuni	0:75fc82583a41	2337
DiegoOstuni	0:75fc82583a41	2338
DiegoOstuni	0:75fc82583a41	2339	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	2340	static void rfalFIFOStatusClear( void )
DiegoOstuni	0:75fc82583a41	2341	{
DiegoOstuni	0:75fc82583a41	2342	gRFAL.fifo.status[RFAL_FIFO_STATUS_REG2] = RFAL_FIFO_STATUS_INVALID;
DiegoOstuni	0:75fc82583a41	2343	}
DiegoOstuni	0:75fc82583a41	2344
DiegoOstuni	0:75fc82583a41	2345
DiegoOstuni	0:75fc82583a41	2346	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	2347	static uint8_t rfalFIFOStatusGetNumBytes( ST25R3911* mST25, SPI * mspiChannel, DigitalOut* gpio_cs, InterruptIn* IRQ, DigitalOut* fieldLED_01, DigitalOut* fieldLED_02, DigitalOut* fieldLED_03, DigitalOut* fieldLED_04, DigitalOut* fieldLED_05, DigitalOut* fieldLED_06 )
DiegoOstuni	0:75fc82583a41	2348	{
DiegoOstuni	0:75fc82583a41	2349	rfalFIFOStatusUpdate(mST25, mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	2350
DiegoOstuni	0:75fc82583a41	2351	return gRFAL.fifo.status[RFAL_FIFO_STATUS_REG1];
DiegoOstuni	0:75fc82583a41	2352
DiegoOstuni	0:75fc82583a41	2353	}
DiegoOstuni	0:75fc82583a41	2354
DiegoOstuni	0:75fc82583a41	2355
DiegoOstuni	0:75fc82583a41	2356	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	2357	static bool rfalFIFOStatusIsIncompleteByte( ST25R3911* mST25, SPI * mspiChannel, DigitalOut* gpio_cs, InterruptIn* IRQ, DigitalOut* fieldLED_01, DigitalOut* fieldLED_02, DigitalOut* fieldLED_03, DigitalOut* fieldLED_04, DigitalOut* fieldLED_05, DigitalOut* fieldLED_06 )
DiegoOstuni	0:75fc82583a41	2358	{
DiegoOstuni	0:75fc82583a41	2359	rfalFIFOStatusUpdate(mST25, mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	2360	return ((gRFAL.fifo.status[RFAL_FIFO_STATUS_REG2] & (ST25R3911_REG_FIFO_RX_STATUS2_mask_fifo_lb \| ST25R3911_REG_FIFO_RX_STATUS2_fifo_ncp)) != 0);
DiegoOstuni	0:75fc82583a41	2361	}
DiegoOstuni	0:75fc82583a41	2362
DiegoOstuni	0:75fc82583a41	2363
DiegoOstuni	0:75fc82583a41	2364	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	2365	static bool rfalFIFOStatusIsMissingPar( ST25R3911* mST25, SPI * mspiChannel, DigitalOut* gpio_cs, InterruptIn* IRQ, DigitalOut* fieldLED_01, DigitalOut* fieldLED_02, DigitalOut* fieldLED_03, DigitalOut* fieldLED_04, DigitalOut* fieldLED_05, DigitalOut* fieldLED_06 )
DiegoOstuni	0:75fc82583a41	2366	{
DiegoOstuni	0:75fc82583a41	2367	rfalFIFOStatusUpdate(mST25, mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	2368	return ((gRFAL.fifo.status[RFAL_FIFO_STATUS_REG2] & ST25R3911_REG_FIFO_RX_STATUS2_np_lb) != 0);
DiegoOstuni	0:75fc82583a41	2369	}
DiegoOstuni	0:75fc82583a41	2370
DiegoOstuni	0:75fc82583a41	2371
DiegoOstuni	0:75fc82583a41	2372	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	2373	static uint8_t rfalFIFOGetNumIncompleteBits( ST25R3911* mST25, SPI * mspiChannel, DigitalOut* gpio_cs, InterruptIn* IRQ, DigitalOut* fieldLED_01, DigitalOut* fieldLED_02, DigitalOut* fieldLED_03, DigitalOut* fieldLED_04, DigitalOut* fieldLED_05, DigitalOut* fieldLED_06 )
DiegoOstuni	0:75fc82583a41	2374	{
DiegoOstuni	0:75fc82583a41	2375	rfalFIFOStatusUpdate(mST25, mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	2376	return ((gRFAL.fifo.status[RFAL_FIFO_STATUS_REG2] & ST25R3911_REG_FIFO_RX_STATUS2_mask_fifo_lb) >> ST25R3911_REG_FIFO_RX_STATUS2_shift_fifo_lb);
DiegoOstuni	0:75fc82583a41	2377	}
DiegoOstuni	0:75fc82583a41	2378
DiegoOstuni	0:75fc82583a41	2379
DiegoOstuni	0:75fc82583a41	2380	#if RFAL_FEATURE_NFCA
DiegoOstuni	0:75fc82583a41	2381
DiegoOstuni	0:75fc82583a41	2382	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	2383	ReturnCode rfalISO14443ATransceiveShortFrame( rfal14443AShortFrameCmd txCmd, uint8_t* rxBuf, uint8_t rxBufLen, uint16_t* rxRcvdLen, uint32_t fwt, SPI* mspiChannel, ST25R3911* mST25, DigitalOut* gpio_cs, InterruptIn* IRQ, DigitalOut* fieldLED_01, DigitalOut* fieldLED_02, DigitalOut* fieldLED_03, DigitalOut* fieldLED_04, DigitalOut* fieldLED_05, DigitalOut* fieldLED_06 )
DiegoOstuni	0:75fc82583a41	2384	{
DiegoOstuni	0:75fc82583a41	2385	ReturnCode ret;
DiegoOstuni	0:75fc82583a41	2386	uint8_t directCmd;
DiegoOstuni	0:75fc82583a41	2387
DiegoOstuni	0:75fc82583a41	2388	/* Check if RFAL is properly initialized */
DiegoOstuni	0:75fc82583a41	2389	if( (gRFAL.state < RFAL_STATE_MODE_SET) \|\| (( gRFAL.mode != RFAL_MODE_POLL_NFCA ) && ( gRFAL.mode != RFAL_MODE_POLL_NFCA_T1T )) \|\|
DiegoOstuni	0:75fc82583a41	2390	!( st25r3911CheckReg(ST25R3911_REG_OP_CONTROL, ST25R3911_REG_OP_CONTROL_tx_en, ST25R3911_REG_OP_CONTROL_tx_en, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ) )
DiegoOstuni	0:75fc82583a41	2391	{
DiegoOstuni	0:75fc82583a41	2392	return ERR_WRONG_STATE;
DiegoOstuni	0:75fc82583a41	2393	}
DiegoOstuni	0:75fc82583a41	2394
DiegoOstuni	0:75fc82583a41	2395	/* Check for valid parameters */
DiegoOstuni	0:75fc82583a41	2396	if( (rxBuf == NULL) \|\| (rxRcvdLen == NULL) \|\| (fwt == RFAL_FWT_NONE) )
DiegoOstuni	0:75fc82583a41	2397	{
DiegoOstuni	0:75fc82583a41	2398	return ERR_PARAM;
DiegoOstuni	0:75fc82583a41	2399	}
DiegoOstuni	0:75fc82583a41	2400
DiegoOstuni	0:75fc82583a41	2401	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	2402	/* Select the Direct Command to be performed */
DiegoOstuni	0:75fc82583a41	2403	switch (txCmd)
DiegoOstuni	0:75fc82583a41	2404	{
DiegoOstuni	0:75fc82583a41	2405	case RFAL_14443A_SHORTFRAME_CMD_WUPA:
DiegoOstuni	0:75fc82583a41	2406	directCmd = ST25R3911_CMD_TRANSMIT_WUPA;
DiegoOstuni	0:75fc82583a41	2407	break;
DiegoOstuni	0:75fc82583a41	2408
DiegoOstuni	0:75fc82583a41	2409	case RFAL_14443A_SHORTFRAME_CMD_REQA:
DiegoOstuni	0:75fc82583a41	2410	directCmd = ST25R3911_CMD_TRANSMIT_REQA;
DiegoOstuni	0:75fc82583a41	2411	break;
DiegoOstuni	0:75fc82583a41	2412
DiegoOstuni	0:75fc82583a41	2413	default:
DiegoOstuni	0:75fc82583a41	2414	return ERR_PARAM;
DiegoOstuni	0:75fc82583a41	2415	}
DiegoOstuni	0:75fc82583a41	2416
DiegoOstuni	0:75fc82583a41	2417
DiegoOstuni	0:75fc82583a41	2418	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	2419	/* Enable anti collision to recognise collision in first byte of SENS_REQ */
DiegoOstuni	0:75fc82583a41	2420	st25r3911SetRegisterBits( ST25R3911_REG_ISO14443A_NFC, ST25R3911_REG_ISO14443A_NFC_antcl, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	2421
DiegoOstuni	0:75fc82583a41	2422	/* Disable CRC while receiving since ATQA has no CRC included */
DiegoOstuni	0:75fc82583a41	2423	st25r3911SetRegisterBits( ST25R3911_REG_AUX, ST25R3911_REG_AUX_no_crc_rx, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	2424
DiegoOstuni	0:75fc82583a41	2425
DiegoOstuni	0:75fc82583a41	2426	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	2427	/* Wait for GT and FDT */
DiegoOstuni	0:75fc82583a41	2428	while( !rfalIsGTExpired() );
DiegoOstuni	0:75fc82583a41	2429	while( st25r3911CheckReg(ST25R3911_REG_REGULATOR_RESULT, ST25R3911_REG_REGULATOR_RESULT_gpt_on, ST25R3911_REG_REGULATOR_RESULT_gpt_on, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) );
DiegoOstuni	0:75fc82583a41	2430
DiegoOstuni	0:75fc82583a41	2431	gRFAL.tmr.GT = RFAL_TIMING_NONE;
DiegoOstuni	0:75fc82583a41	2432
DiegoOstuni	0:75fc82583a41	2433
DiegoOstuni	0:75fc82583a41	2434	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	2435	/* Prepare for Transceive, Receive only (bypass Tx states) */
DiegoOstuni	0:75fc82583a41	2436	gRFAL.TxRx.ctx.flags = ( RFAL_TXRX_FLAGS_CRC_TX_MANUAL \| RFAL_TXRX_FLAGS_CRC_RX_KEEP );
DiegoOstuni	0:75fc82583a41	2437	gRFAL.TxRx.ctx.rxBuf = rxBuf;
DiegoOstuni	0:75fc82583a41	2438	gRFAL.TxRx.ctx.rxBufLen = rxBufLen;
DiegoOstuni	0:75fc82583a41	2439	gRFAL.TxRx.ctx.rxRcvdLen = rxRcvdLen;
DiegoOstuni	0:75fc82583a41	2440
DiegoOstuni	0:75fc82583a41	2441	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	2442	/* Load NRT with FWT */
DiegoOstuni	0:75fc82583a41	2443	st25r3911SetNoResponseTime_64fcs( rfalConv1fcTo64fc( MIN( (fwt + RFAL_FWT_ADJUSTMENT + RFAL_FWT_A_ADJUSTMENT), RFAL_ST25R3911_NRT_MAX_1FC ) ),
DiegoOstuni	0:75fc82583a41	2444	mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	2445
DiegoOstuni	0:75fc82583a41	2446	if( gRFAL.timings.FDTListen != RFAL_TIMING_NONE )
DiegoOstuni	0:75fc82583a41	2447	{
DiegoOstuni	0:75fc82583a41	2448	/* Set Minimum FDT(Listen) in which PICC is not allowed to send a response */
DiegoOstuni	0:75fc82583a41	2449	mST25 -> writeRegister( ST25R3911_REG_MASK_RX_TIMER, rfalConv1fcTo64fc( ((RFAL_FDT_LISTEN_MRT_ADJUSTMENT + RFAL_FDT_LISTEN_A_ADJUSTMENT) > gRFAL.timings.FDTListen) ? RFAL_ST25R3911_MRT_MIN_1FC : (gRFAL.timings.FDTListen - (RFAL_FDT_LISTEN_MRT_ADJUSTMENT + RFAL_FDT_LISTEN_A_ADJUSTMENT)) ),
DiegoOstuni	0:75fc82583a41	2450	mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	2451	}
DiegoOstuni	0:75fc82583a41	2452
DiegoOstuni	0:75fc82583a41	2453	/* In Passive communications General Purpose Timer is used to measure FDT Poll */
DiegoOstuni	0:75fc82583a41	2454	if( gRFAL.timings.FDTPoll != RFAL_TIMING_NONE )
DiegoOstuni	0:75fc82583a41	2455	{
DiegoOstuni	0:75fc82583a41	2456	/* Configure GPT to start at RX end */
DiegoOstuni	0:75fc82583a41	2457	st25r3911StartGPTimer_8fcs( rfalConv1fcTo8fc( MIN( gRFAL.timings.FDTPoll, (gRFAL.timings.FDTPoll - RFAL_FDT_POLL_ADJUSTMENT) ) ), ST25R3911_REG_GPT_CONTROL_gptc_erx,
DiegoOstuni	0:75fc82583a41	2458	mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	2459	}
DiegoOstuni	0:75fc82583a41	2460
DiegoOstuni	0:75fc82583a41	2461	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	2462	rfalPrepareTransceive( mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	2463
DiegoOstuni	0:75fc82583a41	2464	/* Also enable bit collision interrupt */
DiegoOstuni	0:75fc82583a41	2465	st25r3911GetInterrupt( ST25R3911_IRQ_MASK_COL, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	2466	st25r3911EnableInterrupts( ST25R3911_IRQ_MASK_COL, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	2467
DiegoOstuni	0:75fc82583a41	2468	/Check if Observation Mode is enabled and set it on ST25R391x /
DiegoOstuni	0:75fc82583a41	2469	rfalCheckEnableObsModeTx();
DiegoOstuni	0:75fc82583a41	2470
DiegoOstuni	0:75fc82583a41	2471	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	2472	/* Chip bug: Clear nbtx bits before sending WUPA/REQA - otherwise ST25R3911 will report parity error */
DiegoOstuni	0:75fc82583a41	2473	mST25 -> writeRegister( ST25R3911_REG_NUM_TX_BYTES2, 0, mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	2474
DiegoOstuni	0:75fc82583a41	2475	/* Send either WUPA or REQA. All affected tags will backscatter ATQA and change to READY state */
DiegoOstuni	0:75fc82583a41	2476	mST25 -> executeCommand( directCmd, mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	2477
DiegoOstuni	0:75fc82583a41	2478	/* Wait for TXE */
DiegoOstuni	0:75fc82583a41	2479	if( !st25r3911WaitForInterruptsTimed( ST25R3911_IRQ_MASK_TXE, MAX( rfalConv1fcToMs( fwt ), RFAL_ST25R3911_SW_TMR_MIN_1MS ), mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) )
DiegoOstuni	0:75fc82583a41	2480	{
DiegoOstuni	0:75fc82583a41	2481	ret = ERR_IO;
DiegoOstuni	0:75fc82583a41	2482	}
DiegoOstuni	0:75fc82583a41	2483	else
DiegoOstuni	0:75fc82583a41	2484	{
DiegoOstuni	0:75fc82583a41	2485	/Check if Observation Mode is enabled and set it on ST25R391x /
DiegoOstuni	0:75fc82583a41	2486	rfalCheckEnableObsModeRx();
DiegoOstuni	0:75fc82583a41	2487
DiegoOstuni	0:75fc82583a41	2488	/* Jump into a transceive Rx state for reception (bypass Tx states) */
DiegoOstuni	0:75fc82583a41	2489	gRFAL.state = RFAL_STATE_TXRX;
DiegoOstuni	0:75fc82583a41	2490	gRFAL.TxRx.state = RFAL_TXRX_STATE_RX_IDLE;
DiegoOstuni	0:75fc82583a41	2491	gRFAL.TxRx.status = ERR_BUSY;
DiegoOstuni	0:75fc82583a41	2492
DiegoOstuni	0:75fc82583a41	2493	/* Execute Transceive Rx blocking */
DiegoOstuni	0:75fc82583a41	2494	ret = rfalTransceiveBlockingRx( mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	2495	}
DiegoOstuni	0:75fc82583a41	2496
DiegoOstuni	0:75fc82583a41	2497
DiegoOstuni	0:75fc82583a41	2498	/* Disable Collision interrupt */
DiegoOstuni	0:75fc82583a41	2499	st25r3911DisableInterrupts( (ST25R3911_IRQ_MASK_COL), mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	2500
DiegoOstuni	0:75fc82583a41	2501	/* Disable anti collision again */
DiegoOstuni	0:75fc82583a41	2502	st25r3911ClrRegisterBits( ST25R3911_REG_ISO14443A_NFC, ST25R3911_REG_ISO14443A_NFC_antcl, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	2503
DiegoOstuni	0:75fc82583a41	2504	/* ReEnable CRC on Rx */
DiegoOstuni	0:75fc82583a41	2505	st25r3911ClrRegisterBits(ST25R3911_REG_AUX, ST25R3911_REG_AUX_no_crc_rx, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 );
DiegoOstuni	0:75fc82583a41	2506
DiegoOstuni	0:75fc82583a41	2507	return ret;
DiegoOstuni	0:75fc82583a41	2508	}
DiegoOstuni	0:75fc82583a41	2509
DiegoOstuni	0:75fc82583a41	2510	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	2511	ReturnCode rfalISO14443ATransceiveAnticollisionFrame( uint8_t buf, uint8_t bytesToSend, uint8_t *bitsToSend,
DiegoOstuni	0:75fc82583a41	2512	uint16_t rxLength, uint32_t fwt, SPI mspiChannel, ST25R3911* mST25, DigitalOut* gpio_cs, InterruptIn* IRQ, DigitalOut* fieldLED_01, DigitalOut* fieldLED_02, DigitalOut* fieldLED_03, DigitalOut* fieldLED_04, DigitalOut* fieldLED_05, DigitalOut* fieldLED_06 )
DiegoOstuni	0:75fc82583a41	2513	{
DiegoOstuni	0:75fc82583a41	2514	ReturnCode ret;
DiegoOstuni	0:75fc82583a41	2515	rfalTransceiveContext ctx;
DiegoOstuni	0:75fc82583a41	2516	uint8_t collByte;
DiegoOstuni	0:75fc82583a41	2517	uint8_t collData;
DiegoOstuni	0:75fc82583a41	2518
DiegoOstuni	0:75fc82583a41	2519	/* Check if RFAL is properly initialized */
DiegoOstuni	0:75fc82583a41	2520	if( (gRFAL.state < RFAL_STATE_MODE_SET) \|\| ( gRFAL.mode != RFAL_MODE_POLL_NFCA ) )
DiegoOstuni	0:75fc82583a41	2521	{
DiegoOstuni	0:75fc82583a41	2522	return ERR_WRONG_STATE;
DiegoOstuni	0:75fc82583a41	2523	}
DiegoOstuni	0:75fc82583a41	2524
DiegoOstuni	0:75fc82583a41	2525	/* Check for valid parameters */
DiegoOstuni	0:75fc82583a41	2526	if( (buf == NULL) \|\| (bytesToSend == NULL) \|\| (bitsToSend == NULL) \|\| (rxLength == NULL) )
DiegoOstuni	0:75fc82583a41	2527	{
DiegoOstuni	0:75fc82583a41	2528	return ERR_PARAM;
DiegoOstuni	0:75fc82583a41	2529	}
DiegoOstuni	0:75fc82583a41	2530
DiegoOstuni	0:75fc82583a41	2531	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	2532	/* Enable anti collision to recognise collision in first byte of SENS_REQ */
DiegoOstuni	0:75fc82583a41	2533	st25r3911SetRegisterBits( ST25R3911_REG_ISO14443A_NFC, ST25R3911_REG_ISO14443A_NFC_antcl, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	2534
DiegoOstuni	0:75fc82583a41	2535	/* Disable CRC while receiving */
DiegoOstuni	0:75fc82583a41	2536	st25r3911SetRegisterBits( ST25R3911_REG_AUX, ST25R3911_REG_AUX_no_crc_rx, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	2537
DiegoOstuni	0:75fc82583a41	2538
DiegoOstuni	0:75fc82583a41	2539
DiegoOstuni	0:75fc82583a41	2540	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	2541	/* Prepare for Transceive */
DiegoOstuni	0:75fc82583a41	2542	ctx.flags = ( RFAL_TXRX_FLAGS_CRC_TX_MANUAL \| RFAL_TXRX_FLAGS_CRC_RX_KEEP \| RFAL_TXRX_FLAGS_AGC_OFF ); /* Disable Automatic Gain Control (AGC) for better detection of collision */
DiegoOstuni	0:75fc82583a41	2543	ctx.txBuf = buf;
DiegoOstuni	0:75fc82583a41	2544	ctx.txBufLen = (rfalConvBytesToBits( bytesToSend ) + bitsToSend );
DiegoOstuni	0:75fc82583a41	2545	ctx.rxBuf = (buf + (*bytesToSend));
DiegoOstuni	0:75fc82583a41	2546	ctx.rxBufLen = rfalConvBytesToBits( RFAL_ISO14443A_SDD_RES_LEN );
DiegoOstuni	0:75fc82583a41	2547	ctx.rxRcvdLen = rxLength;
DiegoOstuni	0:75fc82583a41	2548	ctx.fwt = fwt;
DiegoOstuni	0:75fc82583a41	2549
DiegoOstuni	0:75fc82583a41	2550	rfalStartTransceive( &ctx, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	2551
DiegoOstuni	0:75fc82583a41	2552	/* Additionally enable bit collision interrupt */
DiegoOstuni	0:75fc82583a41	2553	st25r3911GetInterrupt( ST25R3911_IRQ_MASK_COL, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	2554	st25r3911EnableInterrupts( ST25R3911_IRQ_MASK_COL, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	2555
DiegoOstuni	0:75fc82583a41	2556	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	2557	collByte = 0;
DiegoOstuni	0:75fc82583a41	2558
DiegoOstuni	0:75fc82583a41	2559	/* save the collision byte */
DiegoOstuni	0:75fc82583a41	2560	if ((*bitsToSend) > 0)
DiegoOstuni	0:75fc82583a41	2561	{
DiegoOstuni	0:75fc82583a41	2562	buf[(bytesToSend)] <<= (RFAL_BITS_IN_BYTE - (bitsToSend));
DiegoOstuni	0:75fc82583a41	2563	buf[(bytesToSend)] >>= (RFAL_BITS_IN_BYTE - (bitsToSend));
DiegoOstuni	0:75fc82583a41	2564	collByte = buf[(*bytesToSend)];
DiegoOstuni	0:75fc82583a41	2565	}
DiegoOstuni	0:75fc82583a41	2566
DiegoOstuni	0:75fc82583a41	2567
DiegoOstuni	0:75fc82583a41	2568	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	2569	/* Run Transceive blocking */
DiegoOstuni	0:75fc82583a41	2570	ret = rfalTransceiveRunBlockingTx( mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	2571	if( ret == ERR_NONE)
DiegoOstuni	0:75fc82583a41	2572	{
DiegoOstuni	0:75fc82583a41	2573	ret = rfalTransceiveBlockingRx( mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 );
DiegoOstuni	0:75fc82583a41	2574
DiegoOstuni	0:75fc82583a41	2575	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	2576	if ((*bitsToSend) > 0)
DiegoOstuni	0:75fc82583a41	2577	{
DiegoOstuni	0:75fc82583a41	2578	buf[(bytesToSend)] >>= (bitsToSend);
DiegoOstuni	0:75fc82583a41	2579	buf[(bytesToSend)] <<= (bitsToSend);
DiegoOstuni	0:75fc82583a41	2580	buf[(*bytesToSend)] \|= collByte;
DiegoOstuni	0:75fc82583a41	2581	}
DiegoOstuni	0:75fc82583a41	2582
DiegoOstuni	0:75fc82583a41	2583	if( (ERR_RF_COLLISION == ret) )
DiegoOstuni	0:75fc82583a41	2584	{
DiegoOstuni	0:75fc82583a41	2585	/* read out collision register */
DiegoOstuni	0:75fc82583a41	2586	mST25 -> readRegister( ST25R3911_REG_COLLISION_STATUS, &collData, mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	2587
DiegoOstuni	0:75fc82583a41	2588	(bytesToSend) = ((collData >> ST25R3911_REG_COLLISION_STATUS_shift_c_byte) & 0x0F); / 4-bits Byte information */
DiegoOstuni	0:75fc82583a41	2589	(bitsToSend) = ((collData >> ST25R3911_REG_COLLISION_STATUS_shift_c_bit) & 0x07); / 3-bits bit information */
DiegoOstuni	0:75fc82583a41	2590
DiegoOstuni	0:75fc82583a41	2591	}
DiegoOstuni	0:75fc82583a41	2592	}
DiegoOstuni	0:75fc82583a41	2593
DiegoOstuni	0:75fc82583a41	2594
DiegoOstuni	0:75fc82583a41	2595	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	2596	/* Disable Collision interrupt */
DiegoOstuni	0:75fc82583a41	2597	st25r3911DisableInterrupts( (ST25R3911_IRQ_MASK_COL), mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	2598
DiegoOstuni	0:75fc82583a41	2599	/* Disable anti collision again */
DiegoOstuni	0:75fc82583a41	2600	st25r3911ClrRegisterBits( ST25R3911_REG_ISO14443A_NFC, ST25R3911_REG_ISO14443A_NFC_antcl, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	2601
DiegoOstuni	0:75fc82583a41	2602	/* ReEnable CRC on Rx */
DiegoOstuni	0:75fc82583a41	2603	st25r3911ClrRegisterBits( ST25R3911_REG_AUX, ST25R3911_REG_AUX_no_crc_rx, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	2604
DiegoOstuni	0:75fc82583a41	2605	return ret;
DiegoOstuni	0:75fc82583a41	2606	}
DiegoOstuni	0:75fc82583a41	2607
DiegoOstuni	0:75fc82583a41	2608	#endif /* RFAL_FEATURE_NFCA */
DiegoOstuni	0:75fc82583a41	2609
DiegoOstuni	0:75fc82583a41	2610	#if RFAL_FEATURE_NFCV
DiegoOstuni	0:75fc82583a41	2611
DiegoOstuni	0:75fc82583a41	2612	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	2613	ReturnCode rfalISO15693TransceiveAnticollisionFrame( uint8_t txBuf, uint8_t txBufLen, uint8_t rxBuf, uint8_t rxBufLen, uint16_t actLen, SPI mspiChannel, ST25R3911* mST25, DigitalOut* gpio_cs, InterruptIn* IRQ, DigitalOut* fieldLED_01, DigitalOut* fieldLED_02, DigitalOut* fieldLED_03, DigitalOut* fieldLED_04, DigitalOut* fieldLED_05, DigitalOut* fieldLED_06 )
DiegoOstuni	0:75fc82583a41	2614	{
DiegoOstuni	0:75fc82583a41	2615	ReturnCode ret;
DiegoOstuni	0:75fc82583a41	2616	rfalTransceiveContext ctx;
DiegoOstuni	0:75fc82583a41	2617
DiegoOstuni	0:75fc82583a41	2618	/* Check if RFAL is properly initialized */
DiegoOstuni	0:75fc82583a41	2619	if( (gRFAL.state < RFAL_STATE_MODE_SET) \|\| ( gRFAL.mode != RFAL_MODE_POLL_NFCV ) )
DiegoOstuni	0:75fc82583a41	2620	{
DiegoOstuni	0:75fc82583a41	2621	return ERR_WRONG_STATE;
DiegoOstuni	0:75fc82583a41	2622	}
DiegoOstuni	0:75fc82583a41	2623
DiegoOstuni	0:75fc82583a41	2624	/* Ignoring collisions before the UID (RES_FLAG + DSFID) */
DiegoOstuni	0:75fc82583a41	2625	gRFAL.nfcvData.ignoreBits = RFAL_ISO15693_IGNORE_BITS;
DiegoOstuni	0:75fc82583a41	2626
DiegoOstuni	0:75fc82583a41	2627	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	2628	/* Prepare for Transceive */
DiegoOstuni	0:75fc82583a41	2629	ctx.flags = ( ((txBufLen==0)?RFAL_TXRX_FLAGS_CRC_TX_MANUAL:RFAL_TXRX_FLAGS_CRC_TX_AUTO) \| RFAL_TXRX_FLAGS_CRC_RX_KEEP \| RFAL_TXRX_FLAGS_AGC_OFF \| ((txBufLen==0)?RFAL_TXRX_FLAGS_NFCV_FLAG_MANUAL:RFAL_TXRX_FLAGS_NFCV_FLAG_AUTO) ); /* Disable Automatic Gain Control (AGC) for better detection of collision */
DiegoOstuni	0:75fc82583a41	2630	ctx.txBuf = txBuf;
DiegoOstuni	0:75fc82583a41	2631	ctx.txBufLen = rfalConvBytesToBits(txBufLen);
DiegoOstuni	0:75fc82583a41	2632	ctx.rxBuf = rxBuf;
DiegoOstuni	0:75fc82583a41	2633	ctx.rxBufLen = rfalConvBytesToBits(rxBufLen);
DiegoOstuni	0:75fc82583a41	2634	ctx.rxRcvdLen = actLen;
DiegoOstuni	0:75fc82583a41	2635	ctx.fwt = rfalConv64fcTo1fc(ISO15693_NO_RESPONSE_TIME);
DiegoOstuni	0:75fc82583a41	2636
DiegoOstuni	0:75fc82583a41	2637	rfalStartTransceive( &ctx, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	2638
DiegoOstuni	0:75fc82583a41	2639	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	2640	/* Run Transceive blocking */
DiegoOstuni	0:75fc82583a41	2641	ret = rfalTransceiveRunBlockingTx( mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	2642	if( ret == ERR_NONE)
DiegoOstuni	0:75fc82583a41	2643	{
DiegoOstuni	0:75fc82583a41	2644	ret = rfalTransceiveBlockingRx( mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	2645	}
DiegoOstuni	0:75fc82583a41	2646
DiegoOstuni	0:75fc82583a41	2647	gRFAL.nfcvData.ignoreBits = 0;
DiegoOstuni	0:75fc82583a41	2648	return ret;
DiegoOstuni	0:75fc82583a41	2649	}
DiegoOstuni	0:75fc82583a41	2650
DiegoOstuni	0:75fc82583a41	2651	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	2652	ReturnCode rfalISO15693TransceiveAnticollisionEOF( uint8_t rxBuf, uint8_t rxBufLen, uint16_t actLen, SPI* mspiChannel,
DiegoOstuni	0:75fc82583a41	2653	ST25R3911* mST25, DigitalOut* gpio_cs, InterruptIn* IRQ, DigitalOut* fieldLED_01, DigitalOut* fieldLED_02, DigitalOut* fieldLED_03, DigitalOut* fieldLED_04, DigitalOut* fieldLED_05, DigitalOut* fieldLED_06 )
DiegoOstuni	0:75fc82583a41	2654	{
DiegoOstuni	0:75fc82583a41	2655	uint8_t dummy;
DiegoOstuni	0:75fc82583a41	2656
DiegoOstuni	0:75fc82583a41	2657	return rfalISO15693TransceiveAnticollisionFrame( &dummy, 0, rxBuf, rxBufLen, actLen, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	2658	}
DiegoOstuni	0:75fc82583a41	2659
DiegoOstuni	0:75fc82583a41	2660	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	2661	ReturnCode rfalISO15693TransceiveEOF( uint8_t rxBuf, uint8_t rxBufLen, uint16_t actLen,
DiegoOstuni	0:75fc82583a41	2662	SPI* mspiChannel, ST25R3911* mST25, DigitalOut* gpio_cs, InterruptIn* IRQ, DigitalOut* fieldLED_01, DigitalOut* fieldLED_02, DigitalOut* fieldLED_03, DigitalOut* fieldLED_04, DigitalOut* fieldLED_05, DigitalOut* fieldLED_06 )
DiegoOstuni	0:75fc82583a41	2663	{
DiegoOstuni	0:75fc82583a41	2664	ReturnCode ret;
DiegoOstuni	0:75fc82583a41	2665	uint8_t dummy;
DiegoOstuni	0:75fc82583a41	2666
DiegoOstuni	0:75fc82583a41	2667	/* Check if RFAL is properly initialized */
DiegoOstuni	0:75fc82583a41	2668	if( ( gRFAL.state < RFAL_STATE_MODE_SET ) \|\| ( gRFAL.mode != RFAL_MODE_POLL_NFCV ) )
DiegoOstuni	0:75fc82583a41	2669	{
DiegoOstuni	0:75fc82583a41	2670	return ERR_WRONG_STATE;
DiegoOstuni	0:75fc82583a41	2671	}
DiegoOstuni	0:75fc82583a41	2672
DiegoOstuni	0:75fc82583a41	2673	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	2674	/* Run Transceive blocking */
DiegoOstuni	0:75fc82583a41	2675	ret = rfalTransceiveBlockingTxRx( &dummy,
DiegoOstuni	0:75fc82583a41	2676	0,
DiegoOstuni	0:75fc82583a41	2677	rxBuf,
DiegoOstuni	0:75fc82583a41	2678	rxBufLen,
DiegoOstuni	0:75fc82583a41	2679	actLen,
DiegoOstuni	0:75fc82583a41	2680	( RFAL_TXRX_FLAGS_CRC_TX_MANUAL \| RFAL_TXRX_FLAGS_CRC_RX_KEEP \| RFAL_TXRX_FLAGS_AGC_ON ),
DiegoOstuni	0:75fc82583a41	2681	rfalConv64fcTo1fc(ISO15693_NO_RESPONSE_TIME), mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	2682	return ret;
DiegoOstuni	0:75fc82583a41	2683	}
DiegoOstuni	0:75fc82583a41	2684
DiegoOstuni	0:75fc82583a41	2685	#endif /* RFAL_FEATURE_NFCV */
DiegoOstuni	0:75fc82583a41	2686
DiegoOstuni	0:75fc82583a41	2687	#if RFAL_FEATURE_NFCF
DiegoOstuni	0:75fc82583a41	2688
DiegoOstuni	0:75fc82583a41	2689	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	2690	ReturnCode rfalFeliCaPoll( rfalFeliCaPollSlots slots, uint16_t sysCode, uint8_t reqCode, rfalFeliCaPollRes* pollResList, uint8_t pollResListSize, uint8_t *devicesDetected,
DiegoOstuni	0:75fc82583a41	2691	uint8_t collisionsDetected, SPI mspiChannel, ST25R3911* mST25,
DiegoOstuni	0:75fc82583a41	2692	DigitalOut* gpio_cs, InterruptIn* IRQ, DigitalOut* fieldLED_01, DigitalOut* fieldLED_02, DigitalOut* fieldLED_03, DigitalOut* fieldLED_04, DigitalOut* fieldLED_05, DigitalOut* fieldLED_06 )
DiegoOstuni	0:75fc82583a41	2693	{
DiegoOstuni	0:75fc82583a41	2694	ReturnCode ret;
DiegoOstuni	0:75fc82583a41	2695	uint8_t frame[RFAL_FELICA_POLL_REQ_LEN - RFAL_FELICA_LEN_LEN]; /* LEN is added by ST25R3911 automatically */
DiegoOstuni	0:75fc82583a41	2696	uint16_t actLen;
DiegoOstuni	0:75fc82583a41	2697	uint8_t frameIdx;
DiegoOstuni	0:75fc82583a41	2698	uint8_t devDetected;
DiegoOstuni	0:75fc82583a41	2699	uint8_t colDetected;
DiegoOstuni	0:75fc82583a41	2700	rfalEHandling curHandling;
DiegoOstuni	0:75fc82583a41	2701
DiegoOstuni	0:75fc82583a41	2702	int index = (int)slots;
DiegoOstuni	0:75fc82583a41	2703
DiegoOstuni	0:75fc82583a41	2704	/* Check if RFAL is properly initialized */
DiegoOstuni	0:75fc82583a41	2705	if( (gRFAL.state < RFAL_STATE_MODE_SET) \|\| ( gRFAL.mode != RFAL_MODE_POLL_NFCF ) )
DiegoOstuni	0:75fc82583a41	2706	{
DiegoOstuni	0:75fc82583a41	2707	return ERR_WRONG_STATE;
DiegoOstuni	0:75fc82583a41	2708	}
DiegoOstuni	0:75fc82583a41	2709
DiegoOstuni	0:75fc82583a41	2710	frameIdx = 0;
DiegoOstuni	0:75fc82583a41	2711	colDetected = 0;
DiegoOstuni	0:75fc82583a41	2712	devDetected = 0;
DiegoOstuni	0:75fc82583a41	2713
DiegoOstuni	0:75fc82583a41	2714	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	2715	/* Compute SENSF_REQ frame */
DiegoOstuni	0:75fc82583a41	2716	frame[frameIdx++] = FELICA_CMD_POLLING; /* CMD: SENF_REQ */
DiegoOstuni	0:75fc82583a41	2717	frame[frameIdx++] = (uint8_t)(sysCode >> 8); /* System Code (SC) */
DiegoOstuni	0:75fc82583a41	2718	frame[frameIdx++] = (uint8_t)(sysCode & 0xFF); /* System Code (SC) */
DiegoOstuni	0:75fc82583a41	2719	frame[frameIdx++] = reqCode; /* Communication Parameter Request (RC)*/
DiegoOstuni	0:75fc82583a41	2720	frame[frameIdx++] = (uint8_t)slots; /* TimeSlot (TSN) */
DiegoOstuni	0:75fc82583a41	2721
DiegoOstuni	0:75fc82583a41	2722
DiegoOstuni	0:75fc82583a41	2723	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	2724	/* NRT should not stop on reception - Use EMVCo mode to run NRT in nrt_emv *
DiegoOstuni	0:75fc82583a41	2725	* ERRORHANDLING_EMVCO has no special handling for NFC-F mode */
DiegoOstuni	0:75fc82583a41	2726	curHandling = gRFAL.conf.eHandling;
DiegoOstuni	0:75fc82583a41	2727	rfalSetErrorHandling( RFAL_ERRORHANDLING_EMVCO );
DiegoOstuni	0:75fc82583a41	2728
DiegoOstuni	0:75fc82583a41	2729	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	2730	/* Run transceive blocking,
DiegoOstuni	0:75fc82583a41	2731	* Calculate Total Response Time in(64/fc):
DiegoOstuni	0:75fc82583a41	2732	* 512 PICC process time + (n * 256 Time Slot duration) */
DiegoOstuni	0:75fc82583a41	2733	ret = rfalTransceiveBlockingTx( frame,
DiegoOstuni	0:75fc82583a41	2734	frameIdx,
DiegoOstuni	0:75fc82583a41	2735	(uint8_t*)gRFAL.nfcfData.pollResponses,
DiegoOstuni	0:75fc82583a41	2736	RFAL_FELICA_POLL_RES_LEN,
DiegoOstuni	0:75fc82583a41	2737	&actLen,
DiegoOstuni	0:75fc82583a41	2738	(RFAL_TXRX_FLAGS_DEFAULT),
DiegoOstuni	0:75fc82583a41	2739	rfalConv64fcTo1fc( RFAL_FELICA_POLL_DELAY_TIME + (RFAL_FELICA_POLL_SLOT_TIME * (slots + 1)) ),
DiegoOstuni	0:75fc82583a41	2740	mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	2741
DiegoOstuni	0:75fc82583a41	2742
DiegoOstuni	0:75fc82583a41	2743	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	2744	/* If Tx OK, Wait for all responses, store them as soon as they appear */
DiegoOstuni	0:75fc82583a41	2745	if( ret == ERR_NONE )
DiegoOstuni	0:75fc82583a41	2746	{
DiegoOstuni	0:75fc82583a41	2747	do
DiegoOstuni	0:75fc82583a41	2748	{
DiegoOstuni	0:75fc82583a41	2749	ret = rfalTransceiveBlockingRx( mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	2750	if( ret == ERR_TIMEOUT )
DiegoOstuni	0:75fc82583a41	2751	{
DiegoOstuni	0:75fc82583a41	2752	/* Upon timeout the full Poll Delay + (Slot time)(slots) has expired /
DiegoOstuni	0:75fc82583a41	2753	break;
DiegoOstuni	0:75fc82583a41	2754	}
DiegoOstuni	0:75fc82583a41	2755	else
DiegoOstuni	0:75fc82583a41	2756	{
DiegoOstuni	0:75fc82583a41	2757	/* Reception done, reEnabled Rx for following Slot */
DiegoOstuni	0:75fc82583a41	2758	mST25 -> executeCommand( ST25R3911_CMD_UNMASK_RECEIVE_DATA, mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	2759	mST25 -> executeCommand( ST25R3911_CMD_CLEAR_SQUELCH, mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	2760
DiegoOstuni	0:75fc82583a41	2761	/* If the reception was OK, new device found */
DiegoOstuni	0:75fc82583a41	2762	if( ret == ERR_NONE )
DiegoOstuni	0:75fc82583a41	2763	{
DiegoOstuni	0:75fc82583a41	2764	devDetected++;
DiegoOstuni	0:75fc82583a41	2765
DiegoOstuni	0:75fc82583a41	2766	/* Overwrite the Transceive context for the next reception */
DiegoOstuni	0:75fc82583a41	2767	gRFAL.TxRx.ctx.rxBuf = (uint8_t*)gRFAL.nfcfData.pollResponses[devDetected];
DiegoOstuni	0:75fc82583a41	2768	}
DiegoOstuni	0:75fc82583a41	2769	/* If the reception was not OK, mark as collision */
DiegoOstuni	0:75fc82583a41	2770	else
DiegoOstuni	0:75fc82583a41	2771	{
DiegoOstuni	0:75fc82583a41	2772	colDetected++;
DiegoOstuni	0:75fc82583a41	2773	}
DiegoOstuni	0:75fc82583a41	2774
DiegoOstuni	0:75fc82583a41	2775	/* Check whether NRT has expired meanwhile */
DiegoOstuni	0:75fc82583a41	2776	if( st25r3911CheckReg( ST25R3911_REG_REGULATOR_RESULT, ST25R3911_REG_REGULATOR_RESULT_nrt_on, 0x00, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) )
DiegoOstuni	0:75fc82583a41	2777	{
DiegoOstuni	0:75fc82583a41	2778	break;
DiegoOstuni	0:75fc82583a41	2779	}
DiegoOstuni	0:75fc82583a41	2780	}
DiegoOstuni	0:75fc82583a41	2781
DiegoOstuni	0:75fc82583a41	2782	/* Jump again into transceive Rx state for the following reception */
DiegoOstuni	0:75fc82583a41	2783	gRFAL.TxRx.status = ERR_BUSY;
DiegoOstuni	0:75fc82583a41	2784	gRFAL.state = RFAL_STATE_TXRX;
DiegoOstuni	0:75fc82583a41	2785	gRFAL.TxRx.state = RFAL_TXRX_STATE_RX_IDLE;
DiegoOstuni	0:75fc82583a41	2786
DiegoOstuni	0:75fc82583a41	2787	}while(index--);
DiegoOstuni	0:75fc82583a41	2788	}
DiegoOstuni	0:75fc82583a41	2789
DiegoOstuni	0:75fc82583a41	2790	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	2791	/* Restore NRT to normal mode - back to previous error handling */
DiegoOstuni	0:75fc82583a41	2792	rfalSetErrorHandling( curHandling );
DiegoOstuni	0:75fc82583a41	2793
DiegoOstuni	0:75fc82583a41	2794	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	2795	/* Assign output parameters if requested */
DiegoOstuni	0:75fc82583a41	2796
DiegoOstuni	0:75fc82583a41	2797	if( (pollResList != NULL) && (pollResListSize > 0) && (devDetected > 0) )
DiegoOstuni	0:75fc82583a41	2798	{
DiegoOstuni	0:75fc82583a41	2799	ST_MEMCPY( pollResList, gRFAL.nfcfData.pollResponses, (RFAL_FELICA_POLL_RES_LEN * MIN(pollResListSize, devDetected) ) );
DiegoOstuni	0:75fc82583a41	2800	}
DiegoOstuni	0:75fc82583a41	2801
DiegoOstuni	0:75fc82583a41	2802	if( devicesDetected != NULL )
DiegoOstuni	0:75fc82583a41	2803	{
DiegoOstuni	0:75fc82583a41	2804	*devicesDetected = devDetected;
DiegoOstuni	0:75fc82583a41	2805	}
DiegoOstuni	0:75fc82583a41	2806
DiegoOstuni	0:75fc82583a41	2807	if( collisionsDetected != NULL )
DiegoOstuni	0:75fc82583a41	2808	{
DiegoOstuni	0:75fc82583a41	2809	*collisionsDetected = colDetected;
DiegoOstuni	0:75fc82583a41	2810	}
DiegoOstuni	0:75fc82583a41	2811	uint16_t ERR_NONEUI = ERR_NONE;
DiegoOstuni	0:75fc82583a41	2812	return (( colDetected \|\| devDetected ) ? ERR_NONEUI : ret);
DiegoOstuni	0:75fc82583a41	2813	}
DiegoOstuni	0:75fc82583a41	2814
DiegoOstuni	0:75fc82583a41	2815	#endif /* RFAL_FEATURE_NFCF */
DiegoOstuni	0:75fc82583a41	2816
DiegoOstuni	0:75fc82583a41	2817
DiegoOstuni	0:75fc82583a41	2818	/*****************************************************************************
DiegoOstuni	0:75fc82583a41	2819	* Listen Mode *
DiegoOstuni	0:75fc82583a41	2820	*****************************************************************************/
DiegoOstuni	0:75fc82583a41	2821
DiegoOstuni	0:75fc82583a41	2822
DiegoOstuni	0:75fc82583a41	2823
DiegoOstuni	0:75fc82583a41	2824	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	2825	bool rfalIsExtFieldOn( SPI* mspiChannel, ST25R3911* mST25, DigitalOut* gpio_cs, InterruptIn* IRQ, DigitalOut* fieldLED_01, DigitalOut* fieldLED_02, DigitalOut* fieldLED_03, DigitalOut* fieldLED_04, DigitalOut* fieldLED_05, DigitalOut* fieldLED_06 )
DiegoOstuni	0:75fc82583a41	2826	{
DiegoOstuni	0:75fc82583a41	2827	return st25r3911CheckReg(ST25R3911_REG_AUX_DISPLAY, ST25R3911_REG_AUX_DISPLAY_efd_o, ST25R3911_REG_AUX_DISPLAY_efd_o, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	2828	}
DiegoOstuni	0:75fc82583a41	2829
DiegoOstuni	0:75fc82583a41	2830
DiegoOstuni	0:75fc82583a41	2831	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	2832	ReturnCode rfalListenStart( uint32_t lmMask, rfalLmConfPA confA, rfalLmConfPB confB,
DiegoOstuni	0:75fc82583a41	2833	rfalLmConfPF confF, uint8_t rxBuf, uint16_t rxBufLen, uint16_t *rxLen,
DiegoOstuni	0:75fc82583a41	2834	SPI* mspiChannel, ST25R3911* mST25, DigitalOut* gpio_cs, InterruptIn* IRQ, DigitalOut* fieldLED_01, DigitalOut* fieldLED_02, DigitalOut* fieldLED_03, DigitalOut* fieldLED_04, DigitalOut* fieldLED_05, DigitalOut* fieldLED_06 )
DiegoOstuni	0:75fc82583a41	2835	{
DiegoOstuni	0:75fc82583a41	2836	NO_WARNING(confA);
DiegoOstuni	0:75fc82583a41	2837	NO_WARNING(confB);
DiegoOstuni	0:75fc82583a41	2838	NO_WARNING(confF);
DiegoOstuni	0:75fc82583a41	2839
DiegoOstuni	0:75fc82583a41	2840
DiegoOstuni	0:75fc82583a41	2841	gRFAL.Lm.state = RFAL_LM_STATE_NOT_INIT;
DiegoOstuni	0:75fc82583a41	2842
DiegoOstuni	0:75fc82583a41	2843
DiegoOstuni	0:75fc82583a41	2844	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	2845	if( (lmMask & RFAL_LM_MASK_NFCA) \|\| (lmMask & RFAL_LM_MASK_NFCB) \|\| (lmMask & RFAL_LM_MASK_NFCF) )
DiegoOstuni	0:75fc82583a41	2846	{
DiegoOstuni	0:75fc82583a41	2847	return ERR_NOTSUPP;
DiegoOstuni	0:75fc82583a41	2848	}
DiegoOstuni	0:75fc82583a41	2849
DiegoOstuni	0:75fc82583a41	2850
DiegoOstuni	0:75fc82583a41	2851
DiegoOstuni	0:75fc82583a41	2852	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	2853	if( (lmMask & RFAL_LM_MASK_ACTIVE_P2P) )
DiegoOstuni	0:75fc82583a41	2854	{
DiegoOstuni	0:75fc82583a41	2855	gRFAL.state = RFAL_STATE_LM;
DiegoOstuni	0:75fc82583a41	2856
DiegoOstuni	0:75fc82583a41	2857	gRFAL.Lm.rxBuf = rxBuf;
DiegoOstuni	0:75fc82583a41	2858	gRFAL.Lm.rxBufLen = rxBufLen;
DiegoOstuni	0:75fc82583a41	2859	gRFAL.Lm.rxLen = rxLen;
DiegoOstuni	0:75fc82583a41	2860	*gRFAL.Lm.rxLen = 0;
DiegoOstuni	0:75fc82583a41	2861	gRFAL.Lm.dataFlag = false;
DiegoOstuni	0:75fc82583a41	2862
DiegoOstuni	0:75fc82583a41	2863	/* On Bit Rate Detection Mode ST25R391x will filter incoming frames during MRT time starting on External Field On event, use 512/fc steps */
DiegoOstuni	0:75fc82583a41	2864	mST25 -> writeRegister( ST25R3911_REG_MASK_RX_TIMER, rfalConv1fcTo512fc( RFAL_LM_GT ), mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	2865
DiegoOstuni	0:75fc82583a41	2866	/* Restore default settings on NFCIP1 mode, Receiving parity + CRC bits and manual Tx Parity*/
DiegoOstuni	0:75fc82583a41	2867	st25r3911ClrRegisterBits( ST25R3911_REG_ISO14443A_NFC,
DiegoOstuni	0:75fc82583a41	2868	(ST25R3911_REG_ISO14443A_NFC_no_tx_par \| ST25R3911_REG_ISO14443A_NFC_no_rx_par \| ST25R3911_REG_ISO14443A_NFC_nfc_f0),
DiegoOstuni	0:75fc82583a41	2869	mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	2870
DiegoOstuni	0:75fc82583a41	2871	/* Enable External Field Detector */
DiegoOstuni	0:75fc82583a41	2872	st25r3911SetRegisterBits( ST25R3911_REG_AUX, ST25R3911_REG_AUX_en_fd, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	2873
DiegoOstuni	0:75fc82583a41	2874	/* Enable Receiver */
DiegoOstuni	0:75fc82583a41	2875	st25r3911ChangeRegisterBits( ST25R3911_REG_OP_CONTROL, ST25R3911_REG_OP_CONTROL_rx_en, ST25R3911_REG_OP_CONTROL_rx_en,
DiegoOstuni	0:75fc82583a41	2876	mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	2877
DiegoOstuni	0:75fc82583a41	2878	/* Set Analog configurations for generic Listen mode */
DiegoOstuni	0:75fc82583a41	2879	/* Not on SetState(POWER OFF) as otherwise would be applied on every Field Event */
DiegoOstuni	0:75fc82583a41	2880	rfalSetAnalogConfig( (RFAL_ANALOG_CONFIG_LISTEN \| RFAL_ANALOG_CONFIG_TECH_AP2P \| RFAL_ANALOG_CONFIG_BITRATE_COMMON \| RFAL_ANALOG_CONFIG_TX), mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	2881	rfalSetAnalogConfig( (RFAL_ANALOG_CONFIG_LISTEN \| RFAL_ANALOG_CONFIG_TECH_AP2P \| RFAL_ANALOG_CONFIG_BITRATE_COMMON \| RFAL_ANALOG_CONFIG_RX), mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	2882
DiegoOstuni	0:75fc82583a41	2883	/* Initialize as POWER_OFF and set proper mode in RF Chip */
DiegoOstuni	0:75fc82583a41	2884	rfalListenSetState( RFAL_LM_STATE_POWER_OFF, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	2885	}
DiegoOstuni	0:75fc82583a41	2886	else
DiegoOstuni	0:75fc82583a41	2887	{
DiegoOstuni	0:75fc82583a41	2888	return ERR_REQUEST; /* Listen Start called but no mode was enabled */
DiegoOstuni	0:75fc82583a41	2889	}
DiegoOstuni	0:75fc82583a41	2890
DiegoOstuni	0:75fc82583a41	2891	return ERR_NONE;
DiegoOstuni	0:75fc82583a41	2892	}
DiegoOstuni	0:75fc82583a41	2893
DiegoOstuni	0:75fc82583a41	2894
DiegoOstuni	0:75fc82583a41	2895
DiegoOstuni	0:75fc82583a41	2896	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	2897	static ReturnCode rfalRunListenModeWorker( SPI* mspiChannel, ST25R3911* mST25, DigitalOut* gpio_cs, InterruptIn* IRQ, DigitalOut* fieldLED_01, DigitalOut* fieldLED_02, DigitalOut* fieldLED_03, DigitalOut* fieldLED_04, DigitalOut* fieldLED_05, DigitalOut* fieldLED_06 )
DiegoOstuni	0:75fc82583a41	2898	{
DiegoOstuni	0:75fc82583a41	2899	volatile uint32_t irqs;
DiegoOstuni	0:75fc82583a41	2900	uint8_t tmp;
DiegoOstuni	0:75fc82583a41	2901
DiegoOstuni	0:75fc82583a41	2902	if( gRFAL.state != RFAL_STATE_LM )
DiegoOstuni	0:75fc82583a41	2903	{
DiegoOstuni	0:75fc82583a41	2904	return ERR_WRONG_STATE;
DiegoOstuni	0:75fc82583a41	2905	}
DiegoOstuni	0:75fc82583a41	2906
DiegoOstuni	0:75fc82583a41	2907	switch( gRFAL.Lm.state )
DiegoOstuni	0:75fc82583a41	2908	{
DiegoOstuni	0:75fc82583a41	2909	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	2910	case RFAL_LM_STATE_POWER_OFF:
DiegoOstuni	0:75fc82583a41	2911
DiegoOstuni	0:75fc82583a41	2912	irqs = st25r3911GetInterrupt( ( ST25R3911_IRQ_MASK_EON ), mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	2913	if( irqs == ST25R3911_IRQ_MASK_NONE )
DiegoOstuni	0:75fc82583a41	2914	{
DiegoOstuni	0:75fc82583a41	2915	break; /* No interrupt to process */
DiegoOstuni	0:75fc82583a41	2916	}
DiegoOstuni	0:75fc82583a41	2917
DiegoOstuni	0:75fc82583a41	2918	if( (irqs & ST25R3911_IRQ_MASK_EON) )
DiegoOstuni	0:75fc82583a41	2919	{
DiegoOstuni	0:75fc82583a41	2920	rfalListenSetState( RFAL_LM_STATE_IDLE, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	2921	}
DiegoOstuni	0:75fc82583a41	2922	else
DiegoOstuni	0:75fc82583a41	2923	{
DiegoOstuni	0:75fc82583a41	2924	break;
DiegoOstuni	0:75fc82583a41	2925	}
DiegoOstuni	0:75fc82583a41	2926	/* fall through */
DiegoOstuni	0:75fc82583a41	2927
DiegoOstuni	0:75fc82583a41	2928
DiegoOstuni	0:75fc82583a41	2929	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	2930	case RFAL_LM_STATE_IDLE:
DiegoOstuni	0:75fc82583a41	2931
DiegoOstuni	0:75fc82583a41	2932	irqs = st25r3911GetInterrupt( ( ST25R3911_IRQ_MASK_NFCT \| ST25R3911_IRQ_MASK_RXE \| ST25R3911_IRQ_MASK_EOF ), mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	2933	if( irqs == ST25R3911_IRQ_MASK_NONE )
DiegoOstuni	0:75fc82583a41	2934	{
DiegoOstuni	0:75fc82583a41	2935	break; /* No interrupt to process */
DiegoOstuni	0:75fc82583a41	2936	}
DiegoOstuni	0:75fc82583a41	2937
DiegoOstuni	0:75fc82583a41	2938	if( (irqs & ST25R3911_IRQ_MASK_NFCT) )
DiegoOstuni	0:75fc82583a41	2939	{
DiegoOstuni	0:75fc82583a41	2940	/* Retrieve bitrate detected */
DiegoOstuni	0:75fc82583a41	2941	mST25 -> readRegister( ST25R3911_REG_NFCIP1_BIT_RATE, (uint8_t*)&gRFAL.Lm.brDetected, mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	2942	// rfalBitRate test = RFAL_BR_1695;
DiegoOstuni	0:75fc82583a41	2943	gRFAL.Lm.brDetected = (rfalBitRate)((int)gRFAL.Lm.brDetected >> ST25R3911_REG_NFCIP1_BIT_RATE_nfc_rate_shift);
DiegoOstuni	0:75fc82583a41	2944	//(rfalBitRate) ST25R3911_REG_NFCIP1_BIT_RATE_nfc_rate_shift;
DiegoOstuni	0:75fc82583a41	2945	}
DiegoOstuni	0:75fc82583a41	2946	else if( (irqs & ST25R3911_IRQ_MASK_RXE) && (gRFAL.Lm.brDetected != RFAL_BR_KEEP) )
DiegoOstuni	0:75fc82583a41	2947	{
DiegoOstuni	0:75fc82583a41	2948	irqs = st25r3911GetInterrupt( ( ST25R3911_IRQ_MASK_RXE \| ST25R3911_IRQ_MASK_EOF \| ST25R3911_IRQ_MASK_CRC \| ST25R3911_IRQ_MASK_PAR \| ST25R3911_IRQ_MASK_ERR2 \| ST25R3911_IRQ_MASK_ERR1 ), mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	2949
DiegoOstuni	0:75fc82583a41	2950	if( (irqs & ST25R3911_IRQ_MASK_CRC) \|\| (irqs & ST25R3911_IRQ_MASK_PAR) \|\| (irqs & ST25R3911_IRQ_MASK_ERR1) )
DiegoOstuni	0:75fc82583a41	2951	{
DiegoOstuni	0:75fc82583a41	2952	/* nfc_ar may have triggered RF Collision Avoidance, disable it before executing Clear (Stop All activities) */
DiegoOstuni	0:75fc82583a41	2953	st25r3911ClrRegisterBits( ST25R3911_REG_MODE, ST25R3911_REG_MODE_nfc_ar, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	2954	mST25 -> executeCommand( ST25R3911_CMD_CLEAR_FIFO, mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	2955	mST25 -> executeCommand( ST25R3911_CMD_UNMASK_RECEIVE_DATA, mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	2956	st25r3911SetRegisterBits( ST25R3911_REG_MODE, ST25R3911_REG_MODE_nfc_ar, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	2957	st25r3911ClrRegisterBits(ST25R3911_REG_OP_CONTROL, ST25R3911_REG_OP_CONTROL_tx_en, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	2958	break; /* A bad reception occurred, remain in same state */
DiegoOstuni	0:75fc82583a41	2959	}
DiegoOstuni	0:75fc82583a41	2960
DiegoOstuni	0:75fc82583a41	2961	/* Retrieve received data */
DiegoOstuni	0:75fc82583a41	2962	mST25 -> readRegister(ST25R3911_REG_FIFO_RX_STATUS1, &tmp, mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	2963	*gRFAL.Lm.rxLen = tmp;
DiegoOstuni	0:75fc82583a41	2964
DiegoOstuni	0:75fc82583a41	2965	mST25 -> readFifo( gRFAL.Lm.rxBuf, MIN( *gRFAL.Lm.rxLen, rfalConvBitsToBytes(gRFAL.Lm.rxBufLen) ), mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	2966
DiegoOstuni	0:75fc82583a41	2967	/* Check if the data we got has at least the CRC and remove it, otherwise leave at 0 */
DiegoOstuni	0:75fc82583a41	2968	gRFAL.Lm.rxLen -= ((gRFAL.Lm.rxLen > RFAL_CRC_LEN) ? RFAL_CRC_LEN : *gRFAL.Lm.rxLen);
DiegoOstuni	0:75fc82583a41	2969	gRFAL.Lm.rxLen = rfalConvBytesToBits( gRFAL.Lm.rxLen );
DiegoOstuni	0:75fc82583a41	2970	gRFAL.Lm.dataFlag = true;
DiegoOstuni	0:75fc82583a41	2971
DiegoOstuni	0:75fc82583a41	2972	/Check if Observation Mode was enabled and disable it on ST25R391x /
DiegoOstuni	0:75fc82583a41	2973	rfalCheckDisableObsMode();
DiegoOstuni	0:75fc82583a41	2974	}
DiegoOstuni	0:75fc82583a41	2975	else if( (irqs & ST25R3911_IRQ_MASK_EOF) && (!gRFAL.Lm.dataFlag) )
DiegoOstuni	0:75fc82583a41	2976	{
DiegoOstuni	0:75fc82583a41	2977	rfalListenSetState( RFAL_LM_STATE_POWER_OFF, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	2978	}
DiegoOstuni	0:75fc82583a41	2979	break;
DiegoOstuni	0:75fc82583a41	2980
DiegoOstuni	0:75fc82583a41	2981	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	2982	case RFAL_LM_STATE_READY_F:
DiegoOstuni	0:75fc82583a41	2983	case RFAL_LM_STATE_READY_A:
DiegoOstuni	0:75fc82583a41	2984	case RFAL_LM_STATE_ACTIVE_A:
DiegoOstuni	0:75fc82583a41	2985	case RFAL_LM_STATE_ACTIVE_Ax:
DiegoOstuni	0:75fc82583a41	2986	case RFAL_LM_STATE_SLEEP_A:
DiegoOstuni	0:75fc82583a41	2987	case RFAL_LM_STATE_SLEEP_B:
DiegoOstuni	0:75fc82583a41	2988	case RFAL_LM_STATE_SLEEP_AF:
DiegoOstuni	0:75fc82583a41	2989	case RFAL_LM_STATE_READY_Ax:
DiegoOstuni	0:75fc82583a41	2990	case RFAL_LM_STATE_CARDEMU_4A:
DiegoOstuni	0:75fc82583a41	2991	case RFAL_LM_STATE_CARDEMU_4B:
DiegoOstuni	0:75fc82583a41	2992	case RFAL_LM_STATE_CARDEMU_3:
DiegoOstuni	0:75fc82583a41	2993	return ERR_INTERNAL;
DiegoOstuni	0:75fc82583a41	2994
DiegoOstuni	0:75fc82583a41	2995	case RFAL_LM_STATE_TARGET_F:
DiegoOstuni	0:75fc82583a41	2996	case RFAL_LM_STATE_TARGET_A:
DiegoOstuni	0:75fc82583a41	2997	break;
DiegoOstuni	0:75fc82583a41	2998
DiegoOstuni	0:75fc82583a41	2999	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	3000	default:
DiegoOstuni	0:75fc82583a41	3001	return ERR_WRONG_STATE;
DiegoOstuni	0:75fc82583a41	3002	}
DiegoOstuni	0:75fc82583a41	3003	return ERR_NONE;
DiegoOstuni	0:75fc82583a41	3004	}
DiegoOstuni	0:75fc82583a41	3005
DiegoOstuni	0:75fc82583a41	3006
DiegoOstuni	0:75fc82583a41	3007	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	3008	ReturnCode rfalListenStop( SPI* mspiChannel, ST25R3911* mST25, DigitalOut* gpio_cs, InterruptIn* IRQ, DigitalOut* fieldLED_01, DigitalOut* fieldLED_02, DigitalOut* fieldLED_03, DigitalOut* fieldLED_04, DigitalOut* fieldLED_05, DigitalOut* fieldLED_06 )
DiegoOstuni	0:75fc82583a41	3009	{
DiegoOstuni	0:75fc82583a41	3010	gRFAL.Lm.state = RFAL_LM_STATE_NOT_INIT;
DiegoOstuni	0:75fc82583a41	3011
DiegoOstuni	0:75fc82583a41	3012	/Check if Observation Mode was enabled and disable it on ST25R391x /
DiegoOstuni	0:75fc82583a41	3013	rfalCheckDisableObsMode();
DiegoOstuni	0:75fc82583a41	3014
DiegoOstuni	0:75fc82583a41	3015	/* Disable Receiver and Transmitter */
DiegoOstuni	0:75fc82583a41	3016	rfalFieldOff( mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	3017
DiegoOstuni	0:75fc82583a41	3018	/* As there's no Off mode, set default value: ISO14443A with automatic RF Collision Avoidance Off */
DiegoOstuni	0:75fc82583a41	3019	mST25 -> writeRegister( ST25R3911_REG_MODE, (ST25R3911_REG_MODE_om_iso14443a \| ST25R3911_REG_MODE_nfc_ar_off), mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	3020
DiegoOstuni	0:75fc82583a41	3021	return ERR_NONE;
DiegoOstuni	0:75fc82583a41	3022	}
DiegoOstuni	0:75fc82583a41	3023
DiegoOstuni	0:75fc82583a41	3024
DiegoOstuni	0:75fc82583a41	3025	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	3026	ReturnCode rfalListenSleepStart( rfalLmState sleepSt, uint8_t rxBuf, uint16_t rxBufLen, uint16_t rxLen )
DiegoOstuni	0:75fc82583a41	3027	{
DiegoOstuni	0:75fc82583a41	3028	NO_WARNING(sleepSt);
DiegoOstuni	0:75fc82583a41	3029	NO_WARNING(rxBuf);
DiegoOstuni	0:75fc82583a41	3030	NO_WARNING(rxBufLen);
DiegoOstuni	0:75fc82583a41	3031	NO_WARNING(rxLen);
DiegoOstuni	0:75fc82583a41	3032
DiegoOstuni	0:75fc82583a41	3033	return ERR_NOTSUPP;
DiegoOstuni	0:75fc82583a41	3034	}
DiegoOstuni	0:75fc82583a41	3035
DiegoOstuni	0:75fc82583a41	3036
DiegoOstuni	0:75fc82583a41	3037	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	3038	rfalLmState rfalListenGetState( bool dataFlag, rfalBitRate lastBR )
DiegoOstuni	0:75fc82583a41	3039	{
DiegoOstuni	0:75fc82583a41	3040	/* Allow state retrieval even if gRFAL.state != RFAL_STATE_LM so *
DiegoOstuni	0:75fc82583a41	3041	* that this Lm state can be used by caller after activation */
DiegoOstuni	0:75fc82583a41	3042
DiegoOstuni	0:75fc82583a41	3043	if( lastBR != NULL )
DiegoOstuni	0:75fc82583a41	3044	{
DiegoOstuni	0:75fc82583a41	3045	*lastBR = gRFAL.Lm.brDetected;
DiegoOstuni	0:75fc82583a41	3046	}
DiegoOstuni	0:75fc82583a41	3047
DiegoOstuni	0:75fc82583a41	3048	if( dataFlag != NULL )
DiegoOstuni	0:75fc82583a41	3049	{
DiegoOstuni	0:75fc82583a41	3050	*dataFlag = gRFAL.Lm.dataFlag;
DiegoOstuni	0:75fc82583a41	3051	}
DiegoOstuni	0:75fc82583a41	3052
DiegoOstuni	0:75fc82583a41	3053	return gRFAL.Lm.state;
DiegoOstuni	0:75fc82583a41	3054	}
DiegoOstuni	0:75fc82583a41	3055
DiegoOstuni	0:75fc82583a41	3056
DiegoOstuni	0:75fc82583a41	3057	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	3058	ReturnCode rfalListenSetState( rfalLmState newSt, SPI* mspiChannel, ST25R3911* mST25, DigitalOut* gpio_cs, InterruptIn* IRQ, DigitalOut* fieldLED_01, DigitalOut* fieldLED_02, DigitalOut* fieldLED_03, DigitalOut* fieldLED_04, DigitalOut* fieldLED_05, DigitalOut* fieldLED_06 )
DiegoOstuni	0:75fc82583a41	3059	{
DiegoOstuni	0:75fc82583a41	3060	ReturnCode ret;
DiegoOstuni	0:75fc82583a41	3061	uint8_t tmp;
DiegoOstuni	0:75fc82583a41	3062
DiegoOstuni	0:75fc82583a41	3063	/rfalLogD( "RFAL: curState: %02X newState: %02X \r\n", gRFAL.Lm.state, newSt );/
DiegoOstuni	0:75fc82583a41	3064
DiegoOstuni	0:75fc82583a41	3065	/* SetState clears the Data flag */
DiegoOstuni	0:75fc82583a41	3066	gRFAL.Lm.dataFlag = false;
DiegoOstuni	0:75fc82583a41	3067	ret = ERR_NONE;
DiegoOstuni	0:75fc82583a41	3068
DiegoOstuni	0:75fc82583a41	3069	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	3070	switch( newSt )
DiegoOstuni	0:75fc82583a41	3071	{
DiegoOstuni	0:75fc82583a41	3072	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	3073	case RFAL_LM_STATE_POWER_OFF:
DiegoOstuni	0:75fc82583a41	3074
DiegoOstuni	0:75fc82583a41	3075	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	3076	/* Disable nfc_ar as RF Collision Avoidance timer may have already started */
DiegoOstuni	0:75fc82583a41	3077	st25r3911ClrRegisterBits( ST25R3911_REG_MODE, ST25R3911_REG_MODE_nfc_ar, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	3078
DiegoOstuni	0:75fc82583a41	3079	mST25 -> executeCommand( ST25R3911_CMD_CLEAR_FIFO, mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	3080
DiegoOstuni	0:75fc82583a41	3081	/* Ensure that our field is Off, as automatic response RF Collision Avoidance may have been triggered */
DiegoOstuni	0:75fc82583a41	3082	st25r3911ClrRegisterBits(ST25R3911_REG_OP_CONTROL, ST25R3911_REG_OP_CONTROL_tx_en, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	3083
DiegoOstuni	0:75fc82583a41	3084	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	3085	/* Ensure that the NFCIP1 mode is disabled */
DiegoOstuni	0:75fc82583a41	3086	st25r3911ClrRegisterBits( ST25R3911_REG_ISO14443A_NFC, ST25R3911_REG_ISO14443A_NFC_nfc_f0, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	3087
DiegoOstuni	0:75fc82583a41	3088
DiegoOstuni	0:75fc82583a41	3089	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	3090	/* Clear and enable required IRQs */
DiegoOstuni	0:75fc82583a41	3091	st25r3911DisableInterrupts( ST25R3911_IRQ_MASK_ALL, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 );
DiegoOstuni	0:75fc82583a41	3092
DiegoOstuni	0:75fc82583a41	3093
DiegoOstuni	0:75fc82583a41	3094	st25r3911GetInterrupt( (ST25R3911_IRQ_MASK_NFCT \| ST25R3911_IRQ_MASK_RXS \| ST25R3911_IRQ_MASK_CRC \| ST25R3911_IRQ_MASK_ERR1 \|
DiegoOstuni	0:75fc82583a41	3095	ST25R3911_IRQ_MASK_ERR2 \| ST25R3911_IRQ_MASK_PAR \| ST25R3911_IRQ_MASK_EON \| ST25R3911_IRQ_MASK_EOF \| ST25R3911_IRQ_MASK_RXE ), mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	3096
DiegoOstuni	0:75fc82583a41	3097
DiegoOstuni	0:75fc82583a41	3098	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	3099	/* REMARK: Silicon workaround ST25R3911 Errata TDB */
DiegoOstuni	0:75fc82583a41	3100	/* RXS and NFCT are triggered very close (specially in higher bitrates). *
DiegoOstuni	0:75fc82583a41	3101	* If the interrupt status register is being read when NFCT is trigerred, the *
DiegoOstuni	0:75fc82583a41	3102	* IRQ line might go low and NFCT is not signalled on the status register. *
DiegoOstuni	0:75fc82583a41	3103	* For initial bitrate detection, mask RXS, only wait for NFCT and RXE. */
DiegoOstuni	0:75fc82583a41	3104	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	3105
DiegoOstuni	0:75fc82583a41	3106	st25r3911EnableInterrupts( (ST25R3911_IRQ_MASK_NFCT \| ST25R3911_IRQ_MASK_CRC \| ST25R3911_IRQ_MASK_ERR1 \|
DiegoOstuni	0:75fc82583a41	3107	ST25R3911_IRQ_MASK_ERR2 \| ST25R3911_IRQ_MASK_PAR \| ST25R3911_IRQ_MASK_EON \| ST25R3911_IRQ_MASK_EOF \| ST25R3911_IRQ_MASK_RXE ),
DiegoOstuni	0:75fc82583a41	3108	mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	3109
DiegoOstuni	0:75fc82583a41	3110	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	3111	/* Clear the bitRate previously detected */
DiegoOstuni	0:75fc82583a41	3112	gRFAL.Lm.brDetected = RFAL_BR_KEEP;
DiegoOstuni	0:75fc82583a41	3113
DiegoOstuni	0:75fc82583a41	3114
DiegoOstuni	0:75fc82583a41	3115	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	3116	/* Apply the BitRate detection mode mode */
DiegoOstuni	0:75fc82583a41	3117	mST25 -> writeRegister( ST25R3911_REG_MODE,
DiegoOstuni	0:75fc82583a41	3118	(ST25R3911_REG_MODE_targ_targ \| ST25R3911_REG_MODE_om_bit_rate_detection \| ST25R3911_REG_MODE_nfc_ar_on),
DiegoOstuni	0:75fc82583a41	3119	mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	3120
DiegoOstuni	0:75fc82583a41	3121
DiegoOstuni	0:75fc82583a41	3122	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	3123	/* REMARK: Silicon workaround ST25R3911 Errata #1.3 */
DiegoOstuni	0:75fc82583a41	3124	/* Even though bitrate is going to be detected the bitrate must be set to *
DiegoOstuni	0:75fc82583a41	3125	* 106kbps to get correct 106kbps parity */
DiegoOstuni	0:75fc82583a41	3126	mST25 -> writeRegister( ST25R3911_REG_BIT_RATE, (ST25R3911_REG_BIT_RATE_txrate_106 \| ST25R3911_REG_BIT_RATE_rxrate_106),
DiegoOstuni	0:75fc82583a41	3127	mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	3128	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	3129
DiegoOstuni	0:75fc82583a41	3130
DiegoOstuni	0:75fc82583a41	3131	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	3132	/* Check if external Field is already On */
DiegoOstuni	0:75fc82583a41	3133	if( rfalIsExtFieldOn( mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) )
DiegoOstuni	0:75fc82583a41	3134	{
DiegoOstuni	0:75fc82583a41	3135	return rfalListenSetState( RFAL_LM_STATE_IDLE, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ; /* Set IDLE state */
DiegoOstuni	0:75fc82583a41	3136	}
DiegoOstuni	0:75fc82583a41	3137	break;
DiegoOstuni	0:75fc82583a41	3138
DiegoOstuni	0:75fc82583a41	3139	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	3140	case RFAL_LM_STATE_IDLE:
DiegoOstuni	0:75fc82583a41	3141
DiegoOstuni	0:75fc82583a41	3142	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	3143	/* In Active P2P the Initiator may: Turn its field On; LM goes into IDLE state;
DiegoOstuni	0:75fc82583a41	3144	* Initiator sends an unexpected frame raising a Protocol error; Initiator
DiegoOstuni	0:75fc82583a41	3145	* turns its field Off and ST25R3911 performs the automatic RF Collision
DiegoOstuni	0:75fc82583a41	3146	* Avoidance keeping our field On; upon a Protocol error upper layer sets
DiegoOstuni	0:75fc82583a41	3147	* again the state to IDLE to clear dataFlag and wait for next data.
DiegoOstuni	0:75fc82583a41	3148	*
DiegoOstuni	0:75fc82583a41	3149	* Ensure that when upper layer calls SetState(IDLE), it restores initial
DiegoOstuni	0:75fc82583a41	3150	* configuration and that check whether an external Field is still present */
DiegoOstuni	0:75fc82583a41	3151
DiegoOstuni	0:75fc82583a41	3152	/* nfc_ar may have triggered RF Collision Avoidance, disable it before executing Clear (Stop All activities) */
DiegoOstuni	0:75fc82583a41	3153	st25r3911ClrRegisterBits( ST25R3911_REG_MODE, ST25R3911_REG_MODE_nfc_ar, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	3154	mST25 -> executeCommand( ST25R3911_CMD_CLEAR_FIFO, mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	3155	st25r3911SetRegisterBits( ST25R3911_REG_MODE, ST25R3911_REG_MODE_nfc_ar, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	3156
DiegoOstuni	0:75fc82583a41	3157	/* Ensure that our field is Off, as automatic response RF Collision Avoidance may have been triggered */
DiegoOstuni	0:75fc82583a41	3158	st25r3911ClrRegisterBits(ST25R3911_REG_OP_CONTROL, ST25R3911_REG_OP_CONTROL_tx_en , mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	3159
DiegoOstuni	0:75fc82583a41	3160
DiegoOstuni	0:75fc82583a41	3161	/* Load 2nd/3rd stage gain setting from registers into the receiver */
DiegoOstuni	0:75fc82583a41	3162	mST25 -> executeCommand( ST25R3911_CMD_CLEAR_SQUELCH, mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	3163
DiegoOstuni	0:75fc82583a41	3164	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	3165	/* REMARK: Silicon workaround ST25R3911 Errata #1.4 */
DiegoOstuni	0:75fc82583a41	3166	/* Enable; disable; enable mixer to make sure the digital decoder is in *
DiegoOstuni	0:75fc82583a41	3167	* high state. This also switches the demodulator to mixer mode. */
DiegoOstuni	0:75fc82583a41	3168	mST25 -> readRegister( ST25R3911_REG_RX_CONF1, &tmp, mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	3169	mST25 -> writeRegister( ST25R3911_REG_RX_CONF1, (tmp \| ST25R3911_REG_RX_CONF1_amd_sel), mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	3170	mST25 -> writeRegister( ST25R3911_REG_RX_CONF1, (tmp & ~ST25R3911_REG_RX_CONF1_amd_sel), mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	3171	mST25 -> writeRegister( ST25R3911_REG_RX_CONF1, (tmp \| ST25R3911_REG_RX_CONF1_amd_sel), mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	3172	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	3173
DiegoOstuni	0:75fc82583a41	3174	/* ReEnable the receiver */
DiegoOstuni	0:75fc82583a41	3175	mST25 -> executeCommand( ST25R3911_CMD_UNMASK_RECEIVE_DATA, mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	3176
DiegoOstuni	0:75fc82583a41	3177
DiegoOstuni	0:75fc82583a41	3178	/* If external Field is no longer detected go back to POWER_OFF */
DiegoOstuni	0:75fc82583a41	3179	if( !st25r3911CheckReg(ST25R3911_REG_AUX_DISPLAY, ST25R3911_REG_AUX_DISPLAY_efd_o, ST25R3911_REG_AUX_DISPLAY_efd_o, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) )
DiegoOstuni	0:75fc82583a41	3180	{
DiegoOstuni	0:75fc82583a41	3181	return rfalListenSetState( RFAL_LM_STATE_POWER_OFF, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ; /* Set POWER_OFF state */
DiegoOstuni	0:75fc82583a41	3182	}
DiegoOstuni	0:75fc82583a41	3183
DiegoOstuni	0:75fc82583a41	3184	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	3185	/Check if Observation Mode is enabled and set it on ST25R391x /
DiegoOstuni	0:75fc82583a41	3186	rfalCheckEnableObsModeRx();
DiegoOstuni	0:75fc82583a41	3187	break;
DiegoOstuni	0:75fc82583a41	3188
DiegoOstuni	0:75fc82583a41	3189	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	3190	case RFAL_LM_STATE_TARGET_A:
DiegoOstuni	0:75fc82583a41	3191	case RFAL_LM_STATE_TARGET_F:
DiegoOstuni	0:75fc82583a41	3192	/* States not handled by the LM, just keep state context */
DiegoOstuni	0:75fc82583a41	3193	break;
DiegoOstuni	0:75fc82583a41	3194
DiegoOstuni	0:75fc82583a41	3195	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	3196	case RFAL_LM_STATE_READY_F:
DiegoOstuni	0:75fc82583a41	3197	case RFAL_LM_STATE_CARDEMU_3:
DiegoOstuni	0:75fc82583a41	3198	case RFAL_LM_STATE_READY_Ax:
DiegoOstuni	0:75fc82583a41	3199	case RFAL_LM_STATE_READY_A:
DiegoOstuni	0:75fc82583a41	3200	case RFAL_LM_STATE_ACTIVE_Ax:
DiegoOstuni	0:75fc82583a41	3201	case RFAL_LM_STATE_ACTIVE_A:
DiegoOstuni	0:75fc82583a41	3202	case RFAL_LM_STATE_SLEEP_A:
DiegoOstuni	0:75fc82583a41	3203	case RFAL_LM_STATE_SLEEP_B:
DiegoOstuni	0:75fc82583a41	3204	case RFAL_LM_STATE_SLEEP_AF:
DiegoOstuni	0:75fc82583a41	3205	case RFAL_LM_STATE_CARDEMU_4A:
DiegoOstuni	0:75fc82583a41	3206	case RFAL_LM_STATE_CARDEMU_4B:
DiegoOstuni	0:75fc82583a41	3207	return ERR_NOTSUPP;
DiegoOstuni	0:75fc82583a41	3208
DiegoOstuni	0:75fc82583a41	3209	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	3210	default:
DiegoOstuni	0:75fc82583a41	3211	return ERR_WRONG_STATE;
DiegoOstuni	0:75fc82583a41	3212	}
DiegoOstuni	0:75fc82583a41	3213
DiegoOstuni	0:75fc82583a41	3214	gRFAL.Lm.state = newSt;
DiegoOstuni	0:75fc82583a41	3215
DiegoOstuni	0:75fc82583a41	3216	return ret;
DiegoOstuni	0:75fc82583a41	3217	}
DiegoOstuni	0:75fc82583a41	3218
DiegoOstuni	0:75fc82583a41	3219
DiegoOstuni	0:75fc82583a41	3220	/*******************************************************************************
DiegoOstuni	0:75fc82583a41	3221	* Wake-Up Mode *
DiegoOstuni	0:75fc82583a41	3222	*******************************************************************************/
DiegoOstuni	0:75fc82583a41	3223
DiegoOstuni	0:75fc82583a41	3224	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	3225	ReturnCode rfalWakeUpModeStart( void config, ST25R3911 mST25, SPI* mspiChannel, DigitalOut* gpio_cs, InterruptIn* IRQ, DigitalOut* fieldLED_01, DigitalOut* fieldLED_02, DigitalOut* fieldLED_03, DigitalOut* fieldLED_04, DigitalOut* fieldLED_05, DigitalOut* fieldLED_06 )
DiegoOstuni	0:75fc82583a41	3226	{
DiegoOstuni	0:75fc82583a41	3227	uint8_t aux;
DiegoOstuni	0:75fc82583a41	3228	uint8_t reg;
DiegoOstuni	0:75fc82583a41	3229	uint32_t irqs;
DiegoOstuni	0:75fc82583a41	3230
DiegoOstuni	0:75fc82583a41	3231	/* The Wake-Up procedure is explained in detail in Application Note: AN4985 */
DiegoOstuni	0:75fc82583a41	3232
DiegoOstuni	0:75fc82583a41	3233	if( config == NULL)
DiegoOstuni	0:75fc82583a41	3234	{
DiegoOstuni	0:75fc82583a41	3235	gRFAL.wum.cfg.period = ST25R3911_WUM_PERIDOD_500MS;
DiegoOstuni	0:75fc82583a41	3236	gRFAL.wum.cfg.irqTout = false;
DiegoOstuni	0:75fc82583a41	3237
DiegoOstuni	0:75fc82583a41	3238	gRFAL.wum.cfg.indPha.enabled = true;
DiegoOstuni	0:75fc82583a41	3239	gRFAL.wum.cfg.indPha.delta = 3;
DiegoOstuni	0:75fc82583a41	3240	gRFAL.wum.cfg.indPha.reference = ST25R3911_WUM_REFRENCE_AUTO;
DiegoOstuni	0:75fc82583a41	3241	gRFAL.wum.cfg.indPha.autoAvg = true;
DiegoOstuni	0:75fc82583a41	3242
DiegoOstuni	0:75fc82583a41	3243
DiegoOstuni	0:75fc82583a41	3244	gRFAL.wum.cfg.cap.enabled = false;
DiegoOstuni	0:75fc82583a41	3245	gRFAL.wum.cfg.cap.delta = 3;
DiegoOstuni	0:75fc82583a41	3246	gRFAL.wum.cfg.cap.reference = ST25R3911_WUM_REFRENCE_AUTO;
DiegoOstuni	0:75fc82583a41	3247	gRFAL.wum.cfg.cap.autoAvg = true;
DiegoOstuni	0:75fc82583a41	3248
DiegoOstuni	0:75fc82583a41	3249
DiegoOstuni	0:75fc82583a41	3250
DiegoOstuni	0:75fc82583a41	3251	gRFAL.wum.cfg.indAmp.enabled = false;
DiegoOstuni	0:75fc82583a41	3252	gRFAL.wum.cfg.indAmp.delta = 3;
DiegoOstuni	0:75fc82583a41	3253	gRFAL.wum.cfg.indAmp.reference = ST25R3911_WUM_REFRENCE_AUTO;
DiegoOstuni	0:75fc82583a41	3254	gRFAL.wum.cfg.indAmp.autoAvg = true;
DiegoOstuni	0:75fc82583a41	3255	}
DiegoOstuni	0:75fc82583a41	3256	else
DiegoOstuni	0:75fc82583a41	3257	{
DiegoOstuni	0:75fc82583a41	3258	gRFAL.wum.cfg = ((st25r3911WakeUpConfig)config);
DiegoOstuni	0:75fc82583a41	3259	}
DiegoOstuni	0:75fc82583a41	3260
DiegoOstuni	0:75fc82583a41	3261
DiegoOstuni	0:75fc82583a41	3262	if( gRFAL.wum.cfg.cap.enabled && (gRFAL.wum.cfg.indAmp.enabled \|\| gRFAL.wum.cfg.indPha.enabled) )
DiegoOstuni	0:75fc82583a41	3263	{
DiegoOstuni	0:75fc82583a41	3264	return ERR_PARAM;
DiegoOstuni	0:75fc82583a41	3265	}
DiegoOstuni	0:75fc82583a41	3266
DiegoOstuni	0:75fc82583a41	3267	irqs = ST25R3911_IRQ_MASK_NONE;
DiegoOstuni	0:75fc82583a41	3268
DiegoOstuni	0:75fc82583a41	3269
DiegoOstuni	0:75fc82583a41	3270
DiegoOstuni	0:75fc82583a41	3271	///// conf wake up timer and control register IRQ if diff larger that delta am -> 00000100
DiegoOstuni	0:75fc82583a41	3272
DiegoOstuni	0:75fc82583a41	3273	//mST25->writeRegister(ST25R3911_REG_WUP_TIMER_CONTROL, ST25R3911_REG_WUP_TIMER_CONTROL_wam, mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	3274
DiegoOstuni	0:75fc82583a41	3275
DiegoOstuni	0:75fc82583a41	3276
DiegoOstuni	0:75fc82583a41	3277
DiegoOstuni	0:75fc82583a41	3278	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	3279	/* Prepare Wake-Up Timer Control Register */
DiegoOstuni	0:75fc82583a41	3280	reg = ((gRFAL.wum.cfg.period & 0x0F) << ST25R3911_REG_WUP_TIMER_CONTROL_shift_wut);
DiegoOstuni	0:75fc82583a41	3281	reg \|= ((gRFAL.wum.cfg.period < ST25R3911_WUM_PERIDOD_100MS) ? ST25R3911_REG_WUP_TIMER_CONTROL_wur : 0x00);
DiegoOstuni	0:75fc82583a41	3282
DiegoOstuni	0:75fc82583a41	3283	if(gRFAL.wum.cfg.irqTout)
DiegoOstuni	0:75fc82583a41	3284	{
DiegoOstuni	0:75fc82583a41	3285	reg \|= ST25R3911_REG_WUP_TIMER_CONTROL_wto;
DiegoOstuni	0:75fc82583a41	3286	irqs \|= ST25R3911_IRQ_MASK_WT;
DiegoOstuni	0:75fc82583a41	3287	}
DiegoOstuni	0:75fc82583a41	3288
DiegoOstuni	0:75fc82583a41	3289	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	3290	/* Check if Inductive Amplitude is to be performed */
DiegoOstuni	0:75fc82583a41	3291	if( gRFAL.wum.cfg.indAmp.enabled )
DiegoOstuni	0:75fc82583a41	3292	{
DiegoOstuni	0:75fc82583a41	3293	aux = ((gRFAL.wum.cfg.indAmp.delta) << ST25R3911_REG_AMPLITUDE_MEASURE_CONF_shift_am_d);
DiegoOstuni	0:75fc82583a41	3294	aux \|= (gRFAL.wum.cfg.indAmp.aaInclMeas ? ST25R3911_REG_AMPLITUDE_MEASURE_CONF_am_aam : 0x00);
DiegoOstuni	0:75fc82583a41	3295	aux \|= ((gRFAL.wum.cfg.indAmp.aaWeight << ST25R3911_REG_AMPLITUDE_MEASURE_CONF_shift_am_aew) & ST25R3911_REG_AMPLITUDE_MEASURE_CONF_mask_am_aew);
DiegoOstuni	0:75fc82583a41	3296	aux \|= (gRFAL.wum.cfg.indAmp.autoAvg ? ST25R3911_REG_AMPLITUDE_MEASURE_CONF_am_ae : 0x00);
DiegoOstuni	0:75fc82583a41	3297
DiegoOstuni	0:75fc82583a41	3298	mST25->writeRegister(ST25R3911_REG_AMPLITUDE_MEASURE_CONF, aux, mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	3299
DiegoOstuni	0:75fc82583a41	3300	/* Only need to set the reference if not using Auto Average */
DiegoOstuni	0:75fc82583a41	3301	if( !gRFAL.wum.cfg.indAmp.autoAvg )
DiegoOstuni	0:75fc82583a41	3302	{
DiegoOstuni	0:75fc82583a41	3303	if( gRFAL.wum.cfg.indAmp.reference == ST25R3911_WUM_REFRENCE_AUTO )
DiegoOstuni	0:75fc82583a41	3304	{
DiegoOstuni	0:75fc82583a41	3305	st25r3911MeasureRF( &aux, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	3306	mST25->writeRegister(ST25R3911_REG_AMPLITUDE_MEASURE_REF, aux, mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	3307	}
DiegoOstuni	0:75fc82583a41	3308	else
DiegoOstuni	0:75fc82583a41	3309	{
DiegoOstuni	0:75fc82583a41	3310	mST25->writeRegister(ST25R3911_REG_AMPLITUDE_MEASURE_REF, gRFAL.wum.cfg.indAmp.reference, mspiChannel, gpio_cs,
DiegoOstuni	0:75fc82583a41	3311	IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	3312	}
DiegoOstuni	0:75fc82583a41	3313	}
DiegoOstuni	0:75fc82583a41	3314
DiegoOstuni	0:75fc82583a41	3315	reg \|= ST25R3911_REG_WUP_TIMER_CONTROL_wam;
DiegoOstuni	0:75fc82583a41	3316	irqs \|= ST25R3911_IRQ_MASK_WAM;
DiegoOstuni	0:75fc82583a41	3317	}
DiegoOstuni	0:75fc82583a41	3318
DiegoOstuni	0:75fc82583a41	3319	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	3320	/* Check if Inductive Phase is to be performed */
DiegoOstuni	0:75fc82583a41	3321	if( gRFAL.wum.cfg.indPha.enabled )
DiegoOstuni	0:75fc82583a41	3322	{
DiegoOstuni	0:75fc82583a41	3323	aux = ((gRFAL.wum.cfg.indPha.delta) << ST25R3911_REG_PHASE_MEASURE_CONF_shift_pm_d);
DiegoOstuni	0:75fc82583a41	3324	aux \|= (gRFAL.wum.cfg.indPha.aaInclMeas ? ST25R3911_REG_PHASE_MEASURE_CONF_pm_aam : 0x00);
DiegoOstuni	0:75fc82583a41	3325	aux \|= ((gRFAL.wum.cfg.indPha.aaWeight << ST25R3911_REG_PHASE_MEASURE_CONF_shift_pm_aew) & ST25R3911_REG_PHASE_MEASURE_CONF_mask_pm_aew);
DiegoOstuni	0:75fc82583a41	3326	aux \|= (gRFAL.wum.cfg.indPha.autoAvg ? ST25R3911_REG_PHASE_MEASURE_CONF_pm_ae : 0x00);
DiegoOstuni	0:75fc82583a41	3327
DiegoOstuni	0:75fc82583a41	3328	mST25->writeRegister(ST25R3911_REG_PHASE_MEASURE_CONF, aux, mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	3329
DiegoOstuni	0:75fc82583a41	3330	/* Only need to set the reference if not using Auto Average */
DiegoOstuni	0:75fc82583a41	3331	if( !gRFAL.wum.cfg.indPha.autoAvg )
DiegoOstuni	0:75fc82583a41	3332	{
DiegoOstuni	0:75fc82583a41	3333	if( gRFAL.wum.cfg.indPha.reference == ST25R3911_WUM_REFRENCE_AUTO )
DiegoOstuni	0:75fc82583a41	3334	{
DiegoOstuni	0:75fc82583a41	3335	st25r3911MeasureAntennaResonance( &aux, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	3336	mST25->writeRegister(ST25R3911_REG_PHASE_MEASURE_REF, aux, mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	3337	}
DiegoOstuni	0:75fc82583a41	3338	else
DiegoOstuni	0:75fc82583a41	3339	{
DiegoOstuni	0:75fc82583a41	3340
DiegoOstuni	0:75fc82583a41	3341	mST25->writeRegister(ST25R3911_REG_PHASE_MEASURE_REF, gRFAL.wum.cfg.indPha.reference, mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	3342
DiegoOstuni	0:75fc82583a41	3343	}
DiegoOstuni	0:75fc82583a41	3344	}
DiegoOstuni	0:75fc82583a41	3345
DiegoOstuni	0:75fc82583a41	3346	reg \|= ST25R3911_REG_WUP_TIMER_CONTROL_wph;
DiegoOstuni	0:75fc82583a41	3347	irqs \|= ST25R3911_IRQ_MASK_WPH;
DiegoOstuni	0:75fc82583a41	3348	}
DiegoOstuni	0:75fc82583a41	3349
DiegoOstuni	0:75fc82583a41	3350	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	3351	/* Check if Capacitive is to be performed */
DiegoOstuni	0:75fc82583a41	3352	if( gRFAL.wum.cfg.cap.enabled )
DiegoOstuni	0:75fc82583a41	3353	{
DiegoOstuni	0:75fc82583a41	3354	return ERR_NOT_IMPLEMENTED;
DiegoOstuni	0:75fc82583a41	3355	}
DiegoOstuni	0:75fc82583a41	3356
DiegoOstuni	0:75fc82583a41	3357	/* Disable External Field Detector */
DiegoOstuni	0:75fc82583a41	3358	st25r3911ClrRegisterBits( ST25R3911_REG_AUX, ST25R3911_REG_AUX_en_fd, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	3359
DiegoOstuni	0:75fc82583a41	3360	/* Disable and clear all interrupts except Wake-Up IRQs */
DiegoOstuni	0:75fc82583a41	3361	st25r3911DisableInterrupts( ST25R3911_IRQ_MASK_ALL, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	3362	st25r3911GetInterrupt( irqs, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	3363	st25r3911EnableInterrupts( irqs, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	3364
DiegoOstuni	0:75fc82583a41	3365	/* Enable Low Power Wake-Up Mode */
DiegoOstuni	0:75fc82583a41	3366	mST25->writeRegister(ST25R3911_REG_WUP_TIMER_CONTROL, reg, mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	3367	mST25->writeRegister(ST25R3911_REG_OP_CONTROL, ST25R3911_REG_OP_CONTROL_wu, mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	3368
DiegoOstuni	0:75fc82583a41	3369
DiegoOstuni	0:75fc82583a41	3370
DiegoOstuni	0:75fc82583a41	3371	gRFAL.wum.state = RFAL_WUM_STATE_ENABLED;
DiegoOstuni	0:75fc82583a41	3372	gRFAL.state = RFAL_STATE_WUM;
DiegoOstuni	0:75fc82583a41	3373
DiegoOstuni	0:75fc82583a41	3374	return ERR_NONE;
DiegoOstuni	0:75fc82583a41	3375	}
DiegoOstuni	0:75fc82583a41	3376
DiegoOstuni	0:75fc82583a41	3377
DiegoOstuni	0:75fc82583a41	3378	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	3379	bool rfalWakeUpModeHasWoke( ST25R3911* mST25, SPI* mspiChannel, DigitalOut* gpio_cs, InterruptIn* IRQ, DigitalOut* fieldLED_01, DigitalOut* fieldLED_02, DigitalOut* fieldLED_03, DigitalOut* fieldLED_04, DigitalOut* fieldLED_05, DigitalOut* fieldLED_06 )
DiegoOstuni	0:75fc82583a41	3380	{
DiegoOstuni	0:75fc82583a41	3381
DiegoOstuni	0:75fc82583a41	3382	return (gRFAL.wum.state == RFAL_WUM_STATE_ENABLED_WOKE);
DiegoOstuni	0:75fc82583a41	3383	}
DiegoOstuni	0:75fc82583a41	3384
DiegoOstuni	0:75fc82583a41	3385
DiegoOstuni	0:75fc82583a41	3386	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	3387	static void rfalRunWakeUpModeWorker( SPI* mspiChannel, ST25R3911* mST25, DigitalOut* gpio_cs, InterruptIn* IRQ, DigitalOut* fieldLED_01, DigitalOut* fieldLED_02, DigitalOut* fieldLED_03, DigitalOut* fieldLED_04, DigitalOut* fieldLED_05, DigitalOut* fieldLED_06 )
DiegoOstuni	0:75fc82583a41	3388	{
DiegoOstuni	0:75fc82583a41	3389	uint32_t irqs;
DiegoOstuni	0:75fc82583a41	3390
DiegoOstuni	0:75fc82583a41	3391	if( gRFAL.state != RFAL_STATE_WUM )
DiegoOstuni	0:75fc82583a41	3392	{
DiegoOstuni	0:75fc82583a41	3393	return;
DiegoOstuni	0:75fc82583a41	3394	}
DiegoOstuni	0:75fc82583a41	3395
DiegoOstuni	0:75fc82583a41	3396	switch( gRFAL.wum.state )
DiegoOstuni	0:75fc82583a41	3397	{
DiegoOstuni	0:75fc82583a41	3398	case RFAL_WUM_STATE_ENABLED:
DiegoOstuni	0:75fc82583a41	3399	case RFAL_WUM_STATE_ENABLED_WOKE:
DiegoOstuni	0:75fc82583a41	3400
DiegoOstuni	0:75fc82583a41	3401	irqs = st25r3911GetInterrupt( ( ST25R3911_IRQ_MASK_WT \| ST25R3911_IRQ_MASK_WAM \| ST25R3911_IRQ_MASK_WPH \| ST25R3911_IRQ_MASK_WCAP ), mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	3402	if( irqs == ST25R3911_IRQ_MASK_NONE )
DiegoOstuni	0:75fc82583a41	3403	{
DiegoOstuni	0:75fc82583a41	3404	break; /* No interrupt to process */
DiegoOstuni	0:75fc82583a41	3405	}
DiegoOstuni	0:75fc82583a41	3406
DiegoOstuni	0:75fc82583a41	3407	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	3408	/* Check and mark which measurement(s) cause interrupt */
DiegoOstuni	0:75fc82583a41	3409	if(irqs & ST25R3911_IRQ_MASK_WAM)
DiegoOstuni	0:75fc82583a41	3410	{
DiegoOstuni	0:75fc82583a41	3411	gRFAL.wum.state = RFAL_WUM_STATE_ENABLED_WOKE;
DiegoOstuni	0:75fc82583a41	3412	}
DiegoOstuni	0:75fc82583a41	3413
DiegoOstuni	0:75fc82583a41	3414	if(irqs & ST25R3911_IRQ_MASK_WPH)
DiegoOstuni	0:75fc82583a41	3415	{
DiegoOstuni	0:75fc82583a41	3416	gRFAL.wum.state = RFAL_WUM_STATE_ENABLED_WOKE;
DiegoOstuni	0:75fc82583a41	3417	}
DiegoOstuni	0:75fc82583a41	3418
DiegoOstuni	0:75fc82583a41	3419	if(irqs & ST25R3911_IRQ_MASK_WCAP)
DiegoOstuni	0:75fc82583a41	3420	{
DiegoOstuni	0:75fc82583a41	3421	gRFAL.wum.state = RFAL_WUM_STATE_ENABLED_WOKE;
DiegoOstuni	0:75fc82583a41	3422	}
DiegoOstuni	0:75fc82583a41	3423	break;
DiegoOstuni	0:75fc82583a41	3424
DiegoOstuni	0:75fc82583a41	3425	default:
DiegoOstuni	0:75fc82583a41	3426	break;
DiegoOstuni	0:75fc82583a41	3427	}
DiegoOstuni	0:75fc82583a41	3428	}
DiegoOstuni	0:75fc82583a41	3429
DiegoOstuni	0:75fc82583a41	3430
DiegoOstuni	0:75fc82583a41	3431	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	3432	ReturnCode rfalWakeUpModeStop( SPI* mspiChannel, ST25R3911* mST25, DigitalOut* gpio_cs, InterruptIn* IRQ, DigitalOut* fieldLED_01, DigitalOut* fieldLED_02, DigitalOut* fieldLED_03, DigitalOut* fieldLED_04, DigitalOut* fieldLED_05, DigitalOut* fieldLED_06 )
DiegoOstuni	0:75fc82583a41	3433	{
DiegoOstuni	0:75fc82583a41	3434	if( gRFAL.wum.state == RFAL_WUM_STATE_NOT_INIT )
DiegoOstuni	0:75fc82583a41	3435	{
DiegoOstuni	0:75fc82583a41	3436	return ERR_WRONG_STATE;
DiegoOstuni	0:75fc82583a41	3437	}
DiegoOstuni	0:75fc82583a41	3438
DiegoOstuni	0:75fc82583a41	3439	gRFAL.wum.state = RFAL_WUM_STATE_NOT_INIT;
DiegoOstuni	0:75fc82583a41	3440
DiegoOstuni	0:75fc82583a41	3441	/* Re-Enable External Field Detector */
DiegoOstuni	0:75fc82583a41	3442	st25r3911SetRegisterBits( ST25R3911_REG_AUX, ST25R3911_REG_AUX_en_fd, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	3443
DiegoOstuni	0:75fc82583a41	3444	/* Disable Wake-Up Mode */
DiegoOstuni	0:75fc82583a41	3445	st25r3911ClrRegisterBits( ST25R3911_REG_OP_CONTROL, ST25R3911_REG_OP_CONTROL_wu, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	3446	st25r3911DisableInterrupts( (ST25R3911_IRQ_MASK_WT \| ST25R3911_IRQ_MASK_WAM \| ST25R3911_IRQ_MASK_WPH \| ST25R3911_IRQ_MASK_WCAP),
DiegoOstuni	0:75fc82583a41	3447	mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	3448
DiegoOstuni	0:75fc82583a41	3449	/* Re-Enable the Oscillator */
DiegoOstuni	0:75fc82583a41	3450	st25r3911OscOn( mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	3451
DiegoOstuni	0:75fc82583a41	3452	return ERR_NONE;
DiegoOstuni	0:75fc82583a41	3453	}
DiegoOstuni	0:75fc82583a41	3454
DiegoOstuni	0:75fc82583a41	3455
DiegoOstuni	0:75fc82583a41	3456	/*******************************************************************************
DiegoOstuni	0:75fc82583a41	3457	* RF Chip *
DiegoOstuni	0:75fc82583a41	3458	*******************************************************************************/
DiegoOstuni	0:75fc82583a41	3459
DiegoOstuni	0:75fc82583a41	3460	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	3461	ReturnCode rfalChipWriteReg( uint16_t reg, uint8_t* values, uint8_t len, SPI * mspiChannel, ST25R3911* mST25, DigitalOut* gpio_cs, InterruptIn* IRQ, DigitalOut* fieldLED_01, DigitalOut* fieldLED_02, DigitalOut* fieldLED_03, DigitalOut* fieldLED_04, DigitalOut* fieldLED_05, DigitalOut* fieldLED_06 )
DiegoOstuni	0:75fc82583a41	3462	{
DiegoOstuni	0:75fc82583a41	3463	if( !st25r3911IsRegValid( (uint8_t)reg) )
DiegoOstuni	0:75fc82583a41	3464	{
DiegoOstuni	0:75fc82583a41	3465	return ERR_PARAM;
DiegoOstuni	0:75fc82583a41	3466	}
DiegoOstuni	0:75fc82583a41	3467
DiegoOstuni	0:75fc82583a41	3468	mST25 -> writeMultipleRegisters( (uint8_t)reg, values, len, mspiChannel,mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	3469	return ERR_NONE;
DiegoOstuni	0:75fc82583a41	3470	}
DiegoOstuni	0:75fc82583a41	3471
DiegoOstuni	0:75fc82583a41	3472	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	3473	ReturnCode rfalChipReadReg( uint16_t reg, uint8_t* values, uint8_t len, SPI * mspiChannel, ST25R3911* mST25, DigitalOut* gpio_cs, InterruptIn* IRQ, DigitalOut* fieldLED_01, DigitalOut* fieldLED_02, DigitalOut* fieldLED_03, DigitalOut* fieldLED_04, DigitalOut* fieldLED_05, DigitalOut* fieldLED_06 )
DiegoOstuni	0:75fc82583a41	3474	{
DiegoOstuni	0:75fc82583a41	3475	if( !st25r3911IsRegValid( (uint8_t)reg) )
DiegoOstuni	0:75fc82583a41	3476	{
DiegoOstuni	0:75fc82583a41	3477	return ERR_PARAM;
DiegoOstuni	0:75fc82583a41	3478	}
DiegoOstuni	0:75fc82583a41	3479
DiegoOstuni	0:75fc82583a41	3480	mST25 -> readMultipleRegisters( (uint8_t)reg, values, len, mspiChannel,mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	3481	return ERR_NONE;
DiegoOstuni	0:75fc82583a41	3482	}
DiegoOstuni	0:75fc82583a41	3483
DiegoOstuni	0:75fc82583a41	3484	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	3485	ReturnCode rfalChipExecCmd( uint16_t cmd, SPI * mspiChannel, ST25R3911* mST25, DigitalOut* gpio_cs, InterruptIn* IRQ, DigitalOut* fieldLED_01, DigitalOut* fieldLED_02, DigitalOut* fieldLED_03, DigitalOut* fieldLED_04, DigitalOut* fieldLED_05, DigitalOut* fieldLED_06 )
DiegoOstuni	0:75fc82583a41	3486	{
DiegoOstuni	0:75fc82583a41	3487	if( !st25r3911IsCmdValid( (uint8_t)cmd) )
DiegoOstuni	0:75fc82583a41	3488	{
DiegoOstuni	0:75fc82583a41	3489	return ERR_PARAM;
DiegoOstuni	0:75fc82583a41	3490	}
DiegoOstuni	0:75fc82583a41	3491
DiegoOstuni	0:75fc82583a41	3492	mST25 -> executeCommand( (uint8_t) cmd, mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	3493	return ERR_NONE;
DiegoOstuni	0:75fc82583a41	3494	}
DiegoOstuni	0:75fc82583a41	3495
DiegoOstuni	0:75fc82583a41	3496	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	3497	ReturnCode rfalChipWriteTestReg( uint16_t reg, uint8_t value, SPI * mspiChannel, ST25R3911* mST25, DigitalOut* gpio_cs, InterruptIn* IRQ, DigitalOut* fieldLED_01, DigitalOut* fieldLED_02, DigitalOut* fieldLED_03, DigitalOut* fieldLED_04, DigitalOut* fieldLED_05, DigitalOut* fieldLED_06 )
DiegoOstuni	0:75fc82583a41	3498	{
DiegoOstuni	0:75fc82583a41	3499	st25r3911WriteTestRegister( (uint8_t)reg, value, mST25, mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	3500	return ERR_NONE;
DiegoOstuni	0:75fc82583a41	3501	}
DiegoOstuni	0:75fc82583a41	3502
DiegoOstuni	0:75fc82583a41	3503	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	3504	ReturnCode rfalChipReadTestReg( uint16_t reg, uint8_t* value, SPI * mspiChannel, ST25R3911* mST25, DigitalOut* gpio_cs, InterruptIn* IRQ, DigitalOut* fieldLED_01, DigitalOut* fieldLED_02, DigitalOut* fieldLED_03, DigitalOut* fieldLED_04, DigitalOut* fieldLED_05, DigitalOut* fieldLED_06 )
DiegoOstuni	0:75fc82583a41	3505	{
DiegoOstuni	0:75fc82583a41	3506	st25r3911ReadTestRegister( (uint8_t)reg, value, mST25, mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	3507	return ERR_NONE;
DiegoOstuni	0:75fc82583a41	3508	}
DiegoOstuni	0:75fc82583a41	3509
DiegoOstuni	0:75fc82583a41	3510	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	3511	ReturnCode rfalChipChangeRegBits( uint16_t reg, uint8_t valueMask, uint8_t value, SPI* mspiChannel,
DiegoOstuni	0:75fc82583a41	3512	ST25R3911* mST25, DigitalOut* gpio_cs, InterruptIn* IRQ, DigitalOut* fieldLED_01, DigitalOut* fieldLED_02, DigitalOut* fieldLED_03, DigitalOut* fieldLED_04, DigitalOut* fieldLED_05, DigitalOut* fieldLED_06 )
DiegoOstuni	0:75fc82583a41	3513	{
DiegoOstuni	0:75fc82583a41	3514	st25r3911ChangeRegisterBits( (uint8_t)reg, valueMask, value, mspiChannel, mST25, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	3515	return ERR_NONE;
DiegoOstuni	0:75fc82583a41	3516	}
DiegoOstuni	0:75fc82583a41	3517
DiegoOstuni	0:75fc82583a41	3518	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	3519	ReturnCode rfalChipChangeTestRegBits( uint16_t reg, uint8_t valueMask, uint8_t value, SPI * mspiChannel, ST25R3911* mST25,
DiegoOstuni	0:75fc82583a41	3520	DigitalOut* gpio_cs, InterruptIn* IRQ, DigitalOut* fieldLED_01, DigitalOut* fieldLED_02, DigitalOut* fieldLED_03, DigitalOut* fieldLED_04, DigitalOut* fieldLED_05, DigitalOut* fieldLED_06 )
DiegoOstuni	0:75fc82583a41	3521	{
DiegoOstuni	0:75fc82583a41	3522	st25r3911ChangeTestRegisterBits( (uint8_t)reg, valueMask, value, mST25, mspiChannel, gpio_cs, IRQ, fieldLED_01, fieldLED_02, fieldLED_03, fieldLED_04, fieldLED_05, fieldLED_06 ) ;
DiegoOstuni	0:75fc82583a41	3523	return ERR_NONE;
DiegoOstuni	0:75fc82583a41	3524	}
DiegoOstuni	0:75fc82583a41	3525
DiegoOstuni	0:75fc82583a41	3526
DiegoOstuni	0:75fc82583a41	3527
DiegoOstuni	0:75fc82583a41	3528	void rfalSetWumState( void )
DiegoOstuni	0:75fc82583a41	3529	{
DiegoOstuni	0:75fc82583a41	3530	gRFAL.wum.state = RFAL_WUM_STATE_ENABLED_WOKE;
DiegoOstuni	0:75fc82583a41	3531	}
DiegoOstuni	0:75fc82583a41	3532
DiegoOstuni	0:75fc82583a41	3533
DiegoOstuni	0:75fc82583a41	3534	/*******************************************************************************/
DiegoOstuni	0:75fc82583a41	3535	/* extern uint8_t invalid_size_of_stream_configs[(sizeof(struct st25r3911StreamConfig) == sizeof(struct iso15693StreamConfig))?1:(-1)]; */

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Type:	Library
Created:	14 Nov 2019
Imports:	0
Forks:	0
Commits:	1
Dependents:	0
Dependencies:	0
Followers:	1

The code in this repository is Apache licensed.

rfal_rf.cpp@0:75fc82583a41, 2019-11-14 (annotated)

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