Diego Ostuni / RFAL

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rfal_analogConfigTbl.h@0:75fc82583a41, 2019-11-14 (annotated)

Committer:
DiegoOstuni
Date:
Thu Nov 14 14:34:50 2019 +0000
Revision:
0:75fc82583a41
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DiegoOstuni 0:75fc82583a41 1
DiegoOstuni 0:75fc82583a41 2 /******************************************************************************
DiegoOstuni 0:75fc82583a41 3 * @attention
DiegoOstuni 0:75fc82583a41 4 *
DiegoOstuni 0:75fc82583a41 5 * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
DiegoOstuni 0:75fc82583a41 6 *
DiegoOstuni 0:75fc82583a41 7 * Licensed under ST MYLIBERTY SOFTWARE LICENSE AGREEMENT (the "License");
DiegoOstuni 0:75fc82583a41 8 * You may not use this file except in compliance with the License.
DiegoOstuni 0:75fc82583a41 9 * You may obtain a copy of the License at:
DiegoOstuni 0:75fc82583a41 10 *
DiegoOstuni 0:75fc82583a41 11 * http://www.st.com/myliberty
DiegoOstuni 0:75fc82583a41 12 *
DiegoOstuni 0:75fc82583a41 13 * Unless required by applicable law or agreed to in writing, software
DiegoOstuni 0:75fc82583a41 14 * distributed under the License is distributed on an "AS IS" BASIS,
DiegoOstuni 0:75fc82583a41 15 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied,
DiegoOstuni 0:75fc82583a41 16 * AND SPECIFICALLY DISCLAIMING THE IMPLIED WARRANTIES OF MERCHANTABILITY,
DiegoOstuni 0:75fc82583a41 17 * FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT.
DiegoOstuni 0:75fc82583a41 18 * See the License for the specific language governing permissions and
DiegoOstuni 0:75fc82583a41 19 * limitations under the License.
DiegoOstuni 0:75fc82583a41 20 *
DiegoOstuni 0:75fc82583a41 21 ******************************************************************************/
DiegoOstuni 0:75fc82583a41 22
DiegoOstuni 0:75fc82583a41 23 /*
DiegoOstuni 0:75fc82583a41 24 * PROJECT: ST25R391x firmware
DiegoOstuni 0:75fc82583a41 25 * $Revision: $
DiegoOstuni 0:75fc82583a41 26 * LANGUAGE: ISO C99
DiegoOstuni 0:75fc82583a41 27 */
DiegoOstuni 0:75fc82583a41 28
DiegoOstuni 0:75fc82583a41 29 /*! \file rfal_analogConfig.h
DiegoOstuni 0:75fc82583a41 30 *
DiegoOstuni 0:75fc82583a41 31 * \author bkam
DiegoOstuni 0:75fc82583a41 32 *
DiegoOstuni 0:75fc82583a41 33 * \brief ST25R3911 Analog Configuration Settings
DiegoOstuni 0:75fc82583a41 34 *
DiegoOstuni 0:75fc82583a41 35 */
DiegoOstuni 0:75fc82583a41 36
DiegoOstuni 0:75fc82583a41 37 #ifndef ST25R3911_ANALOGCONFIG_H
DiegoOstuni 0:75fc82583a41 38 #define ST25R3911_ANALOGCONFIG_H
DiegoOstuni 0:75fc82583a41 39
DiegoOstuni 0:75fc82583a41 40 /*
DiegoOstuni 0:75fc82583a41 41 ******************************************************************************
DiegoOstuni 0:75fc82583a41 42 * INCLUDES
DiegoOstuni 0:75fc82583a41 43 ******************************************************************************
DiegoOstuni 0:75fc82583a41 44 */
DiegoOstuni 0:75fc82583a41 45 #include "rfal_AnalogConfig.h"
DiegoOstuni 0:75fc82583a41 46 #include "st25r3911_com.h"
DiegoOstuni 0:75fc82583a41 47
DiegoOstuni 0:75fc82583a41 48 /*
DiegoOstuni 0:75fc82583a41 49 ******************************************************************************
DiegoOstuni 0:75fc82583a41 50 * DEFINES
DiegoOstuni 0:75fc82583a41 51 ******************************************************************************
DiegoOstuni 0:75fc82583a41 52 */
DiegoOstuni 0:75fc82583a41 53
DiegoOstuni 0:75fc82583a41 54 /*
DiegoOstuni 0:75fc82583a41 55 ******************************************************************************
DiegoOstuni 0:75fc82583a41 56 * GLOBAL MACROS
DiegoOstuni 0:75fc82583a41 57 ******************************************************************************
DiegoOstuni 0:75fc82583a41 58 */
DiegoOstuni 0:75fc82583a41 59
DiegoOstuni 0:75fc82583a41 60 /*! Macro for Configuration Setting with only one register-mask-value set:
DiegoOstuni 0:75fc82583a41 61 * - Configuration ID[2], Number of Register sets to follow[1], Register[2], Mask[1], Value[1] */
DiegoOstuni 0:75fc82583a41 62 #define MODE_ENTRY_1_REG(MODE, R0, M0, V0) \
DiegoOstuni 0:75fc82583a41 63 (MODE >> 8), (MODE & 0xFF), 1, (R0 >> 8), (R0 & 0xFF), (M0), (V0)
DiegoOstuni 0:75fc82583a41 64
DiegoOstuni 0:75fc82583a41 65 /*! Macro for Configuration Setting with only two register-mask-value sets:
DiegoOstuni 0:75fc82583a41 66 * - Configuration ID[2], Number of Register sets to follow[1], Register[2], Mask[1], Value[1], Register[2], Mask[1], Value[1] */
DiegoOstuni 0:75fc82583a41 67 #define MODE_ENTRY_2_REG(MODE, R0, M0, V0, R1, M1, V1) \
DiegoOstuni 0:75fc82583a41 68 (MODE >> 8), (MODE & 0xFF), 2, (R0 >> 8), (R0 & 0xFF), (M0), (V0) \
DiegoOstuni 0:75fc82583a41 69 , (R1 >> 8), (R1 & 0xFF), (M1), (V1)
DiegoOstuni 0:75fc82583a41 70
DiegoOstuni 0:75fc82583a41 71 /*! Macro for Configuration Setting with only three register-mask-value sets:
DiegoOstuni 0:75fc82583a41 72 * - Configuration ID[2], Number of Register sets to follow[1], Register[2], Mask[1], Value[1], Register[2], Mask[1], Value[1], Register[2]... */
DiegoOstuni 0:75fc82583a41 73 #define MODE_ENTRY_3_REG(MODE, R0, M0, V0, R1, M1, V1, R2, M2, V2) \
DiegoOstuni 0:75fc82583a41 74 (MODE >> 8), (MODE & 0xFF), 3, (R0 >> 8), (R0 & 0xFF), (M0), (V0) \
DiegoOstuni 0:75fc82583a41 75 , (R1 >> 8), (R1 & 0xFF), (M1), (V1) \
DiegoOstuni 0:75fc82583a41 76 , (R2 >> 8), (R2 & 0xFF), (M2), (V2) \
DiegoOstuni 0:75fc82583a41 77
DiegoOstuni 0:75fc82583a41 78 /*! Macro for Configuration Setting with only four register-mask-value sets:
DiegoOstuni 0:75fc82583a41 79 * - Configuration ID[2], Number of Register sets to follow[1], Register[2], Mask[1], Value[1], Register[2], Mask[1], Value[1], Register[2]... */
DiegoOstuni 0:75fc82583a41 80 #define MODE_ENTRY_4_REG(MODE, R0, M0, V0, R1, M1, V1, R2, M2, V2, R3, M3, V3) \
DiegoOstuni 0:75fc82583a41 81 (MODE >> 8), (MODE & 0xFF), 4, (R0 >> 8), (R0 & 0xFF), (M0), (V0) \
DiegoOstuni 0:75fc82583a41 82 , (R1 >> 8), (R1 & 0xFF), (M1), (V1) \
DiegoOstuni 0:75fc82583a41 83 , (R2 >> 8), (R2 & 0xFF), (M2), (V2) \
DiegoOstuni 0:75fc82583a41 84 , (R3 >> 8), (R3 & 0xFF), (M3), (V3) \
DiegoOstuni 0:75fc82583a41 85
DiegoOstuni 0:75fc82583a41 86 /*! Macro for Configuration Setting with only five register-mask-value sets:
DiegoOstuni 0:75fc82583a41 87 * - Configuration ID[2], Number of Register sets to follow[1], Register[2], Mask[1], Value[1], Register[2], Mask[1], Value[1], Register[2]... */
DiegoOstuni 0:75fc82583a41 88 #define MODE_ENTRY_5_REG(MODE, R0, M0, V0, R1, M1, V1, R2, M2, V2, R3, M3, V3, R4, M4, V4) \
DiegoOstuni 0:75fc82583a41 89 (MODE >> 8), (MODE & 0xFF), 5, (R0 >> 8), (R0 & 0xFF), (M0), (V0) \
DiegoOstuni 0:75fc82583a41 90 , (R1 >> 8), (R1 & 0xFF), (M1), (V1) \
DiegoOstuni 0:75fc82583a41 91 , (R2 >> 8), (R2 & 0xFF), (M2), (V2) \
DiegoOstuni 0:75fc82583a41 92 , (R3 >> 8), (R3 & 0xFF), (M3), (V3) \
DiegoOstuni 0:75fc82583a41 93 , (R4 >> 8), (R4 & 0xFF), (M4), (V4) \
DiegoOstuni 0:75fc82583a41 94
DiegoOstuni 0:75fc82583a41 95 /*! Macro for Configuration Setting with only six register-mask-value sets:
DiegoOstuni 0:75fc82583a41 96 * - Configuration ID[2], Number of Register sets to follow[1], Register[2], Mask[1], Value[1], Register[2], Mask[1], Value[1], Register[2]... */
DiegoOstuni 0:75fc82583a41 97 #define MODE_ENTRY_6_REG(MODE, R0, M0, V0, R1, M1, V1, R2, M2, V2, R3, M3, V3, R4, M4, V4, R5, M5, V5) \
DiegoOstuni 0:75fc82583a41 98 (MODE >> 8), (MODE & 0xFF), 6, (R0 >> 8), (R0 & 0xFF), (M0), (V0) \
DiegoOstuni 0:75fc82583a41 99 , (R1 >> 8), (R1 & 0xFF), (M1), (V1) \
DiegoOstuni 0:75fc82583a41 100 , (R2 >> 8), (R2 & 0xFF), (M2), (V2) \
DiegoOstuni 0:75fc82583a41 101 , (R3 >> 8), (R3 & 0xFF), (M3), (V3) \
DiegoOstuni 0:75fc82583a41 102 , (R4 >> 8), (R4 & 0xFF), (M4), (V4) \
DiegoOstuni 0:75fc82583a41 103 , (R5 >> 8), (R5 & 0xFF), (M5), (V5) \
DiegoOstuni 0:75fc82583a41 104
DiegoOstuni 0:75fc82583a41 105 /*! Macro for Configuration Setting with only seven register-mask-value sets:
DiegoOstuni 0:75fc82583a41 106 * - Configuration ID[2], Number of Register sets to follow[1], Register[2], Mask[1], Value[1], Register[2], Mask[1], Value[1], Register[2]... */
DiegoOstuni 0:75fc82583a41 107 #define MODE_ENTRY_7_REG(MODE, R0, M0, V0, R1, M1, V1, R2, M2, V2, R3, M3, V3, R4, M4, V4, R5, M5, V5, R6, M6, V6) \
DiegoOstuni 0:75fc82583a41 108 (MODE >> 8), (MODE & 0xFF), 7, (R0 >> 8), (R0 & 0xFF), (M0), (V0) \
DiegoOstuni 0:75fc82583a41 109 , (R1 >> 8), (R1 & 0xFF), (M1), (V1) \
DiegoOstuni 0:75fc82583a41 110 , (R2 >> 8), (R2 & 0xFF), (M2), (V2) \
DiegoOstuni 0:75fc82583a41 111 , (R3 >> 8), (R3 & 0xFF), (M3), (V3) \
DiegoOstuni 0:75fc82583a41 112 , (R4 >> 8), (R4 & 0xFF), (M4), (V4) \
DiegoOstuni 0:75fc82583a41 113 , (R5 >> 8), (R5 & 0xFF), (M5), (V5) \
DiegoOstuni 0:75fc82583a41 114 , (R6 >> 8), (R6 & 0xFF), (M6), (V6) \
DiegoOstuni 0:75fc82583a41 115
DiegoOstuni 0:75fc82583a41 116 /*! Macro for Configuration Setting with only eight register-mask-value sets:
DiegoOstuni 0:75fc82583a41 117 * - Configuration ID[2], Number of Register sets to follow[1], Register[2], Mask[1], Value[1], Register[2], Mask[1], Value[1], Register[2]... */
DiegoOstuni 0:75fc82583a41 118 #define MODE_ENTRY_8_REG(MODE, R0, M0, V0, R1, M1, V1, R2, M2, V2, R3, M3, V3, R4, M4, V4, R5, M5, V5, R6, M6, V6, R7, M7, V7) \
DiegoOstuni 0:75fc82583a41 119 (MODE >> 8), (MODE & 0xFF), 8, (R0 >> 8), (R0 & 0xFF), (M0), (V0) \
DiegoOstuni 0:75fc82583a41 120 , (R1 >> 8), (R1 & 0xFF), (M1), (V1) \
DiegoOstuni 0:75fc82583a41 121 , (R2 >> 8), (R2 & 0xFF), (M2), (V2) \
DiegoOstuni 0:75fc82583a41 122 , (R3 >> 8), (R3 & 0xFF), (M3), (V3) \
DiegoOstuni 0:75fc82583a41 123 , (R4 >> 8), (R4 & 0xFF), (M4), (V4) \
DiegoOstuni 0:75fc82583a41 124 , (R5 >> 8), (R5 & 0xFF), (M5), (V5) \
DiegoOstuni 0:75fc82583a41 125 , (R6 >> 8), (R6 & 0xFF), (M6), (V6) \
DiegoOstuni 0:75fc82583a41 126 , (R7 >> 8), (R7 & 0xFF), (M7), (V7) \
DiegoOstuni 0:75fc82583a41 127
DiegoOstuni 0:75fc82583a41 128 /*! Macro for Configuration Setting with only nine register-mask-value sets:
DiegoOstuni 0:75fc82583a41 129 * - Configuration ID[2], Number of Register sets to follow[1], Register[2], Mask[1], Value[1], Register[2], Mask[1], Value[1], Register[2]... */
DiegoOstuni 0:75fc82583a41 130 #define MODE_ENTRY_9_REG(MODE, R0, M0, V0, R1, M1, V1, R2, M2, V2, R3, M3, V3, R4, M4, V4, R5, M5, V5, R6, M6, V6, R7, M7, V7, R8, M8, V8) \
DiegoOstuni 0:75fc82583a41 131 (MODE >> 8), (MODE & 0xFF), 9, (R0 >> 8), (R0 & 0xFF), (M0), (V0) \
DiegoOstuni 0:75fc82583a41 132 , (R1 >> 8), (R1 & 0xFF), (M1), (V1) \
DiegoOstuni 0:75fc82583a41 133 , (R2 >> 8), (R2 & 0xFF), (M2), (V2) \
DiegoOstuni 0:75fc82583a41 134 , (R3 >> 8), (R3 & 0xFF), (M3), (V3) \
DiegoOstuni 0:75fc82583a41 135 , (R4 >> 8), (R4 & 0xFF), (M4), (V4) \
DiegoOstuni 0:75fc82583a41 136 , (R5 >> 8), (R5 & 0xFF), (M5), (V5) \
DiegoOstuni 0:75fc82583a41 137 , (R6 >> 8), (R6 & 0xFF), (M6), (V6) \
DiegoOstuni 0:75fc82583a41 138 , (R7 >> 8), (R7 & 0xFF), (M7), (V7) \
DiegoOstuni 0:75fc82583a41 139 , (R8 >> 8), (R8 & 0xFF), (M8), (V8) \
DiegoOstuni 0:75fc82583a41 140
DiegoOstuni 0:75fc82583a41 141 /*! Macro for Configuration Setting with only ten register-mask-value sets:
DiegoOstuni 0:75fc82583a41 142 * - Configuration ID[2], Number of Register sets to follow[1], Register[2], Mask[1], Value[1], Register[2], Mask[1], Value[1], Register[2]... */
DiegoOstuni 0:75fc82583a41 143 #define MODE_ENTRY_10_REG(MODE, R0, M0, V0, R1, M1, V1, R2, M2, V2, R3, M3, V3, R4, M4, V4, R5, M5, V5, R6, M6, V6, R7, M7, V7, R8, M8, V8, R9, M9, V9) \
DiegoOstuni 0:75fc82583a41 144 (MODE >> 8), (MODE & 0xFF),10, (R0 >> 8), (R0 & 0xFF), (M0), (V0) \
DiegoOstuni 0:75fc82583a41 145 , (R1 >> 8), (R1 & 0xFF), (M1), (V1) \
DiegoOstuni 0:75fc82583a41 146 , (R2 >> 8), (R2 & 0xFF), (M2), (V2) \
DiegoOstuni 0:75fc82583a41 147 , (R3 >> 8), (R3 & 0xFF), (M3), (V3) \
DiegoOstuni 0:75fc82583a41 148 , (R4 >> 8), (R4 & 0xFF), (M4), (V4) \
DiegoOstuni 0:75fc82583a41 149 , (R5 >> 8), (R5 & 0xFF), (M5), (V5) \
DiegoOstuni 0:75fc82583a41 150 , (R6 >> 8), (R6 & 0xFF), (M6), (V6) \
DiegoOstuni 0:75fc82583a41 151 , (R7 >> 8), (R7 & 0xFF), (M7), (V7) \
DiegoOstuni 0:75fc82583a41 152 , (R8 >> 8), (R8 & 0xFF), (M8), (V8) \
DiegoOstuni 0:75fc82583a41 153 , (R9 >> 8), (R9 & 0xFF), (M9), (V9) \
DiegoOstuni 0:75fc82583a41 154
DiegoOstuni 0:75fc82583a41 155 /*! Macro for Configuration Setting with eleven register-mask-value sets:
DiegoOstuni 0:75fc82583a41 156 * - Configuration ID[2], Number of Register sets to follow[1], Register[2], Mask[1], Value[1], Register[2], Mask[1], Value[1], Register[2]... */
DiegoOstuni 0:75fc82583a41 157 #define MODE_ENTRY_11_REG(MODE, R0, M0, V0, R1, M1, V1, R2, M2, V2, R3, M3, V3, R4, M4, V4, R5, M5, V5, R6, M6, V6, R7, M7, V7, R8, M8, V8, R9, M9, V9, R10, M10, V10) \
DiegoOstuni 0:75fc82583a41 158 (MODE >> 8), (MODE & 0xFF),11, (R0 >> 8), (R0 & 0xFF), (M0), (V0) \
DiegoOstuni 0:75fc82583a41 159 , (R1 >> 8), (R1 & 0xFF), (M1), (V1) \
DiegoOstuni 0:75fc82583a41 160 , (R2 >> 8), (R2 & 0xFF), (M2), (V2) \
DiegoOstuni 0:75fc82583a41 161 , (R3 >> 8), (R3 & 0xFF), (M3), (V3) \
DiegoOstuni 0:75fc82583a41 162 , (R4 >> 8), (R4 & 0xFF), (M4), (V4) \
DiegoOstuni 0:75fc82583a41 163 , (R5 >> 8), (R5 & 0xFF), (M5), (V5) \
DiegoOstuni 0:75fc82583a41 164 , (R6 >> 8), (R6 & 0xFF), (M6), (V6) \
DiegoOstuni 0:75fc82583a41 165 , (R7 >> 8), (R7 & 0xFF), (M7), (V7) \
DiegoOstuni 0:75fc82583a41 166 , (R8 >> 8), (R8 & 0xFF), (M8), (V8) \
DiegoOstuni 0:75fc82583a41 167 , (R9 >> 8), (R9 & 0xFF), (M9), (V9) \
DiegoOstuni 0:75fc82583a41 168 , (R10 >> 8), (R10 & 0xFF), (M10), (V10) \
DiegoOstuni 0:75fc82583a41 169
DiegoOstuni 0:75fc82583a41 170 /*! Macro for Configuration Setting with twelve register-mask-value sets:
DiegoOstuni 0:75fc82583a41 171 * - Configuration ID[2], Number of Register sets to follow[1], Register[2], Mask[1], Value[1], Register[2], Mask[1], Value[1], Register[2]... */
DiegoOstuni 0:75fc82583a41 172 #define MODE_ENTRY_12_REG(MODE, R0, M0, V0, R1, M1, V1, R2, M2, V2, R3, M3, V3, R4, M4, V4, R5, M5, V5, R6, M6, V6, R7, M7, V7, R8, M8, V8, R9, M9, V9, R10, M10, V10, R11, M11, V11) \
DiegoOstuni 0:75fc82583a41 173 (MODE >> 8), (MODE & 0xFF),12, (R0 >> 8), (R0 & 0xFF), (M0), (V0) \
DiegoOstuni 0:75fc82583a41 174 , (R1 >> 8), (R1 & 0xFF), (M1), (V1) \
DiegoOstuni 0:75fc82583a41 175 , (R2 >> 8), (R2 & 0xFF), (M2), (V2) \
DiegoOstuni 0:75fc82583a41 176 , (R3 >> 8), (R3 & 0xFF), (M3), (V3) \
DiegoOstuni 0:75fc82583a41 177 , (R4 >> 8), (R4 & 0xFF), (M4), (V4) \
DiegoOstuni 0:75fc82583a41 178 , (R5 >> 8), (R5 & 0xFF), (M5), (V5) \
DiegoOstuni 0:75fc82583a41 179 , (R6 >> 8), (R6 & 0xFF), (M6), (V6) \
DiegoOstuni 0:75fc82583a41 180 , (R7 >> 8), (R7 & 0xFF), (M7), (V7) \
DiegoOstuni 0:75fc82583a41 181 , (R8 >> 8), (R8 & 0xFF), (M8), (V8) \
DiegoOstuni 0:75fc82583a41 182 , (R9 >> 8), (R9 & 0xFF), (M9), (V9) \
DiegoOstuni 0:75fc82583a41 183 , (R10 >> 8), (R10 & 0xFF), (M10), (V10) \
DiegoOstuni 0:75fc82583a41 184 , (R11 >> 8), (R11 & 0xFF), (M11), (V11) \
DiegoOstuni 0:75fc82583a41 185
DiegoOstuni 0:75fc82583a41 186 /*! Macro for Configuration Setting with thirteen register-mask-value sets:
DiegoOstuni 0:75fc82583a41 187 * - Configuration ID[2], Number of Register sets to follow[1], Register[2], Mask[1], Value[1], Register[2], Mask[1], Value[1], Register[2]... */
DiegoOstuni 0:75fc82583a41 188 #define MODE_ENTRY_13_REG(MODE, R0, M0, V0, R1, M1, V1, R2, M2, V2, R3, M3, V3, R4, M4, V4, R5, M5, V5, R6, M6, V6, R7, M7, V7, R8, M8, V8, R9, M9, V9, R10, M10, V10, R11, M11, V11, R12, M12, V12) \
DiegoOstuni 0:75fc82583a41 189 (MODE >> 8), (MODE & 0xFF),13, (R0 >> 8), (R0 & 0xFF), (M0), (V0) \
DiegoOstuni 0:75fc82583a41 190 , (R1 >> 8), (R1 & 0xFF), (M1), (V1) \
DiegoOstuni 0:75fc82583a41 191 , (R2 >> 8), (R2 & 0xFF), (M2), (V2) \
DiegoOstuni 0:75fc82583a41 192 , (R3 >> 8), (R3 & 0xFF), (M3), (V3) \
DiegoOstuni 0:75fc82583a41 193 , (R4 >> 8), (R4 & 0xFF), (M4), (V4) \
DiegoOstuni 0:75fc82583a41 194 , (R5 >> 8), (R5 & 0xFF), (M5), (V5) \
DiegoOstuni 0:75fc82583a41 195 , (R6 >> 8), (R6 & 0xFF), (M6), (V6) \
DiegoOstuni 0:75fc82583a41 196 , (R7 >> 8), (R7 & 0xFF), (M7), (V7) \
DiegoOstuni 0:75fc82583a41 197 , (R8 >> 8), (R8 & 0xFF), (M8), (V8) \
DiegoOstuni 0:75fc82583a41 198 , (R9 >> 8), (R9 & 0xFF), (M9), (V9) \
DiegoOstuni 0:75fc82583a41 199 , (R10 >> 8), (R10 & 0xFF), (M10), (V10) \
DiegoOstuni 0:75fc82583a41 200 , (R11 >> 8), (R11 & 0xFF), (M11), (V11) \
DiegoOstuni 0:75fc82583a41 201 , (R12 >> 8), (R12 & 0xFF), (M12), (V12) \
DiegoOstuni 0:75fc82583a41 202 /* Setting for approximately 14%: */
DiegoOstuni 0:75fc82583a41 203 #define AM_MOD_DRIVER_LEVEL_DEFAULT 0xb9
DiegoOstuni 0:75fc82583a41 204 /*
DiegoOstuni 0:75fc82583a41 205 ******************************************************************************
DiegoOstuni 0:75fc82583a41 206 * GLOBAL DATA TYPES
DiegoOstuni 0:75fc82583a41 207 ******************************************************************************
DiegoOstuni 0:75fc82583a41 208 */
DiegoOstuni 0:75fc82583a41 209 const uint8_t rfalAnalogConfigDefaultSettings[] = {
DiegoOstuni 0:75fc82583a41 210 /****** Default Analog Configuration for Chip-Specific. ******/
DiegoOstuni 0:75fc82583a41 211 MODE_ENTRY_10_REG( RFAL_ANALOG_CONFIG_TECH_CHIP
DiegoOstuni 0:75fc82583a41 212 , ST25R3911_REG_OP_CONTROL, 0x30, 0x10 /* default to AM */
DiegoOstuni 0:75fc82583a41 213 , ST25R3911_REG_IO_CONF1, 0x06, 0x06 /* MCUCLK: HF clk off */
DiegoOstuni 0:75fc82583a41 214 , ST25R3911_REG_IO_CONF1, ST25R3911_REG_IO_CONF1_lf_clk_off, ST25R3911_REG_IO_CONF1_lf_clk_off /* MCUCLK: LF clk off */
DiegoOstuni 0:75fc82583a41 215 , ST25R3911_REG_IO_CONF2, 0x18, 0x18 /* pull downs */
DiegoOstuni 0:75fc82583a41 216 , ST25R3911_REG_RX_CONF4, ST25R3911_REG_RX_CONF4_mask_rg2_pm, 0x1<<ST25R3911_REG_RX_CONF4_shift_rg2_pm /* increase digitizer window for PM */
DiegoOstuni 0:75fc82583a41 217 , ST25R3911_REG_ANT_CAL_TARGET, 0xFF, 0x80 /* 90degrees */
DiegoOstuni 0:75fc82583a41 218 , ST25R3911_REG_ANT_CAL_CONTROL, 0xF8, 0x00 /* trim value from calibrate antenna */
DiegoOstuni 0:75fc82583a41 219 , ST25R3911_REG_AM_MOD_DEPTH_CONTROL, ST25R3911_REG_AM_MOD_DEPTH_CONTROL_am_s, ST25R3911_REG_AM_MOD_DEPTH_CONTROL_am_s /* AM modulated level is defined by RFO AM Modulated Level Def Reg, fixed setting, no automatic adjustment */
DiegoOstuni 0:75fc82583a41 220 , ST25R3911_REG_FIELD_THRESHOLD, ST25R3911_REG_FIELD_THRESHOLD_mask_trg, ST25R3911_REG_FIELD_THRESHOLD_trg_75mV
DiegoOstuni 0:75fc82583a41 221 , ST25R3911_REG_FIELD_THRESHOLD, ST25R3911_REG_FIELD_THRESHOLD_mask_rfe, ST25R3911_REG_FIELD_THRESHOLD_rfe_75mV
DiegoOstuni 0:75fc82583a41 222 )
DiegoOstuni 0:75fc82583a41 223
DiegoOstuni 0:75fc82583a41 224 /****** Default Analog Configuration for Poll NFC-A Tx. ******/
DiegoOstuni 0:75fc82583a41 225 , MODE_ENTRY_1_REG( (RFAL_ANALOG_CONFIG_POLL | RFAL_ANALOG_CONFIG_TECH_NFCA | RFAL_ANALOG_CONFIG_BITRATE_COMMON | RFAL_ANALOG_CONFIG_TX)
DiegoOstuni 0:75fc82583a41 226 , ST25R3911_REG_RFO_AM_ON_LEVEL, 0xff, 0xf0 /* Used for 848 TX: very high AM to keep wave shapes */
DiegoOstuni 0:75fc82583a41 227 )
DiegoOstuni 0:75fc82583a41 228
DiegoOstuni 0:75fc82583a41 229 , MODE_ENTRY_1_REG( (RFAL_ANALOG_CONFIG_POLL | RFAL_ANALOG_CONFIG_TECH_NFCA | RFAL_ANALOG_CONFIG_BITRATE_106 | RFAL_ANALOG_CONFIG_TX)
DiegoOstuni 0:75fc82583a41 230 , ST25R3911_REG_AUX, ST25R3911_REG_AUX_tr_am, 0x00 /* OOK */
DiegoOstuni 0:75fc82583a41 231 )
DiegoOstuni 0:75fc82583a41 232
DiegoOstuni 0:75fc82583a41 233 , MODE_ENTRY_1_REG( (RFAL_ANALOG_CONFIG_POLL | RFAL_ANALOG_CONFIG_TECH_NFCA | RFAL_ANALOG_CONFIG_BITRATE_212 | RFAL_ANALOG_CONFIG_TX)
DiegoOstuni 0:75fc82583a41 234 , ST25R3911_REG_AUX, ST25R3911_REG_AUX_tr_am, 0x00 /* OOK */
DiegoOstuni 0:75fc82583a41 235 )
DiegoOstuni 0:75fc82583a41 236
DiegoOstuni 0:75fc82583a41 237 , MODE_ENTRY_1_REG( (RFAL_ANALOG_CONFIG_POLL | RFAL_ANALOG_CONFIG_TECH_NFCA | RFAL_ANALOG_CONFIG_BITRATE_424 | RFAL_ANALOG_CONFIG_TX)
DiegoOstuni 0:75fc82583a41 238 , ST25R3911_REG_AUX, ST25R3911_REG_AUX_tr_am, 0x00 /* OOK */
DiegoOstuni 0:75fc82583a41 239 )
DiegoOstuni 0:75fc82583a41 240
DiegoOstuni 0:75fc82583a41 241 , MODE_ENTRY_2_REG( (RFAL_ANALOG_CONFIG_POLL | RFAL_ANALOG_CONFIG_TECH_NFCA | RFAL_ANALOG_CONFIG_BITRATE_848 | RFAL_ANALOG_CONFIG_TX)
DiegoOstuni 0:75fc82583a41 242 , ST25R3911_REG_AUX, ST25R3911_REG_AUX_tr_am, ST25R3911_REG_AUX_tr_am /* AM! */
DiegoOstuni 0:75fc82583a41 243 , ST25R3911_REG_RFO_AM_ON_LEVEL, 0xff, 0xf0 /* Used for 848 TX: very high AM to keep wave shapes */
DiegoOstuni 0:75fc82583a41 244 )
DiegoOstuni 0:75fc82583a41 245
DiegoOstuni 0:75fc82583a41 246 /****** Default Analog Configuration for Poll NFC-A Rx. ******/
DiegoOstuni 0:75fc82583a41 247 , MODE_ENTRY_3_REG( (RFAL_ANALOG_CONFIG_POLL | RFAL_ANALOG_CONFIG_TECH_NFCA | RFAL_ANALOG_CONFIG_BITRATE_COMMON | RFAL_ANALOG_CONFIG_RX)
DiegoOstuni 0:75fc82583a41 248 , ST25R3911_REG_RX_CONF3, 0xff, 0x18
DiegoOstuni 0:75fc82583a41 249 , ST25R3911_REG_RX_CONF4, ST25R3911_REG_RX_CONF4_mask_rg2_am, 0x2<<ST25R3911_REG_RX_CONF4_shift_rg2_am /* increase digitizer window for AM */
DiegoOstuni 0:75fc82583a41 250 , ST25R3911_REG_AUX, ST25R3911_REG_AUX_rx_tol, 0x00 /* rx_tol Off */
DiegoOstuni 0:75fc82583a41 251 )
DiegoOstuni 0:75fc82583a41 252
DiegoOstuni 0:75fc82583a41 253 , MODE_ENTRY_1_REG( (RFAL_ANALOG_CONFIG_POLL | RFAL_ANALOG_CONFIG_TECH_NFCA | RFAL_ANALOG_CONFIG_BITRATE_106 | RFAL_ANALOG_CONFIG_RX)
DiegoOstuni 0:75fc82583a41 254 , ST25R3911_REG_RX_CONF1, 0x7f, 0x00
DiegoOstuni 0:75fc82583a41 255 )
DiegoOstuni 0:75fc82583a41 256
DiegoOstuni 0:75fc82583a41 257 , MODE_ENTRY_1_REG( (RFAL_ANALOG_CONFIG_POLL | RFAL_ANALOG_CONFIG_TECH_NFCA | RFAL_ANALOG_CONFIG_BITRATE_212 | RFAL_ANALOG_CONFIG_RX)
DiegoOstuni 0:75fc82583a41 258 , ST25R3911_REG_RX_CONF1, 0x7f, 0x04
DiegoOstuni 0:75fc82583a41 259 )
DiegoOstuni 0:75fc82583a41 260
DiegoOstuni 0:75fc82583a41 261 , MODE_ENTRY_1_REG( (RFAL_ANALOG_CONFIG_POLL | RFAL_ANALOG_CONFIG_TECH_NFCA | RFAL_ANALOG_CONFIG_BITRATE_424 | RFAL_ANALOG_CONFIG_RX)
DiegoOstuni 0:75fc82583a41 262 , ST25R3911_REG_RX_CONF1, 0x7f, 0x22
DiegoOstuni 0:75fc82583a41 263 )
DiegoOstuni 0:75fc82583a41 264
DiegoOstuni 0:75fc82583a41 265 , MODE_ENTRY_1_REG( (RFAL_ANALOG_CONFIG_POLL | RFAL_ANALOG_CONFIG_TECH_NFCA | RFAL_ANALOG_CONFIG_BITRATE_848 | RFAL_ANALOG_CONFIG_RX)
DiegoOstuni 0:75fc82583a41 266 , ST25R3911_REG_RX_CONF1, 0x7f, 0x22
DiegoOstuni 0:75fc82583a41 267 )
DiegoOstuni 0:75fc82583a41 268
DiegoOstuni 0:75fc82583a41 269 /****** Default Analog Configuration for Poll NFC-B Tx. ******/
DiegoOstuni 0:75fc82583a41 270 , MODE_ENTRY_2_REG( (RFAL_ANALOG_CONFIG_POLL | RFAL_ANALOG_CONFIG_TECH_NFCB | RFAL_ANALOG_CONFIG_BITRATE_COMMON | RFAL_ANALOG_CONFIG_TX)
DiegoOstuni 0:75fc82583a41 271 , ST25R3911_REG_AUX, ST25R3911_REG_AUX_tr_am, ST25R3911_REG_AUX_tr_am /* AM */
DiegoOstuni 0:75fc82583a41 272 , ST25R3911_REG_RFO_AM_ON_LEVEL, 0xff, AM_MOD_DRIVER_LEVEL_DEFAULT /* Fixed driver for AM level: ~14% */
DiegoOstuni 0:75fc82583a41 273 )
DiegoOstuni 0:75fc82583a41 274
DiegoOstuni 0:75fc82583a41 275 /****** Default Analog Configuration for Poll NFC-B Rx. ******/
DiegoOstuni 0:75fc82583a41 276 , MODE_ENTRY_3_REG( (RFAL_ANALOG_CONFIG_POLL | RFAL_ANALOG_CONFIG_TECH_NFCB | RFAL_ANALOG_CONFIG_BITRATE_COMMON | RFAL_ANALOG_CONFIG_RX)
DiegoOstuni 0:75fc82583a41 277 , ST25R3911_REG_RX_CONF3, 0xff, 0x18
DiegoOstuni 0:75fc82583a41 278 , ST25R3911_REG_RX_CONF4, ST25R3911_REG_RX_CONF4_mask_rg2_am, 0x1<<ST25R3911_REG_RX_CONF4_shift_rg2_am /* increase digitizer window for AM */
DiegoOstuni 0:75fc82583a41 279 , ST25R3911_REG_AUX, ST25R3911_REG_AUX_rx_tol, ST25R3911_REG_AUX_rx_tol /* rx_tol On as default */
DiegoOstuni 0:75fc82583a41 280 )
DiegoOstuni 0:75fc82583a41 281
DiegoOstuni 0:75fc82583a41 282 , MODE_ENTRY_1_REG( (RFAL_ANALOG_CONFIG_POLL | RFAL_ANALOG_CONFIG_TECH_NFCB | RFAL_ANALOG_CONFIG_BITRATE_106 | RFAL_ANALOG_CONFIG_RX)
DiegoOstuni 0:75fc82583a41 283 , ST25R3911_REG_RX_CONF1, 0x7f, 0x04
DiegoOstuni 0:75fc82583a41 284 )
DiegoOstuni 0:75fc82583a41 285
DiegoOstuni 0:75fc82583a41 286 , MODE_ENTRY_1_REG( (RFAL_ANALOG_CONFIG_POLL | RFAL_ANALOG_CONFIG_TECH_NFCB | RFAL_ANALOG_CONFIG_BITRATE_212 | RFAL_ANALOG_CONFIG_RX)
DiegoOstuni 0:75fc82583a41 287 , ST25R3911_REG_RX_CONF1, 0x7f, 0x04
DiegoOstuni 0:75fc82583a41 288 )
DiegoOstuni 0:75fc82583a41 289
DiegoOstuni 0:75fc82583a41 290 , MODE_ENTRY_1_REG( (RFAL_ANALOG_CONFIG_POLL | RFAL_ANALOG_CONFIG_TECH_NFCB | RFAL_ANALOG_CONFIG_BITRATE_424 | RFAL_ANALOG_CONFIG_RX)
DiegoOstuni 0:75fc82583a41 291 , ST25R3911_REG_RX_CONF1, 0x7f, 0x22
DiegoOstuni 0:75fc82583a41 292 )
DiegoOstuni 0:75fc82583a41 293
DiegoOstuni 0:75fc82583a41 294 , MODE_ENTRY_1_REG( (RFAL_ANALOG_CONFIG_POLL | RFAL_ANALOG_CONFIG_TECH_NFCB | RFAL_ANALOG_CONFIG_BITRATE_848 | RFAL_ANALOG_CONFIG_RX)
DiegoOstuni 0:75fc82583a41 295 , ST25R3911_REG_RX_CONF1, 0x7f, 0x22
DiegoOstuni 0:75fc82583a41 296 )
DiegoOstuni 0:75fc82583a41 297
DiegoOstuni 0:75fc82583a41 298 , MODE_ENTRY_1_REG( (RFAL_ANALOG_CONFIG_POLL | RFAL_ANALOG_CONFIG_TECH_NFCB | RFAL_ANALOG_CONFIG_BITRATE_1695 | RFAL_ANALOG_CONFIG_RX)
DiegoOstuni 0:75fc82583a41 299 , ST25R3911_REG_RX_CONF1, 0x7f, 0x6c
DiegoOstuni 0:75fc82583a41 300 )
DiegoOstuni 0:75fc82583a41 301
DiegoOstuni 0:75fc82583a41 302 , MODE_ENTRY_1_REG( (RFAL_ANALOG_CONFIG_POLL | RFAL_ANALOG_CONFIG_TECH_NFCB | RFAL_ANALOG_CONFIG_BITRATE_3390 | RFAL_ANALOG_CONFIG_RX)
DiegoOstuni 0:75fc82583a41 303 , ST25R3911_REG_RX_CONF1, 0x7f, 0x6c
DiegoOstuni 0:75fc82583a41 304 )
DiegoOstuni 0:75fc82583a41 305
DiegoOstuni 0:75fc82583a41 306 /****** Default Analog Configuration for Poll NFC-F Tx. ******/
DiegoOstuni 0:75fc82583a41 307 , MODE_ENTRY_2_REG( (RFAL_ANALOG_CONFIG_POLL | RFAL_ANALOG_CONFIG_TECH_NFCF | RFAL_ANALOG_CONFIG_BITRATE_COMMON | RFAL_ANALOG_CONFIG_TX)
DiegoOstuni 0:75fc82583a41 308 , ST25R3911_REG_AUX, ST25R3911_REG_AUX_tr_am, ST25R3911_REG_AUX_tr_am /* AM */
DiegoOstuni 0:75fc82583a41 309 , ST25R3911_REG_RFO_AM_ON_LEVEL, 0xff, AM_MOD_DRIVER_LEVEL_DEFAULT /* Fixed driver for AM level: ~14% */
DiegoOstuni 0:75fc82583a41 310 )
DiegoOstuni 0:75fc82583a41 311
DiegoOstuni 0:75fc82583a41 312 /****** Default Analog Configuration for Poll NFC-F Common bitrate Rx. ******/
DiegoOstuni 0:75fc82583a41 313 , MODE_ENTRY_3_REG( (RFAL_ANALOG_CONFIG_POLL | RFAL_ANALOG_CONFIG_TECH_NFCF | RFAL_ANALOG_CONFIG_BITRATE_COMMON | RFAL_ANALOG_CONFIG_RX)
DiegoOstuni 0:75fc82583a41 314 , ST25R3911_REG_RX_CONF3, 0xff, 0x18
DiegoOstuni 0:75fc82583a41 315 , ST25R3911_REG_RX_CONF4, ST25R3911_REG_RX_CONF4_mask_rg2_am, 0x1<<ST25R3911_REG_RX_CONF4_shift_rg2_am /* increase digitizer window for AM */
DiegoOstuni 0:75fc82583a41 316 , ST25R3911_REG_AUX, ST25R3911_REG_AUX_rx_tol, ST25R3911_REG_AUX_rx_tol /* rx_tol On as default */
DiegoOstuni 0:75fc82583a41 317 )
DiegoOstuni 0:75fc82583a41 318
DiegoOstuni 0:75fc82583a41 319 , MODE_ENTRY_1_REG( (RFAL_ANALOG_CONFIG_POLL | RFAL_ANALOG_CONFIG_TECH_NFCF | RFAL_ANALOG_CONFIG_BITRATE_212 | RFAL_ANALOG_CONFIG_RX)
DiegoOstuni 0:75fc82583a41 320 , ST25R3911_REG_RX_CONF1, 0x7f, 0x13 /* dev. from data sheet: lp 300kKz */
DiegoOstuni 0:75fc82583a41 321 )
DiegoOstuni 0:75fc82583a41 322
DiegoOstuni 0:75fc82583a41 323 , MODE_ENTRY_1_REG( (RFAL_ANALOG_CONFIG_POLL | RFAL_ANALOG_CONFIG_TECH_NFCF | RFAL_ANALOG_CONFIG_BITRATE_424 | RFAL_ANALOG_CONFIG_RX)
DiegoOstuni 0:75fc82583a41 324 , ST25R3911_REG_RX_CONF1, 0x7f, 0x0b /* dev. from data sheet: lp 600kHz */
DiegoOstuni 0:75fc82583a41 325 )
DiegoOstuni 0:75fc82583a41 326
DiegoOstuni 0:75fc82583a41 327 /****** Default Analog Configuration for Poll NFC-V Common bitrate Tx ******/
DiegoOstuni 0:75fc82583a41 328 , MODE_ENTRY_1_REG( (RFAL_ANALOG_CONFIG_POLL | RFAL_ANALOG_CONFIG_TECH_NFCV | RFAL_ANALOG_CONFIG_BITRATE_COMMON | RFAL_ANALOG_CONFIG_TX)
DiegoOstuni 0:75fc82583a41 329 , ST25R3911_REG_AUX, ST25R3911_REG_AUX_tr_am, 0x00
DiegoOstuni 0:75fc82583a41 330 )
DiegoOstuni 0:75fc82583a41 331
DiegoOstuni 0:75fc82583a41 332 /****** Default Analog Configuration for Poll NFC-V Common bitrate Rx ******/
DiegoOstuni 0:75fc82583a41 333 , MODE_ENTRY_4_REG( (RFAL_ANALOG_CONFIG_POLL | RFAL_ANALOG_CONFIG_TECH_NFCV | RFAL_ANALOG_CONFIG_BITRATE_COMMON | RFAL_ANALOG_CONFIG_RX)
DiegoOstuni 0:75fc82583a41 334 , ST25R3911_REG_RX_CONF1, 0x7f, 0x0c /* use filter settings from table 9: "Recommended for 424/484 kHz sub-carrier" */
DiegoOstuni 0:75fc82583a41 335 , ST25R3911_REG_RX_CONF3, 0xff, 0x18
DiegoOstuni 0:75fc82583a41 336 , ST25R3911_REG_RX_CONF4, ST25R3911_REG_RX_CONF4_mask_rg2_am, 0x1<<ST25R3911_REG_RX_CONF4_shift_rg2_am /* increase digitizer window for AM */
DiegoOstuni 0:75fc82583a41 337 , ST25R3911_REG_AUX, ST25R3911_REG_AUX_rx_tol, ST25R3911_REG_AUX_rx_tol /* rx_tol On as default */
DiegoOstuni 0:75fc82583a41 338 )
DiegoOstuni 0:75fc82583a41 339
DiegoOstuni 0:75fc82583a41 340 /****** Default Analog Configuration for Poll AP2P Common bitrate Tx. ******/
DiegoOstuni 0:75fc82583a41 341 , MODE_ENTRY_1_REG( (RFAL_ANALOG_CONFIG_POLL | RFAL_ANALOG_CONFIG_TECH_AP2P | RFAL_ANALOG_CONFIG_BITRATE_COMMON | RFAL_ANALOG_CONFIG_TX)
DiegoOstuni 0:75fc82583a41 342 , ST25R3911_REG_RFO_AM_ON_LEVEL, 0xff, AM_MOD_DRIVER_LEVEL_DEFAULT /* Fixed driver for AM level: ~14% */
DiegoOstuni 0:75fc82583a41 343 )
DiegoOstuni 0:75fc82583a41 344
DiegoOstuni 0:75fc82583a41 345 , MODE_ENTRY_1_REG( (RFAL_ANALOG_CONFIG_POLL | RFAL_ANALOG_CONFIG_TECH_AP2P | RFAL_ANALOG_CONFIG_BITRATE_106 | RFAL_ANALOG_CONFIG_TX)
DiegoOstuni 0:75fc82583a41 346 , ST25R3911_REG_AUX, ST25R3911_REG_AUX_tr_am, 0x00 /* OOK */
DiegoOstuni 0:75fc82583a41 347 )
DiegoOstuni 0:75fc82583a41 348
DiegoOstuni 0:75fc82583a41 349 , MODE_ENTRY_2_REG( (RFAL_ANALOG_CONFIG_POLL | RFAL_ANALOG_CONFIG_TECH_AP2P | RFAL_ANALOG_CONFIG_BITRATE_212 | RFAL_ANALOG_CONFIG_TX)
DiegoOstuni 0:75fc82583a41 350 , ST25R3911_REG_AUX, ST25R3911_REG_AUX_tr_am, ST25R3911_REG_AUX_tr_am /* AM */
DiegoOstuni 0:75fc82583a41 351 , ST25R3911_REG_RFO_AM_ON_LEVEL, 0xff, AM_MOD_DRIVER_LEVEL_DEFAULT /* Fixed driver for AM level: ~14% */
DiegoOstuni 0:75fc82583a41 352 )
DiegoOstuni 0:75fc82583a41 353
DiegoOstuni 0:75fc82583a41 354 , MODE_ENTRY_2_REG( (RFAL_ANALOG_CONFIG_POLL | RFAL_ANALOG_CONFIG_TECH_AP2P | RFAL_ANALOG_CONFIG_BITRATE_424 | RFAL_ANALOG_CONFIG_TX)
DiegoOstuni 0:75fc82583a41 355 , ST25R3911_REG_AUX, ST25R3911_REG_AUX_tr_am, ST25R3911_REG_AUX_tr_am /* AM */
DiegoOstuni 0:75fc82583a41 356 , ST25R3911_REG_RFO_AM_ON_LEVEL, 0xff, AM_MOD_DRIVER_LEVEL_DEFAULT /* Fixed driver for AM level: ~14% */
DiegoOstuni 0:75fc82583a41 357 )
DiegoOstuni 0:75fc82583a41 358
DiegoOstuni 0:75fc82583a41 359 /****** Default Analog Configuration for Poll AP2P Common bitrate Rx. ******/
DiegoOstuni 0:75fc82583a41 360 , MODE_ENTRY_4_REG( (RFAL_ANALOG_CONFIG_POLL | RFAL_ANALOG_CONFIG_TECH_AP2P | RFAL_ANALOG_CONFIG_BITRATE_COMMON | RFAL_ANALOG_CONFIG_RX)
DiegoOstuni 0:75fc82583a41 361 , ST25R3911_REG_RX_CONF1, 0x7f, 0x45
DiegoOstuni 0:75fc82583a41 362 , ST25R3911_REG_RX_CONF3, (ST25R3911_REG_RX_CONF3_lim | ST25R3911_REG_RX_CONF3_rg_nfc), (ST25R3911_REG_RX_CONF3_lim | ST25R3911_REG_RX_CONF3_rg_nfc)
DiegoOstuni 0:75fc82583a41 363 , ST25R3911_REG_AUX, ST25R3911_REG_AUX_rx_tol, ST25R3911_REG_AUX_rx_tol /* rx_tol On as default */
DiegoOstuni 0:75fc82583a41 364 , ST25R3911_REG_RX_CONF4, ST25R3911_REG_RX_CONF4_mask_rg2_am, 0x1<<ST25R3911_REG_RX_CONF4_shift_rg2_am /* increase digitizer window for AM */
DiegoOstuni 0:75fc82583a41 365 )
DiegoOstuni 0:75fc82583a41 366
DiegoOstuni 0:75fc82583a41 367 , MODE_ENTRY_1_REG( (RFAL_ANALOG_CONFIG_POLL | RFAL_ANALOG_CONFIG_TECH_AP2P | RFAL_ANALOG_CONFIG_BITRATE_106 | RFAL_ANALOG_CONFIG_RX)
DiegoOstuni 0:75fc82583a41 368 , ST25R3911_REG_RX_CONF3, ST25R3911_REG_RX_CONF3_mask_rg1_am, 0xc0
DiegoOstuni 0:75fc82583a41 369 )
DiegoOstuni 0:75fc82583a41 370
DiegoOstuni 0:75fc82583a41 371 , MODE_ENTRY_1_REG( (RFAL_ANALOG_CONFIG_POLL | RFAL_ANALOG_CONFIG_TECH_AP2P | RFAL_ANALOG_CONFIG_BITRATE_212 | RFAL_ANALOG_CONFIG_RX)
DiegoOstuni 0:75fc82583a41 372 , ST25R3911_REG_RX_CONF3, ST25R3911_REG_RX_CONF3_mask_rg1_am, 0x00
DiegoOstuni 0:75fc82583a41 373 )
DiegoOstuni 0:75fc82583a41 374
DiegoOstuni 0:75fc82583a41 375 , MODE_ENTRY_1_REG( (RFAL_ANALOG_CONFIG_POLL | RFAL_ANALOG_CONFIG_TECH_AP2P | RFAL_ANALOG_CONFIG_BITRATE_424 | RFAL_ANALOG_CONFIG_RX)
DiegoOstuni 0:75fc82583a41 376 , ST25R3911_REG_RX_CONF3, ST25R3911_REG_RX_CONF3_mask_rg1_am, 0x00
DiegoOstuni 0:75fc82583a41 377 )
DiegoOstuni 0:75fc82583a41 378
DiegoOstuni 0:75fc82583a41 379 /****** Default Analog Configuration for Listen AP2P Common bitrate Tx. ******/
DiegoOstuni 0:75fc82583a41 380 , MODE_ENTRY_1_REG( (RFAL_ANALOG_CONFIG_LISTEN | RFAL_ANALOG_CONFIG_TECH_AP2P | RFAL_ANALOG_CONFIG_BITRATE_COMMON | RFAL_ANALOG_CONFIG_TX)
DiegoOstuni 0:75fc82583a41 381 , ST25R3911_REG_RFO_AM_ON_LEVEL, 0xff, AM_MOD_DRIVER_LEVEL_DEFAULT /* Fixed driver for AM level: ~14% */
DiegoOstuni 0:75fc82583a41 382 )
DiegoOstuni 0:75fc82583a41 383
DiegoOstuni 0:75fc82583a41 384 , MODE_ENTRY_1_REG( (RFAL_ANALOG_CONFIG_LISTEN | RFAL_ANALOG_CONFIG_TECH_AP2P | RFAL_ANALOG_CONFIG_BITRATE_106 | RFAL_ANALOG_CONFIG_TX)
DiegoOstuni 0:75fc82583a41 385 , ST25R3911_REG_AUX, ST25R3911_REG_AUX_tr_am, 0x00 /* OOK */
DiegoOstuni 0:75fc82583a41 386 )
DiegoOstuni 0:75fc82583a41 387
DiegoOstuni 0:75fc82583a41 388 , MODE_ENTRY_1_REG( (RFAL_ANALOG_CONFIG_LISTEN | RFAL_ANALOG_CONFIG_TECH_AP2P | RFAL_ANALOG_CONFIG_BITRATE_212 | RFAL_ANALOG_CONFIG_TX)
DiegoOstuni 0:75fc82583a41 389 , ST25R3911_REG_AUX, ST25R3911_REG_AUX_tr_am, ST25R3911_REG_AUX_tr_am /* AM */
DiegoOstuni 0:75fc82583a41 390 )
DiegoOstuni 0:75fc82583a41 391
DiegoOstuni 0:75fc82583a41 392 , MODE_ENTRY_1_REG( (RFAL_ANALOG_CONFIG_LISTEN | RFAL_ANALOG_CONFIG_TECH_AP2P | RFAL_ANALOG_CONFIG_BITRATE_424 | RFAL_ANALOG_CONFIG_TX)
DiegoOstuni 0:75fc82583a41 393 , ST25R3911_REG_AUX, ST25R3911_REG_AUX_tr_am, ST25R3911_REG_AUX_tr_am /* AM */
DiegoOstuni 0:75fc82583a41 394 )
DiegoOstuni 0:75fc82583a41 395
DiegoOstuni 0:75fc82583a41 396 /****** Default Analog Configuration for Listen AP2P Common bitrate Rx. ******/
DiegoOstuni 0:75fc82583a41 397 , MODE_ENTRY_3_REG( (RFAL_ANALOG_CONFIG_LISTEN | RFAL_ANALOG_CONFIG_TECH_AP2P | RFAL_ANALOG_CONFIG_BITRATE_COMMON | RFAL_ANALOG_CONFIG_RX)
DiegoOstuni 0:75fc82583a41 398 , ST25R3911_REG_RX_CONF1, 0x7f, 0x45
DiegoOstuni 0:75fc82583a41 399 , ST25R3911_REG_RX_CONF3, (ST25R3911_REG_RX_CONF3_lim | ST25R3911_REG_RX_CONF3_rg_nfc), (ST25R3911_REG_RX_CONF3_lim | ST25R3911_REG_RX_CONF3_rg_nfc)
DiegoOstuni 0:75fc82583a41 400 , ST25R3911_REG_RX_CONF4, ST25R3911_REG_RX_CONF4_mask_rg2_am, 0x1<<ST25R3911_REG_RX_CONF4_shift_rg2_am /* increase digitizer window for AM */
DiegoOstuni 0:75fc82583a41 401 )
DiegoOstuni 0:75fc82583a41 402
DiegoOstuni 0:75fc82583a41 403 , MODE_ENTRY_1_REG( (RFAL_ANALOG_CONFIG_LISTEN | RFAL_ANALOG_CONFIG_TECH_AP2P | RFAL_ANALOG_CONFIG_BITRATE_106 | RFAL_ANALOG_CONFIG_RX)
DiegoOstuni 0:75fc82583a41 404 , ST25R3911_REG_RX_CONF3, ST25R3911_REG_RX_CONF3_mask_rg1_am, 0xc0
DiegoOstuni 0:75fc82583a41 405 )
DiegoOstuni 0:75fc82583a41 406
DiegoOstuni 0:75fc82583a41 407 , MODE_ENTRY_1_REG( (RFAL_ANALOG_CONFIG_LISTEN | RFAL_ANALOG_CONFIG_TECH_AP2P | RFAL_ANALOG_CONFIG_BITRATE_212 | RFAL_ANALOG_CONFIG_RX)
DiegoOstuni 0:75fc82583a41 408 , ST25R3911_REG_RX_CONF3, ST25R3911_REG_RX_CONF3_mask_rg1_am, 0x00
DiegoOstuni 0:75fc82583a41 409 )
DiegoOstuni 0:75fc82583a41 410
DiegoOstuni 0:75fc82583a41 411 , MODE_ENTRY_1_REG( (RFAL_ANALOG_CONFIG_LISTEN | RFAL_ANALOG_CONFIG_TECH_AP2P | RFAL_ANALOG_CONFIG_BITRATE_424 | RFAL_ANALOG_CONFIG_RX)
DiegoOstuni 0:75fc82583a41 412 , ST25R3911_REG_RX_CONF3, ST25R3911_REG_RX_CONF3_mask_rg1_am, 0x00
DiegoOstuni 0:75fc82583a41 413 )
DiegoOstuni 0:75fc82583a41 414 };
DiegoOstuni 0:75fc82583a41 415
DiegoOstuni 0:75fc82583a41 416 #endif /* ST25R3911_ANALOGCONFIG_H */