David Saul
R1 code for micro:bit based train controller code, requires second micro:bit running rx code to operate - see https://meanderingpi.wordpress.com/ for more information
Fork of
mbed-dev-bin
by 
Lancaster University
Diff: TARGET_NRF51_MICROBIT/nrf51.h
- Revision:
- 1:a7c51b5e0534
- Parent:
- 0:e1a608bb55e8
- Child:
- 2:e32c8485c88f
--- a/TARGET_NRF51_MICROBIT/nrf51.h Thu Apr 07 18:33:58 2016 +0100
+++ b/TARGET_NRF51_MICROBIT/nrf51.h Thu Apr 07 17:50:29 2016 +0000
@@ -1,57 +1,35 @@
-
-/****************************************************************************************************//**
- * @file nRF51.h
- *
- * @brief CMSIS Cortex-M0 Peripheral Access Layer Header File for
- * nRF51 from Nordic Semiconductor.
- *
- * @version V522
- * @date 31. October 2014
- *
- * @note Generated with SVDConv V2.81d
- * from CMSIS SVD File 'nRF51.xml' Version 522,
- *
- * @par Copyright (c) 2013, Nordic Semiconductor ASA
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * * Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * * Neither the name of Nordic Semiconductor ASA nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *
- *******************************************************************************************************/
-
-
-
-/** @addtogroup Nordic Semiconductor
- * @{
- */
-
-/** @addtogroup nRF51
- * @{
- */
-
+/*
+ * Copyright (c) Nordic Semiconductor ASA
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * 3. Neither the name of Nordic Semiconductor ASA nor the names of other
+ * contributors to this software may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
#ifndef NRF51_H
#define NRF51_H
@@ -71,7 +49,7 @@
DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
SysTick_IRQn = -1, /*!< 15 System Tick Timer */
-/* ---------------------- nRF51 Specific Interrupt Numbers ---------------------- */
+/* ---------------------- nrf51 Specific Interrupt Numbers ---------------------- */
POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */
RADIO_IRQn = 1, /*!< 1 RADIO */
UART0_IRQn = 2, /*!< 2 UART0 */
@@ -117,7 +95,8 @@
/** @} */ /* End of group Configuration_of_CMSIS */
#include "core_cm0.h" /*!< Cortex-M0 processor and core peripherals */
-#include "system_nrf51.h" /*!< nRF51 System */
+#include "system_nrf51.h" /*!< nrf51 System */
+
/* ================================================================================ */
/* ================ Device Specific Peripheral Section ================ */
@@ -183,15 +162,6 @@
__IO uint32_t TEP; /*!< Channel task end-point. */
} PPI_CH_Type;
-typedef struct {
- __I uint32_t PART; /*!< Part code */
- __I uint32_t VARIANT; /*!< Part variant */
- __I uint32_t PACKAGE; /*!< Package option */
- __I uint32_t RAM; /*!< RAM variant */
- __I uint32_t FLASH; /*!< Flash variant */
- __I uint32_t RESERVED[3]; /*!< Reserved */
-} FICR_INFO_Type;
-
/* ================================================================================ */
/* ================ POWER ================ */
@@ -301,27 +271,6 @@
/* ================================================================================ */
-/* ================ PU ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief Patch unit. (PU)
- */
-
-typedef struct { /*!< PU Structure */
- __I uint32_t RESERVED0[448];
- __IO uint32_t REPLACEADDR[8]; /*!< Address of first instruction to replace. */
- __I uint32_t RESERVED1[24];
- __IO uint32_t PATCHADDR[8]; /*!< Relative address of patch instructions. */
- __I uint32_t RESERVED2[24];
- __IO uint32_t PATCHEN; /*!< Patch enable register. */
- __IO uint32_t PATCHENSET; /*!< Patch enable register. */
- __IO uint32_t PATCHENCLR; /*!< Patch disable register. */
-} NRF_PU_Type;
-
-
-/* ================================================================================ */
/* ================ AMLI ================ */
/* ================================================================================ */
@@ -366,7 +315,7 @@
__IO uint32_t EVENTS_RSSIEND; /*!< Sampling of the receive signal strength complete. A new RSSI
sample is ready for readout at the RSSISAMPLE register. */
__I uint32_t RESERVED1[2];
- __IO uint32_t EVENTS_BCMATCH; /*!< Bit counter reached bit count value specified in BC register. */
+ __IO uint32_t EVENTS_BCMATCH; /*!< Bit counter reached bit count value specified in BCC register. */
__I uint32_t RESERVED2[53];
__IO uint32_t SHORTS; /*!< Shortcuts for the radio. */
__I uint32_t RESERVED3[64];
@@ -374,11 +323,11 @@
__IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
__I uint32_t RESERVED4[61];
__I uint32_t CRCSTATUS; /*!< CRC status of received packet. */
- __I uint32_t CD; /*!< Carrier detect. */
+ __I uint32_t RESERVED5;
__I uint32_t RXMATCH; /*!< Received address. */
__I uint32_t RXCRC; /*!< Received CRC. */
__I uint32_t DAI; /*!< Device address match index. */
- __I uint32_t RESERVED5[60];
+ __I uint32_t RESERVED6[60];
__IO uint32_t PACKETPTR; /*!< Packet pointer. Decision point: START task. */
__IO uint32_t FREQUENCY; /*!< Frequency. */
__IO uint32_t TXPOWER; /*!< Output power. */
@@ -397,22 +346,22 @@
__IO uint32_t TEST; /*!< Test features enable register. */
__IO uint32_t TIFS; /*!< Inter Frame Spacing in microseconds. */
__I uint32_t RSSISAMPLE; /*!< RSSI sample. */
- __I uint32_t RESERVED6;
+ __I uint32_t RESERVED7;
__I uint32_t STATE; /*!< Current radio state. */
__IO uint32_t DATAWHITEIV; /*!< Data whitening initial value. */
- __I uint32_t RESERVED7[2];
+ __I uint32_t RESERVED8[2];
__IO uint32_t BCC; /*!< Bit counter compare. */
- __I uint32_t RESERVED8[39];
+ __I uint32_t RESERVED9[39];
__IO uint32_t DAB[8]; /*!< Device address base segment. */
__IO uint32_t DAP[8]; /*!< Device address prefix. */
__IO uint32_t DACNF; /*!< Device address match configuration. */
- __I uint32_t RESERVED9[56];
+ __I uint32_t RESERVED10[56];
__IO uint32_t OVERRIDE0; /*!< Trim value override register 0. */
__IO uint32_t OVERRIDE1; /*!< Trim value override register 1. */
__IO uint32_t OVERRIDE2; /*!< Trim value override register 2. */
__IO uint32_t OVERRIDE3; /*!< Trim value override register 3. */
__IO uint32_t OVERRIDE4; /*!< Trim value override register 4. */
- __I uint32_t RESERVED10[561];
+ __I uint32_t RESERVED11[561];
__IO uint32_t POWER; /*!< Peripheral power control. */
} NRF_RADIO_Type;
@@ -571,39 +520,41 @@
__O uint32_t TASKS_RELEASE; /*!< Release SPI semaphore. */
__I uint32_t RESERVED1[54];
__IO uint32_t EVENTS_END; /*!< Granted transaction completed. */
- __I uint32_t RESERVED2[8];
+ __I uint32_t RESERVED2[2];
+ __IO uint32_t EVENTS_ENDRX; /*!< End of RXD buffer reached */
+ __I uint32_t RESERVED3[5];
__IO uint32_t EVENTS_ACQUIRED; /*!< Semaphore acquired. */
- __I uint32_t RESERVED3[53];
+ __I uint32_t RESERVED4[53];
__IO uint32_t SHORTS; /*!< Shortcuts for SPIS. */
- __I uint32_t RESERVED4[64];
+ __I uint32_t RESERVED5[64];
__IO uint32_t INTENSET; /*!< Interrupt enable set register. */
__IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
- __I uint32_t RESERVED5[61];
+ __I uint32_t RESERVED6[61];
__I uint32_t SEMSTAT; /*!< Semaphore status. */
- __I uint32_t RESERVED6[15];
+ __I uint32_t RESERVED7[15];
__IO uint32_t STATUS; /*!< Status from last transaction. */
- __I uint32_t RESERVED7[47];
+ __I uint32_t RESERVED8[47];
__IO uint32_t ENABLE; /*!< Enable SPIS. */
- __I uint32_t RESERVED8;
+ __I uint32_t RESERVED9;
__IO uint32_t PSELSCK; /*!< Pin select for SCK. */
__IO uint32_t PSELMISO; /*!< Pin select for MISO. */
__IO uint32_t PSELMOSI; /*!< Pin select for MOSI. */
__IO uint32_t PSELCSN; /*!< Pin select for CSN. */
- __I uint32_t RESERVED9[7];
+ __I uint32_t RESERVED10[7];
__IO uint32_t RXDPTR; /*!< RX data pointer. */
__IO uint32_t MAXRX; /*!< Maximum number of bytes in the receive buffer. */
__I uint32_t AMOUNTRX; /*!< Number of bytes received in last granted transaction. */
- __I uint32_t RESERVED10;
+ __I uint32_t RESERVED11;
__IO uint32_t TXDPTR; /*!< TX data pointer. */
__IO uint32_t MAXTX; /*!< Maximum number of bytes in the transmit buffer. */
__I uint32_t AMOUNTTX; /*!< Number of bytes transmitted in last granted transaction. */
- __I uint32_t RESERVED11;
+ __I uint32_t RESERVED12;
__IO uint32_t CONFIG; /*!< Configuration register. */
- __I uint32_t RESERVED12;
+ __I uint32_t RESERVED13;
__IO uint32_t DEF; /*!< Default character. */
- __I uint32_t RESERVED13[24];
+ __I uint32_t RESERVED14[24];
__IO uint32_t ORC; /*!< Over-read character. */
- __I uint32_t RESERVED14[654];
+ __I uint32_t RESERVED15[654];
__IO uint32_t POWER; /*!< Peripheral power control. */
} NRF_SPIS_Type;
@@ -628,35 +579,28 @@
__IO uint32_t EVENTS_STOPPED; /*!< SPI transaction has stopped. */
__I uint32_t RESERVED3[2];
__IO uint32_t EVENTS_ENDRX; /*!< End of RXD buffer reached. */
- __I uint32_t RESERVED4;
- __IO uint32_t EVENTS_END; /*!< End of RXD buffer and TXD buffer reached. */
- __I uint32_t RESERVED5;
+ __I uint32_t RESERVED4[3];
__IO uint32_t EVENTS_ENDTX; /*!< End of TXD buffer reached. */
- __I uint32_t RESERVED6[10];
+ __I uint32_t RESERVED5[10];
__IO uint32_t EVENTS_STARTED; /*!< Transaction started. */
- __I uint32_t RESERVED7[44];
- __IO uint32_t SHORTS; /*!< Shortcuts for SPIM. */
- __I uint32_t RESERVED8[64];
+ __I uint32_t RESERVED6[109];
__IO uint32_t INTENSET; /*!< Interrupt enable set register. */
__IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
- __I uint32_t RESERVED9[125];
+ __I uint32_t RESERVED7[125];
__IO uint32_t ENABLE; /*!< Enable SPIM. */
- __I uint32_t RESERVED10;
+ __I uint32_t RESERVED8;
SPIM_PSEL_Type PSEL; /*!< Pin select configuration. */
- __I uint32_t RESERVED11;
- __I uint32_t RXDDATA; /*!< RXD register. */
- __IO uint32_t TXDDATA; /*!< TXD register. */
- __I uint32_t RESERVED12;
+ __I uint32_t RESERVED9[4];
__IO uint32_t FREQUENCY; /*!< SPI frequency. */
- __I uint32_t RESERVED13[3];
+ __I uint32_t RESERVED10[3];
SPIM_RXD_Type RXD; /*!< RXD EasyDMA configuration and status. */
- __I uint32_t RESERVED14;
+ __I uint32_t RESERVED11;
SPIM_TXD_Type TXD; /*!< TXD EasyDMA configuration and status. */
- __I uint32_t RESERVED15;
+ __I uint32_t RESERVED12;
__IO uint32_t CONFIG; /*!< Configuration register. */
- __I uint32_t RESERVED16[26];
+ __I uint32_t RESERVED13[26];
__IO uint32_t ORC; /*!< Over-read character. */
- __I uint32_t RESERVED17[654];
+ __I uint32_t RESERVED14[654];
__IO uint32_t POWER; /*!< Peripheral power control. */
} NRF_SPIM_Type;
@@ -1087,9 +1031,13 @@
__I uint32_t READY; /*!< Ready flag. */
__I uint32_t RESERVED1[64];
__IO uint32_t CONFIG; /*!< Configuration register. */
- __IO uint32_t ERASEPAGE; /*!< Register for erasing a non-protected non-volatile memory page. */
+
+ union {
+ __IO uint32_t ERASEPCR1; /*!< Register for erasing a non-protected non-volatile memory page. */
+ __IO uint32_t ERASEPAGE; /*!< Register for erasing a non-protected non-volatile memory page. */
+ };
__IO uint32_t ERASEALL; /*!< Register for erasing all non-volatile user memory. */
- __IO uint32_t ERASEPROTECTEDPAGE; /*!< Register for erasing a protected non-volatile memory page. */
+ __IO uint32_t ERASEPCR0; /*!< Register for erasing a protected non-volatile memory page. */
__IO uint32_t ERASEUICR; /*!< Register for start erasing User Information Congfiguration Registers. */
} NRF_NVMC_Type;
@@ -1134,7 +1082,7 @@
__I uint32_t PPFC; /*!< Pre-programmed factory code present. */
__I uint32_t RESERVED2;
__I uint32_t NUMRAMBLOCK; /*!< Number of individualy controllable RAM blocks. */
-
+
union {
__I uint32_t SIZERAMBLOCK[4]; /*!< Deprecated array of size of RAM block in bytes. This name is
kept for backward compatinility purposes. Use SIZERAMBLOCKS
@@ -1155,7 +1103,6 @@
__I uint32_t RESERVED5[10];
__I uint32_t BLE_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for BLE_1Mbit
mode. */
- FICR_INFO_Type INFO; /*!< Device info */
} NRF_FICR_Type;
@@ -1174,7 +1121,13 @@
__IO uint32_t XTALFREQ; /*!< Reset value for CLOCK XTALFREQ register. */
__I uint32_t RESERVED0;
__I uint32_t FWID; /*!< Firmware ID. */
- __IO uint32_t BOOTLOADERADDR; /*!< Bootloader start address. */
+
+ union {
+ __IO uint32_t NRFFW[15]; /*!< Reserved for Nordic firmware design. */
+ __IO uint32_t BOOTLOADERADDR; /*!< Bootloader start address. */
+ };
+ __IO uint32_t NRFHW[12]; /*!< Reserved for Nordic hardware design. */
+ __IO uint32_t CUSTOMER[32]; /*!< Reserved for customer. */
} NRF_UICR_Type;
@@ -1226,7 +1179,6 @@
#define NRF_POWER_BASE 0x40000000UL
#define NRF_CLOCK_BASE 0x40000000UL
#define NRF_MPU_BASE 0x40000000UL
-#define NRF_PU_BASE 0x40000000UL
#define NRF_AMLI_BASE 0x40000000UL
#define NRF_RADIO_BASE 0x40001000UL
#define NRF_UART0_BASE 0x40002000UL
@@ -1266,7 +1218,6 @@
#define NRF_POWER ((NRF_POWER_Type *) NRF_POWER_BASE)
#define NRF_CLOCK ((NRF_CLOCK_Type *) NRF_CLOCK_BASE)
#define NRF_MPU ((NRF_MPU_Type *) NRF_MPU_BASE)
-#define NRF_PU ((NRF_PU_Type *) NRF_PU_BASE)
#define NRF_AMLI ((NRF_AMLI_Type *) NRF_AMLI_BASE)
#define NRF_RADIO ((NRF_RADIO_Type *) NRF_RADIO_BASE)
#define NRF_UART0 ((NRF_UART_Type *) NRF_UART0_BASE)
@@ -1300,7 +1251,7 @@
/** @} */ /* End of group Device_Peripheral_Registers */
-/** @} */ /* End of group nRF51 */
+/** @} */ /* End of group nrf51 */
/** @} */ /* End of group Nordic Semiconductor */
#ifdef __cplusplus
@@ -1308,5 +1259,5 @@
#endif
-#endif /* nRF51_H */
+#endif /* nrf51_H */