David Saul / mbed-dev-bin

R1 code for micro:bit based train controller code, requires second micro:bit running rx code to operate - see https://meanderingpi.wordpress.com/ for more information

Fork of mbed-dev-bin by Lancaster University

TARGET_NRF51_MICROBIT/nrf_delay.h@4:98796b85dcf3, 2017-05-23 (annotated)

Committer:
DavidMS
Date:
Tue May 23 12:27:33 2017 +0000
Revision:
4:98796b85dcf3
Parent:
0:e1a608bb55e8 
basic_microbit_tx_train_controller_code: R1 code for micro:bit based train controller code, requires second micro:bit running rx code to operate - see https://meanderingpi.wordpress.com/ for more details

Who changed what in which revision?

UserRevisionLine numberNew contents of line
jamesadevine 0:e1a608bb55e8 1 #ifndef _NRF_DELAY_H
jamesadevine 0:e1a608bb55e8 2 #define _NRF_DELAY_H
jamesadevine 0:e1a608bb55e8 3
jamesadevine 0:e1a608bb55e8 4 // #include "nrf.h"
jamesadevine 0:e1a608bb55e8 5
jamesadevine 0:e1a608bb55e8 6 /*lint --e{438, 522} "Variable not used" "Function lacks side-effects" */
jamesadevine 0:e1a608bb55e8 7 #if defined ( __CC_ARM )
jamesadevine 0:e1a608bb55e8 8 static __ASM void __INLINE nrf_delay_us(uint32_t volatile number_of_us)
jamesadevine 0:e1a608bb55e8 9 {
jamesadevine 0:e1a608bb55e8 10 loop
jamesadevine 0:e1a608bb55e8 11 SUBS R0, R0, #1
jamesadevine 0:e1a608bb55e8 12 NOP
jamesadevine 0:e1a608bb55e8 13 NOP
jamesadevine 0:e1a608bb55e8 14 NOP
jamesadevine 0:e1a608bb55e8 15 NOP
jamesadevine 0:e1a608bb55e8 16 NOP
jamesadevine 0:e1a608bb55e8 17 NOP
jamesadevine 0:e1a608bb55e8 18 NOP
jamesadevine 0:e1a608bb55e8 19 NOP
jamesadevine 0:e1a608bb55e8 20 NOP
jamesadevine 0:e1a608bb55e8 21 NOP
jamesadevine 0:e1a608bb55e8 22 NOP
jamesadevine 0:e1a608bb55e8 23 NOP
jamesadevine 0:e1a608bb55e8 24 BNE loop
jamesadevine 0:e1a608bb55e8 25 BX LR
jamesadevine 0:e1a608bb55e8 26 }
jamesadevine 0:e1a608bb55e8 27 #elif defined ( __ICCARM__ )
jamesadevine 0:e1a608bb55e8 28 static void __INLINE nrf_delay_us(uint32_t volatile number_of_us)
jamesadevine 0:e1a608bb55e8 29 {
jamesadevine 0:e1a608bb55e8 30 __ASM (
jamesadevine 0:e1a608bb55e8 31 "loop:\n\t"
jamesadevine 0:e1a608bb55e8 32 " SUBS R0, R0, #1\n\t"
jamesadevine 0:e1a608bb55e8 33 " NOP\n\t"
jamesadevine 0:e1a608bb55e8 34 " NOP\n\t"
jamesadevine 0:e1a608bb55e8 35 " NOP\n\t"
jamesadevine 0:e1a608bb55e8 36 " NOP\n\t"
jamesadevine 0:e1a608bb55e8 37 " NOP\n\t"
jamesadevine 0:e1a608bb55e8 38 " NOP\n\t"
jamesadevine 0:e1a608bb55e8 39 " NOP\n\t"
jamesadevine 0:e1a608bb55e8 40 " NOP\n\t"
jamesadevine 0:e1a608bb55e8 41 " NOP\n\t"
jamesadevine 0:e1a608bb55e8 42 " NOP\n\t"
jamesadevine 0:e1a608bb55e8 43 " NOP\n\t"
jamesadevine 0:e1a608bb55e8 44 " NOP\n\t"
jamesadevine 0:e1a608bb55e8 45 " BNE loop\n\t");
jamesadevine 0:e1a608bb55e8 46 }
jamesadevine 0:e1a608bb55e8 47 #elif defined ( __GNUC__ )
jamesadevine 0:e1a608bb55e8 48 __INLINE static void nrf_delay_us(uint32_t volatile number_of_us)
jamesadevine 0:e1a608bb55e8 49 {
jamesadevine 0:e1a608bb55e8 50 do
jamesadevine 0:e1a608bb55e8 51 {
jamesadevine 0:e1a608bb55e8 52 __ASM volatile (
jamesadevine 0:e1a608bb55e8 53 "NOP\n\t"
jamesadevine 0:e1a608bb55e8 54 "NOP\n\t"
jamesadevine 0:e1a608bb55e8 55 "NOP\n\t"
jamesadevine 0:e1a608bb55e8 56 "NOP\n\t"
jamesadevine 0:e1a608bb55e8 57 "NOP\n\t"
jamesadevine 0:e1a608bb55e8 58 "NOP\n\t"
jamesadevine 0:e1a608bb55e8 59 "NOP\n\t"
jamesadevine 0:e1a608bb55e8 60 "NOP\n\t"
jamesadevine 0:e1a608bb55e8 61 "NOP\n\t"
jamesadevine 0:e1a608bb55e8 62 "NOP\n\t"
jamesadevine 0:e1a608bb55e8 63 "NOP\n\t"
jamesadevine 0:e1a608bb55e8 64 "NOP\n\t"
jamesadevine 0:e1a608bb55e8 65 "NOP\n\t"
jamesadevine 0:e1a608bb55e8 66 "NOP\n\t"
jamesadevine 0:e1a608bb55e8 67 );
jamesadevine 0:e1a608bb55e8 68 } while (--number_of_us);
jamesadevine 0:e1a608bb55e8 69 }
jamesadevine 0:e1a608bb55e8 70 #endif
jamesadevine 0:e1a608bb55e8 71
jamesadevine 0:e1a608bb55e8 72 void nrf_delay_ms(uint32_t volatile number_of_ms);
jamesadevine 0:e1a608bb55e8 73
jamesadevine 0:e1a608bb55e8 74 #endif