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R1 code for micro:bit based train controller code, requires second micro:bit running rx code to operate - see https://meanderingpi.wordpress.com/ for more information

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TARGET_NRF51_MICROBIT/nrf51_bitfields.h@4:98796b85dcf3, 2017-05-23 (annotated)

Committer:: DavidMS
Date:: Tue May 23 12:27:33 2017 +0000
Revision:: 4:98796b85dcf3
Parent:: 0:e1a608bb55e8

basic_microbit_tx_train_controller_code: R1 code for micro:bit based train controller code, requires second micro:bit running rx code to operate - see https://meanderingpi.wordpress.com/ for more details

Who changed what in which revision?

User	Revision	Line number	New contents of line
jamesadevine	0:e1a608bb55e8	1	/* Copyright (c) 2013, Nordic Semiconductor ASA
jamesadevine	0:e1a608bb55e8	2	* All rights reserved.
jamesadevine	0:e1a608bb55e8	3	*
jamesadevine	0:e1a608bb55e8	4	* Redistribution and use in source and binary forms, with or without
jamesadevine	0:e1a608bb55e8	5	* modification, are permitted provided that the following conditions are met:
jamesadevine	0:e1a608bb55e8	6	*
jamesadevine	0:e1a608bb55e8	7	* * Redistributions of source code must retain the above copyright notice, this
jamesadevine	0:e1a608bb55e8	8	* list of conditions and the following disclaimer.
jamesadevine	0:e1a608bb55e8	9	*
jamesadevine	0:e1a608bb55e8	10	* * Redistributions in binary form must reproduce the above copyright notice,
jamesadevine	0:e1a608bb55e8	11	* this list of conditions and the following disclaimer in the documentation
jamesadevine	0:e1a608bb55e8	12	* and/or other materials provided with the distribution.
jamesadevine	0:e1a608bb55e8	13	*
jamesadevine	0:e1a608bb55e8	14	* * Neither the name of Nordic Semiconductor ASA nor the names of its
jamesadevine	0:e1a608bb55e8	15	* contributors may be used to endorse or promote products derived from
jamesadevine	0:e1a608bb55e8	16	* this software without specific prior written permission.
jamesadevine	0:e1a608bb55e8	17	*
jamesadevine	0:e1a608bb55e8	18	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
jamesadevine	0:e1a608bb55e8	19	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
jamesadevine	0:e1a608bb55e8	20	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
jamesadevine	0:e1a608bb55e8	21	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
jamesadevine	0:e1a608bb55e8	22	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
jamesadevine	0:e1a608bb55e8	23	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
jamesadevine	0:e1a608bb55e8	24	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
jamesadevine	0:e1a608bb55e8	25	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
jamesadevine	0:e1a608bb55e8	26	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
jamesadevine	0:e1a608bb55e8	27	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
jamesadevine	0:e1a608bb55e8	28	*
jamesadevine	0:e1a608bb55e8	29	*/
jamesadevine	0:e1a608bb55e8	30	#ifndef __NRF51_BITS_H
jamesadevine	0:e1a608bb55e8	31	#define __NRF51_BITS_H
jamesadevine	0:e1a608bb55e8	32
jamesadevine	0:e1a608bb55e8	33	/lint ++flb "Enter library region /
jamesadevine	0:e1a608bb55e8	34
jamesadevine	0:e1a608bb55e8	35	#include <core_cm0.h>
jamesadevine	0:e1a608bb55e8	36
jamesadevine	0:e1a608bb55e8	37	/* Peripheral: AAR */
jamesadevine	0:e1a608bb55e8	38	/* Description: Accelerated Address Resolver. */
jamesadevine	0:e1a608bb55e8	39
jamesadevine	0:e1a608bb55e8	40	/* Register: AAR_INTENSET */
jamesadevine	0:e1a608bb55e8	41	/* Description: Interrupt enable set register. */
jamesadevine	0:e1a608bb55e8	42
jamesadevine	0:e1a608bb55e8	43	/* Bit 2 : Enable interrupt on NOTRESOLVED event. */
jamesadevine	0:e1a608bb55e8	44	#define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /!< Position of NOTRESOLVED field. /
jamesadevine	0:e1a608bb55e8	45	#define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /!< Bit mask of NOTRESOLVED field. /
jamesadevine	0:e1a608bb55e8	46	#define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	47	#define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	48	#define AAR_INTENSET_NOTRESOLVED_Set (1UL) /!< Enable interrupt on write. /
jamesadevine	0:e1a608bb55e8	49
jamesadevine	0:e1a608bb55e8	50	/* Bit 1 : Enable interrupt on RESOLVED event. */
jamesadevine	0:e1a608bb55e8	51	#define AAR_INTENSET_RESOLVED_Pos (1UL) /!< Position of RESOLVED field. /
jamesadevine	0:e1a608bb55e8	52	#define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /!< Bit mask of RESOLVED field. /
jamesadevine	0:e1a608bb55e8	53	#define AAR_INTENSET_RESOLVED_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	54	#define AAR_INTENSET_RESOLVED_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	55	#define AAR_INTENSET_RESOLVED_Set (1UL) /!< Enable interrupt on write. /
jamesadevine	0:e1a608bb55e8	56
jamesadevine	0:e1a608bb55e8	57	/* Bit 0 : Enable interrupt on END event. */
jamesadevine	0:e1a608bb55e8	58	#define AAR_INTENSET_END_Pos (0UL) /!< Position of END field. /
jamesadevine	0:e1a608bb55e8	59	#define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /!< Bit mask of END field. /
jamesadevine	0:e1a608bb55e8	60	#define AAR_INTENSET_END_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	61	#define AAR_INTENSET_END_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	62	#define AAR_INTENSET_END_Set (1UL) /!< Enable interrupt on write. /
jamesadevine	0:e1a608bb55e8	63
jamesadevine	0:e1a608bb55e8	64	/* Register: AAR_INTENCLR */
jamesadevine	0:e1a608bb55e8	65	/* Description: Interrupt enable clear register. */
jamesadevine	0:e1a608bb55e8	66
jamesadevine	0:e1a608bb55e8	67	/* Bit 2 : Disable interrupt on NOTRESOLVED event. */
jamesadevine	0:e1a608bb55e8	68	#define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /!< Position of NOTRESOLVED field. /
jamesadevine	0:e1a608bb55e8	69	#define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /!< Bit mask of NOTRESOLVED field. /
jamesadevine	0:e1a608bb55e8	70	#define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	71	#define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	72	#define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /!< Disable interrupt on write. /
jamesadevine	0:e1a608bb55e8	73
jamesadevine	0:e1a608bb55e8	74	/* Bit 1 : Disable interrupt on RESOLVED event. */
jamesadevine	0:e1a608bb55e8	75	#define AAR_INTENCLR_RESOLVED_Pos (1UL) /!< Position of RESOLVED field. /
jamesadevine	0:e1a608bb55e8	76	#define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /!< Bit mask of RESOLVED field. /
jamesadevine	0:e1a608bb55e8	77	#define AAR_INTENCLR_RESOLVED_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	78	#define AAR_INTENCLR_RESOLVED_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	79	#define AAR_INTENCLR_RESOLVED_Clear (1UL) /!< Disable interrupt on write. /
jamesadevine	0:e1a608bb55e8	80
jamesadevine	0:e1a608bb55e8	81	/* Bit 0 : Disable interrupt on ENDKSGEN event. */
jamesadevine	0:e1a608bb55e8	82	#define AAR_INTENCLR_END_Pos (0UL) /!< Position of END field. /
jamesadevine	0:e1a608bb55e8	83	#define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /!< Bit mask of END field. /
jamesadevine	0:e1a608bb55e8	84	#define AAR_INTENCLR_END_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	85	#define AAR_INTENCLR_END_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	86	#define AAR_INTENCLR_END_Clear (1UL) /!< Disable interrupt on write. /
jamesadevine	0:e1a608bb55e8	87
jamesadevine	0:e1a608bb55e8	88	/* Register: AAR_STATUS */
jamesadevine	0:e1a608bb55e8	89	/* Description: Resolution status. */
jamesadevine	0:e1a608bb55e8	90
jamesadevine	0:e1a608bb55e8	91	/* Bits 3..0 : The IRK used last time an address was resolved. */
jamesadevine	0:e1a608bb55e8	92	#define AAR_STATUS_STATUS_Pos (0UL) /!< Position of STATUS field. /
jamesadevine	0:e1a608bb55e8	93	#define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos) /!< Bit mask of STATUS field. /
jamesadevine	0:e1a608bb55e8	94
jamesadevine	0:e1a608bb55e8	95	/* Register: AAR_ENABLE */
jamesadevine	0:e1a608bb55e8	96	/* Description: Enable AAR. */
jamesadevine	0:e1a608bb55e8	97
jamesadevine	0:e1a608bb55e8	98	/* Bits 1..0 : Enable AAR. */
jamesadevine	0:e1a608bb55e8	99	#define AAR_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
jamesadevine	0:e1a608bb55e8	100	#define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
jamesadevine	0:e1a608bb55e8	101	#define AAR_ENABLE_ENABLE_Disabled (0x00UL) /!< Disabled AAR. /
jamesadevine	0:e1a608bb55e8	102	#define AAR_ENABLE_ENABLE_Enabled (0x03UL) /!< Enable AAR. /
jamesadevine	0:e1a608bb55e8	103
jamesadevine	0:e1a608bb55e8	104	/* Register: AAR_NIRK */
jamesadevine	0:e1a608bb55e8	105	/* Description: Number of Identity root Keys in the IRK data structure. */
jamesadevine	0:e1a608bb55e8	106
jamesadevine	0:e1a608bb55e8	107	/* Bits 4..0 : Number of Identity root Keys in the IRK data structure. */
jamesadevine	0:e1a608bb55e8	108	#define AAR_NIRK_NIRK_Pos (0UL) /!< Position of NIRK field. /
jamesadevine	0:e1a608bb55e8	109	#define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /!< Bit mask of NIRK field. /
jamesadevine	0:e1a608bb55e8	110
jamesadevine	0:e1a608bb55e8	111	/* Register: AAR_POWER */
jamesadevine	0:e1a608bb55e8	112	/* Description: Peripheral power control. */
jamesadevine	0:e1a608bb55e8	113
jamesadevine	0:e1a608bb55e8	114	/* Bit 0 : Peripheral power control. */
jamesadevine	0:e1a608bb55e8	115	#define AAR_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
jamesadevine	0:e1a608bb55e8	116	#define AAR_POWER_POWER_Msk (0x1UL << AAR_POWER_POWER_Pos) /!< Bit mask of POWER field. /
jamesadevine	0:e1a608bb55e8	117	#define AAR_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
jamesadevine	0:e1a608bb55e8	118	#define AAR_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
jamesadevine	0:e1a608bb55e8	119
jamesadevine	0:e1a608bb55e8	120
jamesadevine	0:e1a608bb55e8	121	/* Peripheral: ADC */
jamesadevine	0:e1a608bb55e8	122	/* Description: Analog to digital converter. */
jamesadevine	0:e1a608bb55e8	123
jamesadevine	0:e1a608bb55e8	124	/* Register: ADC_INTENSET */
jamesadevine	0:e1a608bb55e8	125	/* Description: Interrupt enable set register. */
jamesadevine	0:e1a608bb55e8	126
jamesadevine	0:e1a608bb55e8	127	/* Bit 0 : Enable interrupt on END event. */
jamesadevine	0:e1a608bb55e8	128	#define ADC_INTENSET_END_Pos (0UL) /!< Position of END field. /
jamesadevine	0:e1a608bb55e8	129	#define ADC_INTENSET_END_Msk (0x1UL << ADC_INTENSET_END_Pos) /!< Bit mask of END field. /
jamesadevine	0:e1a608bb55e8	130	#define ADC_INTENSET_END_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	131	#define ADC_INTENSET_END_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	132	#define ADC_INTENSET_END_Set (1UL) /!< Enable interrupt on write. /
jamesadevine	0:e1a608bb55e8	133
jamesadevine	0:e1a608bb55e8	134	/* Register: ADC_INTENCLR */
jamesadevine	0:e1a608bb55e8	135	/* Description: Interrupt enable clear register. */
jamesadevine	0:e1a608bb55e8	136
jamesadevine	0:e1a608bb55e8	137	/* Bit 0 : Disable interrupt on END event. */
jamesadevine	0:e1a608bb55e8	138	#define ADC_INTENCLR_END_Pos (0UL) /!< Position of END field. /
jamesadevine	0:e1a608bb55e8	139	#define ADC_INTENCLR_END_Msk (0x1UL << ADC_INTENCLR_END_Pos) /!< Bit mask of END field. /
jamesadevine	0:e1a608bb55e8	140	#define ADC_INTENCLR_END_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	141	#define ADC_INTENCLR_END_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	142	#define ADC_INTENCLR_END_Clear (1UL) /!< Disable interrupt on write. /
jamesadevine	0:e1a608bb55e8	143
jamesadevine	0:e1a608bb55e8	144	/* Register: ADC_BUSY */
jamesadevine	0:e1a608bb55e8	145	/* Description: ADC busy register. */
jamesadevine	0:e1a608bb55e8	146
jamesadevine	0:e1a608bb55e8	147	/* Bit 0 : ADC busy register. */
jamesadevine	0:e1a608bb55e8	148	#define ADC_BUSY_BUSY_Pos (0UL) /!< Position of BUSY field. /
jamesadevine	0:e1a608bb55e8	149	#define ADC_BUSY_BUSY_Msk (0x1UL << ADC_BUSY_BUSY_Pos) /!< Bit mask of BUSY field. /
jamesadevine	0:e1a608bb55e8	150	#define ADC_BUSY_BUSY_Ready (0UL) /!< No ongoing ADC conversion is taking place. ADC is ready. /
jamesadevine	0:e1a608bb55e8	151	#define ADC_BUSY_BUSY_Busy (1UL) /!< An ADC conversion is taking place. ADC is busy. /
jamesadevine	0:e1a608bb55e8	152
jamesadevine	0:e1a608bb55e8	153	/* Register: ADC_ENABLE */
jamesadevine	0:e1a608bb55e8	154	/* Description: ADC enable. */
jamesadevine	0:e1a608bb55e8	155
jamesadevine	0:e1a608bb55e8	156	/* Bits 1..0 : ADC enable. */
jamesadevine	0:e1a608bb55e8	157	#define ADC_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
jamesadevine	0:e1a608bb55e8	158	#define ADC_ENABLE_ENABLE_Msk (0x3UL << ADC_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
jamesadevine	0:e1a608bb55e8	159	#define ADC_ENABLE_ENABLE_Disabled (0x00UL) /!< ADC is disabled. /
jamesadevine	0:e1a608bb55e8	160	#define ADC_ENABLE_ENABLE_Enabled (0x01UL) /!< ADC is enabled. If an analog input pin is selected as source of the conversion, the selected pin is configured as an analog input. /
jamesadevine	0:e1a608bb55e8	161
jamesadevine	0:e1a608bb55e8	162	/* Register: ADC_CONFIG */
jamesadevine	0:e1a608bb55e8	163	/* Description: ADC configuration register. */
jamesadevine	0:e1a608bb55e8	164
jamesadevine	0:e1a608bb55e8	165	/* Bits 17..16 : ADC external reference pin selection. */
jamesadevine	0:e1a608bb55e8	166	#define ADC_CONFIG_EXTREFSEL_Pos (16UL) /!< Position of EXTREFSEL field. /
jamesadevine	0:e1a608bb55e8	167	#define ADC_CONFIG_EXTREFSEL_Msk (0x3UL << ADC_CONFIG_EXTREFSEL_Pos) /!< Bit mask of EXTREFSEL field. /
jamesadevine	0:e1a608bb55e8	168	#define ADC_CONFIG_EXTREFSEL_None (0UL) /!< Analog external reference inputs disabled. /
jamesadevine	0:e1a608bb55e8	169	#define ADC_CONFIG_EXTREFSEL_AnalogReference0 (1UL) /!< Use analog reference 0 as reference. /
jamesadevine	0:e1a608bb55e8	170	#define ADC_CONFIG_EXTREFSEL_AnalogReference1 (2UL) /!< Use analog reference 1 as reference. /
jamesadevine	0:e1a608bb55e8	171
jamesadevine	0:e1a608bb55e8	172	/* Bits 15..8 : ADC analog pin selection. */
jamesadevine	0:e1a608bb55e8	173	#define ADC_CONFIG_PSEL_Pos (8UL) /!< Position of PSEL field. /
jamesadevine	0:e1a608bb55e8	174	#define ADC_CONFIG_PSEL_Msk (0xFFUL << ADC_CONFIG_PSEL_Pos) /!< Bit mask of PSEL field. /
jamesadevine	0:e1a608bb55e8	175	#define ADC_CONFIG_PSEL_Disabled (0UL) /!< Analog input pins disabled. /
jamesadevine	0:e1a608bb55e8	176	#define ADC_CONFIG_PSEL_AnalogInput0 (1UL) /!< Use analog input 0 as analog input. /
jamesadevine	0:e1a608bb55e8	177	#define ADC_CONFIG_PSEL_AnalogInput1 (2UL) /!< Use analog input 1 as analog input. /
jamesadevine	0:e1a608bb55e8	178	#define ADC_CONFIG_PSEL_AnalogInput2 (4UL) /!< Use analog input 2 as analog input. /
jamesadevine	0:e1a608bb55e8	179	#define ADC_CONFIG_PSEL_AnalogInput3 (8UL) /!< Use analog input 3 as analog input. /
jamesadevine	0:e1a608bb55e8	180	#define ADC_CONFIG_PSEL_AnalogInput4 (16UL) /!< Use analog input 4 as analog input. /
jamesadevine	0:e1a608bb55e8	181	#define ADC_CONFIG_PSEL_AnalogInput5 (32UL) /!< Use analog input 5 as analog input. /
jamesadevine	0:e1a608bb55e8	182	#define ADC_CONFIG_PSEL_AnalogInput6 (64UL) /!< Use analog input 6 as analog input. /
jamesadevine	0:e1a608bb55e8	183	#define ADC_CONFIG_PSEL_AnalogInput7 (128UL) /!< Use analog input 7 as analog input. /
jamesadevine	0:e1a608bb55e8	184
jamesadevine	0:e1a608bb55e8	185	/* Bits 6..5 : ADC reference selection. */
jamesadevine	0:e1a608bb55e8	186	#define ADC_CONFIG_REFSEL_Pos (5UL) /!< Position of REFSEL field. /
jamesadevine	0:e1a608bb55e8	187	#define ADC_CONFIG_REFSEL_Msk (0x3UL << ADC_CONFIG_REFSEL_Pos) /!< Bit mask of REFSEL field. /
jamesadevine	0:e1a608bb55e8	188	#define ADC_CONFIG_REFSEL_VBG (0x00UL) /!< Use internal 1.2V bandgap voltage as reference for conversion. /
jamesadevine	0:e1a608bb55e8	189	#define ADC_CONFIG_REFSEL_External (0x01UL) /!< Use external source configured by EXTREFSEL as reference for conversion. /
jamesadevine	0:e1a608bb55e8	190	#define ADC_CONFIG_REFSEL_SupplyOneHalfPrescaling (0x02UL) /!< Use supply voltage with 1/2 prescaling as reference for conversion. Only usable when supply voltage is between 1.7V and 2.6V. /
jamesadevine	0:e1a608bb55e8	191	#define ADC_CONFIG_REFSEL_SupplyOneThirdPrescaling (0x03UL) /!< Use supply voltage with 1/3 prescaling as reference for conversion. Only usable when supply voltage is between 2.5V and 3.6V. /
jamesadevine	0:e1a608bb55e8	192
jamesadevine	0:e1a608bb55e8	193	/* Bits 4..2 : ADC input selection. */
jamesadevine	0:e1a608bb55e8	194	#define ADC_CONFIG_INPSEL_Pos (2UL) /!< Position of INPSEL field. /
jamesadevine	0:e1a608bb55e8	195	#define ADC_CONFIG_INPSEL_Msk (0x7UL << ADC_CONFIG_INPSEL_Pos) /!< Bit mask of INPSEL field. /
jamesadevine	0:e1a608bb55e8	196	#define ADC_CONFIG_INPSEL_AnalogInputNoPrescaling (0x00UL) /!< Analog input specified by PSEL with no prescaling used as input for the conversion. /
jamesadevine	0:e1a608bb55e8	197	#define ADC_CONFIG_INPSEL_AnalogInputTwoThirdsPrescaling (0x01UL) /!< Analog input specified by PSEL with 2/3 prescaling used as input for the conversion. /
jamesadevine	0:e1a608bb55e8	198	#define ADC_CONFIG_INPSEL_AnalogInputOneThirdPrescaling (0x02UL) /!< Analog input specified by PSEL with 1/3 prescaling used as input for the conversion. /
jamesadevine	0:e1a608bb55e8	199	#define ADC_CONFIG_INPSEL_SupplyTwoThirdsPrescaling (0x05UL) /!< Supply voltage with 2/3 prescaling used as input for the conversion. /
jamesadevine	0:e1a608bb55e8	200	#define ADC_CONFIG_INPSEL_SupplyOneThirdPrescaling (0x06UL) /!< Supply voltage with 1/3 prescaling used as input for the conversion. /
jamesadevine	0:e1a608bb55e8	201
jamesadevine	0:e1a608bb55e8	202	/* Bits 1..0 : ADC resolution. */
jamesadevine	0:e1a608bb55e8	203	#define ADC_CONFIG_RES_Pos (0UL) /!< Position of RES field. /
jamesadevine	0:e1a608bb55e8	204	#define ADC_CONFIG_RES_Msk (0x3UL << ADC_CONFIG_RES_Pos) /!< Bit mask of RES field. /
jamesadevine	0:e1a608bb55e8	205	#define ADC_CONFIG_RES_8bit (0x00UL) /!< 8bit ADC resolution. /
jamesadevine	0:e1a608bb55e8	206	#define ADC_CONFIG_RES_9bit (0x01UL) /!< 9bit ADC resolution. /
jamesadevine	0:e1a608bb55e8	207	#define ADC_CONFIG_RES_10bit (0x02UL) /!< 10bit ADC resolution. /
jamesadevine	0:e1a608bb55e8	208
jamesadevine	0:e1a608bb55e8	209	/* Register: ADC_RESULT */
jamesadevine	0:e1a608bb55e8	210	/* Description: Result of ADC conversion. */
jamesadevine	0:e1a608bb55e8	211
jamesadevine	0:e1a608bb55e8	212	/* Bits 9..0 : Result of ADC conversion. */
jamesadevine	0:e1a608bb55e8	213	#define ADC_RESULT_RESULT_Pos (0UL) /!< Position of RESULT field. /
jamesadevine	0:e1a608bb55e8	214	#define ADC_RESULT_RESULT_Msk (0x3FFUL << ADC_RESULT_RESULT_Pos) /!< Bit mask of RESULT field. /
jamesadevine	0:e1a608bb55e8	215
jamesadevine	0:e1a608bb55e8	216	/* Register: ADC_POWER */
jamesadevine	0:e1a608bb55e8	217	/* Description: Peripheral power control. */
jamesadevine	0:e1a608bb55e8	218
jamesadevine	0:e1a608bb55e8	219	/* Bit 0 : Peripheral power control. */
jamesadevine	0:e1a608bb55e8	220	#define ADC_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
jamesadevine	0:e1a608bb55e8	221	#define ADC_POWER_POWER_Msk (0x1UL << ADC_POWER_POWER_Pos) /!< Bit mask of POWER field. /
jamesadevine	0:e1a608bb55e8	222	#define ADC_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
jamesadevine	0:e1a608bb55e8	223	#define ADC_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
jamesadevine	0:e1a608bb55e8	224
jamesadevine	0:e1a608bb55e8	225
jamesadevine	0:e1a608bb55e8	226	/* Peripheral: AMLI */
jamesadevine	0:e1a608bb55e8	227	/* Description: AHB Multi-Layer Interface. */
jamesadevine	0:e1a608bb55e8	228
jamesadevine	0:e1a608bb55e8	229	/* Register: AMLI_RAMPRI_CPU0 */
jamesadevine	0:e1a608bb55e8	230	/* Description: Configurable priority configuration register for CPU0. */
jamesadevine	0:e1a608bb55e8	231
jamesadevine	0:e1a608bb55e8	232	/* Bits 31..28 : Configuration field for RAM block 7. */
jamesadevine	0:e1a608bb55e8	233	#define AMLI_RAMPRI_CPU0_RAM7_Pos (28UL) /!< Position of RAM7 field. /
jamesadevine	0:e1a608bb55e8	234	#define AMLI_RAMPRI_CPU0_RAM7_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM7_Pos) /!< Bit mask of RAM7 field. /
jamesadevine	0:e1a608bb55e8	235	#define AMLI_RAMPRI_CPU0_RAM7_Pri0 (0x0UL) /!< Priority 0. /
jamesadevine	0:e1a608bb55e8	236	#define AMLI_RAMPRI_CPU0_RAM7_Pri2 (0x2UL) /!< Priority 2. /
jamesadevine	0:e1a608bb55e8	237	#define AMLI_RAMPRI_CPU0_RAM7_Pri4 (0x4UL) /!< Priority 4. /
jamesadevine	0:e1a608bb55e8	238	#define AMLI_RAMPRI_CPU0_RAM7_Pri6 (0x6UL) /!< Priority 6. /
jamesadevine	0:e1a608bb55e8	239	#define AMLI_RAMPRI_CPU0_RAM7_Pri8 (0x8UL) /!< Priority 8. /
jamesadevine	0:e1a608bb55e8	240	#define AMLI_RAMPRI_CPU0_RAM7_Pri10 (0xAUL) /!< Priority 10. /
jamesadevine	0:e1a608bb55e8	241	#define AMLI_RAMPRI_CPU0_RAM7_Pri12 (0xCUL) /!< Priority 12. /
jamesadevine	0:e1a608bb55e8	242	#define AMLI_RAMPRI_CPU0_RAM7_Pri14 (0xEUL) /!< Priority 14. /
jamesadevine	0:e1a608bb55e8	243
jamesadevine	0:e1a608bb55e8	244	/* Bits 27..24 : Configuration field for RAM block 6. */
jamesadevine	0:e1a608bb55e8	245	#define AMLI_RAMPRI_CPU0_RAM6_Pos (24UL) /!< Position of RAM6 field. /
jamesadevine	0:e1a608bb55e8	246	#define AMLI_RAMPRI_CPU0_RAM6_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM6_Pos) /!< Bit mask of RAM6 field. /
jamesadevine	0:e1a608bb55e8	247	#define AMLI_RAMPRI_CPU0_RAM6_Pri0 (0x0UL) /!< Priority 0. /
jamesadevine	0:e1a608bb55e8	248	#define AMLI_RAMPRI_CPU0_RAM6_Pri2 (0x2UL) /!< Priority 2. /
jamesadevine	0:e1a608bb55e8	249	#define AMLI_RAMPRI_CPU0_RAM6_Pri4 (0x4UL) /!< Priority 4. /
jamesadevine	0:e1a608bb55e8	250	#define AMLI_RAMPRI_CPU0_RAM6_Pri6 (0x6UL) /!< Priority 6. /
jamesadevine	0:e1a608bb55e8	251	#define AMLI_RAMPRI_CPU0_RAM6_Pri8 (0x8UL) /!< Priority 8. /
jamesadevine	0:e1a608bb55e8	252	#define AMLI_RAMPRI_CPU0_RAM6_Pri10 (0xAUL) /!< Priority 10. /
jamesadevine	0:e1a608bb55e8	253	#define AMLI_RAMPRI_CPU0_RAM6_Pri12 (0xCUL) /!< Priority 12. /
jamesadevine	0:e1a608bb55e8	254	#define AMLI_RAMPRI_CPU0_RAM6_Pri14 (0xEUL) /!< Priority 14. /
jamesadevine	0:e1a608bb55e8	255
jamesadevine	0:e1a608bb55e8	256	/* Bits 23..20 : Configuration field for RAM block 5. */
jamesadevine	0:e1a608bb55e8	257	#define AMLI_RAMPRI_CPU0_RAM5_Pos (20UL) /!< Position of RAM5 field. /
jamesadevine	0:e1a608bb55e8	258	#define AMLI_RAMPRI_CPU0_RAM5_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM5_Pos) /!< Bit mask of RAM5 field. /
jamesadevine	0:e1a608bb55e8	259	#define AMLI_RAMPRI_CPU0_RAM5_Pri0 (0x0UL) /!< Priority 0. /
jamesadevine	0:e1a608bb55e8	260	#define AMLI_RAMPRI_CPU0_RAM5_Pri2 (0x2UL) /!< Priority 2. /
jamesadevine	0:e1a608bb55e8	261	#define AMLI_RAMPRI_CPU0_RAM5_Pri4 (0x4UL) /!< Priority 4. /
jamesadevine	0:e1a608bb55e8	262	#define AMLI_RAMPRI_CPU0_RAM5_Pri6 (0x6UL) /!< Priority 6. /
jamesadevine	0:e1a608bb55e8	263	#define AMLI_RAMPRI_CPU0_RAM5_Pri8 (0x8UL) /!< Priority 8. /
jamesadevine	0:e1a608bb55e8	264	#define AMLI_RAMPRI_CPU0_RAM5_Pri10 (0xAUL) /!< Priority 10. /
jamesadevine	0:e1a608bb55e8	265	#define AMLI_RAMPRI_CPU0_RAM5_Pri12 (0xCUL) /!< Priority 12. /
jamesadevine	0:e1a608bb55e8	266	#define AMLI_RAMPRI_CPU0_RAM5_Pri14 (0xEUL) /!< Priority 14. /
jamesadevine	0:e1a608bb55e8	267
jamesadevine	0:e1a608bb55e8	268	/* Bits 19..16 : Configuration field for RAM block 4. */
jamesadevine	0:e1a608bb55e8	269	#define AMLI_RAMPRI_CPU0_RAM4_Pos (16UL) /!< Position of RAM4 field. /
jamesadevine	0:e1a608bb55e8	270	#define AMLI_RAMPRI_CPU0_RAM4_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM4_Pos) /!< Bit mask of RAM4 field. /
jamesadevine	0:e1a608bb55e8	271	#define AMLI_RAMPRI_CPU0_RAM4_Pri0 (0x0UL) /!< Priority 0. /
jamesadevine	0:e1a608bb55e8	272	#define AMLI_RAMPRI_CPU0_RAM4_Pri2 (0x2UL) /!< Priority 2. /
jamesadevine	0:e1a608bb55e8	273	#define AMLI_RAMPRI_CPU0_RAM4_Pri4 (0x4UL) /!< Priority 4. /
jamesadevine	0:e1a608bb55e8	274	#define AMLI_RAMPRI_CPU0_RAM4_Pri6 (0x6UL) /!< Priority 6. /
jamesadevine	0:e1a608bb55e8	275	#define AMLI_RAMPRI_CPU0_RAM4_Pri8 (0x8UL) /!< Priority 8. /
jamesadevine	0:e1a608bb55e8	276	#define AMLI_RAMPRI_CPU0_RAM4_Pri10 (0xAUL) /!< Priority 10. /
jamesadevine	0:e1a608bb55e8	277	#define AMLI_RAMPRI_CPU0_RAM4_Pri12 (0xCUL) /!< Priority 12. /
jamesadevine	0:e1a608bb55e8	278	#define AMLI_RAMPRI_CPU0_RAM4_Pri14 (0xEUL) /!< Priority 14. /
jamesadevine	0:e1a608bb55e8	279
jamesadevine	0:e1a608bb55e8	280	/* Bits 15..12 : Configuration field for RAM block 3. */
jamesadevine	0:e1a608bb55e8	281	#define AMLI_RAMPRI_CPU0_RAM3_Pos (12UL) /!< Position of RAM3 field. /
jamesadevine	0:e1a608bb55e8	282	#define AMLI_RAMPRI_CPU0_RAM3_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM3_Pos) /!< Bit mask of RAM3 field. /
jamesadevine	0:e1a608bb55e8	283	#define AMLI_RAMPRI_CPU0_RAM3_Pri0 (0x0UL) /!< Priority 0. /
jamesadevine	0:e1a608bb55e8	284	#define AMLI_RAMPRI_CPU0_RAM3_Pri2 (0x2UL) /!< Priority 2. /
jamesadevine	0:e1a608bb55e8	285	#define AMLI_RAMPRI_CPU0_RAM3_Pri4 (0x4UL) /!< Priority 4. /
jamesadevine	0:e1a608bb55e8	286	#define AMLI_RAMPRI_CPU0_RAM3_Pri6 (0x6UL) /!< Priority 6. /
jamesadevine	0:e1a608bb55e8	287	#define AMLI_RAMPRI_CPU0_RAM3_Pri8 (0x8UL) /!< Priority 8. /
jamesadevine	0:e1a608bb55e8	288	#define AMLI_RAMPRI_CPU0_RAM3_Pri10 (0xAUL) /!< Priority 10. /
jamesadevine	0:e1a608bb55e8	289	#define AMLI_RAMPRI_CPU0_RAM3_Pri12 (0xCUL) /!< Priority 12. /
jamesadevine	0:e1a608bb55e8	290	#define AMLI_RAMPRI_CPU0_RAM3_Pri14 (0xEUL) /!< Priority 14. /
jamesadevine	0:e1a608bb55e8	291
jamesadevine	0:e1a608bb55e8	292	/* Bits 11..8 : Configuration field for RAM block 2. */
jamesadevine	0:e1a608bb55e8	293	#define AMLI_RAMPRI_CPU0_RAM2_Pos (8UL) /!< Position of RAM2 field. /
jamesadevine	0:e1a608bb55e8	294	#define AMLI_RAMPRI_CPU0_RAM2_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM2_Pos) /!< Bit mask of RAM2 field. /
jamesadevine	0:e1a608bb55e8	295	#define AMLI_RAMPRI_CPU0_RAM2_Pri0 (0x0UL) /!< Priority 0. /
jamesadevine	0:e1a608bb55e8	296	#define AMLI_RAMPRI_CPU0_RAM2_Pri2 (0x2UL) /!< Priority 2. /
jamesadevine	0:e1a608bb55e8	297	#define AMLI_RAMPRI_CPU0_RAM2_Pri4 (0x4UL) /!< Priority 4. /
jamesadevine	0:e1a608bb55e8	298	#define AMLI_RAMPRI_CPU0_RAM2_Pri6 (0x6UL) /!< Priority 6. /
jamesadevine	0:e1a608bb55e8	299	#define AMLI_RAMPRI_CPU0_RAM2_Pri8 (0x8UL) /!< Priority 8. /
jamesadevine	0:e1a608bb55e8	300	#define AMLI_RAMPRI_CPU0_RAM2_Pri10 (0xAUL) /!< Priority 10. /
jamesadevine	0:e1a608bb55e8	301	#define AMLI_RAMPRI_CPU0_RAM2_Pri12 (0xCUL) /!< Priority 12. /
jamesadevine	0:e1a608bb55e8	302	#define AMLI_RAMPRI_CPU0_RAM2_Pri14 (0xEUL) /!< Priority 14. /
jamesadevine	0:e1a608bb55e8	303
jamesadevine	0:e1a608bb55e8	304	/* Bits 7..4 : Configuration field for RAM block 1. */
jamesadevine	0:e1a608bb55e8	305	#define AMLI_RAMPRI_CPU0_RAM1_Pos (4UL) /!< Position of RAM1 field. /
jamesadevine	0:e1a608bb55e8	306	#define AMLI_RAMPRI_CPU0_RAM1_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM1_Pos) /!< Bit mask of RAM1 field. /
jamesadevine	0:e1a608bb55e8	307	#define AMLI_RAMPRI_CPU0_RAM1_Pri0 (0x0UL) /!< Priority 0. /
jamesadevine	0:e1a608bb55e8	308	#define AMLI_RAMPRI_CPU0_RAM1_Pri2 (0x2UL) /!< Priority 2. /
jamesadevine	0:e1a608bb55e8	309	#define AMLI_RAMPRI_CPU0_RAM1_Pri4 (0x4UL) /!< Priority 4. /
jamesadevine	0:e1a608bb55e8	310	#define AMLI_RAMPRI_CPU0_RAM1_Pri6 (0x6UL) /!< Priority 6. /
jamesadevine	0:e1a608bb55e8	311	#define AMLI_RAMPRI_CPU0_RAM1_Pri8 (0x8UL) /!< Priority 8. /
jamesadevine	0:e1a608bb55e8	312	#define AMLI_RAMPRI_CPU0_RAM1_Pri10 (0xAUL) /!< Priority 10. /
jamesadevine	0:e1a608bb55e8	313	#define AMLI_RAMPRI_CPU0_RAM1_Pri12 (0xCUL) /!< Priority 12. /
jamesadevine	0:e1a608bb55e8	314	#define AMLI_RAMPRI_CPU0_RAM1_Pri14 (0xEUL) /!< Priority 14. /
jamesadevine	0:e1a608bb55e8	315
jamesadevine	0:e1a608bb55e8	316	/* Bits 3..0 : Configuration field for RAM block 0. */
jamesadevine	0:e1a608bb55e8	317	#define AMLI_RAMPRI_CPU0_RAM0_Pos (0UL) /!< Position of RAM0 field. /
jamesadevine	0:e1a608bb55e8	318	#define AMLI_RAMPRI_CPU0_RAM0_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM0_Pos) /!< Bit mask of RAM0 field. /
jamesadevine	0:e1a608bb55e8	319	#define AMLI_RAMPRI_CPU0_RAM0_Pri0 (0x0UL) /!< Priority 0. /
jamesadevine	0:e1a608bb55e8	320	#define AMLI_RAMPRI_CPU0_RAM0_Pri2 (0x2UL) /!< Priority 2. /
jamesadevine	0:e1a608bb55e8	321	#define AMLI_RAMPRI_CPU0_RAM0_Pri4 (0x4UL) /!< Priority 4. /
jamesadevine	0:e1a608bb55e8	322	#define AMLI_RAMPRI_CPU0_RAM0_Pri6 (0x6UL) /!< Priority 6. /
jamesadevine	0:e1a608bb55e8	323	#define AMLI_RAMPRI_CPU0_RAM0_Pri8 (0x8UL) /!< Priority 8. /
jamesadevine	0:e1a608bb55e8	324	#define AMLI_RAMPRI_CPU0_RAM0_Pri10 (0xAUL) /!< Priority 10. /
jamesadevine	0:e1a608bb55e8	325	#define AMLI_RAMPRI_CPU0_RAM0_Pri12 (0xCUL) /!< Priority 12. /
jamesadevine	0:e1a608bb55e8	326	#define AMLI_RAMPRI_CPU0_RAM0_Pri14 (0xEUL) /!< Priority 14. /
jamesadevine	0:e1a608bb55e8	327
jamesadevine	0:e1a608bb55e8	328	/* Register: AMLI_RAMPRI_SPIS1 */
jamesadevine	0:e1a608bb55e8	329	/* Description: Configurable priority configuration register for SPIS1. */
jamesadevine	0:e1a608bb55e8	330
jamesadevine	0:e1a608bb55e8	331	/* Bits 31..28 : Configuration field for RAM block 7. */
jamesadevine	0:e1a608bb55e8	332	#define AMLI_RAMPRI_SPIS1_RAM7_Pos (28UL) /!< Position of RAM7 field. /
jamesadevine	0:e1a608bb55e8	333	#define AMLI_RAMPRI_SPIS1_RAM7_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM7_Pos) /!< Bit mask of RAM7 field. /
jamesadevine	0:e1a608bb55e8	334	#define AMLI_RAMPRI_SPIS1_RAM7_Pri0 (0x0UL) /!< Priority 0. /
jamesadevine	0:e1a608bb55e8	335	#define AMLI_RAMPRI_SPIS1_RAM7_Pri2 (0x2UL) /!< Priority 2. /
jamesadevine	0:e1a608bb55e8	336	#define AMLI_RAMPRI_SPIS1_RAM7_Pri4 (0x4UL) /!< Priority 4. /
jamesadevine	0:e1a608bb55e8	337	#define AMLI_RAMPRI_SPIS1_RAM7_Pri6 (0x6UL) /!< Priority 6. /
jamesadevine	0:e1a608bb55e8	338	#define AMLI_RAMPRI_SPIS1_RAM7_Pri8 (0x8UL) /!< Priority 8. /
jamesadevine	0:e1a608bb55e8	339	#define AMLI_RAMPRI_SPIS1_RAM7_Pri10 (0xAUL) /!< Priority 10. /
jamesadevine	0:e1a608bb55e8	340	#define AMLI_RAMPRI_SPIS1_RAM7_Pri12 (0xCUL) /!< Priority 12. /
jamesadevine	0:e1a608bb55e8	341	#define AMLI_RAMPRI_SPIS1_RAM7_Pri14 (0xEUL) /!< Priority 14. /
jamesadevine	0:e1a608bb55e8	342
jamesadevine	0:e1a608bb55e8	343	/* Bits 27..24 : Configuration field for RAM block 6. */
jamesadevine	0:e1a608bb55e8	344	#define AMLI_RAMPRI_SPIS1_RAM6_Pos (24UL) /!< Position of RAM6 field. /
jamesadevine	0:e1a608bb55e8	345	#define AMLI_RAMPRI_SPIS1_RAM6_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM6_Pos) /!< Bit mask of RAM6 field. /
jamesadevine	0:e1a608bb55e8	346	#define AMLI_RAMPRI_SPIS1_RAM6_Pri0 (0x0UL) /!< Priority 0. /
jamesadevine	0:e1a608bb55e8	347	#define AMLI_RAMPRI_SPIS1_RAM6_Pri2 (0x2UL) /!< Priority 2. /
jamesadevine	0:e1a608bb55e8	348	#define AMLI_RAMPRI_SPIS1_RAM6_Pri4 (0x4UL) /!< Priority 4. /
jamesadevine	0:e1a608bb55e8	349	#define AMLI_RAMPRI_SPIS1_RAM6_Pri6 (0x6UL) /!< Priority 6. /
jamesadevine	0:e1a608bb55e8	350	#define AMLI_RAMPRI_SPIS1_RAM6_Pri8 (0x8UL) /!< Priority 8. /
jamesadevine	0:e1a608bb55e8	351	#define AMLI_RAMPRI_SPIS1_RAM6_Pri10 (0xAUL) /!< Priority 10. /
jamesadevine	0:e1a608bb55e8	352	#define AMLI_RAMPRI_SPIS1_RAM6_Pri12 (0xCUL) /!< Priority 12. /
jamesadevine	0:e1a608bb55e8	353	#define AMLI_RAMPRI_SPIS1_RAM6_Pri14 (0xEUL) /!< Priority 14. /
jamesadevine	0:e1a608bb55e8	354
jamesadevine	0:e1a608bb55e8	355	/* Bits 23..20 : Configuration field for RAM block 5. */
jamesadevine	0:e1a608bb55e8	356	#define AMLI_RAMPRI_SPIS1_RAM5_Pos (20UL) /!< Position of RAM5 field. /
jamesadevine	0:e1a608bb55e8	357	#define AMLI_RAMPRI_SPIS1_RAM5_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM5_Pos) /!< Bit mask of RAM5 field. /
jamesadevine	0:e1a608bb55e8	358	#define AMLI_RAMPRI_SPIS1_RAM5_Pri0 (0x0UL) /!< Priority 0. /
jamesadevine	0:e1a608bb55e8	359	#define AMLI_RAMPRI_SPIS1_RAM5_Pri2 (0x2UL) /!< Priority 2. /
jamesadevine	0:e1a608bb55e8	360	#define AMLI_RAMPRI_SPIS1_RAM5_Pri4 (0x4UL) /!< Priority 4. /
jamesadevine	0:e1a608bb55e8	361	#define AMLI_RAMPRI_SPIS1_RAM5_Pri6 (0x6UL) /!< Priority 6. /
jamesadevine	0:e1a608bb55e8	362	#define AMLI_RAMPRI_SPIS1_RAM5_Pri8 (0x8UL) /!< Priority 8. /
jamesadevine	0:e1a608bb55e8	363	#define AMLI_RAMPRI_SPIS1_RAM5_Pri10 (0xAUL) /!< Priority 10. /
jamesadevine	0:e1a608bb55e8	364	#define AMLI_RAMPRI_SPIS1_RAM5_Pri12 (0xCUL) /!< Priority 12. /
jamesadevine	0:e1a608bb55e8	365	#define AMLI_RAMPRI_SPIS1_RAM5_Pri14 (0xEUL) /!< Priority 14. /
jamesadevine	0:e1a608bb55e8	366
jamesadevine	0:e1a608bb55e8	367	/* Bits 19..16 : Configuration field for RAM block 4. */
jamesadevine	0:e1a608bb55e8	368	#define AMLI_RAMPRI_SPIS1_RAM4_Pos (16UL) /!< Position of RAM4 field. /
jamesadevine	0:e1a608bb55e8	369	#define AMLI_RAMPRI_SPIS1_RAM4_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM4_Pos) /!< Bit mask of RAM4 field. /
jamesadevine	0:e1a608bb55e8	370	#define AMLI_RAMPRI_SPIS1_RAM4_Pri0 (0x0UL) /!< Priority 0. /
jamesadevine	0:e1a608bb55e8	371	#define AMLI_RAMPRI_SPIS1_RAM4_Pri2 (0x2UL) /!< Priority 2. /
jamesadevine	0:e1a608bb55e8	372	#define AMLI_RAMPRI_SPIS1_RAM4_Pri4 (0x4UL) /!< Priority 4. /
jamesadevine	0:e1a608bb55e8	373	#define AMLI_RAMPRI_SPIS1_RAM4_Pri6 (0x6UL) /!< Priority 6. /
jamesadevine	0:e1a608bb55e8	374	#define AMLI_RAMPRI_SPIS1_RAM4_Pri8 (0x8UL) /!< Priority 8. /
jamesadevine	0:e1a608bb55e8	375	#define AMLI_RAMPRI_SPIS1_RAM4_Pri10 (0xAUL) /!< Priority 10. /
jamesadevine	0:e1a608bb55e8	376	#define AMLI_RAMPRI_SPIS1_RAM4_Pri12 (0xCUL) /!< Priority 12. /
jamesadevine	0:e1a608bb55e8	377	#define AMLI_RAMPRI_SPIS1_RAM4_Pri14 (0xEUL) /!< Priority 14. /
jamesadevine	0:e1a608bb55e8	378
jamesadevine	0:e1a608bb55e8	379	/* Bits 15..12 : Configuration field for RAM block 3. */
jamesadevine	0:e1a608bb55e8	380	#define AMLI_RAMPRI_SPIS1_RAM3_Pos (12UL) /!< Position of RAM3 field. /
jamesadevine	0:e1a608bb55e8	381	#define AMLI_RAMPRI_SPIS1_RAM3_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM3_Pos) /!< Bit mask of RAM3 field. /
jamesadevine	0:e1a608bb55e8	382	#define AMLI_RAMPRI_SPIS1_RAM3_Pri0 (0x0UL) /!< Priority 0. /
jamesadevine	0:e1a608bb55e8	383	#define AMLI_RAMPRI_SPIS1_RAM3_Pri2 (0x2UL) /!< Priority 2. /
jamesadevine	0:e1a608bb55e8	384	#define AMLI_RAMPRI_SPIS1_RAM3_Pri4 (0x4UL) /!< Priority 4. /
jamesadevine	0:e1a608bb55e8	385	#define AMLI_RAMPRI_SPIS1_RAM3_Pri6 (0x6UL) /!< Priority 6. /
jamesadevine	0:e1a608bb55e8	386	#define AMLI_RAMPRI_SPIS1_RAM3_Pri8 (0x8UL) /!< Priority 8. /
jamesadevine	0:e1a608bb55e8	387	#define AMLI_RAMPRI_SPIS1_RAM3_Pri10 (0xAUL) /!< Priority 10. /
jamesadevine	0:e1a608bb55e8	388	#define AMLI_RAMPRI_SPIS1_RAM3_Pri12 (0xCUL) /!< Priority 12. /
jamesadevine	0:e1a608bb55e8	389	#define AMLI_RAMPRI_SPIS1_RAM3_Pri14 (0xEUL) /!< Priority 14. /
jamesadevine	0:e1a608bb55e8	390
jamesadevine	0:e1a608bb55e8	391	/* Bits 11..8 : Configuration field for RAM block 2. */
jamesadevine	0:e1a608bb55e8	392	#define AMLI_RAMPRI_SPIS1_RAM2_Pos (8UL) /!< Position of RAM2 field. /
jamesadevine	0:e1a608bb55e8	393	#define AMLI_RAMPRI_SPIS1_RAM2_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM2_Pos) /!< Bit mask of RAM2 field. /
jamesadevine	0:e1a608bb55e8	394	#define AMLI_RAMPRI_SPIS1_RAM2_Pri0 (0x0UL) /!< Priority 0. /
jamesadevine	0:e1a608bb55e8	395	#define AMLI_RAMPRI_SPIS1_RAM2_Pri2 (0x2UL) /!< Priority 2. /
jamesadevine	0:e1a608bb55e8	396	#define AMLI_RAMPRI_SPIS1_RAM2_Pri4 (0x4UL) /!< Priority 4. /
jamesadevine	0:e1a608bb55e8	397	#define AMLI_RAMPRI_SPIS1_RAM2_Pri6 (0x6UL) /!< Priority 6. /
jamesadevine	0:e1a608bb55e8	398	#define AMLI_RAMPRI_SPIS1_RAM2_Pri8 (0x8UL) /!< Priority 8. /
jamesadevine	0:e1a608bb55e8	399	#define AMLI_RAMPRI_SPIS1_RAM2_Pri10 (0xAUL) /!< Priority 10. /
jamesadevine	0:e1a608bb55e8	400	#define AMLI_RAMPRI_SPIS1_RAM2_Pri12 (0xCUL) /!< Priority 12. /
jamesadevine	0:e1a608bb55e8	401	#define AMLI_RAMPRI_SPIS1_RAM2_Pri14 (0xEUL) /!< Priority 14. /
jamesadevine	0:e1a608bb55e8	402
jamesadevine	0:e1a608bb55e8	403	/* Bits 7..4 : Configuration field for RAM block 1. */
jamesadevine	0:e1a608bb55e8	404	#define AMLI_RAMPRI_SPIS1_RAM1_Pos (4UL) /!< Position of RAM1 field. /
jamesadevine	0:e1a608bb55e8	405	#define AMLI_RAMPRI_SPIS1_RAM1_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM1_Pos) /!< Bit mask of RAM1 field. /
jamesadevine	0:e1a608bb55e8	406	#define AMLI_RAMPRI_SPIS1_RAM1_Pri0 (0x0UL) /!< Priority 0. /
jamesadevine	0:e1a608bb55e8	407	#define AMLI_RAMPRI_SPIS1_RAM1_Pri2 (0x2UL) /!< Priority 2. /
jamesadevine	0:e1a608bb55e8	408	#define AMLI_RAMPRI_SPIS1_RAM1_Pri4 (0x4UL) /!< Priority 4. /
jamesadevine	0:e1a608bb55e8	409	#define AMLI_RAMPRI_SPIS1_RAM1_Pri6 (0x6UL) /!< Priority 6. /
jamesadevine	0:e1a608bb55e8	410	#define AMLI_RAMPRI_SPIS1_RAM1_Pri8 (0x8UL) /!< Priority 8. /
jamesadevine	0:e1a608bb55e8	411	#define AMLI_RAMPRI_SPIS1_RAM1_Pri10 (0xAUL) /!< Priority 10. /
jamesadevine	0:e1a608bb55e8	412	#define AMLI_RAMPRI_SPIS1_RAM1_Pri12 (0xCUL) /!< Priority 12. /
jamesadevine	0:e1a608bb55e8	413	#define AMLI_RAMPRI_SPIS1_RAM1_Pri14 (0xEUL) /!< Priority 14. /
jamesadevine	0:e1a608bb55e8	414
jamesadevine	0:e1a608bb55e8	415	/* Bits 3..0 : Configuration field for RAM block 0. */
jamesadevine	0:e1a608bb55e8	416	#define AMLI_RAMPRI_SPIS1_RAM0_Pos (0UL) /!< Position of RAM0 field. /
jamesadevine	0:e1a608bb55e8	417	#define AMLI_RAMPRI_SPIS1_RAM0_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM0_Pos) /!< Bit mask of RAM0 field. /
jamesadevine	0:e1a608bb55e8	418	#define AMLI_RAMPRI_SPIS1_RAM0_Pri0 (0x0UL) /!< Priority 0. /
jamesadevine	0:e1a608bb55e8	419	#define AMLI_RAMPRI_SPIS1_RAM0_Pri2 (0x2UL) /!< Priority 2. /
jamesadevine	0:e1a608bb55e8	420	#define AMLI_RAMPRI_SPIS1_RAM0_Pri4 (0x4UL) /!< Priority 4. /
jamesadevine	0:e1a608bb55e8	421	#define AMLI_RAMPRI_SPIS1_RAM0_Pri6 (0x6UL) /!< Priority 6. /
jamesadevine	0:e1a608bb55e8	422	#define AMLI_RAMPRI_SPIS1_RAM0_Pri8 (0x8UL) /!< Priority 8. /
jamesadevine	0:e1a608bb55e8	423	#define AMLI_RAMPRI_SPIS1_RAM0_Pri10 (0xAUL) /!< Priority 10. /
jamesadevine	0:e1a608bb55e8	424	#define AMLI_RAMPRI_SPIS1_RAM0_Pri12 (0xCUL) /!< Priority 12. /
jamesadevine	0:e1a608bb55e8	425	#define AMLI_RAMPRI_SPIS1_RAM0_Pri14 (0xEUL) /!< Priority 14. /
jamesadevine	0:e1a608bb55e8	426
jamesadevine	0:e1a608bb55e8	427	/* Register: AMLI_RAMPRI_RADIO */
jamesadevine	0:e1a608bb55e8	428	/* Description: Configurable priority configuration register for RADIO. */
jamesadevine	0:e1a608bb55e8	429
jamesadevine	0:e1a608bb55e8	430	/* Bits 31..28 : Configuration field for RAM block 7. */
jamesadevine	0:e1a608bb55e8	431	#define AMLI_RAMPRI_RADIO_RAM7_Pos (28UL) /!< Position of RAM7 field. /
jamesadevine	0:e1a608bb55e8	432	#define AMLI_RAMPRI_RADIO_RAM7_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM7_Pos) /!< Bit mask of RAM7 field. /
jamesadevine	0:e1a608bb55e8	433	#define AMLI_RAMPRI_RADIO_RAM7_Pri0 (0x0UL) /!< Priority 0. /
jamesadevine	0:e1a608bb55e8	434	#define AMLI_RAMPRI_RADIO_RAM7_Pri2 (0x2UL) /!< Priority 2. /
jamesadevine	0:e1a608bb55e8	435	#define AMLI_RAMPRI_RADIO_RAM7_Pri4 (0x4UL) /!< Priority 4. /
jamesadevine	0:e1a608bb55e8	436	#define AMLI_RAMPRI_RADIO_RAM7_Pri6 (0x6UL) /!< Priority 6. /
jamesadevine	0:e1a608bb55e8	437	#define AMLI_RAMPRI_RADIO_RAM7_Pri8 (0x8UL) /!< Priority 8. /
jamesadevine	0:e1a608bb55e8	438	#define AMLI_RAMPRI_RADIO_RAM7_Pri10 (0xAUL) /!< Priority 10. /
jamesadevine	0:e1a608bb55e8	439	#define AMLI_RAMPRI_RADIO_RAM7_Pri12 (0xCUL) /!< Priority 12. /
jamesadevine	0:e1a608bb55e8	440	#define AMLI_RAMPRI_RADIO_RAM7_Pri14 (0xEUL) /!< Priority 14. /
jamesadevine	0:e1a608bb55e8	441
jamesadevine	0:e1a608bb55e8	442	/* Bits 27..24 : Configuration field for RAM block 6. */
jamesadevine	0:e1a608bb55e8	443	#define AMLI_RAMPRI_RADIO_RAM6_Pos (24UL) /!< Position of RAM6 field. /
jamesadevine	0:e1a608bb55e8	444	#define AMLI_RAMPRI_RADIO_RAM6_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM6_Pos) /!< Bit mask of RAM6 field. /
jamesadevine	0:e1a608bb55e8	445	#define AMLI_RAMPRI_RADIO_RAM6_Pri0 (0x0UL) /!< Priority 0. /
jamesadevine	0:e1a608bb55e8	446	#define AMLI_RAMPRI_RADIO_RAM6_Pri2 (0x2UL) /!< Priority 2. /
jamesadevine	0:e1a608bb55e8	447	#define AMLI_RAMPRI_RADIO_RAM6_Pri4 (0x4UL) /!< Priority 4. /
jamesadevine	0:e1a608bb55e8	448	#define AMLI_RAMPRI_RADIO_RAM6_Pri6 (0x6UL) /!< Priority 6. /
jamesadevine	0:e1a608bb55e8	449	#define AMLI_RAMPRI_RADIO_RAM6_Pri8 (0x8UL) /!< Priority 8. /
jamesadevine	0:e1a608bb55e8	450	#define AMLI_RAMPRI_RADIO_RAM6_Pri10 (0xAUL) /!< Priority 10. /
jamesadevine	0:e1a608bb55e8	451	#define AMLI_RAMPRI_RADIO_RAM6_Pri12 (0xCUL) /!< Priority 12. /
jamesadevine	0:e1a608bb55e8	452	#define AMLI_RAMPRI_RADIO_RAM6_Pri14 (0xEUL) /!< Priority 14. /
jamesadevine	0:e1a608bb55e8	453
jamesadevine	0:e1a608bb55e8	454	/* Bits 23..20 : Configuration field for RAM block 5. */
jamesadevine	0:e1a608bb55e8	455	#define AMLI_RAMPRI_RADIO_RAM5_Pos (20UL) /!< Position of RAM5 field. /
jamesadevine	0:e1a608bb55e8	456	#define AMLI_RAMPRI_RADIO_RAM5_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM5_Pos) /!< Bit mask of RAM5 field. /
jamesadevine	0:e1a608bb55e8	457	#define AMLI_RAMPRI_RADIO_RAM5_Pri0 (0x0UL) /!< Priority 0. /
jamesadevine	0:e1a608bb55e8	458	#define AMLI_RAMPRI_RADIO_RAM5_Pri2 (0x2UL) /!< Priority 2. /
jamesadevine	0:e1a608bb55e8	459	#define AMLI_RAMPRI_RADIO_RAM5_Pri4 (0x4UL) /!< Priority 4. /
jamesadevine	0:e1a608bb55e8	460	#define AMLI_RAMPRI_RADIO_RAM5_Pri6 (0x6UL) /!< Priority 6. /
jamesadevine	0:e1a608bb55e8	461	#define AMLI_RAMPRI_RADIO_RAM5_Pri8 (0x8UL) /!< Priority 8. /
jamesadevine	0:e1a608bb55e8	462	#define AMLI_RAMPRI_RADIO_RAM5_Pri10 (0xAUL) /!< Priority 10. /
jamesadevine	0:e1a608bb55e8	463	#define AMLI_RAMPRI_RADIO_RAM5_Pri12 (0xCUL) /!< Priority 12. /
jamesadevine	0:e1a608bb55e8	464	#define AMLI_RAMPRI_RADIO_RAM5_Pri14 (0xEUL) /!< Priority 14. /
jamesadevine	0:e1a608bb55e8	465
jamesadevine	0:e1a608bb55e8	466	/* Bits 19..16 : Configuration field for RAM block 4. */
jamesadevine	0:e1a608bb55e8	467	#define AMLI_RAMPRI_RADIO_RAM4_Pos (16UL) /!< Position of RAM4 field. /
jamesadevine	0:e1a608bb55e8	468	#define AMLI_RAMPRI_RADIO_RAM4_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM4_Pos) /!< Bit mask of RAM4 field. /
jamesadevine	0:e1a608bb55e8	469	#define AMLI_RAMPRI_RADIO_RAM4_Pri0 (0x0UL) /!< Priority 0. /
jamesadevine	0:e1a608bb55e8	470	#define AMLI_RAMPRI_RADIO_RAM4_Pri2 (0x2UL) /!< Priority 2. /
jamesadevine	0:e1a608bb55e8	471	#define AMLI_RAMPRI_RADIO_RAM4_Pri4 (0x4UL) /!< Priority 4. /
jamesadevine	0:e1a608bb55e8	472	#define AMLI_RAMPRI_RADIO_RAM4_Pri6 (0x6UL) /!< Priority 6. /
jamesadevine	0:e1a608bb55e8	473	#define AMLI_RAMPRI_RADIO_RAM4_Pri8 (0x8UL) /!< Priority 8. /
jamesadevine	0:e1a608bb55e8	474	#define AMLI_RAMPRI_RADIO_RAM4_Pri10 (0xAUL) /!< Priority 10. /
jamesadevine	0:e1a608bb55e8	475	#define AMLI_RAMPRI_RADIO_RAM4_Pri12 (0xCUL) /!< Priority 12. /
jamesadevine	0:e1a608bb55e8	476	#define AMLI_RAMPRI_RADIO_RAM4_Pri14 (0xEUL) /!< Priority 14. /
jamesadevine	0:e1a608bb55e8	477
jamesadevine	0:e1a608bb55e8	478	/* Bits 15..12 : Configuration field for RAM block 3. */
jamesadevine	0:e1a608bb55e8	479	#define AMLI_RAMPRI_RADIO_RAM3_Pos (12UL) /!< Position of RAM3 field. /
jamesadevine	0:e1a608bb55e8	480	#define AMLI_RAMPRI_RADIO_RAM3_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM3_Pos) /!< Bit mask of RAM3 field. /
jamesadevine	0:e1a608bb55e8	481	#define AMLI_RAMPRI_RADIO_RAM3_Pri0 (0x0UL) /!< Priority 0. /
jamesadevine	0:e1a608bb55e8	482	#define AMLI_RAMPRI_RADIO_RAM3_Pri2 (0x2UL) /!< Priority 2. /
jamesadevine	0:e1a608bb55e8	483	#define AMLI_RAMPRI_RADIO_RAM3_Pri4 (0x4UL) /!< Priority 4. /
jamesadevine	0:e1a608bb55e8	484	#define AMLI_RAMPRI_RADIO_RAM3_Pri6 (0x6UL) /!< Priority 6. /
jamesadevine	0:e1a608bb55e8	485	#define AMLI_RAMPRI_RADIO_RAM3_Pri8 (0x8UL) /!< Priority 8. /
jamesadevine	0:e1a608bb55e8	486	#define AMLI_RAMPRI_RADIO_RAM3_Pri10 (0xAUL) /!< Priority 10. /
jamesadevine	0:e1a608bb55e8	487	#define AMLI_RAMPRI_RADIO_RAM3_Pri12 (0xCUL) /!< Priority 12. /
jamesadevine	0:e1a608bb55e8	488	#define AMLI_RAMPRI_RADIO_RAM3_Pri14 (0xEUL) /!< Priority 14. /
jamesadevine	0:e1a608bb55e8	489
jamesadevine	0:e1a608bb55e8	490	/* Bits 11..8 : Configuration field for RAM block 2. */
jamesadevine	0:e1a608bb55e8	491	#define AMLI_RAMPRI_RADIO_RAM2_Pos (8UL) /!< Position of RAM2 field. /
jamesadevine	0:e1a608bb55e8	492	#define AMLI_RAMPRI_RADIO_RAM2_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM2_Pos) /!< Bit mask of RAM2 field. /
jamesadevine	0:e1a608bb55e8	493	#define AMLI_RAMPRI_RADIO_RAM2_Pri0 (0x0UL) /!< Priority 0. /
jamesadevine	0:e1a608bb55e8	494	#define AMLI_RAMPRI_RADIO_RAM2_Pri2 (0x2UL) /!< Priority 2. /
jamesadevine	0:e1a608bb55e8	495	#define AMLI_RAMPRI_RADIO_RAM2_Pri4 (0x4UL) /!< Priority 4. /
jamesadevine	0:e1a608bb55e8	496	#define AMLI_RAMPRI_RADIO_RAM2_Pri6 (0x6UL) /!< Priority 6. /
jamesadevine	0:e1a608bb55e8	497	#define AMLI_RAMPRI_RADIO_RAM2_Pri8 (0x8UL) /!< Priority 8. /
jamesadevine	0:e1a608bb55e8	498	#define AMLI_RAMPRI_RADIO_RAM2_Pri10 (0xAUL) /!< Priority 10. /
jamesadevine	0:e1a608bb55e8	499	#define AMLI_RAMPRI_RADIO_RAM2_Pri12 (0xCUL) /!< Priority 12. /
jamesadevine	0:e1a608bb55e8	500	#define AMLI_RAMPRI_RADIO_RAM2_Pri14 (0xEUL) /!< Priority 14. /
jamesadevine	0:e1a608bb55e8	501
jamesadevine	0:e1a608bb55e8	502	/* Bits 7..4 : Configuration field for RAM block 1. */
jamesadevine	0:e1a608bb55e8	503	#define AMLI_RAMPRI_RADIO_RAM1_Pos (4UL) /!< Position of RAM1 field. /
jamesadevine	0:e1a608bb55e8	504	#define AMLI_RAMPRI_RADIO_RAM1_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM1_Pos) /!< Bit mask of RAM1 field. /
jamesadevine	0:e1a608bb55e8	505	#define AMLI_RAMPRI_RADIO_RAM1_Pri0 (0x0UL) /!< Priority 0. /
jamesadevine	0:e1a608bb55e8	506	#define AMLI_RAMPRI_RADIO_RAM1_Pri2 (0x2UL) /!< Priority 2. /
jamesadevine	0:e1a608bb55e8	507	#define AMLI_RAMPRI_RADIO_RAM1_Pri4 (0x4UL) /!< Priority 4. /
jamesadevine	0:e1a608bb55e8	508	#define AMLI_RAMPRI_RADIO_RAM1_Pri6 (0x6UL) /!< Priority 6. /
jamesadevine	0:e1a608bb55e8	509	#define AMLI_RAMPRI_RADIO_RAM1_Pri8 (0x8UL) /!< Priority 8. /
jamesadevine	0:e1a608bb55e8	510	#define AMLI_RAMPRI_RADIO_RAM1_Pri10 (0xAUL) /!< Priority 10. /
jamesadevine	0:e1a608bb55e8	511	#define AMLI_RAMPRI_RADIO_RAM1_Pri12 (0xCUL) /!< Priority 12. /
jamesadevine	0:e1a608bb55e8	512	#define AMLI_RAMPRI_RADIO_RAM1_Pri14 (0xEUL) /!< Priority 14. /
jamesadevine	0:e1a608bb55e8	513
jamesadevine	0:e1a608bb55e8	514	/* Bits 3..0 : Configuration field for RAM block 0. */
jamesadevine	0:e1a608bb55e8	515	#define AMLI_RAMPRI_RADIO_RAM0_Pos (0UL) /!< Position of RAM0 field. /
jamesadevine	0:e1a608bb55e8	516	#define AMLI_RAMPRI_RADIO_RAM0_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM0_Pos) /!< Bit mask of RAM0 field. /
jamesadevine	0:e1a608bb55e8	517	#define AMLI_RAMPRI_RADIO_RAM0_Pri0 (0x0UL) /!< Priority 0. /
jamesadevine	0:e1a608bb55e8	518	#define AMLI_RAMPRI_RADIO_RAM0_Pri2 (0x2UL) /!< Priority 2. /
jamesadevine	0:e1a608bb55e8	519	#define AMLI_RAMPRI_RADIO_RAM0_Pri4 (0x4UL) /!< Priority 4. /
jamesadevine	0:e1a608bb55e8	520	#define AMLI_RAMPRI_RADIO_RAM0_Pri6 (0x6UL) /!< Priority 6. /
jamesadevine	0:e1a608bb55e8	521	#define AMLI_RAMPRI_RADIO_RAM0_Pri8 (0x8UL) /!< Priority 8. /
jamesadevine	0:e1a608bb55e8	522	#define AMLI_RAMPRI_RADIO_RAM0_Pri10 (0xAUL) /!< Priority 10. /
jamesadevine	0:e1a608bb55e8	523	#define AMLI_RAMPRI_RADIO_RAM0_Pri12 (0xCUL) /!< Priority 12. /
jamesadevine	0:e1a608bb55e8	524	#define AMLI_RAMPRI_RADIO_RAM0_Pri14 (0xEUL) /!< Priority 14. /
jamesadevine	0:e1a608bb55e8	525
jamesadevine	0:e1a608bb55e8	526	/* Register: AMLI_RAMPRI_ECB */
jamesadevine	0:e1a608bb55e8	527	/* Description: Configurable priority configuration register for ECB. */
jamesadevine	0:e1a608bb55e8	528
jamesadevine	0:e1a608bb55e8	529	/* Bits 31..28 : Configuration field for RAM block 7. */
jamesadevine	0:e1a608bb55e8	530	#define AMLI_RAMPRI_ECB_RAM7_Pos (28UL) /!< Position of RAM7 field. /
jamesadevine	0:e1a608bb55e8	531	#define AMLI_RAMPRI_ECB_RAM7_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM7_Pos) /!< Bit mask of RAM7 field. /
jamesadevine	0:e1a608bb55e8	532	#define AMLI_RAMPRI_ECB_RAM7_Pri0 (0x0UL) /!< Priority 0. /
jamesadevine	0:e1a608bb55e8	533	#define AMLI_RAMPRI_ECB_RAM7_Pri2 (0x2UL) /!< Priority 2. /
jamesadevine	0:e1a608bb55e8	534	#define AMLI_RAMPRI_ECB_RAM7_Pri4 (0x4UL) /!< Priority 4. /
jamesadevine	0:e1a608bb55e8	535	#define AMLI_RAMPRI_ECB_RAM7_Pri6 (0x6UL) /!< Priority 6. /
jamesadevine	0:e1a608bb55e8	536	#define AMLI_RAMPRI_ECB_RAM7_Pri8 (0x8UL) /!< Priority 8. /
jamesadevine	0:e1a608bb55e8	537	#define AMLI_RAMPRI_ECB_RAM7_Pri10 (0xAUL) /!< Priority 10. /
jamesadevine	0:e1a608bb55e8	538	#define AMLI_RAMPRI_ECB_RAM7_Pri12 (0xCUL) /!< Priority 12. /
jamesadevine	0:e1a608bb55e8	539	#define AMLI_RAMPRI_ECB_RAM7_Pri14 (0xEUL) /!< Priority 14. /
jamesadevine	0:e1a608bb55e8	540
jamesadevine	0:e1a608bb55e8	541	/* Bits 27..24 : Configuration field for RAM block 6. */
jamesadevine	0:e1a608bb55e8	542	#define AMLI_RAMPRI_ECB_RAM6_Pos (24UL) /!< Position of RAM6 field. /
jamesadevine	0:e1a608bb55e8	543	#define AMLI_RAMPRI_ECB_RAM6_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM6_Pos) /!< Bit mask of RAM6 field. /
jamesadevine	0:e1a608bb55e8	544	#define AMLI_RAMPRI_ECB_RAM6_Pri0 (0x0UL) /!< Priority 0. /
jamesadevine	0:e1a608bb55e8	545	#define AMLI_RAMPRI_ECB_RAM6_Pri2 (0x2UL) /!< Priority 2. /
jamesadevine	0:e1a608bb55e8	546	#define AMLI_RAMPRI_ECB_RAM6_Pri4 (0x4UL) /!< Priority 4. /
jamesadevine	0:e1a608bb55e8	547	#define AMLI_RAMPRI_ECB_RAM6_Pri6 (0x6UL) /!< Priority 6. /
jamesadevine	0:e1a608bb55e8	548	#define AMLI_RAMPRI_ECB_RAM6_Pri8 (0x8UL) /!< Priority 8. /
jamesadevine	0:e1a608bb55e8	549	#define AMLI_RAMPRI_ECB_RAM6_Pri10 (0xAUL) /!< Priority 10. /
jamesadevine	0:e1a608bb55e8	550	#define AMLI_RAMPRI_ECB_RAM6_Pri12 (0xCUL) /!< Priority 12. /
jamesadevine	0:e1a608bb55e8	551	#define AMLI_RAMPRI_ECB_RAM6_Pri14 (0xEUL) /!< Priority 14. /
jamesadevine	0:e1a608bb55e8	552
jamesadevine	0:e1a608bb55e8	553	/* Bits 23..20 : Configuration field for RAM block 5. */
jamesadevine	0:e1a608bb55e8	554	#define AMLI_RAMPRI_ECB_RAM5_Pos (20UL) /!< Position of RAM5 field. /
jamesadevine	0:e1a608bb55e8	555	#define AMLI_RAMPRI_ECB_RAM5_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM5_Pos) /!< Bit mask of RAM5 field. /
jamesadevine	0:e1a608bb55e8	556	#define AMLI_RAMPRI_ECB_RAM5_Pri0 (0x0UL) /!< Priority 0. /
jamesadevine	0:e1a608bb55e8	557	#define AMLI_RAMPRI_ECB_RAM5_Pri2 (0x2UL) /!< Priority 2. /
jamesadevine	0:e1a608bb55e8	558	#define AMLI_RAMPRI_ECB_RAM5_Pri4 (0x4UL) /!< Priority 4. /
jamesadevine	0:e1a608bb55e8	559	#define AMLI_RAMPRI_ECB_RAM5_Pri6 (0x6UL) /!< Priority 6. /
jamesadevine	0:e1a608bb55e8	560	#define AMLI_RAMPRI_ECB_RAM5_Pri8 (0x8UL) /!< Priority 8. /
jamesadevine	0:e1a608bb55e8	561	#define AMLI_RAMPRI_ECB_RAM5_Pri10 (0xAUL) /!< Priority 10. /
jamesadevine	0:e1a608bb55e8	562	#define AMLI_RAMPRI_ECB_RAM5_Pri12 (0xCUL) /!< Priority 12. /
jamesadevine	0:e1a608bb55e8	563	#define AMLI_RAMPRI_ECB_RAM5_Pri14 (0xEUL) /!< Priority 14. /
jamesadevine	0:e1a608bb55e8	564
jamesadevine	0:e1a608bb55e8	565	/* Bits 19..16 : Configuration field for RAM block 4. */
jamesadevine	0:e1a608bb55e8	566	#define AMLI_RAMPRI_ECB_RAM4_Pos (16UL) /!< Position of RAM4 field. /
jamesadevine	0:e1a608bb55e8	567	#define AMLI_RAMPRI_ECB_RAM4_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM4_Pos) /!< Bit mask of RAM4 field. /
jamesadevine	0:e1a608bb55e8	568	#define AMLI_RAMPRI_ECB_RAM4_Pri0 (0x0UL) /!< Priority 0. /
jamesadevine	0:e1a608bb55e8	569	#define AMLI_RAMPRI_ECB_RAM4_Pri2 (0x2UL) /!< Priority 2. /
jamesadevine	0:e1a608bb55e8	570	#define AMLI_RAMPRI_ECB_RAM4_Pri4 (0x4UL) /!< Priority 4. /
jamesadevine	0:e1a608bb55e8	571	#define AMLI_RAMPRI_ECB_RAM4_Pri6 (0x6UL) /!< Priority 6. /
jamesadevine	0:e1a608bb55e8	572	#define AMLI_RAMPRI_ECB_RAM4_Pri8 (0x8UL) /!< Priority 8. /
jamesadevine	0:e1a608bb55e8	573	#define AMLI_RAMPRI_ECB_RAM4_Pri10 (0xAUL) /!< Priority 10. /
jamesadevine	0:e1a608bb55e8	574	#define AMLI_RAMPRI_ECB_RAM4_Pri12 (0xCUL) /!< Priority 12. /
jamesadevine	0:e1a608bb55e8	575	#define AMLI_RAMPRI_ECB_RAM4_Pri14 (0xEUL) /!< Priority 14. /
jamesadevine	0:e1a608bb55e8	576
jamesadevine	0:e1a608bb55e8	577	/* Bits 15..12 : Configuration field for RAM block 3. */
jamesadevine	0:e1a608bb55e8	578	#define AMLI_RAMPRI_ECB_RAM3_Pos (12UL) /!< Position of RAM3 field. /
jamesadevine	0:e1a608bb55e8	579	#define AMLI_RAMPRI_ECB_RAM3_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM3_Pos) /!< Bit mask of RAM3 field. /
jamesadevine	0:e1a608bb55e8	580	#define AMLI_RAMPRI_ECB_RAM3_Pri0 (0x0UL) /!< Priority 0. /
jamesadevine	0:e1a608bb55e8	581	#define AMLI_RAMPRI_ECB_RAM3_Pri2 (0x2UL) /!< Priority 2. /
jamesadevine	0:e1a608bb55e8	582	#define AMLI_RAMPRI_ECB_RAM3_Pri4 (0x4UL) /!< Priority 4. /
jamesadevine	0:e1a608bb55e8	583	#define AMLI_RAMPRI_ECB_RAM3_Pri6 (0x6UL) /!< Priority 6. /
jamesadevine	0:e1a608bb55e8	584	#define AMLI_RAMPRI_ECB_RAM3_Pri8 (0x8UL) /!< Priority 8. /
jamesadevine	0:e1a608bb55e8	585	#define AMLI_RAMPRI_ECB_RAM3_Pri10 (0xAUL) /!< Priority 10. /
jamesadevine	0:e1a608bb55e8	586	#define AMLI_RAMPRI_ECB_RAM3_Pri12 (0xCUL) /!< Priority 12. /
jamesadevine	0:e1a608bb55e8	587	#define AMLI_RAMPRI_ECB_RAM3_Pri14 (0xEUL) /!< Priority 14. /
jamesadevine	0:e1a608bb55e8	588
jamesadevine	0:e1a608bb55e8	589	/* Bits 11..8 : Configuration field for RAM block 2. */
jamesadevine	0:e1a608bb55e8	590	#define AMLI_RAMPRI_ECB_RAM2_Pos (8UL) /!< Position of RAM2 field. /
jamesadevine	0:e1a608bb55e8	591	#define AMLI_RAMPRI_ECB_RAM2_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM2_Pos) /!< Bit mask of RAM2 field. /
jamesadevine	0:e1a608bb55e8	592	#define AMLI_RAMPRI_ECB_RAM2_Pri0 (0x0UL) /!< Priority 0. /
jamesadevine	0:e1a608bb55e8	593	#define AMLI_RAMPRI_ECB_RAM2_Pri2 (0x2UL) /!< Priority 2. /
jamesadevine	0:e1a608bb55e8	594	#define AMLI_RAMPRI_ECB_RAM2_Pri4 (0x4UL) /!< Priority 4. /
jamesadevine	0:e1a608bb55e8	595	#define AMLI_RAMPRI_ECB_RAM2_Pri6 (0x6UL) /!< Priority 6. /
jamesadevine	0:e1a608bb55e8	596	#define AMLI_RAMPRI_ECB_RAM2_Pri8 (0x8UL) /!< Priority 8. /
jamesadevine	0:e1a608bb55e8	597	#define AMLI_RAMPRI_ECB_RAM2_Pri10 (0xAUL) /!< Priority 10. /
jamesadevine	0:e1a608bb55e8	598	#define AMLI_RAMPRI_ECB_RAM2_Pri12 (0xCUL) /!< Priority 12. /
jamesadevine	0:e1a608bb55e8	599	#define AMLI_RAMPRI_ECB_RAM2_Pri14 (0xEUL) /!< Priority 14. /
jamesadevine	0:e1a608bb55e8	600
jamesadevine	0:e1a608bb55e8	601	/* Bits 7..4 : Configuration field for RAM block 1. */
jamesadevine	0:e1a608bb55e8	602	#define AMLI_RAMPRI_ECB_RAM1_Pos (4UL) /!< Position of RAM1 field. /
jamesadevine	0:e1a608bb55e8	603	#define AMLI_RAMPRI_ECB_RAM1_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM1_Pos) /!< Bit mask of RAM1 field. /
jamesadevine	0:e1a608bb55e8	604	#define AMLI_RAMPRI_ECB_RAM1_Pri0 (0x0UL) /!< Priority 0. /
jamesadevine	0:e1a608bb55e8	605	#define AMLI_RAMPRI_ECB_RAM1_Pri2 (0x2UL) /!< Priority 2. /
jamesadevine	0:e1a608bb55e8	606	#define AMLI_RAMPRI_ECB_RAM1_Pri4 (0x4UL) /!< Priority 4. /
jamesadevine	0:e1a608bb55e8	607	#define AMLI_RAMPRI_ECB_RAM1_Pri6 (0x6UL) /!< Priority 6. /
jamesadevine	0:e1a608bb55e8	608	#define AMLI_RAMPRI_ECB_RAM1_Pri8 (0x8UL) /!< Priority 8. /
jamesadevine	0:e1a608bb55e8	609	#define AMLI_RAMPRI_ECB_RAM1_Pri10 (0xAUL) /!< Priority 10. /
jamesadevine	0:e1a608bb55e8	610	#define AMLI_RAMPRI_ECB_RAM1_Pri12 (0xCUL) /!< Priority 12. /
jamesadevine	0:e1a608bb55e8	611	#define AMLI_RAMPRI_ECB_RAM1_Pri14 (0xEUL) /!< Priority 14. /
jamesadevine	0:e1a608bb55e8	612
jamesadevine	0:e1a608bb55e8	613	/* Bits 3..0 : Configuration field for RAM block 0. */
jamesadevine	0:e1a608bb55e8	614	#define AMLI_RAMPRI_ECB_RAM0_Pos (0UL) /!< Position of RAM0 field. /
jamesadevine	0:e1a608bb55e8	615	#define AMLI_RAMPRI_ECB_RAM0_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM0_Pos) /!< Bit mask of RAM0 field. /
jamesadevine	0:e1a608bb55e8	616	#define AMLI_RAMPRI_ECB_RAM0_Pri0 (0x0UL) /!< Priority 0. /
jamesadevine	0:e1a608bb55e8	617	#define AMLI_RAMPRI_ECB_RAM0_Pri2 (0x2UL) /!< Priority 2. /
jamesadevine	0:e1a608bb55e8	618	#define AMLI_RAMPRI_ECB_RAM0_Pri4 (0x4UL) /!< Priority 4. /
jamesadevine	0:e1a608bb55e8	619	#define AMLI_RAMPRI_ECB_RAM0_Pri6 (0x6UL) /!< Priority 6. /
jamesadevine	0:e1a608bb55e8	620	#define AMLI_RAMPRI_ECB_RAM0_Pri8 (0x8UL) /!< Priority 8. /
jamesadevine	0:e1a608bb55e8	621	#define AMLI_RAMPRI_ECB_RAM0_Pri10 (0xAUL) /!< Priority 10. /
jamesadevine	0:e1a608bb55e8	622	#define AMLI_RAMPRI_ECB_RAM0_Pri12 (0xCUL) /!< Priority 12. /
jamesadevine	0:e1a608bb55e8	623	#define AMLI_RAMPRI_ECB_RAM0_Pri14 (0xEUL) /!< Priority 14. /
jamesadevine	0:e1a608bb55e8	624
jamesadevine	0:e1a608bb55e8	625	/* Register: AMLI_RAMPRI_CCM */
jamesadevine	0:e1a608bb55e8	626	/* Description: Configurable priority configuration register for CCM. */
jamesadevine	0:e1a608bb55e8	627
jamesadevine	0:e1a608bb55e8	628	/* Bits 31..28 : Configuration field for RAM block 7. */
jamesadevine	0:e1a608bb55e8	629	#define AMLI_RAMPRI_CCM_RAM7_Pos (28UL) /!< Position of RAM7 field. /
jamesadevine	0:e1a608bb55e8	630	#define AMLI_RAMPRI_CCM_RAM7_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM7_Pos) /!< Bit mask of RAM7 field. /
jamesadevine	0:e1a608bb55e8	631	#define AMLI_RAMPRI_CCM_RAM7_Pri0 (0x0UL) /!< Priority 0. /
jamesadevine	0:e1a608bb55e8	632	#define AMLI_RAMPRI_CCM_RAM7_Pri2 (0x2UL) /!< Priority 2. /
jamesadevine	0:e1a608bb55e8	633	#define AMLI_RAMPRI_CCM_RAM7_Pri4 (0x4UL) /!< Priority 4. /
jamesadevine	0:e1a608bb55e8	634	#define AMLI_RAMPRI_CCM_RAM7_Pri6 (0x6UL) /!< Priority 6. /
jamesadevine	0:e1a608bb55e8	635	#define AMLI_RAMPRI_CCM_RAM7_Pri8 (0x8UL) /!< Priority 8. /
jamesadevine	0:e1a608bb55e8	636	#define AMLI_RAMPRI_CCM_RAM7_Pri10 (0xAUL) /!< Priority 10. /
jamesadevine	0:e1a608bb55e8	637	#define AMLI_RAMPRI_CCM_RAM7_Pri12 (0xCUL) /!< Priority 12. /
jamesadevine	0:e1a608bb55e8	638	#define AMLI_RAMPRI_CCM_RAM7_Pri14 (0xEUL) /!< Priority 14. /
jamesadevine	0:e1a608bb55e8	639
jamesadevine	0:e1a608bb55e8	640	/* Bits 27..24 : Configuration field for RAM block 6. */
jamesadevine	0:e1a608bb55e8	641	#define AMLI_RAMPRI_CCM_RAM6_Pos (24UL) /!< Position of RAM6 field. /
jamesadevine	0:e1a608bb55e8	642	#define AMLI_RAMPRI_CCM_RAM6_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM6_Pos) /!< Bit mask of RAM6 field. /
jamesadevine	0:e1a608bb55e8	643	#define AMLI_RAMPRI_CCM_RAM6_Pri0 (0x0UL) /!< Priority 0. /
jamesadevine	0:e1a608bb55e8	644	#define AMLI_RAMPRI_CCM_RAM6_Pri2 (0x2UL) /!< Priority 2. /
jamesadevine	0:e1a608bb55e8	645	#define AMLI_RAMPRI_CCM_RAM6_Pri4 (0x4UL) /!< Priority 4. /
jamesadevine	0:e1a608bb55e8	646	#define AMLI_RAMPRI_CCM_RAM6_Pri6 (0x6UL) /!< Priority 6. /
jamesadevine	0:e1a608bb55e8	647	#define AMLI_RAMPRI_CCM_RAM6_Pri8 (0x8UL) /!< Priority 8. /
jamesadevine	0:e1a608bb55e8	648	#define AMLI_RAMPRI_CCM_RAM6_Pri10 (0xAUL) /!< Priority 10. /
jamesadevine	0:e1a608bb55e8	649	#define AMLI_RAMPRI_CCM_RAM6_Pri12 (0xCUL) /!< Priority 12. /
jamesadevine	0:e1a608bb55e8	650	#define AMLI_RAMPRI_CCM_RAM6_Pri14 (0xEUL) /!< Priority 14. /
jamesadevine	0:e1a608bb55e8	651
jamesadevine	0:e1a608bb55e8	652	/* Bits 23..20 : Configuration field for RAM block 5. */
jamesadevine	0:e1a608bb55e8	653	#define AMLI_RAMPRI_CCM_RAM5_Pos (20UL) /!< Position of RAM5 field. /
jamesadevine	0:e1a608bb55e8	654	#define AMLI_RAMPRI_CCM_RAM5_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM5_Pos) /!< Bit mask of RAM5 field. /
jamesadevine	0:e1a608bb55e8	655	#define AMLI_RAMPRI_CCM_RAM5_Pri0 (0x0UL) /!< Priority 0. /
jamesadevine	0:e1a608bb55e8	656	#define AMLI_RAMPRI_CCM_RAM5_Pri2 (0x2UL) /!< Priority 2. /
jamesadevine	0:e1a608bb55e8	657	#define AMLI_RAMPRI_CCM_RAM5_Pri4 (0x4UL) /!< Priority 4. /
jamesadevine	0:e1a608bb55e8	658	#define AMLI_RAMPRI_CCM_RAM5_Pri6 (0x6UL) /!< Priority 6. /
jamesadevine	0:e1a608bb55e8	659	#define AMLI_RAMPRI_CCM_RAM5_Pri8 (0x8UL) /!< Priority 8. /
jamesadevine	0:e1a608bb55e8	660	#define AMLI_RAMPRI_CCM_RAM5_Pri10 (0xAUL) /!< Priority 10. /
jamesadevine	0:e1a608bb55e8	661	#define AMLI_RAMPRI_CCM_RAM5_Pri12 (0xCUL) /!< Priority 12. /
jamesadevine	0:e1a608bb55e8	662	#define AMLI_RAMPRI_CCM_RAM5_Pri14 (0xEUL) /!< Priority 14. /
jamesadevine	0:e1a608bb55e8	663
jamesadevine	0:e1a608bb55e8	664	/* Bits 19..16 : Configuration field for RAM block 4. */
jamesadevine	0:e1a608bb55e8	665	#define AMLI_RAMPRI_CCM_RAM4_Pos (16UL) /!< Position of RAM4 field. /
jamesadevine	0:e1a608bb55e8	666	#define AMLI_RAMPRI_CCM_RAM4_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM4_Pos) /!< Bit mask of RAM4 field. /
jamesadevine	0:e1a608bb55e8	667	#define AMLI_RAMPRI_CCM_RAM4_Pri0 (0x0UL) /!< Priority 0. /
jamesadevine	0:e1a608bb55e8	668	#define AMLI_RAMPRI_CCM_RAM4_Pri2 (0x2UL) /!< Priority 2. /
jamesadevine	0:e1a608bb55e8	669	#define AMLI_RAMPRI_CCM_RAM4_Pri4 (0x4UL) /!< Priority 4. /
jamesadevine	0:e1a608bb55e8	670	#define AMLI_RAMPRI_CCM_RAM4_Pri6 (0x6UL) /!< Priority 6. /
jamesadevine	0:e1a608bb55e8	671	#define AMLI_RAMPRI_CCM_RAM4_Pri8 (0x8UL) /!< Priority 8. /
jamesadevine	0:e1a608bb55e8	672	#define AMLI_RAMPRI_CCM_RAM4_Pri10 (0xAUL) /!< Priority 10. /
jamesadevine	0:e1a608bb55e8	673	#define AMLI_RAMPRI_CCM_RAM4_Pri12 (0xCUL) /!< Priority 12. /
jamesadevine	0:e1a608bb55e8	674	#define AMLI_RAMPRI_CCM_RAM4_Pri14 (0xEUL) /!< Priority 14. /
jamesadevine	0:e1a608bb55e8	675
jamesadevine	0:e1a608bb55e8	676	/* Bits 15..12 : Configuration field for RAM block 3. */
jamesadevine	0:e1a608bb55e8	677	#define AMLI_RAMPRI_CCM_RAM3_Pos (12UL) /!< Position of RAM3 field. /
jamesadevine	0:e1a608bb55e8	678	#define AMLI_RAMPRI_CCM_RAM3_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM3_Pos) /!< Bit mask of RAM3 field. /
jamesadevine	0:e1a608bb55e8	679	#define AMLI_RAMPRI_CCM_RAM3_Pri0 (0x0UL) /!< Priority 0. /
jamesadevine	0:e1a608bb55e8	680	#define AMLI_RAMPRI_CCM_RAM3_Pri2 (0x2UL) /!< Priority 2. /
jamesadevine	0:e1a608bb55e8	681	#define AMLI_RAMPRI_CCM_RAM3_Pri4 (0x4UL) /!< Priority 4. /
jamesadevine	0:e1a608bb55e8	682	#define AMLI_RAMPRI_CCM_RAM3_Pri6 (0x6UL) /!< Priority 6. /
jamesadevine	0:e1a608bb55e8	683	#define AMLI_RAMPRI_CCM_RAM3_Pri8 (0x8UL) /!< Priority 8. /
jamesadevine	0:e1a608bb55e8	684	#define AMLI_RAMPRI_CCM_RAM3_Pri10 (0xAUL) /!< Priority 10. /
jamesadevine	0:e1a608bb55e8	685	#define AMLI_RAMPRI_CCM_RAM3_Pri12 (0xCUL) /!< Priority 12. /
jamesadevine	0:e1a608bb55e8	686	#define AMLI_RAMPRI_CCM_RAM3_Pri14 (0xEUL) /!< Priority 14. /
jamesadevine	0:e1a608bb55e8	687
jamesadevine	0:e1a608bb55e8	688	/* Bits 11..8 : Configuration field for RAM block 2. */
jamesadevine	0:e1a608bb55e8	689	#define AMLI_RAMPRI_CCM_RAM2_Pos (8UL) /!< Position of RAM2 field. /
jamesadevine	0:e1a608bb55e8	690	#define AMLI_RAMPRI_CCM_RAM2_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM2_Pos) /!< Bit mask of RAM2 field. /
jamesadevine	0:e1a608bb55e8	691	#define AMLI_RAMPRI_CCM_RAM2_Pri0 (0x0UL) /!< Priority 0. /
jamesadevine	0:e1a608bb55e8	692	#define AMLI_RAMPRI_CCM_RAM2_Pri2 (0x2UL) /!< Priority 2. /
jamesadevine	0:e1a608bb55e8	693	#define AMLI_RAMPRI_CCM_RAM2_Pri4 (0x4UL) /!< Priority 4. /
jamesadevine	0:e1a608bb55e8	694	#define AMLI_RAMPRI_CCM_RAM2_Pri6 (0x6UL) /!< Priority 6. /
jamesadevine	0:e1a608bb55e8	695	#define AMLI_RAMPRI_CCM_RAM2_Pri8 (0x8UL) /!< Priority 8. /
jamesadevine	0:e1a608bb55e8	696	#define AMLI_RAMPRI_CCM_RAM2_Pri10 (0xAUL) /!< Priority 10. /
jamesadevine	0:e1a608bb55e8	697	#define AMLI_RAMPRI_CCM_RAM2_Pri12 (0xCUL) /!< Priority 12. /
jamesadevine	0:e1a608bb55e8	698	#define AMLI_RAMPRI_CCM_RAM2_Pri14 (0xEUL) /!< Priority 14. /
jamesadevine	0:e1a608bb55e8	699
jamesadevine	0:e1a608bb55e8	700	/* Bits 7..4 : Configuration field for RAM block 1. */
jamesadevine	0:e1a608bb55e8	701	#define AMLI_RAMPRI_CCM_RAM1_Pos (4UL) /!< Position of RAM1 field. /
jamesadevine	0:e1a608bb55e8	702	#define AMLI_RAMPRI_CCM_RAM1_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM1_Pos) /!< Bit mask of RAM1 field. /
jamesadevine	0:e1a608bb55e8	703	#define AMLI_RAMPRI_CCM_RAM1_Pri0 (0x0UL) /!< Priority 0. /
jamesadevine	0:e1a608bb55e8	704	#define AMLI_RAMPRI_CCM_RAM1_Pri2 (0x2UL) /!< Priority 2. /
jamesadevine	0:e1a608bb55e8	705	#define AMLI_RAMPRI_CCM_RAM1_Pri4 (0x4UL) /!< Priority 4. /
jamesadevine	0:e1a608bb55e8	706	#define AMLI_RAMPRI_CCM_RAM1_Pri6 (0x6UL) /!< Priority 6. /
jamesadevine	0:e1a608bb55e8	707	#define AMLI_RAMPRI_CCM_RAM1_Pri8 (0x8UL) /!< Priority 8. /
jamesadevine	0:e1a608bb55e8	708	#define AMLI_RAMPRI_CCM_RAM1_Pri10 (0xAUL) /!< Priority 10. /
jamesadevine	0:e1a608bb55e8	709	#define AMLI_RAMPRI_CCM_RAM1_Pri12 (0xCUL) /!< Priority 12. /
jamesadevine	0:e1a608bb55e8	710	#define AMLI_RAMPRI_CCM_RAM1_Pri14 (0xEUL) /!< Priority 14. /
jamesadevine	0:e1a608bb55e8	711
jamesadevine	0:e1a608bb55e8	712	/* Bits 3..0 : Configuration field for RAM block 0. */
jamesadevine	0:e1a608bb55e8	713	#define AMLI_RAMPRI_CCM_RAM0_Pos (0UL) /!< Position of RAM0 field. /
jamesadevine	0:e1a608bb55e8	714	#define AMLI_RAMPRI_CCM_RAM0_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM0_Pos) /!< Bit mask of RAM0 field. /
jamesadevine	0:e1a608bb55e8	715	#define AMLI_RAMPRI_CCM_RAM0_Pri0 (0x0UL) /!< Priority 0. /
jamesadevine	0:e1a608bb55e8	716	#define AMLI_RAMPRI_CCM_RAM0_Pri2 (0x2UL) /!< Priority 2. /
jamesadevine	0:e1a608bb55e8	717	#define AMLI_RAMPRI_CCM_RAM0_Pri4 (0x4UL) /!< Priority 4. /
jamesadevine	0:e1a608bb55e8	718	#define AMLI_RAMPRI_CCM_RAM0_Pri6 (0x6UL) /!< Priority 6. /
jamesadevine	0:e1a608bb55e8	719	#define AMLI_RAMPRI_CCM_RAM0_Pri8 (0x8UL) /!< Priority 8. /
jamesadevine	0:e1a608bb55e8	720	#define AMLI_RAMPRI_CCM_RAM0_Pri10 (0xAUL) /!< Priority 10. /
jamesadevine	0:e1a608bb55e8	721	#define AMLI_RAMPRI_CCM_RAM0_Pri12 (0xCUL) /!< Priority 12. /
jamesadevine	0:e1a608bb55e8	722	#define AMLI_RAMPRI_CCM_RAM0_Pri14 (0xEUL) /!< Priority 14. /
jamesadevine	0:e1a608bb55e8	723
jamesadevine	0:e1a608bb55e8	724	/* Register: AMLI_RAMPRI_AAR */
jamesadevine	0:e1a608bb55e8	725	/* Description: Configurable priority configuration register for AAR. */
jamesadevine	0:e1a608bb55e8	726
jamesadevine	0:e1a608bb55e8	727	/* Bits 31..28 : Configuration field for RAM block 7. */
jamesadevine	0:e1a608bb55e8	728	#define AMLI_RAMPRI_AAR_RAM7_Pos (28UL) /!< Position of RAM7 field. /
jamesadevine	0:e1a608bb55e8	729	#define AMLI_RAMPRI_AAR_RAM7_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM7_Pos) /!< Bit mask of RAM7 field. /
jamesadevine	0:e1a608bb55e8	730	#define AMLI_RAMPRI_AAR_RAM7_Pri0 (0x0UL) /!< Priority 0. /
jamesadevine	0:e1a608bb55e8	731	#define AMLI_RAMPRI_AAR_RAM7_Pri2 (0x2UL) /!< Priority 2. /
jamesadevine	0:e1a608bb55e8	732	#define AMLI_RAMPRI_AAR_RAM7_Pri4 (0x4UL) /!< Priority 4. /
jamesadevine	0:e1a608bb55e8	733	#define AMLI_RAMPRI_AAR_RAM7_Pri6 (0x6UL) /!< Priority 6. /
jamesadevine	0:e1a608bb55e8	734	#define AMLI_RAMPRI_AAR_RAM7_Pri8 (0x8UL) /!< Priority 8. /
jamesadevine	0:e1a608bb55e8	735	#define AMLI_RAMPRI_AAR_RAM7_Pri10 (0xAUL) /!< Priority 10. /
jamesadevine	0:e1a608bb55e8	736	#define AMLI_RAMPRI_AAR_RAM7_Pri12 (0xCUL) /!< Priority 12. /
jamesadevine	0:e1a608bb55e8	737	#define AMLI_RAMPRI_AAR_RAM7_Pri14 (0xEUL) /!< Priority 14. /
jamesadevine	0:e1a608bb55e8	738
jamesadevine	0:e1a608bb55e8	739	/* Bits 27..24 : Configuration field for RAM block 6. */
jamesadevine	0:e1a608bb55e8	740	#define AMLI_RAMPRI_AAR_RAM6_Pos (24UL) /!< Position of RAM6 field. /
jamesadevine	0:e1a608bb55e8	741	#define AMLI_RAMPRI_AAR_RAM6_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM6_Pos) /!< Bit mask of RAM6 field. /
jamesadevine	0:e1a608bb55e8	742	#define AMLI_RAMPRI_AAR_RAM6_Pri0 (0x0UL) /!< Priority 0. /
jamesadevine	0:e1a608bb55e8	743	#define AMLI_RAMPRI_AAR_RAM6_Pri2 (0x2UL) /!< Priority 2. /
jamesadevine	0:e1a608bb55e8	744	#define AMLI_RAMPRI_AAR_RAM6_Pri4 (0x4UL) /!< Priority 4. /
jamesadevine	0:e1a608bb55e8	745	#define AMLI_RAMPRI_AAR_RAM6_Pri6 (0x6UL) /!< Priority 6. /
jamesadevine	0:e1a608bb55e8	746	#define AMLI_RAMPRI_AAR_RAM6_Pri8 (0x8UL) /!< Priority 8. /
jamesadevine	0:e1a608bb55e8	747	#define AMLI_RAMPRI_AAR_RAM6_Pri10 (0xAUL) /!< Priority 10. /
jamesadevine	0:e1a608bb55e8	748	#define AMLI_RAMPRI_AAR_RAM6_Pri12 (0xCUL) /!< Priority 12. /
jamesadevine	0:e1a608bb55e8	749	#define AMLI_RAMPRI_AAR_RAM6_Pri14 (0xEUL) /!< Priority 14. /
jamesadevine	0:e1a608bb55e8	750
jamesadevine	0:e1a608bb55e8	751	/* Bits 23..20 : Configuration field for RAM block 5. */
jamesadevine	0:e1a608bb55e8	752	#define AMLI_RAMPRI_AAR_RAM5_Pos (20UL) /!< Position of RAM5 field. /
jamesadevine	0:e1a608bb55e8	753	#define AMLI_RAMPRI_AAR_RAM5_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM5_Pos) /!< Bit mask of RAM5 field. /
jamesadevine	0:e1a608bb55e8	754	#define AMLI_RAMPRI_AAR_RAM5_Pri0 (0x0UL) /!< Priority 0. /
jamesadevine	0:e1a608bb55e8	755	#define AMLI_RAMPRI_AAR_RAM5_Pri2 (0x2UL) /!< Priority 2. /
jamesadevine	0:e1a608bb55e8	756	#define AMLI_RAMPRI_AAR_RAM5_Pri4 (0x4UL) /!< Priority 4. /
jamesadevine	0:e1a608bb55e8	757	#define AMLI_RAMPRI_AAR_RAM5_Pri6 (0x6UL) /!< Priority 6. /
jamesadevine	0:e1a608bb55e8	758	#define AMLI_RAMPRI_AAR_RAM5_Pri8 (0x8UL) /!< Priority 8. /
jamesadevine	0:e1a608bb55e8	759	#define AMLI_RAMPRI_AAR_RAM5_Pri10 (0xAUL) /!< Priority 10. /
jamesadevine	0:e1a608bb55e8	760	#define AMLI_RAMPRI_AAR_RAM5_Pri12 (0xCUL) /!< Priority 12. /
jamesadevine	0:e1a608bb55e8	761	#define AMLI_RAMPRI_AAR_RAM5_Pri14 (0xEUL) /!< Priority 14. /
jamesadevine	0:e1a608bb55e8	762
jamesadevine	0:e1a608bb55e8	763	/* Bits 19..16 : Configuration field for RAM block 4. */
jamesadevine	0:e1a608bb55e8	764	#define AMLI_RAMPRI_AAR_RAM4_Pos (16UL) /!< Position of RAM4 field. /
jamesadevine	0:e1a608bb55e8	765	#define AMLI_RAMPRI_AAR_RAM4_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM4_Pos) /!< Bit mask of RAM4 field. /
jamesadevine	0:e1a608bb55e8	766	#define AMLI_RAMPRI_AAR_RAM4_Pri0 (0x0UL) /!< Priority 0. /
jamesadevine	0:e1a608bb55e8	767	#define AMLI_RAMPRI_AAR_RAM4_Pri2 (0x2UL) /!< Priority 2. /
jamesadevine	0:e1a608bb55e8	768	#define AMLI_RAMPRI_AAR_RAM4_Pri4 (0x4UL) /!< Priority 4. /
jamesadevine	0:e1a608bb55e8	769	#define AMLI_RAMPRI_AAR_RAM4_Pri6 (0x6UL) /!< Priority 6. /
jamesadevine	0:e1a608bb55e8	770	#define AMLI_RAMPRI_AAR_RAM4_Pri8 (0x8UL) /!< Priority 8. /
jamesadevine	0:e1a608bb55e8	771	#define AMLI_RAMPRI_AAR_RAM4_Pri10 (0xAUL) /!< Priority 10. /
jamesadevine	0:e1a608bb55e8	772	#define AMLI_RAMPRI_AAR_RAM4_Pri12 (0xCUL) /!< Priority 12. /
jamesadevine	0:e1a608bb55e8	773	#define AMLI_RAMPRI_AAR_RAM4_Pri14 (0xEUL) /!< Priority 14. /
jamesadevine	0:e1a608bb55e8	774
jamesadevine	0:e1a608bb55e8	775	/* Bits 15..12 : Configuration field for RAM block 3. */
jamesadevine	0:e1a608bb55e8	776	#define AMLI_RAMPRI_AAR_RAM3_Pos (12UL) /!< Position of RAM3 field. /
jamesadevine	0:e1a608bb55e8	777	#define AMLI_RAMPRI_AAR_RAM3_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM3_Pos) /!< Bit mask of RAM3 field. /
jamesadevine	0:e1a608bb55e8	778	#define AMLI_RAMPRI_AAR_RAM3_Pri0 (0x0UL) /!< Priority 0. /
jamesadevine	0:e1a608bb55e8	779	#define AMLI_RAMPRI_AAR_RAM3_Pri2 (0x2UL) /!< Priority 2. /
jamesadevine	0:e1a608bb55e8	780	#define AMLI_RAMPRI_AAR_RAM3_Pri4 (0x4UL) /!< Priority 4. /
jamesadevine	0:e1a608bb55e8	781	#define AMLI_RAMPRI_AAR_RAM3_Pri6 (0x6UL) /!< Priority 6. /
jamesadevine	0:e1a608bb55e8	782	#define AMLI_RAMPRI_AAR_RAM3_Pri8 (0x8UL) /!< Priority 8. /
jamesadevine	0:e1a608bb55e8	783	#define AMLI_RAMPRI_AAR_RAM3_Pri10 (0xAUL) /!< Priority 10. /
jamesadevine	0:e1a608bb55e8	784	#define AMLI_RAMPRI_AAR_RAM3_Pri12 (0xCUL) /!< Priority 12. /
jamesadevine	0:e1a608bb55e8	785	#define AMLI_RAMPRI_AAR_RAM3_Pri14 (0xEUL) /!< Priority 14. /
jamesadevine	0:e1a608bb55e8	786
jamesadevine	0:e1a608bb55e8	787	/* Bits 11..8 : Configuration field for RAM block 2. */
jamesadevine	0:e1a608bb55e8	788	#define AMLI_RAMPRI_AAR_RAM2_Pos (8UL) /!< Position of RAM2 field. /
jamesadevine	0:e1a608bb55e8	789	#define AMLI_RAMPRI_AAR_RAM2_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM2_Pos) /!< Bit mask of RAM2 field. /
jamesadevine	0:e1a608bb55e8	790	#define AMLI_RAMPRI_AAR_RAM2_Pri0 (0x0UL) /!< Priority 0. /
jamesadevine	0:e1a608bb55e8	791	#define AMLI_RAMPRI_AAR_RAM2_Pri2 (0x2UL) /!< Priority 2. /
jamesadevine	0:e1a608bb55e8	792	#define AMLI_RAMPRI_AAR_RAM2_Pri4 (0x4UL) /!< Priority 4. /
jamesadevine	0:e1a608bb55e8	793	#define AMLI_RAMPRI_AAR_RAM2_Pri6 (0x6UL) /!< Priority 6. /
jamesadevine	0:e1a608bb55e8	794	#define AMLI_RAMPRI_AAR_RAM2_Pri8 (0x8UL) /!< Priority 8. /
jamesadevine	0:e1a608bb55e8	795	#define AMLI_RAMPRI_AAR_RAM2_Pri10 (0xAUL) /!< Priority 10. /
jamesadevine	0:e1a608bb55e8	796	#define AMLI_RAMPRI_AAR_RAM2_Pri12 (0xCUL) /!< Priority 12. /
jamesadevine	0:e1a608bb55e8	797	#define AMLI_RAMPRI_AAR_RAM2_Pri14 (0xEUL) /!< Priority 14. /
jamesadevine	0:e1a608bb55e8	798
jamesadevine	0:e1a608bb55e8	799	/* Bits 7..4 : Configuration field for RAM block 1. */
jamesadevine	0:e1a608bb55e8	800	#define AMLI_RAMPRI_AAR_RAM1_Pos (4UL) /!< Position of RAM1 field. /
jamesadevine	0:e1a608bb55e8	801	#define AMLI_RAMPRI_AAR_RAM1_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM1_Pos) /!< Bit mask of RAM1 field. /
jamesadevine	0:e1a608bb55e8	802	#define AMLI_RAMPRI_AAR_RAM1_Pri0 (0x0UL) /!< Priority 0. /
jamesadevine	0:e1a608bb55e8	803	#define AMLI_RAMPRI_AAR_RAM1_Pri2 (0x2UL) /!< Priority 2. /
jamesadevine	0:e1a608bb55e8	804	#define AMLI_RAMPRI_AAR_RAM1_Pri4 (0x4UL) /!< Priority 4. /
jamesadevine	0:e1a608bb55e8	805	#define AMLI_RAMPRI_AAR_RAM1_Pri6 (0x6UL) /!< Priority 6. /
jamesadevine	0:e1a608bb55e8	806	#define AMLI_RAMPRI_AAR_RAM1_Pri8 (0x8UL) /!< Priority 8. /
jamesadevine	0:e1a608bb55e8	807	#define AMLI_RAMPRI_AAR_RAM1_Pri10 (0xAUL) /!< Priority 10. /
jamesadevine	0:e1a608bb55e8	808	#define AMLI_RAMPRI_AAR_RAM1_Pri12 (0xCUL) /!< Priority 12. /
jamesadevine	0:e1a608bb55e8	809	#define AMLI_RAMPRI_AAR_RAM1_Pri14 (0xEUL) /!< Priority 14. /
jamesadevine	0:e1a608bb55e8	810
jamesadevine	0:e1a608bb55e8	811	/* Bits 3..0 : Configuration field for RAM block 0. */
jamesadevine	0:e1a608bb55e8	812	#define AMLI_RAMPRI_AAR_RAM0_Pos (0UL) /!< Position of RAM0 field. /
jamesadevine	0:e1a608bb55e8	813	#define AMLI_RAMPRI_AAR_RAM0_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM0_Pos) /!< Bit mask of RAM0 field. /
jamesadevine	0:e1a608bb55e8	814	#define AMLI_RAMPRI_AAR_RAM0_Pri0 (0x0UL) /!< Priority 0. /
jamesadevine	0:e1a608bb55e8	815	#define AMLI_RAMPRI_AAR_RAM0_Pri2 (0x2UL) /!< Priority 2. /
jamesadevine	0:e1a608bb55e8	816	#define AMLI_RAMPRI_AAR_RAM0_Pri4 (0x4UL) /!< Priority 4. /
jamesadevine	0:e1a608bb55e8	817	#define AMLI_RAMPRI_AAR_RAM0_Pri6 (0x6UL) /!< Priority 6. /
jamesadevine	0:e1a608bb55e8	818	#define AMLI_RAMPRI_AAR_RAM0_Pri8 (0x8UL) /!< Priority 8. /
jamesadevine	0:e1a608bb55e8	819	#define AMLI_RAMPRI_AAR_RAM0_Pri10 (0xAUL) /!< Priority 10. /
jamesadevine	0:e1a608bb55e8	820	#define AMLI_RAMPRI_AAR_RAM0_Pri12 (0xCUL) /!< Priority 12. /
jamesadevine	0:e1a608bb55e8	821	#define AMLI_RAMPRI_AAR_RAM0_Pri14 (0xEUL) /!< Priority 14. /
jamesadevine	0:e1a608bb55e8	822
jamesadevine	0:e1a608bb55e8	823	/* Peripheral: CCM */
jamesadevine	0:e1a608bb55e8	824	/* Description: AES CCM Mode Encryption. */
jamesadevine	0:e1a608bb55e8	825
jamesadevine	0:e1a608bb55e8	826	/* Register: CCM_SHORTS */
jamesadevine	0:e1a608bb55e8	827	/* Description: Shortcuts for the CCM. */
jamesadevine	0:e1a608bb55e8	828
jamesadevine	0:e1a608bb55e8	829	/* Bit 0 : Shortcut between ENDKSGEN event and CRYPT task. */
jamesadevine	0:e1a608bb55e8	830	#define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /!< Position of ENDKSGEN_CRYPT field. /
jamesadevine	0:e1a608bb55e8	831	#define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /!< Bit mask of ENDKSGEN_CRYPT field. /
jamesadevine	0:e1a608bb55e8	832	#define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /!< Shortcut disabled. /
jamesadevine	0:e1a608bb55e8	833	#define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /!< Shortcut enabled. /
jamesadevine	0:e1a608bb55e8	834
jamesadevine	0:e1a608bb55e8	835	/* Register: CCM_INTENSET */
jamesadevine	0:e1a608bb55e8	836	/* Description: Interrupt enable set register. */
jamesadevine	0:e1a608bb55e8	837
jamesadevine	0:e1a608bb55e8	838	/* Bit 2 : Enable interrupt on ERROR event. */
jamesadevine	0:e1a608bb55e8	839	#define CCM_INTENSET_ERROR_Pos (2UL) /!< Position of ERROR field. /
jamesadevine	0:e1a608bb55e8	840	#define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /!< Bit mask of ERROR field. /
jamesadevine	0:e1a608bb55e8	841	#define CCM_INTENSET_ERROR_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	842	#define CCM_INTENSET_ERROR_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	843	#define CCM_INTENSET_ERROR_Set (1UL) /!< Enable interrupt on write. /
jamesadevine	0:e1a608bb55e8	844
jamesadevine	0:e1a608bb55e8	845	/* Bit 1 : Enable interrupt on ENDCRYPT event. */
jamesadevine	0:e1a608bb55e8	846	#define CCM_INTENSET_ENDCRYPT_Pos (1UL) /!< Position of ENDCRYPT field. /
jamesadevine	0:e1a608bb55e8	847	#define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /!< Bit mask of ENDCRYPT field. /
jamesadevine	0:e1a608bb55e8	848	#define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	849	#define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	850	#define CCM_INTENSET_ENDCRYPT_Set (1UL) /!< Enable interrupt on write. /
jamesadevine	0:e1a608bb55e8	851
jamesadevine	0:e1a608bb55e8	852	/* Bit 0 : Enable interrupt on ENDKSGEN event. */
jamesadevine	0:e1a608bb55e8	853	#define CCM_INTENSET_ENDKSGEN_Pos (0UL) /!< Position of ENDKSGEN field. /
jamesadevine	0:e1a608bb55e8	854	#define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /!< Bit mask of ENDKSGEN field. /
jamesadevine	0:e1a608bb55e8	855	#define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	856	#define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	857	#define CCM_INTENSET_ENDKSGEN_Set (1UL) /!< Enable interrupt on write. /
jamesadevine	0:e1a608bb55e8	858
jamesadevine	0:e1a608bb55e8	859	/* Register: CCM_INTENCLR */
jamesadevine	0:e1a608bb55e8	860	/* Description: Interrupt enable clear register. */
jamesadevine	0:e1a608bb55e8	861
jamesadevine	0:e1a608bb55e8	862	/* Bit 2 : Disable interrupt on ERROR event. */
jamesadevine	0:e1a608bb55e8	863	#define CCM_INTENCLR_ERROR_Pos (2UL) /!< Position of ERROR field. /
jamesadevine	0:e1a608bb55e8	864	#define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /!< Bit mask of ERROR field. /
jamesadevine	0:e1a608bb55e8	865	#define CCM_INTENCLR_ERROR_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	866	#define CCM_INTENCLR_ERROR_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	867	#define CCM_INTENCLR_ERROR_Clear (1UL) /!< Disable interrupt on write. /
jamesadevine	0:e1a608bb55e8	868
jamesadevine	0:e1a608bb55e8	869	/* Bit 1 : Disable interrupt on ENDCRYPT event. */
jamesadevine	0:e1a608bb55e8	870	#define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /!< Position of ENDCRYPT field. /
jamesadevine	0:e1a608bb55e8	871	#define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /!< Bit mask of ENDCRYPT field. /
jamesadevine	0:e1a608bb55e8	872	#define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	873	#define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	874	#define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /!< Disable interrupt on write. /
jamesadevine	0:e1a608bb55e8	875
jamesadevine	0:e1a608bb55e8	876	/* Bit 0 : Disable interrupt on ENDKSGEN event. */
jamesadevine	0:e1a608bb55e8	877	#define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /!< Position of ENDKSGEN field. /
jamesadevine	0:e1a608bb55e8	878	#define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /!< Bit mask of ENDKSGEN field. /
jamesadevine	0:e1a608bb55e8	879	#define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	880	#define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	881	#define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /!< Disable interrupt on write. /
jamesadevine	0:e1a608bb55e8	882
jamesadevine	0:e1a608bb55e8	883	/* Register: CCM_MICSTATUS */
jamesadevine	0:e1a608bb55e8	884	/* Description: CCM RX MIC check result. */
jamesadevine	0:e1a608bb55e8	885
jamesadevine	0:e1a608bb55e8	886	/* Bit 0 : Result of the MIC check performed during the previous CCM RX STARTCRYPT */
jamesadevine	0:e1a608bb55e8	887	#define CCM_MICSTATUS_MICSTATUS_Pos (0UL) /!< Position of MICSTATUS field. /
jamesadevine	0:e1a608bb55e8	888	#define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos) /!< Bit mask of MICSTATUS field. /
jamesadevine	0:e1a608bb55e8	889	#define CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL) /!< MIC check failed. /
jamesadevine	0:e1a608bb55e8	890	#define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL) /!< MIC check passed. /
jamesadevine	0:e1a608bb55e8	891
jamesadevine	0:e1a608bb55e8	892	/* Register: CCM_ENABLE */
jamesadevine	0:e1a608bb55e8	893	/* Description: CCM enable. */
jamesadevine	0:e1a608bb55e8	894
jamesadevine	0:e1a608bb55e8	895	/* Bits 1..0 : CCM enable. */
jamesadevine	0:e1a608bb55e8	896	#define CCM_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
jamesadevine	0:e1a608bb55e8	897	#define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
jamesadevine	0:e1a608bb55e8	898	#define CCM_ENABLE_ENABLE_Disabled (0x00UL) /!< CCM is disabled. /
jamesadevine	0:e1a608bb55e8	899	#define CCM_ENABLE_ENABLE_Enabled (0x02UL) /!< CCM is enabled. /
jamesadevine	0:e1a608bb55e8	900
jamesadevine	0:e1a608bb55e8	901	/* Register: CCM_MODE */
jamesadevine	0:e1a608bb55e8	902	/* Description: Operation mode. */
jamesadevine	0:e1a608bb55e8	903
jamesadevine	0:e1a608bb55e8	904	/* Bit 0 : CCM mode operation. */
jamesadevine	0:e1a608bb55e8	905	#define CCM_MODE_MODE_Pos (0UL) /!< Position of MODE field. /
jamesadevine	0:e1a608bb55e8	906	#define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /!< Bit mask of MODE field. /
jamesadevine	0:e1a608bb55e8	907	#define CCM_MODE_MODE_Encryption (0UL) /!< CCM mode TX /
jamesadevine	0:e1a608bb55e8	908	#define CCM_MODE_MODE_Decryption (1UL) /!< CCM mode TX /
jamesadevine	0:e1a608bb55e8	909
jamesadevine	0:e1a608bb55e8	910	/* Register: CCM_POWER */
jamesadevine	0:e1a608bb55e8	911	/* Description: Peripheral power control. */
jamesadevine	0:e1a608bb55e8	912
jamesadevine	0:e1a608bb55e8	913	/* Bit 0 : Peripheral power control. */
jamesadevine	0:e1a608bb55e8	914	#define CCM_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
jamesadevine	0:e1a608bb55e8	915	#define CCM_POWER_POWER_Msk (0x1UL << CCM_POWER_POWER_Pos) /!< Bit mask of POWER field. /
jamesadevine	0:e1a608bb55e8	916	#define CCM_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
jamesadevine	0:e1a608bb55e8	917	#define CCM_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
jamesadevine	0:e1a608bb55e8	918
jamesadevine	0:e1a608bb55e8	919
jamesadevine	0:e1a608bb55e8	920	/* Peripheral: CLOCK */
jamesadevine	0:e1a608bb55e8	921	/* Description: Clock control. */
jamesadevine	0:e1a608bb55e8	922
jamesadevine	0:e1a608bb55e8	923	/* Register: CLOCK_INTENSET */
jamesadevine	0:e1a608bb55e8	924	/* Description: Interrupt enable set register. */
jamesadevine	0:e1a608bb55e8	925
jamesadevine	0:e1a608bb55e8	926	/* Bit 4 : Enable interrupt on CTTO event. */
jamesadevine	0:e1a608bb55e8	927	#define CLOCK_INTENSET_CTTO_Pos (4UL) /!< Position of CTTO field. /
jamesadevine	0:e1a608bb55e8	928	#define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /!< Bit mask of CTTO field. /
jamesadevine	0:e1a608bb55e8	929	#define CLOCK_INTENSET_CTTO_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	930	#define CLOCK_INTENSET_CTTO_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	931	#define CLOCK_INTENSET_CTTO_Set (1UL) /!< Enable interrupt on write. /
jamesadevine	0:e1a608bb55e8	932
jamesadevine	0:e1a608bb55e8	933	/* Bit 3 : Enable interrupt on DONE event. */
jamesadevine	0:e1a608bb55e8	934	#define CLOCK_INTENSET_DONE_Pos (3UL) /!< Position of DONE field. /
jamesadevine	0:e1a608bb55e8	935	#define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /!< Bit mask of DONE field. /
jamesadevine	0:e1a608bb55e8	936	#define CLOCK_INTENSET_DONE_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	937	#define CLOCK_INTENSET_DONE_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	938	#define CLOCK_INTENSET_DONE_Set (1UL) /!< Enable interrupt on write. /
jamesadevine	0:e1a608bb55e8	939
jamesadevine	0:e1a608bb55e8	940	/* Bit 1 : Enable interrupt on LFCLKSTARTED event. */
jamesadevine	0:e1a608bb55e8	941	#define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /!< Position of LFCLKSTARTED field. /
jamesadevine	0:e1a608bb55e8	942	#define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /!< Bit mask of LFCLKSTARTED field. /
jamesadevine	0:e1a608bb55e8	943	#define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	944	#define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	945	#define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /!< Enable interrupt on write. /
jamesadevine	0:e1a608bb55e8	946
jamesadevine	0:e1a608bb55e8	947	/* Bit 0 : Enable interrupt on HFCLKSTARTED event. */
jamesadevine	0:e1a608bb55e8	948	#define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /!< Position of HFCLKSTARTED field. /
jamesadevine	0:e1a608bb55e8	949	#define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /!< Bit mask of HFCLKSTARTED field. /
jamesadevine	0:e1a608bb55e8	950	#define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	951	#define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	952	#define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /!< Enable interrupt on write. /
jamesadevine	0:e1a608bb55e8	953
jamesadevine	0:e1a608bb55e8	954	/* Register: CLOCK_INTENCLR */
jamesadevine	0:e1a608bb55e8	955	/* Description: Interrupt enable clear register. */
jamesadevine	0:e1a608bb55e8	956
jamesadevine	0:e1a608bb55e8	957	/* Bit 4 : Disable interrupt on CTTO event. */
jamesadevine	0:e1a608bb55e8	958	#define CLOCK_INTENCLR_CTTO_Pos (4UL) /!< Position of CTTO field. /
jamesadevine	0:e1a608bb55e8	959	#define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /!< Bit mask of CTTO field. /
jamesadevine	0:e1a608bb55e8	960	#define CLOCK_INTENCLR_CTTO_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	961	#define CLOCK_INTENCLR_CTTO_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	962	#define CLOCK_INTENCLR_CTTO_Clear (1UL) /!< Disable interrupt on write. /
jamesadevine	0:e1a608bb55e8	963
jamesadevine	0:e1a608bb55e8	964	/* Bit 3 : Disable interrupt on DONE event. */
jamesadevine	0:e1a608bb55e8	965	#define CLOCK_INTENCLR_DONE_Pos (3UL) /!< Position of DONE field. /
jamesadevine	0:e1a608bb55e8	966	#define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /!< Bit mask of DONE field. /
jamesadevine	0:e1a608bb55e8	967	#define CLOCK_INTENCLR_DONE_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	968	#define CLOCK_INTENCLR_DONE_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	969	#define CLOCK_INTENCLR_DONE_Clear (1UL) /!< Disable interrupt on write. /
jamesadevine	0:e1a608bb55e8	970
jamesadevine	0:e1a608bb55e8	971	/* Bit 1 : Disable interrupt on LFCLKSTARTED event. */
jamesadevine	0:e1a608bb55e8	972	#define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /!< Position of LFCLKSTARTED field. /
jamesadevine	0:e1a608bb55e8	973	#define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /!< Bit mask of LFCLKSTARTED field. /
jamesadevine	0:e1a608bb55e8	974	#define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	975	#define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	976	#define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /!< Disable interrupt on write. /
jamesadevine	0:e1a608bb55e8	977
jamesadevine	0:e1a608bb55e8	978	/* Bit 0 : Disable interrupt on HFCLKSTARTED event. */
jamesadevine	0:e1a608bb55e8	979	#define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /!< Position of HFCLKSTARTED field. /
jamesadevine	0:e1a608bb55e8	980	#define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /!< Bit mask of HFCLKSTARTED field. /
jamesadevine	0:e1a608bb55e8	981	#define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	982	#define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	983	#define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /!< Disable interrupt on write. /
jamesadevine	0:e1a608bb55e8	984
jamesadevine	0:e1a608bb55e8	985	/* Register: CLOCK_HFCLKRUN */
jamesadevine	0:e1a608bb55e8	986	/* Description: Task HFCLKSTART trigger status. */
jamesadevine	0:e1a608bb55e8	987
jamesadevine	0:e1a608bb55e8	988	/* Bit 0 : Task HFCLKSTART trigger status. */
jamesadevine	0:e1a608bb55e8	989	#define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /!< Position of STATUS field. /
jamesadevine	0:e1a608bb55e8	990	#define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /!< Bit mask of STATUS field. /
jamesadevine	0:e1a608bb55e8	991	#define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /!< Task HFCLKSTART has not been triggered. /
jamesadevine	0:e1a608bb55e8	992	#define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /!< Task HFCLKSTART has been triggered. /
jamesadevine	0:e1a608bb55e8	993
jamesadevine	0:e1a608bb55e8	994	/* Register: CLOCK_HFCLKSTAT */
jamesadevine	0:e1a608bb55e8	995	/* Description: High frequency clock status. */
jamesadevine	0:e1a608bb55e8	996
jamesadevine	0:e1a608bb55e8	997	/* Bit 16 : State for the HFCLK. */
jamesadevine	0:e1a608bb55e8	998	#define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /!< Position of STATE field. /
jamesadevine	0:e1a608bb55e8	999	#define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /!< Bit mask of STATE field. /
jamesadevine	0:e1a608bb55e8	1000	#define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /!< HFCLK clock not running. /
jamesadevine	0:e1a608bb55e8	1001	#define CLOCK_HFCLKSTAT_STATE_Running (1UL) /!< HFCLK clock running. /
jamesadevine	0:e1a608bb55e8	1002
jamesadevine	0:e1a608bb55e8	1003	/* Bit 0 : Active clock source for the HF clock. */
jamesadevine	0:e1a608bb55e8	1004	#define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /!< Position of SRC field. /
jamesadevine	0:e1a608bb55e8	1005	#define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /!< Bit mask of SRC field. /
jamesadevine	0:e1a608bb55e8	1006	#define CLOCK_HFCLKSTAT_SRC_RC (0UL) /!< Internal 16MHz RC oscillator running and generating the HFCLK clock. /
jamesadevine	0:e1a608bb55e8	1007	#define CLOCK_HFCLKSTAT_SRC_Xtal (1UL) /!< External 16MHz/32MHz crystal oscillator running and generating the HFCLK clock. /
jamesadevine	0:e1a608bb55e8	1008
jamesadevine	0:e1a608bb55e8	1009	/* Register: CLOCK_LFCLKRUN */
jamesadevine	0:e1a608bb55e8	1010	/* Description: Task LFCLKSTART triggered status. */
jamesadevine	0:e1a608bb55e8	1011
jamesadevine	0:e1a608bb55e8	1012	/* Bit 0 : Task LFCLKSTART triggered status. */
jamesadevine	0:e1a608bb55e8	1013	#define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /!< Position of STATUS field. /
jamesadevine	0:e1a608bb55e8	1014	#define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /!< Bit mask of STATUS field. /
jamesadevine	0:e1a608bb55e8	1015	#define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /!< Task LFCLKSTART has not been triggered. /
jamesadevine	0:e1a608bb55e8	1016	#define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /!< Task LFCLKSTART has been triggered. /
jamesadevine	0:e1a608bb55e8	1017
jamesadevine	0:e1a608bb55e8	1018	/* Register: CLOCK_LFCLKSTAT */
jamesadevine	0:e1a608bb55e8	1019	/* Description: Low frequency clock status. */
jamesadevine	0:e1a608bb55e8	1020
jamesadevine	0:e1a608bb55e8	1021	/* Bit 16 : State for the LF clock. */
jamesadevine	0:e1a608bb55e8	1022	#define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /!< Position of STATE field. /
jamesadevine	0:e1a608bb55e8	1023	#define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /!< Bit mask of STATE field. /
jamesadevine	0:e1a608bb55e8	1024	#define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /!< LFCLK clock not running. /
jamesadevine	0:e1a608bb55e8	1025	#define CLOCK_LFCLKSTAT_STATE_Running (1UL) /!< LFCLK clock running. /
jamesadevine	0:e1a608bb55e8	1026
jamesadevine	0:e1a608bb55e8	1027	/* Bits 1..0 : Active clock source for the LF clock. */
jamesadevine	0:e1a608bb55e8	1028	#define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /!< Position of SRC field. /
jamesadevine	0:e1a608bb55e8	1029	#define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /!< Bit mask of SRC field. /
jamesadevine	0:e1a608bb55e8	1030	#define CLOCK_LFCLKSTAT_SRC_RC (0UL) /!< Internal 32KiHz RC oscillator running and generating the LFCLK clock. /
jamesadevine	0:e1a608bb55e8	1031	#define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /!< External 32KiHz crystal oscillator running and generating the LFCLK clock. /
jamesadevine	0:e1a608bb55e8	1032	#define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /!< Internal 32KiHz synthesizer from the HFCLK running and generating the LFCLK clock. /
jamesadevine	0:e1a608bb55e8	1033
jamesadevine	0:e1a608bb55e8	1034	/* Register: CLOCK_LFCLKSRCCOPY */
jamesadevine	0:e1a608bb55e8	1035	/* Description: Clock source for the LFCLK clock, set when task LKCLKSTART is triggered. */
jamesadevine	0:e1a608bb55e8	1036
jamesadevine	0:e1a608bb55e8	1037	/* Bits 1..0 : Clock source for the LFCLK clock, set when task LKCLKSTART is triggered. */
jamesadevine	0:e1a608bb55e8	1038	#define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /!< Position of SRC field. /
jamesadevine	0:e1a608bb55e8	1039	#define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /!< Bit mask of SRC field. /
jamesadevine	0:e1a608bb55e8	1040	#define CLOCK_LFCLKSRCCOPY_SRC_RC (0UL) /!< Internal 32KiHz RC oscillator. /
jamesadevine	0:e1a608bb55e8	1041	#define CLOCK_LFCLKSRCCOPY_SRC_Xtal (1UL) /!< External 32KiHz crystal. /
jamesadevine	0:e1a608bb55e8	1042	#define CLOCK_LFCLKSRCCOPY_SRC_Synth (2UL) /!< Internal 32KiHz synthesizer from HFCLK system clock. /
jamesadevine	0:e1a608bb55e8	1043
jamesadevine	0:e1a608bb55e8	1044	/* Register: CLOCK_LFCLKSRC */
jamesadevine	0:e1a608bb55e8	1045	/* Description: Clock source for the LFCLK clock. */
jamesadevine	0:e1a608bb55e8	1046
jamesadevine	0:e1a608bb55e8	1047	/* Bits 1..0 : Clock source. */
jamesadevine	0:e1a608bb55e8	1048	#define CLOCK_LFCLKSRC_SRC_Pos (0UL) /!< Position of SRC field. /
jamesadevine	0:e1a608bb55e8	1049	#define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /!< Bit mask of SRC field. /
jamesadevine	0:e1a608bb55e8	1050	#define CLOCK_LFCLKSRC_SRC_RC (0UL) /!< Internal 32KiHz RC oscillator. /
jamesadevine	0:e1a608bb55e8	1051	#define CLOCK_LFCLKSRC_SRC_Xtal (1UL) /!< External 32KiHz crystal. /
jamesadevine	0:e1a608bb55e8	1052	#define CLOCK_LFCLKSRC_SRC_Synth (2UL) /!< Internal 32KiHz synthesizer from HFCLK system clock. /
jamesadevine	0:e1a608bb55e8	1053
jamesadevine	0:e1a608bb55e8	1054	/* Register: CLOCK_CTIV */
jamesadevine	0:e1a608bb55e8	1055	/* Description: Calibration timer interval. */
jamesadevine	0:e1a608bb55e8	1056
jamesadevine	0:e1a608bb55e8	1057	/* Bits 6..0 : Calibration timer interval in 0.25s resolution. */
jamesadevine	0:e1a608bb55e8	1058	#define CLOCK_CTIV_CTIV_Pos (0UL) /!< Position of CTIV field. /
jamesadevine	0:e1a608bb55e8	1059	#define CLOCK_CTIV_CTIV_Msk (0x7FUL << CLOCK_CTIV_CTIV_Pos) /!< Bit mask of CTIV field. /
jamesadevine	0:e1a608bb55e8	1060
jamesadevine	0:e1a608bb55e8	1061	/* Register: CLOCK_XTALFREQ */
jamesadevine	0:e1a608bb55e8	1062	/* Description: Crystal frequency. */
jamesadevine	0:e1a608bb55e8	1063
jamesadevine	0:e1a608bb55e8	1064	/* Bits 7..0 : External Xtal frequency selection. */
jamesadevine	0:e1a608bb55e8	1065	#define CLOCK_XTALFREQ_XTALFREQ_Pos (0UL) /!< Position of XTALFREQ field. /
jamesadevine	0:e1a608bb55e8	1066	#define CLOCK_XTALFREQ_XTALFREQ_Msk (0xFFUL << CLOCK_XTALFREQ_XTALFREQ_Pos) /!< Bit mask of XTALFREQ field. /
jamesadevine	0:e1a608bb55e8	1067	#define CLOCK_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /!< 16MHz xtal is used as source for the HFCLK oscillator. /
jamesadevine	0:e1a608bb55e8	1068	#define CLOCK_XTALFREQ_XTALFREQ_32MHz (0x00UL) /!< 32MHz xtal is used as source for the HFCLK oscillator. /
jamesadevine	0:e1a608bb55e8	1069
jamesadevine	0:e1a608bb55e8	1070
jamesadevine	0:e1a608bb55e8	1071	/* Peripheral: ECB */
jamesadevine	0:e1a608bb55e8	1072	/* Description: AES ECB Mode Encryption. */
jamesadevine	0:e1a608bb55e8	1073
jamesadevine	0:e1a608bb55e8	1074	/* Register: ECB_INTENSET */
jamesadevine	0:e1a608bb55e8	1075	/* Description: Interrupt enable set register. */
jamesadevine	0:e1a608bb55e8	1076
jamesadevine	0:e1a608bb55e8	1077	/* Bit 1 : Enable interrupt on ERRORECB event. */
jamesadevine	0:e1a608bb55e8	1078	#define ECB_INTENSET_ERRORECB_Pos (1UL) /!< Position of ERRORECB field. /
jamesadevine	0:e1a608bb55e8	1079	#define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /!< Bit mask of ERRORECB field. /
jamesadevine	0:e1a608bb55e8	1080	#define ECB_INTENSET_ERRORECB_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	1081	#define ECB_INTENSET_ERRORECB_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	1082	#define ECB_INTENSET_ERRORECB_Set (1UL) /!< Enable interrupt on write. /
jamesadevine	0:e1a608bb55e8	1083
jamesadevine	0:e1a608bb55e8	1084	/* Bit 0 : Enable interrupt on ENDECB event. */
jamesadevine	0:e1a608bb55e8	1085	#define ECB_INTENSET_ENDECB_Pos (0UL) /!< Position of ENDECB field. /
jamesadevine	0:e1a608bb55e8	1086	#define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /!< Bit mask of ENDECB field. /
jamesadevine	0:e1a608bb55e8	1087	#define ECB_INTENSET_ENDECB_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	1088	#define ECB_INTENSET_ENDECB_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	1089	#define ECB_INTENSET_ENDECB_Set (1UL) /!< Enable interrupt on write. /
jamesadevine	0:e1a608bb55e8	1090
jamesadevine	0:e1a608bb55e8	1091	/* Register: ECB_INTENCLR */
jamesadevine	0:e1a608bb55e8	1092	/* Description: Interrupt enable clear register. */
jamesadevine	0:e1a608bb55e8	1093
jamesadevine	0:e1a608bb55e8	1094	/* Bit 1 : Disable interrupt on ERRORECB event. */
jamesadevine	0:e1a608bb55e8	1095	#define ECB_INTENCLR_ERRORECB_Pos (1UL) /!< Position of ERRORECB field. /
jamesadevine	0:e1a608bb55e8	1096	#define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /!< Bit mask of ERRORECB field. /
jamesadevine	0:e1a608bb55e8	1097	#define ECB_INTENCLR_ERRORECB_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	1098	#define ECB_INTENCLR_ERRORECB_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	1099	#define ECB_INTENCLR_ERRORECB_Clear (1UL) /!< Disable interrupt on write. /
jamesadevine	0:e1a608bb55e8	1100
jamesadevine	0:e1a608bb55e8	1101	/* Bit 0 : Disable interrupt on ENDECB event. */
jamesadevine	0:e1a608bb55e8	1102	#define ECB_INTENCLR_ENDECB_Pos (0UL) /!< Position of ENDECB field. /
jamesadevine	0:e1a608bb55e8	1103	#define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /!< Bit mask of ENDECB field. /
jamesadevine	0:e1a608bb55e8	1104	#define ECB_INTENCLR_ENDECB_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	1105	#define ECB_INTENCLR_ENDECB_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	1106	#define ECB_INTENCLR_ENDECB_Clear (1UL) /!< Disable interrupt on write. /
jamesadevine	0:e1a608bb55e8	1107
jamesadevine	0:e1a608bb55e8	1108	/* Register: ECB_POWER */
jamesadevine	0:e1a608bb55e8	1109	/* Description: Peripheral power control. */
jamesadevine	0:e1a608bb55e8	1110
jamesadevine	0:e1a608bb55e8	1111	/* Bit 0 : Peripheral power control. */
jamesadevine	0:e1a608bb55e8	1112	#define ECB_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
jamesadevine	0:e1a608bb55e8	1113	#define ECB_POWER_POWER_Msk (0x1UL << ECB_POWER_POWER_Pos) /!< Bit mask of POWER field. /
jamesadevine	0:e1a608bb55e8	1114	#define ECB_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
jamesadevine	0:e1a608bb55e8	1115	#define ECB_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
jamesadevine	0:e1a608bb55e8	1116
jamesadevine	0:e1a608bb55e8	1117
jamesadevine	0:e1a608bb55e8	1118	/* Peripheral: FICR */
jamesadevine	0:e1a608bb55e8	1119	/* Description: Factory Information Configuration. */
jamesadevine	0:e1a608bb55e8	1120
jamesadevine	0:e1a608bb55e8	1121	/* Register: FICR_PPFC */
jamesadevine	0:e1a608bb55e8	1122	/* Description: Pre-programmed factory code present. */
jamesadevine	0:e1a608bb55e8	1123
jamesadevine	0:e1a608bb55e8	1124	/* Bits 7..0 : Pre-programmed factory code present. */
jamesadevine	0:e1a608bb55e8	1125	#define FICR_PPFC_PPFC_Pos (0UL) /!< Position of PPFC field. /
jamesadevine	0:e1a608bb55e8	1126	#define FICR_PPFC_PPFC_Msk (0xFFUL << FICR_PPFC_PPFC_Pos) /!< Bit mask of PPFC field. /
jamesadevine	0:e1a608bb55e8	1127	#define FICR_PPFC_PPFC_NotPresent (0xFFUL) /!< Not present. /
jamesadevine	0:e1a608bb55e8	1128	#define FICR_PPFC_PPFC_Present (0x00UL) /!< Present. /
jamesadevine	0:e1a608bb55e8	1129
jamesadevine	0:e1a608bb55e8	1130	/* Register: FICR_CONFIGID */
jamesadevine	0:e1a608bb55e8	1131	/* Description: Configuration identifier. */
jamesadevine	0:e1a608bb55e8	1132
jamesadevine	0:e1a608bb55e8	1133	/* Bits 31..16 : Firmware Identification Number pre-loaded into the flash. */
jamesadevine	0:e1a608bb55e8	1134	#define FICR_CONFIGID_FWID_Pos (16UL) /!< Position of FWID field. /
jamesadevine	0:e1a608bb55e8	1135	#define FICR_CONFIGID_FWID_Msk (0xFFFFUL << FICR_CONFIGID_FWID_Pos) /!< Bit mask of FWID field. /
jamesadevine	0:e1a608bb55e8	1136
jamesadevine	0:e1a608bb55e8	1137	/* Bits 15..0 : Hardware Identification Number. */
jamesadevine	0:e1a608bb55e8	1138	#define FICR_CONFIGID_HWID_Pos (0UL) /!< Position of HWID field. /
jamesadevine	0:e1a608bb55e8	1139	#define FICR_CONFIGID_HWID_Msk (0xFFFFUL << FICR_CONFIGID_HWID_Pos) /!< Bit mask of HWID field. /
jamesadevine	0:e1a608bb55e8	1140
jamesadevine	0:e1a608bb55e8	1141	/* Register: FICR_DEVICEADDRTYPE */
jamesadevine	0:e1a608bb55e8	1142	/* Description: Device address type. */
jamesadevine	0:e1a608bb55e8	1143
jamesadevine	0:e1a608bb55e8	1144	/* Bit 0 : Device address type. */
jamesadevine	0:e1a608bb55e8	1145	#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos (0UL) /!< Position of DEVICEADDRTYPE field. /
jamesadevine	0:e1a608bb55e8	1146	#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos) /!< Bit mask of DEVICEADDRTYPE field. /
jamesadevine	0:e1a608bb55e8	1147	#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public (0UL) /!< Public address. /
jamesadevine	0:e1a608bb55e8	1148	#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /!< Random address. /
jamesadevine	0:e1a608bb55e8	1149
jamesadevine	0:e1a608bb55e8	1150	/* Register: FICR_OVERRIDEEN */
jamesadevine	0:e1a608bb55e8	1151	/* Description: Radio calibration override enable. */
jamesadevine	0:e1a608bb55e8	1152
jamesadevine	0:e1a608bb55e8	1153	/* Bit 3 : Override default values for BLE_1Mbit mode. */
jamesadevine	0:e1a608bb55e8	1154	#define FICR_OVERRIDEEN_BLE_1MBIT_Pos (3UL) /!< Position of BLE_1MBIT field. /
jamesadevine	0:e1a608bb55e8	1155	#define FICR_OVERRIDEEN_BLE_1MBIT_Msk (0x1UL << FICR_OVERRIDEEN_BLE_1MBIT_Pos) /!< Bit mask of BLE_1MBIT field. /
jamesadevine	0:e1a608bb55e8	1156	#define FICR_OVERRIDEEN_BLE_1MBIT_Override (0UL) /!< Override the default values for BLE_1Mbit mode. /
jamesadevine	0:e1a608bb55e8	1157	#define FICR_OVERRIDEEN_BLE_1MBIT_NotOverride (1UL) /!< Do not override the default values for BLE_1Mbit mode. /
jamesadevine	0:e1a608bb55e8	1158
jamesadevine	0:e1a608bb55e8	1159	/* Bit 0 : Override default values for NRF_1Mbit mode. */
jamesadevine	0:e1a608bb55e8	1160	#define FICR_OVERRIDEEN_NRF_1MBIT_Pos (0UL) /!< Position of NRF_1MBIT field. /
jamesadevine	0:e1a608bb55e8	1161	#define FICR_OVERRIDEEN_NRF_1MBIT_Msk (0x1UL << FICR_OVERRIDEEN_NRF_1MBIT_Pos) /!< Bit mask of NRF_1MBIT field. /
jamesadevine	0:e1a608bb55e8	1162	#define FICR_OVERRIDEEN_NRF_1MBIT_Override (0UL) /!< Override the default values for NRF_1Mbit mode. /
jamesadevine	0:e1a608bb55e8	1163	#define FICR_OVERRIDEEN_NRF_1MBIT_NotOverride (1UL) /!< Do not override the default values for NRF_1Mbit mode. /
jamesadevine	0:e1a608bb55e8	1164
jamesadevine	0:e1a608bb55e8	1165	/* Register: FICR_INFO_PART */
jamesadevine	0:e1a608bb55e8	1166	/* Description: Part code */
jamesadevine	0:e1a608bb55e8	1167
jamesadevine	0:e1a608bb55e8	1168	/* Bits 31..0 : Part code */
jamesadevine	0:e1a608bb55e8	1169	#define FICR_INFO_PART_PART_Pos (0UL) /!< Position of PART field. /
jamesadevine	0:e1a608bb55e8	1170	#define FICR_INFO_PART_PART_Msk (0xFFFFFFFFUL << FICR_INFO_PART_PART_Pos) /!< Bit mask of PART field. /
jamesadevine	0:e1a608bb55e8	1171	#define FICR_INFO_PART_PART_N51822 (0x51822UL) /!< nRF51822 /
jamesadevine	0:e1a608bb55e8	1172	#define FICR_INFO_PART_PART_N51422 (0x51422UL) /!< nRF51422 /
jamesadevine	0:e1a608bb55e8	1173	#define FICR_INFO_PART_PART_Unspecified (0xFFFFFFFFUL) /!< Unspecified /
jamesadevine	0:e1a608bb55e8	1174
jamesadevine	0:e1a608bb55e8	1175	/* Register: FICR_INFO_VARIANT */
jamesadevine	0:e1a608bb55e8	1176	/* Description: Part variant */
jamesadevine	0:e1a608bb55e8	1177
jamesadevine	0:e1a608bb55e8	1178	/* Bits 31..0 : Part variant */
jamesadevine	0:e1a608bb55e8	1179	#define FICR_INFO_VARIANT_VARIANT_Pos (0UL) /!< Position of VARIANT field. /
jamesadevine	0:e1a608bb55e8	1180	#define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos) /!< Bit mask of VARIANT field. /
jamesadevine	0:e1a608bb55e8	1181	#define FICR_INFO_VARIANT_VARIANT_nRF51C (0x1002UL) /!< nRF51-C (XLR3) /
jamesadevine	0:e1a608bb55e8	1182	#define FICR_INFO_VARIANT_VARIANT_nRF51D (0x1003UL) /!< nRF51-D (L3) /
jamesadevine	0:e1a608bb55e8	1183	#define FICR_INFO_VARIANT_VARIANT_nRF51E (0x1004UL) /!< nRF51-E (XLR3P) /
jamesadevine	0:e1a608bb55e8	1184	#define FICR_INFO_VARIANT_VARIANT_Unspecified (0xFFFFFFFFUL) /!< Unspecified /
jamesadevine	0:e1a608bb55e8	1185
jamesadevine	0:e1a608bb55e8	1186	/* Register: FICR_INFO_PACKAGE */
jamesadevine	0:e1a608bb55e8	1187	/* Description: Package option */
jamesadevine	0:e1a608bb55e8	1188
jamesadevine	0:e1a608bb55e8	1189	/* Bits 31..0 : Package option */
jamesadevine	0:e1a608bb55e8	1190	#define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL) /!< Position of PACKAGE field. /
jamesadevine	0:e1a608bb55e8	1191	#define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /!< Bit mask of PACKAGE field. /
jamesadevine	0:e1a608bb55e8	1192	#define FICR_INFO_PACKAGE_PACKAGE_QFN48 (0x0000UL) /!< 48-pin QFN with 31 GPIO /
jamesadevine	0:e1a608bb55e8	1193	#define FICR_INFO_PACKAGE_PACKAGE_nRF51CSP56A (0x1000UL) /!< nRF51x22 CDxx - WLCSP 56 balls /
jamesadevine	0:e1a608bb55e8	1194	#define FICR_INFO_PACKAGE_PACKAGE_nRF51CSP62A (0x1001UL) /!< nRF51x22 CExx - WLCSP 62 balls /
jamesadevine	0:e1a608bb55e8	1195	#define FICR_INFO_PACKAGE_PACKAGE_nRF51CSP62B (0x1002UL) /!< nRF51x22 CFxx - WLCSP 62 balls /
jamesadevine	0:e1a608bb55e8	1196	#define FICR_INFO_PACKAGE_PACKAGE_nRF51CSP62C (0x1003UL) /!< nRF51x22 CTxx - WLCSP 62 balls /
jamesadevine	0:e1a608bb55e8	1197	#define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL) /!< Unspecified /
jamesadevine	0:e1a608bb55e8	1198
jamesadevine	0:e1a608bb55e8	1199	/* Register: FICR_INFO_RAM */
jamesadevine	0:e1a608bb55e8	1200	/* Description: RAM variant */
jamesadevine	0:e1a608bb55e8	1201
jamesadevine	0:e1a608bb55e8	1202	/* Bits 31..0 : RAM variant */
jamesadevine	0:e1a608bb55e8	1203	#define FICR_INFO_RAM_RAM_Pos (0UL) /!< Position of RAM field. /
jamesadevine	0:e1a608bb55e8	1204	#define FICR_INFO_RAM_RAM_Msk (0xFFFFFFFFUL << FICR_INFO_RAM_RAM_Pos) /!< Bit mask of RAM field. /
jamesadevine	0:e1a608bb55e8	1205	#define FICR_INFO_RAM_RAM_Unspecified (0xFFFFFFFFUL) /!< Unspecified /
jamesadevine	0:e1a608bb55e8	1206	#define FICR_INFO_RAM_RAM_K16 (16UL) /!< 16 kByte RAM. /
jamesadevine	0:e1a608bb55e8	1207	#define FICR_INFO_RAM_RAM_K32 (32UL) /!< 32 kByte RAM. /
jamesadevine	0:e1a608bb55e8	1208
jamesadevine	0:e1a608bb55e8	1209	/* Register: FICR_INFO_FLASH */
jamesadevine	0:e1a608bb55e8	1210	/* Description: Flash variant */
jamesadevine	0:e1a608bb55e8	1211
jamesadevine	0:e1a608bb55e8	1212	/* Bits 31..0 : Flash variant */
jamesadevine	0:e1a608bb55e8	1213	#define FICR_INFO_FLASH_FLASH_Pos (0UL) /!< Position of FLASH field. /
jamesadevine	0:e1a608bb55e8	1214	#define FICR_INFO_FLASH_FLASH_Msk (0xFFFFFFFFUL << FICR_INFO_FLASH_FLASH_Pos) /!< Bit mask of FLASH field. /
jamesadevine	0:e1a608bb55e8	1215	#define FICR_INFO_FLASH_FLASH_Unspecified (0xFFFFFFFFUL) /!< Unspecified /
jamesadevine	0:e1a608bb55e8	1216	#define FICR_INFO_FLASH_FLASH_K128 (128UL) /!< 128 kByte FLASH. /
jamesadevine	0:e1a608bb55e8	1217	#define FICR_INFO_FLASH_FLASH_K256 (256UL) /!< 256 kByte FLASH. /
jamesadevine	0:e1a608bb55e8	1218
jamesadevine	0:e1a608bb55e8	1219
jamesadevine	0:e1a608bb55e8	1220	/* Peripheral: GPIO */
jamesadevine	0:e1a608bb55e8	1221	/* Description: General purpose input and output. */
jamesadevine	0:e1a608bb55e8	1222
jamesadevine	0:e1a608bb55e8	1223	/* Register: GPIO_OUT */
jamesadevine	0:e1a608bb55e8	1224	/* Description: Write GPIO port. */
jamesadevine	0:e1a608bb55e8	1225
jamesadevine	0:e1a608bb55e8	1226	/* Bit 31 : Pin 31. */
jamesadevine	0:e1a608bb55e8	1227	#define GPIO_OUT_PIN31_Pos (31UL) /!< Position of PIN31 field. /
jamesadevine	0:e1a608bb55e8	1228	#define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /!< Bit mask of PIN31 field. /
jamesadevine	0:e1a608bb55e8	1229	#define GPIO_OUT_PIN31_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1230	#define GPIO_OUT_PIN31_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1231
jamesadevine	0:e1a608bb55e8	1232	/* Bit 30 : Pin 30. */
jamesadevine	0:e1a608bb55e8	1233	#define GPIO_OUT_PIN30_Pos (30UL) /!< Position of PIN30 field. /
jamesadevine	0:e1a608bb55e8	1234	#define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /!< Bit mask of PIN30 field. /
jamesadevine	0:e1a608bb55e8	1235	#define GPIO_OUT_PIN30_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1236	#define GPIO_OUT_PIN30_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1237
jamesadevine	0:e1a608bb55e8	1238	/* Bit 29 : Pin 29. */
jamesadevine	0:e1a608bb55e8	1239	#define GPIO_OUT_PIN29_Pos (29UL) /!< Position of PIN29 field. /
jamesadevine	0:e1a608bb55e8	1240	#define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /!< Bit mask of PIN29 field. /
jamesadevine	0:e1a608bb55e8	1241	#define GPIO_OUT_PIN29_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1242	#define GPIO_OUT_PIN29_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1243
jamesadevine	0:e1a608bb55e8	1244	/* Bit 28 : Pin 28. */
jamesadevine	0:e1a608bb55e8	1245	#define GPIO_OUT_PIN28_Pos (28UL) /!< Position of PIN28 field. /
jamesadevine	0:e1a608bb55e8	1246	#define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /!< Bit mask of PIN28 field. /
jamesadevine	0:e1a608bb55e8	1247	#define GPIO_OUT_PIN28_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1248	#define GPIO_OUT_PIN28_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1249
jamesadevine	0:e1a608bb55e8	1250	/* Bit 27 : Pin 27. */
jamesadevine	0:e1a608bb55e8	1251	#define GPIO_OUT_PIN27_Pos (27UL) /!< Position of PIN27 field. /
jamesadevine	0:e1a608bb55e8	1252	#define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /!< Bit mask of PIN27 field. /
jamesadevine	0:e1a608bb55e8	1253	#define GPIO_OUT_PIN27_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1254	#define GPIO_OUT_PIN27_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1255
jamesadevine	0:e1a608bb55e8	1256	/* Bit 26 : Pin 26. */
jamesadevine	0:e1a608bb55e8	1257	#define GPIO_OUT_PIN26_Pos (26UL) /!< Position of PIN26 field. /
jamesadevine	0:e1a608bb55e8	1258	#define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /!< Bit mask of PIN26 field. /
jamesadevine	0:e1a608bb55e8	1259	#define GPIO_OUT_PIN26_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1260	#define GPIO_OUT_PIN26_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1261
jamesadevine	0:e1a608bb55e8	1262	/* Bit 25 : Pin 25. */
jamesadevine	0:e1a608bb55e8	1263	#define GPIO_OUT_PIN25_Pos (25UL) /!< Position of PIN25 field. /
jamesadevine	0:e1a608bb55e8	1264	#define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /!< Bit mask of PIN25 field. /
jamesadevine	0:e1a608bb55e8	1265	#define GPIO_OUT_PIN25_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1266	#define GPIO_OUT_PIN25_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1267
jamesadevine	0:e1a608bb55e8	1268	/* Bit 24 : Pin 24. */
jamesadevine	0:e1a608bb55e8	1269	#define GPIO_OUT_PIN24_Pos (24UL) /!< Position of PIN24 field. /
jamesadevine	0:e1a608bb55e8	1270	#define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /!< Bit mask of PIN24 field. /
jamesadevine	0:e1a608bb55e8	1271	#define GPIO_OUT_PIN24_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1272	#define GPIO_OUT_PIN24_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1273
jamesadevine	0:e1a608bb55e8	1274	/* Bit 23 : Pin 23. */
jamesadevine	0:e1a608bb55e8	1275	#define GPIO_OUT_PIN23_Pos (23UL) /!< Position of PIN23 field. /
jamesadevine	0:e1a608bb55e8	1276	#define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /!< Bit mask of PIN23 field. /
jamesadevine	0:e1a608bb55e8	1277	#define GPIO_OUT_PIN23_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1278	#define GPIO_OUT_PIN23_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1279
jamesadevine	0:e1a608bb55e8	1280	/* Bit 22 : Pin 22. */
jamesadevine	0:e1a608bb55e8	1281	#define GPIO_OUT_PIN22_Pos (22UL) /!< Position of PIN22 field. /
jamesadevine	0:e1a608bb55e8	1282	#define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /!< Bit mask of PIN22 field. /
jamesadevine	0:e1a608bb55e8	1283	#define GPIO_OUT_PIN22_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1284	#define GPIO_OUT_PIN22_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1285
jamesadevine	0:e1a608bb55e8	1286	/* Bit 21 : Pin 21. */
jamesadevine	0:e1a608bb55e8	1287	#define GPIO_OUT_PIN21_Pos (21UL) /!< Position of PIN21 field. /
jamesadevine	0:e1a608bb55e8	1288	#define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /!< Bit mask of PIN21 field. /
jamesadevine	0:e1a608bb55e8	1289	#define GPIO_OUT_PIN21_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1290	#define GPIO_OUT_PIN21_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1291
jamesadevine	0:e1a608bb55e8	1292	/* Bit 20 : Pin 20. */
jamesadevine	0:e1a608bb55e8	1293	#define GPIO_OUT_PIN20_Pos (20UL) /!< Position of PIN20 field. /
jamesadevine	0:e1a608bb55e8	1294	#define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /!< Bit mask of PIN20 field. /
jamesadevine	0:e1a608bb55e8	1295	#define GPIO_OUT_PIN20_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1296	#define GPIO_OUT_PIN20_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1297
jamesadevine	0:e1a608bb55e8	1298	/* Bit 19 : Pin 19. */
jamesadevine	0:e1a608bb55e8	1299	#define GPIO_OUT_PIN19_Pos (19UL) /!< Position of PIN19 field. /
jamesadevine	0:e1a608bb55e8	1300	#define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /!< Bit mask of PIN19 field. /
jamesadevine	0:e1a608bb55e8	1301	#define GPIO_OUT_PIN19_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1302	#define GPIO_OUT_PIN19_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1303
jamesadevine	0:e1a608bb55e8	1304	/* Bit 18 : Pin 18. */
jamesadevine	0:e1a608bb55e8	1305	#define GPIO_OUT_PIN18_Pos (18UL) /!< Position of PIN18 field. /
jamesadevine	0:e1a608bb55e8	1306	#define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /!< Bit mask of PIN18 field. /
jamesadevine	0:e1a608bb55e8	1307	#define GPIO_OUT_PIN18_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1308	#define GPIO_OUT_PIN18_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1309
jamesadevine	0:e1a608bb55e8	1310	/* Bit 17 : Pin 17. */
jamesadevine	0:e1a608bb55e8	1311	#define GPIO_OUT_PIN17_Pos (17UL) /!< Position of PIN17 field. /
jamesadevine	0:e1a608bb55e8	1312	#define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /!< Bit mask of PIN17 field. /
jamesadevine	0:e1a608bb55e8	1313	#define GPIO_OUT_PIN17_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1314	#define GPIO_OUT_PIN17_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1315
jamesadevine	0:e1a608bb55e8	1316	/* Bit 16 : Pin 16. */
jamesadevine	0:e1a608bb55e8	1317	#define GPIO_OUT_PIN16_Pos (16UL) /!< Position of PIN16 field. /
jamesadevine	0:e1a608bb55e8	1318	#define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /!< Bit mask of PIN16 field. /
jamesadevine	0:e1a608bb55e8	1319	#define GPIO_OUT_PIN16_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1320	#define GPIO_OUT_PIN16_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1321
jamesadevine	0:e1a608bb55e8	1322	/* Bit 15 : Pin 15. */
jamesadevine	0:e1a608bb55e8	1323	#define GPIO_OUT_PIN15_Pos (15UL) /!< Position of PIN15 field. /
jamesadevine	0:e1a608bb55e8	1324	#define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /!< Bit mask of PIN15 field. /
jamesadevine	0:e1a608bb55e8	1325	#define GPIO_OUT_PIN15_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1326	#define GPIO_OUT_PIN15_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1327
jamesadevine	0:e1a608bb55e8	1328	/* Bit 14 : Pin 14. */
jamesadevine	0:e1a608bb55e8	1329	#define GPIO_OUT_PIN14_Pos (14UL) /!< Position of PIN14 field. /
jamesadevine	0:e1a608bb55e8	1330	#define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /!< Bit mask of PIN14 field. /
jamesadevine	0:e1a608bb55e8	1331	#define GPIO_OUT_PIN14_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1332	#define GPIO_OUT_PIN14_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1333
jamesadevine	0:e1a608bb55e8	1334	/* Bit 13 : Pin 13. */
jamesadevine	0:e1a608bb55e8	1335	#define GPIO_OUT_PIN13_Pos (13UL) /!< Position of PIN13 field. /
jamesadevine	0:e1a608bb55e8	1336	#define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /!< Bit mask of PIN13 field. /
jamesadevine	0:e1a608bb55e8	1337	#define GPIO_OUT_PIN13_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1338	#define GPIO_OUT_PIN13_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1339
jamesadevine	0:e1a608bb55e8	1340	/* Bit 12 : Pin 12. */
jamesadevine	0:e1a608bb55e8	1341	#define GPIO_OUT_PIN12_Pos (12UL) /!< Position of PIN12 field. /
jamesadevine	0:e1a608bb55e8	1342	#define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /!< Bit mask of PIN12 field. /
jamesadevine	0:e1a608bb55e8	1343	#define GPIO_OUT_PIN12_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1344	#define GPIO_OUT_PIN12_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1345
jamesadevine	0:e1a608bb55e8	1346	/* Bit 11 : Pin 11. */
jamesadevine	0:e1a608bb55e8	1347	#define GPIO_OUT_PIN11_Pos (11UL) /!< Position of PIN11 field. /
jamesadevine	0:e1a608bb55e8	1348	#define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /!< Bit mask of PIN11 field. /
jamesadevine	0:e1a608bb55e8	1349	#define GPIO_OUT_PIN11_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1350	#define GPIO_OUT_PIN11_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1351
jamesadevine	0:e1a608bb55e8	1352	/* Bit 10 : Pin 10. */
jamesadevine	0:e1a608bb55e8	1353	#define GPIO_OUT_PIN10_Pos (10UL) /!< Position of PIN10 field. /
jamesadevine	0:e1a608bb55e8	1354	#define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /!< Bit mask of PIN10 field. /
jamesadevine	0:e1a608bb55e8	1355	#define GPIO_OUT_PIN10_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1356	#define GPIO_OUT_PIN10_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1357
jamesadevine	0:e1a608bb55e8	1358	/* Bit 9 : Pin 9. */
jamesadevine	0:e1a608bb55e8	1359	#define GPIO_OUT_PIN9_Pos (9UL) /!< Position of PIN9 field. /
jamesadevine	0:e1a608bb55e8	1360	#define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /!< Bit mask of PIN9 field. /
jamesadevine	0:e1a608bb55e8	1361	#define GPIO_OUT_PIN9_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1362	#define GPIO_OUT_PIN9_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1363
jamesadevine	0:e1a608bb55e8	1364	/* Bit 8 : Pin 8. */
jamesadevine	0:e1a608bb55e8	1365	#define GPIO_OUT_PIN8_Pos (8UL) /!< Position of PIN8 field. /
jamesadevine	0:e1a608bb55e8	1366	#define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /!< Bit mask of PIN8 field. /
jamesadevine	0:e1a608bb55e8	1367	#define GPIO_OUT_PIN8_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1368	#define GPIO_OUT_PIN8_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1369
jamesadevine	0:e1a608bb55e8	1370	/* Bit 7 : Pin 7. */
jamesadevine	0:e1a608bb55e8	1371	#define GPIO_OUT_PIN7_Pos (7UL) /!< Position of PIN7 field. /
jamesadevine	0:e1a608bb55e8	1372	#define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /!< Bit mask of PIN7 field. /
jamesadevine	0:e1a608bb55e8	1373	#define GPIO_OUT_PIN7_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1374	#define GPIO_OUT_PIN7_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1375
jamesadevine	0:e1a608bb55e8	1376	/* Bit 6 : Pin 6. */
jamesadevine	0:e1a608bb55e8	1377	#define GPIO_OUT_PIN6_Pos (6UL) /!< Position of PIN6 field. /
jamesadevine	0:e1a608bb55e8	1378	#define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /!< Bit mask of PIN6 field. /
jamesadevine	0:e1a608bb55e8	1379	#define GPIO_OUT_PIN6_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1380	#define GPIO_OUT_PIN6_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1381
jamesadevine	0:e1a608bb55e8	1382	/* Bit 5 : Pin 5. */
jamesadevine	0:e1a608bb55e8	1383	#define GPIO_OUT_PIN5_Pos (5UL) /!< Position of PIN5 field. /
jamesadevine	0:e1a608bb55e8	1384	#define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /!< Bit mask of PIN5 field. /
jamesadevine	0:e1a608bb55e8	1385	#define GPIO_OUT_PIN5_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1386	#define GPIO_OUT_PIN5_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1387
jamesadevine	0:e1a608bb55e8	1388	/* Bit 4 : Pin 4. */
jamesadevine	0:e1a608bb55e8	1389	#define GPIO_OUT_PIN4_Pos (4UL) /!< Position of PIN4 field. /
jamesadevine	0:e1a608bb55e8	1390	#define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /!< Bit mask of PIN4 field. /
jamesadevine	0:e1a608bb55e8	1391	#define GPIO_OUT_PIN4_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1392	#define GPIO_OUT_PIN4_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1393
jamesadevine	0:e1a608bb55e8	1394	/* Bit 3 : Pin 3. */
jamesadevine	0:e1a608bb55e8	1395	#define GPIO_OUT_PIN3_Pos (3UL) /!< Position of PIN3 field. /
jamesadevine	0:e1a608bb55e8	1396	#define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /!< Bit mask of PIN3 field. /
jamesadevine	0:e1a608bb55e8	1397	#define GPIO_OUT_PIN3_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1398	#define GPIO_OUT_PIN3_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1399
jamesadevine	0:e1a608bb55e8	1400	/* Bit 2 : Pin 2. */
jamesadevine	0:e1a608bb55e8	1401	#define GPIO_OUT_PIN2_Pos (2UL) /!< Position of PIN2 field. /
jamesadevine	0:e1a608bb55e8	1402	#define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /!< Bit mask of PIN2 field. /
jamesadevine	0:e1a608bb55e8	1403	#define GPIO_OUT_PIN2_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1404	#define GPIO_OUT_PIN2_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1405
jamesadevine	0:e1a608bb55e8	1406	/* Bit 1 : Pin 1. */
jamesadevine	0:e1a608bb55e8	1407	#define GPIO_OUT_PIN1_Pos (1UL) /!< Position of PIN1 field. /
jamesadevine	0:e1a608bb55e8	1408	#define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /!< Bit mask of PIN1 field. /
jamesadevine	0:e1a608bb55e8	1409	#define GPIO_OUT_PIN1_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1410	#define GPIO_OUT_PIN1_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1411
jamesadevine	0:e1a608bb55e8	1412	/* Bit 0 : Pin 0. */
jamesadevine	0:e1a608bb55e8	1413	#define GPIO_OUT_PIN0_Pos (0UL) /!< Position of PIN0 field. /
jamesadevine	0:e1a608bb55e8	1414	#define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /!< Bit mask of PIN0 field. /
jamesadevine	0:e1a608bb55e8	1415	#define GPIO_OUT_PIN0_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1416	#define GPIO_OUT_PIN0_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1417
jamesadevine	0:e1a608bb55e8	1418	/* Register: GPIO_OUTSET */
jamesadevine	0:e1a608bb55e8	1419	/* Description: Set individual bits in GPIO port. */
jamesadevine	0:e1a608bb55e8	1420
jamesadevine	0:e1a608bb55e8	1421	/* Bit 31 : Pin 31. */
jamesadevine	0:e1a608bb55e8	1422	#define GPIO_OUTSET_PIN31_Pos (31UL) /!< Position of PIN31 field. /
jamesadevine	0:e1a608bb55e8	1423	#define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /!< Bit mask of PIN31 field. /
jamesadevine	0:e1a608bb55e8	1424	#define GPIO_OUTSET_PIN31_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1425	#define GPIO_OUTSET_PIN31_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1426	#define GPIO_OUTSET_PIN31_Set (1UL) /!< Set pin driver high. /
jamesadevine	0:e1a608bb55e8	1427
jamesadevine	0:e1a608bb55e8	1428	/* Bit 30 : Pin 30. */
jamesadevine	0:e1a608bb55e8	1429	#define GPIO_OUTSET_PIN30_Pos (30UL) /!< Position of PIN30 field. /
jamesadevine	0:e1a608bb55e8	1430	#define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /!< Bit mask of PIN30 field. /
jamesadevine	0:e1a608bb55e8	1431	#define GPIO_OUTSET_PIN30_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1432	#define GPIO_OUTSET_PIN30_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1433	#define GPIO_OUTSET_PIN30_Set (1UL) /!< Set pin driver high. /
jamesadevine	0:e1a608bb55e8	1434
jamesadevine	0:e1a608bb55e8	1435	/* Bit 29 : Pin 29. */
jamesadevine	0:e1a608bb55e8	1436	#define GPIO_OUTSET_PIN29_Pos (29UL) /!< Position of PIN29 field. /
jamesadevine	0:e1a608bb55e8	1437	#define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /!< Bit mask of PIN29 field. /
jamesadevine	0:e1a608bb55e8	1438	#define GPIO_OUTSET_PIN29_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1439	#define GPIO_OUTSET_PIN29_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1440	#define GPIO_OUTSET_PIN29_Set (1UL) /!< Set pin driver high. /
jamesadevine	0:e1a608bb55e8	1441
jamesadevine	0:e1a608bb55e8	1442	/* Bit 28 : Pin 28. */
jamesadevine	0:e1a608bb55e8	1443	#define GPIO_OUTSET_PIN28_Pos (28UL) /!< Position of PIN28 field. /
jamesadevine	0:e1a608bb55e8	1444	#define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /!< Bit mask of PIN28 field. /
jamesadevine	0:e1a608bb55e8	1445	#define GPIO_OUTSET_PIN28_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1446	#define GPIO_OUTSET_PIN28_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1447	#define GPIO_OUTSET_PIN28_Set (1UL) /!< Set pin driver high. /
jamesadevine	0:e1a608bb55e8	1448
jamesadevine	0:e1a608bb55e8	1449	/* Bit 27 : Pin 27. */
jamesadevine	0:e1a608bb55e8	1450	#define GPIO_OUTSET_PIN27_Pos (27UL) /!< Position of PIN27 field. /
jamesadevine	0:e1a608bb55e8	1451	#define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /!< Bit mask of PIN27 field. /
jamesadevine	0:e1a608bb55e8	1452	#define GPIO_OUTSET_PIN27_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1453	#define GPIO_OUTSET_PIN27_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1454	#define GPIO_OUTSET_PIN27_Set (1UL) /!< Set pin driver high. /
jamesadevine	0:e1a608bb55e8	1455
jamesadevine	0:e1a608bb55e8	1456	/* Bit 26 : Pin 26. */
jamesadevine	0:e1a608bb55e8	1457	#define GPIO_OUTSET_PIN26_Pos (26UL) /!< Position of PIN26 field. /
jamesadevine	0:e1a608bb55e8	1458	#define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /!< Bit mask of PIN26 field. /
jamesadevine	0:e1a608bb55e8	1459	#define GPIO_OUTSET_PIN26_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1460	#define GPIO_OUTSET_PIN26_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1461	#define GPIO_OUTSET_PIN26_Set (1UL) /!< Set pin driver high. /
jamesadevine	0:e1a608bb55e8	1462
jamesadevine	0:e1a608bb55e8	1463	/* Bit 25 : Pin 25. */
jamesadevine	0:e1a608bb55e8	1464	#define GPIO_OUTSET_PIN25_Pos (25UL) /!< Position of PIN25 field. /
jamesadevine	0:e1a608bb55e8	1465	#define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /!< Bit mask of PIN25 field. /
jamesadevine	0:e1a608bb55e8	1466	#define GPIO_OUTSET_PIN25_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1467	#define GPIO_OUTSET_PIN25_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1468	#define GPIO_OUTSET_PIN25_Set (1UL) /!< Set pin driver high. /
jamesadevine	0:e1a608bb55e8	1469
jamesadevine	0:e1a608bb55e8	1470	/* Bit 24 : Pin 24. */
jamesadevine	0:e1a608bb55e8	1471	#define GPIO_OUTSET_PIN24_Pos (24UL) /!< Position of PIN24 field. /
jamesadevine	0:e1a608bb55e8	1472	#define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /!< Bit mask of PIN24 field. /
jamesadevine	0:e1a608bb55e8	1473	#define GPIO_OUTSET_PIN24_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1474	#define GPIO_OUTSET_PIN24_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1475	#define GPIO_OUTSET_PIN24_Set (1UL) /!< Set pin driver high. /
jamesadevine	0:e1a608bb55e8	1476
jamesadevine	0:e1a608bb55e8	1477	/* Bit 23 : Pin 23. */
jamesadevine	0:e1a608bb55e8	1478	#define GPIO_OUTSET_PIN23_Pos (23UL) /!< Position of PIN23 field. /
jamesadevine	0:e1a608bb55e8	1479	#define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /!< Bit mask of PIN23 field. /
jamesadevine	0:e1a608bb55e8	1480	#define GPIO_OUTSET_PIN23_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1481	#define GPIO_OUTSET_PIN23_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1482	#define GPIO_OUTSET_PIN23_Set (1UL) /!< Set pin driver high. /
jamesadevine	0:e1a608bb55e8	1483
jamesadevine	0:e1a608bb55e8	1484	/* Bit 22 : Pin 22. */
jamesadevine	0:e1a608bb55e8	1485	#define GPIO_OUTSET_PIN22_Pos (22UL) /!< Position of PIN22 field. /
jamesadevine	0:e1a608bb55e8	1486	#define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /!< Bit mask of PIN22 field. /
jamesadevine	0:e1a608bb55e8	1487	#define GPIO_OUTSET_PIN22_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1488	#define GPIO_OUTSET_PIN22_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1489	#define GPIO_OUTSET_PIN22_Set (1UL) /!< Set pin driver high. /
jamesadevine	0:e1a608bb55e8	1490
jamesadevine	0:e1a608bb55e8	1491	/* Bit 21 : Pin 21. */
jamesadevine	0:e1a608bb55e8	1492	#define GPIO_OUTSET_PIN21_Pos (21UL) /!< Position of PIN21 field. /
jamesadevine	0:e1a608bb55e8	1493	#define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /!< Bit mask of PIN21 field. /
jamesadevine	0:e1a608bb55e8	1494	#define GPIO_OUTSET_PIN21_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1495	#define GPIO_OUTSET_PIN21_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1496	#define GPIO_OUTSET_PIN21_Set (1UL) /!< Set pin driver high. /
jamesadevine	0:e1a608bb55e8	1497
jamesadevine	0:e1a608bb55e8	1498	/* Bit 20 : Pin 20. */
jamesadevine	0:e1a608bb55e8	1499	#define GPIO_OUTSET_PIN20_Pos (20UL) /!< Position of PIN20 field. /
jamesadevine	0:e1a608bb55e8	1500	#define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /!< Bit mask of PIN20 field. /
jamesadevine	0:e1a608bb55e8	1501	#define GPIO_OUTSET_PIN20_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1502	#define GPIO_OUTSET_PIN20_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1503	#define GPIO_OUTSET_PIN20_Set (1UL) /!< Set pin driver high. /
jamesadevine	0:e1a608bb55e8	1504
jamesadevine	0:e1a608bb55e8	1505	/* Bit 19 : Pin 19. */
jamesadevine	0:e1a608bb55e8	1506	#define GPIO_OUTSET_PIN19_Pos (19UL) /!< Position of PIN19 field. /
jamesadevine	0:e1a608bb55e8	1507	#define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /!< Bit mask of PIN19 field. /
jamesadevine	0:e1a608bb55e8	1508	#define GPIO_OUTSET_PIN19_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1509	#define GPIO_OUTSET_PIN19_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1510	#define GPIO_OUTSET_PIN19_Set (1UL) /!< Set pin driver high. /
jamesadevine	0:e1a608bb55e8	1511
jamesadevine	0:e1a608bb55e8	1512	/* Bit 18 : Pin 18. */
jamesadevine	0:e1a608bb55e8	1513	#define GPIO_OUTSET_PIN18_Pos (18UL) /!< Position of PIN18 field. /
jamesadevine	0:e1a608bb55e8	1514	#define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /!< Bit mask of PIN18 field. /
jamesadevine	0:e1a608bb55e8	1515	#define GPIO_OUTSET_PIN18_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1516	#define GPIO_OUTSET_PIN18_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1517	#define GPIO_OUTSET_PIN18_Set (1UL) /!< Set pin driver high. /
jamesadevine	0:e1a608bb55e8	1518
jamesadevine	0:e1a608bb55e8	1519	/* Bit 17 : Pin 17. */
jamesadevine	0:e1a608bb55e8	1520	#define GPIO_OUTSET_PIN17_Pos (17UL) /!< Position of PIN17 field. /
jamesadevine	0:e1a608bb55e8	1521	#define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /!< Bit mask of PIN17 field. /
jamesadevine	0:e1a608bb55e8	1522	#define GPIO_OUTSET_PIN17_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1523	#define GPIO_OUTSET_PIN17_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1524	#define GPIO_OUTSET_PIN17_Set (1UL) /!< Set pin driver high. /
jamesadevine	0:e1a608bb55e8	1525
jamesadevine	0:e1a608bb55e8	1526	/* Bit 16 : Pin 16. */
jamesadevine	0:e1a608bb55e8	1527	#define GPIO_OUTSET_PIN16_Pos (16UL) /!< Position of PIN16 field. /
jamesadevine	0:e1a608bb55e8	1528	#define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /!< Bit mask of PIN16 field. /
jamesadevine	0:e1a608bb55e8	1529	#define GPIO_OUTSET_PIN16_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1530	#define GPIO_OUTSET_PIN16_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1531	#define GPIO_OUTSET_PIN16_Set (1UL) /!< Set pin driver high. /
jamesadevine	0:e1a608bb55e8	1532
jamesadevine	0:e1a608bb55e8	1533	/* Bit 15 : Pin 15. */
jamesadevine	0:e1a608bb55e8	1534	#define GPIO_OUTSET_PIN15_Pos (15UL) /!< Position of PIN15 field. /
jamesadevine	0:e1a608bb55e8	1535	#define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /!< Bit mask of PIN15 field. /
jamesadevine	0:e1a608bb55e8	1536	#define GPIO_OUTSET_PIN15_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1537	#define GPIO_OUTSET_PIN15_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1538	#define GPIO_OUTSET_PIN15_Set (1UL) /!< Set pin driver high. /
jamesadevine	0:e1a608bb55e8	1539
jamesadevine	0:e1a608bb55e8	1540	/* Bit 14 : Pin 14. */
jamesadevine	0:e1a608bb55e8	1541	#define GPIO_OUTSET_PIN14_Pos (14UL) /!< Position of PIN14 field. /
jamesadevine	0:e1a608bb55e8	1542	#define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /!< Bit mask of PIN14 field. /
jamesadevine	0:e1a608bb55e8	1543	#define GPIO_OUTSET_PIN14_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1544	#define GPIO_OUTSET_PIN14_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1545	#define GPIO_OUTSET_PIN14_Set (1UL) /!< Set pin driver high. /
jamesadevine	0:e1a608bb55e8	1546
jamesadevine	0:e1a608bb55e8	1547	/* Bit 13 : Pin 13. */
jamesadevine	0:e1a608bb55e8	1548	#define GPIO_OUTSET_PIN13_Pos (13UL) /!< Position of PIN13 field. /
jamesadevine	0:e1a608bb55e8	1549	#define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /!< Bit mask of PIN13 field. /
jamesadevine	0:e1a608bb55e8	1550	#define GPIO_OUTSET_PIN13_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1551	#define GPIO_OUTSET_PIN13_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1552	#define GPIO_OUTSET_PIN13_Set (1UL) /!< Set pin driver high. /
jamesadevine	0:e1a608bb55e8	1553
jamesadevine	0:e1a608bb55e8	1554	/* Bit 12 : Pin 12. */
jamesadevine	0:e1a608bb55e8	1555	#define GPIO_OUTSET_PIN12_Pos (12UL) /!< Position of PIN12 field. /
jamesadevine	0:e1a608bb55e8	1556	#define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /!< Bit mask of PIN12 field. /
jamesadevine	0:e1a608bb55e8	1557	#define GPIO_OUTSET_PIN12_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1558	#define GPIO_OUTSET_PIN12_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1559	#define GPIO_OUTSET_PIN12_Set (1UL) /!< Set pin driver high. /
jamesadevine	0:e1a608bb55e8	1560
jamesadevine	0:e1a608bb55e8	1561	/* Bit 11 : Pin 11. */
jamesadevine	0:e1a608bb55e8	1562	#define GPIO_OUTSET_PIN11_Pos (11UL) /!< Position of PIN11 field. /
jamesadevine	0:e1a608bb55e8	1563	#define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /!< Bit mask of PIN11 field. /
jamesadevine	0:e1a608bb55e8	1564	#define GPIO_OUTSET_PIN11_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1565	#define GPIO_OUTSET_PIN11_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1566	#define GPIO_OUTSET_PIN11_Set (1UL) /!< Set pin driver high. /
jamesadevine	0:e1a608bb55e8	1567
jamesadevine	0:e1a608bb55e8	1568	/* Bit 10 : Pin 10. */
jamesadevine	0:e1a608bb55e8	1569	#define GPIO_OUTSET_PIN10_Pos (10UL) /!< Position of PIN10 field. /
jamesadevine	0:e1a608bb55e8	1570	#define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /!< Bit mask of PIN10 field. /
jamesadevine	0:e1a608bb55e8	1571	#define GPIO_OUTSET_PIN10_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1572	#define GPIO_OUTSET_PIN10_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1573	#define GPIO_OUTSET_PIN10_Set (1UL) /!< Set pin driver high. /
jamesadevine	0:e1a608bb55e8	1574
jamesadevine	0:e1a608bb55e8	1575	/* Bit 9 : Pin 9. */
jamesadevine	0:e1a608bb55e8	1576	#define GPIO_OUTSET_PIN9_Pos (9UL) /!< Position of PIN9 field. /
jamesadevine	0:e1a608bb55e8	1577	#define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /!< Bit mask of PIN9 field. /
jamesadevine	0:e1a608bb55e8	1578	#define GPIO_OUTSET_PIN9_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1579	#define GPIO_OUTSET_PIN9_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1580	#define GPIO_OUTSET_PIN9_Set (1UL) /!< Set pin driver high. /
jamesadevine	0:e1a608bb55e8	1581
jamesadevine	0:e1a608bb55e8	1582	/* Bit 8 : Pin 8. */
jamesadevine	0:e1a608bb55e8	1583	#define GPIO_OUTSET_PIN8_Pos (8UL) /!< Position of PIN8 field. /
jamesadevine	0:e1a608bb55e8	1584	#define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /!< Bit mask of PIN8 field. /
jamesadevine	0:e1a608bb55e8	1585	#define GPIO_OUTSET_PIN8_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1586	#define GPIO_OUTSET_PIN8_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1587	#define GPIO_OUTSET_PIN8_Set (1UL) /!< Set pin driver high. /
jamesadevine	0:e1a608bb55e8	1588
jamesadevine	0:e1a608bb55e8	1589	/* Bit 7 : Pin 7. */
jamesadevine	0:e1a608bb55e8	1590	#define GPIO_OUTSET_PIN7_Pos (7UL) /!< Position of PIN7 field. /
jamesadevine	0:e1a608bb55e8	1591	#define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /!< Bit mask of PIN7 field. /
jamesadevine	0:e1a608bb55e8	1592	#define GPIO_OUTSET_PIN7_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1593	#define GPIO_OUTSET_PIN7_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1594	#define GPIO_OUTSET_PIN7_Set (1UL) /!< Set pin driver high. /
jamesadevine	0:e1a608bb55e8	1595
jamesadevine	0:e1a608bb55e8	1596	/* Bit 6 : Pin 6. */
jamesadevine	0:e1a608bb55e8	1597	#define GPIO_OUTSET_PIN6_Pos (6UL) /!< Position of PIN6 field. /
jamesadevine	0:e1a608bb55e8	1598	#define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /!< Bit mask of PIN6 field. /
jamesadevine	0:e1a608bb55e8	1599	#define GPIO_OUTSET_PIN6_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1600	#define GPIO_OUTSET_PIN6_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1601	#define GPIO_OUTSET_PIN6_Set (1UL) /!< Set pin driver high. /
jamesadevine	0:e1a608bb55e8	1602
jamesadevine	0:e1a608bb55e8	1603	/* Bit 5 : Pin 5. */
jamesadevine	0:e1a608bb55e8	1604	#define GPIO_OUTSET_PIN5_Pos (5UL) /!< Position of PIN5 field. /
jamesadevine	0:e1a608bb55e8	1605	#define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /!< Bit mask of PIN5 field. /
jamesadevine	0:e1a608bb55e8	1606	#define GPIO_OUTSET_PIN5_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1607	#define GPIO_OUTSET_PIN5_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1608	#define GPIO_OUTSET_PIN5_Set (1UL) /!< Set pin driver high. /
jamesadevine	0:e1a608bb55e8	1609
jamesadevine	0:e1a608bb55e8	1610	/* Bit 4 : Pin 4. */
jamesadevine	0:e1a608bb55e8	1611	#define GPIO_OUTSET_PIN4_Pos (4UL) /!< Position of PIN4 field. /
jamesadevine	0:e1a608bb55e8	1612	#define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /!< Bit mask of PIN4 field. /
jamesadevine	0:e1a608bb55e8	1613	#define GPIO_OUTSET_PIN4_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1614	#define GPIO_OUTSET_PIN4_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1615	#define GPIO_OUTSET_PIN4_Set (1UL) /!< Set pin driver high. /
jamesadevine	0:e1a608bb55e8	1616
jamesadevine	0:e1a608bb55e8	1617	/* Bit 3 : Pin 3. */
jamesadevine	0:e1a608bb55e8	1618	#define GPIO_OUTSET_PIN3_Pos (3UL) /!< Position of PIN3 field. /
jamesadevine	0:e1a608bb55e8	1619	#define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /!< Bit mask of PIN3 field. /
jamesadevine	0:e1a608bb55e8	1620	#define GPIO_OUTSET_PIN3_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1621	#define GPIO_OUTSET_PIN3_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1622	#define GPIO_OUTSET_PIN3_Set (1UL) /!< Set pin driver high. /
jamesadevine	0:e1a608bb55e8	1623
jamesadevine	0:e1a608bb55e8	1624	/* Bit 2 : Pin 2. */
jamesadevine	0:e1a608bb55e8	1625	#define GPIO_OUTSET_PIN2_Pos (2UL) /!< Position of PIN2 field. /
jamesadevine	0:e1a608bb55e8	1626	#define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /!< Bit mask of PIN2 field. /
jamesadevine	0:e1a608bb55e8	1627	#define GPIO_OUTSET_PIN2_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1628	#define GPIO_OUTSET_PIN2_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1629	#define GPIO_OUTSET_PIN2_Set (1UL) /!< Set pin driver high. /
jamesadevine	0:e1a608bb55e8	1630
jamesadevine	0:e1a608bb55e8	1631	/* Bit 1 : Pin 1. */
jamesadevine	0:e1a608bb55e8	1632	#define GPIO_OUTSET_PIN1_Pos (1UL) /!< Position of PIN1 field. /
jamesadevine	0:e1a608bb55e8	1633	#define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /!< Bit mask of PIN1 field. /
jamesadevine	0:e1a608bb55e8	1634	#define GPIO_OUTSET_PIN1_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1635	#define GPIO_OUTSET_PIN1_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1636	#define GPIO_OUTSET_PIN1_Set (1UL) /!< Set pin driver high. /
jamesadevine	0:e1a608bb55e8	1637
jamesadevine	0:e1a608bb55e8	1638	/* Bit 0 : Pin 0. */
jamesadevine	0:e1a608bb55e8	1639	#define GPIO_OUTSET_PIN0_Pos (0UL) /!< Position of PIN0 field. /
jamesadevine	0:e1a608bb55e8	1640	#define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /!< Bit mask of PIN0 field. /
jamesadevine	0:e1a608bb55e8	1641	#define GPIO_OUTSET_PIN0_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1642	#define GPIO_OUTSET_PIN0_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1643	#define GPIO_OUTSET_PIN0_Set (1UL) /!< Set pin driver high. /
jamesadevine	0:e1a608bb55e8	1644
jamesadevine	0:e1a608bb55e8	1645	/* Register: GPIO_OUTCLR */
jamesadevine	0:e1a608bb55e8	1646	/* Description: Clear individual bits in GPIO port. */
jamesadevine	0:e1a608bb55e8	1647
jamesadevine	0:e1a608bb55e8	1648	/* Bit 31 : Pin 31. */
jamesadevine	0:e1a608bb55e8	1649	#define GPIO_OUTCLR_PIN31_Pos (31UL) /!< Position of PIN31 field. /
jamesadevine	0:e1a608bb55e8	1650	#define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /!< Bit mask of PIN31 field. /
jamesadevine	0:e1a608bb55e8	1651	#define GPIO_OUTCLR_PIN31_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1652	#define GPIO_OUTCLR_PIN31_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1653	#define GPIO_OUTCLR_PIN31_Clear (1UL) /!< Set pin driver low. /
jamesadevine	0:e1a608bb55e8	1654
jamesadevine	0:e1a608bb55e8	1655	/* Bit 30 : Pin 30. */
jamesadevine	0:e1a608bb55e8	1656	#define GPIO_OUTCLR_PIN30_Pos (30UL) /!< Position of PIN30 field. /
jamesadevine	0:e1a608bb55e8	1657	#define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /!< Bit mask of PIN30 field. /
jamesadevine	0:e1a608bb55e8	1658	#define GPIO_OUTCLR_PIN30_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1659	#define GPIO_OUTCLR_PIN30_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1660	#define GPIO_OUTCLR_PIN30_Clear (1UL) /!< Set pin driver low. /
jamesadevine	0:e1a608bb55e8	1661
jamesadevine	0:e1a608bb55e8	1662	/* Bit 29 : Pin 29. */
jamesadevine	0:e1a608bb55e8	1663	#define GPIO_OUTCLR_PIN29_Pos (29UL) /!< Position of PIN29 field. /
jamesadevine	0:e1a608bb55e8	1664	#define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /!< Bit mask of PIN29 field. /
jamesadevine	0:e1a608bb55e8	1665	#define GPIO_OUTCLR_PIN29_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1666	#define GPIO_OUTCLR_PIN29_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1667	#define GPIO_OUTCLR_PIN29_Clear (1UL) /!< Set pin driver low. /
jamesadevine	0:e1a608bb55e8	1668
jamesadevine	0:e1a608bb55e8	1669	/* Bit 28 : Pin 28. */
jamesadevine	0:e1a608bb55e8	1670	#define GPIO_OUTCLR_PIN28_Pos (28UL) /!< Position of PIN28 field. /
jamesadevine	0:e1a608bb55e8	1671	#define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /!< Bit mask of PIN28 field. /
jamesadevine	0:e1a608bb55e8	1672	#define GPIO_OUTCLR_PIN28_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1673	#define GPIO_OUTCLR_PIN28_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1674	#define GPIO_OUTCLR_PIN28_Clear (1UL) /!< Set pin driver low. /
jamesadevine	0:e1a608bb55e8	1675
jamesadevine	0:e1a608bb55e8	1676	/* Bit 27 : Pin 27. */
jamesadevine	0:e1a608bb55e8	1677	#define GPIO_OUTCLR_PIN27_Pos (27UL) /!< Position of PIN27 field. /
jamesadevine	0:e1a608bb55e8	1678	#define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /!< Bit mask of PIN27 field. /
jamesadevine	0:e1a608bb55e8	1679	#define GPIO_OUTCLR_PIN27_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1680	#define GPIO_OUTCLR_PIN27_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1681	#define GPIO_OUTCLR_PIN27_Clear (1UL) /!< Set pin driver low. /
jamesadevine	0:e1a608bb55e8	1682
jamesadevine	0:e1a608bb55e8	1683	/* Bit 26 : Pin 26. */
jamesadevine	0:e1a608bb55e8	1684	#define GPIO_OUTCLR_PIN26_Pos (26UL) /!< Position of PIN26 field. /
jamesadevine	0:e1a608bb55e8	1685	#define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /!< Bit mask of PIN26 field. /
jamesadevine	0:e1a608bb55e8	1686	#define GPIO_OUTCLR_PIN26_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1687	#define GPIO_OUTCLR_PIN26_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1688	#define GPIO_OUTCLR_PIN26_Clear (1UL) /!< Set pin driver low. /
jamesadevine	0:e1a608bb55e8	1689
jamesadevine	0:e1a608bb55e8	1690	/* Bit 25 : Pin 25. */
jamesadevine	0:e1a608bb55e8	1691	#define GPIO_OUTCLR_PIN25_Pos (25UL) /!< Position of PIN25 field. /
jamesadevine	0:e1a608bb55e8	1692	#define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /!< Bit mask of PIN25 field. /
jamesadevine	0:e1a608bb55e8	1693	#define GPIO_OUTCLR_PIN25_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1694	#define GPIO_OUTCLR_PIN25_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1695	#define GPIO_OUTCLR_PIN25_Clear (1UL) /!< Set pin driver low. /
jamesadevine	0:e1a608bb55e8	1696
jamesadevine	0:e1a608bb55e8	1697	/* Bit 24 : Pin 24. */
jamesadevine	0:e1a608bb55e8	1698	#define GPIO_OUTCLR_PIN24_Pos (24UL) /!< Position of PIN24 field. /
jamesadevine	0:e1a608bb55e8	1699	#define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /!< Bit mask of PIN24 field. /
jamesadevine	0:e1a608bb55e8	1700	#define GPIO_OUTCLR_PIN24_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1701	#define GPIO_OUTCLR_PIN24_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1702	#define GPIO_OUTCLR_PIN24_Clear (1UL) /!< Set pin driver low. /
jamesadevine	0:e1a608bb55e8	1703
jamesadevine	0:e1a608bb55e8	1704	/* Bit 23 : Pin 23. */
jamesadevine	0:e1a608bb55e8	1705	#define GPIO_OUTCLR_PIN23_Pos (23UL) /!< Position of PIN23 field. /
jamesadevine	0:e1a608bb55e8	1706	#define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /!< Bit mask of PIN23 field. /
jamesadevine	0:e1a608bb55e8	1707	#define GPIO_OUTCLR_PIN23_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1708	#define GPIO_OUTCLR_PIN23_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1709	#define GPIO_OUTCLR_PIN23_Clear (1UL) /!< Set pin driver low. /
jamesadevine	0:e1a608bb55e8	1710
jamesadevine	0:e1a608bb55e8	1711	/* Bit 22 : Pin 22. */
jamesadevine	0:e1a608bb55e8	1712	#define GPIO_OUTCLR_PIN22_Pos (22UL) /!< Position of PIN22 field. /
jamesadevine	0:e1a608bb55e8	1713	#define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /!< Bit mask of PIN22 field. /
jamesadevine	0:e1a608bb55e8	1714	#define GPIO_OUTCLR_PIN22_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1715	#define GPIO_OUTCLR_PIN22_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1716	#define GPIO_OUTCLR_PIN22_Clear (1UL) /!< Set pin driver low. /
jamesadevine	0:e1a608bb55e8	1717
jamesadevine	0:e1a608bb55e8	1718	/* Bit 21 : Pin 21. */
jamesadevine	0:e1a608bb55e8	1719	#define GPIO_OUTCLR_PIN21_Pos (21UL) /!< Position of PIN21 field. /
jamesadevine	0:e1a608bb55e8	1720	#define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /!< Bit mask of PIN21 field. /
jamesadevine	0:e1a608bb55e8	1721	#define GPIO_OUTCLR_PIN21_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1722	#define GPIO_OUTCLR_PIN21_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1723	#define GPIO_OUTCLR_PIN21_Clear (1UL) /!< Set pin driver low. /
jamesadevine	0:e1a608bb55e8	1724
jamesadevine	0:e1a608bb55e8	1725	/* Bit 20 : Pin 20. */
jamesadevine	0:e1a608bb55e8	1726	#define GPIO_OUTCLR_PIN20_Pos (20UL) /!< Position of PIN20 field. /
jamesadevine	0:e1a608bb55e8	1727	#define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /!< Bit mask of PIN20 field. /
jamesadevine	0:e1a608bb55e8	1728	#define GPIO_OUTCLR_PIN20_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1729	#define GPIO_OUTCLR_PIN20_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1730	#define GPIO_OUTCLR_PIN20_Clear (1UL) /!< Set pin driver low. /
jamesadevine	0:e1a608bb55e8	1731
jamesadevine	0:e1a608bb55e8	1732	/* Bit 19 : Pin 19. */
jamesadevine	0:e1a608bb55e8	1733	#define GPIO_OUTCLR_PIN19_Pos (19UL) /!< Position of PIN19 field. /
jamesadevine	0:e1a608bb55e8	1734	#define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /!< Bit mask of PIN19 field. /
jamesadevine	0:e1a608bb55e8	1735	#define GPIO_OUTCLR_PIN19_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1736	#define GPIO_OUTCLR_PIN19_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1737	#define GPIO_OUTCLR_PIN19_Clear (1UL) /!< Set pin driver low. /
jamesadevine	0:e1a608bb55e8	1738
jamesadevine	0:e1a608bb55e8	1739	/* Bit 18 : Pin 18. */
jamesadevine	0:e1a608bb55e8	1740	#define GPIO_OUTCLR_PIN18_Pos (18UL) /!< Position of PIN18 field. /
jamesadevine	0:e1a608bb55e8	1741	#define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /!< Bit mask of PIN18 field. /
jamesadevine	0:e1a608bb55e8	1742	#define GPIO_OUTCLR_PIN18_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1743	#define GPIO_OUTCLR_PIN18_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1744	#define GPIO_OUTCLR_PIN18_Clear (1UL) /!< Set pin driver low. /
jamesadevine	0:e1a608bb55e8	1745
jamesadevine	0:e1a608bb55e8	1746	/* Bit 17 : Pin 17. */
jamesadevine	0:e1a608bb55e8	1747	#define GPIO_OUTCLR_PIN17_Pos (17UL) /!< Position of PIN17 field. /
jamesadevine	0:e1a608bb55e8	1748	#define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /!< Bit mask of PIN17 field. /
jamesadevine	0:e1a608bb55e8	1749	#define GPIO_OUTCLR_PIN17_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1750	#define GPIO_OUTCLR_PIN17_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1751	#define GPIO_OUTCLR_PIN17_Clear (1UL) /!< Set pin driver low. /
jamesadevine	0:e1a608bb55e8	1752
jamesadevine	0:e1a608bb55e8	1753	/* Bit 16 : Pin 16. */
jamesadevine	0:e1a608bb55e8	1754	#define GPIO_OUTCLR_PIN16_Pos (16UL) /!< Position of PIN16 field. /
jamesadevine	0:e1a608bb55e8	1755	#define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /!< Bit mask of PIN16 field. /
jamesadevine	0:e1a608bb55e8	1756	#define GPIO_OUTCLR_PIN16_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1757	#define GPIO_OUTCLR_PIN16_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1758	#define GPIO_OUTCLR_PIN16_Clear (1UL) /!< Set pin driver low. /
jamesadevine	0:e1a608bb55e8	1759
jamesadevine	0:e1a608bb55e8	1760	/* Bit 15 : Pin 15. */
jamesadevine	0:e1a608bb55e8	1761	#define GPIO_OUTCLR_PIN15_Pos (15UL) /!< Position of PIN15 field. /
jamesadevine	0:e1a608bb55e8	1762	#define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /!< Bit mask of PIN15 field. /
jamesadevine	0:e1a608bb55e8	1763	#define GPIO_OUTCLR_PIN15_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1764	#define GPIO_OUTCLR_PIN15_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1765	#define GPIO_OUTCLR_PIN15_Clear (1UL) /!< Set pin driver low. /
jamesadevine	0:e1a608bb55e8	1766
jamesadevine	0:e1a608bb55e8	1767	/* Bit 14 : Pin 14. */
jamesadevine	0:e1a608bb55e8	1768	#define GPIO_OUTCLR_PIN14_Pos (14UL) /!< Position of PIN14 field. /
jamesadevine	0:e1a608bb55e8	1769	#define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /!< Bit mask of PIN14 field. /
jamesadevine	0:e1a608bb55e8	1770	#define GPIO_OUTCLR_PIN14_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1771	#define GPIO_OUTCLR_PIN14_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1772	#define GPIO_OUTCLR_PIN14_Clear (1UL) /!< Set pin driver low. /
jamesadevine	0:e1a608bb55e8	1773
jamesadevine	0:e1a608bb55e8	1774	/* Bit 13 : Pin 13. */
jamesadevine	0:e1a608bb55e8	1775	#define GPIO_OUTCLR_PIN13_Pos (13UL) /!< Position of PIN13 field. /
jamesadevine	0:e1a608bb55e8	1776	#define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /!< Bit mask of PIN13 field. /
jamesadevine	0:e1a608bb55e8	1777	#define GPIO_OUTCLR_PIN13_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1778	#define GPIO_OUTCLR_PIN13_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1779	#define GPIO_OUTCLR_PIN13_Clear (1UL) /!< Set pin driver low. /
jamesadevine	0:e1a608bb55e8	1780
jamesadevine	0:e1a608bb55e8	1781	/* Bit 12 : Pin 12. */
jamesadevine	0:e1a608bb55e8	1782	#define GPIO_OUTCLR_PIN12_Pos (12UL) /!< Position of PIN12 field. /
jamesadevine	0:e1a608bb55e8	1783	#define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /!< Bit mask of PIN12 field. /
jamesadevine	0:e1a608bb55e8	1784	#define GPIO_OUTCLR_PIN12_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1785	#define GPIO_OUTCLR_PIN12_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1786	#define GPIO_OUTCLR_PIN12_Clear (1UL) /!< Set pin driver low. /
jamesadevine	0:e1a608bb55e8	1787
jamesadevine	0:e1a608bb55e8	1788	/* Bit 11 : Pin 11. */
jamesadevine	0:e1a608bb55e8	1789	#define GPIO_OUTCLR_PIN11_Pos (11UL) /!< Position of PIN11 field. /
jamesadevine	0:e1a608bb55e8	1790	#define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /!< Bit mask of PIN11 field. /
jamesadevine	0:e1a608bb55e8	1791	#define GPIO_OUTCLR_PIN11_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1792	#define GPIO_OUTCLR_PIN11_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1793	#define GPIO_OUTCLR_PIN11_Clear (1UL) /!< Set pin driver low. /
jamesadevine	0:e1a608bb55e8	1794
jamesadevine	0:e1a608bb55e8	1795	/* Bit 10 : Pin 10. */
jamesadevine	0:e1a608bb55e8	1796	#define GPIO_OUTCLR_PIN10_Pos (10UL) /!< Position of PIN10 field. /
jamesadevine	0:e1a608bb55e8	1797	#define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /!< Bit mask of PIN10 field. /
jamesadevine	0:e1a608bb55e8	1798	#define GPIO_OUTCLR_PIN10_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1799	#define GPIO_OUTCLR_PIN10_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1800	#define GPIO_OUTCLR_PIN10_Clear (1UL) /!< Set pin driver low. /
jamesadevine	0:e1a608bb55e8	1801
jamesadevine	0:e1a608bb55e8	1802	/* Bit 9 : Pin 9. */
jamesadevine	0:e1a608bb55e8	1803	#define GPIO_OUTCLR_PIN9_Pos (9UL) /!< Position of PIN9 field. /
jamesadevine	0:e1a608bb55e8	1804	#define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /!< Bit mask of PIN9 field. /
jamesadevine	0:e1a608bb55e8	1805	#define GPIO_OUTCLR_PIN9_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1806	#define GPIO_OUTCLR_PIN9_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1807	#define GPIO_OUTCLR_PIN9_Clear (1UL) /!< Set pin driver low. /
jamesadevine	0:e1a608bb55e8	1808
jamesadevine	0:e1a608bb55e8	1809	/* Bit 8 : Pin 8. */
jamesadevine	0:e1a608bb55e8	1810	#define GPIO_OUTCLR_PIN8_Pos (8UL) /!< Position of PIN8 field. /
jamesadevine	0:e1a608bb55e8	1811	#define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /!< Bit mask of PIN8 field. /
jamesadevine	0:e1a608bb55e8	1812	#define GPIO_OUTCLR_PIN8_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1813	#define GPIO_OUTCLR_PIN8_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1814	#define GPIO_OUTCLR_PIN8_Clear (1UL) /!< Set pin driver low. /
jamesadevine	0:e1a608bb55e8	1815
jamesadevine	0:e1a608bb55e8	1816	/* Bit 7 : Pin 7. */
jamesadevine	0:e1a608bb55e8	1817	#define GPIO_OUTCLR_PIN7_Pos (7UL) /!< Position of PIN7 field. /
jamesadevine	0:e1a608bb55e8	1818	#define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /!< Bit mask of PIN7 field. /
jamesadevine	0:e1a608bb55e8	1819	#define GPIO_OUTCLR_PIN7_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1820	#define GPIO_OUTCLR_PIN7_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1821	#define GPIO_OUTCLR_PIN7_Clear (1UL) /!< Set pin driver low. /
jamesadevine	0:e1a608bb55e8	1822
jamesadevine	0:e1a608bb55e8	1823	/* Bit 6 : Pin 6. */
jamesadevine	0:e1a608bb55e8	1824	#define GPIO_OUTCLR_PIN6_Pos (6UL) /!< Position of PIN6 field. /
jamesadevine	0:e1a608bb55e8	1825	#define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /!< Bit mask of PIN6 field. /
jamesadevine	0:e1a608bb55e8	1826	#define GPIO_OUTCLR_PIN6_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1827	#define GPIO_OUTCLR_PIN6_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1828	#define GPIO_OUTCLR_PIN6_Clear (1UL) /!< Set pin driver low. /
jamesadevine	0:e1a608bb55e8	1829
jamesadevine	0:e1a608bb55e8	1830	/* Bit 5 : Pin 5. */
jamesadevine	0:e1a608bb55e8	1831	#define GPIO_OUTCLR_PIN5_Pos (5UL) /!< Position of PIN5 field. /
jamesadevine	0:e1a608bb55e8	1832	#define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /!< Bit mask of PIN5 field. /
jamesadevine	0:e1a608bb55e8	1833	#define GPIO_OUTCLR_PIN5_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1834	#define GPIO_OUTCLR_PIN5_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1835	#define GPIO_OUTCLR_PIN5_Clear (1UL) /!< Set pin driver low. /
jamesadevine	0:e1a608bb55e8	1836
jamesadevine	0:e1a608bb55e8	1837	/* Bit 4 : Pin 4. */
jamesadevine	0:e1a608bb55e8	1838	#define GPIO_OUTCLR_PIN4_Pos (4UL) /!< Position of PIN4 field. /
jamesadevine	0:e1a608bb55e8	1839	#define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /!< Bit mask of PIN4 field. /
jamesadevine	0:e1a608bb55e8	1840	#define GPIO_OUTCLR_PIN4_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1841	#define GPIO_OUTCLR_PIN4_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1842	#define GPIO_OUTCLR_PIN4_Clear (1UL) /!< Set pin driver low. /
jamesadevine	0:e1a608bb55e8	1843
jamesadevine	0:e1a608bb55e8	1844	/* Bit 3 : Pin 3. */
jamesadevine	0:e1a608bb55e8	1845	#define GPIO_OUTCLR_PIN3_Pos (3UL) /!< Position of PIN3 field. /
jamesadevine	0:e1a608bb55e8	1846	#define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /!< Bit mask of PIN3 field. /
jamesadevine	0:e1a608bb55e8	1847	#define GPIO_OUTCLR_PIN3_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1848	#define GPIO_OUTCLR_PIN3_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1849	#define GPIO_OUTCLR_PIN3_Clear (1UL) /!< Set pin driver low. /
jamesadevine	0:e1a608bb55e8	1850
jamesadevine	0:e1a608bb55e8	1851	/* Bit 2 : Pin 2. */
jamesadevine	0:e1a608bb55e8	1852	#define GPIO_OUTCLR_PIN2_Pos (2UL) /!< Position of PIN2 field. /
jamesadevine	0:e1a608bb55e8	1853	#define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /!< Bit mask of PIN2 field. /
jamesadevine	0:e1a608bb55e8	1854	#define GPIO_OUTCLR_PIN2_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1855	#define GPIO_OUTCLR_PIN2_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1856	#define GPIO_OUTCLR_PIN2_Clear (1UL) /!< Set pin driver low. /
jamesadevine	0:e1a608bb55e8	1857
jamesadevine	0:e1a608bb55e8	1858	/* Bit 1 : Pin 1. */
jamesadevine	0:e1a608bb55e8	1859	#define GPIO_OUTCLR_PIN1_Pos (1UL) /!< Position of PIN1 field. /
jamesadevine	0:e1a608bb55e8	1860	#define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /!< Bit mask of PIN1 field. /
jamesadevine	0:e1a608bb55e8	1861	#define GPIO_OUTCLR_PIN1_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1862	#define GPIO_OUTCLR_PIN1_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1863	#define GPIO_OUTCLR_PIN1_Clear (1UL) /!< Set pin driver low. /
jamesadevine	0:e1a608bb55e8	1864
jamesadevine	0:e1a608bb55e8	1865	/* Bit 0 : Pin 0. */
jamesadevine	0:e1a608bb55e8	1866	#define GPIO_OUTCLR_PIN0_Pos (0UL) /!< Position of PIN0 field. /
jamesadevine	0:e1a608bb55e8	1867	#define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /!< Bit mask of PIN0 field. /
jamesadevine	0:e1a608bb55e8	1868	#define GPIO_OUTCLR_PIN0_Low (0UL) /!< Pin driver is low. /
jamesadevine	0:e1a608bb55e8	1869	#define GPIO_OUTCLR_PIN0_High (1UL) /!< Pin driver is high. /
jamesadevine	0:e1a608bb55e8	1870	#define GPIO_OUTCLR_PIN0_Clear (1UL) /!< Set pin driver low. /
jamesadevine	0:e1a608bb55e8	1871
jamesadevine	0:e1a608bb55e8	1872	/* Register: GPIO_IN */
jamesadevine	0:e1a608bb55e8	1873	/* Description: Read GPIO port. */
jamesadevine	0:e1a608bb55e8	1874
jamesadevine	0:e1a608bb55e8	1875	/* Bit 31 : Pin 31. */
jamesadevine	0:e1a608bb55e8	1876	#define GPIO_IN_PIN31_Pos (31UL) /!< Position of PIN31 field. /
jamesadevine	0:e1a608bb55e8	1877	#define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /!< Bit mask of PIN31 field. /
jamesadevine	0:e1a608bb55e8	1878	#define GPIO_IN_PIN31_Low (0UL) /!< Pin input is low. /
jamesadevine	0:e1a608bb55e8	1879	#define GPIO_IN_PIN31_High (1UL) /!< Pin input is high. /
jamesadevine	0:e1a608bb55e8	1880
jamesadevine	0:e1a608bb55e8	1881	/* Bit 30 : Pin 30. */
jamesadevine	0:e1a608bb55e8	1882	#define GPIO_IN_PIN30_Pos (30UL) /!< Position of PIN30 field. /
jamesadevine	0:e1a608bb55e8	1883	#define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /!< Bit mask of PIN30 field. /
jamesadevine	0:e1a608bb55e8	1884	#define GPIO_IN_PIN30_Low (0UL) /!< Pin input is low. /
jamesadevine	0:e1a608bb55e8	1885	#define GPIO_IN_PIN30_High (1UL) /!< Pin input is high. /
jamesadevine	0:e1a608bb55e8	1886
jamesadevine	0:e1a608bb55e8	1887	/* Bit 29 : Pin 29. */
jamesadevine	0:e1a608bb55e8	1888	#define GPIO_IN_PIN29_Pos (29UL) /!< Position of PIN29 field. /
jamesadevine	0:e1a608bb55e8	1889	#define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /!< Bit mask of PIN29 field. /
jamesadevine	0:e1a608bb55e8	1890	#define GPIO_IN_PIN29_Low (0UL) /!< Pin input is low. /
jamesadevine	0:e1a608bb55e8	1891	#define GPIO_IN_PIN29_High (1UL) /!< Pin input is high. /
jamesadevine	0:e1a608bb55e8	1892
jamesadevine	0:e1a608bb55e8	1893	/* Bit 28 : Pin 28. */
jamesadevine	0:e1a608bb55e8	1894	#define GPIO_IN_PIN28_Pos (28UL) /!< Position of PIN28 field. /
jamesadevine	0:e1a608bb55e8	1895	#define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /!< Bit mask of PIN28 field. /
jamesadevine	0:e1a608bb55e8	1896	#define GPIO_IN_PIN28_Low (0UL) /!< Pin input is low. /
jamesadevine	0:e1a608bb55e8	1897	#define GPIO_IN_PIN28_High (1UL) /!< Pin input is high. /
jamesadevine	0:e1a608bb55e8	1898
jamesadevine	0:e1a608bb55e8	1899	/* Bit 27 : Pin 27. */
jamesadevine	0:e1a608bb55e8	1900	#define GPIO_IN_PIN27_Pos (27UL) /!< Position of PIN27 field. /
jamesadevine	0:e1a608bb55e8	1901	#define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /!< Bit mask of PIN27 field. /
jamesadevine	0:e1a608bb55e8	1902	#define GPIO_IN_PIN27_Low (0UL) /!< Pin input is low. /
jamesadevine	0:e1a608bb55e8	1903	#define GPIO_IN_PIN27_High (1UL) /!< Pin input is high. /
jamesadevine	0:e1a608bb55e8	1904
jamesadevine	0:e1a608bb55e8	1905	/* Bit 26 : Pin 26. */
jamesadevine	0:e1a608bb55e8	1906	#define GPIO_IN_PIN26_Pos (26UL) /!< Position of PIN26 field. /
jamesadevine	0:e1a608bb55e8	1907	#define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /!< Bit mask of PIN26 field. /
jamesadevine	0:e1a608bb55e8	1908	#define GPIO_IN_PIN26_Low (0UL) /!< Pin input is low. /
jamesadevine	0:e1a608bb55e8	1909	#define GPIO_IN_PIN26_High (1UL) /!< Pin input is high. /
jamesadevine	0:e1a608bb55e8	1910
jamesadevine	0:e1a608bb55e8	1911	/* Bit 25 : Pin 25. */
jamesadevine	0:e1a608bb55e8	1912	#define GPIO_IN_PIN25_Pos (25UL) /!< Position of PIN25 field. /
jamesadevine	0:e1a608bb55e8	1913	#define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /!< Bit mask of PIN25 field. /
jamesadevine	0:e1a608bb55e8	1914	#define GPIO_IN_PIN25_Low (0UL) /!< Pin input is low. /
jamesadevine	0:e1a608bb55e8	1915	#define GPIO_IN_PIN25_High (1UL) /!< Pin input is high. /
jamesadevine	0:e1a608bb55e8	1916
jamesadevine	0:e1a608bb55e8	1917	/* Bit 24 : Pin 24. */
jamesadevine	0:e1a608bb55e8	1918	#define GPIO_IN_PIN24_Pos (24UL) /!< Position of PIN24 field. /
jamesadevine	0:e1a608bb55e8	1919	#define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /!< Bit mask of PIN24 field. /
jamesadevine	0:e1a608bb55e8	1920	#define GPIO_IN_PIN24_Low (0UL) /!< Pin input is low. /
jamesadevine	0:e1a608bb55e8	1921	#define GPIO_IN_PIN24_High (1UL) /!< Pin input is high. /
jamesadevine	0:e1a608bb55e8	1922
jamesadevine	0:e1a608bb55e8	1923	/* Bit 23 : Pin 23. */
jamesadevine	0:e1a608bb55e8	1924	#define GPIO_IN_PIN23_Pos (23UL) /!< Position of PIN23 field. /
jamesadevine	0:e1a608bb55e8	1925	#define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /!< Bit mask of PIN23 field. /
jamesadevine	0:e1a608bb55e8	1926	#define GPIO_IN_PIN23_Low (0UL) /!< Pin input is low. /
jamesadevine	0:e1a608bb55e8	1927	#define GPIO_IN_PIN23_High (1UL) /!< Pin input is high. /
jamesadevine	0:e1a608bb55e8	1928
jamesadevine	0:e1a608bb55e8	1929	/* Bit 22 : Pin 22. */
jamesadevine	0:e1a608bb55e8	1930	#define GPIO_IN_PIN22_Pos (22UL) /!< Position of PIN22 field. /
jamesadevine	0:e1a608bb55e8	1931	#define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /!< Bit mask of PIN22 field. /
jamesadevine	0:e1a608bb55e8	1932	#define GPIO_IN_PIN22_Low (0UL) /!< Pin input is low. /
jamesadevine	0:e1a608bb55e8	1933	#define GPIO_IN_PIN22_High (1UL) /!< Pin input is high. /
jamesadevine	0:e1a608bb55e8	1934
jamesadevine	0:e1a608bb55e8	1935	/* Bit 21 : Pin 21. */
jamesadevine	0:e1a608bb55e8	1936	#define GPIO_IN_PIN21_Pos (21UL) /!< Position of PIN21 field. /
jamesadevine	0:e1a608bb55e8	1937	#define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /!< Bit mask of PIN21 field. /
jamesadevine	0:e1a608bb55e8	1938	#define GPIO_IN_PIN21_Low (0UL) /!< Pin input is low. /
jamesadevine	0:e1a608bb55e8	1939	#define GPIO_IN_PIN21_High (1UL) /!< Pin input is high. /
jamesadevine	0:e1a608bb55e8	1940
jamesadevine	0:e1a608bb55e8	1941	/* Bit 20 : Pin 20. */
jamesadevine	0:e1a608bb55e8	1942	#define GPIO_IN_PIN20_Pos (20UL) /!< Position of PIN20 field. /
jamesadevine	0:e1a608bb55e8	1943	#define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /!< Bit mask of PIN20 field. /
jamesadevine	0:e1a608bb55e8	1944	#define GPIO_IN_PIN20_Low (0UL) /!< Pin input is low. /
jamesadevine	0:e1a608bb55e8	1945	#define GPIO_IN_PIN20_High (1UL) /!< Pin input is high. /
jamesadevine	0:e1a608bb55e8	1946
jamesadevine	0:e1a608bb55e8	1947	/* Bit 19 : Pin 19. */
jamesadevine	0:e1a608bb55e8	1948	#define GPIO_IN_PIN19_Pos (19UL) /!< Position of PIN19 field. /
jamesadevine	0:e1a608bb55e8	1949	#define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /!< Bit mask of PIN19 field. /
jamesadevine	0:e1a608bb55e8	1950	#define GPIO_IN_PIN19_Low (0UL) /!< Pin input is low. /
jamesadevine	0:e1a608bb55e8	1951	#define GPIO_IN_PIN19_High (1UL) /!< Pin input is high. /
jamesadevine	0:e1a608bb55e8	1952
jamesadevine	0:e1a608bb55e8	1953	/* Bit 18 : Pin 18. */
jamesadevine	0:e1a608bb55e8	1954	#define GPIO_IN_PIN18_Pos (18UL) /!< Position of PIN18 field. /
jamesadevine	0:e1a608bb55e8	1955	#define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /!< Bit mask of PIN18 field. /
jamesadevine	0:e1a608bb55e8	1956	#define GPIO_IN_PIN18_Low (0UL) /!< Pin input is low. /
jamesadevine	0:e1a608bb55e8	1957	#define GPIO_IN_PIN18_High (1UL) /!< Pin input is high. /
jamesadevine	0:e1a608bb55e8	1958
jamesadevine	0:e1a608bb55e8	1959	/* Bit 17 : Pin 17. */
jamesadevine	0:e1a608bb55e8	1960	#define GPIO_IN_PIN17_Pos (17UL) /!< Position of PIN17 field. /
jamesadevine	0:e1a608bb55e8	1961	#define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /!< Bit mask of PIN17 field. /
jamesadevine	0:e1a608bb55e8	1962	#define GPIO_IN_PIN17_Low (0UL) /!< Pin input is low. /
jamesadevine	0:e1a608bb55e8	1963	#define GPIO_IN_PIN17_High (1UL) /!< Pin input is high. /
jamesadevine	0:e1a608bb55e8	1964
jamesadevine	0:e1a608bb55e8	1965	/* Bit 16 : Pin 16. */
jamesadevine	0:e1a608bb55e8	1966	#define GPIO_IN_PIN16_Pos (16UL) /!< Position of PIN16 field. /
jamesadevine	0:e1a608bb55e8	1967	#define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /!< Bit mask of PIN16 field. /
jamesadevine	0:e1a608bb55e8	1968	#define GPIO_IN_PIN16_Low (0UL) /!< Pin input is low. /
jamesadevine	0:e1a608bb55e8	1969	#define GPIO_IN_PIN16_High (1UL) /!< Pin input is high. /
jamesadevine	0:e1a608bb55e8	1970
jamesadevine	0:e1a608bb55e8	1971	/* Bit 15 : Pin 15. */
jamesadevine	0:e1a608bb55e8	1972	#define GPIO_IN_PIN15_Pos (15UL) /!< Position of PIN15 field. /
jamesadevine	0:e1a608bb55e8	1973	#define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /!< Bit mask of PIN15 field. /
jamesadevine	0:e1a608bb55e8	1974	#define GPIO_IN_PIN15_Low (0UL) /!< Pin input is low. /
jamesadevine	0:e1a608bb55e8	1975	#define GPIO_IN_PIN15_High (1UL) /!< Pin input is high. /
jamesadevine	0:e1a608bb55e8	1976
jamesadevine	0:e1a608bb55e8	1977	/* Bit 14 : Pin 14. */
jamesadevine	0:e1a608bb55e8	1978	#define GPIO_IN_PIN14_Pos (14UL) /!< Position of PIN14 field. /
jamesadevine	0:e1a608bb55e8	1979	#define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /!< Bit mask of PIN14 field. /
jamesadevine	0:e1a608bb55e8	1980	#define GPIO_IN_PIN14_Low (0UL) /!< Pin input is low. /
jamesadevine	0:e1a608bb55e8	1981	#define GPIO_IN_PIN14_High (1UL) /!< Pin input is high. /
jamesadevine	0:e1a608bb55e8	1982
jamesadevine	0:e1a608bb55e8	1983	/* Bit 13 : Pin 13. */
jamesadevine	0:e1a608bb55e8	1984	#define GPIO_IN_PIN13_Pos (13UL) /!< Position of PIN13 field. /
jamesadevine	0:e1a608bb55e8	1985	#define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /!< Bit mask of PIN13 field. /
jamesadevine	0:e1a608bb55e8	1986	#define GPIO_IN_PIN13_Low (0UL) /!< Pin input is low. /
jamesadevine	0:e1a608bb55e8	1987	#define GPIO_IN_PIN13_High (1UL) /!< Pin input is high. /
jamesadevine	0:e1a608bb55e8	1988
jamesadevine	0:e1a608bb55e8	1989	/* Bit 12 : Pin 12. */
jamesadevine	0:e1a608bb55e8	1990	#define GPIO_IN_PIN12_Pos (12UL) /!< Position of PIN12 field. /
jamesadevine	0:e1a608bb55e8	1991	#define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /!< Bit mask of PIN12 field. /
jamesadevine	0:e1a608bb55e8	1992	#define GPIO_IN_PIN12_Low (0UL) /!< Pin input is low. /
jamesadevine	0:e1a608bb55e8	1993	#define GPIO_IN_PIN12_High (1UL) /!< Pin input is high. /
jamesadevine	0:e1a608bb55e8	1994
jamesadevine	0:e1a608bb55e8	1995	/* Bit 11 : Pin 11. */
jamesadevine	0:e1a608bb55e8	1996	#define GPIO_IN_PIN11_Pos (11UL) /!< Position of PIN11 field. /
jamesadevine	0:e1a608bb55e8	1997	#define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /!< Bit mask of PIN11 field. /
jamesadevine	0:e1a608bb55e8	1998	#define GPIO_IN_PIN11_Low (0UL) /!< Pin input is low. /
jamesadevine	0:e1a608bb55e8	1999	#define GPIO_IN_PIN11_High (1UL) /!< Pin input is high. /
jamesadevine	0:e1a608bb55e8	2000
jamesadevine	0:e1a608bb55e8	2001	/* Bit 10 : Pin 10. */
jamesadevine	0:e1a608bb55e8	2002	#define GPIO_IN_PIN10_Pos (10UL) /!< Position of PIN10 field. /
jamesadevine	0:e1a608bb55e8	2003	#define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /!< Bit mask of PIN10 field. /
jamesadevine	0:e1a608bb55e8	2004	#define GPIO_IN_PIN10_Low (0UL) /!< Pin input is low. /
jamesadevine	0:e1a608bb55e8	2005	#define GPIO_IN_PIN10_High (1UL) /!< Pin input is high. /
jamesadevine	0:e1a608bb55e8	2006
jamesadevine	0:e1a608bb55e8	2007	/* Bit 9 : Pin 9. */
jamesadevine	0:e1a608bb55e8	2008	#define GPIO_IN_PIN9_Pos (9UL) /!< Position of PIN9 field. /
jamesadevine	0:e1a608bb55e8	2009	#define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /!< Bit mask of PIN9 field. /
jamesadevine	0:e1a608bb55e8	2010	#define GPIO_IN_PIN9_Low (0UL) /!< Pin input is low. /
jamesadevine	0:e1a608bb55e8	2011	#define GPIO_IN_PIN9_High (1UL) /!< Pin input is high. /
jamesadevine	0:e1a608bb55e8	2012
jamesadevine	0:e1a608bb55e8	2013	/* Bit 8 : Pin 8. */
jamesadevine	0:e1a608bb55e8	2014	#define GPIO_IN_PIN8_Pos (8UL) /!< Position of PIN8 field. /
jamesadevine	0:e1a608bb55e8	2015	#define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /!< Bit mask of PIN8 field. /
jamesadevine	0:e1a608bb55e8	2016	#define GPIO_IN_PIN8_Low (0UL) /!< Pin input is low. /
jamesadevine	0:e1a608bb55e8	2017	#define GPIO_IN_PIN8_High (1UL) /!< Pin input is high. /
jamesadevine	0:e1a608bb55e8	2018
jamesadevine	0:e1a608bb55e8	2019	/* Bit 7 : Pin 7. */
jamesadevine	0:e1a608bb55e8	2020	#define GPIO_IN_PIN7_Pos (7UL) /!< Position of PIN7 field. /
jamesadevine	0:e1a608bb55e8	2021	#define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /!< Bit mask of PIN7 field. /
jamesadevine	0:e1a608bb55e8	2022	#define GPIO_IN_PIN7_Low (0UL) /!< Pin input is low. /
jamesadevine	0:e1a608bb55e8	2023	#define GPIO_IN_PIN7_High (1UL) /!< Pin input is high. /
jamesadevine	0:e1a608bb55e8	2024
jamesadevine	0:e1a608bb55e8	2025	/* Bit 6 : Pin 6. */
jamesadevine	0:e1a608bb55e8	2026	#define GPIO_IN_PIN6_Pos (6UL) /!< Position of PIN6 field. /
jamesadevine	0:e1a608bb55e8	2027	#define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /!< Bit mask of PIN6 field. /
jamesadevine	0:e1a608bb55e8	2028	#define GPIO_IN_PIN6_Low (0UL) /!< Pin input is low. /
jamesadevine	0:e1a608bb55e8	2029	#define GPIO_IN_PIN6_High (1UL) /!< Pin input is high. /
jamesadevine	0:e1a608bb55e8	2030
jamesadevine	0:e1a608bb55e8	2031	/* Bit 5 : Pin 5. */
jamesadevine	0:e1a608bb55e8	2032	#define GPIO_IN_PIN5_Pos (5UL) /!< Position of PIN5 field. /
jamesadevine	0:e1a608bb55e8	2033	#define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /!< Bit mask of PIN5 field. /
jamesadevine	0:e1a608bb55e8	2034	#define GPIO_IN_PIN5_Low (0UL) /!< Pin input is low. /
jamesadevine	0:e1a608bb55e8	2035	#define GPIO_IN_PIN5_High (1UL) /!< Pin input is high. /
jamesadevine	0:e1a608bb55e8	2036
jamesadevine	0:e1a608bb55e8	2037	/* Bit 4 : Pin 4. */
jamesadevine	0:e1a608bb55e8	2038	#define GPIO_IN_PIN4_Pos (4UL) /!< Position of PIN4 field. /
jamesadevine	0:e1a608bb55e8	2039	#define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /!< Bit mask of PIN4 field. /
jamesadevine	0:e1a608bb55e8	2040	#define GPIO_IN_PIN4_Low (0UL) /!< Pin input is low. /
jamesadevine	0:e1a608bb55e8	2041	#define GPIO_IN_PIN4_High (1UL) /!< Pin input is high. /
jamesadevine	0:e1a608bb55e8	2042
jamesadevine	0:e1a608bb55e8	2043	/* Bit 3 : Pin 3. */
jamesadevine	0:e1a608bb55e8	2044	#define GPIO_IN_PIN3_Pos (3UL) /!< Position of PIN3 field. /
jamesadevine	0:e1a608bb55e8	2045	#define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /!< Bit mask of PIN3 field. /
jamesadevine	0:e1a608bb55e8	2046	#define GPIO_IN_PIN3_Low (0UL) /!< Pin input is low. /
jamesadevine	0:e1a608bb55e8	2047	#define GPIO_IN_PIN3_High (1UL) /!< Pin input is high. /
jamesadevine	0:e1a608bb55e8	2048
jamesadevine	0:e1a608bb55e8	2049	/* Bit 2 : Pin 2. */
jamesadevine	0:e1a608bb55e8	2050	#define GPIO_IN_PIN2_Pos (2UL) /!< Position of PIN2 field. /
jamesadevine	0:e1a608bb55e8	2051	#define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /!< Bit mask of PIN2 field. /
jamesadevine	0:e1a608bb55e8	2052	#define GPIO_IN_PIN2_Low (0UL) /!< Pin input is low. /
jamesadevine	0:e1a608bb55e8	2053	#define GPIO_IN_PIN2_High (1UL) /!< Pin input is high. /
jamesadevine	0:e1a608bb55e8	2054
jamesadevine	0:e1a608bb55e8	2055	/* Bit 1 : Pin 1. */
jamesadevine	0:e1a608bb55e8	2056	#define GPIO_IN_PIN1_Pos (1UL) /!< Position of PIN1 field. /
jamesadevine	0:e1a608bb55e8	2057	#define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /!< Bit mask of PIN1 field. /
jamesadevine	0:e1a608bb55e8	2058	#define GPIO_IN_PIN1_Low (0UL) /!< Pin input is low. /
jamesadevine	0:e1a608bb55e8	2059	#define GPIO_IN_PIN1_High (1UL) /!< Pin input is high. /
jamesadevine	0:e1a608bb55e8	2060
jamesadevine	0:e1a608bb55e8	2061	/* Bit 0 : Pin 0. */
jamesadevine	0:e1a608bb55e8	2062	#define GPIO_IN_PIN0_Pos (0UL) /!< Position of PIN0 field. /
jamesadevine	0:e1a608bb55e8	2063	#define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /!< Bit mask of PIN0 field. /
jamesadevine	0:e1a608bb55e8	2064	#define GPIO_IN_PIN0_Low (0UL) /!< Pin input is low. /
jamesadevine	0:e1a608bb55e8	2065	#define GPIO_IN_PIN0_High (1UL) /!< Pin input is high. /
jamesadevine	0:e1a608bb55e8	2066
jamesadevine	0:e1a608bb55e8	2067	/* Register: GPIO_DIR */
jamesadevine	0:e1a608bb55e8	2068	/* Description: Direction of GPIO pins. */
jamesadevine	0:e1a608bb55e8	2069
jamesadevine	0:e1a608bb55e8	2070	/* Bit 31 : Pin 31. */
jamesadevine	0:e1a608bb55e8	2071	#define GPIO_DIR_PIN31_Pos (31UL) /!< Position of PIN31 field. /
jamesadevine	0:e1a608bb55e8	2072	#define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /!< Bit mask of PIN31 field. /
jamesadevine	0:e1a608bb55e8	2073	#define GPIO_DIR_PIN31_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2074	#define GPIO_DIR_PIN31_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2075
jamesadevine	0:e1a608bb55e8	2076	/* Bit 30 : Pin 30. */
jamesadevine	0:e1a608bb55e8	2077	#define GPIO_DIR_PIN30_Pos (30UL) /!< Position of PIN30 field. /
jamesadevine	0:e1a608bb55e8	2078	#define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /!< Bit mask of PIN30 field. /
jamesadevine	0:e1a608bb55e8	2079	#define GPIO_DIR_PIN30_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2080	#define GPIO_DIR_PIN30_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2081
jamesadevine	0:e1a608bb55e8	2082	/* Bit 29 : Pin 29. */
jamesadevine	0:e1a608bb55e8	2083	#define GPIO_DIR_PIN29_Pos (29UL) /!< Position of PIN29 field. /
jamesadevine	0:e1a608bb55e8	2084	#define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /!< Bit mask of PIN29 field. /
jamesadevine	0:e1a608bb55e8	2085	#define GPIO_DIR_PIN29_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2086	#define GPIO_DIR_PIN29_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2087
jamesadevine	0:e1a608bb55e8	2088	/* Bit 28 : Pin 28. */
jamesadevine	0:e1a608bb55e8	2089	#define GPIO_DIR_PIN28_Pos (28UL) /!< Position of PIN28 field. /
jamesadevine	0:e1a608bb55e8	2090	#define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /!< Bit mask of PIN28 field. /
jamesadevine	0:e1a608bb55e8	2091	#define GPIO_DIR_PIN28_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2092	#define GPIO_DIR_PIN28_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2093
jamesadevine	0:e1a608bb55e8	2094	/* Bit 27 : Pin 27. */
jamesadevine	0:e1a608bb55e8	2095	#define GPIO_DIR_PIN27_Pos (27UL) /!< Position of PIN27 field. /
jamesadevine	0:e1a608bb55e8	2096	#define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /!< Bit mask of PIN27 field. /
jamesadevine	0:e1a608bb55e8	2097	#define GPIO_DIR_PIN27_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2098	#define GPIO_DIR_PIN27_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2099
jamesadevine	0:e1a608bb55e8	2100	/* Bit 26 : Pin 26. */
jamesadevine	0:e1a608bb55e8	2101	#define GPIO_DIR_PIN26_Pos (26UL) /!< Position of PIN26 field. /
jamesadevine	0:e1a608bb55e8	2102	#define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /!< Bit mask of PIN26 field. /
jamesadevine	0:e1a608bb55e8	2103	#define GPIO_DIR_PIN26_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2104	#define GPIO_DIR_PIN26_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2105
jamesadevine	0:e1a608bb55e8	2106	/* Bit 25 : Pin 25. */
jamesadevine	0:e1a608bb55e8	2107	#define GPIO_DIR_PIN25_Pos (25UL) /!< Position of PIN25 field. /
jamesadevine	0:e1a608bb55e8	2108	#define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /!< Bit mask of PIN25 field. /
jamesadevine	0:e1a608bb55e8	2109	#define GPIO_DIR_PIN25_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2110	#define GPIO_DIR_PIN25_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2111
jamesadevine	0:e1a608bb55e8	2112	/* Bit 24 : Pin 24. */
jamesadevine	0:e1a608bb55e8	2113	#define GPIO_DIR_PIN24_Pos (24UL) /!< Position of PIN24 field. /
jamesadevine	0:e1a608bb55e8	2114	#define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /!< Bit mask of PIN24 field. /
jamesadevine	0:e1a608bb55e8	2115	#define GPIO_DIR_PIN24_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2116	#define GPIO_DIR_PIN24_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2117
jamesadevine	0:e1a608bb55e8	2118	/* Bit 23 : Pin 23. */
jamesadevine	0:e1a608bb55e8	2119	#define GPIO_DIR_PIN23_Pos (23UL) /!< Position of PIN23 field. /
jamesadevine	0:e1a608bb55e8	2120	#define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /!< Bit mask of PIN23 field. /
jamesadevine	0:e1a608bb55e8	2121	#define GPIO_DIR_PIN23_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2122	#define GPIO_DIR_PIN23_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2123
jamesadevine	0:e1a608bb55e8	2124	/* Bit 22 : Pin 22. */
jamesadevine	0:e1a608bb55e8	2125	#define GPIO_DIR_PIN22_Pos (22UL) /!< Position of PIN22 field. /
jamesadevine	0:e1a608bb55e8	2126	#define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /!< Bit mask of PIN22 field. /
jamesadevine	0:e1a608bb55e8	2127	#define GPIO_DIR_PIN22_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2128	#define GPIO_DIR_PIN22_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2129
jamesadevine	0:e1a608bb55e8	2130	/* Bit 21 : Pin 21. */
jamesadevine	0:e1a608bb55e8	2131	#define GPIO_DIR_PIN21_Pos (21UL) /!< Position of PIN21 field. /
jamesadevine	0:e1a608bb55e8	2132	#define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /!< Bit mask of PIN21 field. /
jamesadevine	0:e1a608bb55e8	2133	#define GPIO_DIR_PIN21_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2134	#define GPIO_DIR_PIN21_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2135
jamesadevine	0:e1a608bb55e8	2136	/* Bit 20 : Pin 20. */
jamesadevine	0:e1a608bb55e8	2137	#define GPIO_DIR_PIN20_Pos (20UL) /!< Position of PIN20 field. /
jamesadevine	0:e1a608bb55e8	2138	#define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /!< Bit mask of PIN20 field. /
jamesadevine	0:e1a608bb55e8	2139	#define GPIO_DIR_PIN20_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2140	#define GPIO_DIR_PIN20_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2141
jamesadevine	0:e1a608bb55e8	2142	/* Bit 19 : Pin 19. */
jamesadevine	0:e1a608bb55e8	2143	#define GPIO_DIR_PIN19_Pos (19UL) /!< Position of PIN19 field. /
jamesadevine	0:e1a608bb55e8	2144	#define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /!< Bit mask of PIN19 field. /
jamesadevine	0:e1a608bb55e8	2145	#define GPIO_DIR_PIN19_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2146	#define GPIO_DIR_PIN19_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2147
jamesadevine	0:e1a608bb55e8	2148	/* Bit 18 : Pin 18. */
jamesadevine	0:e1a608bb55e8	2149	#define GPIO_DIR_PIN18_Pos (18UL) /!< Position of PIN18 field. /
jamesadevine	0:e1a608bb55e8	2150	#define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /!< Bit mask of PIN18 field. /
jamesadevine	0:e1a608bb55e8	2151	#define GPIO_DIR_PIN18_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2152	#define GPIO_DIR_PIN18_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2153
jamesadevine	0:e1a608bb55e8	2154	/* Bit 17 : Pin 17. */
jamesadevine	0:e1a608bb55e8	2155	#define GPIO_DIR_PIN17_Pos (17UL) /!< Position of PIN17 field. /
jamesadevine	0:e1a608bb55e8	2156	#define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /!< Bit mask of PIN17 field. /
jamesadevine	0:e1a608bb55e8	2157	#define GPIO_DIR_PIN17_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2158	#define GPIO_DIR_PIN17_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2159
jamesadevine	0:e1a608bb55e8	2160	/* Bit 16 : Pin 16. */
jamesadevine	0:e1a608bb55e8	2161	#define GPIO_DIR_PIN16_Pos (16UL) /!< Position of PIN16 field. /
jamesadevine	0:e1a608bb55e8	2162	#define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /!< Bit mask of PIN16 field. /
jamesadevine	0:e1a608bb55e8	2163	#define GPIO_DIR_PIN16_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2164	#define GPIO_DIR_PIN16_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2165
jamesadevine	0:e1a608bb55e8	2166	/* Bit 15 : Pin 15. */
jamesadevine	0:e1a608bb55e8	2167	#define GPIO_DIR_PIN15_Pos (15UL) /!< Position of PIN15 field. /
jamesadevine	0:e1a608bb55e8	2168	#define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /!< Bit mask of PIN15 field. /
jamesadevine	0:e1a608bb55e8	2169	#define GPIO_DIR_PIN15_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2170	#define GPIO_DIR_PIN15_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2171
jamesadevine	0:e1a608bb55e8	2172	/* Bit 14 : Pin 14. */
jamesadevine	0:e1a608bb55e8	2173	#define GPIO_DIR_PIN14_Pos (14UL) /!< Position of PIN14 field. /
jamesadevine	0:e1a608bb55e8	2174	#define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /!< Bit mask of PIN14 field. /
jamesadevine	0:e1a608bb55e8	2175	#define GPIO_DIR_PIN14_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2176	#define GPIO_DIR_PIN14_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2177
jamesadevine	0:e1a608bb55e8	2178	/* Bit 13 : Pin 13. */
jamesadevine	0:e1a608bb55e8	2179	#define GPIO_DIR_PIN13_Pos (13UL) /!< Position of PIN13 field. /
jamesadevine	0:e1a608bb55e8	2180	#define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /!< Bit mask of PIN13 field. /
jamesadevine	0:e1a608bb55e8	2181	#define GPIO_DIR_PIN13_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2182	#define GPIO_DIR_PIN13_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2183
jamesadevine	0:e1a608bb55e8	2184	/* Bit 12 : Pin 12. */
jamesadevine	0:e1a608bb55e8	2185	#define GPIO_DIR_PIN12_Pos (12UL) /!< Position of PIN12 field. /
jamesadevine	0:e1a608bb55e8	2186	#define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /!< Bit mask of PIN12 field. /
jamesadevine	0:e1a608bb55e8	2187	#define GPIO_DIR_PIN12_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2188	#define GPIO_DIR_PIN12_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2189
jamesadevine	0:e1a608bb55e8	2190	/* Bit 11 : Pin 11. */
jamesadevine	0:e1a608bb55e8	2191	#define GPIO_DIR_PIN11_Pos (11UL) /!< Position of PIN11 field. /
jamesadevine	0:e1a608bb55e8	2192	#define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /!< Bit mask of PIN11 field. /
jamesadevine	0:e1a608bb55e8	2193	#define GPIO_DIR_PIN11_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2194	#define GPIO_DIR_PIN11_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2195
jamesadevine	0:e1a608bb55e8	2196	/* Bit 10 : Pin 10. */
jamesadevine	0:e1a608bb55e8	2197	#define GPIO_DIR_PIN10_Pos (10UL) /!< Position of PIN10 field. /
jamesadevine	0:e1a608bb55e8	2198	#define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /!< Bit mask of PIN10 field. /
jamesadevine	0:e1a608bb55e8	2199	#define GPIO_DIR_PIN10_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2200	#define GPIO_DIR_PIN10_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2201
jamesadevine	0:e1a608bb55e8	2202	/* Bit 9 : Pin 9. */
jamesadevine	0:e1a608bb55e8	2203	#define GPIO_DIR_PIN9_Pos (9UL) /!< Position of PIN9 field. /
jamesadevine	0:e1a608bb55e8	2204	#define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /!< Bit mask of PIN9 field. /
jamesadevine	0:e1a608bb55e8	2205	#define GPIO_DIR_PIN9_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2206	#define GPIO_DIR_PIN9_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2207
jamesadevine	0:e1a608bb55e8	2208	/* Bit 8 : Pin 8. */
jamesadevine	0:e1a608bb55e8	2209	#define GPIO_DIR_PIN8_Pos (8UL) /!< Position of PIN8 field. /
jamesadevine	0:e1a608bb55e8	2210	#define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /!< Bit mask of PIN8 field. /
jamesadevine	0:e1a608bb55e8	2211	#define GPIO_DIR_PIN8_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2212	#define GPIO_DIR_PIN8_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2213
jamesadevine	0:e1a608bb55e8	2214	/* Bit 7 : Pin 7. */
jamesadevine	0:e1a608bb55e8	2215	#define GPIO_DIR_PIN7_Pos (7UL) /!< Position of PIN7 field. /
jamesadevine	0:e1a608bb55e8	2216	#define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /!< Bit mask of PIN7 field. /
jamesadevine	0:e1a608bb55e8	2217	#define GPIO_DIR_PIN7_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2218	#define GPIO_DIR_PIN7_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2219
jamesadevine	0:e1a608bb55e8	2220	/* Bit 6 : Pin 6. */
jamesadevine	0:e1a608bb55e8	2221	#define GPIO_DIR_PIN6_Pos (6UL) /!< Position of PIN6 field. /
jamesadevine	0:e1a608bb55e8	2222	#define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /!< Bit mask of PIN6 field. /
jamesadevine	0:e1a608bb55e8	2223	#define GPIO_DIR_PIN6_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2224	#define GPIO_DIR_PIN6_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2225
jamesadevine	0:e1a608bb55e8	2226	/* Bit 5 : Pin 5. */
jamesadevine	0:e1a608bb55e8	2227	#define GPIO_DIR_PIN5_Pos (5UL) /!< Position of PIN5 field. /
jamesadevine	0:e1a608bb55e8	2228	#define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /!< Bit mask of PIN5 field. /
jamesadevine	0:e1a608bb55e8	2229	#define GPIO_DIR_PIN5_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2230	#define GPIO_DIR_PIN5_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2231
jamesadevine	0:e1a608bb55e8	2232	/* Bit 4 : Pin 4. */
jamesadevine	0:e1a608bb55e8	2233	#define GPIO_DIR_PIN4_Pos (4UL) /!< Position of PIN4 field. /
jamesadevine	0:e1a608bb55e8	2234	#define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /!< Bit mask of PIN4 field. /
jamesadevine	0:e1a608bb55e8	2235	#define GPIO_DIR_PIN4_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2236	#define GPIO_DIR_PIN4_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2237
jamesadevine	0:e1a608bb55e8	2238	/* Bit 3 : Pin 3. */
jamesadevine	0:e1a608bb55e8	2239	#define GPIO_DIR_PIN3_Pos (3UL) /!< Position of PIN3 field. /
jamesadevine	0:e1a608bb55e8	2240	#define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /!< Bit mask of PIN3 field. /
jamesadevine	0:e1a608bb55e8	2241	#define GPIO_DIR_PIN3_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2242	#define GPIO_DIR_PIN3_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2243
jamesadevine	0:e1a608bb55e8	2244	/* Bit 2 : Pin 2. */
jamesadevine	0:e1a608bb55e8	2245	#define GPIO_DIR_PIN2_Pos (2UL) /!< Position of PIN2 field. /
jamesadevine	0:e1a608bb55e8	2246	#define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /!< Bit mask of PIN2 field. /
jamesadevine	0:e1a608bb55e8	2247	#define GPIO_DIR_PIN2_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2248	#define GPIO_DIR_PIN2_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2249
jamesadevine	0:e1a608bb55e8	2250	/* Bit 1 : Pin 1. */
jamesadevine	0:e1a608bb55e8	2251	#define GPIO_DIR_PIN1_Pos (1UL) /!< Position of PIN1 field. /
jamesadevine	0:e1a608bb55e8	2252	#define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /!< Bit mask of PIN1 field. /
jamesadevine	0:e1a608bb55e8	2253	#define GPIO_DIR_PIN1_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2254	#define GPIO_DIR_PIN1_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2255
jamesadevine	0:e1a608bb55e8	2256	/* Bit 0 : Pin 0. */
jamesadevine	0:e1a608bb55e8	2257	#define GPIO_DIR_PIN0_Pos (0UL) /!< Position of PIN0 field. /
jamesadevine	0:e1a608bb55e8	2258	#define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /!< Bit mask of PIN0 field. /
jamesadevine	0:e1a608bb55e8	2259	#define GPIO_DIR_PIN0_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2260	#define GPIO_DIR_PIN0_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2261
jamesadevine	0:e1a608bb55e8	2262	/* Register: GPIO_DIRSET */
jamesadevine	0:e1a608bb55e8	2263	/* Description: DIR set register. */
jamesadevine	0:e1a608bb55e8	2264
jamesadevine	0:e1a608bb55e8	2265	/* Bit 31 : Set as output pin 31. */
jamesadevine	0:e1a608bb55e8	2266	#define GPIO_DIRSET_PIN31_Pos (31UL) /!< Position of PIN31 field. /
jamesadevine	0:e1a608bb55e8	2267	#define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /!< Bit mask of PIN31 field. /
jamesadevine	0:e1a608bb55e8	2268	#define GPIO_DIRSET_PIN31_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2269	#define GPIO_DIRSET_PIN31_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2270	#define GPIO_DIRSET_PIN31_Set (1UL) /!< Set pin as output. /
jamesadevine	0:e1a608bb55e8	2271
jamesadevine	0:e1a608bb55e8	2272	/* Bit 30 : Set as output pin 30. */
jamesadevine	0:e1a608bb55e8	2273	#define GPIO_DIRSET_PIN30_Pos (30UL) /!< Position of PIN30 field. /
jamesadevine	0:e1a608bb55e8	2274	#define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /!< Bit mask of PIN30 field. /
jamesadevine	0:e1a608bb55e8	2275	#define GPIO_DIRSET_PIN30_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2276	#define GPIO_DIRSET_PIN30_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2277	#define GPIO_DIRSET_PIN30_Set (1UL) /!< Set pin as output. /
jamesadevine	0:e1a608bb55e8	2278
jamesadevine	0:e1a608bb55e8	2279	/* Bit 29 : Set as output pin 29. */
jamesadevine	0:e1a608bb55e8	2280	#define GPIO_DIRSET_PIN29_Pos (29UL) /!< Position of PIN29 field. /
jamesadevine	0:e1a608bb55e8	2281	#define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /!< Bit mask of PIN29 field. /
jamesadevine	0:e1a608bb55e8	2282	#define GPIO_DIRSET_PIN29_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2283	#define GPIO_DIRSET_PIN29_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2284	#define GPIO_DIRSET_PIN29_Set (1UL) /!< Set pin as output. /
jamesadevine	0:e1a608bb55e8	2285
jamesadevine	0:e1a608bb55e8	2286	/* Bit 28 : Set as output pin 28. */
jamesadevine	0:e1a608bb55e8	2287	#define GPIO_DIRSET_PIN28_Pos (28UL) /!< Position of PIN28 field. /
jamesadevine	0:e1a608bb55e8	2288	#define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /!< Bit mask of PIN28 field. /
jamesadevine	0:e1a608bb55e8	2289	#define GPIO_DIRSET_PIN28_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2290	#define GPIO_DIRSET_PIN28_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2291	#define GPIO_DIRSET_PIN28_Set (1UL) /!< Set pin as output. /
jamesadevine	0:e1a608bb55e8	2292
jamesadevine	0:e1a608bb55e8	2293	/* Bit 27 : Set as output pin 27. */
jamesadevine	0:e1a608bb55e8	2294	#define GPIO_DIRSET_PIN27_Pos (27UL) /!< Position of PIN27 field. /
jamesadevine	0:e1a608bb55e8	2295	#define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /!< Bit mask of PIN27 field. /
jamesadevine	0:e1a608bb55e8	2296	#define GPIO_DIRSET_PIN27_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2297	#define GPIO_DIRSET_PIN27_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2298	#define GPIO_DIRSET_PIN27_Set (1UL) /!< Set pin as output. /
jamesadevine	0:e1a608bb55e8	2299
jamesadevine	0:e1a608bb55e8	2300	/* Bit 26 : Set as output pin 26. */
jamesadevine	0:e1a608bb55e8	2301	#define GPIO_DIRSET_PIN26_Pos (26UL) /!< Position of PIN26 field. /
jamesadevine	0:e1a608bb55e8	2302	#define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /!< Bit mask of PIN26 field. /
jamesadevine	0:e1a608bb55e8	2303	#define GPIO_DIRSET_PIN26_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2304	#define GPIO_DIRSET_PIN26_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2305	#define GPIO_DIRSET_PIN26_Set (1UL) /!< Set pin as output. /
jamesadevine	0:e1a608bb55e8	2306
jamesadevine	0:e1a608bb55e8	2307	/* Bit 25 : Set as output pin 25. */
jamesadevine	0:e1a608bb55e8	2308	#define GPIO_DIRSET_PIN25_Pos (25UL) /!< Position of PIN25 field. /
jamesadevine	0:e1a608bb55e8	2309	#define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /!< Bit mask of PIN25 field. /
jamesadevine	0:e1a608bb55e8	2310	#define GPIO_DIRSET_PIN25_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2311	#define GPIO_DIRSET_PIN25_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2312	#define GPIO_DIRSET_PIN25_Set (1UL) /!< Set pin as output. /
jamesadevine	0:e1a608bb55e8	2313
jamesadevine	0:e1a608bb55e8	2314	/* Bit 24 : Set as output pin 24. */
jamesadevine	0:e1a608bb55e8	2315	#define GPIO_DIRSET_PIN24_Pos (24UL) /!< Position of PIN24 field. /
jamesadevine	0:e1a608bb55e8	2316	#define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /!< Bit mask of PIN24 field. /
jamesadevine	0:e1a608bb55e8	2317	#define GPIO_DIRSET_PIN24_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2318	#define GPIO_DIRSET_PIN24_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2319	#define GPIO_DIRSET_PIN24_Set (1UL) /!< Set pin as output. /
jamesadevine	0:e1a608bb55e8	2320
jamesadevine	0:e1a608bb55e8	2321	/* Bit 23 : Set as output pin 23. */
jamesadevine	0:e1a608bb55e8	2322	#define GPIO_DIRSET_PIN23_Pos (23UL) /!< Position of PIN23 field. /
jamesadevine	0:e1a608bb55e8	2323	#define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /!< Bit mask of PIN23 field. /
jamesadevine	0:e1a608bb55e8	2324	#define GPIO_DIRSET_PIN23_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2325	#define GPIO_DIRSET_PIN23_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2326	#define GPIO_DIRSET_PIN23_Set (1UL) /!< Set pin as output. /
jamesadevine	0:e1a608bb55e8	2327
jamesadevine	0:e1a608bb55e8	2328	/* Bit 22 : Set as output pin 22. */
jamesadevine	0:e1a608bb55e8	2329	#define GPIO_DIRSET_PIN22_Pos (22UL) /!< Position of PIN22 field. /
jamesadevine	0:e1a608bb55e8	2330	#define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /!< Bit mask of PIN22 field. /
jamesadevine	0:e1a608bb55e8	2331	#define GPIO_DIRSET_PIN22_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2332	#define GPIO_DIRSET_PIN22_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2333	#define GPIO_DIRSET_PIN22_Set (1UL) /!< Set pin as output. /
jamesadevine	0:e1a608bb55e8	2334
jamesadevine	0:e1a608bb55e8	2335	/* Bit 21 : Set as output pin 21. */
jamesadevine	0:e1a608bb55e8	2336	#define GPIO_DIRSET_PIN21_Pos (21UL) /!< Position of PIN21 field. /
jamesadevine	0:e1a608bb55e8	2337	#define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /!< Bit mask of PIN21 field. /
jamesadevine	0:e1a608bb55e8	2338	#define GPIO_DIRSET_PIN21_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2339	#define GPIO_DIRSET_PIN21_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2340	#define GPIO_DIRSET_PIN21_Set (1UL) /!< Set pin as output. /
jamesadevine	0:e1a608bb55e8	2341
jamesadevine	0:e1a608bb55e8	2342	/* Bit 20 : Set as output pin 20. */
jamesadevine	0:e1a608bb55e8	2343	#define GPIO_DIRSET_PIN20_Pos (20UL) /!< Position of PIN20 field. /
jamesadevine	0:e1a608bb55e8	2344	#define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /!< Bit mask of PIN20 field. /
jamesadevine	0:e1a608bb55e8	2345	#define GPIO_DIRSET_PIN20_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2346	#define GPIO_DIRSET_PIN20_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2347	#define GPIO_DIRSET_PIN20_Set (1UL) /!< Set pin as output. /
jamesadevine	0:e1a608bb55e8	2348
jamesadevine	0:e1a608bb55e8	2349	/* Bit 19 : Set as output pin 19. */
jamesadevine	0:e1a608bb55e8	2350	#define GPIO_DIRSET_PIN19_Pos (19UL) /!< Position of PIN19 field. /
jamesadevine	0:e1a608bb55e8	2351	#define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /!< Bit mask of PIN19 field. /
jamesadevine	0:e1a608bb55e8	2352	#define GPIO_DIRSET_PIN19_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2353	#define GPIO_DIRSET_PIN19_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2354	#define GPIO_DIRSET_PIN19_Set (1UL) /!< Set pin as output. /
jamesadevine	0:e1a608bb55e8	2355
jamesadevine	0:e1a608bb55e8	2356	/* Bit 18 : Set as output pin 18. */
jamesadevine	0:e1a608bb55e8	2357	#define GPIO_DIRSET_PIN18_Pos (18UL) /!< Position of PIN18 field. /
jamesadevine	0:e1a608bb55e8	2358	#define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /!< Bit mask of PIN18 field. /
jamesadevine	0:e1a608bb55e8	2359	#define GPIO_DIRSET_PIN18_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2360	#define GPIO_DIRSET_PIN18_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2361	#define GPIO_DIRSET_PIN18_Set (1UL) /!< Set pin as output. /
jamesadevine	0:e1a608bb55e8	2362
jamesadevine	0:e1a608bb55e8	2363	/* Bit 17 : Set as output pin 17. */
jamesadevine	0:e1a608bb55e8	2364	#define GPIO_DIRSET_PIN17_Pos (17UL) /!< Position of PIN17 field. /
jamesadevine	0:e1a608bb55e8	2365	#define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /!< Bit mask of PIN17 field. /
jamesadevine	0:e1a608bb55e8	2366	#define GPIO_DIRSET_PIN17_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2367	#define GPIO_DIRSET_PIN17_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2368	#define GPIO_DIRSET_PIN17_Set (1UL) /!< Set pin as output. /
jamesadevine	0:e1a608bb55e8	2369
jamesadevine	0:e1a608bb55e8	2370	/* Bit 16 : Set as output pin 16. */
jamesadevine	0:e1a608bb55e8	2371	#define GPIO_DIRSET_PIN16_Pos (16UL) /!< Position of PIN16 field. /
jamesadevine	0:e1a608bb55e8	2372	#define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /!< Bit mask of PIN16 field. /
jamesadevine	0:e1a608bb55e8	2373	#define GPIO_DIRSET_PIN16_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2374	#define GPIO_DIRSET_PIN16_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2375	#define GPIO_DIRSET_PIN16_Set (1UL) /!< Set pin as output. /
jamesadevine	0:e1a608bb55e8	2376
jamesadevine	0:e1a608bb55e8	2377	/* Bit 15 : Set as output pin 15. */
jamesadevine	0:e1a608bb55e8	2378	#define GPIO_DIRSET_PIN15_Pos (15UL) /!< Position of PIN15 field. /
jamesadevine	0:e1a608bb55e8	2379	#define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /!< Bit mask of PIN15 field. /
jamesadevine	0:e1a608bb55e8	2380	#define GPIO_DIRSET_PIN15_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2381	#define GPIO_DIRSET_PIN15_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2382	#define GPIO_DIRSET_PIN15_Set (1UL) /!< Set pin as output. /
jamesadevine	0:e1a608bb55e8	2383
jamesadevine	0:e1a608bb55e8	2384	/* Bit 14 : Set as output pin 14. */
jamesadevine	0:e1a608bb55e8	2385	#define GPIO_DIRSET_PIN14_Pos (14UL) /!< Position of PIN14 field. /
jamesadevine	0:e1a608bb55e8	2386	#define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /!< Bit mask of PIN14 field. /
jamesadevine	0:e1a608bb55e8	2387	#define GPIO_DIRSET_PIN14_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2388	#define GPIO_DIRSET_PIN14_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2389	#define GPIO_DIRSET_PIN14_Set (1UL) /!< Set pin as output. /
jamesadevine	0:e1a608bb55e8	2390
jamesadevine	0:e1a608bb55e8	2391	/* Bit 13 : Set as output pin 13. */
jamesadevine	0:e1a608bb55e8	2392	#define GPIO_DIRSET_PIN13_Pos (13UL) /!< Position of PIN13 field. /
jamesadevine	0:e1a608bb55e8	2393	#define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /!< Bit mask of PIN13 field. /
jamesadevine	0:e1a608bb55e8	2394	#define GPIO_DIRSET_PIN13_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2395	#define GPIO_DIRSET_PIN13_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2396	#define GPIO_DIRSET_PIN13_Set (1UL) /!< Set pin as output. /
jamesadevine	0:e1a608bb55e8	2397
jamesadevine	0:e1a608bb55e8	2398	/* Bit 12 : Set as output pin 12. */
jamesadevine	0:e1a608bb55e8	2399	#define GPIO_DIRSET_PIN12_Pos (12UL) /!< Position of PIN12 field. /
jamesadevine	0:e1a608bb55e8	2400	#define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /!< Bit mask of PIN12 field. /
jamesadevine	0:e1a608bb55e8	2401	#define GPIO_DIRSET_PIN12_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2402	#define GPIO_DIRSET_PIN12_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2403	#define GPIO_DIRSET_PIN12_Set (1UL) /!< Set pin as output. /
jamesadevine	0:e1a608bb55e8	2404
jamesadevine	0:e1a608bb55e8	2405	/* Bit 11 : Set as output pin 11. */
jamesadevine	0:e1a608bb55e8	2406	#define GPIO_DIRSET_PIN11_Pos (11UL) /!< Position of PIN11 field. /
jamesadevine	0:e1a608bb55e8	2407	#define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /!< Bit mask of PIN11 field. /
jamesadevine	0:e1a608bb55e8	2408	#define GPIO_DIRSET_PIN11_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2409	#define GPIO_DIRSET_PIN11_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2410	#define GPIO_DIRSET_PIN11_Set (1UL) /!< Set pin as output. /
jamesadevine	0:e1a608bb55e8	2411
jamesadevine	0:e1a608bb55e8	2412	/* Bit 10 : Set as output pin 10. */
jamesadevine	0:e1a608bb55e8	2413	#define GPIO_DIRSET_PIN10_Pos (10UL) /!< Position of PIN10 field. /
jamesadevine	0:e1a608bb55e8	2414	#define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /!< Bit mask of PIN10 field. /
jamesadevine	0:e1a608bb55e8	2415	#define GPIO_DIRSET_PIN10_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2416	#define GPIO_DIRSET_PIN10_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2417	#define GPIO_DIRSET_PIN10_Set (1UL) /!< Set pin as output. /
jamesadevine	0:e1a608bb55e8	2418
jamesadevine	0:e1a608bb55e8	2419	/* Bit 9 : Set as output pin 9. */
jamesadevine	0:e1a608bb55e8	2420	#define GPIO_DIRSET_PIN9_Pos (9UL) /!< Position of PIN9 field. /
jamesadevine	0:e1a608bb55e8	2421	#define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /!< Bit mask of PIN9 field. /
jamesadevine	0:e1a608bb55e8	2422	#define GPIO_DIRSET_PIN9_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2423	#define GPIO_DIRSET_PIN9_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2424	#define GPIO_DIRSET_PIN9_Set (1UL) /!< Set pin as output. /
jamesadevine	0:e1a608bb55e8	2425
jamesadevine	0:e1a608bb55e8	2426	/* Bit 8 : Set as output pin 8. */
jamesadevine	0:e1a608bb55e8	2427	#define GPIO_DIRSET_PIN8_Pos (8UL) /!< Position of PIN8 field. /
jamesadevine	0:e1a608bb55e8	2428	#define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /!< Bit mask of PIN8 field. /
jamesadevine	0:e1a608bb55e8	2429	#define GPIO_DIRSET_PIN8_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2430	#define GPIO_DIRSET_PIN8_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2431	#define GPIO_DIRSET_PIN8_Set (1UL) /!< Set pin as output. /
jamesadevine	0:e1a608bb55e8	2432
jamesadevine	0:e1a608bb55e8	2433	/* Bit 7 : Set as output pin 7. */
jamesadevine	0:e1a608bb55e8	2434	#define GPIO_DIRSET_PIN7_Pos (7UL) /!< Position of PIN7 field. /
jamesadevine	0:e1a608bb55e8	2435	#define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /!< Bit mask of PIN7 field. /
jamesadevine	0:e1a608bb55e8	2436	#define GPIO_DIRSET_PIN7_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2437	#define GPIO_DIRSET_PIN7_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2438	#define GPIO_DIRSET_PIN7_Set (1UL) /!< Set pin as output. /
jamesadevine	0:e1a608bb55e8	2439
jamesadevine	0:e1a608bb55e8	2440	/* Bit 6 : Set as output pin 6. */
jamesadevine	0:e1a608bb55e8	2441	#define GPIO_DIRSET_PIN6_Pos (6UL) /!< Position of PIN6 field. /
jamesadevine	0:e1a608bb55e8	2442	#define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /!< Bit mask of PIN6 field. /
jamesadevine	0:e1a608bb55e8	2443	#define GPIO_DIRSET_PIN6_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2444	#define GPIO_DIRSET_PIN6_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2445	#define GPIO_DIRSET_PIN6_Set (1UL) /!< Set pin as output. /
jamesadevine	0:e1a608bb55e8	2446
jamesadevine	0:e1a608bb55e8	2447	/* Bit 5 : Set as output pin 5. */
jamesadevine	0:e1a608bb55e8	2448	#define GPIO_DIRSET_PIN5_Pos (5UL) /!< Position of PIN5 field. /
jamesadevine	0:e1a608bb55e8	2449	#define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /!< Bit mask of PIN5 field. /
jamesadevine	0:e1a608bb55e8	2450	#define GPIO_DIRSET_PIN5_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2451	#define GPIO_DIRSET_PIN5_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2452	#define GPIO_DIRSET_PIN5_Set (1UL) /!< Set pin as output. /
jamesadevine	0:e1a608bb55e8	2453
jamesadevine	0:e1a608bb55e8	2454	/* Bit 4 : Set as output pin 4. */
jamesadevine	0:e1a608bb55e8	2455	#define GPIO_DIRSET_PIN4_Pos (4UL) /!< Position of PIN4 field. /
jamesadevine	0:e1a608bb55e8	2456	#define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /!< Bit mask of PIN4 field. /
jamesadevine	0:e1a608bb55e8	2457	#define GPIO_DIRSET_PIN4_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2458	#define GPIO_DIRSET_PIN4_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2459	#define GPIO_DIRSET_PIN4_Set (1UL) /!< Set pin as output. /
jamesadevine	0:e1a608bb55e8	2460
jamesadevine	0:e1a608bb55e8	2461	/* Bit 3 : Set as output pin 3. */
jamesadevine	0:e1a608bb55e8	2462	#define GPIO_DIRSET_PIN3_Pos (3UL) /!< Position of PIN3 field. /
jamesadevine	0:e1a608bb55e8	2463	#define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /!< Bit mask of PIN3 field. /
jamesadevine	0:e1a608bb55e8	2464	#define GPIO_DIRSET_PIN3_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2465	#define GPIO_DIRSET_PIN3_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2466	#define GPIO_DIRSET_PIN3_Set (1UL) /!< Set pin as output. /
jamesadevine	0:e1a608bb55e8	2467
jamesadevine	0:e1a608bb55e8	2468	/* Bit 2 : Set as output pin 2. */
jamesadevine	0:e1a608bb55e8	2469	#define GPIO_DIRSET_PIN2_Pos (2UL) /!< Position of PIN2 field. /
jamesadevine	0:e1a608bb55e8	2470	#define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /!< Bit mask of PIN2 field. /
jamesadevine	0:e1a608bb55e8	2471	#define GPIO_DIRSET_PIN2_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2472	#define GPIO_DIRSET_PIN2_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2473	#define GPIO_DIRSET_PIN2_Set (1UL) /!< Set pin as output. /
jamesadevine	0:e1a608bb55e8	2474
jamesadevine	0:e1a608bb55e8	2475	/* Bit 1 : Set as output pin 1. */
jamesadevine	0:e1a608bb55e8	2476	#define GPIO_DIRSET_PIN1_Pos (1UL) /!< Position of PIN1 field. /
jamesadevine	0:e1a608bb55e8	2477	#define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /!< Bit mask of PIN1 field. /
jamesadevine	0:e1a608bb55e8	2478	#define GPIO_DIRSET_PIN1_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2479	#define GPIO_DIRSET_PIN1_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2480	#define GPIO_DIRSET_PIN1_Set (1UL) /!< Set pin as output. /
jamesadevine	0:e1a608bb55e8	2481
jamesadevine	0:e1a608bb55e8	2482	/* Bit 0 : Set as output pin 0. */
jamesadevine	0:e1a608bb55e8	2483	#define GPIO_DIRSET_PIN0_Pos (0UL) /!< Position of PIN0 field. /
jamesadevine	0:e1a608bb55e8	2484	#define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /!< Bit mask of PIN0 field. /
jamesadevine	0:e1a608bb55e8	2485	#define GPIO_DIRSET_PIN0_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2486	#define GPIO_DIRSET_PIN0_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2487	#define GPIO_DIRSET_PIN0_Set (1UL) /!< Set pin as output. /
jamesadevine	0:e1a608bb55e8	2488
jamesadevine	0:e1a608bb55e8	2489	/* Register: GPIO_DIRCLR */
jamesadevine	0:e1a608bb55e8	2490	/* Description: DIR clear register. */
jamesadevine	0:e1a608bb55e8	2491
jamesadevine	0:e1a608bb55e8	2492	/* Bit 31 : Set as input pin 31. */
jamesadevine	0:e1a608bb55e8	2493	#define GPIO_DIRCLR_PIN31_Pos (31UL) /!< Position of PIN31 field. /
jamesadevine	0:e1a608bb55e8	2494	#define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /!< Bit mask of PIN31 field. /
jamesadevine	0:e1a608bb55e8	2495	#define GPIO_DIRCLR_PIN31_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2496	#define GPIO_DIRCLR_PIN31_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2497	#define GPIO_DIRCLR_PIN31_Clear (1UL) /!< Set pin as input. /
jamesadevine	0:e1a608bb55e8	2498
jamesadevine	0:e1a608bb55e8	2499	/* Bit 30 : Set as input pin 30. */
jamesadevine	0:e1a608bb55e8	2500	#define GPIO_DIRCLR_PIN30_Pos (30UL) /!< Position of PIN30 field. /
jamesadevine	0:e1a608bb55e8	2501	#define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /!< Bit mask of PIN30 field. /
jamesadevine	0:e1a608bb55e8	2502	#define GPIO_DIRCLR_PIN30_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2503	#define GPIO_DIRCLR_PIN30_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2504	#define GPIO_DIRCLR_PIN30_Clear (1UL) /!< Set pin as input. /
jamesadevine	0:e1a608bb55e8	2505
jamesadevine	0:e1a608bb55e8	2506	/* Bit 29 : Set as input pin 29. */
jamesadevine	0:e1a608bb55e8	2507	#define GPIO_DIRCLR_PIN29_Pos (29UL) /!< Position of PIN29 field. /
jamesadevine	0:e1a608bb55e8	2508	#define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /!< Bit mask of PIN29 field. /
jamesadevine	0:e1a608bb55e8	2509	#define GPIO_DIRCLR_PIN29_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2510	#define GPIO_DIRCLR_PIN29_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2511	#define GPIO_DIRCLR_PIN29_Clear (1UL) /!< Set pin as input. /
jamesadevine	0:e1a608bb55e8	2512
jamesadevine	0:e1a608bb55e8	2513	/* Bit 28 : Set as input pin 28. */
jamesadevine	0:e1a608bb55e8	2514	#define GPIO_DIRCLR_PIN28_Pos (28UL) /!< Position of PIN28 field. /
jamesadevine	0:e1a608bb55e8	2515	#define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /!< Bit mask of PIN28 field. /
jamesadevine	0:e1a608bb55e8	2516	#define GPIO_DIRCLR_PIN28_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2517	#define GPIO_DIRCLR_PIN28_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2518	#define GPIO_DIRCLR_PIN28_Clear (1UL) /!< Set pin as input. /
jamesadevine	0:e1a608bb55e8	2519
jamesadevine	0:e1a608bb55e8	2520	/* Bit 27 : Set as input pin 27. */
jamesadevine	0:e1a608bb55e8	2521	#define GPIO_DIRCLR_PIN27_Pos (27UL) /!< Position of PIN27 field. /
jamesadevine	0:e1a608bb55e8	2522	#define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /!< Bit mask of PIN27 field. /
jamesadevine	0:e1a608bb55e8	2523	#define GPIO_DIRCLR_PIN27_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2524	#define GPIO_DIRCLR_PIN27_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2525	#define GPIO_DIRCLR_PIN27_Clear (1UL) /!< Set pin as input. /
jamesadevine	0:e1a608bb55e8	2526
jamesadevine	0:e1a608bb55e8	2527	/* Bit 26 : Set as input pin 26. */
jamesadevine	0:e1a608bb55e8	2528	#define GPIO_DIRCLR_PIN26_Pos (26UL) /!< Position of PIN26 field. /
jamesadevine	0:e1a608bb55e8	2529	#define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /!< Bit mask of PIN26 field. /
jamesadevine	0:e1a608bb55e8	2530	#define GPIO_DIRCLR_PIN26_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2531	#define GPIO_DIRCLR_PIN26_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2532	#define GPIO_DIRCLR_PIN26_Clear (1UL) /!< Set pin as input. /
jamesadevine	0:e1a608bb55e8	2533
jamesadevine	0:e1a608bb55e8	2534	/* Bit 25 : Set as input pin 25. */
jamesadevine	0:e1a608bb55e8	2535	#define GPIO_DIRCLR_PIN25_Pos (25UL) /!< Position of PIN25 field. /
jamesadevine	0:e1a608bb55e8	2536	#define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /!< Bit mask of PIN25 field. /
jamesadevine	0:e1a608bb55e8	2537	#define GPIO_DIRCLR_PIN25_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2538	#define GPIO_DIRCLR_PIN25_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2539	#define GPIO_DIRCLR_PIN25_Clear (1UL) /!< Set pin as input. /
jamesadevine	0:e1a608bb55e8	2540
jamesadevine	0:e1a608bb55e8	2541	/* Bit 24 : Set as input pin 24. */
jamesadevine	0:e1a608bb55e8	2542	#define GPIO_DIRCLR_PIN24_Pos (24UL) /!< Position of PIN24 field. /
jamesadevine	0:e1a608bb55e8	2543	#define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /!< Bit mask of PIN24 field. /
jamesadevine	0:e1a608bb55e8	2544	#define GPIO_DIRCLR_PIN24_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2545	#define GPIO_DIRCLR_PIN24_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2546	#define GPIO_DIRCLR_PIN24_Clear (1UL) /!< Set pin as input. /
jamesadevine	0:e1a608bb55e8	2547
jamesadevine	0:e1a608bb55e8	2548	/* Bit 23 : Set as input pin 23. */
jamesadevine	0:e1a608bb55e8	2549	#define GPIO_DIRCLR_PIN23_Pos (23UL) /!< Position of PIN23 field. /
jamesadevine	0:e1a608bb55e8	2550	#define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /!< Bit mask of PIN23 field. /
jamesadevine	0:e1a608bb55e8	2551	#define GPIO_DIRCLR_PIN23_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2552	#define GPIO_DIRCLR_PIN23_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2553	#define GPIO_DIRCLR_PIN23_Clear (1UL) /!< Set pin as input. /
jamesadevine	0:e1a608bb55e8	2554
jamesadevine	0:e1a608bb55e8	2555	/* Bit 22 : Set as input pin 22. */
jamesadevine	0:e1a608bb55e8	2556	#define GPIO_DIRCLR_PIN22_Pos (22UL) /!< Position of PIN22 field. /
jamesadevine	0:e1a608bb55e8	2557	#define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /!< Bit mask of PIN22 field. /
jamesadevine	0:e1a608bb55e8	2558	#define GPIO_DIRCLR_PIN22_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2559	#define GPIO_DIRCLR_PIN22_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2560	#define GPIO_DIRCLR_PIN22_Clear (1UL) /!< Set pin as input. /
jamesadevine	0:e1a608bb55e8	2561
jamesadevine	0:e1a608bb55e8	2562	/* Bit 21 : Set as input pin 21. */
jamesadevine	0:e1a608bb55e8	2563	#define GPIO_DIRCLR_PIN21_Pos (21UL) /!< Position of PIN21 field. /
jamesadevine	0:e1a608bb55e8	2564	#define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /!< Bit mask of PIN21 field. /
jamesadevine	0:e1a608bb55e8	2565	#define GPIO_DIRCLR_PIN21_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2566	#define GPIO_DIRCLR_PIN21_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2567	#define GPIO_DIRCLR_PIN21_Clear (1UL) /!< Set pin as input. /
jamesadevine	0:e1a608bb55e8	2568
jamesadevine	0:e1a608bb55e8	2569	/* Bit 20 : Set as input pin 20. */
jamesadevine	0:e1a608bb55e8	2570	#define GPIO_DIRCLR_PIN20_Pos (20UL) /!< Position of PIN20 field. /
jamesadevine	0:e1a608bb55e8	2571	#define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /!< Bit mask of PIN20 field. /
jamesadevine	0:e1a608bb55e8	2572	#define GPIO_DIRCLR_PIN20_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2573	#define GPIO_DIRCLR_PIN20_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2574	#define GPIO_DIRCLR_PIN20_Clear (1UL) /!< Set pin as input. /
jamesadevine	0:e1a608bb55e8	2575
jamesadevine	0:e1a608bb55e8	2576	/* Bit 19 : Set as input pin 19. */
jamesadevine	0:e1a608bb55e8	2577	#define GPIO_DIRCLR_PIN19_Pos (19UL) /!< Position of PIN19 field. /
jamesadevine	0:e1a608bb55e8	2578	#define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /!< Bit mask of PIN19 field. /
jamesadevine	0:e1a608bb55e8	2579	#define GPIO_DIRCLR_PIN19_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2580	#define GPIO_DIRCLR_PIN19_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2581	#define GPIO_DIRCLR_PIN19_Clear (1UL) /!< Set pin as input. /
jamesadevine	0:e1a608bb55e8	2582
jamesadevine	0:e1a608bb55e8	2583	/* Bit 18 : Set as input pin 18. */
jamesadevine	0:e1a608bb55e8	2584	#define GPIO_DIRCLR_PIN18_Pos (18UL) /!< Position of PIN18 field. /
jamesadevine	0:e1a608bb55e8	2585	#define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /!< Bit mask of PIN18 field. /
jamesadevine	0:e1a608bb55e8	2586	#define GPIO_DIRCLR_PIN18_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2587	#define GPIO_DIRCLR_PIN18_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2588	#define GPIO_DIRCLR_PIN18_Clear (1UL) /!< Set pin as input. /
jamesadevine	0:e1a608bb55e8	2589
jamesadevine	0:e1a608bb55e8	2590	/* Bit 17 : Set as input pin 17. */
jamesadevine	0:e1a608bb55e8	2591	#define GPIO_DIRCLR_PIN17_Pos (17UL) /!< Position of PIN17 field. /
jamesadevine	0:e1a608bb55e8	2592	#define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /!< Bit mask of PIN17 field. /
jamesadevine	0:e1a608bb55e8	2593	#define GPIO_DIRCLR_PIN17_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2594	#define GPIO_DIRCLR_PIN17_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2595	#define GPIO_DIRCLR_PIN17_Clear (1UL) /!< Set pin as input. /
jamesadevine	0:e1a608bb55e8	2596
jamesadevine	0:e1a608bb55e8	2597	/* Bit 16 : Set as input pin 16. */
jamesadevine	0:e1a608bb55e8	2598	#define GPIO_DIRCLR_PIN16_Pos (16UL) /!< Position of PIN16 field. /
jamesadevine	0:e1a608bb55e8	2599	#define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /!< Bit mask of PIN16 field. /
jamesadevine	0:e1a608bb55e8	2600	#define GPIO_DIRCLR_PIN16_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2601	#define GPIO_DIRCLR_PIN16_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2602	#define GPIO_DIRCLR_PIN16_Clear (1UL) /!< Set pin as input. /
jamesadevine	0:e1a608bb55e8	2603
jamesadevine	0:e1a608bb55e8	2604	/* Bit 15 : Set as input pin 15. */
jamesadevine	0:e1a608bb55e8	2605	#define GPIO_DIRCLR_PIN15_Pos (15UL) /!< Position of PIN15 field. /
jamesadevine	0:e1a608bb55e8	2606	#define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /!< Bit mask of PIN15 field. /
jamesadevine	0:e1a608bb55e8	2607	#define GPIO_DIRCLR_PIN15_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2608	#define GPIO_DIRCLR_PIN15_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2609	#define GPIO_DIRCLR_PIN15_Clear (1UL) /!< Set pin as input. /
jamesadevine	0:e1a608bb55e8	2610
jamesadevine	0:e1a608bb55e8	2611	/* Bit 14 : Set as input pin 14. */
jamesadevine	0:e1a608bb55e8	2612	#define GPIO_DIRCLR_PIN14_Pos (14UL) /!< Position of PIN14 field. /
jamesadevine	0:e1a608bb55e8	2613	#define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /!< Bit mask of PIN14 field. /
jamesadevine	0:e1a608bb55e8	2614	#define GPIO_DIRCLR_PIN14_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2615	#define GPIO_DIRCLR_PIN14_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2616	#define GPIO_DIRCLR_PIN14_Clear (1UL) /!< Set pin as input. /
jamesadevine	0:e1a608bb55e8	2617
jamesadevine	0:e1a608bb55e8	2618	/* Bit 13 : Set as input pin 13. */
jamesadevine	0:e1a608bb55e8	2619	#define GPIO_DIRCLR_PIN13_Pos (13UL) /!< Position of PIN13 field. /
jamesadevine	0:e1a608bb55e8	2620	#define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /!< Bit mask of PIN13 field. /
jamesadevine	0:e1a608bb55e8	2621	#define GPIO_DIRCLR_PIN13_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2622	#define GPIO_DIRCLR_PIN13_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2623	#define GPIO_DIRCLR_PIN13_Clear (1UL) /!< Set pin as input. /
jamesadevine	0:e1a608bb55e8	2624
jamesadevine	0:e1a608bb55e8	2625	/* Bit 12 : Set as input pin 12. */
jamesadevine	0:e1a608bb55e8	2626	#define GPIO_DIRCLR_PIN12_Pos (12UL) /!< Position of PIN12 field. /
jamesadevine	0:e1a608bb55e8	2627	#define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /!< Bit mask of PIN12 field. /
jamesadevine	0:e1a608bb55e8	2628	#define GPIO_DIRCLR_PIN12_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2629	#define GPIO_DIRCLR_PIN12_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2630	#define GPIO_DIRCLR_PIN12_Clear (1UL) /!< Set pin as input. /
jamesadevine	0:e1a608bb55e8	2631
jamesadevine	0:e1a608bb55e8	2632	/* Bit 11 : Set as input pin 11. */
jamesadevine	0:e1a608bb55e8	2633	#define GPIO_DIRCLR_PIN11_Pos (11UL) /!< Position of PIN11 field. /
jamesadevine	0:e1a608bb55e8	2634	#define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /!< Bit mask of PIN11 field. /
jamesadevine	0:e1a608bb55e8	2635	#define GPIO_DIRCLR_PIN11_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2636	#define GPIO_DIRCLR_PIN11_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2637	#define GPIO_DIRCLR_PIN11_Clear (1UL) /!< Set pin as input. /
jamesadevine	0:e1a608bb55e8	2638
jamesadevine	0:e1a608bb55e8	2639	/* Bit 10 : Set as input pin 10. */
jamesadevine	0:e1a608bb55e8	2640	#define GPIO_DIRCLR_PIN10_Pos (10UL) /!< Position of PIN10 field. /
jamesadevine	0:e1a608bb55e8	2641	#define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /!< Bit mask of PIN10 field. /
jamesadevine	0:e1a608bb55e8	2642	#define GPIO_DIRCLR_PIN10_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2643	#define GPIO_DIRCLR_PIN10_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2644	#define GPIO_DIRCLR_PIN10_Clear (1UL) /!< Set pin as input. /
jamesadevine	0:e1a608bb55e8	2645
jamesadevine	0:e1a608bb55e8	2646	/* Bit 9 : Set as input pin 9. */
jamesadevine	0:e1a608bb55e8	2647	#define GPIO_DIRCLR_PIN9_Pos (9UL) /!< Position of PIN9 field. /
jamesadevine	0:e1a608bb55e8	2648	#define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /!< Bit mask of PIN9 field. /
jamesadevine	0:e1a608bb55e8	2649	#define GPIO_DIRCLR_PIN9_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2650	#define GPIO_DIRCLR_PIN9_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2651	#define GPIO_DIRCLR_PIN9_Clear (1UL) /!< Set pin as input. /
jamesadevine	0:e1a608bb55e8	2652
jamesadevine	0:e1a608bb55e8	2653	/* Bit 8 : Set as input pin 8. */
jamesadevine	0:e1a608bb55e8	2654	#define GPIO_DIRCLR_PIN8_Pos (8UL) /!< Position of PIN8 field. /
jamesadevine	0:e1a608bb55e8	2655	#define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /!< Bit mask of PIN8 field. /
jamesadevine	0:e1a608bb55e8	2656	#define GPIO_DIRCLR_PIN8_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2657	#define GPIO_DIRCLR_PIN8_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2658	#define GPIO_DIRCLR_PIN8_Clear (1UL) /!< Set pin as input. /
jamesadevine	0:e1a608bb55e8	2659
jamesadevine	0:e1a608bb55e8	2660	/* Bit 7 : Set as input pin 7. */
jamesadevine	0:e1a608bb55e8	2661	#define GPIO_DIRCLR_PIN7_Pos (7UL) /!< Position of PIN7 field. /
jamesadevine	0:e1a608bb55e8	2662	#define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /!< Bit mask of PIN7 field. /
jamesadevine	0:e1a608bb55e8	2663	#define GPIO_DIRCLR_PIN7_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2664	#define GPIO_DIRCLR_PIN7_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2665	#define GPIO_DIRCLR_PIN7_Clear (1UL) /!< Set pin as input. /
jamesadevine	0:e1a608bb55e8	2666
jamesadevine	0:e1a608bb55e8	2667	/* Bit 6 : Set as input pin 6. */
jamesadevine	0:e1a608bb55e8	2668	#define GPIO_DIRCLR_PIN6_Pos (6UL) /!< Position of PIN6 field. /
jamesadevine	0:e1a608bb55e8	2669	#define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /!< Bit mask of PIN6 field. /
jamesadevine	0:e1a608bb55e8	2670	#define GPIO_DIRCLR_PIN6_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2671	#define GPIO_DIRCLR_PIN6_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2672	#define GPIO_DIRCLR_PIN6_Clear (1UL) /!< Set pin as input. /
jamesadevine	0:e1a608bb55e8	2673
jamesadevine	0:e1a608bb55e8	2674	/* Bit 5 : Set as input pin 5. */
jamesadevine	0:e1a608bb55e8	2675	#define GPIO_DIRCLR_PIN5_Pos (5UL) /!< Position of PIN5 field. /
jamesadevine	0:e1a608bb55e8	2676	#define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /!< Bit mask of PIN5 field. /
jamesadevine	0:e1a608bb55e8	2677	#define GPIO_DIRCLR_PIN5_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2678	#define GPIO_DIRCLR_PIN5_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2679	#define GPIO_DIRCLR_PIN5_Clear (1UL) /!< Set pin as input. /
jamesadevine	0:e1a608bb55e8	2680
jamesadevine	0:e1a608bb55e8	2681	/* Bit 4 : Set as input pin 4. */
jamesadevine	0:e1a608bb55e8	2682	#define GPIO_DIRCLR_PIN4_Pos (4UL) /!< Position of PIN4 field. /
jamesadevine	0:e1a608bb55e8	2683	#define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /!< Bit mask of PIN4 field. /
jamesadevine	0:e1a608bb55e8	2684	#define GPIO_DIRCLR_PIN4_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2685	#define GPIO_DIRCLR_PIN4_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2686	#define GPIO_DIRCLR_PIN4_Clear (1UL) /!< Set pin as input. /
jamesadevine	0:e1a608bb55e8	2687
jamesadevine	0:e1a608bb55e8	2688	/* Bit 3 : Set as input pin 3. */
jamesadevine	0:e1a608bb55e8	2689	#define GPIO_DIRCLR_PIN3_Pos (3UL) /!< Position of PIN3 field. /
jamesadevine	0:e1a608bb55e8	2690	#define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /!< Bit mask of PIN3 field. /
jamesadevine	0:e1a608bb55e8	2691	#define GPIO_DIRCLR_PIN3_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2692	#define GPIO_DIRCLR_PIN3_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2693	#define GPIO_DIRCLR_PIN3_Clear (1UL) /!< Set pin as input. /
jamesadevine	0:e1a608bb55e8	2694
jamesadevine	0:e1a608bb55e8	2695	/* Bit 2 : Set as input pin 2. */
jamesadevine	0:e1a608bb55e8	2696	#define GPIO_DIRCLR_PIN2_Pos (2UL) /!< Position of PIN2 field. /
jamesadevine	0:e1a608bb55e8	2697	#define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /!< Bit mask of PIN2 field. /
jamesadevine	0:e1a608bb55e8	2698	#define GPIO_DIRCLR_PIN2_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2699	#define GPIO_DIRCLR_PIN2_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2700	#define GPIO_DIRCLR_PIN2_Clear (1UL) /!< Set pin as input. /
jamesadevine	0:e1a608bb55e8	2701
jamesadevine	0:e1a608bb55e8	2702	/* Bit 1 : Set as input pin 1. */
jamesadevine	0:e1a608bb55e8	2703	#define GPIO_DIRCLR_PIN1_Pos (1UL) /!< Position of PIN1 field. /
jamesadevine	0:e1a608bb55e8	2704	#define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /!< Bit mask of PIN1 field. /
jamesadevine	0:e1a608bb55e8	2705	#define GPIO_DIRCLR_PIN1_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2706	#define GPIO_DIRCLR_PIN1_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2707	#define GPIO_DIRCLR_PIN1_Clear (1UL) /!< Set pin as input. /
jamesadevine	0:e1a608bb55e8	2708
jamesadevine	0:e1a608bb55e8	2709	/* Bit 0 : Set as input pin 0. */
jamesadevine	0:e1a608bb55e8	2710	#define GPIO_DIRCLR_PIN0_Pos (0UL) /!< Position of PIN0 field. /
jamesadevine	0:e1a608bb55e8	2711	#define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /!< Bit mask of PIN0 field. /
jamesadevine	0:e1a608bb55e8	2712	#define GPIO_DIRCLR_PIN0_Input (0UL) /!< Pin set as input. /
jamesadevine	0:e1a608bb55e8	2713	#define GPIO_DIRCLR_PIN0_Output (1UL) /!< Pin set as output. /
jamesadevine	0:e1a608bb55e8	2714	#define GPIO_DIRCLR_PIN0_Clear (1UL) /!< Set pin as input. /
jamesadevine	0:e1a608bb55e8	2715
jamesadevine	0:e1a608bb55e8	2716	/* Register: GPIO_PIN_CNF */
jamesadevine	0:e1a608bb55e8	2717	/* Description: Configuration of GPIO pins. */
jamesadevine	0:e1a608bb55e8	2718
jamesadevine	0:e1a608bb55e8	2719	/* Bits 17..16 : Pin sensing mechanism. */
jamesadevine	0:e1a608bb55e8	2720	#define GPIO_PIN_CNF_SENSE_Pos (16UL) /!< Position of SENSE field. /
jamesadevine	0:e1a608bb55e8	2721	#define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /!< Bit mask of SENSE field. /
jamesadevine	0:e1a608bb55e8	2722	#define GPIO_PIN_CNF_SENSE_Disabled (0x00UL) /!< Disabled. /
jamesadevine	0:e1a608bb55e8	2723	#define GPIO_PIN_CNF_SENSE_High (0x02UL) /!< Wakeup on high level. /
jamesadevine	0:e1a608bb55e8	2724	#define GPIO_PIN_CNF_SENSE_Low (0x03UL) /!< Wakeup on low level. /
jamesadevine	0:e1a608bb55e8	2725
jamesadevine	0:e1a608bb55e8	2726	/* Bits 10..8 : Drive configuration. */
jamesadevine	0:e1a608bb55e8	2727	#define GPIO_PIN_CNF_DRIVE_Pos (8UL) /!< Position of DRIVE field. /
jamesadevine	0:e1a608bb55e8	2728	#define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /!< Bit mask of DRIVE field. /
jamesadevine	0:e1a608bb55e8	2729	#define GPIO_PIN_CNF_DRIVE_S0S1 (0x00UL) /!< Standard '0', Standard '1'. /
jamesadevine	0:e1a608bb55e8	2730	#define GPIO_PIN_CNF_DRIVE_H0S1 (0x01UL) /!< High '0', Standard '1'. /
jamesadevine	0:e1a608bb55e8	2731	#define GPIO_PIN_CNF_DRIVE_S0H1 (0x02UL) /!< Standard '0', High '1'. /
jamesadevine	0:e1a608bb55e8	2732	#define GPIO_PIN_CNF_DRIVE_H0H1 (0x03UL) /!< High '0', High '1'. /
jamesadevine	0:e1a608bb55e8	2733	#define GPIO_PIN_CNF_DRIVE_D0S1 (0x04UL) /!< Disconnected '0', Standard '1'. /
jamesadevine	0:e1a608bb55e8	2734	#define GPIO_PIN_CNF_DRIVE_D0H1 (0x05UL) /!< Disconnected '0', High '1'. /
jamesadevine	0:e1a608bb55e8	2735	#define GPIO_PIN_CNF_DRIVE_S0D1 (0x06UL) /!< Standard '0', Disconnected '1'. /
jamesadevine	0:e1a608bb55e8	2736	#define GPIO_PIN_CNF_DRIVE_H0D1 (0x07UL) /!< High '0', Disconnected '1'. /
jamesadevine	0:e1a608bb55e8	2737
jamesadevine	0:e1a608bb55e8	2738	/* Bits 3..2 : Pull-up or -down configuration. */
jamesadevine	0:e1a608bb55e8	2739	#define GPIO_PIN_CNF_PULL_Pos (2UL) /!< Position of PULL field. /
jamesadevine	0:e1a608bb55e8	2740	#define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /!< Bit mask of PULL field. /
jamesadevine	0:e1a608bb55e8	2741	#define GPIO_PIN_CNF_PULL_Disabled (0x00UL) /!< No pull. /
jamesadevine	0:e1a608bb55e8	2742	#define GPIO_PIN_CNF_PULL_Pulldown (0x01UL) /!< Pulldown on pin. /
jamesadevine	0:e1a608bb55e8	2743	#define GPIO_PIN_CNF_PULL_Pullup (0x03UL) /!< Pullup on pin. /
jamesadevine	0:e1a608bb55e8	2744
jamesadevine	0:e1a608bb55e8	2745	/* Bit 1 : Connect or disconnect input path. */
jamesadevine	0:e1a608bb55e8	2746	#define GPIO_PIN_CNF_INPUT_Pos (1UL) /!< Position of INPUT field. /
jamesadevine	0:e1a608bb55e8	2747	#define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /!< Bit mask of INPUT field. /
jamesadevine	0:e1a608bb55e8	2748	#define GPIO_PIN_CNF_INPUT_Connect (0UL) /!< Connect input pin. /
jamesadevine	0:e1a608bb55e8	2749	#define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /!< Disconnect input pin. /
jamesadevine	0:e1a608bb55e8	2750
jamesadevine	0:e1a608bb55e8	2751	/* Bit 0 : Pin direction. */
jamesadevine	0:e1a608bb55e8	2752	#define GPIO_PIN_CNF_DIR_Pos (0UL) /!< Position of DIR field. /
jamesadevine	0:e1a608bb55e8	2753	#define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /!< Bit mask of DIR field. /
jamesadevine	0:e1a608bb55e8	2754	#define GPIO_PIN_CNF_DIR_Input (0UL) /!< Configure pin as an input pin. /
jamesadevine	0:e1a608bb55e8	2755	#define GPIO_PIN_CNF_DIR_Output (1UL) /!< Configure pin as an output pin. /
jamesadevine	0:e1a608bb55e8	2756
jamesadevine	0:e1a608bb55e8	2757
jamesadevine	0:e1a608bb55e8	2758	/* Peripheral: GPIOTE */
jamesadevine	0:e1a608bb55e8	2759	/* Description: GPIO tasks and events. */
jamesadevine	0:e1a608bb55e8	2760
jamesadevine	0:e1a608bb55e8	2761	/* Register: GPIOTE_INTENSET */
jamesadevine	0:e1a608bb55e8	2762	/* Description: Interrupt enable set register. */
jamesadevine	0:e1a608bb55e8	2763
jamesadevine	0:e1a608bb55e8	2764	/* Bit 31 : Enable interrupt on PORT event. */
jamesadevine	0:e1a608bb55e8	2765	#define GPIOTE_INTENSET_PORT_Pos (31UL) /!< Position of PORT field. /
jamesadevine	0:e1a608bb55e8	2766	#define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /!< Bit mask of PORT field. /
jamesadevine	0:e1a608bb55e8	2767	#define GPIOTE_INTENSET_PORT_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	2768	#define GPIOTE_INTENSET_PORT_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	2769	#define GPIOTE_INTENSET_PORT_Set (1UL) /!< Enable interrupt on write. /
jamesadevine	0:e1a608bb55e8	2770
jamesadevine	0:e1a608bb55e8	2771	/* Bit 3 : Enable interrupt on IN[3] event. */
jamesadevine	0:e1a608bb55e8	2772	#define GPIOTE_INTENSET_IN3_Pos (3UL) /!< Position of IN3 field. /
jamesadevine	0:e1a608bb55e8	2773	#define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /!< Bit mask of IN3 field. /
jamesadevine	0:e1a608bb55e8	2774	#define GPIOTE_INTENSET_IN3_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	2775	#define GPIOTE_INTENSET_IN3_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	2776	#define GPIOTE_INTENSET_IN3_Set (1UL) /!< Enable interrupt on write. /
jamesadevine	0:e1a608bb55e8	2777
jamesadevine	0:e1a608bb55e8	2778	/* Bit 2 : Enable interrupt on IN[2] event. */
jamesadevine	0:e1a608bb55e8	2779	#define GPIOTE_INTENSET_IN2_Pos (2UL) /!< Position of IN2 field. /
jamesadevine	0:e1a608bb55e8	2780	#define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /!< Bit mask of IN2 field. /
jamesadevine	0:e1a608bb55e8	2781	#define GPIOTE_INTENSET_IN2_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	2782	#define GPIOTE_INTENSET_IN2_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	2783	#define GPIOTE_INTENSET_IN2_Set (1UL) /!< Enable interrupt on write. /
jamesadevine	0:e1a608bb55e8	2784
jamesadevine	0:e1a608bb55e8	2785	/* Bit 1 : Enable interrupt on IN[1] event. */
jamesadevine	0:e1a608bb55e8	2786	#define GPIOTE_INTENSET_IN1_Pos (1UL) /!< Position of IN1 field. /
jamesadevine	0:e1a608bb55e8	2787	#define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /!< Bit mask of IN1 field. /
jamesadevine	0:e1a608bb55e8	2788	#define GPIOTE_INTENSET_IN1_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	2789	#define GPIOTE_INTENSET_IN1_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	2790	#define GPIOTE_INTENSET_IN1_Set (1UL) /!< Enable interrupt on write. /
jamesadevine	0:e1a608bb55e8	2791
jamesadevine	0:e1a608bb55e8	2792	/* Bit 0 : Enable interrupt on IN[0] event. */
jamesadevine	0:e1a608bb55e8	2793	#define GPIOTE_INTENSET_IN0_Pos (0UL) /!< Position of IN0 field. /
jamesadevine	0:e1a608bb55e8	2794	#define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /!< Bit mask of IN0 field. /
jamesadevine	0:e1a608bb55e8	2795	#define GPIOTE_INTENSET_IN0_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	2796	#define GPIOTE_INTENSET_IN0_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	2797	#define GPIOTE_INTENSET_IN0_Set (1UL) /!< Enable interrupt on write. /
jamesadevine	0:e1a608bb55e8	2798
jamesadevine	0:e1a608bb55e8	2799	/* Register: GPIOTE_INTENCLR */
jamesadevine	0:e1a608bb55e8	2800	/* Description: Interrupt enable clear register. */
jamesadevine	0:e1a608bb55e8	2801
jamesadevine	0:e1a608bb55e8	2802	/* Bit 31 : Disable interrupt on PORT event. */
jamesadevine	0:e1a608bb55e8	2803	#define GPIOTE_INTENCLR_PORT_Pos (31UL) /!< Position of PORT field. /
jamesadevine	0:e1a608bb55e8	2804	#define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /!< Bit mask of PORT field. /
jamesadevine	0:e1a608bb55e8	2805	#define GPIOTE_INTENCLR_PORT_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	2806	#define GPIOTE_INTENCLR_PORT_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	2807	#define GPIOTE_INTENCLR_PORT_Clear (1UL) /!< Disable interrupt on write. /
jamesadevine	0:e1a608bb55e8	2808
jamesadevine	0:e1a608bb55e8	2809	/* Bit 3 : Disable interrupt on IN[3] event. */
jamesadevine	0:e1a608bb55e8	2810	#define GPIOTE_INTENCLR_IN3_Pos (3UL) /!< Position of IN3 field. /
jamesadevine	0:e1a608bb55e8	2811	#define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /!< Bit mask of IN3 field. /
jamesadevine	0:e1a608bb55e8	2812	#define GPIOTE_INTENCLR_IN3_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	2813	#define GPIOTE_INTENCLR_IN3_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	2814	#define GPIOTE_INTENCLR_IN3_Clear (1UL) /!< Disable interrupt on write. /
jamesadevine	0:e1a608bb55e8	2815
jamesadevine	0:e1a608bb55e8	2816	/* Bit 2 : Disable interrupt on IN[2] event. */
jamesadevine	0:e1a608bb55e8	2817	#define GPIOTE_INTENCLR_IN2_Pos (2UL) /!< Position of IN2 field. /
jamesadevine	0:e1a608bb55e8	2818	#define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /!< Bit mask of IN2 field. /
jamesadevine	0:e1a608bb55e8	2819	#define GPIOTE_INTENCLR_IN2_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	2820	#define GPIOTE_INTENCLR_IN2_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	2821	#define GPIOTE_INTENCLR_IN2_Clear (1UL) /!< Disable interrupt on write. /
jamesadevine	0:e1a608bb55e8	2822
jamesadevine	0:e1a608bb55e8	2823	/* Bit 1 : Disable interrupt on IN[1] event. */
jamesadevine	0:e1a608bb55e8	2824	#define GPIOTE_INTENCLR_IN1_Pos (1UL) /!< Position of IN1 field. /
jamesadevine	0:e1a608bb55e8	2825	#define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /!< Bit mask of IN1 field. /
jamesadevine	0:e1a608bb55e8	2826	#define GPIOTE_INTENCLR_IN1_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	2827	#define GPIOTE_INTENCLR_IN1_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	2828	#define GPIOTE_INTENCLR_IN1_Clear (1UL) /!< Disable interrupt on write. /
jamesadevine	0:e1a608bb55e8	2829
jamesadevine	0:e1a608bb55e8	2830	/* Bit 0 : Disable interrupt on IN[0] event. */
jamesadevine	0:e1a608bb55e8	2831	#define GPIOTE_INTENCLR_IN0_Pos (0UL) /!< Position of IN0 field. /
jamesadevine	0:e1a608bb55e8	2832	#define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /!< Bit mask of IN0 field. /
jamesadevine	0:e1a608bb55e8	2833	#define GPIOTE_INTENCLR_IN0_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	2834	#define GPIOTE_INTENCLR_IN0_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	2835	#define GPIOTE_INTENCLR_IN0_Clear (1UL) /!< Disable interrupt on write. /
jamesadevine	0:e1a608bb55e8	2836
jamesadevine	0:e1a608bb55e8	2837	/* Register: GPIOTE_CONFIG */
jamesadevine	0:e1a608bb55e8	2838	/* Description: Channel configuration registers. */
jamesadevine	0:e1a608bb55e8	2839
jamesadevine	0:e1a608bb55e8	2840	/* Bit 20 : Initial value of the output when the GPIOTE channel is configured as a Task. */
jamesadevine	0:e1a608bb55e8	2841	#define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /!< Position of OUTINIT field. /
jamesadevine	0:e1a608bb55e8	2842	#define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /!< Bit mask of OUTINIT field. /
jamesadevine	0:e1a608bb55e8	2843	#define GPIOTE_CONFIG_OUTINIT_Low (0UL) /!< Initial low output when in task mode. /
jamesadevine	0:e1a608bb55e8	2844	#define GPIOTE_CONFIG_OUTINIT_High (1UL) /!< Initial high output when in task mode. /
jamesadevine	0:e1a608bb55e8	2845
jamesadevine	0:e1a608bb55e8	2846	/* Bits 17..16 : Effects on output when in Task mode, or events on input that generates an event. */
jamesadevine	0:e1a608bb55e8	2847	#define GPIOTE_CONFIG_POLARITY_Pos (16UL) /!< Position of POLARITY field. /
jamesadevine	0:e1a608bb55e8	2848	#define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /!< Bit mask of POLARITY field. /
jamesadevine	0:e1a608bb55e8	2849	#define GPIOTE_CONFIG_POLARITY_LoToHi (0x01UL) /!< Low to high. /
jamesadevine	0:e1a608bb55e8	2850	#define GPIOTE_CONFIG_POLARITY_HiToLo (0x02UL) /!< High to low. /
jamesadevine	0:e1a608bb55e8	2851	#define GPIOTE_CONFIG_POLARITY_Toggle (0x03UL) /!< Toggle. /
jamesadevine	0:e1a608bb55e8	2852
jamesadevine	0:e1a608bb55e8	2853	/* Bits 12..8 : Pin select. */
jamesadevine	0:e1a608bb55e8	2854	#define GPIOTE_CONFIG_PSEL_Pos (8UL) /!< Position of PSEL field. /
jamesadevine	0:e1a608bb55e8	2855	#define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /!< Bit mask of PSEL field. /
jamesadevine	0:e1a608bb55e8	2856
jamesadevine	0:e1a608bb55e8	2857	/* Bits 1..0 : Mode */
jamesadevine	0:e1a608bb55e8	2858	#define GPIOTE_CONFIG_MODE_Pos (0UL) /!< Position of MODE field. /
jamesadevine	0:e1a608bb55e8	2859	#define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /!< Bit mask of MODE field. /
jamesadevine	0:e1a608bb55e8	2860	#define GPIOTE_CONFIG_MODE_Disabled (0x00UL) /!< Disabled. /
jamesadevine	0:e1a608bb55e8	2861	#define GPIOTE_CONFIG_MODE_Event (0x01UL) /!< Channel configure in event mode. /
jamesadevine	0:e1a608bb55e8	2862	#define GPIOTE_CONFIG_MODE_Task (0x03UL) /!< Channel configure in task mode. /
jamesadevine	0:e1a608bb55e8	2863
jamesadevine	0:e1a608bb55e8	2864	/* Register: GPIOTE_POWER */
jamesadevine	0:e1a608bb55e8	2865	/* Description: Peripheral power control. */
jamesadevine	0:e1a608bb55e8	2866
jamesadevine	0:e1a608bb55e8	2867	/* Bit 0 : Peripheral power control. */
jamesadevine	0:e1a608bb55e8	2868	#define GPIOTE_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
jamesadevine	0:e1a608bb55e8	2869	#define GPIOTE_POWER_POWER_Msk (0x1UL << GPIOTE_POWER_POWER_Pos) /!< Bit mask of POWER field. /
jamesadevine	0:e1a608bb55e8	2870	#define GPIOTE_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
jamesadevine	0:e1a608bb55e8	2871	#define GPIOTE_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
jamesadevine	0:e1a608bb55e8	2872
jamesadevine	0:e1a608bb55e8	2873
jamesadevine	0:e1a608bb55e8	2874	/* Peripheral: LPCOMP */
jamesadevine	0:e1a608bb55e8	2875	/* Description: Low power comparator. */
jamesadevine	0:e1a608bb55e8	2876
jamesadevine	0:e1a608bb55e8	2877	/* Register: LPCOMP_SHORTS */
jamesadevine	0:e1a608bb55e8	2878	/* Description: Shortcuts for the LPCOMP. */
jamesadevine	0:e1a608bb55e8	2879
jamesadevine	0:e1a608bb55e8	2880	/* Bit 4 : Shortcut between CROSS event and STOP task. */
jamesadevine	0:e1a608bb55e8	2881	#define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL) /!< Position of CROSS_STOP field. /
jamesadevine	0:e1a608bb55e8	2882	#define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos) /!< Bit mask of CROSS_STOP field. /
jamesadevine	0:e1a608bb55e8	2883	#define LPCOMP_SHORTS_CROSS_STOP_Disabled (0UL) /!< Shortcut disabled. /
jamesadevine	0:e1a608bb55e8	2884	#define LPCOMP_SHORTS_CROSS_STOP_Enabled (1UL) /!< Shortcut enabled. /
jamesadevine	0:e1a608bb55e8	2885
jamesadevine	0:e1a608bb55e8	2886	/* Bit 3 : Shortcut between UP event and STOP task. */
jamesadevine	0:e1a608bb55e8	2887	#define LPCOMP_SHORTS_UP_STOP_Pos (3UL) /!< Position of UP_STOP field. /
jamesadevine	0:e1a608bb55e8	2888	#define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos) /!< Bit mask of UP_STOP field. /
jamesadevine	0:e1a608bb55e8	2889	#define LPCOMP_SHORTS_UP_STOP_Disabled (0UL) /!< Shortcut disabled. /
jamesadevine	0:e1a608bb55e8	2890	#define LPCOMP_SHORTS_UP_STOP_Enabled (1UL) /!< Shortcut enabled. /
jamesadevine	0:e1a608bb55e8	2891
jamesadevine	0:e1a608bb55e8	2892	/* Bit 2 : Shortcut between DOWN event and STOP task. */
jamesadevine	0:e1a608bb55e8	2893	#define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL) /!< Position of DOWN_STOP field. /
jamesadevine	0:e1a608bb55e8	2894	#define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos) /!< Bit mask of DOWN_STOP field. /
jamesadevine	0:e1a608bb55e8	2895	#define LPCOMP_SHORTS_DOWN_STOP_Disabled (0UL) /!< Shortcut disabled. /
jamesadevine	0:e1a608bb55e8	2896	#define LPCOMP_SHORTS_DOWN_STOP_Enabled (1UL) /!< Shortcut enabled. /
jamesadevine	0:e1a608bb55e8	2897
jamesadevine	0:e1a608bb55e8	2898	/* Bit 1 : Shortcut between RADY event and STOP task. */
jamesadevine	0:e1a608bb55e8	2899	#define LPCOMP_SHORTS_READY_STOP_Pos (1UL) /!< Position of READY_STOP field. /
jamesadevine	0:e1a608bb55e8	2900	#define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos) /!< Bit mask of READY_STOP field. /
jamesadevine	0:e1a608bb55e8	2901	#define LPCOMP_SHORTS_READY_STOP_Disabled (0UL) /!< Shortcut disabled. /
jamesadevine	0:e1a608bb55e8	2902	#define LPCOMP_SHORTS_READY_STOP_Enabled (1UL) /!< Shortcut enabled. /
jamesadevine	0:e1a608bb55e8	2903
jamesadevine	0:e1a608bb55e8	2904	/* Bit 0 : Shortcut between READY event and SAMPLE task. */
jamesadevine	0:e1a608bb55e8	2905	#define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL) /!< Position of READY_SAMPLE field. /
jamesadevine	0:e1a608bb55e8	2906	#define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos) /!< Bit mask of READY_SAMPLE field. /
jamesadevine	0:e1a608bb55e8	2907	#define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0UL) /!< Shortcut disabled. /
jamesadevine	0:e1a608bb55e8	2908	#define LPCOMP_SHORTS_READY_SAMPLE_Enabled (1UL) /!< Shortcut enabled. /
jamesadevine	0:e1a608bb55e8	2909
jamesadevine	0:e1a608bb55e8	2910	/* Register: LPCOMP_INTENSET */
jamesadevine	0:e1a608bb55e8	2911	/* Description: Interrupt enable set register. */
jamesadevine	0:e1a608bb55e8	2912
jamesadevine	0:e1a608bb55e8	2913	/* Bit 3 : Enable interrupt on CROSS event. */
jamesadevine	0:e1a608bb55e8	2914	#define LPCOMP_INTENSET_CROSS_Pos (3UL) /!< Position of CROSS field. /
jamesadevine	0:e1a608bb55e8	2915	#define LPCOMP_INTENSET_CROSS_Msk (0x1UL << LPCOMP_INTENSET_CROSS_Pos) /!< Bit mask of CROSS field. /
jamesadevine	0:e1a608bb55e8	2916	#define LPCOMP_INTENSET_CROSS_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	2917	#define LPCOMP_INTENSET_CROSS_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	2918	#define LPCOMP_INTENSET_CROSS_Set (1UL) /!< Enable interrupt on write. /
jamesadevine	0:e1a608bb55e8	2919
jamesadevine	0:e1a608bb55e8	2920	/* Bit 2 : Enable interrupt on UP event. */
jamesadevine	0:e1a608bb55e8	2921	#define LPCOMP_INTENSET_UP_Pos (2UL) /!< Position of UP field. /
jamesadevine	0:e1a608bb55e8	2922	#define LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos) /!< Bit mask of UP field. /
jamesadevine	0:e1a608bb55e8	2923	#define LPCOMP_INTENSET_UP_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	2924	#define LPCOMP_INTENSET_UP_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	2925	#define LPCOMP_INTENSET_UP_Set (1UL) /!< Enable interrupt on write. /
jamesadevine	0:e1a608bb55e8	2926
jamesadevine	0:e1a608bb55e8	2927	/* Bit 1 : Enable interrupt on DOWN event. */
jamesadevine	0:e1a608bb55e8	2928	#define LPCOMP_INTENSET_DOWN_Pos (1UL) /!< Position of DOWN field. /
jamesadevine	0:e1a608bb55e8	2929	#define LPCOMP_INTENSET_DOWN_Msk (0x1UL << LPCOMP_INTENSET_DOWN_Pos) /!< Bit mask of DOWN field. /
jamesadevine	0:e1a608bb55e8	2930	#define LPCOMP_INTENSET_DOWN_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	2931	#define LPCOMP_INTENSET_DOWN_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	2932	#define LPCOMP_INTENSET_DOWN_Set (1UL) /!< Enable interrupt on write. /
jamesadevine	0:e1a608bb55e8	2933
jamesadevine	0:e1a608bb55e8	2934	/* Bit 0 : Enable interrupt on READY event. */
jamesadevine	0:e1a608bb55e8	2935	#define LPCOMP_INTENSET_READY_Pos (0UL) /!< Position of READY field. /
jamesadevine	0:e1a608bb55e8	2936	#define LPCOMP_INTENSET_READY_Msk (0x1UL << LPCOMP_INTENSET_READY_Pos) /!< Bit mask of READY field. /
jamesadevine	0:e1a608bb55e8	2937	#define LPCOMP_INTENSET_READY_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	2938	#define LPCOMP_INTENSET_READY_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	2939	#define LPCOMP_INTENSET_READY_Set (1UL) /!< Enable interrupt on write. /
jamesadevine	0:e1a608bb55e8	2940
jamesadevine	0:e1a608bb55e8	2941	/* Register: LPCOMP_INTENCLR */
jamesadevine	0:e1a608bb55e8	2942	/* Description: Interrupt enable clear register. */
jamesadevine	0:e1a608bb55e8	2943
jamesadevine	0:e1a608bb55e8	2944	/* Bit 3 : Disable interrupt on CROSS event. */
jamesadevine	0:e1a608bb55e8	2945	#define LPCOMP_INTENCLR_CROSS_Pos (3UL) /!< Position of CROSS field. /
jamesadevine	0:e1a608bb55e8	2946	#define LPCOMP_INTENCLR_CROSS_Msk (0x1UL << LPCOMP_INTENCLR_CROSS_Pos) /!< Bit mask of CROSS field. /
jamesadevine	0:e1a608bb55e8	2947	#define LPCOMP_INTENCLR_CROSS_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	2948	#define LPCOMP_INTENCLR_CROSS_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	2949	#define LPCOMP_INTENCLR_CROSS_Clear (1UL) /!< Disable interrupt on write. /
jamesadevine	0:e1a608bb55e8	2950
jamesadevine	0:e1a608bb55e8	2951	/* Bit 2 : Disable interrupt on UP event. */
jamesadevine	0:e1a608bb55e8	2952	#define LPCOMP_INTENCLR_UP_Pos (2UL) /!< Position of UP field. /
jamesadevine	0:e1a608bb55e8	2953	#define LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos) /!< Bit mask of UP field. /
jamesadevine	0:e1a608bb55e8	2954	#define LPCOMP_INTENCLR_UP_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	2955	#define LPCOMP_INTENCLR_UP_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	2956	#define LPCOMP_INTENCLR_UP_Clear (1UL) /!< Disable interrupt on write. /
jamesadevine	0:e1a608bb55e8	2957
jamesadevine	0:e1a608bb55e8	2958	/* Bit 1 : Disable interrupt on DOWN event. */
jamesadevine	0:e1a608bb55e8	2959	#define LPCOMP_INTENCLR_DOWN_Pos (1UL) /!< Position of DOWN field. /
jamesadevine	0:e1a608bb55e8	2960	#define LPCOMP_INTENCLR_DOWN_Msk (0x1UL << LPCOMP_INTENCLR_DOWN_Pos) /!< Bit mask of DOWN field. /
jamesadevine	0:e1a608bb55e8	2961	#define LPCOMP_INTENCLR_DOWN_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	2962	#define LPCOMP_INTENCLR_DOWN_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	2963	#define LPCOMP_INTENCLR_DOWN_Clear (1UL) /!< Disable interrupt on write. /
jamesadevine	0:e1a608bb55e8	2964
jamesadevine	0:e1a608bb55e8	2965	/* Bit 0 : Disable interrupt on READY event. */
jamesadevine	0:e1a608bb55e8	2966	#define LPCOMP_INTENCLR_READY_Pos (0UL) /!< Position of READY field. /
jamesadevine	0:e1a608bb55e8	2967	#define LPCOMP_INTENCLR_READY_Msk (0x1UL << LPCOMP_INTENCLR_READY_Pos) /!< Bit mask of READY field. /
jamesadevine	0:e1a608bb55e8	2968	#define LPCOMP_INTENCLR_READY_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	2969	#define LPCOMP_INTENCLR_READY_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	2970	#define LPCOMP_INTENCLR_READY_Clear (1UL) /!< Disable interrupt on write. /
jamesadevine	0:e1a608bb55e8	2971
jamesadevine	0:e1a608bb55e8	2972	/* Register: LPCOMP_RESULT */
jamesadevine	0:e1a608bb55e8	2973	/* Description: Result of last compare. */
jamesadevine	0:e1a608bb55e8	2974
jamesadevine	0:e1a608bb55e8	2975	/* Bit 0 : Result of last compare. Decision point SAMPLE task. */
jamesadevine	0:e1a608bb55e8	2976	#define LPCOMP_RESULT_RESULT_Pos (0UL) /!< Position of RESULT field. /
jamesadevine	0:e1a608bb55e8	2977	#define LPCOMP_RESULT_RESULT_Msk (0x1UL << LPCOMP_RESULT_RESULT_Pos) /!< Bit mask of RESULT field. /
jamesadevine	0:e1a608bb55e8	2978	#define LPCOMP_RESULT_RESULT_Bellow (0UL) /!< Input voltage is bellow the reference threshold. /
jamesadevine	0:e1a608bb55e8	2979	#define LPCOMP_RESULT_RESULT_Above (1UL) /!< Input voltage is above the reference threshold. /
jamesadevine	0:e1a608bb55e8	2980
jamesadevine	0:e1a608bb55e8	2981	/* Register: LPCOMP_ENABLE */
jamesadevine	0:e1a608bb55e8	2982	/* Description: Enable the LPCOMP. */
jamesadevine	0:e1a608bb55e8	2983
jamesadevine	0:e1a608bb55e8	2984	/* Bits 1..0 : Enable or disable LPCOMP. */
jamesadevine	0:e1a608bb55e8	2985	#define LPCOMP_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
jamesadevine	0:e1a608bb55e8	2986	#define LPCOMP_ENABLE_ENABLE_Msk (0x3UL << LPCOMP_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
jamesadevine	0:e1a608bb55e8	2987	#define LPCOMP_ENABLE_ENABLE_Disabled (0x00UL) /!< Disabled LPCOMP. /
jamesadevine	0:e1a608bb55e8	2988	#define LPCOMP_ENABLE_ENABLE_Enabled (0x01UL) /!< Enable LPCOMP. /
jamesadevine	0:e1a608bb55e8	2989
jamesadevine	0:e1a608bb55e8	2990	/* Register: LPCOMP_PSEL */
jamesadevine	0:e1a608bb55e8	2991	/* Description: Input pin select. */
jamesadevine	0:e1a608bb55e8	2992
jamesadevine	0:e1a608bb55e8	2993	/* Bits 2..0 : Analog input pin select. */
jamesadevine	0:e1a608bb55e8	2994	#define LPCOMP_PSEL_PSEL_Pos (0UL) /!< Position of PSEL field. /
jamesadevine	0:e1a608bb55e8	2995	#define LPCOMP_PSEL_PSEL_Msk (0x7UL << LPCOMP_PSEL_PSEL_Pos) /!< Bit mask of PSEL field. /
jamesadevine	0:e1a608bb55e8	2996	#define LPCOMP_PSEL_PSEL_AnalogInput0 (0UL) /!< Use analog input 0 as analog input. /
jamesadevine	0:e1a608bb55e8	2997	#define LPCOMP_PSEL_PSEL_AnalogInput1 (1UL) /!< Use analog input 1 as analog input. /
jamesadevine	0:e1a608bb55e8	2998	#define LPCOMP_PSEL_PSEL_AnalogInput2 (2UL) /!< Use analog input 2 as analog input. /
jamesadevine	0:e1a608bb55e8	2999	#define LPCOMP_PSEL_PSEL_AnalogInput3 (3UL) /!< Use analog input 3 as analog input. /
jamesadevine	0:e1a608bb55e8	3000	#define LPCOMP_PSEL_PSEL_AnalogInput4 (4UL) /!< Use analog input 4 as analog input. /
jamesadevine	0:e1a608bb55e8	3001	#define LPCOMP_PSEL_PSEL_AnalogInput5 (5UL) /!< Use analog input 5 as analog input. /
jamesadevine	0:e1a608bb55e8	3002	#define LPCOMP_PSEL_PSEL_AnalogInput6 (6UL) /!< Use analog input 6 as analog input. /
jamesadevine	0:e1a608bb55e8	3003	#define LPCOMP_PSEL_PSEL_AnalogInput7 (7UL) /!< Use analog input 7 as analog input. /
jamesadevine	0:e1a608bb55e8	3004
jamesadevine	0:e1a608bb55e8	3005	/* Register: LPCOMP_REFSEL */
jamesadevine	0:e1a608bb55e8	3006	/* Description: Reference select. */
jamesadevine	0:e1a608bb55e8	3007
jamesadevine	0:e1a608bb55e8	3008	/* Bits 2..0 : Reference select. */
jamesadevine	0:e1a608bb55e8	3009	#define LPCOMP_REFSEL_REFSEL_Pos (0UL) /!< Position of REFSEL field. /
jamesadevine	0:e1a608bb55e8	3010	#define LPCOMP_REFSEL_REFSEL_Msk (0x7UL << LPCOMP_REFSEL_REFSEL_Pos) /!< Bit mask of REFSEL field. /
jamesadevine	0:e1a608bb55e8	3011	#define LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling (0UL) /!< Use supply with a 1/8 prescaler as reference. /
jamesadevine	0:e1a608bb55e8	3012	#define LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling (1UL) /!< Use supply with a 2/8 prescaler as reference. /
jamesadevine	0:e1a608bb55e8	3013	#define LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling (2UL) /!< Use supply with a 3/8 prescaler as reference. /
jamesadevine	0:e1a608bb55e8	3014	#define LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling (3UL) /!< Use supply with a 4/8 prescaler as reference. /
jamesadevine	0:e1a608bb55e8	3015	#define LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling (4UL) /!< Use supply with a 5/8 prescaler as reference. /
jamesadevine	0:e1a608bb55e8	3016	#define LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling (5UL) /!< Use supply with a 6/8 prescaler as reference. /
jamesadevine	0:e1a608bb55e8	3017	#define LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling (6UL) /!< Use supply with a 7/8 prescaler as reference. /
jamesadevine	0:e1a608bb55e8	3018	#define LPCOMP_REFSEL_REFSEL_ARef (7UL) /!< Use external analog reference as reference. /
jamesadevine	0:e1a608bb55e8	3019
jamesadevine	0:e1a608bb55e8	3020	/* Register: LPCOMP_EXTREFSEL */
jamesadevine	0:e1a608bb55e8	3021	/* Description: External reference select. */
jamesadevine	0:e1a608bb55e8	3022
jamesadevine	0:e1a608bb55e8	3023	/* Bit 0 : External analog reference pin selection. */
jamesadevine	0:e1a608bb55e8	3024	#define LPCOMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /!< Position of EXTREFSEL field. /
jamesadevine	0:e1a608bb55e8	3025	#define LPCOMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << LPCOMP_EXTREFSEL_EXTREFSEL_Pos) /!< Bit mask of EXTREFSEL field. /
jamesadevine	0:e1a608bb55e8	3026	#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /!< Use analog reference 0 as reference. /
jamesadevine	0:e1a608bb55e8	3027	#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /!< Use analog reference 1 as reference. /
jamesadevine	0:e1a608bb55e8	3028
jamesadevine	0:e1a608bb55e8	3029	/* Register: LPCOMP_ANADETECT */
jamesadevine	0:e1a608bb55e8	3030	/* Description: Analog detect configuration. */
jamesadevine	0:e1a608bb55e8	3031
jamesadevine	0:e1a608bb55e8	3032	/* Bits 1..0 : Analog detect configuration. */
jamesadevine	0:e1a608bb55e8	3033	#define LPCOMP_ANADETECT_ANADETECT_Pos (0UL) /!< Position of ANADETECT field. /
jamesadevine	0:e1a608bb55e8	3034	#define LPCOMP_ANADETECT_ANADETECT_Msk (0x3UL << LPCOMP_ANADETECT_ANADETECT_Pos) /!< Bit mask of ANADETECT field. /
jamesadevine	0:e1a608bb55e8	3035	#define LPCOMP_ANADETECT_ANADETECT_Cross (0UL) /!< Generate ANADETEC on crossing, both upwards and downwards crossing. /
jamesadevine	0:e1a608bb55e8	3036	#define LPCOMP_ANADETECT_ANADETECT_Up (1UL) /!< Generate ANADETEC on upwards crossing only. /
jamesadevine	0:e1a608bb55e8	3037	#define LPCOMP_ANADETECT_ANADETECT_Down (2UL) /!< Generate ANADETEC on downwards crossing only. /
jamesadevine	0:e1a608bb55e8	3038
jamesadevine	0:e1a608bb55e8	3039	/* Register: LPCOMP_POWER */
jamesadevine	0:e1a608bb55e8	3040	/* Description: Peripheral power control. */
jamesadevine	0:e1a608bb55e8	3041
jamesadevine	0:e1a608bb55e8	3042	/* Bit 0 : Peripheral power control. */
jamesadevine	0:e1a608bb55e8	3043	#define LPCOMP_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
jamesadevine	0:e1a608bb55e8	3044	#define LPCOMP_POWER_POWER_Msk (0x1UL << LPCOMP_POWER_POWER_Pos) /!< Bit mask of POWER field. /
jamesadevine	0:e1a608bb55e8	3045	#define LPCOMP_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
jamesadevine	0:e1a608bb55e8	3046	#define LPCOMP_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
jamesadevine	0:e1a608bb55e8	3047
jamesadevine	0:e1a608bb55e8	3048
jamesadevine	0:e1a608bb55e8	3049	/* Peripheral: MPU */
jamesadevine	0:e1a608bb55e8	3050	/* Description: Memory Protection Unit. */
jamesadevine	0:e1a608bb55e8	3051
jamesadevine	0:e1a608bb55e8	3052	/* Register: MPU_PERR0 */
jamesadevine	0:e1a608bb55e8	3053	/* Description: Configuration of peripherals in mpu regions. */
jamesadevine	0:e1a608bb55e8	3054
jamesadevine	0:e1a608bb55e8	3055	/* Bit 31 : PPI region configuration. */
jamesadevine	0:e1a608bb55e8	3056	#define MPU_PERR0_PPI_Pos (31UL) /!< Position of PPI field. /
jamesadevine	0:e1a608bb55e8	3057	#define MPU_PERR0_PPI_Msk (0x1UL << MPU_PERR0_PPI_Pos) /!< Bit mask of PPI field. /
jamesadevine	0:e1a608bb55e8	3058	#define MPU_PERR0_PPI_InRegion1 (0UL) /!< Peripheral configured in region 1. /
jamesadevine	0:e1a608bb55e8	3059	#define MPU_PERR0_PPI_InRegion0 (1UL) /!< Peripheral configured in region 0. /
jamesadevine	0:e1a608bb55e8	3060
jamesadevine	0:e1a608bb55e8	3061	/* Bit 30 : NVMC region configuration. */
jamesadevine	0:e1a608bb55e8	3062	#define MPU_PERR0_NVMC_Pos (30UL) /!< Position of NVMC field. /
jamesadevine	0:e1a608bb55e8	3063	#define MPU_PERR0_NVMC_Msk (0x1UL << MPU_PERR0_NVMC_Pos) /!< Bit mask of NVMC field. /
jamesadevine	0:e1a608bb55e8	3064	#define MPU_PERR0_NVMC_InRegion1 (0UL) /!< Peripheral configured in region 1. /
jamesadevine	0:e1a608bb55e8	3065	#define MPU_PERR0_NVMC_InRegion0 (1UL) /!< Peripheral configured in region 0. /
jamesadevine	0:e1a608bb55e8	3066
jamesadevine	0:e1a608bb55e8	3067	/* Bit 19 : LPCOMP region configuration. */
jamesadevine	0:e1a608bb55e8	3068	#define MPU_PERR0_LPCOMP_Pos (19UL) /!< Position of LPCOMP field. /
jamesadevine	0:e1a608bb55e8	3069	#define MPU_PERR0_LPCOMP_Msk (0x1UL << MPU_PERR0_LPCOMP_Pos) /!< Bit mask of LPCOMP field. /
jamesadevine	0:e1a608bb55e8	3070	#define MPU_PERR0_LPCOMP_InRegion1 (0UL) /!< Peripheral configured in region 1. /
jamesadevine	0:e1a608bb55e8	3071	#define MPU_PERR0_LPCOMP_InRegion0 (1UL) /!< Peripheral configured in region 0. /
jamesadevine	0:e1a608bb55e8	3072
jamesadevine	0:e1a608bb55e8	3073	/* Bit 18 : QDEC region configuration. */
jamesadevine	0:e1a608bb55e8	3074	#define MPU_PERR0_QDEC_Pos (18UL) /!< Position of QDEC field. /
jamesadevine	0:e1a608bb55e8	3075	#define MPU_PERR0_QDEC_Msk (0x1UL << MPU_PERR0_QDEC_Pos) /!< Bit mask of QDEC field. /
jamesadevine	0:e1a608bb55e8	3076	#define MPU_PERR0_QDEC_InRegion1 (0UL) /!< Peripheral configured in region 1. /
jamesadevine	0:e1a608bb55e8	3077	#define MPU_PERR0_QDEC_InRegion0 (1UL) /!< Peripheral configured in region 0. /
jamesadevine	0:e1a608bb55e8	3078
jamesadevine	0:e1a608bb55e8	3079	/* Bit 17 : RTC1 region configuration. */
jamesadevine	0:e1a608bb55e8	3080	#define MPU_PERR0_RTC1_Pos (17UL) /!< Position of RTC1 field. /
jamesadevine	0:e1a608bb55e8	3081	#define MPU_PERR0_RTC1_Msk (0x1UL << MPU_PERR0_RTC1_Pos) /!< Bit mask of RTC1 field. /
jamesadevine	0:e1a608bb55e8	3082	#define MPU_PERR0_RTC1_InRegion1 (0UL) /!< Peripheral configured in region 1. /
jamesadevine	0:e1a608bb55e8	3083	#define MPU_PERR0_RTC1_InRegion0 (1UL) /!< Peripheral configured in region 0. /
jamesadevine	0:e1a608bb55e8	3084
jamesadevine	0:e1a608bb55e8	3085	/* Bit 16 : WDT region configuration. */
jamesadevine	0:e1a608bb55e8	3086	#define MPU_PERR0_WDT_Pos (16UL) /!< Position of WDT field. /
jamesadevine	0:e1a608bb55e8	3087	#define MPU_PERR0_WDT_Msk (0x1UL << MPU_PERR0_WDT_Pos) /!< Bit mask of WDT field. /
jamesadevine	0:e1a608bb55e8	3088	#define MPU_PERR0_WDT_InRegion1 (0UL) /!< Peripheral configured in region 1. /
jamesadevine	0:e1a608bb55e8	3089	#define MPU_PERR0_WDT_InRegion0 (1UL) /!< Peripheral configured in region 0. /
jamesadevine	0:e1a608bb55e8	3090
jamesadevine	0:e1a608bb55e8	3091	/* Bit 15 : CCM and AAR region configuration. */
jamesadevine	0:e1a608bb55e8	3092	#define MPU_PERR0_CCM_AAR_Pos (15UL) /!< Position of CCM_AAR field. /
jamesadevine	0:e1a608bb55e8	3093	#define MPU_PERR0_CCM_AAR_Msk (0x1UL << MPU_PERR0_CCM_AAR_Pos) /!< Bit mask of CCM_AAR field. /
jamesadevine	0:e1a608bb55e8	3094	#define MPU_PERR0_CCM_AAR_InRegion1 (0UL) /!< Peripheral configured in region 1. /
jamesadevine	0:e1a608bb55e8	3095	#define MPU_PERR0_CCM_AAR_InRegion0 (1UL) /!< Peripheral configured in region 0. /
jamesadevine	0:e1a608bb55e8	3096
jamesadevine	0:e1a608bb55e8	3097	/* Bit 14 : ECB region configuration. */
jamesadevine	0:e1a608bb55e8	3098	#define MPU_PERR0_ECB_Pos (14UL) /!< Position of ECB field. /
jamesadevine	0:e1a608bb55e8	3099	#define MPU_PERR0_ECB_Msk (0x1UL << MPU_PERR0_ECB_Pos) /!< Bit mask of ECB field. /
jamesadevine	0:e1a608bb55e8	3100	#define MPU_PERR0_ECB_InRegion1 (0UL) /!< Peripheral configured in region 1. /
jamesadevine	0:e1a608bb55e8	3101	#define MPU_PERR0_ECB_InRegion0 (1UL) /!< Peripheral configured in region 0. /
jamesadevine	0:e1a608bb55e8	3102
jamesadevine	0:e1a608bb55e8	3103	/* Bit 13 : RNG region configuration. */
jamesadevine	0:e1a608bb55e8	3104	#define MPU_PERR0_RNG_Pos (13UL) /!< Position of RNG field. /
jamesadevine	0:e1a608bb55e8	3105	#define MPU_PERR0_RNG_Msk (0x1UL << MPU_PERR0_RNG_Pos) /!< Bit mask of RNG field. /
jamesadevine	0:e1a608bb55e8	3106	#define MPU_PERR0_RNG_InRegion1 (0UL) /!< Peripheral configured in region 1. /
jamesadevine	0:e1a608bb55e8	3107	#define MPU_PERR0_RNG_InRegion0 (1UL) /!< Peripheral configured in region 0. /
jamesadevine	0:e1a608bb55e8	3108
jamesadevine	0:e1a608bb55e8	3109	/* Bit 12 : TEMP region configuration. */
jamesadevine	0:e1a608bb55e8	3110	#define MPU_PERR0_TEMP_Pos (12UL) /!< Position of TEMP field. /
jamesadevine	0:e1a608bb55e8	3111	#define MPU_PERR0_TEMP_Msk (0x1UL << MPU_PERR0_TEMP_Pos) /!< Bit mask of TEMP field. /
jamesadevine	0:e1a608bb55e8	3112	#define MPU_PERR0_TEMP_InRegion1 (0UL) /!< Peripheral configured in region 1. /
jamesadevine	0:e1a608bb55e8	3113	#define MPU_PERR0_TEMP_InRegion0 (1UL) /!< Peripheral configured in region 0. /
jamesadevine	0:e1a608bb55e8	3114
jamesadevine	0:e1a608bb55e8	3115	/* Bit 11 : RTC0 region configuration. */
jamesadevine	0:e1a608bb55e8	3116	#define MPU_PERR0_RTC0_Pos (11UL) /!< Position of RTC0 field. /
jamesadevine	0:e1a608bb55e8	3117	#define MPU_PERR0_RTC0_Msk (0x1UL << MPU_PERR0_RTC0_Pos) /!< Bit mask of RTC0 field. /
jamesadevine	0:e1a608bb55e8	3118	#define MPU_PERR0_RTC0_InRegion1 (0UL) /!< Peripheral configured in region 1. /
jamesadevine	0:e1a608bb55e8	3119	#define MPU_PERR0_RTC0_InRegion0 (1UL) /!< Peripheral configured in region 0. /
jamesadevine	0:e1a608bb55e8	3120
jamesadevine	0:e1a608bb55e8	3121	/* Bit 10 : TIMER2 region configuration. */
jamesadevine	0:e1a608bb55e8	3122	#define MPU_PERR0_TIMER2_Pos (10UL) /!< Position of TIMER2 field. /
jamesadevine	0:e1a608bb55e8	3123	#define MPU_PERR0_TIMER2_Msk (0x1UL << MPU_PERR0_TIMER2_Pos) /!< Bit mask of TIMER2 field. /
jamesadevine	0:e1a608bb55e8	3124	#define MPU_PERR0_TIMER2_InRegion1 (0UL) /!< Peripheral configured in region 1. /
jamesadevine	0:e1a608bb55e8	3125	#define MPU_PERR0_TIMER2_InRegion0 (1UL) /!< Peripheral configured in region 0. /
jamesadevine	0:e1a608bb55e8	3126
jamesadevine	0:e1a608bb55e8	3127	/* Bit 9 : TIMER1 region configuration. */
jamesadevine	0:e1a608bb55e8	3128	#define MPU_PERR0_TIMER1_Pos (9UL) /!< Position of TIMER1 field. /
jamesadevine	0:e1a608bb55e8	3129	#define MPU_PERR0_TIMER1_Msk (0x1UL << MPU_PERR0_TIMER1_Pos) /!< Bit mask of TIMER1 field. /
jamesadevine	0:e1a608bb55e8	3130	#define MPU_PERR0_TIMER1_InRegion1 (0UL) /!< Peripheral configured in region 1. /
jamesadevine	0:e1a608bb55e8	3131	#define MPU_PERR0_TIMER1_InRegion0 (1UL) /!< Peripheral configured in region 0. /
jamesadevine	0:e1a608bb55e8	3132
jamesadevine	0:e1a608bb55e8	3133	/* Bit 8 : TIMER0 region configuration. */
jamesadevine	0:e1a608bb55e8	3134	#define MPU_PERR0_TIMER0_Pos (8UL) /!< Position of TIMER0 field. /
jamesadevine	0:e1a608bb55e8	3135	#define MPU_PERR0_TIMER0_Msk (0x1UL << MPU_PERR0_TIMER0_Pos) /!< Bit mask of TIMER0 field. /
jamesadevine	0:e1a608bb55e8	3136	#define MPU_PERR0_TIMER0_InRegion1 (0UL) /!< Peripheral configured in region 1. /
jamesadevine	0:e1a608bb55e8	3137	#define MPU_PERR0_TIMER0_InRegion0 (1UL) /!< Peripheral configured in region 0. /
jamesadevine	0:e1a608bb55e8	3138
jamesadevine	0:e1a608bb55e8	3139	/* Bit 7 : ADC region configuration. */
jamesadevine	0:e1a608bb55e8	3140	#define MPU_PERR0_ADC_Pos (7UL) /!< Position of ADC field. /
jamesadevine	0:e1a608bb55e8	3141	#define MPU_PERR0_ADC_Msk (0x1UL << MPU_PERR0_ADC_Pos) /!< Bit mask of ADC field. /
jamesadevine	0:e1a608bb55e8	3142	#define MPU_PERR0_ADC_InRegion1 (0UL) /!< Peripheral configured in region 1. /
jamesadevine	0:e1a608bb55e8	3143	#define MPU_PERR0_ADC_InRegion0 (1UL) /!< Peripheral configured in region 0. /
jamesadevine	0:e1a608bb55e8	3144
jamesadevine	0:e1a608bb55e8	3145	/* Bit 6 : GPIOTE region configuration. */
jamesadevine	0:e1a608bb55e8	3146	#define MPU_PERR0_GPIOTE_Pos (6UL) /!< Position of GPIOTE field. /
jamesadevine	0:e1a608bb55e8	3147	#define MPU_PERR0_GPIOTE_Msk (0x1UL << MPU_PERR0_GPIOTE_Pos) /!< Bit mask of GPIOTE field. /
jamesadevine	0:e1a608bb55e8	3148	#define MPU_PERR0_GPIOTE_InRegion1 (0UL) /!< Peripheral configured in region 1. /
jamesadevine	0:e1a608bb55e8	3149	#define MPU_PERR0_GPIOTE_InRegion0 (1UL) /!< Peripheral configured in region 0. /
jamesadevine	0:e1a608bb55e8	3150
jamesadevine	0:e1a608bb55e8	3151	/* Bit 4 : SPI1 and TWI1 region configuration. */
jamesadevine	0:e1a608bb55e8	3152	#define MPU_PERR0_SPI1_TWI1_Pos (4UL) /!< Position of SPI1_TWI1 field. /
jamesadevine	0:e1a608bb55e8	3153	#define MPU_PERR0_SPI1_TWI1_Msk (0x1UL << MPU_PERR0_SPI1_TWI1_Pos) /!< Bit mask of SPI1_TWI1 field. /
jamesadevine	0:e1a608bb55e8	3154	#define MPU_PERR0_SPI1_TWI1_InRegion1 (0UL) /!< Peripheral configured in region 1. /
jamesadevine	0:e1a608bb55e8	3155	#define MPU_PERR0_SPI1_TWI1_InRegion0 (1UL) /!< Peripheral configured in region 0. /
jamesadevine	0:e1a608bb55e8	3156
jamesadevine	0:e1a608bb55e8	3157	/* Bit 3 : SPI0 and TWI0 region configuration. */
jamesadevine	0:e1a608bb55e8	3158	#define MPU_PERR0_SPI0_TWI0_Pos (3UL) /!< Position of SPI0_TWI0 field. /
jamesadevine	0:e1a608bb55e8	3159	#define MPU_PERR0_SPI0_TWI0_Msk (0x1UL << MPU_PERR0_SPI0_TWI0_Pos) /!< Bit mask of SPI0_TWI0 field. /
jamesadevine	0:e1a608bb55e8	3160	#define MPU_PERR0_SPI0_TWI0_InRegion1 (0UL) /!< Peripheral configured in region 1. /
jamesadevine	0:e1a608bb55e8	3161	#define MPU_PERR0_SPI0_TWI0_InRegion0 (1UL) /!< Peripheral configured in region 0. /
jamesadevine	0:e1a608bb55e8	3162
jamesadevine	0:e1a608bb55e8	3163	/* Bit 2 : UART0 region configuration. */
jamesadevine	0:e1a608bb55e8	3164	#define MPU_PERR0_UART0_Pos (2UL) /!< Position of UART0 field. /
jamesadevine	0:e1a608bb55e8	3165	#define MPU_PERR0_UART0_Msk (0x1UL << MPU_PERR0_UART0_Pos) /!< Bit mask of UART0 field. /
jamesadevine	0:e1a608bb55e8	3166	#define MPU_PERR0_UART0_InRegion1 (0UL) /!< Peripheral configured in region 1. /
jamesadevine	0:e1a608bb55e8	3167	#define MPU_PERR0_UART0_InRegion0 (1UL) /!< Peripheral configured in region 0. /
jamesadevine	0:e1a608bb55e8	3168
jamesadevine	0:e1a608bb55e8	3169	/* Bit 1 : RADIO region configuration. */
jamesadevine	0:e1a608bb55e8	3170	#define MPU_PERR0_RADIO_Pos (1UL) /!< Position of RADIO field. /
jamesadevine	0:e1a608bb55e8	3171	#define MPU_PERR0_RADIO_Msk (0x1UL << MPU_PERR0_RADIO_Pos) /!< Bit mask of RADIO field. /
jamesadevine	0:e1a608bb55e8	3172	#define MPU_PERR0_RADIO_InRegion1 (0UL) /!< Peripheral configured in region 1. /
jamesadevine	0:e1a608bb55e8	3173	#define MPU_PERR0_RADIO_InRegion0 (1UL) /!< Peripheral configured in region 0. /
jamesadevine	0:e1a608bb55e8	3174
jamesadevine	0:e1a608bb55e8	3175	/* Bit 0 : POWER_CLOCK region configuration. */
jamesadevine	0:e1a608bb55e8	3176	#define MPU_PERR0_POWER_CLOCK_Pos (0UL) /!< Position of POWER_CLOCK field. /
jamesadevine	0:e1a608bb55e8	3177	#define MPU_PERR0_POWER_CLOCK_Msk (0x1UL << MPU_PERR0_POWER_CLOCK_Pos) /!< Bit mask of POWER_CLOCK field. /
jamesadevine	0:e1a608bb55e8	3178	#define MPU_PERR0_POWER_CLOCK_InRegion1 (0UL) /!< Peripheral configured in region 1. /
jamesadevine	0:e1a608bb55e8	3179	#define MPU_PERR0_POWER_CLOCK_InRegion0 (1UL) /!< Peripheral configured in region 0. /
jamesadevine	0:e1a608bb55e8	3180
jamesadevine	0:e1a608bb55e8	3181	/* Register: MPU_PROTENSET0 */
jamesadevine	0:e1a608bb55e8	3182	/* Description: Erase and write protection bit enable set register. */
jamesadevine	0:e1a608bb55e8	3183
jamesadevine	0:e1a608bb55e8	3184	/* Bit 31 : Protection enable for region 31. */
jamesadevine	0:e1a608bb55e8	3185	#define MPU_PROTENSET0_PROTREG31_Pos (31UL) /!< Position of PROTREG31 field. /
jamesadevine	0:e1a608bb55e8	3186	#define MPU_PROTENSET0_PROTREG31_Msk (0x1UL << MPU_PROTENSET0_PROTREG31_Pos) /!< Bit mask of PROTREG31 field. /
jamesadevine	0:e1a608bb55e8	3187	#define MPU_PROTENSET0_PROTREG31_Disabled (0UL) /!< Protection disabled. /
jamesadevine	0:e1a608bb55e8	3188	#define MPU_PROTENSET0_PROTREG31_Enabled (1UL) /!< Protection enabled. /
jamesadevine	0:e1a608bb55e8	3189	#define MPU_PROTENSET0_PROTREG31_Set (1UL) /!< Enable protection on write. /
jamesadevine	0:e1a608bb55e8	3190
jamesadevine	0:e1a608bb55e8	3191	/* Bit 30 : Protection enable for region 30. */
jamesadevine	0:e1a608bb55e8	3192	#define MPU_PROTENSET0_PROTREG30_Pos (30UL) /!< Position of PROTREG30 field. /
jamesadevine	0:e1a608bb55e8	3193	#define MPU_PROTENSET0_PROTREG30_Msk (0x1UL << MPU_PROTENSET0_PROTREG30_Pos) /!< Bit mask of PROTREG30 field. /
jamesadevine	0:e1a608bb55e8	3194	#define MPU_PROTENSET0_PROTREG30_Disabled (0UL) /!< Protection disabled. /
jamesadevine	0:e1a608bb55e8	3195	#define MPU_PROTENSET0_PROTREG30_Enabled (1UL) /!< Protection enabled. /
jamesadevine	0:e1a608bb55e8	3196	#define MPU_PROTENSET0_PROTREG30_Set (1UL) /!< Enable protection on write. /
jamesadevine	0:e1a608bb55e8	3197
jamesadevine	0:e1a608bb55e8	3198	/* Bit 29 : Protection enable for region 29. */
jamesadevine	0:e1a608bb55e8	3199	#define MPU_PROTENSET0_PROTREG29_Pos (29UL) /!< Position of PROTREG29 field. /
jamesadevine	0:e1a608bb55e8	3200	#define MPU_PROTENSET0_PROTREG29_Msk (0x1UL << MPU_PROTENSET0_PROTREG29_Pos) /!< Bit mask of PROTREG29 field. /
jamesadevine	0:e1a608bb55e8	3201	#define MPU_PROTENSET0_PROTREG29_Disabled (0UL) /!< Protection disabled. /
jamesadevine	0:e1a608bb55e8	3202	#define MPU_PROTENSET0_PROTREG29_Enabled (1UL) /!< Protection enabled. /
jamesadevine	0:e1a608bb55e8	3203	#define MPU_PROTENSET0_PROTREG29_Set (1UL) /!< Enable protection on write. /
jamesadevine	0:e1a608bb55e8	3204
jamesadevine	0:e1a608bb55e8	3205	/* Bit 28 : Protection enable for region 28. */
jamesadevine	0:e1a608bb55e8	3206	#define MPU_PROTENSET0_PROTREG28_Pos (28UL) /!< Position of PROTREG28 field. /
jamesadevine	0:e1a608bb55e8	3207	#define MPU_PROTENSET0_PROTREG28_Msk (0x1UL << MPU_PROTENSET0_PROTREG28_Pos) /!< Bit mask of PROTREG28 field. /
jamesadevine	0:e1a608bb55e8	3208	#define MPU_PROTENSET0_PROTREG28_Disabled (0UL) /!< Protection disabled. /
jamesadevine	0:e1a608bb55e8	3209	#define MPU_PROTENSET0_PROTREG28_Enabled (1UL) /!< Protection enabled. /
jamesadevine	0:e1a608bb55e8	3210	#define MPU_PROTENSET0_PROTREG28_Set (1UL) /!< Enable protection on write. /
jamesadevine	0:e1a608bb55e8	3211
jamesadevine	0:e1a608bb55e8	3212	/* Bit 27 : Protection enable for region 27. */
jamesadevine	0:e1a608bb55e8	3213	#define MPU_PROTENSET0_PROTREG27_Pos (27UL) /!< Position of PROTREG27 field. /
jamesadevine	0:e1a608bb55e8	3214	#define MPU_PROTENSET0_PROTREG27_Msk (0x1UL << MPU_PROTENSET0_PROTREG27_Pos) /!< Bit mask of PROTREG27 field. /
jamesadevine	0:e1a608bb55e8	3215	#define MPU_PROTENSET0_PROTREG27_Disabled (0UL) /!< Protection disabled. /
jamesadevine	0:e1a608bb55e8	3216	#define MPU_PROTENSET0_PROTREG27_Enabled (1UL) /!< Protection enabled. /
jamesadevine	0:e1a608bb55e8	3217	#define MPU_PROTENSET0_PROTREG27_Set (1UL) /!< Enable protection on write. /
jamesadevine	0:e1a608bb55e8	3218
jamesadevine	0:e1a608bb55e8	3219	/* Bit 26 : Protection enable for region 26. */
jamesadevine	0:e1a608bb55e8	3220	#define MPU_PROTENSET0_PROTREG26_Pos (26UL) /!< Position of PROTREG26 field. /
jamesadevine	0:e1a608bb55e8	3221	#define MPU_PROTENSET0_PROTREG26_Msk (0x1UL << MPU_PROTENSET0_PROTREG26_Pos) /!< Bit mask of PROTREG26 field. /
jamesadevine	0:e1a608bb55e8	3222	#define MPU_PROTENSET0_PROTREG26_Disabled (0UL) /!< Protection disabled. /
jamesadevine	0:e1a608bb55e8	3223	#define MPU_PROTENSET0_PROTREG26_Enabled (1UL) /!< Protection enabled. /
jamesadevine	0:e1a608bb55e8	3224	#define MPU_PROTENSET0_PROTREG26_Set (1UL) /!< Enable protection on write. /
jamesadevine	0:e1a608bb55e8	3225
jamesadevine	0:e1a608bb55e8	3226	/* Bit 25 : Protection enable for region 25. */
jamesadevine	0:e1a608bb55e8	3227	#define MPU_PROTENSET0_PROTREG25_Pos (25UL) /!< Position of PROTREG25 field. /
jamesadevine	0:e1a608bb55e8	3228	#define MPU_PROTENSET0_PROTREG25_Msk (0x1UL << MPU_PROTENSET0_PROTREG25_Pos) /!< Bit mask of PROTREG25 field. /
jamesadevine	0:e1a608bb55e8	3229	#define MPU_PROTENSET0_PROTREG25_Disabled (0UL) /!< Protection disabled. /
jamesadevine	0:e1a608bb55e8	3230	#define MPU_PROTENSET0_PROTREG25_Enabled (1UL) /!< Protection enabled. /
jamesadevine	0:e1a608bb55e8	3231	#define MPU_PROTENSET0_PROTREG25_Set (1UL) /!< Enable protection on write. /
jamesadevine	0:e1a608bb55e8	3232
jamesadevine	0:e1a608bb55e8	3233	/* Bit 24 : Protection enable for region 24. */
jamesadevine	0:e1a608bb55e8	3234	#define MPU_PROTENSET0_PROTREG24_Pos (24UL) /!< Position of PROTREG24 field. /
jamesadevine	0:e1a608bb55e8	3235	#define MPU_PROTENSET0_PROTREG24_Msk (0x1UL << MPU_PROTENSET0_PROTREG24_Pos) /!< Bit mask of PROTREG24 field. /
jamesadevine	0:e1a608bb55e8	3236	#define MPU_PROTENSET0_PROTREG24_Disabled (0UL) /!< Protection disabled. /
jamesadevine	0:e1a608bb55e8	3237	#define MPU_PROTENSET0_PROTREG24_Enabled (1UL) /!< Protection enabled. /
jamesadevine	0:e1a608bb55e8	3238	#define MPU_PROTENSET0_PROTREG24_Set (1UL) /!< Enable protection on write. /
jamesadevine	0:e1a608bb55e8	3239
jamesadevine	0:e1a608bb55e8	3240	/* Bit 23 : Protection enable for region 23. */
jamesadevine	0:e1a608bb55e8	3241	#define MPU_PROTENSET0_PROTREG23_Pos (23UL) /!< Position of PROTREG23 field. /
jamesadevine	0:e1a608bb55e8	3242	#define MPU_PROTENSET0_PROTREG23_Msk (0x1UL << MPU_PROTENSET0_PROTREG23_Pos) /!< Bit mask of PROTREG23 field. /
jamesadevine	0:e1a608bb55e8	3243	#define MPU_PROTENSET0_PROTREG23_Disabled (0UL) /!< Protection disabled. /
jamesadevine	0:e1a608bb55e8	3244	#define MPU_PROTENSET0_PROTREG23_Enabled (1UL) /!< Protection enabled. /
jamesadevine	0:e1a608bb55e8	3245	#define MPU_PROTENSET0_PROTREG23_Set (1UL) /!< Enable protection on write. /
jamesadevine	0:e1a608bb55e8	3246
jamesadevine	0:e1a608bb55e8	3247	/* Bit 22 : Protection enable for region 22. */
jamesadevine	0:e1a608bb55e8	3248	#define MPU_PROTENSET0_PROTREG22_Pos (22UL) /!< Position of PROTREG22 field. /
jamesadevine	0:e1a608bb55e8	3249	#define MPU_PROTENSET0_PROTREG22_Msk (0x1UL << MPU_PROTENSET0_PROTREG22_Pos) /!< Bit mask of PROTREG22 field. /
jamesadevine	0:e1a608bb55e8	3250	#define MPU_PROTENSET0_PROTREG22_Disabled (0UL) /!< Protection disabled. /
jamesadevine	0:e1a608bb55e8	3251	#define MPU_PROTENSET0_PROTREG22_Enabled (1UL) /!< Protection enabled. /
jamesadevine	0:e1a608bb55e8	3252	#define MPU_PROTENSET0_PROTREG22_Set (1UL) /!< Enable protection on write. /
jamesadevine	0:e1a608bb55e8	3253
jamesadevine	0:e1a608bb55e8	3254	/* Bit 21 : Protection enable for region 21. */
jamesadevine	0:e1a608bb55e8	3255	#define MPU_PROTENSET0_PROTREG21_Pos (21UL) /!< Position of PROTREG21 field. /
jamesadevine	0:e1a608bb55e8	3256	#define MPU_PROTENSET0_PROTREG21_Msk (0x1UL << MPU_PROTENSET0_PROTREG21_Pos) /!< Bit mask of PROTREG21 field. /
jamesadevine	0:e1a608bb55e8	3257	#define MPU_PROTENSET0_PROTREG21_Disabled (0UL) /!< Protection disabled. /
jamesadevine	0:e1a608bb55e8	3258	#define MPU_PROTENSET0_PROTREG21_Enabled (1UL) /!< Protection enabled. /
jamesadevine	0:e1a608bb55e8	3259	#define MPU_PROTENSET0_PROTREG21_Set (1UL) /!< Enable protection on write. /
jamesadevine	0:e1a608bb55e8	3260
jamesadevine	0:e1a608bb55e8	3261	/* Bit 20 : Protection enable for region 20. */
jamesadevine	0:e1a608bb55e8	3262	#define MPU_PROTENSET0_PROTREG20_Pos (20UL) /!< Position of PROTREG20 field. /
jamesadevine	0:e1a608bb55e8	3263	#define MPU_PROTENSET0_PROTREG20_Msk (0x1UL << MPU_PROTENSET0_PROTREG20_Pos) /!< Bit mask of PROTREG20 field. /
jamesadevine	0:e1a608bb55e8	3264	#define MPU_PROTENSET0_PROTREG20_Disabled (0UL) /!< Protection disabled. /
jamesadevine	0:e1a608bb55e8	3265	#define MPU_PROTENSET0_PROTREG20_Enabled (1UL) /!< Protection enabled. /
jamesadevine	0:e1a608bb55e8	3266	#define MPU_PROTENSET0_PROTREG20_Set (1UL) /!< Enable protection on write. /
jamesadevine	0:e1a608bb55e8	3267
jamesadevine	0:e1a608bb55e8	3268	/* Bit 19 : Protection enable for region 19. */
jamesadevine	0:e1a608bb55e8	3269	#define MPU_PROTENSET0_PROTREG19_Pos (19UL) /!< Position of PROTREG19 field. /
jamesadevine	0:e1a608bb55e8	3270	#define MPU_PROTENSET0_PROTREG19_Msk (0x1UL << MPU_PROTENSET0_PROTREG19_Pos) /!< Bit mask of PROTREG19 field. /
jamesadevine	0:e1a608bb55e8	3271	#define MPU_PROTENSET0_PROTREG19_Disabled (0UL) /!< Protection disabled. /
jamesadevine	0:e1a608bb55e8	3272	#define MPU_PROTENSET0_PROTREG19_Enabled (1UL) /!< Protection enabled. /
jamesadevine	0:e1a608bb55e8	3273	#define MPU_PROTENSET0_PROTREG19_Set (1UL) /!< Enable protection on write. /
jamesadevine	0:e1a608bb55e8	3274
jamesadevine	0:e1a608bb55e8	3275	/* Bit 18 : Protection enable for region 18. */
jamesadevine	0:e1a608bb55e8	3276	#define MPU_PROTENSET0_PROTREG18_Pos (18UL) /!< Position of PROTREG18 field. /
jamesadevine	0:e1a608bb55e8	3277	#define MPU_PROTENSET0_PROTREG18_Msk (0x1UL << MPU_PROTENSET0_PROTREG18_Pos) /!< Bit mask of PROTREG18 field. /
jamesadevine	0:e1a608bb55e8	3278	#define MPU_PROTENSET0_PROTREG18_Disabled (0UL) /!< Protection disabled. /
jamesadevine	0:e1a608bb55e8	3279	#define MPU_PROTENSET0_PROTREG18_Enabled (1UL) /!< Protection enabled. /
jamesadevine	0:e1a608bb55e8	3280	#define MPU_PROTENSET0_PROTREG18_Set (1UL) /!< Enable protection on write. /
jamesadevine	0:e1a608bb55e8	3281
jamesadevine	0:e1a608bb55e8	3282	/* Bit 17 : Protection enable for region 17. */
jamesadevine	0:e1a608bb55e8	3283	#define MPU_PROTENSET0_PROTREG17_Pos (17UL) /!< Position of PROTREG17 field. /
jamesadevine	0:e1a608bb55e8	3284	#define MPU_PROTENSET0_PROTREG17_Msk (0x1UL << MPU_PROTENSET0_PROTREG17_Pos) /!< Bit mask of PROTREG17 field. /
jamesadevine	0:e1a608bb55e8	3285	#define MPU_PROTENSET0_PROTREG17_Disabled (0UL) /!< Protection disabled. /
jamesadevine	0:e1a608bb55e8	3286	#define MPU_PROTENSET0_PROTREG17_Enabled (1UL) /!< Protection enabled. /
jamesadevine	0:e1a608bb55e8	3287	#define MPU_PROTENSET0_PROTREG17_Set (1UL) /!< Enable protection on write. /
jamesadevine	0:e1a608bb55e8	3288
jamesadevine	0:e1a608bb55e8	3289	/* Bit 16 : Protection enable for region 16. */
jamesadevine	0:e1a608bb55e8	3290	#define MPU_PROTENSET0_PROTREG16_Pos (16UL) /!< Position of PROTREG16 field. /
jamesadevine	0:e1a608bb55e8	3291	#define MPU_PROTENSET0_PROTREG16_Msk (0x1UL << MPU_PROTENSET0_PROTREG16_Pos) /!< Bit mask of PROTREG16 field. /
jamesadevine	0:e1a608bb55e8	3292	#define MPU_PROTENSET0_PROTREG16_Disabled (0UL) /!< Protection disabled. /
jamesadevine	0:e1a608bb55e8	3293	#define MPU_PROTENSET0_PROTREG16_Enabled (1UL) /!< Protection enabled. /
jamesadevine	0:e1a608bb55e8	3294	#define MPU_PROTENSET0_PROTREG16_Set (1UL) /!< Enable protection on write. /
jamesadevine	0:e1a608bb55e8	3295
jamesadevine	0:e1a608bb55e8	3296	/* Bit 15 : Protection enable for region 15. */
jamesadevine	0:e1a608bb55e8	3297	#define MPU_PROTENSET0_PROTREG15_Pos (15UL) /!< Position of PROTREG15 field. /
jamesadevine	0:e1a608bb55e8	3298	#define MPU_PROTENSET0_PROTREG15_Msk (0x1UL << MPU_PROTENSET0_PROTREG15_Pos) /!< Bit mask of PROTREG15 field. /
jamesadevine	0:e1a608bb55e8	3299	#define MPU_PROTENSET0_PROTREG15_Disabled (0UL) /!< Protection disabled. /
jamesadevine	0:e1a608bb55e8	3300	#define MPU_PROTENSET0_PROTREG15_Enabled (1UL) /!< Protection enabled. /
jamesadevine	0:e1a608bb55e8	3301	#define MPU_PROTENSET0_PROTREG15_Set (1UL) /!< Enable protection on write. /
jamesadevine	0:e1a608bb55e8	3302
jamesadevine	0:e1a608bb55e8	3303	/* Bit 14 : Protection enable for region 14. */
jamesadevine	0:e1a608bb55e8	3304	#define MPU_PROTENSET0_PROTREG14_Pos (14UL) /!< Position of PROTREG14 field. /
jamesadevine	0:e1a608bb55e8	3305	#define MPU_PROTENSET0_PROTREG14_Msk (0x1UL << MPU_PROTENSET0_PROTREG14_Pos) /!< Bit mask of PROTREG14 field. /
jamesadevine	0:e1a608bb55e8	3306	#define MPU_PROTENSET0_PROTREG14_Disabled (0UL) /!< Protection disabled. /
jamesadevine	0:e1a608bb55e8	3307	#define MPU_PROTENSET0_PROTREG14_Enabled (1UL) /!< Protection enabled. /
jamesadevine	0:e1a608bb55e8	3308	#define MPU_PROTENSET0_PROTREG14_Set (1UL) /!< Enable protection on write. /
jamesadevine	0:e1a608bb55e8	3309
jamesadevine	0:e1a608bb55e8	3310	/* Bit 13 : Protection enable for region 13. */
jamesadevine	0:e1a608bb55e8	3311	#define MPU_PROTENSET0_PROTREG13_Pos (13UL) /!< Position of PROTREG13 field. /
jamesadevine	0:e1a608bb55e8	3312	#define MPU_PROTENSET0_PROTREG13_Msk (0x1UL << MPU_PROTENSET0_PROTREG13_Pos) /!< Bit mask of PROTREG13 field. /
jamesadevine	0:e1a608bb55e8	3313	#define MPU_PROTENSET0_PROTREG13_Disabled (0UL) /!< Protection disabled. /
jamesadevine	0:e1a608bb55e8	3314	#define MPU_PROTENSET0_PROTREG13_Enabled (1UL) /!< Protection enabled. /
jamesadevine	0:e1a608bb55e8	3315	#define MPU_PROTENSET0_PROTREG13_Set (1UL) /!< Enable protection on write. /
jamesadevine	0:e1a608bb55e8	3316
jamesadevine	0:e1a608bb55e8	3317	/* Bit 12 : Protection enable for region 12. */
jamesadevine	0:e1a608bb55e8	3318	#define MPU_PROTENSET0_PROTREG12_Pos (12UL) /!< Position of PROTREG12 field. /
jamesadevine	0:e1a608bb55e8	3319	#define MPU_PROTENSET0_PROTREG12_Msk (0x1UL << MPU_PROTENSET0_PROTREG12_Pos) /!< Bit mask of PROTREG12 field. /
jamesadevine	0:e1a608bb55e8	3320	#define MPU_PROTENSET0_PROTREG12_Disabled (0UL) /!< Protection disabled. /
jamesadevine	0:e1a608bb55e8	3321	#define MPU_PROTENSET0_PROTREG12_Enabled (1UL) /!< Protection enabled. /
jamesadevine	0:e1a608bb55e8	3322	#define MPU_PROTENSET0_PROTREG12_Set (1UL) /!< Enable protection on write. /
jamesadevine	0:e1a608bb55e8	3323
jamesadevine	0:e1a608bb55e8	3324	/* Bit 11 : Protection enable for region 11. */
jamesadevine	0:e1a608bb55e8	3325	#define MPU_PROTENSET0_PROTREG11_Pos (11UL) /!< Position of PROTREG11 field. /
jamesadevine	0:e1a608bb55e8	3326	#define MPU_PROTENSET0_PROTREG11_Msk (0x1UL << MPU_PROTENSET0_PROTREG11_Pos) /!< Bit mask of PROTREG11 field. /
jamesadevine	0:e1a608bb55e8	3327	#define MPU_PROTENSET0_PROTREG11_Disabled (0UL) /!< Protection disabled. /
jamesadevine	0:e1a608bb55e8	3328	#define MPU_PROTENSET0_PROTREG11_Enabled (1UL) /!< Protection enabled. /
jamesadevine	0:e1a608bb55e8	3329	#define MPU_PROTENSET0_PROTREG11_Set (1UL) /!< Enable protection on write. /
jamesadevine	0:e1a608bb55e8	3330
jamesadevine	0:e1a608bb55e8	3331	/* Bit 10 : Protection enable for region 10. */
jamesadevine	0:e1a608bb55e8	3332	#define MPU_PROTENSET0_PROTREG10_Pos (10UL) /!< Position of PROTREG10 field. /
jamesadevine	0:e1a608bb55e8	3333	#define MPU_PROTENSET0_PROTREG10_Msk (0x1UL << MPU_PROTENSET0_PROTREG10_Pos) /!< Bit mask of PROTREG10 field. /
jamesadevine	0:e1a608bb55e8	3334	#define MPU_PROTENSET0_PROTREG10_Disabled (0UL) /!< Protection disabled. /
jamesadevine	0:e1a608bb55e8	3335	#define MPU_PROTENSET0_PROTREG10_Enabled (1UL) /!< Protection enabled. /
jamesadevine	0:e1a608bb55e8	3336	#define MPU_PROTENSET0_PROTREG10_Set (1UL) /!< Enable protection on write. /
jamesadevine	0:e1a608bb55e8	3337
jamesadevine	0:e1a608bb55e8	3338	/* Bit 9 : Protection enable for region 9. */
jamesadevine	0:e1a608bb55e8	3339	#define MPU_PROTENSET0_PROTREG9_Pos (9UL) /!< Position of PROTREG9 field. /
jamesadevine	0:e1a608bb55e8	3340	#define MPU_PROTENSET0_PROTREG9_Msk (0x1UL << MPU_PROTENSET0_PROTREG9_Pos) /!< Bit mask of PROTREG9 field. /
jamesadevine	0:e1a608bb55e8	3341	#define MPU_PROTENSET0_PROTREG9_Disabled (0UL) /!< Protection disabled. /
jamesadevine	0:e1a608bb55e8	3342	#define MPU_PROTENSET0_PROTREG9_Enabled (1UL) /!< Protection enabled. /
jamesadevine	0:e1a608bb55e8	3343	#define MPU_PROTENSET0_PROTREG9_Set (1UL) /!< Enable protection on write. /
jamesadevine	0:e1a608bb55e8	3344
jamesadevine	0:e1a608bb55e8	3345	/* Bit 8 : Protection enable for region 8. */
jamesadevine	0:e1a608bb55e8	3346	#define MPU_PROTENSET0_PROTREG8_Pos (8UL) /!< Position of PROTREG8 field. /
jamesadevine	0:e1a608bb55e8	3347	#define MPU_PROTENSET0_PROTREG8_Msk (0x1UL << MPU_PROTENSET0_PROTREG8_Pos) /!< Bit mask of PROTREG8 field. /
jamesadevine	0:e1a608bb55e8	3348	#define MPU_PROTENSET0_PROTREG8_Disabled (0UL) /!< Protection disabled. /
jamesadevine	0:e1a608bb55e8	3349	#define MPU_PROTENSET0_PROTREG8_Enabled (1UL) /!< Protection enabled. /
jamesadevine	0:e1a608bb55e8	3350	#define MPU_PROTENSET0_PROTREG8_Set (1UL) /!< Enable protection on write. /
jamesadevine	0:e1a608bb55e8	3351
jamesadevine	0:e1a608bb55e8	3352	/* Bit 7 : Protection enable for region 7. */
jamesadevine	0:e1a608bb55e8	3353	#define MPU_PROTENSET0_PROTREG7_Pos (7UL) /!< Position of PROTREG7 field. /
jamesadevine	0:e1a608bb55e8	3354	#define MPU_PROTENSET0_PROTREG7_Msk (0x1UL << MPU_PROTENSET0_PROTREG7_Pos) /!< Bit mask of PROTREG7 field. /
jamesadevine	0:e1a608bb55e8	3355	#define MPU_PROTENSET0_PROTREG7_Disabled (0UL) /!< Protection disabled. /
jamesadevine	0:e1a608bb55e8	3356	#define MPU_PROTENSET0_PROTREG7_Enabled (1UL) /!< Protection enabled. /
jamesadevine	0:e1a608bb55e8	3357	#define MPU_PROTENSET0_PROTREG7_Set (1UL) /!< Enable protection on write. /
jamesadevine	0:e1a608bb55e8	3358
jamesadevine	0:e1a608bb55e8	3359	/* Bit 6 : Protection enable for region 6. */
jamesadevine	0:e1a608bb55e8	3360	#define MPU_PROTENSET0_PROTREG6_Pos (6UL) /!< Position of PROTREG6 field. /
jamesadevine	0:e1a608bb55e8	3361	#define MPU_PROTENSET0_PROTREG6_Msk (0x1UL << MPU_PROTENSET0_PROTREG6_Pos) /!< Bit mask of PROTREG6 field. /
jamesadevine	0:e1a608bb55e8	3362	#define MPU_PROTENSET0_PROTREG6_Disabled (0UL) /!< Protection disabled. /
jamesadevine	0:e1a608bb55e8	3363	#define MPU_PROTENSET0_PROTREG6_Enabled (1UL) /!< Protection enabled. /
jamesadevine	0:e1a608bb55e8	3364	#define MPU_PROTENSET0_PROTREG6_Set (1UL) /!< Enable protection on write. /
jamesadevine	0:e1a608bb55e8	3365
jamesadevine	0:e1a608bb55e8	3366	/* Bit 5 : Protection enable for region 5. */
jamesadevine	0:e1a608bb55e8	3367	#define MPU_PROTENSET0_PROTREG5_Pos (5UL) /!< Position of PROTREG5 field. /
jamesadevine	0:e1a608bb55e8	3368	#define MPU_PROTENSET0_PROTREG5_Msk (0x1UL << MPU_PROTENSET0_PROTREG5_Pos) /!< Bit mask of PROTREG5 field. /
jamesadevine	0:e1a608bb55e8	3369	#define MPU_PROTENSET0_PROTREG5_Disabled (0UL) /!< Protection disabled. /
jamesadevine	0:e1a608bb55e8	3370	#define MPU_PROTENSET0_PROTREG5_Enabled (1UL) /!< Protection enabled. /
jamesadevine	0:e1a608bb55e8	3371	#define MPU_PROTENSET0_PROTREG5_Set (1UL) /!< Enable protection on write. /
jamesadevine	0:e1a608bb55e8	3372
jamesadevine	0:e1a608bb55e8	3373	/* Bit 4 : Protection enable for region 4. */
jamesadevine	0:e1a608bb55e8	3374	#define MPU_PROTENSET0_PROTREG4_Pos (4UL) /!< Position of PROTREG4 field. /
jamesadevine	0:e1a608bb55e8	3375	#define MPU_PROTENSET0_PROTREG4_Msk (0x1UL << MPU_PROTENSET0_PROTREG4_Pos) /!< Bit mask of PROTREG4 field. /
jamesadevine	0:e1a608bb55e8	3376	#define MPU_PROTENSET0_PROTREG4_Disabled (0UL) /!< Protection disabled. /
jamesadevine	0:e1a608bb55e8	3377	#define MPU_PROTENSET0_PROTREG4_Enabled (1UL) /!< Protection enabled. /
jamesadevine	0:e1a608bb55e8	3378	#define MPU_PROTENSET0_PROTREG4_Set (1UL) /!< Enable protection on write. /
jamesadevine	0:e1a608bb55e8	3379
jamesadevine	0:e1a608bb55e8	3380	/* Bit 3 : Protection enable for region 3. */
jamesadevine	0:e1a608bb55e8	3381	#define MPU_PROTENSET0_PROTREG3_Pos (3UL) /!< Position of PROTREG3 field. /
jamesadevine	0:e1a608bb55e8	3382	#define MPU_PROTENSET0_PROTREG3_Msk (0x1UL << MPU_PROTENSET0_PROTREG3_Pos) /!< Bit mask of PROTREG3 field. /
jamesadevine	0:e1a608bb55e8	3383	#define MPU_PROTENSET0_PROTREG3_Disabled (0UL) /!< Protection disabled. /
jamesadevine	0:e1a608bb55e8	3384	#define MPU_PROTENSET0_PROTREG3_Enabled (1UL) /!< Protection enabled. /
jamesadevine	0:e1a608bb55e8	3385	#define MPU_PROTENSET0_PROTREG3_Set (1UL) /!< Enable protection on write. /
jamesadevine	0:e1a608bb55e8	3386
jamesadevine	0:e1a608bb55e8	3387	/* Bit 2 : Protection enable for region 2. */
jamesadevine	0:e1a608bb55e8	3388	#define MPU_PROTENSET0_PROTREG2_Pos (2UL) /!< Position of PROTREG2 field. /
jamesadevine	0:e1a608bb55e8	3389	#define MPU_PROTENSET0_PROTREG2_Msk (0x1UL << MPU_PROTENSET0_PROTREG2_Pos) /!< Bit mask of PROTREG2 field. /
jamesadevine	0:e1a608bb55e8	3390	#define MPU_PROTENSET0_PROTREG2_Disabled (0UL) /!< Protection disabled. /
jamesadevine	0:e1a608bb55e8	3391	#define MPU_PROTENSET0_PROTREG2_Enabled (1UL) /!< Protection enabled. /
jamesadevine	0:e1a608bb55e8	3392	#define MPU_PROTENSET0_PROTREG2_Set (1UL) /!< Enable protection on write. /
jamesadevine	0:e1a608bb55e8	3393
jamesadevine	0:e1a608bb55e8	3394	/* Bit 1 : Protection enable for region 1. */
jamesadevine	0:e1a608bb55e8	3395	#define MPU_PROTENSET0_PROTREG1_Pos (1UL) /!< Position of PROTREG1 field. /
jamesadevine	0:e1a608bb55e8	3396	#define MPU_PROTENSET0_PROTREG1_Msk (0x1UL << MPU_PROTENSET0_PROTREG1_Pos) /!< Bit mask of PROTREG1 field. /
jamesadevine	0:e1a608bb55e8	3397	#define MPU_PROTENSET0_PROTREG1_Disabled (0UL) /!< Protection disabled. /
jamesadevine	0:e1a608bb55e8	3398	#define MPU_PROTENSET0_PROTREG1_Enabled (1UL) /!< Protection enabled. /
jamesadevine	0:e1a608bb55e8	3399	#define MPU_PROTENSET0_PROTREG1_Set (1UL) /!< Enable protection on write. /
jamesadevine	0:e1a608bb55e8	3400
jamesadevine	0:e1a608bb55e8	3401	/* Bit 0 : Protection enable for region 0. */
jamesadevine	0:e1a608bb55e8	3402	#define MPU_PROTENSET0_PROTREG0_Pos (0UL) /!< Position of PROTREG0 field. /
jamesadevine	0:e1a608bb55e8	3403	#define MPU_PROTENSET0_PROTREG0_Msk (0x1UL << MPU_PROTENSET0_PROTREG0_Pos) /!< Bit mask of PROTREG0 field. /
jamesadevine	0:e1a608bb55e8	3404	#define MPU_PROTENSET0_PROTREG0_Disabled (0UL) /!< Protection disabled. /
jamesadevine	0:e1a608bb55e8	3405	#define MPU_PROTENSET0_PROTREG0_Enabled (1UL) /!< Protection enabled. /
jamesadevine	0:e1a608bb55e8	3406	#define MPU_PROTENSET0_PROTREG0_Set (1UL) /!< Enable protection on write. /
jamesadevine	0:e1a608bb55e8	3407
jamesadevine	0:e1a608bb55e8	3408	/* Register: MPU_PROTENSET1 */
jamesadevine	0:e1a608bb55e8	3409	/* Description: Erase and write protection bit enable set register. */
jamesadevine	0:e1a608bb55e8	3410
jamesadevine	0:e1a608bb55e8	3411	/* Bit 31 : Protection enable for region 63. */
jamesadevine	0:e1a608bb55e8	3412	#define MPU_PROTENSET1_PROTREG63_Pos (31UL) /!< Position of PROTREG63 field. /
jamesadevine	0:e1a608bb55e8	3413	#define MPU_PROTENSET1_PROTREG63_Msk (0x1UL << MPU_PROTENSET1_PROTREG63_Pos) /!< Bit mask of PROTREG63 field. /
jamesadevine	0:e1a608bb55e8	3414	#define MPU_PROTENSET1_PROTREG63_Disabled (0UL) /!< Protection disabled. /
jamesadevine	0:e1a608bb55e8	3415	#define MPU_PROTENSET1_PROTREG63_Enabled (1UL) /!< Protection enabled. /
jamesadevine	0:e1a608bb55e8	3416	#define MPU_PROTENSET1_PROTREG63_Set (1UL) /!< Enable protection on write. /
jamesadevine	0:e1a608bb55e8	3417
jamesadevine	0:e1a608bb55e8	3418	/* Bit 30 : Protection enable for region 62. */
jamesadevine	0:e1a608bb55e8	3419	#define MPU_PROTENSET1_PROTREG62_Pos (30UL) /!< Position of PROTREG62 field. /
jamesadevine	0:e1a608bb55e8	3420	#define MPU_PROTENSET1_PROTREG62_Msk (0x1UL << MPU_PROTENSET1_PROTREG62_Pos) /!< Bit mask of PROTREG62 field. /
jamesadevine	0:e1a608bb55e8	3421	#define MPU_PROTENSET1_PROTREG62_Disabled (0UL) /!< Protection disabled. /
jamesadevine	0:e1a608bb55e8	3422	#define MPU_PROTENSET1_PROTREG62_Enabled (1UL) /!< Protection enabled. /
jamesadevine	0:e1a608bb55e8	3423	#define MPU_PROTENSET1_PROTREG62_Set (1UL) /!< Enable protection on write. /
jamesadevine	0:e1a608bb55e8	3424
jamesadevine	0:e1a608bb55e8	3425	/* Bit 29 : Protection enable for region 61. */
jamesadevine	0:e1a608bb55e8	3426	#define MPU_PROTENSET1_PROTREG61_Pos (29UL) /!< Position of PROTREG61 field. /
jamesadevine	0:e1a608bb55e8	3427	#define MPU_PROTENSET1_PROTREG61_Msk (0x1UL << MPU_PROTENSET1_PROTREG61_Pos) /!< Bit mask of PROTREG61 field. /
jamesadevine	0:e1a608bb55e8	3428	#define MPU_PROTENSET1_PROTREG61_Disabled (0UL) /!< Protection disabled. /
jamesadevine	0:e1a608bb55e8	3429	#define MPU_PROTENSET1_PROTREG61_Enabled (1UL) /!< Protection enabled. /
jamesadevine	0:e1a608bb55e8	3430	#define MPU_PROTENSET1_PROTREG61_Set (1UL) /!< Enable protection on write. /
jamesadevine	0:e1a608bb55e8	3431
jamesadevine	0:e1a608bb55e8	3432	/* Bit 28 : Protection enable for region 60. */
jamesadevine	0:e1a608bb55e8	3433	#define MPU_PROTENSET1_PROTREG60_Pos (28UL) /!< Position of PROTREG60 field. /
jamesadevine	0:e1a608bb55e8	3434	#define MPU_PROTENSET1_PROTREG60_Msk (0x1UL << MPU_PROTENSET1_PROTREG60_Pos) /!< Bit mask of PROTREG60 field. /
jamesadevine	0:e1a608bb55e8	3435	#define MPU_PROTENSET1_PROTREG60_Disabled (0UL) /!< Protection disabled. /
jamesadevine	0:e1a608bb55e8	3436	#define MPU_PROTENSET1_PROTREG60_Enabled (1UL) /!< Protection enabled. /
jamesadevine	0:e1a608bb55e8	3437	#define MPU_PROTENSET1_PROTREG60_Set (1UL) /!< Enable protection on write. /
jamesadevine	0:e1a608bb55e8	3438
jamesadevine	0:e1a608bb55e8	3439	/* Bit 27 : Protection enable for region 59. */
jamesadevine	0:e1a608bb55e8	3440	#define MPU_PROTENSET1_PROTREG59_Pos (27UL) /!< Position of PROTREG59 field. /
jamesadevine	0:e1a608bb55e8	3441	#define MPU_PROTENSET1_PROTREG59_Msk (0x1UL << MPU_PROTENSET1_PROTREG59_Pos) /!< Bit mask of PROTREG59 field. /
jamesadevine	0:e1a608bb55e8	3442	#define MPU_PROTENSET1_PROTREG59_Disabled (0UL) /!< Protection disabled. /
jamesadevine	0:e1a608bb55e8	3443	#define MPU_PROTENSET1_PROTREG59_Enabled (1UL) /!< Protection enabled. /
jamesadevine	0:e1a608bb55e8	3444	#define MPU_PROTENSET1_PROTREG59_Set (1UL) /!< Enable protection on write. /
jamesadevine	0:e1a608bb55e8	3445
jamesadevine	0:e1a608bb55e8	3446	/* Bit 26 : Protection enable for region 58. */
jamesadevine	0:e1a608bb55e8	3447	#define MPU_PROTENSET1_PROTREG58_Pos (26UL) /!< Position of PROTREG58 field. /
jamesadevine	0:e1a608bb55e8	3448	#define MPU_PROTENSET1_PROTREG58_Msk (0x1UL << MPU_PROTENSET1_PROTREG58_Pos) /!< Bit mask of PROTREG58 field. /
jamesadevine	0:e1a608bb55e8	3449	#define MPU_PROTENSET1_PROTREG58_Disabled (0UL) /!< Protection disabled. /
jamesadevine	0:e1a608bb55e8	3450	#define MPU_PROTENSET1_PROTREG58_Enabled (1UL) /!< Protection enabled. /
jamesadevine	0:e1a608bb55e8	3451	#define MPU_PROTENSET1_PROTREG58_Set (1UL) /!< Enable protection on write. /
jamesadevine	0:e1a608bb55e8	3452
jamesadevine	0:e1a608bb55e8	3453	/* Bit 25 : Protection enable for region 57. */
jamesadevine	0:e1a608bb55e8	3454	#define MPU_PROTENSET1_PROTREG57_Pos (25UL) /!< Position of PROTREG57 field. /
jamesadevine	0:e1a608bb55e8	3455	#define MPU_PROTENSET1_PROTREG57_Msk (0x1UL << MPU_PROTENSET1_PROTREG57_Pos) /!< Bit mask of PROTREG57 field. /
jamesadevine	0:e1a608bb55e8	3456	#define MPU_PROTENSET1_PROTREG57_Disabled (0UL) /!< Protection disabled. /
jamesadevine	0:e1a608bb55e8	3457	#define MPU_PROTENSET1_PROTREG57_Enabled (1UL) /!< Protection enabled. /
jamesadevine	0:e1a608bb55e8	3458	#define MPU_PROTENSET1_PROTREG57_Set (1UL) /!< Enable protection on write. /
jamesadevine	0:e1a608bb55e8	3459
jamesadevine	0:e1a608bb55e8	3460	/* Bit 24 : Protection enable for region 56. */
jamesadevine	0:e1a608bb55e8	3461	#define MPU_PROTENSET1_PROTREG56_Pos (24UL) /!< Position of PROTREG56 field. /
jamesadevine	0:e1a608bb55e8	3462	#define MPU_PROTENSET1_PROTREG56_Msk (0x1UL << MPU_PROTENSET1_PROTREG56_Pos) /!< Bit mask of PROTREG56 field. /
jamesadevine	0:e1a608bb55e8	3463	#define MPU_PROTENSET1_PROTREG56_Disabled (0UL) /!< Protection disabled. /
jamesadevine	0:e1a608bb55e8	3464	#define MPU_PROTENSET1_PROTREG56_Enabled (1UL) /!< Protection enabled. /
jamesadevine	0:e1a608bb55e8	3465	#define MPU_PROTENSET1_PROTREG56_Set (1UL) /!< Enable protection on write. /
jamesadevine	0:e1a608bb55e8	3466
jamesadevine	0:e1a608bb55e8	3467	/* Bit 23 : Protection enable for region 55. */
jamesadevine	0:e1a608bb55e8	3468	#define MPU_PROTENSET1_PROTREG55_Pos (23UL) /!< Position of PROTREG55 field. /
jamesadevine	0:e1a608bb55e8	3469	#define MPU_PROTENSET1_PROTREG55_Msk (0x1UL << MPU_PROTENSET1_PROTREG55_Pos) /!< Bit mask of PROTREG55 field. /
jamesadevine	0:e1a608bb55e8	3470	#define MPU_PROTENSET1_PROTREG55_Disabled (0UL) /!< Protection disabled. /
jamesadevine	0:e1a608bb55e8	3471	#define MPU_PROTENSET1_PROTREG55_Enabled (1UL) /!< Protection enabled. /
jamesadevine	0:e1a608bb55e8	3472	#define MPU_PROTENSET1_PROTREG55_Set (1UL) /!< Enable protection on write. /
jamesadevine	0:e1a608bb55e8	3473
jamesadevine	0:e1a608bb55e8	3474	/* Bit 22 : Protection enable for region 54. */
jamesadevine	0:e1a608bb55e8	3475	#define MPU_PROTENSET1_PROTREG54_Pos (22UL) /!< Position of PROTREG54 field. /
jamesadevine	0:e1a608bb55e8	3476	#define MPU_PROTENSET1_PROTREG54_Msk (0x1UL << MPU_PROTENSET1_PROTREG54_Pos) /!< Bit mask of PROTREG54 field. /
jamesadevine	0:e1a608bb55e8	3477	#define MPU_PROTENSET1_PROTREG54_Disabled (0UL) /!< Protection disabled. /
jamesadevine	0:e1a608bb55e8	3478	#define MPU_PROTENSET1_PROTREG54_Enabled (1UL) /!< Protection enabled. /
jamesadevine	0:e1a608bb55e8	3479	#define MPU_PROTENSET1_PROTREG54_Set (1UL) /!< Enable protection on write. /
jamesadevine	0:e1a608bb55e8	3480
jamesadevine	0:e1a608bb55e8	3481	/* Bit 21 : Protection enable for region 53. */
jamesadevine	0:e1a608bb55e8	3482	#define MPU_PROTENSET1_PROTREG53_Pos (21UL) /!< Position of PROTREG53 field. /
jamesadevine	0:e1a608bb55e8	3483	#define MPU_PROTENSET1_PROTREG53_Msk (0x1UL << MPU_PROTENSET1_PROTREG53_Pos) /!< Bit mask of PROTREG53 field. /
jamesadevine	0:e1a608bb55e8	3484	#define MPU_PROTENSET1_PROTREG53_Disabled (0UL) /!< Protection disabled. /
jamesadevine	0:e1a608bb55e8	3485	#define MPU_PROTENSET1_PROTREG53_Enabled (1UL) /!< Protection enabled. /
jamesadevine	0:e1a608bb55e8	3486	#define MPU_PROTENSET1_PROTREG53_Set (1UL) /!< Enable protection on write. /
jamesadevine	0:e1a608bb55e8	3487
jamesadevine	0:e1a608bb55e8	3488	/* Bit 20 : Protection enable for region 52. */
jamesadevine	0:e1a608bb55e8	3489	#define MPU_PROTENSET1_PROTREG52_Pos (20UL) /!< Position of PROTREG52 field. /
jamesadevine	0:e1a608bb55e8	3490	#define MPU_PROTENSET1_PROTREG52_Msk (0x1UL << MPU_PROTENSET1_PROTREG52_Pos) /!< Bit mask of PROTREG52 field. /
jamesadevine	0:e1a608bb55e8	3491	#define MPU_PROTENSET1_PROTREG52_Disabled (0UL) /!< Protection disabled. /
jamesadevine	0:e1a608bb55e8	3492	#define MPU_PROTENSET1_PROTREG52_Enabled (1UL) /!< Protection enabled. /
jamesadevine	0:e1a608bb55e8	3493	#define MPU_PROTENSET1_PROTREG52_Set (1UL) /!< Enable protection on write. /
jamesadevine	0:e1a608bb55e8	3494
jamesadevine	0:e1a608bb55e8	3495	/* Bit 19 : Protection enable for region 51. */
jamesadevine	0:e1a608bb55e8	3496	#define MPU_PROTENSET1_PROTREG51_Pos (19UL) /!< Position of PROTREG51 field. /
jamesadevine	0:e1a608bb55e8	3497	#define MPU_PROTENSET1_PROTREG51_Msk (0x1UL << MPU_PROTENSET1_PROTREG51_Pos) /!< Bit mask of PROTREG51 field. /
jamesadevine	0:e1a608bb55e8	3498	#define MPU_PROTENSET1_PROTREG51_Disabled (0UL) /!< Protection disabled. /
jamesadevine	0:e1a608bb55e8	3499	#define MPU_PROTENSET1_PROTREG51_Enabled (1UL) /!< Protection enabled. /
jamesadevine	0:e1a608bb55e8	3500	#define MPU_PROTENSET1_PROTREG51_Set (1UL) /!< Enable protection on write. /
jamesadevine	0:e1a608bb55e8	3501
jamesadevine	0:e1a608bb55e8	3502	/* Bit 18 : Protection enable for region 50. */
jamesadevine	0:e1a608bb55e8	3503	#define MPU_PROTENSET1_PROTREG50_Pos (18UL) /!< Position of PROTREG50 field. /
jamesadevine	0:e1a608bb55e8	3504	#define MPU_PROTENSET1_PROTREG50_Msk (0x1UL << MPU_PROTENSET1_PROTREG50_Pos) /!< Bit mask of PROTREG50 field. /
jamesadevine	0:e1a608bb55e8	3505	#define MPU_PROTENSET1_PROTREG50_Disabled (0UL) /!< Protection disabled. /
jamesadevine	0:e1a608bb55e8	3506	#define MPU_PROTENSET1_PROTREG50_Enabled (1UL) /!< Protection enabled. /
jamesadevine	0:e1a608bb55e8	3507	#define MPU_PROTENSET1_PROTREG50_Set (1UL) /!< Enable protection on write. /
jamesadevine	0:e1a608bb55e8	3508
jamesadevine	0:e1a608bb55e8	3509	/* Bit 17 : Protection enable for region 49. */
jamesadevine	0:e1a608bb55e8	3510	#define MPU_PROTENSET1_PROTREG49_Pos (17UL) /!< Position of PROTREG49 field. /
jamesadevine	0:e1a608bb55e8	3511	#define MPU_PROTENSET1_PROTREG49_Msk (0x1UL << MPU_PROTENSET1_PROTREG49_Pos) /!< Bit mask of PROTREG49 field. /
jamesadevine	0:e1a608bb55e8	3512	#define MPU_PROTENSET1_PROTREG49_Disabled (0UL) /!< Protection disabled. /
jamesadevine	0:e1a608bb55e8	3513	#define MPU_PROTENSET1_PROTREG49_Enabled (1UL) /!< Protection enabled. /
jamesadevine	0:e1a608bb55e8	3514	#define MPU_PROTENSET1_PROTREG49_Set (1UL) /!< Enable protection on write. /
jamesadevine	0:e1a608bb55e8	3515
jamesadevine	0:e1a608bb55e8	3516	/* Bit 16 : Protection enable for region 48. */
jamesadevine	0:e1a608bb55e8	3517	#define MPU_PROTENSET1_PROTREG48_Pos (16UL) /!< Position of PROTREG48 field. /
jamesadevine	0:e1a608bb55e8	3518	#define MPU_PROTENSET1_PROTREG48_Msk (0x1UL << MPU_PROTENSET1_PROTREG48_Pos) /!< Bit mask of PROTREG48 field. /
jamesadevine	0:e1a608bb55e8	3519	#define MPU_PROTENSET1_PROTREG48_Disabled (0UL) /!< Protection disabled. /
jamesadevine	0:e1a608bb55e8	3520	#define MPU_PROTENSET1_PROTREG48_Enabled (1UL) /!< Protection enabled. /
jamesadevine	0:e1a608bb55e8	3521	#define MPU_PROTENSET1_PROTREG48_Set (1UL) /!< Enable protection on write. /
jamesadevine	0:e1a608bb55e8	3522
jamesadevine	0:e1a608bb55e8	3523	/* Bit 15 : Protection enable for region 47. */
jamesadevine	0:e1a608bb55e8	3524	#define MPU_PROTENSET1_PROTREG47_Pos (15UL) /!< Position of PROTREG47 field. /
jamesadevine	0:e1a608bb55e8	3525	#define MPU_PROTENSET1_PROTREG47_Msk (0x1UL << MPU_PROTENSET1_PROTREG47_Pos) /!< Bit mask of PROTREG47 field. /
jamesadevine	0:e1a608bb55e8	3526	#define MPU_PROTENSET1_PROTREG47_Disabled (0UL) /!< Protection disabled. /
jamesadevine	0:e1a608bb55e8	3527	#define MPU_PROTENSET1_PROTREG47_Enabled (1UL) /!< Protection enabled. /
jamesadevine	0:e1a608bb55e8	3528	#define MPU_PROTENSET1_PROTREG47_Set (1UL) /!< Enable protection on write. /
jamesadevine	0:e1a608bb55e8	3529
jamesadevine	0:e1a608bb55e8	3530	/* Bit 14 : Protection enable for region 46. */
jamesadevine	0:e1a608bb55e8	3531	#define MPU_PROTENSET1_PROTREG46_Pos (14UL) /!< Position of PROTREG46 field. /
jamesadevine	0:e1a608bb55e8	3532	#define MPU_PROTENSET1_PROTREG46_Msk (0x1UL << MPU_PROTENSET1_PROTREG46_Pos) /!< Bit mask of PROTREG46 field. /
jamesadevine	0:e1a608bb55e8	3533	#define MPU_PROTENSET1_PROTREG46_Disabled (0UL) /!< Protection disabled. /
jamesadevine	0:e1a608bb55e8	3534	#define MPU_PROTENSET1_PROTREG46_Enabled (1UL) /!< Protection enabled. /
jamesadevine	0:e1a608bb55e8	3535	#define MPU_PROTENSET1_PROTREG46_Set (1UL) /!< Enable protection on write. /
jamesadevine	0:e1a608bb55e8	3536
jamesadevine	0:e1a608bb55e8	3537	/* Bit 13 : Protection enable for region 45. */
jamesadevine	0:e1a608bb55e8	3538	#define MPU_PROTENSET1_PROTREG45_Pos (13UL) /!< Position of PROTREG45 field. /
jamesadevine	0:e1a608bb55e8	3539	#define MPU_PROTENSET1_PROTREG45_Msk (0x1UL << MPU_PROTENSET1_PROTREG45_Pos) /!< Bit mask of PROTREG45 field. /
jamesadevine	0:e1a608bb55e8	3540	#define MPU_PROTENSET1_PROTREG45_Disabled (0UL) /!< Protection disabled. /
jamesadevine	0:e1a608bb55e8	3541	#define MPU_PROTENSET1_PROTREG45_Enabled (1UL) /!< Protection enabled. /
jamesadevine	0:e1a608bb55e8	3542	#define MPU_PROTENSET1_PROTREG45_Set (1UL) /!< Enable protection on write. /
jamesadevine	0:e1a608bb55e8	3543
jamesadevine	0:e1a608bb55e8	3544	/* Bit 12 : Protection enable for region 44. */
jamesadevine	0:e1a608bb55e8	3545	#define MPU_PROTENSET1_PROTREG44_Pos (12UL) /!< Position of PROTREG44 field. /
jamesadevine	0:e1a608bb55e8	3546	#define MPU_PROTENSET1_PROTREG44_Msk (0x1UL << MPU_PROTENSET1_PROTREG44_Pos) /!< Bit mask of PROTREG44 field. /
jamesadevine	0:e1a608bb55e8	3547	#define MPU_PROTENSET1_PROTREG44_Disabled (0UL) /!< Protection disabled. /
jamesadevine	0:e1a608bb55e8	3548	#define MPU_PROTENSET1_PROTREG44_Enabled (1UL) /!< Protection enabled. /
jamesadevine	0:e1a608bb55e8	3549	#define MPU_PROTENSET1_PROTREG44_Set (1UL) /!< Enable protection on write. /
jamesadevine	0:e1a608bb55e8	3550
jamesadevine	0:e1a608bb55e8	3551	/* Bit 11 : Protection enable for region 43. */
jamesadevine	0:e1a608bb55e8	3552	#define MPU_PROTENSET1_PROTREG43_Pos (11UL) /!< Position of PROTREG43 field. /
jamesadevine	0:e1a608bb55e8	3553	#define MPU_PROTENSET1_PROTREG43_Msk (0x1UL << MPU_PROTENSET1_PROTREG43_Pos) /!< Bit mask of PROTREG43 field. /
jamesadevine	0:e1a608bb55e8	3554	#define MPU_PROTENSET1_PROTREG43_Disabled (0UL) /!< Protection disabled. /
jamesadevine	0:e1a608bb55e8	3555	#define MPU_PROTENSET1_PROTREG43_Enabled (1UL) /!< Protection enabled. /
jamesadevine	0:e1a608bb55e8	3556	#define MPU_PROTENSET1_PROTREG43_Set (1UL) /!< Enable protection on write. /
jamesadevine	0:e1a608bb55e8	3557
jamesadevine	0:e1a608bb55e8	3558	/* Bit 10 : Protection enable for region 42. */
jamesadevine	0:e1a608bb55e8	3559	#define MPU_PROTENSET1_PROTREG42_Pos (10UL) /!< Position of PROTREG42 field. /
jamesadevine	0:e1a608bb55e8	3560	#define MPU_PROTENSET1_PROTREG42_Msk (0x1UL << MPU_PROTENSET1_PROTREG42_Pos) /!< Bit mask of PROTREG42 field. /
jamesadevine	0:e1a608bb55e8	3561	#define MPU_PROTENSET1_PROTREG42_Disabled (0UL) /!< Protection disabled. /
jamesadevine	0:e1a608bb55e8	3562	#define MPU_PROTENSET1_PROTREG42_Enabled (1UL) /!< Protection enabled. /
jamesadevine	0:e1a608bb55e8	3563	#define MPU_PROTENSET1_PROTREG42_Set (1UL) /!< Enable protection on write. /
jamesadevine	0:e1a608bb55e8	3564
jamesadevine	0:e1a608bb55e8	3565	/* Bit 9 : Protection enable for region 41. */
jamesadevine	0:e1a608bb55e8	3566	#define MPU_PROTENSET1_PROTREG41_Pos (9UL) /!< Position of PROTREG41 field. /
jamesadevine	0:e1a608bb55e8	3567	#define MPU_PROTENSET1_PROTREG41_Msk (0x1UL << MPU_PROTENSET1_PROTREG41_Pos) /!< Bit mask of PROTREG41 field. /
jamesadevine	0:e1a608bb55e8	3568	#define MPU_PROTENSET1_PROTREG41_Disabled (0UL) /!< Protection disabled. /
jamesadevine	0:e1a608bb55e8	3569	#define MPU_PROTENSET1_PROTREG41_Enabled (1UL) /!< Protection enabled. /
jamesadevine	0:e1a608bb55e8	3570	#define MPU_PROTENSET1_PROTREG41_Set (1UL) /!< Enable protection on write. /
jamesadevine	0:e1a608bb55e8	3571
jamesadevine	0:e1a608bb55e8	3572	/* Bit 8 : Protection enable for region 40. */
jamesadevine	0:e1a608bb55e8	3573	#define MPU_PROTENSET1_PROTREG40_Pos (8UL) /!< Position of PROTREG40 field. /
jamesadevine	0:e1a608bb55e8	3574	#define MPU_PROTENSET1_PROTREG40_Msk (0x1UL << MPU_PROTENSET1_PROTREG40_Pos) /!< Bit mask of PROTREG40 field. /
jamesadevine	0:e1a608bb55e8	3575	#define MPU_PROTENSET1_PROTREG40_Disabled (0UL) /!< Protection disabled. /
jamesadevine	0:e1a608bb55e8	3576	#define MPU_PROTENSET1_PROTREG40_Enabled (1UL) /!< Protection enabled. /
jamesadevine	0:e1a608bb55e8	3577	#define MPU_PROTENSET1_PROTREG40_Set (1UL) /!< Enable protection on write. /
jamesadevine	0:e1a608bb55e8	3578
jamesadevine	0:e1a608bb55e8	3579	/* Bit 7 : Protection enable for region 39. */
jamesadevine	0:e1a608bb55e8	3580	#define MPU_PROTENSET1_PROTREG39_Pos (7UL) /!< Position of PROTREG39 field. /
jamesadevine	0:e1a608bb55e8	3581	#define MPU_PROTENSET1_PROTREG39_Msk (0x1UL << MPU_PROTENSET1_PROTREG39_Pos) /!< Bit mask of PROTREG39 field. /
jamesadevine	0:e1a608bb55e8	3582	#define MPU_PROTENSET1_PROTREG39_Disabled (0UL) /!< Protection disabled. /
jamesadevine	0:e1a608bb55e8	3583	#define MPU_PROTENSET1_PROTREG39_Enabled (1UL) /!< Protection enabled. /
jamesadevine	0:e1a608bb55e8	3584	#define MPU_PROTENSET1_PROTREG39_Set (1UL) /!< Enable protection on write. /
jamesadevine	0:e1a608bb55e8	3585
jamesadevine	0:e1a608bb55e8	3586	/* Bit 6 : Protection enable for region 38. */
jamesadevine	0:e1a608bb55e8	3587	#define MPU_PROTENSET1_PROTREG38_Pos (6UL) /!< Position of PROTREG38 field. /
jamesadevine	0:e1a608bb55e8	3588	#define MPU_PROTENSET1_PROTREG38_Msk (0x1UL << MPU_PROTENSET1_PROTREG38_Pos) /!< Bit mask of PROTREG38 field. /
jamesadevine	0:e1a608bb55e8	3589	#define MPU_PROTENSET1_PROTREG38_Disabled (0UL) /!< Protection disabled. /
jamesadevine	0:e1a608bb55e8	3590	#define MPU_PROTENSET1_PROTREG38_Enabled (1UL) /!< Protection enabled. /
jamesadevine	0:e1a608bb55e8	3591	#define MPU_PROTENSET1_PROTREG38_Set (1UL) /!< Enable protection on write. /
jamesadevine	0:e1a608bb55e8	3592
jamesadevine	0:e1a608bb55e8	3593	/* Bit 5 : Protection enable for region 37. */
jamesadevine	0:e1a608bb55e8	3594	#define MPU_PROTENSET1_PROTREG37_Pos (5UL) /!< Position of PROTREG37 field. /
jamesadevine	0:e1a608bb55e8	3595	#define MPU_PROTENSET1_PROTREG37_Msk (0x1UL << MPU_PROTENSET1_PROTREG37_Pos) /!< Bit mask of PROTREG37 field. /
jamesadevine	0:e1a608bb55e8	3596	#define MPU_PROTENSET1_PROTREG37_Disabled (0UL) /!< Protection disabled. /
jamesadevine	0:e1a608bb55e8	3597	#define MPU_PROTENSET1_PROTREG37_Enabled (1UL) /!< Protection enabled. /
jamesadevine	0:e1a608bb55e8	3598	#define MPU_PROTENSET1_PROTREG37_Set (1UL) /!< Enable protection on write. /
jamesadevine	0:e1a608bb55e8	3599
jamesadevine	0:e1a608bb55e8	3600	/* Bit 4 : Protection enable for region 36. */
jamesadevine	0:e1a608bb55e8	3601	#define MPU_PROTENSET1_PROTREG36_Pos (4UL) /!< Position of PROTREG36 field. /
jamesadevine	0:e1a608bb55e8	3602	#define MPU_PROTENSET1_PROTREG36_Msk (0x1UL << MPU_PROTENSET1_PROTREG36_Pos) /!< Bit mask of PROTREG36 field. /
jamesadevine	0:e1a608bb55e8	3603	#define MPU_PROTENSET1_PROTREG36_Disabled (0UL) /!< Protection disabled. /
jamesadevine	0:e1a608bb55e8	3604	#define MPU_PROTENSET1_PROTREG36_Enabled (1UL) /!< Protection enabled. /
jamesadevine	0:e1a608bb55e8	3605	#define MPU_PROTENSET1_PROTREG36_Set (1UL) /!< Enable protection on write. /
jamesadevine	0:e1a608bb55e8	3606
jamesadevine	0:e1a608bb55e8	3607	/* Bit 3 : Protection enable for region 35. */
jamesadevine	0:e1a608bb55e8	3608	#define MPU_PROTENSET1_PROTREG35_Pos (3UL) /!< Position of PROTREG35 field. /
jamesadevine	0:e1a608bb55e8	3609	#define MPU_PROTENSET1_PROTREG35_Msk (0x1UL << MPU_PROTENSET1_PROTREG35_Pos) /!< Bit mask of PROTREG35 field. /
jamesadevine	0:e1a608bb55e8	3610	#define MPU_PROTENSET1_PROTREG35_Disabled (0UL) /!< Protection disabled. /
jamesadevine	0:e1a608bb55e8	3611	#define MPU_PROTENSET1_PROTREG35_Enabled (1UL) /!< Protection enabled. /
jamesadevine	0:e1a608bb55e8	3612	#define MPU_PROTENSET1_PROTREG35_Set (1UL) /!< Enable protection on write. /
jamesadevine	0:e1a608bb55e8	3613
jamesadevine	0:e1a608bb55e8	3614	/* Bit 2 : Protection enable for region 34. */
jamesadevine	0:e1a608bb55e8	3615	#define MPU_PROTENSET1_PROTREG34_Pos (2UL) /!< Position of PROTREG34 field. /
jamesadevine	0:e1a608bb55e8	3616	#define MPU_PROTENSET1_PROTREG34_Msk (0x1UL << MPU_PROTENSET1_PROTREG34_Pos) /!< Bit mask of PROTREG34 field. /
jamesadevine	0:e1a608bb55e8	3617	#define MPU_PROTENSET1_PROTREG34_Disabled (0UL) /!< Protection disabled. /
jamesadevine	0:e1a608bb55e8	3618	#define MPU_PROTENSET1_PROTREG34_Enabled (1UL) /!< Protection enabled. /
jamesadevine	0:e1a608bb55e8	3619	#define MPU_PROTENSET1_PROTREG34_Set (1UL) /!< Enable protection on write. /
jamesadevine	0:e1a608bb55e8	3620
jamesadevine	0:e1a608bb55e8	3621	/* Bit 1 : Protection enable for region 33. */
jamesadevine	0:e1a608bb55e8	3622	#define MPU_PROTENSET1_PROTREG33_Pos (1UL) /!< Position of PROTREG33 field. /
jamesadevine	0:e1a608bb55e8	3623	#define MPU_PROTENSET1_PROTREG33_Msk (0x1UL << MPU_PROTENSET1_PROTREG33_Pos) /!< Bit mask of PROTREG33 field. /
jamesadevine	0:e1a608bb55e8	3624	#define MPU_PROTENSET1_PROTREG33_Disabled (0UL) /!< Protection disabled. /
jamesadevine	0:e1a608bb55e8	3625	#define MPU_PROTENSET1_PROTREG33_Enabled (1UL) /!< Protection enabled. /
jamesadevine	0:e1a608bb55e8	3626	#define MPU_PROTENSET1_PROTREG33_Set (1UL) /!< Enable protection on write. /
jamesadevine	0:e1a608bb55e8	3627
jamesadevine	0:e1a608bb55e8	3628	/* Bit 0 : Protection enable for region 32. */
jamesadevine	0:e1a608bb55e8	3629	#define MPU_PROTENSET1_PROTREG32_Pos (0UL) /!< Position of PROTREG32 field. /
jamesadevine	0:e1a608bb55e8	3630	#define MPU_PROTENSET1_PROTREG32_Msk (0x1UL << MPU_PROTENSET1_PROTREG32_Pos) /!< Bit mask of PROTREG32 field. /
jamesadevine	0:e1a608bb55e8	3631	#define MPU_PROTENSET1_PROTREG32_Disabled (0UL) /!< Protection disabled. /
jamesadevine	0:e1a608bb55e8	3632	#define MPU_PROTENSET1_PROTREG32_Enabled (1UL) /!< Protection enabled. /
jamesadevine	0:e1a608bb55e8	3633	#define MPU_PROTENSET1_PROTREG32_Set (1UL) /!< Enable protection on write. /
jamesadevine	0:e1a608bb55e8	3634
jamesadevine	0:e1a608bb55e8	3635	/* Register: MPU_DISABLEINDEBUG */
jamesadevine	0:e1a608bb55e8	3636	/* Description: Disable erase and write protection mechanism in debug mode. */
jamesadevine	0:e1a608bb55e8	3637
jamesadevine	0:e1a608bb55e8	3638	/* Bit 0 : Disable protection mechanism in debug mode. */
jamesadevine	0:e1a608bb55e8	3639	#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos (0UL) /!< Position of DISABLEINDEBUG field. /
jamesadevine	0:e1a608bb55e8	3640	#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Msk (0x1UL << MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos) /!< Bit mask of DISABLEINDEBUG field. /
jamesadevine	0:e1a608bb55e8	3641	#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Enabled (0UL) /!< Protection enabled. /
jamesadevine	0:e1a608bb55e8	3642	#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled (1UL) /!< Protection disabled. /
jamesadevine	0:e1a608bb55e8	3643
jamesadevine	0:e1a608bb55e8	3644	/* Register: MPU_PROTBLOCKSIZE */
jamesadevine	0:e1a608bb55e8	3645	/* Description: Erase and write protection block size. */
jamesadevine	0:e1a608bb55e8	3646
jamesadevine	0:e1a608bb55e8	3647	/* Bits 1..0 : Erase and write protection block size. */
jamesadevine	0:e1a608bb55e8	3648	#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Pos (0UL) /!< Position of PROTBLOCKSIZE field. /
jamesadevine	0:e1a608bb55e8	3649	#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Msk (0x3UL << MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Pos) /!< Bit mask of PROTBLOCKSIZE field. /
jamesadevine	0:e1a608bb55e8	3650	#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_4k (0UL) /!< Erase and write protection block size is 4k. /
jamesadevine	0:e1a608bb55e8	3651
jamesadevine	0:e1a608bb55e8	3652
jamesadevine	0:e1a608bb55e8	3653	/* Peripheral: NVMC */
jamesadevine	0:e1a608bb55e8	3654	/* Description: Non Volatile Memory Controller. */
jamesadevine	0:e1a608bb55e8	3655
jamesadevine	0:e1a608bb55e8	3656	/* Register: NVMC_READY */
jamesadevine	0:e1a608bb55e8	3657	/* Description: Ready flag. */
jamesadevine	0:e1a608bb55e8	3658
jamesadevine	0:e1a608bb55e8	3659	/* Bit 0 : NVMC ready. */
jamesadevine	0:e1a608bb55e8	3660	#define NVMC_READY_READY_Pos (0UL) /!< Position of READY field. /
jamesadevine	0:e1a608bb55e8	3661	#define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /!< Bit mask of READY field. /
jamesadevine	0:e1a608bb55e8	3662	#define NVMC_READY_READY_Busy (0UL) /!< NVMC is busy (on-going write or erase operation). /
jamesadevine	0:e1a608bb55e8	3663	#define NVMC_READY_READY_Ready (1UL) /!< NVMC is ready. /
jamesadevine	0:e1a608bb55e8	3664
jamesadevine	0:e1a608bb55e8	3665	/* Register: NVMC_CONFIG */
jamesadevine	0:e1a608bb55e8	3666	/* Description: Configuration register. */
jamesadevine	0:e1a608bb55e8	3667
jamesadevine	0:e1a608bb55e8	3668	/* Bits 1..0 : Program write enable. */
jamesadevine	0:e1a608bb55e8	3669	#define NVMC_CONFIG_WEN_Pos (0UL) /!< Position of WEN field. /
jamesadevine	0:e1a608bb55e8	3670	#define NVMC_CONFIG_WEN_Msk (0x3UL << NVMC_CONFIG_WEN_Pos) /!< Bit mask of WEN field. /
jamesadevine	0:e1a608bb55e8	3671	#define NVMC_CONFIG_WEN_Ren (0x00UL) /!< Read only access. /
jamesadevine	0:e1a608bb55e8	3672	#define NVMC_CONFIG_WEN_Wen (0x01UL) /!< Write enabled. /
jamesadevine	0:e1a608bb55e8	3673	#define NVMC_CONFIG_WEN_Een (0x02UL) /!< Erase enabled. /
jamesadevine	0:e1a608bb55e8	3674
jamesadevine	0:e1a608bb55e8	3675	/* Register: NVMC_ERASEALL */
jamesadevine	0:e1a608bb55e8	3676	/* Description: Register for erasing all non-volatile user memory. */
jamesadevine	0:e1a608bb55e8	3677
jamesadevine	0:e1a608bb55e8	3678	/* Bit 0 : Starts the erasing of all user NVM (code region 0/1 and UICR registers). */
jamesadevine	0:e1a608bb55e8	3679	#define NVMC_ERASEALL_ERASEALL_Pos (0UL) /!< Position of ERASEALL field. /
jamesadevine	0:e1a608bb55e8	3680	#define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /!< Bit mask of ERASEALL field. /
jamesadevine	0:e1a608bb55e8	3681	#define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /!< No operation. /
jamesadevine	0:e1a608bb55e8	3682	#define NVMC_ERASEALL_ERASEALL_Erase (1UL) /!< Start chip erase. /
jamesadevine	0:e1a608bb55e8	3683
jamesadevine	0:e1a608bb55e8	3684	/* Register: NVMC_ERASEUICR */
jamesadevine	0:e1a608bb55e8	3685	/* Description: Register for start erasing User Information Congfiguration Registers. */
jamesadevine	0:e1a608bb55e8	3686
jamesadevine	0:e1a608bb55e8	3687	/* Bit 0 : It can only be used when all contents of code region 1 are erased. */
jamesadevine	0:e1a608bb55e8	3688	#define NVMC_ERASEUICR_ERASEUICR_Pos (0UL) /!< Position of ERASEUICR field. /
jamesadevine	0:e1a608bb55e8	3689	#define NVMC_ERASEUICR_ERASEUICR_Msk (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos) /!< Bit mask of ERASEUICR field. /
jamesadevine	0:e1a608bb55e8	3690	#define NVMC_ERASEUICR_ERASEUICR_NoOperation (0UL) /!< No operation. /
jamesadevine	0:e1a608bb55e8	3691	#define NVMC_ERASEUICR_ERASEUICR_Erase (1UL) /!< Start UICR erase. /
jamesadevine	0:e1a608bb55e8	3692
jamesadevine	0:e1a608bb55e8	3693
jamesadevine	0:e1a608bb55e8	3694	/* Peripheral: POWER */
jamesadevine	0:e1a608bb55e8	3695	/* Description: Power Control. */
jamesadevine	0:e1a608bb55e8	3696
jamesadevine	0:e1a608bb55e8	3697	/* Register: POWER_INTENSET */
jamesadevine	0:e1a608bb55e8	3698	/* Description: Interrupt enable set register. */
jamesadevine	0:e1a608bb55e8	3699
jamesadevine	0:e1a608bb55e8	3700	/* Bit 2 : Enable interrupt on POFWARN event. */
jamesadevine	0:e1a608bb55e8	3701	#define POWER_INTENSET_POFWARN_Pos (2UL) /!< Position of POFWARN field. /
jamesadevine	0:e1a608bb55e8	3702	#define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /!< Bit mask of POFWARN field. /
jamesadevine	0:e1a608bb55e8	3703	#define POWER_INTENSET_POFWARN_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	3704	#define POWER_INTENSET_POFWARN_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	3705	#define POWER_INTENSET_POFWARN_Set (1UL) /!< Enable interrupt on write. /
jamesadevine	0:e1a608bb55e8	3706
jamesadevine	0:e1a608bb55e8	3707	/* Register: POWER_INTENCLR */
jamesadevine	0:e1a608bb55e8	3708	/* Description: Interrupt enable clear register. */
jamesadevine	0:e1a608bb55e8	3709
jamesadevine	0:e1a608bb55e8	3710	/* Bit 2 : Disable interrupt on POFWARN event. */
jamesadevine	0:e1a608bb55e8	3711	#define POWER_INTENCLR_POFWARN_Pos (2UL) /!< Position of POFWARN field. /
jamesadevine	0:e1a608bb55e8	3712	#define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /!< Bit mask of POFWARN field. /
jamesadevine	0:e1a608bb55e8	3713	#define POWER_INTENCLR_POFWARN_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	3714	#define POWER_INTENCLR_POFWARN_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	3715	#define POWER_INTENCLR_POFWARN_Clear (1UL) /!< Disable interrupt on write. /
jamesadevine	0:e1a608bb55e8	3716
jamesadevine	0:e1a608bb55e8	3717	/* Register: POWER_RESETREAS */
jamesadevine	0:e1a608bb55e8	3718	/* Description: Reset reason. */
jamesadevine	0:e1a608bb55e8	3719
jamesadevine	0:e1a608bb55e8	3720	/* Bit 18 : Reset from wake-up from OFF mode detected by entering into debug interface mode. */
jamesadevine	0:e1a608bb55e8	3721	#define POWER_RESETREAS_DIF_Pos (18UL) /!< Position of DIF field. /
jamesadevine	0:e1a608bb55e8	3722	#define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /!< Bit mask of DIF field. /
jamesadevine	0:e1a608bb55e8	3723
jamesadevine	0:e1a608bb55e8	3724	/* Bit 17 : Reset from wake-up from OFF mode detected by the use of ANADETECT signal from LPCOMP. */
jamesadevine	0:e1a608bb55e8	3725	#define POWER_RESETREAS_LPCOMP_Pos (17UL) /!< Position of LPCOMP field. /
jamesadevine	0:e1a608bb55e8	3726	#define POWER_RESETREAS_LPCOMP_Msk (0x1UL << POWER_RESETREAS_LPCOMP_Pos) /!< Bit mask of LPCOMP field. /
jamesadevine	0:e1a608bb55e8	3727
jamesadevine	0:e1a608bb55e8	3728	/* Bit 16 : Reset from wake-up from OFF mode detected by the use of DETECT signal from GPIO. */
jamesadevine	0:e1a608bb55e8	3729	#define POWER_RESETREAS_OFF_Pos (16UL) /!< Position of OFF field. /
jamesadevine	0:e1a608bb55e8	3730	#define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /!< Bit mask of OFF field. /
jamesadevine	0:e1a608bb55e8	3731
jamesadevine	0:e1a608bb55e8	3732	/* Bit 3 : Reset from CPU lock-up detected. */
jamesadevine	0:e1a608bb55e8	3733	#define POWER_RESETREAS_LOCKUP_Pos (3UL) /!< Position of LOCKUP field. /
jamesadevine	0:e1a608bb55e8	3734	#define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /!< Bit mask of LOCKUP field. /
jamesadevine	0:e1a608bb55e8	3735
jamesadevine	0:e1a608bb55e8	3736	/* Bit 2 : Reset from AIRCR.SYSRESETREQ detected. */
jamesadevine	0:e1a608bb55e8	3737	#define POWER_RESETREAS_SREQ_Pos (2UL) /!< Position of SREQ field. /
jamesadevine	0:e1a608bb55e8	3738	#define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /!< Bit mask of SREQ field. /
jamesadevine	0:e1a608bb55e8	3739
jamesadevine	0:e1a608bb55e8	3740	/* Bit 1 : Reset from watchdog detected. */
jamesadevine	0:e1a608bb55e8	3741	#define POWER_RESETREAS_DOG_Pos (1UL) /!< Position of DOG field. /
jamesadevine	0:e1a608bb55e8	3742	#define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /!< Bit mask of DOG field. /
jamesadevine	0:e1a608bb55e8	3743
jamesadevine	0:e1a608bb55e8	3744	/* Bit 0 : Reset from pin-reset detected. */
jamesadevine	0:e1a608bb55e8	3745	#define POWER_RESETREAS_RESETPIN_Pos (0UL) /!< Position of RESETPIN field. /
jamesadevine	0:e1a608bb55e8	3746	#define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /!< Bit mask of RESETPIN field. /
jamesadevine	0:e1a608bb55e8	3747
jamesadevine	0:e1a608bb55e8	3748	/* Register: POWER_RAMSTATUS */
jamesadevine	0:e1a608bb55e8	3749	/* Description: Ram status register. */
jamesadevine	0:e1a608bb55e8	3750
jamesadevine	0:e1a608bb55e8	3751	/* Bit 3 : RAM block 3 status. */
jamesadevine	0:e1a608bb55e8	3752	#define POWER_RAMSTATUS_RAMBLOCK3_Pos (3UL) /!< Position of RAMBLOCK3 field. /
jamesadevine	0:e1a608bb55e8	3753	#define POWER_RAMSTATUS_RAMBLOCK3_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK3_Pos) /!< Bit mask of RAMBLOCK3 field. /
jamesadevine	0:e1a608bb55e8	3754	#define POWER_RAMSTATUS_RAMBLOCK3_Off (0UL) /!< RAM block 3 is off or powering up. /
jamesadevine	0:e1a608bb55e8	3755	#define POWER_RAMSTATUS_RAMBLOCK3_On (1UL) /!< RAM block 3 is on. /
jamesadevine	0:e1a608bb55e8	3756
jamesadevine	0:e1a608bb55e8	3757	/* Bit 2 : RAM block 2 status. */
jamesadevine	0:e1a608bb55e8	3758	#define POWER_RAMSTATUS_RAMBLOCK2_Pos (2UL) /!< Position of RAMBLOCK2 field. /
jamesadevine	0:e1a608bb55e8	3759	#define POWER_RAMSTATUS_RAMBLOCK2_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK2_Pos) /!< Bit mask of RAMBLOCK2 field. /
jamesadevine	0:e1a608bb55e8	3760	#define POWER_RAMSTATUS_RAMBLOCK2_Off (0UL) /!< RAM block 2 is off or powering up. /
jamesadevine	0:e1a608bb55e8	3761	#define POWER_RAMSTATUS_RAMBLOCK2_On (1UL) /!< RAM block 2 is on. /
jamesadevine	0:e1a608bb55e8	3762
jamesadevine	0:e1a608bb55e8	3763	/* Bit 1 : RAM block 1 status. */
jamesadevine	0:e1a608bb55e8	3764	#define POWER_RAMSTATUS_RAMBLOCK1_Pos (1UL) /!< Position of RAMBLOCK1 field. /
jamesadevine	0:e1a608bb55e8	3765	#define POWER_RAMSTATUS_RAMBLOCK1_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK1_Pos) /!< Bit mask of RAMBLOCK1 field. /
jamesadevine	0:e1a608bb55e8	3766	#define POWER_RAMSTATUS_RAMBLOCK1_Off (0UL) /!< RAM block 1 is off or powering up. /
jamesadevine	0:e1a608bb55e8	3767	#define POWER_RAMSTATUS_RAMBLOCK1_On (1UL) /!< RAM block 1 is on. /
jamesadevine	0:e1a608bb55e8	3768
jamesadevine	0:e1a608bb55e8	3769	/* Bit 0 : RAM block 0 status. */
jamesadevine	0:e1a608bb55e8	3770	#define POWER_RAMSTATUS_RAMBLOCK0_Pos (0UL) /!< Position of RAMBLOCK0 field. /
jamesadevine	0:e1a608bb55e8	3771	#define POWER_RAMSTATUS_RAMBLOCK0_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK0_Pos) /!< Bit mask of RAMBLOCK0 field. /
jamesadevine	0:e1a608bb55e8	3772	#define POWER_RAMSTATUS_RAMBLOCK0_Off (0UL) /!< RAM block 0 is off or powering up. /
jamesadevine	0:e1a608bb55e8	3773	#define POWER_RAMSTATUS_RAMBLOCK0_On (1UL) /!< RAM block 0 is on. /
jamesadevine	0:e1a608bb55e8	3774
jamesadevine	0:e1a608bb55e8	3775	/* Register: POWER_SYSTEMOFF */
jamesadevine	0:e1a608bb55e8	3776	/* Description: System off register. */
jamesadevine	0:e1a608bb55e8	3777
jamesadevine	0:e1a608bb55e8	3778	/* Bit 0 : Enter system off mode. */
jamesadevine	0:e1a608bb55e8	3779	#define POWER_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /!< Position of SYSTEMOFF field. /
jamesadevine	0:e1a608bb55e8	3780	#define POWER_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << POWER_SYSTEMOFF_SYSTEMOFF_Pos) /!< Bit mask of SYSTEMOFF field. /
jamesadevine	0:e1a608bb55e8	3781	#define POWER_SYSTEMOFF_SYSTEMOFF_Enter (1UL) /!< Enter system off mode. /
jamesadevine	0:e1a608bb55e8	3782
jamesadevine	0:e1a608bb55e8	3783	/* Register: POWER_POFCON */
jamesadevine	0:e1a608bb55e8	3784	/* Description: Power failure configuration. */
jamesadevine	0:e1a608bb55e8	3785
jamesadevine	0:e1a608bb55e8	3786	/* Bits 2..1 : Set threshold level. */
jamesadevine	0:e1a608bb55e8	3787	#define POWER_POFCON_THRESHOLD_Pos (1UL) /!< Position of THRESHOLD field. /
jamesadevine	0:e1a608bb55e8	3788	#define POWER_POFCON_THRESHOLD_Msk (0x3UL << POWER_POFCON_THRESHOLD_Pos) /!< Bit mask of THRESHOLD field. /
jamesadevine	0:e1a608bb55e8	3789	#define POWER_POFCON_THRESHOLD_V21 (0x00UL) /!< Set threshold to 2.1Volts. /
jamesadevine	0:e1a608bb55e8	3790	#define POWER_POFCON_THRESHOLD_V23 (0x01UL) /!< Set threshold to 2.3Volts. /
jamesadevine	0:e1a608bb55e8	3791	#define POWER_POFCON_THRESHOLD_V25 (0x02UL) /!< Set threshold to 2.5Volts. /
jamesadevine	0:e1a608bb55e8	3792	#define POWER_POFCON_THRESHOLD_V27 (0x03UL) /!< Set threshold to 2.7Volts. /
jamesadevine	0:e1a608bb55e8	3793
jamesadevine	0:e1a608bb55e8	3794	/* Bit 0 : Power failure comparator enable. */
jamesadevine	0:e1a608bb55e8	3795	#define POWER_POFCON_POF_Pos (0UL) /!< Position of POF field. /
jamesadevine	0:e1a608bb55e8	3796	#define POWER_POFCON_POF_Msk (0x1UL << POWER_POFCON_POF_Pos) /!< Bit mask of POF field. /
jamesadevine	0:e1a608bb55e8	3797	#define POWER_POFCON_POF_Disabled (0UL) /!< Disabled. /
jamesadevine	0:e1a608bb55e8	3798	#define POWER_POFCON_POF_Enabled (1UL) /!< Enabled. /
jamesadevine	0:e1a608bb55e8	3799
jamesadevine	0:e1a608bb55e8	3800	/* Register: POWER_GPREGRET */
jamesadevine	0:e1a608bb55e8	3801	/* Description: General purpose retention register. This register is a retained register. */
jamesadevine	0:e1a608bb55e8	3802
jamesadevine	0:e1a608bb55e8	3803	/* Bits 7..0 : General purpose retention register. */
jamesadevine	0:e1a608bb55e8	3804	#define POWER_GPREGRET_GPREGRET_Pos (0UL) /!< Position of GPREGRET field. /
jamesadevine	0:e1a608bb55e8	3805	#define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /!< Bit mask of GPREGRET field. /
jamesadevine	0:e1a608bb55e8	3806
jamesadevine	0:e1a608bb55e8	3807	/* Register: POWER_RAMON */
jamesadevine	0:e1a608bb55e8	3808	/* Description: Ram on/off. */
jamesadevine	0:e1a608bb55e8	3809
jamesadevine	0:e1a608bb55e8	3810	/* Bit 17 : RAM block 1 behaviour in OFF mode. */
jamesadevine	0:e1a608bb55e8	3811	#define POWER_RAMON_OFFRAM1_Pos (17UL) /!< Position of OFFRAM1 field. /
jamesadevine	0:e1a608bb55e8	3812	#define POWER_RAMON_OFFRAM1_Msk (0x1UL << POWER_RAMON_OFFRAM1_Pos) /!< Bit mask of OFFRAM1 field. /
jamesadevine	0:e1a608bb55e8	3813	#define POWER_RAMON_OFFRAM1_RAM1Off (0UL) /!< RAM block 1 OFF in OFF mode. /
jamesadevine	0:e1a608bb55e8	3814	#define POWER_RAMON_OFFRAM1_RAM1On (1UL) /!< RAM block 1 ON in OFF mode. /
jamesadevine	0:e1a608bb55e8	3815
jamesadevine	0:e1a608bb55e8	3816	/* Bit 16 : RAM block 0 behaviour in OFF mode. */
jamesadevine	0:e1a608bb55e8	3817	#define POWER_RAMON_OFFRAM0_Pos (16UL) /!< Position of OFFRAM0 field. /
jamesadevine	0:e1a608bb55e8	3818	#define POWER_RAMON_OFFRAM0_Msk (0x1UL << POWER_RAMON_OFFRAM0_Pos) /!< Bit mask of OFFRAM0 field. /
jamesadevine	0:e1a608bb55e8	3819	#define POWER_RAMON_OFFRAM0_RAM0Off (0UL) /!< RAM block 0 OFF in OFF mode. /
jamesadevine	0:e1a608bb55e8	3820	#define POWER_RAMON_OFFRAM0_RAM0On (1UL) /!< RAM block 0 ON in OFF mode. /
jamesadevine	0:e1a608bb55e8	3821
jamesadevine	0:e1a608bb55e8	3822	/* Bit 1 : RAM block 1 behaviour in ON mode. */
jamesadevine	0:e1a608bb55e8	3823	#define POWER_RAMON_ONRAM1_Pos (1UL) /!< Position of ONRAM1 field. /
jamesadevine	0:e1a608bb55e8	3824	#define POWER_RAMON_ONRAM1_Msk (0x1UL << POWER_RAMON_ONRAM1_Pos) /!< Bit mask of ONRAM1 field. /
jamesadevine	0:e1a608bb55e8	3825	#define POWER_RAMON_ONRAM1_RAM1Off (0UL) /!< RAM block 1 OFF in ON mode. /
jamesadevine	0:e1a608bb55e8	3826	#define POWER_RAMON_ONRAM1_RAM1On (1UL) /!< RAM block 1 ON in ON mode. /
jamesadevine	0:e1a608bb55e8	3827
jamesadevine	0:e1a608bb55e8	3828	/* Bit 0 : RAM block 0 behaviour in ON mode. */
jamesadevine	0:e1a608bb55e8	3829	#define POWER_RAMON_ONRAM0_Pos (0UL) /!< Position of ONRAM0 field. /
jamesadevine	0:e1a608bb55e8	3830	#define POWER_RAMON_ONRAM0_Msk (0x1UL << POWER_RAMON_ONRAM0_Pos) /!< Bit mask of ONRAM0 field. /
jamesadevine	0:e1a608bb55e8	3831	#define POWER_RAMON_ONRAM0_RAM0Off (0UL) /!< RAM block 0 OFF in ON mode. /
jamesadevine	0:e1a608bb55e8	3832	#define POWER_RAMON_ONRAM0_RAM0On (1UL) /!< RAM block 0 ON in ON mode. /
jamesadevine	0:e1a608bb55e8	3833
jamesadevine	0:e1a608bb55e8	3834	/* Register: POWER_RESET */
jamesadevine	0:e1a608bb55e8	3835	/* Description: Pin reset functionality configuration register. This register is a retained register. */
jamesadevine	0:e1a608bb55e8	3836
jamesadevine	0:e1a608bb55e8	3837	/* Bit 0 : Enable or disable pin reset in debug interface mode. */
jamesadevine	0:e1a608bb55e8	3838	#define POWER_RESET_RESET_Pos (0UL) /!< Position of RESET field. /
jamesadevine	0:e1a608bb55e8	3839	#define POWER_RESET_RESET_Msk (0x1UL << POWER_RESET_RESET_Pos) /!< Bit mask of RESET field. /
jamesadevine	0:e1a608bb55e8	3840	#define POWER_RESET_RESET_Disabled (0UL) /!< Pin reset in debug interface mode disabled. /
jamesadevine	0:e1a608bb55e8	3841	#define POWER_RESET_RESET_Enabled (1UL) /!< Pin reset in debug interface mode enabled. /
jamesadevine	0:e1a608bb55e8	3842
jamesadevine	0:e1a608bb55e8	3843	/* Register: POWER_RAMONB */
jamesadevine	0:e1a608bb55e8	3844	/* Description: Ram on/off. */
jamesadevine	0:e1a608bb55e8	3845
jamesadevine	0:e1a608bb55e8	3846	/* Bit 17 : RAM block 3 behaviour in OFF mode. */
jamesadevine	0:e1a608bb55e8	3847	#define POWER_RAMONB_OFFRAM3_Pos (17UL) /!< Position of OFFRAM3 field. /
jamesadevine	0:e1a608bb55e8	3848	#define POWER_RAMONB_OFFRAM3_Msk (0x1UL << POWER_RAMONB_OFFRAM3_Pos) /!< Bit mask of OFFRAM3 field. /
jamesadevine	0:e1a608bb55e8	3849	#define POWER_RAMONB_OFFRAM3_RAM3Off (0UL) /!< RAM block 3 OFF in OFF mode. /
jamesadevine	0:e1a608bb55e8	3850	#define POWER_RAMONB_OFFRAM3_RAM3On (1UL) /!< RAM block 3 ON in OFF mode. /
jamesadevine	0:e1a608bb55e8	3851
jamesadevine	0:e1a608bb55e8	3852	/* Bit 16 : RAM block 2 behaviour in OFF mode. */
jamesadevine	0:e1a608bb55e8	3853	#define POWER_RAMONB_OFFRAM2_Pos (16UL) /!< Position of OFFRAM2 field. /
jamesadevine	0:e1a608bb55e8	3854	#define POWER_RAMONB_OFFRAM2_Msk (0x1UL << POWER_RAMONB_OFFRAM2_Pos) /!< Bit mask of OFFRAM2 field. /
jamesadevine	0:e1a608bb55e8	3855	#define POWER_RAMONB_OFFRAM2_RAM2Off (0UL) /!< RAM block 2 OFF in OFF mode. /
jamesadevine	0:e1a608bb55e8	3856	#define POWER_RAMONB_OFFRAM2_RAM2On (1UL) /!< RAM block 2 ON in OFF mode. /
jamesadevine	0:e1a608bb55e8	3857
jamesadevine	0:e1a608bb55e8	3858	/* Bit 1 : RAM block 3 behaviour in ON mode. */
jamesadevine	0:e1a608bb55e8	3859	#define POWER_RAMONB_ONRAM3_Pos (1UL) /!< Position of ONRAM3 field. /
jamesadevine	0:e1a608bb55e8	3860	#define POWER_RAMONB_ONRAM3_Msk (0x1UL << POWER_RAMONB_ONRAM3_Pos) /!< Bit mask of ONRAM3 field. /
jamesadevine	0:e1a608bb55e8	3861	#define POWER_RAMONB_ONRAM3_RAM3Off (0UL) /!< RAM block 33 OFF in ON mode. /
jamesadevine	0:e1a608bb55e8	3862	#define POWER_RAMONB_ONRAM3_RAM3On (1UL) /!< RAM block 3 ON in ON mode. /
jamesadevine	0:e1a608bb55e8	3863
jamesadevine	0:e1a608bb55e8	3864	/* Bit 0 : RAM block 2 behaviour in ON mode. */
jamesadevine	0:e1a608bb55e8	3865	#define POWER_RAMONB_ONRAM2_Pos (0UL) /!< Position of ONRAM2 field. /
jamesadevine	0:e1a608bb55e8	3866	#define POWER_RAMONB_ONRAM2_Msk (0x1UL << POWER_RAMONB_ONRAM2_Pos) /!< Bit mask of ONRAM2 field. /
jamesadevine	0:e1a608bb55e8	3867	#define POWER_RAMONB_ONRAM2_RAM2Off (0UL) /!< RAM block 2 OFF in ON mode. /
jamesadevine	0:e1a608bb55e8	3868	#define POWER_RAMONB_ONRAM2_RAM2On (1UL) /!< RAM block 2 ON in ON mode. /
jamesadevine	0:e1a608bb55e8	3869
jamesadevine	0:e1a608bb55e8	3870	/* Register: POWER_DCDCEN */
jamesadevine	0:e1a608bb55e8	3871	/* Description: DCDC converter enable configuration register. */
jamesadevine	0:e1a608bb55e8	3872
jamesadevine	0:e1a608bb55e8	3873	/* Bit 0 : Enable DCDC converter. */
jamesadevine	0:e1a608bb55e8	3874	#define POWER_DCDCEN_DCDCEN_Pos (0UL) /!< Position of DCDCEN field. /
jamesadevine	0:e1a608bb55e8	3875	#define POWER_DCDCEN_DCDCEN_Msk (0x1UL << POWER_DCDCEN_DCDCEN_Pos) /!< Bit mask of DCDCEN field. /
jamesadevine	0:e1a608bb55e8	3876	#define POWER_DCDCEN_DCDCEN_Disabled (0UL) /!< DCDC converter disabled. /
jamesadevine	0:e1a608bb55e8	3877	#define POWER_DCDCEN_DCDCEN_Enabled (1UL) /!< DCDC converter enabled. /
jamesadevine	0:e1a608bb55e8	3878
jamesadevine	0:e1a608bb55e8	3879	/* Register: POWER_DCDCFORCE */
jamesadevine	0:e1a608bb55e8	3880	/* Description: DCDC power-up force register. */
jamesadevine	0:e1a608bb55e8	3881
jamesadevine	0:e1a608bb55e8	3882	/* Bit 1 : DCDC power-up force on. */
jamesadevine	0:e1a608bb55e8	3883	#define POWER_DCDCFORCE_FORCEON_Pos (1UL) /!< Position of FORCEON field. /
jamesadevine	0:e1a608bb55e8	3884	#define POWER_DCDCFORCE_FORCEON_Msk (0x1UL << POWER_DCDCFORCE_FORCEON_Pos) /!< Bit mask of FORCEON field. /
jamesadevine	0:e1a608bb55e8	3885	#define POWER_DCDCFORCE_FORCEON_NoForce (0UL) /!< No force. /
jamesadevine	0:e1a608bb55e8	3886	#define POWER_DCDCFORCE_FORCEON_Force (1UL) /!< Force. /
jamesadevine	0:e1a608bb55e8	3887
jamesadevine	0:e1a608bb55e8	3888	/* Bit 0 : DCDC power-up force off. */
jamesadevine	0:e1a608bb55e8	3889	#define POWER_DCDCFORCE_FORCEOFF_Pos (0UL) /!< Position of FORCEOFF field. /
jamesadevine	0:e1a608bb55e8	3890	#define POWER_DCDCFORCE_FORCEOFF_Msk (0x1UL << POWER_DCDCFORCE_FORCEOFF_Pos) /!< Bit mask of FORCEOFF field. /
jamesadevine	0:e1a608bb55e8	3891	#define POWER_DCDCFORCE_FORCEOFF_NoForce (0UL) /!< No force. /
jamesadevine	0:e1a608bb55e8	3892	#define POWER_DCDCFORCE_FORCEOFF_Force (1UL) /!< Force. /
jamesadevine	0:e1a608bb55e8	3893
jamesadevine	0:e1a608bb55e8	3894
jamesadevine	0:e1a608bb55e8	3895	/* Peripheral: PPI */
jamesadevine	0:e1a608bb55e8	3896	/* Description: PPI controller. */
jamesadevine	0:e1a608bb55e8	3897
jamesadevine	0:e1a608bb55e8	3898	/* Register: PPI_CHEN */
jamesadevine	0:e1a608bb55e8	3899	/* Description: Channel enable. */
jamesadevine	0:e1a608bb55e8	3900
jamesadevine	0:e1a608bb55e8	3901	/* Bit 31 : Enable PPI channel 31. */
jamesadevine	0:e1a608bb55e8	3902	#define PPI_CHEN_CH31_Pos (31UL) /!< Position of CH31 field. /
jamesadevine	0:e1a608bb55e8	3903	#define PPI_CHEN_CH31_Msk (0x1UL << PPI_CHEN_CH31_Pos) /!< Bit mask of CH31 field. /
jamesadevine	0:e1a608bb55e8	3904	#define PPI_CHEN_CH31_Disabled (0UL) /!< Channel disabled. /
jamesadevine	0:e1a608bb55e8	3905	#define PPI_CHEN_CH31_Enabled (1UL) /!< Channel enabled. /
jamesadevine	0:e1a608bb55e8	3906
jamesadevine	0:e1a608bb55e8	3907	/* Bit 30 : Enable PPI channel 30. */
jamesadevine	0:e1a608bb55e8	3908	#define PPI_CHEN_CH30_Pos (30UL) /!< Position of CH30 field. /
jamesadevine	0:e1a608bb55e8	3909	#define PPI_CHEN_CH30_Msk (0x1UL << PPI_CHEN_CH30_Pos) /!< Bit mask of CH30 field. /
jamesadevine	0:e1a608bb55e8	3910	#define PPI_CHEN_CH30_Disabled (0UL) /!< Channel disabled. /
jamesadevine	0:e1a608bb55e8	3911	#define PPI_CHEN_CH30_Enabled (1UL) /!< Channel enabled. /
jamesadevine	0:e1a608bb55e8	3912
jamesadevine	0:e1a608bb55e8	3913	/* Bit 29 : Enable PPI channel 29. */
jamesadevine	0:e1a608bb55e8	3914	#define PPI_CHEN_CH29_Pos (29UL) /!< Position of CH29 field. /
jamesadevine	0:e1a608bb55e8	3915	#define PPI_CHEN_CH29_Msk (0x1UL << PPI_CHEN_CH29_Pos) /!< Bit mask of CH29 field. /
jamesadevine	0:e1a608bb55e8	3916	#define PPI_CHEN_CH29_Disabled (0UL) /!< Channel disabled. /
jamesadevine	0:e1a608bb55e8	3917	#define PPI_CHEN_CH29_Enabled (1UL) /!< Channel enabled. /
jamesadevine	0:e1a608bb55e8	3918
jamesadevine	0:e1a608bb55e8	3919	/* Bit 28 : Enable PPI channel 28. */
jamesadevine	0:e1a608bb55e8	3920	#define PPI_CHEN_CH28_Pos (28UL) /!< Position of CH28 field. /
jamesadevine	0:e1a608bb55e8	3921	#define PPI_CHEN_CH28_Msk (0x1UL << PPI_CHEN_CH28_Pos) /!< Bit mask of CH28 field. /
jamesadevine	0:e1a608bb55e8	3922	#define PPI_CHEN_CH28_Disabled (0UL) /!< Channel disabled. /
jamesadevine	0:e1a608bb55e8	3923	#define PPI_CHEN_CH28_Enabled (1UL) /!< Channel enabled. /
jamesadevine	0:e1a608bb55e8	3924
jamesadevine	0:e1a608bb55e8	3925	/* Bit 27 : Enable PPI channel 27. */
jamesadevine	0:e1a608bb55e8	3926	#define PPI_CHEN_CH27_Pos (27UL) /!< Position of CH27 field. /
jamesadevine	0:e1a608bb55e8	3927	#define PPI_CHEN_CH27_Msk (0x1UL << PPI_CHEN_CH27_Pos) /!< Bit mask of CH27 field. /
jamesadevine	0:e1a608bb55e8	3928	#define PPI_CHEN_CH27_Disabled (0UL) /!< Channel disabled. /
jamesadevine	0:e1a608bb55e8	3929	#define PPI_CHEN_CH27_Enabled (1UL) /!< Channel enabled. /
jamesadevine	0:e1a608bb55e8	3930
jamesadevine	0:e1a608bb55e8	3931	/* Bit 26 : Enable PPI channel 26. */
jamesadevine	0:e1a608bb55e8	3932	#define PPI_CHEN_CH26_Pos (26UL) /!< Position of CH26 field. /
jamesadevine	0:e1a608bb55e8	3933	#define PPI_CHEN_CH26_Msk (0x1UL << PPI_CHEN_CH26_Pos) /!< Bit mask of CH26 field. /
jamesadevine	0:e1a608bb55e8	3934	#define PPI_CHEN_CH26_Disabled (0UL) /!< Channel disabled. /
jamesadevine	0:e1a608bb55e8	3935	#define PPI_CHEN_CH26_Enabled (1UL) /!< Channel enabled. /
jamesadevine	0:e1a608bb55e8	3936
jamesadevine	0:e1a608bb55e8	3937	/* Bit 25 : Enable PPI channel 25. */
jamesadevine	0:e1a608bb55e8	3938	#define PPI_CHEN_CH25_Pos (25UL) /!< Position of CH25 field. /
jamesadevine	0:e1a608bb55e8	3939	#define PPI_CHEN_CH25_Msk (0x1UL << PPI_CHEN_CH25_Pos) /!< Bit mask of CH25 field. /
jamesadevine	0:e1a608bb55e8	3940	#define PPI_CHEN_CH25_Disabled (0UL) /!< Channel disabled. /
jamesadevine	0:e1a608bb55e8	3941	#define PPI_CHEN_CH25_Enabled (1UL) /!< Channel enabled. /
jamesadevine	0:e1a608bb55e8	3942
jamesadevine	0:e1a608bb55e8	3943	/* Bit 24 : Enable PPI channel 24. */
jamesadevine	0:e1a608bb55e8	3944	#define PPI_CHEN_CH24_Pos (24UL) /!< Position of CH24 field. /
jamesadevine	0:e1a608bb55e8	3945	#define PPI_CHEN_CH24_Msk (0x1UL << PPI_CHEN_CH24_Pos) /!< Bit mask of CH24 field. /
jamesadevine	0:e1a608bb55e8	3946	#define PPI_CHEN_CH24_Disabled (0UL) /!< Channel disabled. /
jamesadevine	0:e1a608bb55e8	3947	#define PPI_CHEN_CH24_Enabled (1UL) /!< Channel enabled. /
jamesadevine	0:e1a608bb55e8	3948
jamesadevine	0:e1a608bb55e8	3949	/* Bit 23 : Enable PPI channel 23. */
jamesadevine	0:e1a608bb55e8	3950	#define PPI_CHEN_CH23_Pos (23UL) /!< Position of CH23 field. /
jamesadevine	0:e1a608bb55e8	3951	#define PPI_CHEN_CH23_Msk (0x1UL << PPI_CHEN_CH23_Pos) /!< Bit mask of CH23 field. /
jamesadevine	0:e1a608bb55e8	3952	#define PPI_CHEN_CH23_Disabled (0UL) /!< Channel disabled. /
jamesadevine	0:e1a608bb55e8	3953	#define PPI_CHEN_CH23_Enabled (1UL) /!< Channel enabled. /
jamesadevine	0:e1a608bb55e8	3954
jamesadevine	0:e1a608bb55e8	3955	/* Bit 22 : Enable PPI channel 22. */
jamesadevine	0:e1a608bb55e8	3956	#define PPI_CHEN_CH22_Pos (22UL) /!< Position of CH22 field. /
jamesadevine	0:e1a608bb55e8	3957	#define PPI_CHEN_CH22_Msk (0x1UL << PPI_CHEN_CH22_Pos) /!< Bit mask of CH22 field. /
jamesadevine	0:e1a608bb55e8	3958	#define PPI_CHEN_CH22_Disabled (0UL) /!< Channel disabled. /
jamesadevine	0:e1a608bb55e8	3959	#define PPI_CHEN_CH22_Enabled (1UL) /!< Channel enabled. /
jamesadevine	0:e1a608bb55e8	3960
jamesadevine	0:e1a608bb55e8	3961	/* Bit 21 : Enable PPI channel 21. */
jamesadevine	0:e1a608bb55e8	3962	#define PPI_CHEN_CH21_Pos (21UL) /!< Position of CH21 field. /
jamesadevine	0:e1a608bb55e8	3963	#define PPI_CHEN_CH21_Msk (0x1UL << PPI_CHEN_CH21_Pos) /!< Bit mask of CH21 field. /
jamesadevine	0:e1a608bb55e8	3964	#define PPI_CHEN_CH21_Disabled (0UL) /!< Channel disabled. /
jamesadevine	0:e1a608bb55e8	3965	#define PPI_CHEN_CH21_Enabled (1UL) /!< Channel enabled. /
jamesadevine	0:e1a608bb55e8	3966
jamesadevine	0:e1a608bb55e8	3967	/* Bit 20 : Enable PPI channel 20. */
jamesadevine	0:e1a608bb55e8	3968	#define PPI_CHEN_CH20_Pos (20UL) /!< Position of CH20 field. /
jamesadevine	0:e1a608bb55e8	3969	#define PPI_CHEN_CH20_Msk (0x1UL << PPI_CHEN_CH20_Pos) /!< Bit mask of CH20 field. /
jamesadevine	0:e1a608bb55e8	3970	#define PPI_CHEN_CH20_Disabled (0UL) /!< Channel disabled. /
jamesadevine	0:e1a608bb55e8	3971	#define PPI_CHEN_CH20_Enabled (1UL) /!< Channel enabled. /
jamesadevine	0:e1a608bb55e8	3972
jamesadevine	0:e1a608bb55e8	3973	/* Bit 15 : Enable PPI channel 15. */
jamesadevine	0:e1a608bb55e8	3974	#define PPI_CHEN_CH15_Pos (15UL) /!< Position of CH15 field. /
jamesadevine	0:e1a608bb55e8	3975	#define PPI_CHEN_CH15_Msk (0x1UL << PPI_CHEN_CH15_Pos) /!< Bit mask of CH15 field. /
jamesadevine	0:e1a608bb55e8	3976	#define PPI_CHEN_CH15_Disabled (0UL) /!< Channel disabled. /
jamesadevine	0:e1a608bb55e8	3977	#define PPI_CHEN_CH15_Enabled (1UL) /!< Channel enabled. /
jamesadevine	0:e1a608bb55e8	3978
jamesadevine	0:e1a608bb55e8	3979	/* Bit 14 : Enable PPI channel 14. */
jamesadevine	0:e1a608bb55e8	3980	#define PPI_CHEN_CH14_Pos (14UL) /!< Position of CH14 field. /
jamesadevine	0:e1a608bb55e8	3981	#define PPI_CHEN_CH14_Msk (0x1UL << PPI_CHEN_CH14_Pos) /!< Bit mask of CH14 field. /
jamesadevine	0:e1a608bb55e8	3982	#define PPI_CHEN_CH14_Disabled (0UL) /!< Channel disabled. /
jamesadevine	0:e1a608bb55e8	3983	#define PPI_CHEN_CH14_Enabled (1UL) /!< Channel enabled. /
jamesadevine	0:e1a608bb55e8	3984
jamesadevine	0:e1a608bb55e8	3985	/* Bit 13 : Enable PPI channel 13. */
jamesadevine	0:e1a608bb55e8	3986	#define PPI_CHEN_CH13_Pos (13UL) /!< Position of CH13 field. /
jamesadevine	0:e1a608bb55e8	3987	#define PPI_CHEN_CH13_Msk (0x1UL << PPI_CHEN_CH13_Pos) /!< Bit mask of CH13 field. /
jamesadevine	0:e1a608bb55e8	3988	#define PPI_CHEN_CH13_Disabled (0UL) /!< Channel disabled. /
jamesadevine	0:e1a608bb55e8	3989	#define PPI_CHEN_CH13_Enabled (1UL) /!< Channel enabled. /
jamesadevine	0:e1a608bb55e8	3990
jamesadevine	0:e1a608bb55e8	3991	/* Bit 12 : Enable PPI channel 12. */
jamesadevine	0:e1a608bb55e8	3992	#define PPI_CHEN_CH12_Pos (12UL) /!< Position of CH12 field. /
jamesadevine	0:e1a608bb55e8	3993	#define PPI_CHEN_CH12_Msk (0x1UL << PPI_CHEN_CH12_Pos) /!< Bit mask of CH12 field. /
jamesadevine	0:e1a608bb55e8	3994	#define PPI_CHEN_CH12_Disabled (0UL) /!< Channel disabled. /
jamesadevine	0:e1a608bb55e8	3995	#define PPI_CHEN_CH12_Enabled (1UL) /!< Channel enabled. /
jamesadevine	0:e1a608bb55e8	3996
jamesadevine	0:e1a608bb55e8	3997	/* Bit 11 : Enable PPI channel 11. */
jamesadevine	0:e1a608bb55e8	3998	#define PPI_CHEN_CH11_Pos (11UL) /!< Position of CH11 field. /
jamesadevine	0:e1a608bb55e8	3999	#define PPI_CHEN_CH11_Msk (0x1UL << PPI_CHEN_CH11_Pos) /!< Bit mask of CH11 field. /
jamesadevine	0:e1a608bb55e8	4000	#define PPI_CHEN_CH11_Disabled (0UL) /!< Channel disabled. /
jamesadevine	0:e1a608bb55e8	4001	#define PPI_CHEN_CH11_Enabled (1UL) /!< Channel enabled. /
jamesadevine	0:e1a608bb55e8	4002
jamesadevine	0:e1a608bb55e8	4003	/* Bit 10 : Enable PPI channel 10. */
jamesadevine	0:e1a608bb55e8	4004	#define PPI_CHEN_CH10_Pos (10UL) /!< Position of CH10 field. /
jamesadevine	0:e1a608bb55e8	4005	#define PPI_CHEN_CH10_Msk (0x1UL << PPI_CHEN_CH10_Pos) /!< Bit mask of CH10 field. /
jamesadevine	0:e1a608bb55e8	4006	#define PPI_CHEN_CH10_Disabled (0UL) /!< Channel disabled. /
jamesadevine	0:e1a608bb55e8	4007	#define PPI_CHEN_CH10_Enabled (1UL) /!< Channel enabled. /
jamesadevine	0:e1a608bb55e8	4008
jamesadevine	0:e1a608bb55e8	4009	/* Bit 9 : Enable PPI channel 9. */
jamesadevine	0:e1a608bb55e8	4010	#define PPI_CHEN_CH9_Pos (9UL) /!< Position of CH9 field. /
jamesadevine	0:e1a608bb55e8	4011	#define PPI_CHEN_CH9_Msk (0x1UL << PPI_CHEN_CH9_Pos) /!< Bit mask of CH9 field. /
jamesadevine	0:e1a608bb55e8	4012	#define PPI_CHEN_CH9_Disabled (0UL) /!< Channel disabled. /
jamesadevine	0:e1a608bb55e8	4013	#define PPI_CHEN_CH9_Enabled (1UL) /!< Channel enabled. /
jamesadevine	0:e1a608bb55e8	4014
jamesadevine	0:e1a608bb55e8	4015	/* Bit 8 : Enable PPI channel 8. */
jamesadevine	0:e1a608bb55e8	4016	#define PPI_CHEN_CH8_Pos (8UL) /!< Position of CH8 field. /
jamesadevine	0:e1a608bb55e8	4017	#define PPI_CHEN_CH8_Msk (0x1UL << PPI_CHEN_CH8_Pos) /!< Bit mask of CH8 field. /
jamesadevine	0:e1a608bb55e8	4018	#define PPI_CHEN_CH8_Disabled (0UL) /!< Channel disabled. /
jamesadevine	0:e1a608bb55e8	4019	#define PPI_CHEN_CH8_Enabled (1UL) /!< Channel enabled. /
jamesadevine	0:e1a608bb55e8	4020
jamesadevine	0:e1a608bb55e8	4021	/* Bit 7 : Enable PPI channel 7. */
jamesadevine	0:e1a608bb55e8	4022	#define PPI_CHEN_CH7_Pos (7UL) /!< Position of CH7 field. /
jamesadevine	0:e1a608bb55e8	4023	#define PPI_CHEN_CH7_Msk (0x1UL << PPI_CHEN_CH7_Pos) /!< Bit mask of CH7 field. /
jamesadevine	0:e1a608bb55e8	4024	#define PPI_CHEN_CH7_Disabled (0UL) /!< Channel disabled. /
jamesadevine	0:e1a608bb55e8	4025	#define PPI_CHEN_CH7_Enabled (1UL) /!< Channel enabled. /
jamesadevine	0:e1a608bb55e8	4026
jamesadevine	0:e1a608bb55e8	4027	/* Bit 6 : Enable PPI channel 6. */
jamesadevine	0:e1a608bb55e8	4028	#define PPI_CHEN_CH6_Pos (6UL) /!< Position of CH6 field. /
jamesadevine	0:e1a608bb55e8	4029	#define PPI_CHEN_CH6_Msk (0x1UL << PPI_CHEN_CH6_Pos) /!< Bit mask of CH6 field. /
jamesadevine	0:e1a608bb55e8	4030	#define PPI_CHEN_CH6_Disabled (0UL) /!< Channel disabled. /
jamesadevine	0:e1a608bb55e8	4031	#define PPI_CHEN_CH6_Enabled (1UL) /!< Channel enabled. /
jamesadevine	0:e1a608bb55e8	4032
jamesadevine	0:e1a608bb55e8	4033	/* Bit 5 : Enable PPI channel 5. */
jamesadevine	0:e1a608bb55e8	4034	#define PPI_CHEN_CH5_Pos (5UL) /!< Position of CH5 field. /
jamesadevine	0:e1a608bb55e8	4035	#define PPI_CHEN_CH5_Msk (0x1UL << PPI_CHEN_CH5_Pos) /!< Bit mask of CH5 field. /
jamesadevine	0:e1a608bb55e8	4036	#define PPI_CHEN_CH5_Disabled (0UL) /!< Channel disabled. /
jamesadevine	0:e1a608bb55e8	4037	#define PPI_CHEN_CH5_Enabled (1UL) /!< Channel enabled. /
jamesadevine	0:e1a608bb55e8	4038
jamesadevine	0:e1a608bb55e8	4039	/* Bit 4 : Enable PPI channel 4. */
jamesadevine	0:e1a608bb55e8	4040	#define PPI_CHEN_CH4_Pos (4UL) /!< Position of CH4 field. /
jamesadevine	0:e1a608bb55e8	4041	#define PPI_CHEN_CH4_Msk (0x1UL << PPI_CHEN_CH4_Pos) /!< Bit mask of CH4 field. /
jamesadevine	0:e1a608bb55e8	4042	#define PPI_CHEN_CH4_Disabled (0UL) /!< Channel disabled. /
jamesadevine	0:e1a608bb55e8	4043	#define PPI_CHEN_CH4_Enabled (1UL) /!< Channel enabled. /
jamesadevine	0:e1a608bb55e8	4044
jamesadevine	0:e1a608bb55e8	4045	/* Bit 3 : Enable PPI channel 3. */
jamesadevine	0:e1a608bb55e8	4046	#define PPI_CHEN_CH3_Pos (3UL) /!< Position of CH3 field. /
jamesadevine	0:e1a608bb55e8	4047	#define PPI_CHEN_CH3_Msk (0x1UL << PPI_CHEN_CH3_Pos) /!< Bit mask of CH3 field. /
jamesadevine	0:e1a608bb55e8	4048	#define PPI_CHEN_CH3_Disabled (0UL) /!< Channel disabled /
jamesadevine	0:e1a608bb55e8	4049	#define PPI_CHEN_CH3_Enabled (1UL) /!< Channel enabled /
jamesadevine	0:e1a608bb55e8	4050
jamesadevine	0:e1a608bb55e8	4051	/* Bit 2 : Enable PPI channel 2. */
jamesadevine	0:e1a608bb55e8	4052	#define PPI_CHEN_CH2_Pos (2UL) /!< Position of CH2 field. /
jamesadevine	0:e1a608bb55e8	4053	#define PPI_CHEN_CH2_Msk (0x1UL << PPI_CHEN_CH2_Pos) /!< Bit mask of CH2 field. /
jamesadevine	0:e1a608bb55e8	4054	#define PPI_CHEN_CH2_Disabled (0UL) /!< Channel disabled. /
jamesadevine	0:e1a608bb55e8	4055	#define PPI_CHEN_CH2_Enabled (1UL) /!< Channel enabled. /
jamesadevine	0:e1a608bb55e8	4056
jamesadevine	0:e1a608bb55e8	4057	/* Bit 1 : Enable PPI channel 1. */
jamesadevine	0:e1a608bb55e8	4058	#define PPI_CHEN_CH1_Pos (1UL) /!< Position of CH1 field. /
jamesadevine	0:e1a608bb55e8	4059	#define PPI_CHEN_CH1_Msk (0x1UL << PPI_CHEN_CH1_Pos) /!< Bit mask of CH1 field. /
jamesadevine	0:e1a608bb55e8	4060	#define PPI_CHEN_CH1_Disabled (0UL) /!< Channel disabled. /
jamesadevine	0:e1a608bb55e8	4061	#define PPI_CHEN_CH1_Enabled (1UL) /!< Channel enabled. /
jamesadevine	0:e1a608bb55e8	4062
jamesadevine	0:e1a608bb55e8	4063	/* Bit 0 : Enable PPI channel 0. */
jamesadevine	0:e1a608bb55e8	4064	#define PPI_CHEN_CH0_Pos (0UL) /!< Position of CH0 field. /
jamesadevine	0:e1a608bb55e8	4065	#define PPI_CHEN_CH0_Msk (0x1UL << PPI_CHEN_CH0_Pos) /!< Bit mask of CH0 field. /
jamesadevine	0:e1a608bb55e8	4066	#define PPI_CHEN_CH0_Disabled (0UL) /!< Channel disabled. /
jamesadevine	0:e1a608bb55e8	4067	#define PPI_CHEN_CH0_Enabled (1UL) /!< Channel enabled. /
jamesadevine	0:e1a608bb55e8	4068
jamesadevine	0:e1a608bb55e8	4069	/* Register: PPI_CHENSET */
jamesadevine	0:e1a608bb55e8	4070	/* Description: Channel enable set. */
jamesadevine	0:e1a608bb55e8	4071
jamesadevine	0:e1a608bb55e8	4072	/* Bit 31 : Enable PPI channel 31. */
jamesadevine	0:e1a608bb55e8	4073	#define PPI_CHENSET_CH31_Pos (31UL) /!< Position of CH31 field. /
jamesadevine	0:e1a608bb55e8	4074	#define PPI_CHENSET_CH31_Msk (0x1UL << PPI_CHENSET_CH31_Pos) /!< Bit mask of CH31 field. /
jamesadevine	0:e1a608bb55e8	4075	#define PPI_CHENSET_CH31_Disabled (0UL) /!< Channel disabled. /
jamesadevine	0:e1a608bb55e8	4076	#define PPI_CHENSET_CH31_Enabled (1UL) /!< Channel enabled. /
jamesadevine	0:e1a608bb55e8	4077	#define PPI_CHENSET_CH31_Set (1UL) /!< Enable channel on write. /
jamesadevine	0:e1a608bb55e8	4078
jamesadevine	0:e1a608bb55e8	4079	/* Bit 30 : Enable PPI channel 30. */
jamesadevine	0:e1a608bb55e8	4080	#define PPI_CHENSET_CH30_Pos (30UL) /!< Position of CH30 field. /
jamesadevine	0:e1a608bb55e8	4081	#define PPI_CHENSET_CH30_Msk (0x1UL << PPI_CHENSET_CH30_Pos) /!< Bit mask of CH30 field. /
jamesadevine	0:e1a608bb55e8	4082	#define PPI_CHENSET_CH30_Disabled (0UL) /!< Channel disabled. /
jamesadevine	0:e1a608bb55e8	4083	#define PPI_CHENSET_CH30_Enabled (1UL) /!< Channel enabled. /
jamesadevine	0:e1a608bb55e8	4084	#define PPI_CHENSET_CH30_Set (1UL) /!< Enable channel on write. /
jamesadevine	0:e1a608bb55e8	4085
jamesadevine	0:e1a608bb55e8	4086	/* Bit 29 : Enable PPI channel 29. */
jamesadevine	0:e1a608bb55e8	4087	#define PPI_CHENSET_CH29_Pos (29UL) /!< Position of CH29 field. /
jamesadevine	0:e1a608bb55e8	4088	#define PPI_CHENSET_CH29_Msk (0x1UL << PPI_CHENSET_CH29_Pos) /!< Bit mask of CH29 field. /
jamesadevine	0:e1a608bb55e8	4089	#define PPI_CHENSET_CH29_Disabled (0UL) /!< Channel disabled. /
jamesadevine	0:e1a608bb55e8	4090	#define PPI_CHENSET_CH29_Enabled (1UL) /!< Channel enabled. /
jamesadevine	0:e1a608bb55e8	4091	#define PPI_CHENSET_CH29_Set (1UL) /!< Enable channel on write. /
jamesadevine	0:e1a608bb55e8	4092
jamesadevine	0:e1a608bb55e8	4093	/* Bit 28 : Enable PPI channel 28. */
jamesadevine	0:e1a608bb55e8	4094	#define PPI_CHENSET_CH28_Pos (28UL) /!< Position of CH28 field. /
jamesadevine	0:e1a608bb55e8	4095	#define PPI_CHENSET_CH28_Msk (0x1UL << PPI_CHENSET_CH28_Pos) /!< Bit mask of CH28 field. /
jamesadevine	0:e1a608bb55e8	4096	#define PPI_CHENSET_CH28_Disabled (0UL) /!< Channel disabled. /
jamesadevine	0:e1a608bb55e8	4097	#define PPI_CHENSET_CH28_Enabled (1UL) /!< Channel enabled. /
jamesadevine	0:e1a608bb55e8	4098	#define PPI_CHENSET_CH28_Set (1UL) /!< Enable channel on write. /
jamesadevine	0:e1a608bb55e8	4099
jamesadevine	0:e1a608bb55e8	4100	/* Bit 27 : Enable PPI channel 27. */
jamesadevine	0:e1a608bb55e8	4101	#define PPI_CHENSET_CH27_Pos (27UL) /!< Position of CH27 field. /
jamesadevine	0:e1a608bb55e8	4102	#define PPI_CHENSET_CH27_Msk (0x1UL << PPI_CHENSET_CH27_Pos) /!< Bit mask of CH27 field. /
jamesadevine	0:e1a608bb55e8	4103	#define PPI_CHENSET_CH27_Disabled (0UL) /!< Channel disabled. /
jamesadevine	0:e1a608bb55e8	4104	#define PPI_CHENSET_CH27_Enabled (1UL) /!< Channel enabled. /
jamesadevine	0:e1a608bb55e8	4105	#define PPI_CHENSET_CH27_Set (1UL) /!< Enable channel on write. /
jamesadevine	0:e1a608bb55e8	4106
jamesadevine	0:e1a608bb55e8	4107	/* Bit 26 : Enable PPI channel 26. */
jamesadevine	0:e1a608bb55e8	4108	#define PPI_CHENSET_CH26_Pos (26UL) /!< Position of CH26 field. /
jamesadevine	0:e1a608bb55e8	4109	#define PPI_CHENSET_CH26_Msk (0x1UL << PPI_CHENSET_CH26_Pos) /!< Bit mask of CH26 field. /
jamesadevine	0:e1a608bb55e8	4110	#define PPI_CHENSET_CH26_Disabled (0UL) /!< Channel disabled. /
jamesadevine	0:e1a608bb55e8	4111	#define PPI_CHENSET_CH26_Enabled (1UL) /!< Channel enabled. /
jamesadevine	0:e1a608bb55e8	4112	#define PPI_CHENSET_CH26_Set (1UL) /!< Enable channel on write. /
jamesadevine	0:e1a608bb55e8	4113
jamesadevine	0:e1a608bb55e8	4114	/* Bit 25 : Enable PPI channel 25. */
jamesadevine	0:e1a608bb55e8	4115	#define PPI_CHENSET_CH25_Pos (25UL) /!< Position of CH25 field. /
jamesadevine	0:e1a608bb55e8	4116	#define PPI_CHENSET_CH25_Msk (0x1UL << PPI_CHENSET_CH25_Pos) /!< Bit mask of CH25 field. /
jamesadevine	0:e1a608bb55e8	4117	#define PPI_CHENSET_CH25_Disabled (0UL) /!< Channel disabled. /
jamesadevine	0:e1a608bb55e8	4118	#define PPI_CHENSET_CH25_Enabled (1UL) /!< Channel enabled. /
jamesadevine	0:e1a608bb55e8	4119	#define PPI_CHENSET_CH25_Set (1UL) /!< Enable channel on write. /
jamesadevine	0:e1a608bb55e8	4120
jamesadevine	0:e1a608bb55e8	4121	/* Bit 24 : Enable PPI channel 24. */
jamesadevine	0:e1a608bb55e8	4122	#define PPI_CHENSET_CH24_Pos (24UL) /!< Position of CH24 field. /
jamesadevine	0:e1a608bb55e8	4123	#define PPI_CHENSET_CH24_Msk (0x1UL << PPI_CHENSET_CH24_Pos) /!< Bit mask of CH24 field. /
jamesadevine	0:e1a608bb55e8	4124	#define PPI_CHENSET_CH24_Disabled (0UL) /!< Channel disabled. /
jamesadevine	0:e1a608bb55e8	4125	#define PPI_CHENSET_CH24_Enabled (1UL) /!< Channel enabled. /
jamesadevine	0:e1a608bb55e8	4126	#define PPI_CHENSET_CH24_Set (1UL) /!< Enable channel on write. /
jamesadevine	0:e1a608bb55e8	4127
jamesadevine	0:e1a608bb55e8	4128	/* Bit 23 : Enable PPI channel 23. */
jamesadevine	0:e1a608bb55e8	4129	#define PPI_CHENSET_CH23_Pos (23UL) /!< Position of CH23 field. /
jamesadevine	0:e1a608bb55e8	4130	#define PPI_CHENSET_CH23_Msk (0x1UL << PPI_CHENSET_CH23_Pos) /!< Bit mask of CH23 field. /
jamesadevine	0:e1a608bb55e8	4131	#define PPI_CHENSET_CH23_Disabled (0UL) /!< Channel disabled. /
jamesadevine	0:e1a608bb55e8	4132	#define PPI_CHENSET_CH23_Enabled (1UL) /!< Channel enabled. /
jamesadevine	0:e1a608bb55e8	4133	#define PPI_CHENSET_CH23_Set (1UL) /!< Enable channel on write. /
jamesadevine	0:e1a608bb55e8	4134
jamesadevine	0:e1a608bb55e8	4135	/* Bit 22 : Enable PPI channel 22. */
jamesadevine	0:e1a608bb55e8	4136	#define PPI_CHENSET_CH22_Pos (22UL) /!< Position of CH22 field. /
jamesadevine	0:e1a608bb55e8	4137	#define PPI_CHENSET_CH22_Msk (0x1UL << PPI_CHENSET_CH22_Pos) /!< Bit mask of CH22 field. /
jamesadevine	0:e1a608bb55e8	4138	#define PPI_CHENSET_CH22_Disabled (0UL) /!< Channel disabled. /
jamesadevine	0:e1a608bb55e8	4139	#define PPI_CHENSET_CH22_Enabled (1UL) /!< Channel enabled. /
jamesadevine	0:e1a608bb55e8	4140	#define PPI_CHENSET_CH22_Set (1UL) /!< Enable channel on write. /
jamesadevine	0:e1a608bb55e8	4141
jamesadevine	0:e1a608bb55e8	4142	/* Bit 21 : Enable PPI channel 21. */
jamesadevine	0:e1a608bb55e8	4143	#define PPI_CHENSET_CH21_Pos (21UL) /!< Position of CH21 field. /
jamesadevine	0:e1a608bb55e8	4144	#define PPI_CHENSET_CH21_Msk (0x1UL << PPI_CHENSET_CH21_Pos) /!< Bit mask of CH21 field. /
jamesadevine	0:e1a608bb55e8	4145	#define PPI_CHENSET_CH21_Disabled (0UL) /!< Channel disabled. /
jamesadevine	0:e1a608bb55e8	4146	#define PPI_CHENSET_CH21_Enabled (1UL) /!< Channel enabled. /
jamesadevine	0:e1a608bb55e8	4147	#define PPI_CHENSET_CH21_Set (1UL) /!< Enable channel on write. /
jamesadevine	0:e1a608bb55e8	4148
jamesadevine	0:e1a608bb55e8	4149	/* Bit 20 : Enable PPI channel 20. */
jamesadevine	0:e1a608bb55e8	4150	#define PPI_CHENSET_CH20_Pos (20UL) /!< Position of CH20 field. /
jamesadevine	0:e1a608bb55e8	4151	#define PPI_CHENSET_CH20_Msk (0x1UL << PPI_CHENSET_CH20_Pos) /!< Bit mask of CH20 field. /
jamesadevine	0:e1a608bb55e8	4152	#define PPI_CHENSET_CH20_Disabled (0UL) /!< Channel disabled. /
jamesadevine	0:e1a608bb55e8	4153	#define PPI_CHENSET_CH20_Enabled (1UL) /!< Channel enabled. /
jamesadevine	0:e1a608bb55e8	4154	#define PPI_CHENSET_CH20_Set (1UL) /!< Enable channel on write. /
jamesadevine	0:e1a608bb55e8	4155
jamesadevine	0:e1a608bb55e8	4156	/* Bit 15 : Enable PPI channel 15. */
jamesadevine	0:e1a608bb55e8	4157	#define PPI_CHENSET_CH15_Pos (15UL) /!< Position of CH15 field. /
jamesadevine	0:e1a608bb55e8	4158	#define PPI_CHENSET_CH15_Msk (0x1UL << PPI_CHENSET_CH15_Pos) /!< Bit mask of CH15 field. /
jamesadevine	0:e1a608bb55e8	4159	#define PPI_CHENSET_CH15_Disabled (0UL) /!< Channel disabled. /
jamesadevine	0:e1a608bb55e8	4160	#define PPI_CHENSET_CH15_Enabled (1UL) /!< Channel enabled. /
jamesadevine	0:e1a608bb55e8	4161	#define PPI_CHENSET_CH15_Set (1UL) /!< Enable channel on write. /
jamesadevine	0:e1a608bb55e8	4162
jamesadevine	0:e1a608bb55e8	4163	/* Bit 14 : Enable PPI channel 14. */
jamesadevine	0:e1a608bb55e8	4164	#define PPI_CHENSET_CH14_Pos (14UL) /!< Position of CH14 field. /
jamesadevine	0:e1a608bb55e8	4165	#define PPI_CHENSET_CH14_Msk (0x1UL << PPI_CHENSET_CH14_Pos) /!< Bit mask of CH14 field. /
jamesadevine	0:e1a608bb55e8	4166	#define PPI_CHENSET_CH14_Disabled (0UL) /!< Channel disabled. /
jamesadevine	0:e1a608bb55e8	4167	#define PPI_CHENSET_CH14_Enabled (1UL) /!< Channel enabled. /
jamesadevine	0:e1a608bb55e8	4168	#define PPI_CHENSET_CH14_Set (1UL) /!< Enable channel on write. /
jamesadevine	0:e1a608bb55e8	4169
jamesadevine	0:e1a608bb55e8	4170	/* Bit 13 : Enable PPI channel 13. */
jamesadevine	0:e1a608bb55e8	4171	#define PPI_CHENSET_CH13_Pos (13UL) /!< Position of CH13 field. /
jamesadevine	0:e1a608bb55e8	4172	#define PPI_CHENSET_CH13_Msk (0x1UL << PPI_CHENSET_CH13_Pos) /!< Bit mask of CH13 field. /
jamesadevine	0:e1a608bb55e8	4173	#define PPI_CHENSET_CH13_Disabled (0UL) /!< Channel disabled. /
jamesadevine	0:e1a608bb55e8	4174	#define PPI_CHENSET_CH13_Enabled (1UL) /!< Channel enabled. /
jamesadevine	0:e1a608bb55e8	4175	#define PPI_CHENSET_CH13_Set (1UL) /!< Enable channel on write. /
jamesadevine	0:e1a608bb55e8	4176
jamesadevine	0:e1a608bb55e8	4177	/* Bit 12 : Enable PPI channel 12. */
jamesadevine	0:e1a608bb55e8	4178	#define PPI_CHENSET_CH12_Pos (12UL) /!< Position of CH12 field. /
jamesadevine	0:e1a608bb55e8	4179	#define PPI_CHENSET_CH12_Msk (0x1UL << PPI_CHENSET_CH12_Pos) /!< Bit mask of CH12 field. /
jamesadevine	0:e1a608bb55e8	4180	#define PPI_CHENSET_CH12_Disabled (0UL) /!< Channel disabled. /
jamesadevine	0:e1a608bb55e8	4181	#define PPI_CHENSET_CH12_Enabled (1UL) /!< Channel enabled. /
jamesadevine	0:e1a608bb55e8	4182	#define PPI_CHENSET_CH12_Set (1UL) /!< Enable channel on write. /
jamesadevine	0:e1a608bb55e8	4183
jamesadevine	0:e1a608bb55e8	4184	/* Bit 11 : Enable PPI channel 11. */
jamesadevine	0:e1a608bb55e8	4185	#define PPI_CHENSET_CH11_Pos (11UL) /!< Position of CH11 field. /
jamesadevine	0:e1a608bb55e8	4186	#define PPI_CHENSET_CH11_Msk (0x1UL << PPI_CHENSET_CH11_Pos) /!< Bit mask of CH11 field. /
jamesadevine	0:e1a608bb55e8	4187	#define PPI_CHENSET_CH11_Disabled (0UL) /!< Channel disabled. /
jamesadevine	0:e1a608bb55e8	4188	#define PPI_CHENSET_CH11_Enabled (1UL) /!< Channel enabled. /
jamesadevine	0:e1a608bb55e8	4189	#define PPI_CHENSET_CH11_Set (1UL) /!< Enable channel on write. /
jamesadevine	0:e1a608bb55e8	4190
jamesadevine	0:e1a608bb55e8	4191	/* Bit 10 : Enable PPI channel 10. */
jamesadevine	0:e1a608bb55e8	4192	#define PPI_CHENSET_CH10_Pos (10UL) /!< Position of CH10 field. /
jamesadevine	0:e1a608bb55e8	4193	#define PPI_CHENSET_CH10_Msk (0x1UL << PPI_CHENSET_CH10_Pos) /!< Bit mask of CH10 field. /
jamesadevine	0:e1a608bb55e8	4194	#define PPI_CHENSET_CH10_Disabled (0UL) /!< Channel disabled. /
jamesadevine	0:e1a608bb55e8	4195	#define PPI_CHENSET_CH10_Enabled (1UL) /!< Channel enabled. /
jamesadevine	0:e1a608bb55e8	4196	#define PPI_CHENSET_CH10_Set (1UL) /!< Enable channel on write. /
jamesadevine	0:e1a608bb55e8	4197
jamesadevine	0:e1a608bb55e8	4198	/* Bit 9 : Enable PPI channel 9. */
jamesadevine	0:e1a608bb55e8	4199	#define PPI_CHENSET_CH9_Pos (9UL) /!< Position of CH9 field. /
jamesadevine	0:e1a608bb55e8	4200	#define PPI_CHENSET_CH9_Msk (0x1UL << PPI_CHENSET_CH9_Pos) /!< Bit mask of CH9 field. /
jamesadevine	0:e1a608bb55e8	4201	#define PPI_CHENSET_CH9_Disabled (0UL) /!< Channel disabled. /
jamesadevine	0:e1a608bb55e8	4202	#define PPI_CHENSET_CH9_Enabled (1UL) /!< Channel enabled. /
jamesadevine	0:e1a608bb55e8	4203	#define PPI_CHENSET_CH9_Set (1UL) /!< Enable channel on write. /
jamesadevine	0:e1a608bb55e8	4204
jamesadevine	0:e1a608bb55e8	4205	/* Bit 8 : Enable PPI channel 8. */
jamesadevine	0:e1a608bb55e8	4206	#define PPI_CHENSET_CH8_Pos (8UL) /!< Position of CH8 field. /
jamesadevine	0:e1a608bb55e8	4207	#define PPI_CHENSET_CH8_Msk (0x1UL << PPI_CHENSET_CH8_Pos) /!< Bit mask of CH8 field. /
jamesadevine	0:e1a608bb55e8	4208	#define PPI_CHENSET_CH8_Disabled (0UL) /!< Channel disabled. /
jamesadevine	0:e1a608bb55e8	4209	#define PPI_CHENSET_CH8_Enabled (1UL) /!< Channel enabled. /
jamesadevine	0:e1a608bb55e8	4210	#define PPI_CHENSET_CH8_Set (1UL) /!< Enable channel on write. /
jamesadevine	0:e1a608bb55e8	4211
jamesadevine	0:e1a608bb55e8	4212	/* Bit 7 : Enable PPI channel 7. */
jamesadevine	0:e1a608bb55e8	4213	#define PPI_CHENSET_CH7_Pos (7UL) /!< Position of CH7 field. /
jamesadevine	0:e1a608bb55e8	4214	#define PPI_CHENSET_CH7_Msk (0x1UL << PPI_CHENSET_CH7_Pos) /!< Bit mask of CH7 field. /
jamesadevine	0:e1a608bb55e8	4215	#define PPI_CHENSET_CH7_Disabled (0UL) /!< Channel disabled. /
jamesadevine	0:e1a608bb55e8	4216	#define PPI_CHENSET_CH7_Enabled (1UL) /!< Channel enabled. /
jamesadevine	0:e1a608bb55e8	4217	#define PPI_CHENSET_CH7_Set (1UL) /!< Enable channel on write. /
jamesadevine	0:e1a608bb55e8	4218
jamesadevine	0:e1a608bb55e8	4219	/* Bit 6 : Enable PPI channel 6. */
jamesadevine	0:e1a608bb55e8	4220	#define PPI_CHENSET_CH6_Pos (6UL) /!< Position of CH6 field. /
jamesadevine	0:e1a608bb55e8	4221	#define PPI_CHENSET_CH6_Msk (0x1UL << PPI_CHENSET_CH6_Pos) /!< Bit mask of CH6 field. /
jamesadevine	0:e1a608bb55e8	4222	#define PPI_CHENSET_CH6_Disabled (0UL) /!< Channel disabled. /
jamesadevine	0:e1a608bb55e8	4223	#define PPI_CHENSET_CH6_Enabled (1UL) /!< Channel enabled. /
jamesadevine	0:e1a608bb55e8	4224	#define PPI_CHENSET_CH6_Set (1UL) /!< Enable channel on write. /
jamesadevine	0:e1a608bb55e8	4225
jamesadevine	0:e1a608bb55e8	4226	/* Bit 5 : Enable PPI channel 5. */
jamesadevine	0:e1a608bb55e8	4227	#define PPI_CHENSET_CH5_Pos (5UL) /!< Position of CH5 field. /
jamesadevine	0:e1a608bb55e8	4228	#define PPI_CHENSET_CH5_Msk (0x1UL << PPI_CHENSET_CH5_Pos) /!< Bit mask of CH5 field. /
jamesadevine	0:e1a608bb55e8	4229	#define PPI_CHENSET_CH5_Disabled (0UL) /!< Channel disabled. /
jamesadevine	0:e1a608bb55e8	4230	#define PPI_CHENSET_CH5_Enabled (1UL) /!< Channel enabled. /
jamesadevine	0:e1a608bb55e8	4231	#define PPI_CHENSET_CH5_Set (1UL) /!< Enable channel on write. /
jamesadevine	0:e1a608bb55e8	4232
jamesadevine	0:e1a608bb55e8	4233	/* Bit 4 : Enable PPI channel 4. */
jamesadevine	0:e1a608bb55e8	4234	#define PPI_CHENSET_CH4_Pos (4UL) /!< Position of CH4 field. /
jamesadevine	0:e1a608bb55e8	4235	#define PPI_CHENSET_CH4_Msk (0x1UL << PPI_CHENSET_CH4_Pos) /!< Bit mask of CH4 field. /
jamesadevine	0:e1a608bb55e8	4236	#define PPI_CHENSET_CH4_Disabled (0UL) /!< Channel disabled. /
jamesadevine	0:e1a608bb55e8	4237	#define PPI_CHENSET_CH4_Enabled (1UL) /!< Channel enabled. /
jamesadevine	0:e1a608bb55e8	4238	#define PPI_CHENSET_CH4_Set (1UL) /!< Enable channel on write. /
jamesadevine	0:e1a608bb55e8	4239
jamesadevine	0:e1a608bb55e8	4240	/* Bit 3 : Enable PPI channel 3. */
jamesadevine	0:e1a608bb55e8	4241	#define PPI_CHENSET_CH3_Pos (3UL) /!< Position of CH3 field. /
jamesadevine	0:e1a608bb55e8	4242	#define PPI_CHENSET_CH3_Msk (0x1UL << PPI_CHENSET_CH3_Pos) /!< Bit mask of CH3 field. /
jamesadevine	0:e1a608bb55e8	4243	#define PPI_CHENSET_CH3_Disabled (0UL) /!< Channel disabled. /
jamesadevine	0:e1a608bb55e8	4244	#define PPI_CHENSET_CH3_Enabled (1UL) /!< Channel enabled. /
jamesadevine	0:e1a608bb55e8	4245	#define PPI_CHENSET_CH3_Set (1UL) /!< Enable channel on write. /
jamesadevine	0:e1a608bb55e8	4246
jamesadevine	0:e1a608bb55e8	4247	/* Bit 2 : Enable PPI channel 2. */
jamesadevine	0:e1a608bb55e8	4248	#define PPI_CHENSET_CH2_Pos (2UL) /!< Position of CH2 field. /
jamesadevine	0:e1a608bb55e8	4249	#define PPI_CHENSET_CH2_Msk (0x1UL << PPI_CHENSET_CH2_Pos) /!< Bit mask of CH2 field. /
jamesadevine	0:e1a608bb55e8	4250	#define PPI_CHENSET_CH2_Disabled (0UL) /!< Channel disabled. /
jamesadevine	0:e1a608bb55e8	4251	#define PPI_CHENSET_CH2_Enabled (1UL) /!< Channel enabled. /
jamesadevine	0:e1a608bb55e8	4252	#define PPI_CHENSET_CH2_Set (1UL) /!< Enable channel on write. /
jamesadevine	0:e1a608bb55e8	4253
jamesadevine	0:e1a608bb55e8	4254	/* Bit 1 : Enable PPI channel 1. */
jamesadevine	0:e1a608bb55e8	4255	#define PPI_CHENSET_CH1_Pos (1UL) /!< Position of CH1 field. /
jamesadevine	0:e1a608bb55e8	4256	#define PPI_CHENSET_CH1_Msk (0x1UL << PPI_CHENSET_CH1_Pos) /!< Bit mask of CH1 field. /
jamesadevine	0:e1a608bb55e8	4257	#define PPI_CHENSET_CH1_Disabled (0UL) /!< Channel disabled. /
jamesadevine	0:e1a608bb55e8	4258	#define PPI_CHENSET_CH1_Enabled (1UL) /!< Channel enabled. /
jamesadevine	0:e1a608bb55e8	4259	#define PPI_CHENSET_CH1_Set (1UL) /!< Enable channel on write. /
jamesadevine	0:e1a608bb55e8	4260
jamesadevine	0:e1a608bb55e8	4261	/* Bit 0 : Enable PPI channel 0. */
jamesadevine	0:e1a608bb55e8	4262	#define PPI_CHENSET_CH0_Pos (0UL) /!< Position of CH0 field. /
jamesadevine	0:e1a608bb55e8	4263	#define PPI_CHENSET_CH0_Msk (0x1UL << PPI_CHENSET_CH0_Pos) /!< Bit mask of CH0 field. /
jamesadevine	0:e1a608bb55e8	4264	#define PPI_CHENSET_CH0_Disabled (0UL) /!< Channel disabled. /
jamesadevine	0:e1a608bb55e8	4265	#define PPI_CHENSET_CH0_Enabled (1UL) /!< Channel enabled. /
jamesadevine	0:e1a608bb55e8	4266	#define PPI_CHENSET_CH0_Set (1UL) /!< Enable channel on write. /
jamesadevine	0:e1a608bb55e8	4267
jamesadevine	0:e1a608bb55e8	4268	/* Register: PPI_CHENCLR */
jamesadevine	0:e1a608bb55e8	4269	/* Description: Channel enable clear. */
jamesadevine	0:e1a608bb55e8	4270
jamesadevine	0:e1a608bb55e8	4271	/* Bit 31 : Disable PPI channel 31. */
jamesadevine	0:e1a608bb55e8	4272	#define PPI_CHENCLR_CH31_Pos (31UL) /!< Position of CH31 field. /
jamesadevine	0:e1a608bb55e8	4273	#define PPI_CHENCLR_CH31_Msk (0x1UL << PPI_CHENCLR_CH31_Pos) /!< Bit mask of CH31 field. /
jamesadevine	0:e1a608bb55e8	4274	#define PPI_CHENCLR_CH31_Disabled (0UL) /!< Channel disabled. /
jamesadevine	0:e1a608bb55e8	4275	#define PPI_CHENCLR_CH31_Enabled (1UL) /!< Channel enabled. /
jamesadevine	0:e1a608bb55e8	4276	#define PPI_CHENCLR_CH31_Clear (1UL) /!< Disable channel on write. /
jamesadevine	0:e1a608bb55e8	4277
jamesadevine	0:e1a608bb55e8	4278	/* Bit 30 : Disable PPI channel 30. */
jamesadevine	0:e1a608bb55e8	4279	#define PPI_CHENCLR_CH30_Pos (30UL) /!< Position of CH30 field. /
jamesadevine	0:e1a608bb55e8	4280	#define PPI_CHENCLR_CH30_Msk (0x1UL << PPI_CHENCLR_CH30_Pos) /!< Bit mask of CH30 field. /
jamesadevine	0:e1a608bb55e8	4281	#define PPI_CHENCLR_CH30_Disabled (0UL) /!< Channel disabled. /
jamesadevine	0:e1a608bb55e8	4282	#define PPI_CHENCLR_CH30_Enabled (1UL) /!< Channel enabled. /
jamesadevine	0:e1a608bb55e8	4283	#define PPI_CHENCLR_CH30_Clear (1UL) /!< Disable channel on write. /
jamesadevine	0:e1a608bb55e8	4284
jamesadevine	0:e1a608bb55e8	4285	/* Bit 29 : Disable PPI channel 29. */
jamesadevine	0:e1a608bb55e8	4286	#define PPI_CHENCLR_CH29_Pos (29UL) /!< Position of CH29 field. /
jamesadevine	0:e1a608bb55e8	4287	#define PPI_CHENCLR_CH29_Msk (0x1UL << PPI_CHENCLR_CH29_Pos) /!< Bit mask of CH29 field. /
jamesadevine	0:e1a608bb55e8	4288	#define PPI_CHENCLR_CH29_Disabled (0UL) /!< Channel disabled. /
jamesadevine	0:e1a608bb55e8	4289	#define PPI_CHENCLR_CH29_Enabled (1UL) /!< Channel enabled. /
jamesadevine	0:e1a608bb55e8	4290	#define PPI_CHENCLR_CH29_Clear (1UL) /!< Disable channel on write. /
jamesadevine	0:e1a608bb55e8	4291
jamesadevine	0:e1a608bb55e8	4292	/* Bit 28 : Disable PPI channel 28. */
jamesadevine	0:e1a608bb55e8	4293	#define PPI_CHENCLR_CH28_Pos (28UL) /!< Position of CH28 field. /
jamesadevine	0:e1a608bb55e8	4294	#define PPI_CHENCLR_CH28_Msk (0x1UL << PPI_CHENCLR_CH28_Pos) /!< Bit mask of CH28 field. /
jamesadevine	0:e1a608bb55e8	4295	#define PPI_CHENCLR_CH28_Disabled (0UL) /!< Channel disabled. /
jamesadevine	0:e1a608bb55e8	4296	#define PPI_CHENCLR_CH28_Enabled (1UL) /!< Channel enabled. /
jamesadevine	0:e1a608bb55e8	4297	#define PPI_CHENCLR_CH28_Clear (1UL) /!< Disable channel on write. /
jamesadevine	0:e1a608bb55e8	4298
jamesadevine	0:e1a608bb55e8	4299	/* Bit 27 : Disable PPI channel 27. */
jamesadevine	0:e1a608bb55e8	4300	#define PPI_CHENCLR_CH27_Pos (27UL) /!< Position of CH27 field. /
jamesadevine	0:e1a608bb55e8	4301	#define PPI_CHENCLR_CH27_Msk (0x1UL << PPI_CHENCLR_CH27_Pos) /!< Bit mask of CH27 field. /
jamesadevine	0:e1a608bb55e8	4302	#define PPI_CHENCLR_CH27_Disabled (0UL) /!< Channel disabled. /
jamesadevine	0:e1a608bb55e8	4303	#define PPI_CHENCLR_CH27_Enabled (1UL) /!< Channel enabled. /
jamesadevine	0:e1a608bb55e8	4304	#define PPI_CHENCLR_CH27_Clear (1UL) /!< Disable channel on write. /
jamesadevine	0:e1a608bb55e8	4305
jamesadevine	0:e1a608bb55e8	4306	/* Bit 26 : Disable PPI channel 26. */
jamesadevine	0:e1a608bb55e8	4307	#define PPI_CHENCLR_CH26_Pos (26UL) /!< Position of CH26 field. /
jamesadevine	0:e1a608bb55e8	4308	#define PPI_CHENCLR_CH26_Msk (0x1UL << PPI_CHENCLR_CH26_Pos) /!< Bit mask of CH26 field. /
jamesadevine	0:e1a608bb55e8	4309	#define PPI_CHENCLR_CH26_Disabled (0UL) /!< Channel disabled. /
jamesadevine	0:e1a608bb55e8	4310	#define PPI_CHENCLR_CH26_Enabled (1UL) /!< Channel enabled. /
jamesadevine	0:e1a608bb55e8	4311	#define PPI_CHENCLR_CH26_Clear (1UL) /!< Disable channel on write. /
jamesadevine	0:e1a608bb55e8	4312
jamesadevine	0:e1a608bb55e8	4313	/* Bit 25 : Disable PPI channel 25. */
jamesadevine	0:e1a608bb55e8	4314	#define PPI_CHENCLR_CH25_Pos (25UL) /!< Position of CH25 field. /
jamesadevine	0:e1a608bb55e8	4315	#define PPI_CHENCLR_CH25_Msk (0x1UL << PPI_CHENCLR_CH25_Pos) /!< Bit mask of CH25 field. /
jamesadevine	0:e1a608bb55e8	4316	#define PPI_CHENCLR_CH25_Disabled (0UL) /!< Channel disabled. /
jamesadevine	0:e1a608bb55e8	4317	#define PPI_CHENCLR_CH25_Enabled (1UL) /!< Channel enabled. /
jamesadevine	0:e1a608bb55e8	4318	#define PPI_CHENCLR_CH25_Clear (1UL) /!< Disable channel on write. /
jamesadevine	0:e1a608bb55e8	4319
jamesadevine	0:e1a608bb55e8	4320	/* Bit 24 : Disable PPI channel 24. */
jamesadevine	0:e1a608bb55e8	4321	#define PPI_CHENCLR_CH24_Pos (24UL) /!< Position of CH24 field. /
jamesadevine	0:e1a608bb55e8	4322	#define PPI_CHENCLR_CH24_Msk (0x1UL << PPI_CHENCLR_CH24_Pos) /!< Bit mask of CH24 field. /
jamesadevine	0:e1a608bb55e8	4323	#define PPI_CHENCLR_CH24_Disabled (0UL) /!< Channel disabled. /
jamesadevine	0:e1a608bb55e8	4324	#define PPI_CHENCLR_CH24_Enabled (1UL) /!< Channel enabled. /
jamesadevine	0:e1a608bb55e8	4325	#define PPI_CHENCLR_CH24_Clear (1UL) /!< Disable channel on write. /
jamesadevine	0:e1a608bb55e8	4326
jamesadevine	0:e1a608bb55e8	4327	/* Bit 23 : Disable PPI channel 23. */
jamesadevine	0:e1a608bb55e8	4328	#define PPI_CHENCLR_CH23_Pos (23UL) /!< Position of CH23 field. /
jamesadevine	0:e1a608bb55e8	4329	#define PPI_CHENCLR_CH23_Msk (0x1UL << PPI_CHENCLR_CH23_Pos) /!< Bit mask of CH23 field. /
jamesadevine	0:e1a608bb55e8	4330	#define PPI_CHENCLR_CH23_Disabled (0UL) /!< Channel disabled. /
jamesadevine	0:e1a608bb55e8	4331	#define PPI_CHENCLR_CH23_Enabled (1UL) /!< Channel enabled. /
jamesadevine	0:e1a608bb55e8	4332	#define PPI_CHENCLR_CH23_Clear (1UL) /!< Disable channel on write. /
jamesadevine	0:e1a608bb55e8	4333
jamesadevine	0:e1a608bb55e8	4334	/* Bit 22 : Disable PPI channel 22. */
jamesadevine	0:e1a608bb55e8	4335	#define PPI_CHENCLR_CH22_Pos (22UL) /!< Position of CH22 field. /
jamesadevine	0:e1a608bb55e8	4336	#define PPI_CHENCLR_CH22_Msk (0x1UL << PPI_CHENCLR_CH22_Pos) /!< Bit mask of CH22 field. /
jamesadevine	0:e1a608bb55e8	4337	#define PPI_CHENCLR_CH22_Disabled (0UL) /!< Channel disabled. /
jamesadevine	0:e1a608bb55e8	4338	#define PPI_CHENCLR_CH22_Enabled (1UL) /!< Channel enabled. /
jamesadevine	0:e1a608bb55e8	4339	#define PPI_CHENCLR_CH22_Clear (1UL) /!< Disable channel on write. /
jamesadevine	0:e1a608bb55e8	4340
jamesadevine	0:e1a608bb55e8	4341	/* Bit 21 : Disable PPI channel 21. */
jamesadevine	0:e1a608bb55e8	4342	#define PPI_CHENCLR_CH21_Pos (21UL) /!< Position of CH21 field. /
jamesadevine	0:e1a608bb55e8	4343	#define PPI_CHENCLR_CH21_Msk (0x1UL << PPI_CHENCLR_CH21_Pos) /!< Bit mask of CH21 field. /
jamesadevine	0:e1a608bb55e8	4344	#define PPI_CHENCLR_CH21_Disabled (0UL) /!< Channel disabled. /
jamesadevine	0:e1a608bb55e8	4345	#define PPI_CHENCLR_CH21_Enabled (1UL) /!< Channel enabled. /
jamesadevine	0:e1a608bb55e8	4346	#define PPI_CHENCLR_CH21_Clear (1UL) /!< Disable channel on write. /
jamesadevine	0:e1a608bb55e8	4347
jamesadevine	0:e1a608bb55e8	4348	/* Bit 20 : Disable PPI channel 20. */
jamesadevine	0:e1a608bb55e8	4349	#define PPI_CHENCLR_CH20_Pos (20UL) /!< Position of CH20 field. /
jamesadevine	0:e1a608bb55e8	4350	#define PPI_CHENCLR_CH20_Msk (0x1UL << PPI_CHENCLR_CH20_Pos) /!< Bit mask of CH20 field. /
jamesadevine	0:e1a608bb55e8	4351	#define PPI_CHENCLR_CH20_Disabled (0UL) /!< Channel disabled. /
jamesadevine	0:e1a608bb55e8	4352	#define PPI_CHENCLR_CH20_Enabled (1UL) /!< Channel enabled. /
jamesadevine	0:e1a608bb55e8	4353	#define PPI_CHENCLR_CH20_Clear (1UL) /!< Disable channel on write. /
jamesadevine	0:e1a608bb55e8	4354
jamesadevine	0:e1a608bb55e8	4355	/* Bit 15 : Disable PPI channel 15. */
jamesadevine	0:e1a608bb55e8	4356	#define PPI_CHENCLR_CH15_Pos (15UL) /!< Position of CH15 field. /
jamesadevine	0:e1a608bb55e8	4357	#define PPI_CHENCLR_CH15_Msk (0x1UL << PPI_CHENCLR_CH15_Pos) /!< Bit mask of CH15 field. /
jamesadevine	0:e1a608bb55e8	4358	#define PPI_CHENCLR_CH15_Disabled (0UL) /!< Channel disabled. /
jamesadevine	0:e1a608bb55e8	4359	#define PPI_CHENCLR_CH15_Enabled (1UL) /!< Channel enabled. /
jamesadevine	0:e1a608bb55e8	4360	#define PPI_CHENCLR_CH15_Clear (1UL) /!< Disable channel on write. /
jamesadevine	0:e1a608bb55e8	4361
jamesadevine	0:e1a608bb55e8	4362	/* Bit 14 : Disable PPI channel 14. */
jamesadevine	0:e1a608bb55e8	4363	#define PPI_CHENCLR_CH14_Pos (14UL) /!< Position of CH14 field. /
jamesadevine	0:e1a608bb55e8	4364	#define PPI_CHENCLR_CH14_Msk (0x1UL << PPI_CHENCLR_CH14_Pos) /!< Bit mask of CH14 field. /
jamesadevine	0:e1a608bb55e8	4365	#define PPI_CHENCLR_CH14_Disabled (0UL) /!< Channel disabled. /
jamesadevine	0:e1a608bb55e8	4366	#define PPI_CHENCLR_CH14_Enabled (1UL) /!< Channel enabled. /
jamesadevine	0:e1a608bb55e8	4367	#define PPI_CHENCLR_CH14_Clear (1UL) /!< Disable channel on write. /
jamesadevine	0:e1a608bb55e8	4368
jamesadevine	0:e1a608bb55e8	4369	/* Bit 13 : Disable PPI channel 13. */
jamesadevine	0:e1a608bb55e8	4370	#define PPI_CHENCLR_CH13_Pos (13UL) /!< Position of CH13 field. /
jamesadevine	0:e1a608bb55e8	4371	#define PPI_CHENCLR_CH13_Msk (0x1UL << PPI_CHENCLR_CH13_Pos) /!< Bit mask of CH13 field. /
jamesadevine	0:e1a608bb55e8	4372	#define PPI_CHENCLR_CH13_Disabled (0UL) /!< Channel disabled. /
jamesadevine	0:e1a608bb55e8	4373	#define PPI_CHENCLR_CH13_Enabled (1UL) /!< Channel enabled. /
jamesadevine	0:e1a608bb55e8	4374	#define PPI_CHENCLR_CH13_Clear (1UL) /!< Disable channel on write. /
jamesadevine	0:e1a608bb55e8	4375
jamesadevine	0:e1a608bb55e8	4376	/* Bit 12 : Disable PPI channel 12. */
jamesadevine	0:e1a608bb55e8	4377	#define PPI_CHENCLR_CH12_Pos (12UL) /!< Position of CH12 field. /
jamesadevine	0:e1a608bb55e8	4378	#define PPI_CHENCLR_CH12_Msk (0x1UL << PPI_CHENCLR_CH12_Pos) /!< Bit mask of CH12 field. /
jamesadevine	0:e1a608bb55e8	4379	#define PPI_CHENCLR_CH12_Disabled (0UL) /!< Channel disabled. /
jamesadevine	0:e1a608bb55e8	4380	#define PPI_CHENCLR_CH12_Enabled (1UL) /!< Channel enabled. /
jamesadevine	0:e1a608bb55e8	4381	#define PPI_CHENCLR_CH12_Clear (1UL) /!< Disable channel on write. /
jamesadevine	0:e1a608bb55e8	4382
jamesadevine	0:e1a608bb55e8	4383	/* Bit 11 : Disable PPI channel 11. */
jamesadevine	0:e1a608bb55e8	4384	#define PPI_CHENCLR_CH11_Pos (11UL) /!< Position of CH11 field. /
jamesadevine	0:e1a608bb55e8	4385	#define PPI_CHENCLR_CH11_Msk (0x1UL << PPI_CHENCLR_CH11_Pos) /!< Bit mask of CH11 field. /
jamesadevine	0:e1a608bb55e8	4386	#define PPI_CHENCLR_CH11_Disabled (0UL) /!< Channel disabled. /
jamesadevine	0:e1a608bb55e8	4387	#define PPI_CHENCLR_CH11_Enabled (1UL) /!< Channel enabled. /
jamesadevine	0:e1a608bb55e8	4388	#define PPI_CHENCLR_CH11_Clear (1UL) /!< Disable channel on write. /
jamesadevine	0:e1a608bb55e8	4389
jamesadevine	0:e1a608bb55e8	4390	/* Bit 10 : Disable PPI channel 10. */
jamesadevine	0:e1a608bb55e8	4391	#define PPI_CHENCLR_CH10_Pos (10UL) /!< Position of CH10 field. /
jamesadevine	0:e1a608bb55e8	4392	#define PPI_CHENCLR_CH10_Msk (0x1UL << PPI_CHENCLR_CH10_Pos) /!< Bit mask of CH10 field. /
jamesadevine	0:e1a608bb55e8	4393	#define PPI_CHENCLR_CH10_Disabled (0UL) /!< Channel disabled. /
jamesadevine	0:e1a608bb55e8	4394	#define PPI_CHENCLR_CH10_Enabled (1UL) /!< Channel enabled. /
jamesadevine	0:e1a608bb55e8	4395	#define PPI_CHENCLR_CH10_Clear (1UL) /!< Disable channel on write. /
jamesadevine	0:e1a608bb55e8	4396
jamesadevine	0:e1a608bb55e8	4397	/* Bit 9 : Disable PPI channel 9. */
jamesadevine	0:e1a608bb55e8	4398	#define PPI_CHENCLR_CH9_Pos (9UL) /!< Position of CH9 field. /
jamesadevine	0:e1a608bb55e8	4399	#define PPI_CHENCLR_CH9_Msk (0x1UL << PPI_CHENCLR_CH9_Pos) /!< Bit mask of CH9 field. /
jamesadevine	0:e1a608bb55e8	4400	#define PPI_CHENCLR_CH9_Disabled (0UL) /!< Channel disabled. /
jamesadevine	0:e1a608bb55e8	4401	#define PPI_CHENCLR_CH9_Enabled (1UL) /!< Channel enabled. /
jamesadevine	0:e1a608bb55e8	4402	#define PPI_CHENCLR_CH9_Clear (1UL) /!< Disable channel on write. /
jamesadevine	0:e1a608bb55e8	4403
jamesadevine	0:e1a608bb55e8	4404	/* Bit 8 : Disable PPI channel 8. */
jamesadevine	0:e1a608bb55e8	4405	#define PPI_CHENCLR_CH8_Pos (8UL) /!< Position of CH8 field. /
jamesadevine	0:e1a608bb55e8	4406	#define PPI_CHENCLR_CH8_Msk (0x1UL << PPI_CHENCLR_CH8_Pos) /!< Bit mask of CH8 field. /
jamesadevine	0:e1a608bb55e8	4407	#define PPI_CHENCLR_CH8_Disabled (0UL) /!< Channel disabled. /
jamesadevine	0:e1a608bb55e8	4408	#define PPI_CHENCLR_CH8_Enabled (1UL) /!< Channel enabled. /
jamesadevine	0:e1a608bb55e8	4409	#define PPI_CHENCLR_CH8_Clear (1UL) /!< Disable channel on write. /
jamesadevine	0:e1a608bb55e8	4410
jamesadevine	0:e1a608bb55e8	4411	/* Bit 7 : Disable PPI channel 7. */
jamesadevine	0:e1a608bb55e8	4412	#define PPI_CHENCLR_CH7_Pos (7UL) /!< Position of CH7 field. /
jamesadevine	0:e1a608bb55e8	4413	#define PPI_CHENCLR_CH7_Msk (0x1UL << PPI_CHENCLR_CH7_Pos) /!< Bit mask of CH7 field. /
jamesadevine	0:e1a608bb55e8	4414	#define PPI_CHENCLR_CH7_Disabled (0UL) /!< Channel disabled. /
jamesadevine	0:e1a608bb55e8	4415	#define PPI_CHENCLR_CH7_Enabled (1UL) /!< Channel enabled. /
jamesadevine	0:e1a608bb55e8	4416	#define PPI_CHENCLR_CH7_Clear (1UL) /!< Disable channel on write. /
jamesadevine	0:e1a608bb55e8	4417
jamesadevine	0:e1a608bb55e8	4418	/* Bit 6 : Disable PPI channel 6. */
jamesadevine	0:e1a608bb55e8	4419	#define PPI_CHENCLR_CH6_Pos (6UL) /!< Position of CH6 field. /
jamesadevine	0:e1a608bb55e8	4420	#define PPI_CHENCLR_CH6_Msk (0x1UL << PPI_CHENCLR_CH6_Pos) /!< Bit mask of CH6 field. /
jamesadevine	0:e1a608bb55e8	4421	#define PPI_CHENCLR_CH6_Disabled (0UL) /!< Channel disabled. /
jamesadevine	0:e1a608bb55e8	4422	#define PPI_CHENCLR_CH6_Enabled (1UL) /!< Channel enabled. /
jamesadevine	0:e1a608bb55e8	4423	#define PPI_CHENCLR_CH6_Clear (1UL) /!< Disable channel on write. /
jamesadevine	0:e1a608bb55e8	4424
jamesadevine	0:e1a608bb55e8	4425	/* Bit 5 : Disable PPI channel 5. */
jamesadevine	0:e1a608bb55e8	4426	#define PPI_CHENCLR_CH5_Pos (5UL) /!< Position of CH5 field. /
jamesadevine	0:e1a608bb55e8	4427	#define PPI_CHENCLR_CH5_Msk (0x1UL << PPI_CHENCLR_CH5_Pos) /!< Bit mask of CH5 field. /
jamesadevine	0:e1a608bb55e8	4428	#define PPI_CHENCLR_CH5_Disabled (0UL) /!< Channel disabled. /
jamesadevine	0:e1a608bb55e8	4429	#define PPI_CHENCLR_CH5_Enabled (1UL) /!< Channel enabled. /
jamesadevine	0:e1a608bb55e8	4430	#define PPI_CHENCLR_CH5_Clear (1UL) /!< Disable channel on write. /
jamesadevine	0:e1a608bb55e8	4431
jamesadevine	0:e1a608bb55e8	4432	/* Bit 4 : Disable PPI channel 4. */
jamesadevine	0:e1a608bb55e8	4433	#define PPI_CHENCLR_CH4_Pos (4UL) /!< Position of CH4 field. /
jamesadevine	0:e1a608bb55e8	4434	#define PPI_CHENCLR_CH4_Msk (0x1UL << PPI_CHENCLR_CH4_Pos) /!< Bit mask of CH4 field. /
jamesadevine	0:e1a608bb55e8	4435	#define PPI_CHENCLR_CH4_Disabled (0UL) /!< Channel disabled. /
jamesadevine	0:e1a608bb55e8	4436	#define PPI_CHENCLR_CH4_Enabled (1UL) /!< Channel enabled. /
jamesadevine	0:e1a608bb55e8	4437	#define PPI_CHENCLR_CH4_Clear (1UL) /!< Disable channel on write. /
jamesadevine	0:e1a608bb55e8	4438
jamesadevine	0:e1a608bb55e8	4439	/* Bit 3 : Disable PPI channel 3. */
jamesadevine	0:e1a608bb55e8	4440	#define PPI_CHENCLR_CH3_Pos (3UL) /!< Position of CH3 field. /
jamesadevine	0:e1a608bb55e8	4441	#define PPI_CHENCLR_CH3_Msk (0x1UL << PPI_CHENCLR_CH3_Pos) /!< Bit mask of CH3 field. /
jamesadevine	0:e1a608bb55e8	4442	#define PPI_CHENCLR_CH3_Disabled (0UL) /!< Channel disabled. /
jamesadevine	0:e1a608bb55e8	4443	#define PPI_CHENCLR_CH3_Enabled (1UL) /!< Channel enabled. /
jamesadevine	0:e1a608bb55e8	4444	#define PPI_CHENCLR_CH3_Clear (1UL) /!< Disable channel on write. /
jamesadevine	0:e1a608bb55e8	4445
jamesadevine	0:e1a608bb55e8	4446	/* Bit 2 : Disable PPI channel 2. */
jamesadevine	0:e1a608bb55e8	4447	#define PPI_CHENCLR_CH2_Pos (2UL) /!< Position of CH2 field. /
jamesadevine	0:e1a608bb55e8	4448	#define PPI_CHENCLR_CH2_Msk (0x1UL << PPI_CHENCLR_CH2_Pos) /!< Bit mask of CH2 field. /
jamesadevine	0:e1a608bb55e8	4449	#define PPI_CHENCLR_CH2_Disabled (0UL) /!< Channel disabled. /
jamesadevine	0:e1a608bb55e8	4450	#define PPI_CHENCLR_CH2_Enabled (1UL) /!< Channel enabled. /
jamesadevine	0:e1a608bb55e8	4451	#define PPI_CHENCLR_CH2_Clear (1UL) /!< Disable channel on write. /
jamesadevine	0:e1a608bb55e8	4452
jamesadevine	0:e1a608bb55e8	4453	/* Bit 1 : Disable PPI channel 1. */
jamesadevine	0:e1a608bb55e8	4454	#define PPI_CHENCLR_CH1_Pos (1UL) /!< Position of CH1 field. /
jamesadevine	0:e1a608bb55e8	4455	#define PPI_CHENCLR_CH1_Msk (0x1UL << PPI_CHENCLR_CH1_Pos) /!< Bit mask of CH1 field. /
jamesadevine	0:e1a608bb55e8	4456	#define PPI_CHENCLR_CH1_Disabled (0UL) /!< Channel disabled. /
jamesadevine	0:e1a608bb55e8	4457	#define PPI_CHENCLR_CH1_Enabled (1UL) /!< Channel enabled. /
jamesadevine	0:e1a608bb55e8	4458	#define PPI_CHENCLR_CH1_Clear (1UL) /!< Disable channel on write. /
jamesadevine	0:e1a608bb55e8	4459
jamesadevine	0:e1a608bb55e8	4460	/* Bit 0 : Disable PPI channel 0. */
jamesadevine	0:e1a608bb55e8	4461	#define PPI_CHENCLR_CH0_Pos (0UL) /!< Position of CH0 field. /
jamesadevine	0:e1a608bb55e8	4462	#define PPI_CHENCLR_CH0_Msk (0x1UL << PPI_CHENCLR_CH0_Pos) /!< Bit mask of CH0 field. /
jamesadevine	0:e1a608bb55e8	4463	#define PPI_CHENCLR_CH0_Disabled (0UL) /!< Channel disabled. /
jamesadevine	0:e1a608bb55e8	4464	#define PPI_CHENCLR_CH0_Enabled (1UL) /!< Channel enabled. /
jamesadevine	0:e1a608bb55e8	4465	#define PPI_CHENCLR_CH0_Clear (1UL) /!< Disable channel on write. /
jamesadevine	0:e1a608bb55e8	4466
jamesadevine	0:e1a608bb55e8	4467	/* Register: PPI_CHG */
jamesadevine	0:e1a608bb55e8	4468	/* Description: Channel group configuration. */
jamesadevine	0:e1a608bb55e8	4469
jamesadevine	0:e1a608bb55e8	4470	/* Bit 31 : Include CH31 in channel group. */
jamesadevine	0:e1a608bb55e8	4471	#define PPI_CHG_CH31_Pos (31UL) /!< Position of CH31 field. /
jamesadevine	0:e1a608bb55e8	4472	#define PPI_CHG_CH31_Msk (0x1UL << PPI_CHG_CH31_Pos) /!< Bit mask of CH31 field. /
jamesadevine	0:e1a608bb55e8	4473	#define PPI_CHG_CH31_Excluded (0UL) /!< Channel excluded. /
jamesadevine	0:e1a608bb55e8	4474	#define PPI_CHG_CH31_Included (1UL) /!< Channel included. /
jamesadevine	0:e1a608bb55e8	4475
jamesadevine	0:e1a608bb55e8	4476	/* Bit 30 : Include CH30 in channel group. */
jamesadevine	0:e1a608bb55e8	4477	#define PPI_CHG_CH30_Pos (30UL) /!< Position of CH30 field. /
jamesadevine	0:e1a608bb55e8	4478	#define PPI_CHG_CH30_Msk (0x1UL << PPI_CHG_CH30_Pos) /!< Bit mask of CH30 field. /
jamesadevine	0:e1a608bb55e8	4479	#define PPI_CHG_CH30_Excluded (0UL) /!< Channel excluded. /
jamesadevine	0:e1a608bb55e8	4480	#define PPI_CHG_CH30_Included (1UL) /!< Channel included. /
jamesadevine	0:e1a608bb55e8	4481
jamesadevine	0:e1a608bb55e8	4482	/* Bit 29 : Include CH29 in channel group. */
jamesadevine	0:e1a608bb55e8	4483	#define PPI_CHG_CH29_Pos (29UL) /!< Position of CH29 field. /
jamesadevine	0:e1a608bb55e8	4484	#define PPI_CHG_CH29_Msk (0x1UL << PPI_CHG_CH29_Pos) /!< Bit mask of CH29 field. /
jamesadevine	0:e1a608bb55e8	4485	#define PPI_CHG_CH29_Excluded (0UL) /!< Channel excluded. /
jamesadevine	0:e1a608bb55e8	4486	#define PPI_CHG_CH29_Included (1UL) /!< Channel included. /
jamesadevine	0:e1a608bb55e8	4487
jamesadevine	0:e1a608bb55e8	4488	/* Bit 28 : Include CH28 in channel group. */
jamesadevine	0:e1a608bb55e8	4489	#define PPI_CHG_CH28_Pos (28UL) /!< Position of CH28 field. /
jamesadevine	0:e1a608bb55e8	4490	#define PPI_CHG_CH28_Msk (0x1UL << PPI_CHG_CH28_Pos) /!< Bit mask of CH28 field. /
jamesadevine	0:e1a608bb55e8	4491	#define PPI_CHG_CH28_Excluded (0UL) /!< Channel excluded. /
jamesadevine	0:e1a608bb55e8	4492	#define PPI_CHG_CH28_Included (1UL) /!< Channel included. /
jamesadevine	0:e1a608bb55e8	4493
jamesadevine	0:e1a608bb55e8	4494	/* Bit 27 : Include CH27 in channel group. */
jamesadevine	0:e1a608bb55e8	4495	#define PPI_CHG_CH27_Pos (27UL) /!< Position of CH27 field. /
jamesadevine	0:e1a608bb55e8	4496	#define PPI_CHG_CH27_Msk (0x1UL << PPI_CHG_CH27_Pos) /!< Bit mask of CH27 field. /
jamesadevine	0:e1a608bb55e8	4497	#define PPI_CHG_CH27_Excluded (0UL) /!< Channel excluded. /
jamesadevine	0:e1a608bb55e8	4498	#define PPI_CHG_CH27_Included (1UL) /!< Channel included. /
jamesadevine	0:e1a608bb55e8	4499
jamesadevine	0:e1a608bb55e8	4500	/* Bit 26 : Include CH26 in channel group. */
jamesadevine	0:e1a608bb55e8	4501	#define PPI_CHG_CH26_Pos (26UL) /!< Position of CH26 field. /
jamesadevine	0:e1a608bb55e8	4502	#define PPI_CHG_CH26_Msk (0x1UL << PPI_CHG_CH26_Pos) /!< Bit mask of CH26 field. /
jamesadevine	0:e1a608bb55e8	4503	#define PPI_CHG_CH26_Excluded (0UL) /!< Channel excluded. /
jamesadevine	0:e1a608bb55e8	4504	#define PPI_CHG_CH26_Included (1UL) /!< Channel included. /
jamesadevine	0:e1a608bb55e8	4505
jamesadevine	0:e1a608bb55e8	4506	/* Bit 25 : Include CH25 in channel group. */
jamesadevine	0:e1a608bb55e8	4507	#define PPI_CHG_CH25_Pos (25UL) /!< Position of CH25 field. /
jamesadevine	0:e1a608bb55e8	4508	#define PPI_CHG_CH25_Msk (0x1UL << PPI_CHG_CH25_Pos) /!< Bit mask of CH25 field. /
jamesadevine	0:e1a608bb55e8	4509	#define PPI_CHG_CH25_Excluded (0UL) /!< Channel excluded. /
jamesadevine	0:e1a608bb55e8	4510	#define PPI_CHG_CH25_Included (1UL) /!< Channel included. /
jamesadevine	0:e1a608bb55e8	4511
jamesadevine	0:e1a608bb55e8	4512	/* Bit 24 : Include CH24 in channel group. */
jamesadevine	0:e1a608bb55e8	4513	#define PPI_CHG_CH24_Pos (24UL) /!< Position of CH24 field. /
jamesadevine	0:e1a608bb55e8	4514	#define PPI_CHG_CH24_Msk (0x1UL << PPI_CHG_CH24_Pos) /!< Bit mask of CH24 field. /
jamesadevine	0:e1a608bb55e8	4515	#define PPI_CHG_CH24_Excluded (0UL) /!< Channel excluded. /
jamesadevine	0:e1a608bb55e8	4516	#define PPI_CHG_CH24_Included (1UL) /!< Channel included. /
jamesadevine	0:e1a608bb55e8	4517
jamesadevine	0:e1a608bb55e8	4518	/* Bit 23 : Include CH23 in channel group. */
jamesadevine	0:e1a608bb55e8	4519	#define PPI_CHG_CH23_Pos (23UL) /!< Position of CH23 field. /
jamesadevine	0:e1a608bb55e8	4520	#define PPI_CHG_CH23_Msk (0x1UL << PPI_CHG_CH23_Pos) /!< Bit mask of CH23 field. /
jamesadevine	0:e1a608bb55e8	4521	#define PPI_CHG_CH23_Excluded (0UL) /!< Channel excluded. /
jamesadevine	0:e1a608bb55e8	4522	#define PPI_CHG_CH23_Included (1UL) /!< Channel included. /
jamesadevine	0:e1a608bb55e8	4523
jamesadevine	0:e1a608bb55e8	4524	/* Bit 22 : Include CH22 in channel group. */
jamesadevine	0:e1a608bb55e8	4525	#define PPI_CHG_CH22_Pos (22UL) /!< Position of CH22 field. /
jamesadevine	0:e1a608bb55e8	4526	#define PPI_CHG_CH22_Msk (0x1UL << PPI_CHG_CH22_Pos) /!< Bit mask of CH22 field. /
jamesadevine	0:e1a608bb55e8	4527	#define PPI_CHG_CH22_Excluded (0UL) /!< Channel excluded. /
jamesadevine	0:e1a608bb55e8	4528	#define PPI_CHG_CH22_Included (1UL) /!< Channel included. /
jamesadevine	0:e1a608bb55e8	4529
jamesadevine	0:e1a608bb55e8	4530	/* Bit 21 : Include CH21 in channel group. */
jamesadevine	0:e1a608bb55e8	4531	#define PPI_CHG_CH21_Pos (21UL) /!< Position of CH21 field. /
jamesadevine	0:e1a608bb55e8	4532	#define PPI_CHG_CH21_Msk (0x1UL << PPI_CHG_CH21_Pos) /!< Bit mask of CH21 field. /
jamesadevine	0:e1a608bb55e8	4533	#define PPI_CHG_CH21_Excluded (0UL) /!< Channel excluded. /
jamesadevine	0:e1a608bb55e8	4534	#define PPI_CHG_CH21_Included (1UL) /!< Channel included. /
jamesadevine	0:e1a608bb55e8	4535
jamesadevine	0:e1a608bb55e8	4536	/* Bit 20 : Include CH20 in channel group. */
jamesadevine	0:e1a608bb55e8	4537	#define PPI_CHG_CH20_Pos (20UL) /!< Position of CH20 field. /
jamesadevine	0:e1a608bb55e8	4538	#define PPI_CHG_CH20_Msk (0x1UL << PPI_CHG_CH20_Pos) /!< Bit mask of CH20 field. /
jamesadevine	0:e1a608bb55e8	4539	#define PPI_CHG_CH20_Excluded (0UL) /!< Channel excluded. /
jamesadevine	0:e1a608bb55e8	4540	#define PPI_CHG_CH20_Included (1UL) /!< Channel included. /
jamesadevine	0:e1a608bb55e8	4541
jamesadevine	0:e1a608bb55e8	4542	/* Bit 15 : Include CH15 in channel group. */
jamesadevine	0:e1a608bb55e8	4543	#define PPI_CHG_CH15_Pos (15UL) /!< Position of CH15 field. /
jamesadevine	0:e1a608bb55e8	4544	#define PPI_CHG_CH15_Msk (0x1UL << PPI_CHG_CH15_Pos) /!< Bit mask of CH15 field. /
jamesadevine	0:e1a608bb55e8	4545	#define PPI_CHG_CH15_Excluded (0UL) /!< Channel excluded. /
jamesadevine	0:e1a608bb55e8	4546	#define PPI_CHG_CH15_Included (1UL) /!< Channel included. /
jamesadevine	0:e1a608bb55e8	4547
jamesadevine	0:e1a608bb55e8	4548	/* Bit 14 : Include CH14 in channel group. */
jamesadevine	0:e1a608bb55e8	4549	#define PPI_CHG_CH14_Pos (14UL) /!< Position of CH14 field. /
jamesadevine	0:e1a608bb55e8	4550	#define PPI_CHG_CH14_Msk (0x1UL << PPI_CHG_CH14_Pos) /!< Bit mask of CH14 field. /
jamesadevine	0:e1a608bb55e8	4551	#define PPI_CHG_CH14_Excluded (0UL) /!< Channel excluded. /
jamesadevine	0:e1a608bb55e8	4552	#define PPI_CHG_CH14_Included (1UL) /!< Channel included. /
jamesadevine	0:e1a608bb55e8	4553
jamesadevine	0:e1a608bb55e8	4554	/* Bit 13 : Include CH13 in channel group. */
jamesadevine	0:e1a608bb55e8	4555	#define PPI_CHG_CH13_Pos (13UL) /!< Position of CH13 field. /
jamesadevine	0:e1a608bb55e8	4556	#define PPI_CHG_CH13_Msk (0x1UL << PPI_CHG_CH13_Pos) /!< Bit mask of CH13 field. /
jamesadevine	0:e1a608bb55e8	4557	#define PPI_CHG_CH13_Excluded (0UL) /!< Channel excluded. /
jamesadevine	0:e1a608bb55e8	4558	#define PPI_CHG_CH13_Included (1UL) /!< Channel included. /
jamesadevine	0:e1a608bb55e8	4559
jamesadevine	0:e1a608bb55e8	4560	/* Bit 12 : Include CH12 in channel group. */
jamesadevine	0:e1a608bb55e8	4561	#define PPI_CHG_CH12_Pos (12UL) /!< Position of CH12 field. /
jamesadevine	0:e1a608bb55e8	4562	#define PPI_CHG_CH12_Msk (0x1UL << PPI_CHG_CH12_Pos) /!< Bit mask of CH12 field. /
jamesadevine	0:e1a608bb55e8	4563	#define PPI_CHG_CH12_Excluded (0UL) /!< Channel excluded. /
jamesadevine	0:e1a608bb55e8	4564	#define PPI_CHG_CH12_Included (1UL) /!< Channel included. /
jamesadevine	0:e1a608bb55e8	4565
jamesadevine	0:e1a608bb55e8	4566	/* Bit 11 : Include CH11 in channel group. */
jamesadevine	0:e1a608bb55e8	4567	#define PPI_CHG_CH11_Pos (11UL) /!< Position of CH11 field. /
jamesadevine	0:e1a608bb55e8	4568	#define PPI_CHG_CH11_Msk (0x1UL << PPI_CHG_CH11_Pos) /!< Bit mask of CH11 field. /
jamesadevine	0:e1a608bb55e8	4569	#define PPI_CHG_CH11_Excluded (0UL) /!< Channel excluded. /
jamesadevine	0:e1a608bb55e8	4570	#define PPI_CHG_CH11_Included (1UL) /!< Channel included. /
jamesadevine	0:e1a608bb55e8	4571
jamesadevine	0:e1a608bb55e8	4572	/* Bit 10 : Include CH10 in channel group. */
jamesadevine	0:e1a608bb55e8	4573	#define PPI_CHG_CH10_Pos (10UL) /!< Position of CH10 field. /
jamesadevine	0:e1a608bb55e8	4574	#define PPI_CHG_CH10_Msk (0x1UL << PPI_CHG_CH10_Pos) /!< Bit mask of CH10 field. /
jamesadevine	0:e1a608bb55e8	4575	#define PPI_CHG_CH10_Excluded (0UL) /!< Channel excluded. /
jamesadevine	0:e1a608bb55e8	4576	#define PPI_CHG_CH10_Included (1UL) /!< Channel included. /
jamesadevine	0:e1a608bb55e8	4577
jamesadevine	0:e1a608bb55e8	4578	/* Bit 9 : Include CH9 in channel group. */
jamesadevine	0:e1a608bb55e8	4579	#define PPI_CHG_CH9_Pos (9UL) /!< Position of CH9 field. /
jamesadevine	0:e1a608bb55e8	4580	#define PPI_CHG_CH9_Msk (0x1UL << PPI_CHG_CH9_Pos) /!< Bit mask of CH9 field. /
jamesadevine	0:e1a608bb55e8	4581	#define PPI_CHG_CH9_Excluded (0UL) /!< Channel excluded. /
jamesadevine	0:e1a608bb55e8	4582	#define PPI_CHG_CH9_Included (1UL) /!< Channel included. /
jamesadevine	0:e1a608bb55e8	4583
jamesadevine	0:e1a608bb55e8	4584	/* Bit 8 : Include CH8 in channel group. */
jamesadevine	0:e1a608bb55e8	4585	#define PPI_CHG_CH8_Pos (8UL) /!< Position of CH8 field. /
jamesadevine	0:e1a608bb55e8	4586	#define PPI_CHG_CH8_Msk (0x1UL << PPI_CHG_CH8_Pos) /!< Bit mask of CH8 field. /
jamesadevine	0:e1a608bb55e8	4587	#define PPI_CHG_CH8_Excluded (0UL) /!< Channel excluded. /
jamesadevine	0:e1a608bb55e8	4588	#define PPI_CHG_CH8_Included (1UL) /!< Channel included. /
jamesadevine	0:e1a608bb55e8	4589
jamesadevine	0:e1a608bb55e8	4590	/* Bit 7 : Include CH7 in channel group. */
jamesadevine	0:e1a608bb55e8	4591	#define PPI_CHG_CH7_Pos (7UL) /!< Position of CH7 field. /
jamesadevine	0:e1a608bb55e8	4592	#define PPI_CHG_CH7_Msk (0x1UL << PPI_CHG_CH7_Pos) /!< Bit mask of CH7 field. /
jamesadevine	0:e1a608bb55e8	4593	#define PPI_CHG_CH7_Excluded (0UL) /!< Channel excluded. /
jamesadevine	0:e1a608bb55e8	4594	#define PPI_CHG_CH7_Included (1UL) /!< Channel included. /
jamesadevine	0:e1a608bb55e8	4595
jamesadevine	0:e1a608bb55e8	4596	/* Bit 6 : Include CH6 in channel group. */
jamesadevine	0:e1a608bb55e8	4597	#define PPI_CHG_CH6_Pos (6UL) /!< Position of CH6 field. /
jamesadevine	0:e1a608bb55e8	4598	#define PPI_CHG_CH6_Msk (0x1UL << PPI_CHG_CH6_Pos) /!< Bit mask of CH6 field. /
jamesadevine	0:e1a608bb55e8	4599	#define PPI_CHG_CH6_Excluded (0UL) /!< Channel excluded. /
jamesadevine	0:e1a608bb55e8	4600	#define PPI_CHG_CH6_Included (1UL) /!< Channel included. /
jamesadevine	0:e1a608bb55e8	4601
jamesadevine	0:e1a608bb55e8	4602	/* Bit 5 : Include CH5 in channel group. */
jamesadevine	0:e1a608bb55e8	4603	#define PPI_CHG_CH5_Pos (5UL) /!< Position of CH5 field. /
jamesadevine	0:e1a608bb55e8	4604	#define PPI_CHG_CH5_Msk (0x1UL << PPI_CHG_CH5_Pos) /!< Bit mask of CH5 field. /
jamesadevine	0:e1a608bb55e8	4605	#define PPI_CHG_CH5_Excluded (0UL) /!< Channel excluded. /
jamesadevine	0:e1a608bb55e8	4606	#define PPI_CHG_CH5_Included (1UL) /!< Channel included. /
jamesadevine	0:e1a608bb55e8	4607
jamesadevine	0:e1a608bb55e8	4608	/* Bit 4 : Include CH4 in channel group. */
jamesadevine	0:e1a608bb55e8	4609	#define PPI_CHG_CH4_Pos (4UL) /!< Position of CH4 field. /
jamesadevine	0:e1a608bb55e8	4610	#define PPI_CHG_CH4_Msk (0x1UL << PPI_CHG_CH4_Pos) /!< Bit mask of CH4 field. /
jamesadevine	0:e1a608bb55e8	4611	#define PPI_CHG_CH4_Excluded (0UL) /!< Channel excluded. /
jamesadevine	0:e1a608bb55e8	4612	#define PPI_CHG_CH4_Included (1UL) /!< Channel included. /
jamesadevine	0:e1a608bb55e8	4613
jamesadevine	0:e1a608bb55e8	4614	/* Bit 3 : Include CH3 in channel group. */
jamesadevine	0:e1a608bb55e8	4615	#define PPI_CHG_CH3_Pos (3UL) /!< Position of CH3 field. /
jamesadevine	0:e1a608bb55e8	4616	#define PPI_CHG_CH3_Msk (0x1UL << PPI_CHG_CH3_Pos) /!< Bit mask of CH3 field. /
jamesadevine	0:e1a608bb55e8	4617	#define PPI_CHG_CH3_Excluded (0UL) /!< Channel excluded. /
jamesadevine	0:e1a608bb55e8	4618	#define PPI_CHG_CH3_Included (1UL) /!< Channel included. /
jamesadevine	0:e1a608bb55e8	4619
jamesadevine	0:e1a608bb55e8	4620	/* Bit 2 : Include CH2 in channel group. */
jamesadevine	0:e1a608bb55e8	4621	#define PPI_CHG_CH2_Pos (2UL) /!< Position of CH2 field. /
jamesadevine	0:e1a608bb55e8	4622	#define PPI_CHG_CH2_Msk (0x1UL << PPI_CHG_CH2_Pos) /!< Bit mask of CH2 field. /
jamesadevine	0:e1a608bb55e8	4623	#define PPI_CHG_CH2_Excluded (0UL) /!< Channel excluded. /
jamesadevine	0:e1a608bb55e8	4624	#define PPI_CHG_CH2_Included (1UL) /!< Channel included. /
jamesadevine	0:e1a608bb55e8	4625
jamesadevine	0:e1a608bb55e8	4626	/* Bit 1 : Include CH1 in channel group. */
jamesadevine	0:e1a608bb55e8	4627	#define PPI_CHG_CH1_Pos (1UL) /!< Position of CH1 field. /
jamesadevine	0:e1a608bb55e8	4628	#define PPI_CHG_CH1_Msk (0x1UL << PPI_CHG_CH1_Pos) /!< Bit mask of CH1 field. /
jamesadevine	0:e1a608bb55e8	4629	#define PPI_CHG_CH1_Excluded (0UL) /!< Channel excluded. /
jamesadevine	0:e1a608bb55e8	4630	#define PPI_CHG_CH1_Included (1UL) /!< Channel included. /
jamesadevine	0:e1a608bb55e8	4631
jamesadevine	0:e1a608bb55e8	4632	/* Bit 0 : Include CH0 in channel group. */
jamesadevine	0:e1a608bb55e8	4633	#define PPI_CHG_CH0_Pos (0UL) /!< Position of CH0 field. /
jamesadevine	0:e1a608bb55e8	4634	#define PPI_CHG_CH0_Msk (0x1UL << PPI_CHG_CH0_Pos) /!< Bit mask of CH0 field. /
jamesadevine	0:e1a608bb55e8	4635	#define PPI_CHG_CH0_Excluded (0UL) /!< Channel excluded. /
jamesadevine	0:e1a608bb55e8	4636	#define PPI_CHG_CH0_Included (1UL) /!< Channel included. /
jamesadevine	0:e1a608bb55e8	4637
jamesadevine	0:e1a608bb55e8	4638
jamesadevine	0:e1a608bb55e8	4639	/* Peripheral: PU */
jamesadevine	0:e1a608bb55e8	4640	/* Description: Patch unit. */
jamesadevine	0:e1a608bb55e8	4641
jamesadevine	0:e1a608bb55e8	4642	/* Register: PU_PATCHADDR */
jamesadevine	0:e1a608bb55e8	4643	/* Description: Relative address of patch instructions. */
jamesadevine	0:e1a608bb55e8	4644
jamesadevine	0:e1a608bb55e8	4645	/* Bits 24..0 : Relative address of patch instructions. */
jamesadevine	0:e1a608bb55e8	4646	#define PU_PATCHADDR_PATCHADDR_Pos (0UL) /!< Position of PATCHADDR field. /
jamesadevine	0:e1a608bb55e8	4647	#define PU_PATCHADDR_PATCHADDR_Msk (0x1FFFFFFUL << PU_PATCHADDR_PATCHADDR_Pos) /!< Bit mask of PATCHADDR field. /
jamesadevine	0:e1a608bb55e8	4648
jamesadevine	0:e1a608bb55e8	4649	/* Register: PU_PATCHEN */
jamesadevine	0:e1a608bb55e8	4650	/* Description: Patch enable register. */
jamesadevine	0:e1a608bb55e8	4651
jamesadevine	0:e1a608bb55e8	4652	/* Bit 7 : Patch 7 enabled. */
jamesadevine	0:e1a608bb55e8	4653	#define PU_PATCHEN_PATCH7_Pos (7UL) /!< Position of PATCH7 field. /
jamesadevine	0:e1a608bb55e8	4654	#define PU_PATCHEN_PATCH7_Msk (0x1UL << PU_PATCHEN_PATCH7_Pos) /!< Bit mask of PATCH7 field. /
jamesadevine	0:e1a608bb55e8	4655	#define PU_PATCHEN_PATCH7_Disabled (0UL) /!< Patch disabled. /
jamesadevine	0:e1a608bb55e8	4656	#define PU_PATCHEN_PATCH7_Enabled (1UL) /!< Patch enabled. /
jamesadevine	0:e1a608bb55e8	4657
jamesadevine	0:e1a608bb55e8	4658	/* Bit 6 : Patch 6 enabled. */
jamesadevine	0:e1a608bb55e8	4659	#define PU_PATCHEN_PATCH6_Pos (6UL) /!< Position of PATCH6 field. /
jamesadevine	0:e1a608bb55e8	4660	#define PU_PATCHEN_PATCH6_Msk (0x1UL << PU_PATCHEN_PATCH6_Pos) /!< Bit mask of PATCH6 field. /
jamesadevine	0:e1a608bb55e8	4661	#define PU_PATCHEN_PATCH6_Disabled (0UL) /!< Patch disabled. /
jamesadevine	0:e1a608bb55e8	4662	#define PU_PATCHEN_PATCH6_Enabled (1UL) /!< Patch enabled. /
jamesadevine	0:e1a608bb55e8	4663
jamesadevine	0:e1a608bb55e8	4664	/* Bit 5 : Patch 5 enabled. */
jamesadevine	0:e1a608bb55e8	4665	#define PU_PATCHEN_PATCH5_Pos (5UL) /!< Position of PATCH5 field. /
jamesadevine	0:e1a608bb55e8	4666	#define PU_PATCHEN_PATCH5_Msk (0x1UL << PU_PATCHEN_PATCH5_Pos) /!< Bit mask of PATCH5 field. /
jamesadevine	0:e1a608bb55e8	4667	#define PU_PATCHEN_PATCH5_Disabled (0UL) /!< Patch disabled. /
jamesadevine	0:e1a608bb55e8	4668	#define PU_PATCHEN_PATCH5_Enabled (1UL) /!< Patch enabled. /
jamesadevine	0:e1a608bb55e8	4669
jamesadevine	0:e1a608bb55e8	4670	/* Bit 4 : Patch 4 enabled. */
jamesadevine	0:e1a608bb55e8	4671	#define PU_PATCHEN_PATCH4_Pos (4UL) /!< Position of PATCH4 field. /
jamesadevine	0:e1a608bb55e8	4672	#define PU_PATCHEN_PATCH4_Msk (0x1UL << PU_PATCHEN_PATCH4_Pos) /!< Bit mask of PATCH4 field. /
jamesadevine	0:e1a608bb55e8	4673	#define PU_PATCHEN_PATCH4_Disabled (0UL) /!< Patch disabled. /
jamesadevine	0:e1a608bb55e8	4674	#define PU_PATCHEN_PATCH4_Enabled (1UL) /!< Patch enabled. /
jamesadevine	0:e1a608bb55e8	4675
jamesadevine	0:e1a608bb55e8	4676	/* Bit 3 : Patch 3 enabled. */
jamesadevine	0:e1a608bb55e8	4677	#define PU_PATCHEN_PATCH3_Pos (3UL) /!< Position of PATCH3 field. /
jamesadevine	0:e1a608bb55e8	4678	#define PU_PATCHEN_PATCH3_Msk (0x1UL << PU_PATCHEN_PATCH3_Pos) /!< Bit mask of PATCH3 field. /
jamesadevine	0:e1a608bb55e8	4679	#define PU_PATCHEN_PATCH3_Disabled (0UL) /!< Patch disabled. /
jamesadevine	0:e1a608bb55e8	4680	#define PU_PATCHEN_PATCH3_Enabled (1UL) /!< Patch enabled. /
jamesadevine	0:e1a608bb55e8	4681
jamesadevine	0:e1a608bb55e8	4682	/* Bit 2 : Patch 2 enabled. */
jamesadevine	0:e1a608bb55e8	4683	#define PU_PATCHEN_PATCH2_Pos (2UL) /!< Position of PATCH2 field. /
jamesadevine	0:e1a608bb55e8	4684	#define PU_PATCHEN_PATCH2_Msk (0x1UL << PU_PATCHEN_PATCH2_Pos) /!< Bit mask of PATCH2 field. /
jamesadevine	0:e1a608bb55e8	4685	#define PU_PATCHEN_PATCH2_Disabled (0UL) /!< Patch disabled. /
jamesadevine	0:e1a608bb55e8	4686	#define PU_PATCHEN_PATCH2_Enabled (1UL) /!< Patch enabled. /
jamesadevine	0:e1a608bb55e8	4687
jamesadevine	0:e1a608bb55e8	4688	/* Bit 1 : Patch 1 enabled. */
jamesadevine	0:e1a608bb55e8	4689	#define PU_PATCHEN_PATCH1_Pos (1UL) /!< Position of PATCH1 field. /
jamesadevine	0:e1a608bb55e8	4690	#define PU_PATCHEN_PATCH1_Msk (0x1UL << PU_PATCHEN_PATCH1_Pos) /!< Bit mask of PATCH1 field. /
jamesadevine	0:e1a608bb55e8	4691	#define PU_PATCHEN_PATCH1_Disabled (0UL) /!< Patch disabled. /
jamesadevine	0:e1a608bb55e8	4692	#define PU_PATCHEN_PATCH1_Enabled (1UL) /!< Patch enabled. /
jamesadevine	0:e1a608bb55e8	4693
jamesadevine	0:e1a608bb55e8	4694	/* Bit 0 : Patch 0 enabled. */
jamesadevine	0:e1a608bb55e8	4695	#define PU_PATCHEN_PATCH0_Pos (0UL) /!< Position of PATCH0 field. /
jamesadevine	0:e1a608bb55e8	4696	#define PU_PATCHEN_PATCH0_Msk (0x1UL << PU_PATCHEN_PATCH0_Pos) /!< Bit mask of PATCH0 field. /
jamesadevine	0:e1a608bb55e8	4697	#define PU_PATCHEN_PATCH0_Disabled (0UL) /!< Patch disabled. /
jamesadevine	0:e1a608bb55e8	4698	#define PU_PATCHEN_PATCH0_Enabled (1UL) /!< Patch enabled. /
jamesadevine	0:e1a608bb55e8	4699
jamesadevine	0:e1a608bb55e8	4700	/* Register: PU_PATCHENSET */
jamesadevine	0:e1a608bb55e8	4701	/* Description: Patch enable register. */
jamesadevine	0:e1a608bb55e8	4702
jamesadevine	0:e1a608bb55e8	4703	/* Bit 7 : Patch 7 enabled. */
jamesadevine	0:e1a608bb55e8	4704	#define PU_PATCHENSET_PATCH7_Pos (7UL) /!< Position of PATCH7 field. /
jamesadevine	0:e1a608bb55e8	4705	#define PU_PATCHENSET_PATCH7_Msk (0x1UL << PU_PATCHENSET_PATCH7_Pos) /!< Bit mask of PATCH7 field. /
jamesadevine	0:e1a608bb55e8	4706	#define PU_PATCHENSET_PATCH7_Disabled (0UL) /!< Patch disabled. /
jamesadevine	0:e1a608bb55e8	4707	#define PU_PATCHENSET_PATCH7_Enabled (1UL) /!< Patch enabled. /
jamesadevine	0:e1a608bb55e8	4708	#define PU_PATCHENSET_PATCH7_Set (1UL) /!< Enable patch on write. /
jamesadevine	0:e1a608bb55e8	4709
jamesadevine	0:e1a608bb55e8	4710	/* Bit 6 : Patch 6 enabled. */
jamesadevine	0:e1a608bb55e8	4711	#define PU_PATCHENSET_PATCH6_Pos (6UL) /!< Position of PATCH6 field. /
jamesadevine	0:e1a608bb55e8	4712	#define PU_PATCHENSET_PATCH6_Msk (0x1UL << PU_PATCHENSET_PATCH6_Pos) /!< Bit mask of PATCH6 field. /
jamesadevine	0:e1a608bb55e8	4713	#define PU_PATCHENSET_PATCH6_Disabled (0UL) /!< Patch disabled. /
jamesadevine	0:e1a608bb55e8	4714	#define PU_PATCHENSET_PATCH6_Enabled (1UL) /!< Patch enabled. /
jamesadevine	0:e1a608bb55e8	4715	#define PU_PATCHENSET_PATCH6_Set (1UL) /!< Enable patch on write. /
jamesadevine	0:e1a608bb55e8	4716
jamesadevine	0:e1a608bb55e8	4717	/* Bit 5 : Patch 5 enabled. */
jamesadevine	0:e1a608bb55e8	4718	#define PU_PATCHENSET_PATCH5_Pos (5UL) /!< Position of PATCH5 field. /
jamesadevine	0:e1a608bb55e8	4719	#define PU_PATCHENSET_PATCH5_Msk (0x1UL << PU_PATCHENSET_PATCH5_Pos) /!< Bit mask of PATCH5 field. /
jamesadevine	0:e1a608bb55e8	4720	#define PU_PATCHENSET_PATCH5_Disabled (0UL) /!< Patch disabled. /
jamesadevine	0:e1a608bb55e8	4721	#define PU_PATCHENSET_PATCH5_Enabled (1UL) /!< Patch enabled. /
jamesadevine	0:e1a608bb55e8	4722	#define PU_PATCHENSET_PATCH5_Set (1UL) /!< Enable patch on write. /
jamesadevine	0:e1a608bb55e8	4723
jamesadevine	0:e1a608bb55e8	4724	/* Bit 4 : Patch 4 enabled. */
jamesadevine	0:e1a608bb55e8	4725	#define PU_PATCHENSET_PATCH4_Pos (4UL) /!< Position of PATCH4 field. /
jamesadevine	0:e1a608bb55e8	4726	#define PU_PATCHENSET_PATCH4_Msk (0x1UL << PU_PATCHENSET_PATCH4_Pos) /!< Bit mask of PATCH4 field. /
jamesadevine	0:e1a608bb55e8	4727	#define PU_PATCHENSET_PATCH4_Disabled (0UL) /!< Patch disabled. /
jamesadevine	0:e1a608bb55e8	4728	#define PU_PATCHENSET_PATCH4_Enabled (1UL) /!< Patch enabled. /
jamesadevine	0:e1a608bb55e8	4729	#define PU_PATCHENSET_PATCH4_Set (1UL) /!< Enable patch on write. /
jamesadevine	0:e1a608bb55e8	4730
jamesadevine	0:e1a608bb55e8	4731	/* Bit 3 : Patch 3 enabled. */
jamesadevine	0:e1a608bb55e8	4732	#define PU_PATCHENSET_PATCH3_Pos (3UL) /!< Position of PATCH3 field. /
jamesadevine	0:e1a608bb55e8	4733	#define PU_PATCHENSET_PATCH3_Msk (0x1UL << PU_PATCHENSET_PATCH3_Pos) /!< Bit mask of PATCH3 field. /
jamesadevine	0:e1a608bb55e8	4734	#define PU_PATCHENSET_PATCH3_Disabled (0UL) /!< Patch disabled. /
jamesadevine	0:e1a608bb55e8	4735	#define PU_PATCHENSET_PATCH3_Enabled (1UL) /!< Patch enabled. /
jamesadevine	0:e1a608bb55e8	4736	#define PU_PATCHENSET_PATCH3_Set (1UL) /!< Enable patch on write. /
jamesadevine	0:e1a608bb55e8	4737
jamesadevine	0:e1a608bb55e8	4738	/* Bit 2 : Patch 2 enabled. */
jamesadevine	0:e1a608bb55e8	4739	#define PU_PATCHENSET_PATCH2_Pos (2UL) /!< Position of PATCH2 field. /
jamesadevine	0:e1a608bb55e8	4740	#define PU_PATCHENSET_PATCH2_Msk (0x1UL << PU_PATCHENSET_PATCH2_Pos) /!< Bit mask of PATCH2 field. /
jamesadevine	0:e1a608bb55e8	4741	#define PU_PATCHENSET_PATCH2_Disabled (0UL) /!< Patch disabled. /
jamesadevine	0:e1a608bb55e8	4742	#define PU_PATCHENSET_PATCH2_Enabled (1UL) /!< Patch enabled. /
jamesadevine	0:e1a608bb55e8	4743	#define PU_PATCHENSET_PATCH2_Set (1UL) /!< Enable patch on write. /
jamesadevine	0:e1a608bb55e8	4744
jamesadevine	0:e1a608bb55e8	4745	/* Bit 1 : Patch 1 enabled. */
jamesadevine	0:e1a608bb55e8	4746	#define PU_PATCHENSET_PATCH1_Pos (1UL) /!< Position of PATCH1 field. /
jamesadevine	0:e1a608bb55e8	4747	#define PU_PATCHENSET_PATCH1_Msk (0x1UL << PU_PATCHENSET_PATCH1_Pos) /!< Bit mask of PATCH1 field. /
jamesadevine	0:e1a608bb55e8	4748	#define PU_PATCHENSET_PATCH1_Disabled (0UL) /!< Patch disabled. /
jamesadevine	0:e1a608bb55e8	4749	#define PU_PATCHENSET_PATCH1_Enabled (1UL) /!< Patch enabled. /
jamesadevine	0:e1a608bb55e8	4750	#define PU_PATCHENSET_PATCH1_Set (1UL) /!< Enable patch on write. /
jamesadevine	0:e1a608bb55e8	4751
jamesadevine	0:e1a608bb55e8	4752	/* Bit 0 : Patch 0 enabled. */
jamesadevine	0:e1a608bb55e8	4753	#define PU_PATCHENSET_PATCH0_Pos (0UL) /!< Position of PATCH0 field. /
jamesadevine	0:e1a608bb55e8	4754	#define PU_PATCHENSET_PATCH0_Msk (0x1UL << PU_PATCHENSET_PATCH0_Pos) /!< Bit mask of PATCH0 field. /
jamesadevine	0:e1a608bb55e8	4755	#define PU_PATCHENSET_PATCH0_Disabled (0UL) /!< Patch disabled. /
jamesadevine	0:e1a608bb55e8	4756	#define PU_PATCHENSET_PATCH0_Enabled (1UL) /!< Patch enabled. /
jamesadevine	0:e1a608bb55e8	4757	#define PU_PATCHENSET_PATCH0_Set (1UL) /!< Enable patch on write. /
jamesadevine	0:e1a608bb55e8	4758
jamesadevine	0:e1a608bb55e8	4759	/* Register: PU_PATCHENCLR */
jamesadevine	0:e1a608bb55e8	4760	/* Description: Patch disable register. */
jamesadevine	0:e1a608bb55e8	4761
jamesadevine	0:e1a608bb55e8	4762	/* Bit 7 : Patch 7 enabled. */
jamesadevine	0:e1a608bb55e8	4763	#define PU_PATCHENCLR_PATCH7_Pos (7UL) /!< Position of PATCH7 field. /
jamesadevine	0:e1a608bb55e8	4764	#define PU_PATCHENCLR_PATCH7_Msk (0x1UL << PU_PATCHENCLR_PATCH7_Pos) /!< Bit mask of PATCH7 field. /
jamesadevine	0:e1a608bb55e8	4765	#define PU_PATCHENCLR_PATCH7_Disabled (0UL) /!< Patch disabled. /
jamesadevine	0:e1a608bb55e8	4766	#define PU_PATCHENCLR_PATCH7_Enabled (1UL) /!< Patch enabled. /
jamesadevine	0:e1a608bb55e8	4767	#define PU_PATCHENCLR_PATCH7_Clear (1UL) /!< Disable patch on write. /
jamesadevine	0:e1a608bb55e8	4768
jamesadevine	0:e1a608bb55e8	4769	/* Bit 6 : Patch 6 enabled. */
jamesadevine	0:e1a608bb55e8	4770	#define PU_PATCHENCLR_PATCH6_Pos (6UL) /!< Position of PATCH6 field. /
jamesadevine	0:e1a608bb55e8	4771	#define PU_PATCHENCLR_PATCH6_Msk (0x1UL << PU_PATCHENCLR_PATCH6_Pos) /!< Bit mask of PATCH6 field. /
jamesadevine	0:e1a608bb55e8	4772	#define PU_PATCHENCLR_PATCH6_Disabled (0UL) /!< Patch disabled. /
jamesadevine	0:e1a608bb55e8	4773	#define PU_PATCHENCLR_PATCH6_Enabled (1UL) /!< Patch enabled. /
jamesadevine	0:e1a608bb55e8	4774	#define PU_PATCHENCLR_PATCH6_Clear (1UL) /!< Disable patch on write. /
jamesadevine	0:e1a608bb55e8	4775
jamesadevine	0:e1a608bb55e8	4776	/* Bit 5 : Patch 5 enabled. */
jamesadevine	0:e1a608bb55e8	4777	#define PU_PATCHENCLR_PATCH5_Pos (5UL) /!< Position of PATCH5 field. /
jamesadevine	0:e1a608bb55e8	4778	#define PU_PATCHENCLR_PATCH5_Msk (0x1UL << PU_PATCHENCLR_PATCH5_Pos) /!< Bit mask of PATCH5 field. /
jamesadevine	0:e1a608bb55e8	4779	#define PU_PATCHENCLR_PATCH5_Disabled (0UL) /!< Patch disabled. /
jamesadevine	0:e1a608bb55e8	4780	#define PU_PATCHENCLR_PATCH5_Enabled (1UL) /!< Patch enabled. /
jamesadevine	0:e1a608bb55e8	4781	#define PU_PATCHENCLR_PATCH5_Clear (1UL) /!< Disable patch on write. /
jamesadevine	0:e1a608bb55e8	4782
jamesadevine	0:e1a608bb55e8	4783	/* Bit 4 : Patch 4 enabled. */
jamesadevine	0:e1a608bb55e8	4784	#define PU_PATCHENCLR_PATCH4_Pos (4UL) /!< Position of PATCH4 field. /
jamesadevine	0:e1a608bb55e8	4785	#define PU_PATCHENCLR_PATCH4_Msk (0x1UL << PU_PATCHENCLR_PATCH4_Pos) /!< Bit mask of PATCH4 field. /
jamesadevine	0:e1a608bb55e8	4786	#define PU_PATCHENCLR_PATCH4_Disabled (0UL) /!< Patch disabled. /
jamesadevine	0:e1a608bb55e8	4787	#define PU_PATCHENCLR_PATCH4_Enabled (1UL) /!< Patch enabled. /
jamesadevine	0:e1a608bb55e8	4788	#define PU_PATCHENCLR_PATCH4_Clear (1UL) /!< Disable patch on write. /
jamesadevine	0:e1a608bb55e8	4789
jamesadevine	0:e1a608bb55e8	4790	/* Bit 3 : Patch 3 enabled. */
jamesadevine	0:e1a608bb55e8	4791	#define PU_PATCHENCLR_PATCH3_Pos (3UL) /!< Position of PATCH3 field. /
jamesadevine	0:e1a608bb55e8	4792	#define PU_PATCHENCLR_PATCH3_Msk (0x1UL << PU_PATCHENCLR_PATCH3_Pos) /!< Bit mask of PATCH3 field. /
jamesadevine	0:e1a608bb55e8	4793	#define PU_PATCHENCLR_PATCH3_Disabled (0UL) /!< Patch disabled. /
jamesadevine	0:e1a608bb55e8	4794	#define PU_PATCHENCLR_PATCH3_Enabled (1UL) /!< Patch enabled. /
jamesadevine	0:e1a608bb55e8	4795	#define PU_PATCHENCLR_PATCH3_Clear (1UL) /!< Disable patch on write. /
jamesadevine	0:e1a608bb55e8	4796
jamesadevine	0:e1a608bb55e8	4797	/* Bit 2 : Patch 2 enabled. */
jamesadevine	0:e1a608bb55e8	4798	#define PU_PATCHENCLR_PATCH2_Pos (2UL) /!< Position of PATCH2 field. /
jamesadevine	0:e1a608bb55e8	4799	#define PU_PATCHENCLR_PATCH2_Msk (0x1UL << PU_PATCHENCLR_PATCH2_Pos) /!< Bit mask of PATCH2 field. /
jamesadevine	0:e1a608bb55e8	4800	#define PU_PATCHENCLR_PATCH2_Disabled (0UL) /!< Patch disabled. /
jamesadevine	0:e1a608bb55e8	4801	#define PU_PATCHENCLR_PATCH2_Enabled (1UL) /!< Patch enabled. /
jamesadevine	0:e1a608bb55e8	4802	#define PU_PATCHENCLR_PATCH2_Clear (1UL) /!< Disable patch on write. /
jamesadevine	0:e1a608bb55e8	4803
jamesadevine	0:e1a608bb55e8	4804	/* Bit 1 : Patch 1 enabled. */
jamesadevine	0:e1a608bb55e8	4805	#define PU_PATCHENCLR_PATCH1_Pos (1UL) /!< Position of PATCH1 field. /
jamesadevine	0:e1a608bb55e8	4806	#define PU_PATCHENCLR_PATCH1_Msk (0x1UL << PU_PATCHENCLR_PATCH1_Pos) /!< Bit mask of PATCH1 field. /
jamesadevine	0:e1a608bb55e8	4807	#define PU_PATCHENCLR_PATCH1_Disabled (0UL) /!< Patch disabled. /
jamesadevine	0:e1a608bb55e8	4808	#define PU_PATCHENCLR_PATCH1_Enabled (1UL) /!< Patch enabled. /
jamesadevine	0:e1a608bb55e8	4809	#define PU_PATCHENCLR_PATCH1_Clear (1UL) /!< Disable patch on write. /
jamesadevine	0:e1a608bb55e8	4810
jamesadevine	0:e1a608bb55e8	4811	/* Bit 0 : Patch 0 enabled. */
jamesadevine	0:e1a608bb55e8	4812	#define PU_PATCHENCLR_PATCH0_Pos (0UL) /!< Position of PATCH0 field. /
jamesadevine	0:e1a608bb55e8	4813	#define PU_PATCHENCLR_PATCH0_Msk (0x1UL << PU_PATCHENCLR_PATCH0_Pos) /!< Bit mask of PATCH0 field. /
jamesadevine	0:e1a608bb55e8	4814	#define PU_PATCHENCLR_PATCH0_Disabled (0UL) /!< Patch disabled. /
jamesadevine	0:e1a608bb55e8	4815	#define PU_PATCHENCLR_PATCH0_Enabled (1UL) /!< Patch enabled. /
jamesadevine	0:e1a608bb55e8	4816	#define PU_PATCHENCLR_PATCH0_Clear (1UL) /!< Disable patch on write. /
jamesadevine	0:e1a608bb55e8	4817
jamesadevine	0:e1a608bb55e8	4818
jamesadevine	0:e1a608bb55e8	4819	/* Peripheral: QDEC */
jamesadevine	0:e1a608bb55e8	4820	/* Description: Rotary decoder. */
jamesadevine	0:e1a608bb55e8	4821
jamesadevine	0:e1a608bb55e8	4822	/* Register: QDEC_SHORTS */
jamesadevine	0:e1a608bb55e8	4823	/* Description: Shortcuts for the QDEC. */
jamesadevine	0:e1a608bb55e8	4824
jamesadevine	0:e1a608bb55e8	4825	/* Bit 1 : Shortcut between SAMPLERDY event and STOP task. */
jamesadevine	0:e1a608bb55e8	4826	#define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /!< Position of SAMPLERDY_STOP field. /
jamesadevine	0:e1a608bb55e8	4827	#define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /!< Bit mask of SAMPLERDY_STOP field. /
jamesadevine	0:e1a608bb55e8	4828	#define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /!< Shortcut disabled. /
jamesadevine	0:e1a608bb55e8	4829	#define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /!< Shortcut enabled. /
jamesadevine	0:e1a608bb55e8	4830
jamesadevine	0:e1a608bb55e8	4831	/* Bit 0 : Shortcut between REPORTRDY event and READCLRACC task. */
jamesadevine	0:e1a608bb55e8	4832	#define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /!< Position of REPORTRDY_READCLRACC field. /
jamesadevine	0:e1a608bb55e8	4833	#define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /!< Bit mask of REPORTRDY_READCLRACC field. /
jamesadevine	0:e1a608bb55e8	4834	#define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /!< Shortcut disabled. /
jamesadevine	0:e1a608bb55e8	4835	#define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (1UL) /!< Shortcut enabled. /
jamesadevine	0:e1a608bb55e8	4836
jamesadevine	0:e1a608bb55e8	4837	/* Register: QDEC_INTENSET */
jamesadevine	0:e1a608bb55e8	4838	/* Description: Interrupt enable set register. */
jamesadevine	0:e1a608bb55e8	4839
jamesadevine	0:e1a608bb55e8	4840	/* Bit 2 : Enable interrupt on ACCOF event. */
jamesadevine	0:e1a608bb55e8	4841	#define QDEC_INTENSET_ACCOF_Pos (2UL) /!< Position of ACCOF field. /
jamesadevine	0:e1a608bb55e8	4842	#define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /!< Bit mask of ACCOF field. /
jamesadevine	0:e1a608bb55e8	4843	#define QDEC_INTENSET_ACCOF_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	4844	#define QDEC_INTENSET_ACCOF_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	4845	#define QDEC_INTENSET_ACCOF_Set (1UL) /!< Enable interrupt on write. /
jamesadevine	0:e1a608bb55e8	4846
jamesadevine	0:e1a608bb55e8	4847	/* Bit 1 : Enable interrupt on REPORTRDY event. */
jamesadevine	0:e1a608bb55e8	4848	#define QDEC_INTENSET_REPORTRDY_Pos (1UL) /!< Position of REPORTRDY field. /
jamesadevine	0:e1a608bb55e8	4849	#define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /!< Bit mask of REPORTRDY field. /
jamesadevine	0:e1a608bb55e8	4850	#define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	4851	#define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	4852	#define QDEC_INTENSET_REPORTRDY_Set (1UL) /!< Enable interrupt on write. /
jamesadevine	0:e1a608bb55e8	4853
jamesadevine	0:e1a608bb55e8	4854	/* Bit 0 : Enable interrupt on SAMPLERDY event. */
jamesadevine	0:e1a608bb55e8	4855	#define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /!< Position of SAMPLERDY field. /
jamesadevine	0:e1a608bb55e8	4856	#define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /!< Bit mask of SAMPLERDY field. /
jamesadevine	0:e1a608bb55e8	4857	#define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	4858	#define QDEC_INTENSET_SAMPLERDY_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	4859	#define QDEC_INTENSET_SAMPLERDY_Set (1UL) /!< Enable interrupt on write. /
jamesadevine	0:e1a608bb55e8	4860
jamesadevine	0:e1a608bb55e8	4861	/* Register: QDEC_INTENCLR */
jamesadevine	0:e1a608bb55e8	4862	/* Description: Interrupt enable clear register. */
jamesadevine	0:e1a608bb55e8	4863
jamesadevine	0:e1a608bb55e8	4864	/* Bit 2 : Disable interrupt on ACCOF event. */
jamesadevine	0:e1a608bb55e8	4865	#define QDEC_INTENCLR_ACCOF_Pos (2UL) /!< Position of ACCOF field. /
jamesadevine	0:e1a608bb55e8	4866	#define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /!< Bit mask of ACCOF field. /
jamesadevine	0:e1a608bb55e8	4867	#define QDEC_INTENCLR_ACCOF_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	4868	#define QDEC_INTENCLR_ACCOF_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	4869	#define QDEC_INTENCLR_ACCOF_Clear (1UL) /!< Disable interrupt on write. /
jamesadevine	0:e1a608bb55e8	4870
jamesadevine	0:e1a608bb55e8	4871	/* Bit 1 : Disable interrupt on REPORTRDY event. */
jamesadevine	0:e1a608bb55e8	4872	#define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /!< Position of REPORTRDY field. /
jamesadevine	0:e1a608bb55e8	4873	#define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /!< Bit mask of REPORTRDY field. /
jamesadevine	0:e1a608bb55e8	4874	#define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	4875	#define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	4876	#define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /!< Disable interrupt on write. /
jamesadevine	0:e1a608bb55e8	4877
jamesadevine	0:e1a608bb55e8	4878	/* Bit 0 : Disable interrupt on SAMPLERDY event. */
jamesadevine	0:e1a608bb55e8	4879	#define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /!< Position of SAMPLERDY field. /
jamesadevine	0:e1a608bb55e8	4880	#define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /!< Bit mask of SAMPLERDY field. /
jamesadevine	0:e1a608bb55e8	4881	#define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	4882	#define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	4883	#define QDEC_INTENCLR_SAMPLERDY_Clear (1UL) /!< Disable interrupt on write. /
jamesadevine	0:e1a608bb55e8	4884
jamesadevine	0:e1a608bb55e8	4885	/* Register: QDEC_ENABLE */
jamesadevine	0:e1a608bb55e8	4886	/* Description: Enable the QDEC. */
jamesadevine	0:e1a608bb55e8	4887
jamesadevine	0:e1a608bb55e8	4888	/* Bit 0 : Enable or disable QDEC. */
jamesadevine	0:e1a608bb55e8	4889	#define QDEC_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
jamesadevine	0:e1a608bb55e8	4890	#define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
jamesadevine	0:e1a608bb55e8	4891	#define QDEC_ENABLE_ENABLE_Disabled (0UL) /!< Disabled QDEC. /
jamesadevine	0:e1a608bb55e8	4892	#define QDEC_ENABLE_ENABLE_Enabled (1UL) /!< Enable QDEC. /
jamesadevine	0:e1a608bb55e8	4893
jamesadevine	0:e1a608bb55e8	4894	/* Register: QDEC_LEDPOL */
jamesadevine	0:e1a608bb55e8	4895	/* Description: LED output pin polarity. */
jamesadevine	0:e1a608bb55e8	4896
jamesadevine	0:e1a608bb55e8	4897	/* Bit 0 : LED output pin polarity. */
jamesadevine	0:e1a608bb55e8	4898	#define QDEC_LEDPOL_LEDPOL_Pos (0UL) /!< Position of LEDPOL field. /
jamesadevine	0:e1a608bb55e8	4899	#define QDEC_LEDPOL_LEDPOL_Msk (0x1UL << QDEC_LEDPOL_LEDPOL_Pos) /!< Bit mask of LEDPOL field. /
jamesadevine	0:e1a608bb55e8	4900	#define QDEC_LEDPOL_LEDPOL_ActiveLow (0UL) /!< LED output is active low. /
jamesadevine	0:e1a608bb55e8	4901	#define QDEC_LEDPOL_LEDPOL_ActiveHigh (1UL) /!< LED output is active high. /
jamesadevine	0:e1a608bb55e8	4902
jamesadevine	0:e1a608bb55e8	4903	/* Register: QDEC_SAMPLEPER */
jamesadevine	0:e1a608bb55e8	4904	/* Description: Sample period. */
jamesadevine	0:e1a608bb55e8	4905
jamesadevine	0:e1a608bb55e8	4906	/* Bits 2..0 : Sample period. */
jamesadevine	0:e1a608bb55e8	4907	#define QDEC_SAMPLEPER_SAMPLEPER_Pos (0UL) /!< Position of SAMPLEPER field. /
jamesadevine	0:e1a608bb55e8	4908	#define QDEC_SAMPLEPER_SAMPLEPER_Msk (0x7UL << QDEC_SAMPLEPER_SAMPLEPER_Pos) /!< Bit mask of SAMPLEPER field. /
jamesadevine	0:e1a608bb55e8	4909	#define QDEC_SAMPLEPER_SAMPLEPER_128us (0x00UL) /!< 128us sample period. /
jamesadevine	0:e1a608bb55e8	4910	#define QDEC_SAMPLEPER_SAMPLEPER_256us (0x01UL) /!< 256us sample period. /
jamesadevine	0:e1a608bb55e8	4911	#define QDEC_SAMPLEPER_SAMPLEPER_512us (0x02UL) /!< 512us sample period. /
jamesadevine	0:e1a608bb55e8	4912	#define QDEC_SAMPLEPER_SAMPLEPER_1024us (0x03UL) /!< 1024us sample period. /
jamesadevine	0:e1a608bb55e8	4913	#define QDEC_SAMPLEPER_SAMPLEPER_2048us (0x04UL) /!< 2048us sample period. /
jamesadevine	0:e1a608bb55e8	4914	#define QDEC_SAMPLEPER_SAMPLEPER_4096us (0x05UL) /!< 4096us sample period. /
jamesadevine	0:e1a608bb55e8	4915	#define QDEC_SAMPLEPER_SAMPLEPER_8192us (0x06UL) /!< 8192us sample period. /
jamesadevine	0:e1a608bb55e8	4916	#define QDEC_SAMPLEPER_SAMPLEPER_16384us (0x07UL) /!< 16384us sample period. /
jamesadevine	0:e1a608bb55e8	4917
jamesadevine	0:e1a608bb55e8	4918	/* Register: QDEC_SAMPLE */
jamesadevine	0:e1a608bb55e8	4919	/* Description: Motion sample value. */
jamesadevine	0:e1a608bb55e8	4920
jamesadevine	0:e1a608bb55e8	4921	/* Bits 31..0 : Last sample taken in compliment to 2. */
jamesadevine	0:e1a608bb55e8	4922	#define QDEC_SAMPLE_SAMPLE_Pos (0UL) /!< Position of SAMPLE field. /
jamesadevine	0:e1a608bb55e8	4923	#define QDEC_SAMPLE_SAMPLE_Msk (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos) /!< Bit mask of SAMPLE field. /
jamesadevine	0:e1a608bb55e8	4924
jamesadevine	0:e1a608bb55e8	4925	/* Register: QDEC_REPORTPER */
jamesadevine	0:e1a608bb55e8	4926	/* Description: Number of samples to generate an EVENT_REPORTRDY. */
jamesadevine	0:e1a608bb55e8	4927
jamesadevine	0:e1a608bb55e8	4928	/* Bits 2..0 : Number of samples to generate an EVENT_REPORTRDY. */
jamesadevine	0:e1a608bb55e8	4929	#define QDEC_REPORTPER_REPORTPER_Pos (0UL) /!< Position of REPORTPER field. /
jamesadevine	0:e1a608bb55e8	4930	#define QDEC_REPORTPER_REPORTPER_Msk (0x7UL << QDEC_REPORTPER_REPORTPER_Pos) /!< Bit mask of REPORTPER field. /
jamesadevine	0:e1a608bb55e8	4931	#define QDEC_REPORTPER_REPORTPER_10Smpl (0x00UL) /!< 10 samples per report. /
jamesadevine	0:e1a608bb55e8	4932	#define QDEC_REPORTPER_REPORTPER_40Smpl (0x01UL) /!< 40 samples per report. /
jamesadevine	0:e1a608bb55e8	4933	#define QDEC_REPORTPER_REPORTPER_80Smpl (0x02UL) /!< 80 samples per report. /
jamesadevine	0:e1a608bb55e8	4934	#define QDEC_REPORTPER_REPORTPER_120Smpl (0x03UL) /!< 120 samples per report. /
jamesadevine	0:e1a608bb55e8	4935	#define QDEC_REPORTPER_REPORTPER_160Smpl (0x04UL) /!< 160 samples per report. /
jamesadevine	0:e1a608bb55e8	4936	#define QDEC_REPORTPER_REPORTPER_200Smpl (0x05UL) /!< 200 samples per report. /
jamesadevine	0:e1a608bb55e8	4937	#define QDEC_REPORTPER_REPORTPER_240Smpl (0x06UL) /!< 240 samples per report. /
jamesadevine	0:e1a608bb55e8	4938	#define QDEC_REPORTPER_REPORTPER_280Smpl (0x07UL) /!< 280 samples per report. /
jamesadevine	0:e1a608bb55e8	4939
jamesadevine	0:e1a608bb55e8	4940	/* Register: QDEC_DBFEN */
jamesadevine	0:e1a608bb55e8	4941	/* Description: Enable debouncer input filters. */
jamesadevine	0:e1a608bb55e8	4942
jamesadevine	0:e1a608bb55e8	4943	/* Bit 0 : Enable debounce input filters. */
jamesadevine	0:e1a608bb55e8	4944	#define QDEC_DBFEN_DBFEN_Pos (0UL) /!< Position of DBFEN field. /
jamesadevine	0:e1a608bb55e8	4945	#define QDEC_DBFEN_DBFEN_Msk (0x1UL << QDEC_DBFEN_DBFEN_Pos) /!< Bit mask of DBFEN field. /
jamesadevine	0:e1a608bb55e8	4946	#define QDEC_DBFEN_DBFEN_Disabled (0UL) /!< Debounce input filters disabled. /
jamesadevine	0:e1a608bb55e8	4947	#define QDEC_DBFEN_DBFEN_Enabled (1UL) /!< Debounce input filters enabled. /
jamesadevine	0:e1a608bb55e8	4948
jamesadevine	0:e1a608bb55e8	4949	/* Register: QDEC_LEDPRE */
jamesadevine	0:e1a608bb55e8	4950	/* Description: Time LED is switched ON before the sample. */
jamesadevine	0:e1a608bb55e8	4951
jamesadevine	0:e1a608bb55e8	4952	/* Bits 8..0 : Period in us the LED in switched on prior to sampling. */
jamesadevine	0:e1a608bb55e8	4953	#define QDEC_LEDPRE_LEDPRE_Pos (0UL) /!< Position of LEDPRE field. /
jamesadevine	0:e1a608bb55e8	4954	#define QDEC_LEDPRE_LEDPRE_Msk (0x1FFUL << QDEC_LEDPRE_LEDPRE_Pos) /!< Bit mask of LEDPRE field. /
jamesadevine	0:e1a608bb55e8	4955
jamesadevine	0:e1a608bb55e8	4956	/* Register: QDEC_ACCDBL */
jamesadevine	0:e1a608bb55e8	4957	/* Description: Accumulated double (error) transitions register. */
jamesadevine	0:e1a608bb55e8	4958
jamesadevine	0:e1a608bb55e8	4959	/* Bits 3..0 : Accumulated double (error) transitions. */
jamesadevine	0:e1a608bb55e8	4960	#define QDEC_ACCDBL_ACCDBL_Pos (0UL) /!< Position of ACCDBL field. /
jamesadevine	0:e1a608bb55e8	4961	#define QDEC_ACCDBL_ACCDBL_Msk (0xFUL << QDEC_ACCDBL_ACCDBL_Pos) /!< Bit mask of ACCDBL field. /
jamesadevine	0:e1a608bb55e8	4962
jamesadevine	0:e1a608bb55e8	4963	/* Register: QDEC_ACCDBLREAD */
jamesadevine	0:e1a608bb55e8	4964	/* Description: Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC task. */
jamesadevine	0:e1a608bb55e8	4965
jamesadevine	0:e1a608bb55e8	4966	/* Bits 3..0 : Snapshot of accumulated double (error) transitions. */
jamesadevine	0:e1a608bb55e8	4967	#define QDEC_ACCDBLREAD_ACCDBLREAD_Pos (0UL) /!< Position of ACCDBLREAD field. /
jamesadevine	0:e1a608bb55e8	4968	#define QDEC_ACCDBLREAD_ACCDBLREAD_Msk (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos) /!< Bit mask of ACCDBLREAD field. /
jamesadevine	0:e1a608bb55e8	4969
jamesadevine	0:e1a608bb55e8	4970	/* Register: QDEC_POWER */
jamesadevine	0:e1a608bb55e8	4971	/* Description: Peripheral power control. */
jamesadevine	0:e1a608bb55e8	4972
jamesadevine	0:e1a608bb55e8	4973	/* Bit 0 : Peripheral power control. */
jamesadevine	0:e1a608bb55e8	4974	#define QDEC_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
jamesadevine	0:e1a608bb55e8	4975	#define QDEC_POWER_POWER_Msk (0x1UL << QDEC_POWER_POWER_Pos) /!< Bit mask of POWER field. /
jamesadevine	0:e1a608bb55e8	4976	#define QDEC_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
jamesadevine	0:e1a608bb55e8	4977	#define QDEC_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
jamesadevine	0:e1a608bb55e8	4978
jamesadevine	0:e1a608bb55e8	4979
jamesadevine	0:e1a608bb55e8	4980	/* Peripheral: RADIO */
jamesadevine	0:e1a608bb55e8	4981	/* Description: The radio. */
jamesadevine	0:e1a608bb55e8	4982
jamesadevine	0:e1a608bb55e8	4983	/* Register: RADIO_SHORTS */
jamesadevine	0:e1a608bb55e8	4984	/* Description: Shortcuts for the radio. */
jamesadevine	0:e1a608bb55e8	4985
jamesadevine	0:e1a608bb55e8	4986	/* Bit 8 : Shortcut between DISABLED event and RSSISTOP task. */
jamesadevine	0:e1a608bb55e8	4987	#define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /!< Position of DISABLED_RSSISTOP field. /
jamesadevine	0:e1a608bb55e8	4988	#define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /!< Bit mask of DISABLED_RSSISTOP field. /
jamesadevine	0:e1a608bb55e8	4989	#define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /!< Shortcut disabled. /
jamesadevine	0:e1a608bb55e8	4990	#define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /!< Shortcut enabled. /
jamesadevine	0:e1a608bb55e8	4991
jamesadevine	0:e1a608bb55e8	4992	/* Bit 6 : Shortcut between ADDRESS event and BCSTART task. */
jamesadevine	0:e1a608bb55e8	4993	#define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /!< Position of ADDRESS_BCSTART field. /
jamesadevine	0:e1a608bb55e8	4994	#define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /!< Bit mask of ADDRESS_BCSTART field. /
jamesadevine	0:e1a608bb55e8	4995	#define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /!< Shortcut disabled. /
jamesadevine	0:e1a608bb55e8	4996	#define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /!< Shortcut enabled. /
jamesadevine	0:e1a608bb55e8	4997
jamesadevine	0:e1a608bb55e8	4998	/* Bit 5 : Shortcut between END event and START task. */
jamesadevine	0:e1a608bb55e8	4999	#define RADIO_SHORTS_END_START_Pos (5UL) /!< Position of END_START field. /
jamesadevine	0:e1a608bb55e8	5000	#define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /!< Bit mask of END_START field. /
jamesadevine	0:e1a608bb55e8	5001	#define RADIO_SHORTS_END_START_Disabled (0UL) /!< Shortcut disabled. /
jamesadevine	0:e1a608bb55e8	5002	#define RADIO_SHORTS_END_START_Enabled (1UL) /!< Shortcut enabled. /
jamesadevine	0:e1a608bb55e8	5003
jamesadevine	0:e1a608bb55e8	5004	/* Bit 4 : Shortcut between ADDRESS event and RSSISTART task. */
jamesadevine	0:e1a608bb55e8	5005	#define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /!< Position of ADDRESS_RSSISTART field. /
jamesadevine	0:e1a608bb55e8	5006	#define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /!< Bit mask of ADDRESS_RSSISTART field. /
jamesadevine	0:e1a608bb55e8	5007	#define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /!< Shortcut disabled. /
jamesadevine	0:e1a608bb55e8	5008	#define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /!< Shortcut enabled. /
jamesadevine	0:e1a608bb55e8	5009
jamesadevine	0:e1a608bb55e8	5010	/* Bit 3 : Shortcut between DISABLED event and RXEN task. */
jamesadevine	0:e1a608bb55e8	5011	#define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /!< Position of DISABLED_RXEN field. /
jamesadevine	0:e1a608bb55e8	5012	#define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /!< Bit mask of DISABLED_RXEN field. /
jamesadevine	0:e1a608bb55e8	5013	#define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /!< Shortcut disabled. /
jamesadevine	0:e1a608bb55e8	5014	#define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /!< Shortcut enabled. /
jamesadevine	0:e1a608bb55e8	5015
jamesadevine	0:e1a608bb55e8	5016	/* Bit 2 : Shortcut between DISABLED event and TXEN task. */
jamesadevine	0:e1a608bb55e8	5017	#define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /!< Position of DISABLED_TXEN field. /
jamesadevine	0:e1a608bb55e8	5018	#define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /!< Bit mask of DISABLED_TXEN field. /
jamesadevine	0:e1a608bb55e8	5019	#define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /!< Shortcut disabled. /
jamesadevine	0:e1a608bb55e8	5020	#define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /!< Shortcut enabled. /
jamesadevine	0:e1a608bb55e8	5021
jamesadevine	0:e1a608bb55e8	5022	/* Bit 1 : Shortcut between END event and DISABLE task. */
jamesadevine	0:e1a608bb55e8	5023	#define RADIO_SHORTS_END_DISABLE_Pos (1UL) /!< Position of END_DISABLE field. /
jamesadevine	0:e1a608bb55e8	5024	#define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /!< Bit mask of END_DISABLE field. /
jamesadevine	0:e1a608bb55e8	5025	#define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /!< Shortcut disabled. /
jamesadevine	0:e1a608bb55e8	5026	#define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /!< Shortcut enabled. /
jamesadevine	0:e1a608bb55e8	5027
jamesadevine	0:e1a608bb55e8	5028	/* Bit 0 : Shortcut between READY event and START task. */
jamesadevine	0:e1a608bb55e8	5029	#define RADIO_SHORTS_READY_START_Pos (0UL) /!< Position of READY_START field. /
jamesadevine	0:e1a608bb55e8	5030	#define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /!< Bit mask of READY_START field. /
jamesadevine	0:e1a608bb55e8	5031	#define RADIO_SHORTS_READY_START_Disabled (0UL) /!< Shortcut disabled. /
jamesadevine	0:e1a608bb55e8	5032	#define RADIO_SHORTS_READY_START_Enabled (1UL) /!< Shortcut enabled. /
jamesadevine	0:e1a608bb55e8	5033
jamesadevine	0:e1a608bb55e8	5034	/* Register: RADIO_INTENSET */
jamesadevine	0:e1a608bb55e8	5035	/* Description: Interrupt enable set register. */
jamesadevine	0:e1a608bb55e8	5036
jamesadevine	0:e1a608bb55e8	5037	/* Bit 10 : Enable interrupt on BCMATCH event. */
jamesadevine	0:e1a608bb55e8	5038	#define RADIO_INTENSET_BCMATCH_Pos (10UL) /!< Position of BCMATCH field. /
jamesadevine	0:e1a608bb55e8	5039	#define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /!< Bit mask of BCMATCH field. /
jamesadevine	0:e1a608bb55e8	5040	#define RADIO_INTENSET_BCMATCH_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	5041	#define RADIO_INTENSET_BCMATCH_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	5042	#define RADIO_INTENSET_BCMATCH_Set (1UL) /!< Enable interrupt on write. /
jamesadevine	0:e1a608bb55e8	5043
jamesadevine	0:e1a608bb55e8	5044	/* Bit 7 : Enable interrupt on RSSIEND event. */
jamesadevine	0:e1a608bb55e8	5045	#define RADIO_INTENSET_RSSIEND_Pos (7UL) /!< Position of RSSIEND field. /
jamesadevine	0:e1a608bb55e8	5046	#define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /!< Bit mask of RSSIEND field. /
jamesadevine	0:e1a608bb55e8	5047	#define RADIO_INTENSET_RSSIEND_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	5048	#define RADIO_INTENSET_RSSIEND_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	5049	#define RADIO_INTENSET_RSSIEND_Set (1UL) /!< Enable interrupt on write. /
jamesadevine	0:e1a608bb55e8	5050
jamesadevine	0:e1a608bb55e8	5051	/* Bit 6 : Enable interrupt on DEVMISS event. */
jamesadevine	0:e1a608bb55e8	5052	#define RADIO_INTENSET_DEVMISS_Pos (6UL) /!< Position of DEVMISS field. /
jamesadevine	0:e1a608bb55e8	5053	#define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /!< Bit mask of DEVMISS field. /
jamesadevine	0:e1a608bb55e8	5054	#define RADIO_INTENSET_DEVMISS_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	5055	#define RADIO_INTENSET_DEVMISS_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	5056	#define RADIO_INTENSET_DEVMISS_Set (1UL) /!< Enable interrupt on write. /
jamesadevine	0:e1a608bb55e8	5057
jamesadevine	0:e1a608bb55e8	5058	/* Bit 5 : Enable interrupt on DEVMATCH event. */
jamesadevine	0:e1a608bb55e8	5059	#define RADIO_INTENSET_DEVMATCH_Pos (5UL) /!< Position of DEVMATCH field. /
jamesadevine	0:e1a608bb55e8	5060	#define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /!< Bit mask of DEVMATCH field. /
jamesadevine	0:e1a608bb55e8	5061	#define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	5062	#define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	5063	#define RADIO_INTENSET_DEVMATCH_Set (1UL) /!< Enable interrupt on write. /
jamesadevine	0:e1a608bb55e8	5064
jamesadevine	0:e1a608bb55e8	5065	/* Bit 4 : Enable interrupt on DISABLED event. */
jamesadevine	0:e1a608bb55e8	5066	#define RADIO_INTENSET_DISABLED_Pos (4UL) /!< Position of DISABLED field. /
jamesadevine	0:e1a608bb55e8	5067	#define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /!< Bit mask of DISABLED field. /
jamesadevine	0:e1a608bb55e8	5068	#define RADIO_INTENSET_DISABLED_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	5069	#define RADIO_INTENSET_DISABLED_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	5070	#define RADIO_INTENSET_DISABLED_Set (1UL) /!< Enable interrupt on write. /
jamesadevine	0:e1a608bb55e8	5071
jamesadevine	0:e1a608bb55e8	5072	/* Bit 3 : Enable interrupt on END event. */
jamesadevine	0:e1a608bb55e8	5073	#define RADIO_INTENSET_END_Pos (3UL) /!< Position of END field. /
jamesadevine	0:e1a608bb55e8	5074	#define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /!< Bit mask of END field. /
jamesadevine	0:e1a608bb55e8	5075	#define RADIO_INTENSET_END_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	5076	#define RADIO_INTENSET_END_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	5077	#define RADIO_INTENSET_END_Set (1UL) /!< Enable interrupt on write. /
jamesadevine	0:e1a608bb55e8	5078
jamesadevine	0:e1a608bb55e8	5079	/* Bit 2 : Enable interrupt on PAYLOAD event. */
jamesadevine	0:e1a608bb55e8	5080	#define RADIO_INTENSET_PAYLOAD_Pos (2UL) /!< Position of PAYLOAD field. /
jamesadevine	0:e1a608bb55e8	5081	#define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /!< Bit mask of PAYLOAD field. /
jamesadevine	0:e1a608bb55e8	5082	#define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	5083	#define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	5084	#define RADIO_INTENSET_PAYLOAD_Set (1UL) /!< Enable interrupt on write. /
jamesadevine	0:e1a608bb55e8	5085
jamesadevine	0:e1a608bb55e8	5086	/* Bit 1 : Enable interrupt on ADDRESS event. */
jamesadevine	0:e1a608bb55e8	5087	#define RADIO_INTENSET_ADDRESS_Pos (1UL) /!< Position of ADDRESS field. /
jamesadevine	0:e1a608bb55e8	5088	#define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /!< Bit mask of ADDRESS field. /
jamesadevine	0:e1a608bb55e8	5089	#define RADIO_INTENSET_ADDRESS_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	5090	#define RADIO_INTENSET_ADDRESS_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	5091	#define RADIO_INTENSET_ADDRESS_Set (1UL) /!< Enable interrupt on write. /
jamesadevine	0:e1a608bb55e8	5092
jamesadevine	0:e1a608bb55e8	5093	/* Bit 0 : Enable interrupt on READY event. */
jamesadevine	0:e1a608bb55e8	5094	#define RADIO_INTENSET_READY_Pos (0UL) /!< Position of READY field. /
jamesadevine	0:e1a608bb55e8	5095	#define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /!< Bit mask of READY field. /
jamesadevine	0:e1a608bb55e8	5096	#define RADIO_INTENSET_READY_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	5097	#define RADIO_INTENSET_READY_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	5098	#define RADIO_INTENSET_READY_Set (1UL) /!< Enable interrupt on write. /
jamesadevine	0:e1a608bb55e8	5099
jamesadevine	0:e1a608bb55e8	5100	/* Register: RADIO_INTENCLR */
jamesadevine	0:e1a608bb55e8	5101	/* Description: Interrupt enable clear register. */
jamesadevine	0:e1a608bb55e8	5102
jamesadevine	0:e1a608bb55e8	5103	/* Bit 10 : Disable interrupt on BCMATCH event. */
jamesadevine	0:e1a608bb55e8	5104	#define RADIO_INTENCLR_BCMATCH_Pos (10UL) /!< Position of BCMATCH field. /
jamesadevine	0:e1a608bb55e8	5105	#define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /!< Bit mask of BCMATCH field. /
jamesadevine	0:e1a608bb55e8	5106	#define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	5107	#define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	5108	#define RADIO_INTENCLR_BCMATCH_Clear (1UL) /!< Disable interrupt on write. /
jamesadevine	0:e1a608bb55e8	5109
jamesadevine	0:e1a608bb55e8	5110	/* Bit 7 : Disable interrupt on RSSIEND event. */
jamesadevine	0:e1a608bb55e8	5111	#define RADIO_INTENCLR_RSSIEND_Pos (7UL) /!< Position of RSSIEND field. /
jamesadevine	0:e1a608bb55e8	5112	#define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /!< Bit mask of RSSIEND field. /
jamesadevine	0:e1a608bb55e8	5113	#define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	5114	#define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	5115	#define RADIO_INTENCLR_RSSIEND_Clear (1UL) /!< Disable interrupt on write. /
jamesadevine	0:e1a608bb55e8	5116
jamesadevine	0:e1a608bb55e8	5117	/* Bit 6 : Disable interrupt on DEVMISS event. */
jamesadevine	0:e1a608bb55e8	5118	#define RADIO_INTENCLR_DEVMISS_Pos (6UL) /!< Position of DEVMISS field. /
jamesadevine	0:e1a608bb55e8	5119	#define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /!< Bit mask of DEVMISS field. /
jamesadevine	0:e1a608bb55e8	5120	#define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	5121	#define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	5122	#define RADIO_INTENCLR_DEVMISS_Clear (1UL) /!< Disable interrupt on write. /
jamesadevine	0:e1a608bb55e8	5123
jamesadevine	0:e1a608bb55e8	5124	/* Bit 5 : Disable interrupt on DEVMATCH event. */
jamesadevine	0:e1a608bb55e8	5125	#define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /!< Position of DEVMATCH field. /
jamesadevine	0:e1a608bb55e8	5126	#define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /!< Bit mask of DEVMATCH field. /
jamesadevine	0:e1a608bb55e8	5127	#define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	5128	#define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	5129	#define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /!< Disable interrupt on write. /
jamesadevine	0:e1a608bb55e8	5130
jamesadevine	0:e1a608bb55e8	5131	/* Bit 4 : Disable interrupt on DISABLED event. */
jamesadevine	0:e1a608bb55e8	5132	#define RADIO_INTENCLR_DISABLED_Pos (4UL) /!< Position of DISABLED field. /
jamesadevine	0:e1a608bb55e8	5133	#define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /!< Bit mask of DISABLED field. /
jamesadevine	0:e1a608bb55e8	5134	#define RADIO_INTENCLR_DISABLED_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	5135	#define RADIO_INTENCLR_DISABLED_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	5136	#define RADIO_INTENCLR_DISABLED_Clear (1UL) /!< Disable interrupt on write. /
jamesadevine	0:e1a608bb55e8	5137
jamesadevine	0:e1a608bb55e8	5138	/* Bit 3 : Disable interrupt on END event. */
jamesadevine	0:e1a608bb55e8	5139	#define RADIO_INTENCLR_END_Pos (3UL) /!< Position of END field. /
jamesadevine	0:e1a608bb55e8	5140	#define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /!< Bit mask of END field. /
jamesadevine	0:e1a608bb55e8	5141	#define RADIO_INTENCLR_END_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	5142	#define RADIO_INTENCLR_END_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	5143	#define RADIO_INTENCLR_END_Clear (1UL) /!< Disable interrupt on write. /
jamesadevine	0:e1a608bb55e8	5144
jamesadevine	0:e1a608bb55e8	5145	/* Bit 2 : Disable interrupt on PAYLOAD event. */
jamesadevine	0:e1a608bb55e8	5146	#define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /!< Position of PAYLOAD field. /
jamesadevine	0:e1a608bb55e8	5147	#define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /!< Bit mask of PAYLOAD field. /
jamesadevine	0:e1a608bb55e8	5148	#define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	5149	#define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	5150	#define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /!< Disable interrupt on write. /
jamesadevine	0:e1a608bb55e8	5151
jamesadevine	0:e1a608bb55e8	5152	/* Bit 1 : Disable interrupt on ADDRESS event. */
jamesadevine	0:e1a608bb55e8	5153	#define RADIO_INTENCLR_ADDRESS_Pos (1UL) /!< Position of ADDRESS field. /
jamesadevine	0:e1a608bb55e8	5154	#define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /!< Bit mask of ADDRESS field. /
jamesadevine	0:e1a608bb55e8	5155	#define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	5156	#define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	5157	#define RADIO_INTENCLR_ADDRESS_Clear (1UL) /!< Disable interrupt on write. /
jamesadevine	0:e1a608bb55e8	5158
jamesadevine	0:e1a608bb55e8	5159	/* Bit 0 : Disable interrupt on READY event. */
jamesadevine	0:e1a608bb55e8	5160	#define RADIO_INTENCLR_READY_Pos (0UL) /!< Position of READY field. /
jamesadevine	0:e1a608bb55e8	5161	#define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /!< Bit mask of READY field. /
jamesadevine	0:e1a608bb55e8	5162	#define RADIO_INTENCLR_READY_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	5163	#define RADIO_INTENCLR_READY_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	5164	#define RADIO_INTENCLR_READY_Clear (1UL) /!< Disable interrupt on write. /
jamesadevine	0:e1a608bb55e8	5165
jamesadevine	0:e1a608bb55e8	5166	/* Register: RADIO_CRCSTATUS */
jamesadevine	0:e1a608bb55e8	5167	/* Description: CRC status of received packet. */
jamesadevine	0:e1a608bb55e8	5168
jamesadevine	0:e1a608bb55e8	5169	/* Bit 0 : CRC status of received packet. */
jamesadevine	0:e1a608bb55e8	5170	#define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL) /!< Position of CRCSTATUS field. /
jamesadevine	0:e1a608bb55e8	5171	#define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos) /!< Bit mask of CRCSTATUS field. /
jamesadevine	0:e1a608bb55e8	5172	#define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL) /!< Packet received with CRC error. /
jamesadevine	0:e1a608bb55e8	5173	#define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL) /!< Packet received with CRC ok. /
jamesadevine	0:e1a608bb55e8	5174
jamesadevine	0:e1a608bb55e8	5175	/* Register: RADIO_CD */
jamesadevine	0:e1a608bb55e8	5176	/* Description: Carrier detect. */
jamesadevine	0:e1a608bb55e8	5177
jamesadevine	0:e1a608bb55e8	5178	/* Bit 0 : Carrier detect. */
jamesadevine	0:e1a608bb55e8	5179	#define RADIO_CD_CD_Pos (0UL) /!< Position of CD field. /
jamesadevine	0:e1a608bb55e8	5180	#define RADIO_CD_CD_Msk (0x1UL << RADIO_CD_CD_Pos) /!< Bit mask of CD field. /
jamesadevine	0:e1a608bb55e8	5181
jamesadevine	0:e1a608bb55e8	5182	/* Register: RADIO_RXMATCH */
jamesadevine	0:e1a608bb55e8	5183	/* Description: Received address. */
jamesadevine	0:e1a608bb55e8	5184
jamesadevine	0:e1a608bb55e8	5185	/* Bits 2..0 : Logical address in which previous packet was received. */
jamesadevine	0:e1a608bb55e8	5186	#define RADIO_RXMATCH_RXMATCH_Pos (0UL) /!< Position of RXMATCH field. /
jamesadevine	0:e1a608bb55e8	5187	#define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos) /!< Bit mask of RXMATCH field. /
jamesadevine	0:e1a608bb55e8	5188
jamesadevine	0:e1a608bb55e8	5189	/* Register: RADIO_RXCRC */
jamesadevine	0:e1a608bb55e8	5190	/* Description: Received CRC. */
jamesadevine	0:e1a608bb55e8	5191
jamesadevine	0:e1a608bb55e8	5192	/* Bits 23..0 : CRC field of previously received packet. */
jamesadevine	0:e1a608bb55e8	5193	#define RADIO_RXCRC_RXCRC_Pos (0UL) /!< Position of RXCRC field. /
jamesadevine	0:e1a608bb55e8	5194	#define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos) /!< Bit mask of RXCRC field. /
jamesadevine	0:e1a608bb55e8	5195
jamesadevine	0:e1a608bb55e8	5196	/* Register: RADIO_DAI */
jamesadevine	0:e1a608bb55e8	5197	/* Description: Device address match index. */
jamesadevine	0:e1a608bb55e8	5198
jamesadevine	0:e1a608bb55e8	5199	/* Bits 2..0 : Index (n) of device address (see DAB[n] and DAP[n]) that obtained an address match. */
jamesadevine	0:e1a608bb55e8	5200	#define RADIO_DAI_DAI_Pos (0UL) /!< Position of DAI field. /
jamesadevine	0:e1a608bb55e8	5201	#define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /!< Bit mask of DAI field. /
jamesadevine	0:e1a608bb55e8	5202
jamesadevine	0:e1a608bb55e8	5203	/* Register: RADIO_FREQUENCY */
jamesadevine	0:e1a608bb55e8	5204	/* Description: Frequency. */
jamesadevine	0:e1a608bb55e8	5205
jamesadevine	0:e1a608bb55e8	5206	/* Bits 6..0 : Radio channel frequency offset in MHz: RF Frequency = 2400 + FREQUENCY (MHz). Decision point: TXEN or RXEN task. */
jamesadevine	0:e1a608bb55e8	5207	#define RADIO_FREQUENCY_FREQUENCY_Pos (0UL) /!< Position of FREQUENCY field. /
jamesadevine	0:e1a608bb55e8	5208	#define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos) /!< Bit mask of FREQUENCY field. /
jamesadevine	0:e1a608bb55e8	5209
jamesadevine	0:e1a608bb55e8	5210	/* Register: RADIO_TXPOWER */
jamesadevine	0:e1a608bb55e8	5211	/* Description: Output power. */
jamesadevine	0:e1a608bb55e8	5212
jamesadevine	0:e1a608bb55e8	5213	/* Bits 7..0 : Radio output power. Decision point: TXEN task. */
jamesadevine	0:e1a608bb55e8	5214	#define RADIO_TXPOWER_TXPOWER_Pos (0UL) /!< Position of TXPOWER field. /
jamesadevine	0:e1a608bb55e8	5215	#define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /!< Bit mask of TXPOWER field. /
jamesadevine	0:e1a608bb55e8	5216	#define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x04UL) /!< +4dBm. /
jamesadevine	0:e1a608bb55e8	5217	#define RADIO_TXPOWER_TXPOWER_0dBm (0x00UL) /!< 0dBm. /
jamesadevine	0:e1a608bb55e8	5218	#define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /!< -4dBm. /
jamesadevine	0:e1a608bb55e8	5219	#define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /!< -8dBm. /
jamesadevine	0:e1a608bb55e8	5220	#define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /!< -12dBm. /
jamesadevine	0:e1a608bb55e8	5221	#define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /!< -16dBm. /
jamesadevine	0:e1a608bb55e8	5222	#define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /!< -20dBm. /
jamesadevine	0:e1a608bb55e8	5223	#define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xD8UL) /!< -30dBm. /
jamesadevine	0:e1a608bb55e8	5224
jamesadevine	0:e1a608bb55e8	5225	/* Register: RADIO_MODE */
jamesadevine	0:e1a608bb55e8	5226	/* Description: Data rate and modulation. */
jamesadevine	0:e1a608bb55e8	5227
jamesadevine	0:e1a608bb55e8	5228	/* Bits 1..0 : Radio data rate and modulation setting. Decision point: TXEN or RXEN task. */
jamesadevine	0:e1a608bb55e8	5229	#define RADIO_MODE_MODE_Pos (0UL) /!< Position of MODE field. /
jamesadevine	0:e1a608bb55e8	5230	#define RADIO_MODE_MODE_Msk (0x3UL << RADIO_MODE_MODE_Pos) /!< Bit mask of MODE field. /
jamesadevine	0:e1a608bb55e8	5231	#define RADIO_MODE_MODE_Nrf_1Mbit (0x00UL) /!< 1Mbit/s Nordic propietary radio mode. /
jamesadevine	0:e1a608bb55e8	5232	#define RADIO_MODE_MODE_Nrf_2Mbit (0x01UL) /!< 2Mbit/s Nordic propietary radio mode. /
jamesadevine	0:e1a608bb55e8	5233	#define RADIO_MODE_MODE_Nrf_250Kbit (0x02UL) /!< 250kbit/s Nordic propietary radio mode. /
jamesadevine	0:e1a608bb55e8	5234	#define RADIO_MODE_MODE_Ble_1Mbit (0x03UL) /!< 1Mbit/s Bluetooth Low Energy /
jamesadevine	0:e1a608bb55e8	5235
jamesadevine	0:e1a608bb55e8	5236	/* Register: RADIO_PCNF0 */
jamesadevine	0:e1a608bb55e8	5237	/* Description: Packet configuration 0. */
jamesadevine	0:e1a608bb55e8	5238
jamesadevine	0:e1a608bb55e8	5239	/* Bits 19..16 : Length of S1 field in number of bits. Decision point: START task. */
jamesadevine	0:e1a608bb55e8	5240	#define RADIO_PCNF0_S1LEN_Pos (16UL) /!< Position of S1LEN field. /
jamesadevine	0:e1a608bb55e8	5241	#define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /!< Bit mask of S1LEN field. /
jamesadevine	0:e1a608bb55e8	5242
jamesadevine	0:e1a608bb55e8	5243	/* Bit 8 : Length of S0 field in number of bytes. Decision point: START task. */
jamesadevine	0:e1a608bb55e8	5244	#define RADIO_PCNF0_S0LEN_Pos (8UL) /!< Position of S0LEN field. /
jamesadevine	0:e1a608bb55e8	5245	#define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /!< Bit mask of S0LEN field. /
jamesadevine	0:e1a608bb55e8	5246
jamesadevine	0:e1a608bb55e8	5247	/* Bits 3..0 : Length of length field in number of bits. Decision point: START task. */
jamesadevine	0:e1a608bb55e8	5248	#define RADIO_PCNF0_LFLEN_Pos (0UL) /!< Position of LFLEN field. /
jamesadevine	0:e1a608bb55e8	5249	#define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /!< Bit mask of LFLEN field. /
jamesadevine	0:e1a608bb55e8	5250
jamesadevine	0:e1a608bb55e8	5251	/* Register: RADIO_PCNF1 */
jamesadevine	0:e1a608bb55e8	5252	/* Description: Packet configuration 1. */
jamesadevine	0:e1a608bb55e8	5253
jamesadevine	0:e1a608bb55e8	5254	/* Bit 25 : Packet whitening enable. */
jamesadevine	0:e1a608bb55e8	5255	#define RADIO_PCNF1_WHITEEN_Pos (25UL) /!< Position of WHITEEN field. /
jamesadevine	0:e1a608bb55e8	5256	#define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos) /!< Bit mask of WHITEEN field. /
jamesadevine	0:e1a608bb55e8	5257	#define RADIO_PCNF1_WHITEEN_Disabled (0UL) /!< Whitening disabled. /
jamesadevine	0:e1a608bb55e8	5258	#define RADIO_PCNF1_WHITEEN_Enabled (1UL) /!< Whitening enabled. /
jamesadevine	0:e1a608bb55e8	5259
jamesadevine	0:e1a608bb55e8	5260	/* Bit 24 : On air endianness of packet length field. Decision point: START task. */
jamesadevine	0:e1a608bb55e8	5261	#define RADIO_PCNF1_ENDIAN_Pos (24UL) /!< Position of ENDIAN field. /
jamesadevine	0:e1a608bb55e8	5262	#define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /!< Bit mask of ENDIAN field. /
jamesadevine	0:e1a608bb55e8	5263	#define RADIO_PCNF1_ENDIAN_Little (0UL) /!< Least significant bit on air first /
jamesadevine	0:e1a608bb55e8	5264	#define RADIO_PCNF1_ENDIAN_Big (1UL) /!< Most significant bit on air first /
jamesadevine	0:e1a608bb55e8	5265
jamesadevine	0:e1a608bb55e8	5266	/* Bits 18..16 : Base address length in number of bytes. Decision point: START task. */
jamesadevine	0:e1a608bb55e8	5267	#define RADIO_PCNF1_BALEN_Pos (16UL) /!< Position of BALEN field. /
jamesadevine	0:e1a608bb55e8	5268	#define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos) /!< Bit mask of BALEN field. /
jamesadevine	0:e1a608bb55e8	5269
jamesadevine	0:e1a608bb55e8	5270	/* Bits 15..8 : Static length in number of bytes. Decision point: START task. */
jamesadevine	0:e1a608bb55e8	5271	#define RADIO_PCNF1_STATLEN_Pos (8UL) /!< Position of STATLEN field. /
jamesadevine	0:e1a608bb55e8	5272	#define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos) /!< Bit mask of STATLEN field. /
jamesadevine	0:e1a608bb55e8	5273
jamesadevine	0:e1a608bb55e8	5274	/* Bits 7..0 : Maximum length of packet payload in number of bytes. */
jamesadevine	0:e1a608bb55e8	5275	#define RADIO_PCNF1_MAXLEN_Pos (0UL) /!< Position of MAXLEN field. /
jamesadevine	0:e1a608bb55e8	5276	#define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos) /!< Bit mask of MAXLEN field. /
jamesadevine	0:e1a608bb55e8	5277
jamesadevine	0:e1a608bb55e8	5278	/* Register: RADIO_PREFIX0 */
jamesadevine	0:e1a608bb55e8	5279	/* Description: Prefixes bytes for logical addresses 0 to 3. */
jamesadevine	0:e1a608bb55e8	5280
jamesadevine	0:e1a608bb55e8	5281	/* Bits 31..24 : Address prefix 3. Decision point: START task. */
jamesadevine	0:e1a608bb55e8	5282	#define RADIO_PREFIX0_AP3_Pos (24UL) /!< Position of AP3 field. /
jamesadevine	0:e1a608bb55e8	5283	#define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos) /!< Bit mask of AP3 field. /
jamesadevine	0:e1a608bb55e8	5284
jamesadevine	0:e1a608bb55e8	5285	/* Bits 23..16 : Address prefix 2. Decision point: START task. */
jamesadevine	0:e1a608bb55e8	5286	#define RADIO_PREFIX0_AP2_Pos (16UL) /!< Position of AP2 field. /
jamesadevine	0:e1a608bb55e8	5287	#define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos) /!< Bit mask of AP2 field. /
jamesadevine	0:e1a608bb55e8	5288
jamesadevine	0:e1a608bb55e8	5289	/* Bits 15..8 : Address prefix 1. Decision point: START task. */
jamesadevine	0:e1a608bb55e8	5290	#define RADIO_PREFIX0_AP1_Pos (8UL) /!< Position of AP1 field. /
jamesadevine	0:e1a608bb55e8	5291	#define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos) /!< Bit mask of AP1 field. /
jamesadevine	0:e1a608bb55e8	5292
jamesadevine	0:e1a608bb55e8	5293	/* Bits 7..0 : Address prefix 0. Decision point: START task. */
jamesadevine	0:e1a608bb55e8	5294	#define RADIO_PREFIX0_AP0_Pos (0UL) /!< Position of AP0 field. /
jamesadevine	0:e1a608bb55e8	5295	#define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos) /!< Bit mask of AP0 field. /
jamesadevine	0:e1a608bb55e8	5296
jamesadevine	0:e1a608bb55e8	5297	/* Register: RADIO_PREFIX1 */
jamesadevine	0:e1a608bb55e8	5298	/* Description: Prefixes bytes for logical addresses 4 to 7. */
jamesadevine	0:e1a608bb55e8	5299
jamesadevine	0:e1a608bb55e8	5300	/* Bits 31..24 : Address prefix 7. Decision point: START task. */
jamesadevine	0:e1a608bb55e8	5301	#define RADIO_PREFIX1_AP7_Pos (24UL) /!< Position of AP7 field. /
jamesadevine	0:e1a608bb55e8	5302	#define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos) /!< Bit mask of AP7 field. /
jamesadevine	0:e1a608bb55e8	5303
jamesadevine	0:e1a608bb55e8	5304	/* Bits 23..16 : Address prefix 6. Decision point: START task. */
jamesadevine	0:e1a608bb55e8	5305	#define RADIO_PREFIX1_AP6_Pos (16UL) /!< Position of AP6 field. /
jamesadevine	0:e1a608bb55e8	5306	#define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos) /!< Bit mask of AP6 field. /
jamesadevine	0:e1a608bb55e8	5307
jamesadevine	0:e1a608bb55e8	5308	/* Bits 15..8 : Address prefix 5. Decision point: START task. */
jamesadevine	0:e1a608bb55e8	5309	#define RADIO_PREFIX1_AP5_Pos (8UL) /!< Position of AP5 field. /
jamesadevine	0:e1a608bb55e8	5310	#define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos) /!< Bit mask of AP5 field. /
jamesadevine	0:e1a608bb55e8	5311
jamesadevine	0:e1a608bb55e8	5312	/* Bits 7..0 : Address prefix 4. Decision point: START task. */
jamesadevine	0:e1a608bb55e8	5313	#define RADIO_PREFIX1_AP4_Pos (0UL) /!< Position of AP4 field. /
jamesadevine	0:e1a608bb55e8	5314	#define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos) /!< Bit mask of AP4 field. /
jamesadevine	0:e1a608bb55e8	5315
jamesadevine	0:e1a608bb55e8	5316	/* Register: RADIO_TXADDRESS */
jamesadevine	0:e1a608bb55e8	5317	/* Description: Transmit address select. */
jamesadevine	0:e1a608bb55e8	5318
jamesadevine	0:e1a608bb55e8	5319	/* Bits 2..0 : Logical address to be used when transmitting a packet. Decision point: START task. */
jamesadevine	0:e1a608bb55e8	5320	#define RADIO_TXADDRESS_TXADDRESS_Pos (0UL) /!< Position of TXADDRESS field. /
jamesadevine	0:e1a608bb55e8	5321	#define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos) /!< Bit mask of TXADDRESS field. /
jamesadevine	0:e1a608bb55e8	5322
jamesadevine	0:e1a608bb55e8	5323	/* Register: RADIO_RXADDRESSES */
jamesadevine	0:e1a608bb55e8	5324	/* Description: Receive address select. */
jamesadevine	0:e1a608bb55e8	5325
jamesadevine	0:e1a608bb55e8	5326	/* Bit 7 : Enable reception on logical address 7. Decision point: START task. */
jamesadevine	0:e1a608bb55e8	5327	#define RADIO_RXADDRESSES_ADDR7_Pos (7UL) /!< Position of ADDR7 field. /
jamesadevine	0:e1a608bb55e8	5328	#define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos) /!< Bit mask of ADDR7 field. /
jamesadevine	0:e1a608bb55e8	5329	#define RADIO_RXADDRESSES_ADDR7_Disabled (0UL) /!< Reception disabled. /
jamesadevine	0:e1a608bb55e8	5330	#define RADIO_RXADDRESSES_ADDR7_Enabled (1UL) /!< Reception enabled. /
jamesadevine	0:e1a608bb55e8	5331
jamesadevine	0:e1a608bb55e8	5332	/* Bit 6 : Enable reception on logical address 6. Decision point: START task. */
jamesadevine	0:e1a608bb55e8	5333	#define RADIO_RXADDRESSES_ADDR6_Pos (6UL) /!< Position of ADDR6 field. /
jamesadevine	0:e1a608bb55e8	5334	#define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos) /!< Bit mask of ADDR6 field. /
jamesadevine	0:e1a608bb55e8	5335	#define RADIO_RXADDRESSES_ADDR6_Disabled (0UL) /!< Reception disabled. /
jamesadevine	0:e1a608bb55e8	5336	#define RADIO_RXADDRESSES_ADDR6_Enabled (1UL) /!< Reception enabled. /
jamesadevine	0:e1a608bb55e8	5337
jamesadevine	0:e1a608bb55e8	5338	/* Bit 5 : Enable reception on logical address 5. Decision point: START task. */
jamesadevine	0:e1a608bb55e8	5339	#define RADIO_RXADDRESSES_ADDR5_Pos (5UL) /!< Position of ADDR5 field. /
jamesadevine	0:e1a608bb55e8	5340	#define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos) /!< Bit mask of ADDR5 field. /
jamesadevine	0:e1a608bb55e8	5341	#define RADIO_RXADDRESSES_ADDR5_Disabled (0UL) /!< Reception disabled. /
jamesadevine	0:e1a608bb55e8	5342	#define RADIO_RXADDRESSES_ADDR5_Enabled (1UL) /!< Reception enabled. /
jamesadevine	0:e1a608bb55e8	5343
jamesadevine	0:e1a608bb55e8	5344	/* Bit 4 : Enable reception on logical address 4. Decision point: START task. */
jamesadevine	0:e1a608bb55e8	5345	#define RADIO_RXADDRESSES_ADDR4_Pos (4UL) /!< Position of ADDR4 field. /
jamesadevine	0:e1a608bb55e8	5346	#define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos) /!< Bit mask of ADDR4 field. /
jamesadevine	0:e1a608bb55e8	5347	#define RADIO_RXADDRESSES_ADDR4_Disabled (0UL) /!< Reception disabled. /
jamesadevine	0:e1a608bb55e8	5348	#define RADIO_RXADDRESSES_ADDR4_Enabled (1UL) /!< Reception enabled. /
jamesadevine	0:e1a608bb55e8	5349
jamesadevine	0:e1a608bb55e8	5350	/* Bit 3 : Enable reception on logical address 3. Decision point: START task. */
jamesadevine	0:e1a608bb55e8	5351	#define RADIO_RXADDRESSES_ADDR3_Pos (3UL) /!< Position of ADDR3 field. /
jamesadevine	0:e1a608bb55e8	5352	#define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos) /!< Bit mask of ADDR3 field. /
jamesadevine	0:e1a608bb55e8	5353	#define RADIO_RXADDRESSES_ADDR3_Disabled (0UL) /!< Reception disabled. /
jamesadevine	0:e1a608bb55e8	5354	#define RADIO_RXADDRESSES_ADDR3_Enabled (1UL) /!< Reception enabled. /
jamesadevine	0:e1a608bb55e8	5355
jamesadevine	0:e1a608bb55e8	5356	/* Bit 2 : Enable reception on logical address 2. Decision point: START task. */
jamesadevine	0:e1a608bb55e8	5357	#define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /!< Position of ADDR2 field. /
jamesadevine	0:e1a608bb55e8	5358	#define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos) /!< Bit mask of ADDR2 field. /
jamesadevine	0:e1a608bb55e8	5359	#define RADIO_RXADDRESSES_ADDR2_Disabled (0UL) /!< Reception disabled. /
jamesadevine	0:e1a608bb55e8	5360	#define RADIO_RXADDRESSES_ADDR2_Enabled (1UL) /!< Reception enabled. /
jamesadevine	0:e1a608bb55e8	5361
jamesadevine	0:e1a608bb55e8	5362	/* Bit 1 : Enable reception on logical address 1. Decision point: START task. */
jamesadevine	0:e1a608bb55e8	5363	#define RADIO_RXADDRESSES_ADDR1_Pos (1UL) /!< Position of ADDR1 field. /
jamesadevine	0:e1a608bb55e8	5364	#define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos) /!< Bit mask of ADDR1 field. /
jamesadevine	0:e1a608bb55e8	5365	#define RADIO_RXADDRESSES_ADDR1_Disabled (0UL) /!< Reception disabled. /
jamesadevine	0:e1a608bb55e8	5366	#define RADIO_RXADDRESSES_ADDR1_Enabled (1UL) /!< Reception enabled. /
jamesadevine	0:e1a608bb55e8	5367
jamesadevine	0:e1a608bb55e8	5368	/* Bit 0 : Enable reception on logical address 0. Decision point: START task. */
jamesadevine	0:e1a608bb55e8	5369	#define RADIO_RXADDRESSES_ADDR0_Pos (0UL) /!< Position of ADDR0 field. /
jamesadevine	0:e1a608bb55e8	5370	#define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos) /!< Bit mask of ADDR0 field. /
jamesadevine	0:e1a608bb55e8	5371	#define RADIO_RXADDRESSES_ADDR0_Disabled (0UL) /!< Reception disabled. /
jamesadevine	0:e1a608bb55e8	5372	#define RADIO_RXADDRESSES_ADDR0_Enabled (1UL) /!< Reception enabled. /
jamesadevine	0:e1a608bb55e8	5373
jamesadevine	0:e1a608bb55e8	5374	/* Register: RADIO_CRCCNF */
jamesadevine	0:e1a608bb55e8	5375	/* Description: CRC configuration. */
jamesadevine	0:e1a608bb55e8	5376
jamesadevine	0:e1a608bb55e8	5377	/* Bit 8 : Leave packet address field out of the CRC calculation. Decision point: START task. */
jamesadevine	0:e1a608bb55e8	5378	#define RADIO_CRCCNF_SKIPADDR_Pos (8UL) /!< Position of SKIPADDR field. /
jamesadevine	0:e1a608bb55e8	5379	#define RADIO_CRCCNF_SKIPADDR_Msk (0x1UL << RADIO_CRCCNF_SKIPADDR_Pos) /!< Bit mask of SKIPADDR field. /
jamesadevine	0:e1a608bb55e8	5380	#define RADIO_CRCCNF_SKIPADDR_Include (0UL) /!< Include packet address in CRC calculation. /
jamesadevine	0:e1a608bb55e8	5381	#define RADIO_CRCCNF_SKIPADDR_Skip (1UL) /!< Packet address is skipped in CRC calculation. The CRC calculation will start at the first byte after the address. /
jamesadevine	0:e1a608bb55e8	5382
jamesadevine	0:e1a608bb55e8	5383	/* Bits 1..0 : CRC length. Decision point: START task. */
jamesadevine	0:e1a608bb55e8	5384	#define RADIO_CRCCNF_LEN_Pos (0UL) /!< Position of LEN field. /
jamesadevine	0:e1a608bb55e8	5385	#define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /!< Bit mask of LEN field. /
jamesadevine	0:e1a608bb55e8	5386	#define RADIO_CRCCNF_LEN_Disabled (0UL) /!< CRC calculation disabled. /
jamesadevine	0:e1a608bb55e8	5387	#define RADIO_CRCCNF_LEN_One (1UL) /!< One byte long CRC. /
jamesadevine	0:e1a608bb55e8	5388	#define RADIO_CRCCNF_LEN_Two (2UL) /!< Two bytes long CRC. /
jamesadevine	0:e1a608bb55e8	5389	#define RADIO_CRCCNF_LEN_Three (3UL) /!< Three bytes long CRC. /
jamesadevine	0:e1a608bb55e8	5390
jamesadevine	0:e1a608bb55e8	5391	/* Register: RADIO_CRCPOLY */
jamesadevine	0:e1a608bb55e8	5392	/* Description: CRC polynomial. */
jamesadevine	0:e1a608bb55e8	5393
jamesadevine	0:e1a608bb55e8	5394	/* Bits 23..0 : CRC polynomial. Decision point: START task. */
jamesadevine	0:e1a608bb55e8	5395	#define RADIO_CRCPOLY_CRCPOLY_Pos (0UL) /!< Position of CRCPOLY field. /
jamesadevine	0:e1a608bb55e8	5396	#define RADIO_CRCPOLY_CRCPOLY_Msk (0xFFFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /!< Bit mask of CRCPOLY field. /
jamesadevine	0:e1a608bb55e8	5397
jamesadevine	0:e1a608bb55e8	5398	/* Register: RADIO_CRCINIT */
jamesadevine	0:e1a608bb55e8	5399	/* Description: CRC initial value. */
jamesadevine	0:e1a608bb55e8	5400
jamesadevine	0:e1a608bb55e8	5401	/* Bits 23..0 : Initial value for CRC calculation. Decision point: START task. */
jamesadevine	0:e1a608bb55e8	5402	#define RADIO_CRCINIT_CRCINIT_Pos (0UL) /!< Position of CRCINIT field. /
jamesadevine	0:e1a608bb55e8	5403	#define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /!< Bit mask of CRCINIT field. /
jamesadevine	0:e1a608bb55e8	5404
jamesadevine	0:e1a608bb55e8	5405	/* Register: RADIO_TEST */
jamesadevine	0:e1a608bb55e8	5406	/* Description: Test features enable register. */
jamesadevine	0:e1a608bb55e8	5407
jamesadevine	0:e1a608bb55e8	5408	/* Bit 1 : PLL lock. Decision point: TXEN or RXEN task. */
jamesadevine	0:e1a608bb55e8	5409	#define RADIO_TEST_PLLLOCK_Pos (1UL) /!< Position of PLLLOCK field. /
jamesadevine	0:e1a608bb55e8	5410	#define RADIO_TEST_PLLLOCK_Msk (0x1UL << RADIO_TEST_PLLLOCK_Pos) /!< Bit mask of PLLLOCK field. /
jamesadevine	0:e1a608bb55e8	5411	#define RADIO_TEST_PLLLOCK_Disabled (0UL) /!< PLL lock disabled. /
jamesadevine	0:e1a608bb55e8	5412	#define RADIO_TEST_PLLLOCK_Enabled (1UL) /!< PLL lock enabled. /
jamesadevine	0:e1a608bb55e8	5413
jamesadevine	0:e1a608bb55e8	5414	/* Bit 0 : Constant carrier. Decision point: TXEN task. */
jamesadevine	0:e1a608bb55e8	5415	#define RADIO_TEST_CONSTCARRIER_Pos (0UL) /!< Position of CONSTCARRIER field. /
jamesadevine	0:e1a608bb55e8	5416	#define RADIO_TEST_CONSTCARRIER_Msk (0x1UL << RADIO_TEST_CONSTCARRIER_Pos) /!< Bit mask of CONSTCARRIER field. /
jamesadevine	0:e1a608bb55e8	5417	#define RADIO_TEST_CONSTCARRIER_Disabled (0UL) /!< Constant carrier disabled. /
jamesadevine	0:e1a608bb55e8	5418	#define RADIO_TEST_CONSTCARRIER_Enabled (1UL) /!< Constant carrier enabled. /
jamesadevine	0:e1a608bb55e8	5419
jamesadevine	0:e1a608bb55e8	5420	/* Register: RADIO_TIFS */
jamesadevine	0:e1a608bb55e8	5421	/* Description: Inter Frame Spacing in microseconds. */
jamesadevine	0:e1a608bb55e8	5422
jamesadevine	0:e1a608bb55e8	5423	/* Bits 7..0 : Inter frame spacing in microseconds. Decision point: START rask */
jamesadevine	0:e1a608bb55e8	5424	#define RADIO_TIFS_TIFS_Pos (0UL) /!< Position of TIFS field. /
jamesadevine	0:e1a608bb55e8	5425	#define RADIO_TIFS_TIFS_Msk (0xFFUL << RADIO_TIFS_TIFS_Pos) /!< Bit mask of TIFS field. /
jamesadevine	0:e1a608bb55e8	5426
jamesadevine	0:e1a608bb55e8	5427	/* Register: RADIO_RSSISAMPLE */
jamesadevine	0:e1a608bb55e8	5428	/* Description: RSSI sample. */
jamesadevine	0:e1a608bb55e8	5429
jamesadevine	0:e1a608bb55e8	5430	/* Bits 6..0 : RSSI sample result. The result is read as a positive value so that ReceivedSignalStrength = -RSSISAMPLE dBm */
jamesadevine	0:e1a608bb55e8	5431	#define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /!< Position of RSSISAMPLE field. /
jamesadevine	0:e1a608bb55e8	5432	#define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /!< Bit mask of RSSISAMPLE field. /
jamesadevine	0:e1a608bb55e8	5433
jamesadevine	0:e1a608bb55e8	5434	/* Register: RADIO_STATE */
jamesadevine	0:e1a608bb55e8	5435	/* Description: Current radio state. */
jamesadevine	0:e1a608bb55e8	5436
jamesadevine	0:e1a608bb55e8	5437	/* Bits 3..0 : Current radio state. */
jamesadevine	0:e1a608bb55e8	5438	#define RADIO_STATE_STATE_Pos (0UL) /!< Position of STATE field. /
jamesadevine	0:e1a608bb55e8	5439	#define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos) /!< Bit mask of STATE field. /
jamesadevine	0:e1a608bb55e8	5440	#define RADIO_STATE_STATE_Disabled (0x00UL) /!< Radio is in the Disabled state. /
jamesadevine	0:e1a608bb55e8	5441	#define RADIO_STATE_STATE_RxRu (0x01UL) /!< Radio is in the Rx Ramp Up state. /
jamesadevine	0:e1a608bb55e8	5442	#define RADIO_STATE_STATE_RxIdle (0x02UL) /!< Radio is in the Rx Idle state. /
jamesadevine	0:e1a608bb55e8	5443	#define RADIO_STATE_STATE_Rx (0x03UL) /!< Radio is in the Rx state. /
jamesadevine	0:e1a608bb55e8	5444	#define RADIO_STATE_STATE_RxDisable (0x04UL) /!< Radio is in the Rx Disable state. /
jamesadevine	0:e1a608bb55e8	5445	#define RADIO_STATE_STATE_TxRu (0x09UL) /!< Radio is in the Tx Ramp Up state. /
jamesadevine	0:e1a608bb55e8	5446	#define RADIO_STATE_STATE_TxIdle (0x0AUL) /!< Radio is in the Tx Idle state. /
jamesadevine	0:e1a608bb55e8	5447	#define RADIO_STATE_STATE_Tx (0x0BUL) /!< Radio is in the Tx state. /
jamesadevine	0:e1a608bb55e8	5448	#define RADIO_STATE_STATE_TxDisable (0x0CUL) /!< Radio is in the Tx Disable state. /
jamesadevine	0:e1a608bb55e8	5449
jamesadevine	0:e1a608bb55e8	5450	/* Register: RADIO_DATAWHITEIV */
jamesadevine	0:e1a608bb55e8	5451	/* Description: Data whitening initial value. */
jamesadevine	0:e1a608bb55e8	5452
jamesadevine	0:e1a608bb55e8	5453	/* Bits 6..0 : Data whitening initial value. Bit 0 corresponds to Position 0 of the LSFR, Bit 1 to position 5... Decision point: TXEN or RXEN task. */
jamesadevine	0:e1a608bb55e8	5454	#define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL) /!< Position of DATAWHITEIV field. /
jamesadevine	0:e1a608bb55e8	5455	#define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x7FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /!< Bit mask of DATAWHITEIV field. /
jamesadevine	0:e1a608bb55e8	5456
jamesadevine	0:e1a608bb55e8	5457	/* Register: RADIO_DAP */
jamesadevine	0:e1a608bb55e8	5458	/* Description: Device address prefix. */
jamesadevine	0:e1a608bb55e8	5459
jamesadevine	0:e1a608bb55e8	5460	/* Bits 15..0 : Device address prefix. */
jamesadevine	0:e1a608bb55e8	5461	#define RADIO_DAP_DAP_Pos (0UL) /!< Position of DAP field. /
jamesadevine	0:e1a608bb55e8	5462	#define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /!< Bit mask of DAP field. /
jamesadevine	0:e1a608bb55e8	5463
jamesadevine	0:e1a608bb55e8	5464	/* Register: RADIO_DACNF */
jamesadevine	0:e1a608bb55e8	5465	/* Description: Device address match configuration. */
jamesadevine	0:e1a608bb55e8	5466
jamesadevine	0:e1a608bb55e8	5467	/* Bit 15 : TxAdd for device address 7. */
jamesadevine	0:e1a608bb55e8	5468	#define RADIO_DACNF_TXADD7_Pos (15UL) /!< Position of TXADD7 field. /
jamesadevine	0:e1a608bb55e8	5469	#define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos) /!< Bit mask of TXADD7 field. /
jamesadevine	0:e1a608bb55e8	5470
jamesadevine	0:e1a608bb55e8	5471	/* Bit 14 : TxAdd for device address 6. */
jamesadevine	0:e1a608bb55e8	5472	#define RADIO_DACNF_TXADD6_Pos (14UL) /!< Position of TXADD6 field. /
jamesadevine	0:e1a608bb55e8	5473	#define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos) /!< Bit mask of TXADD6 field. /
jamesadevine	0:e1a608bb55e8	5474
jamesadevine	0:e1a608bb55e8	5475	/* Bit 13 : TxAdd for device address 5. */
jamesadevine	0:e1a608bb55e8	5476	#define RADIO_DACNF_TXADD5_Pos (13UL) /!< Position of TXADD5 field. /
jamesadevine	0:e1a608bb55e8	5477	#define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos) /!< Bit mask of TXADD5 field. /
jamesadevine	0:e1a608bb55e8	5478
jamesadevine	0:e1a608bb55e8	5479	/* Bit 12 : TxAdd for device address 4. */
jamesadevine	0:e1a608bb55e8	5480	#define RADIO_DACNF_TXADD4_Pos (12UL) /!< Position of TXADD4 field. /
jamesadevine	0:e1a608bb55e8	5481	#define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos) /!< Bit mask of TXADD4 field. /
jamesadevine	0:e1a608bb55e8	5482
jamesadevine	0:e1a608bb55e8	5483	/* Bit 11 : TxAdd for device address 3. */
jamesadevine	0:e1a608bb55e8	5484	#define RADIO_DACNF_TXADD3_Pos (11UL) /!< Position of TXADD3 field. /
jamesadevine	0:e1a608bb55e8	5485	#define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos) /!< Bit mask of TXADD3 field. /
jamesadevine	0:e1a608bb55e8	5486
jamesadevine	0:e1a608bb55e8	5487	/* Bit 10 : TxAdd for device address 2. */
jamesadevine	0:e1a608bb55e8	5488	#define RADIO_DACNF_TXADD2_Pos (10UL) /!< Position of TXADD2 field. /
jamesadevine	0:e1a608bb55e8	5489	#define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos) /!< Bit mask of TXADD2 field. /
jamesadevine	0:e1a608bb55e8	5490
jamesadevine	0:e1a608bb55e8	5491	/* Bit 9 : TxAdd for device address 1. */
jamesadevine	0:e1a608bb55e8	5492	#define RADIO_DACNF_TXADD1_Pos (9UL) /!< Position of TXADD1 field. /
jamesadevine	0:e1a608bb55e8	5493	#define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos) /!< Bit mask of TXADD1 field. /
jamesadevine	0:e1a608bb55e8	5494
jamesadevine	0:e1a608bb55e8	5495	/* Bit 8 : TxAdd for device address 0. */
jamesadevine	0:e1a608bb55e8	5496	#define RADIO_DACNF_TXADD0_Pos (8UL) /!< Position of TXADD0 field. /
jamesadevine	0:e1a608bb55e8	5497	#define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos) /!< Bit mask of TXADD0 field. /
jamesadevine	0:e1a608bb55e8	5498
jamesadevine	0:e1a608bb55e8	5499	/* Bit 7 : Enable or disable device address matching using device address 7. */
jamesadevine	0:e1a608bb55e8	5500	#define RADIO_DACNF_ENA7_Pos (7UL) /!< Position of ENA7 field. /
jamesadevine	0:e1a608bb55e8	5501	#define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos) /!< Bit mask of ENA7 field. /
jamesadevine	0:e1a608bb55e8	5502	#define RADIO_DACNF_ENA7_Disabled (0UL) /!< Disabled. /
jamesadevine	0:e1a608bb55e8	5503	#define RADIO_DACNF_ENA7_Enabled (1UL) /!< Enabled. /
jamesadevine	0:e1a608bb55e8	5504
jamesadevine	0:e1a608bb55e8	5505	/* Bit 6 : Enable or disable device address matching using device address 6. */
jamesadevine	0:e1a608bb55e8	5506	#define RADIO_DACNF_ENA6_Pos (6UL) /!< Position of ENA6 field. /
jamesadevine	0:e1a608bb55e8	5507	#define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos) /!< Bit mask of ENA6 field. /
jamesadevine	0:e1a608bb55e8	5508	#define RADIO_DACNF_ENA6_Disabled (0UL) /!< Disabled. /
jamesadevine	0:e1a608bb55e8	5509	#define RADIO_DACNF_ENA6_Enabled (1UL) /!< Enabled. /
jamesadevine	0:e1a608bb55e8	5510
jamesadevine	0:e1a608bb55e8	5511	/* Bit 5 : Enable or disable device address matching using device address 5. */
jamesadevine	0:e1a608bb55e8	5512	#define RADIO_DACNF_ENA5_Pos (5UL) /!< Position of ENA5 field. /
jamesadevine	0:e1a608bb55e8	5513	#define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos) /!< Bit mask of ENA5 field. /
jamesadevine	0:e1a608bb55e8	5514	#define RADIO_DACNF_ENA5_Disabled (0UL) /!< Disabled. /
jamesadevine	0:e1a608bb55e8	5515	#define RADIO_DACNF_ENA5_Enabled (1UL) /!< Enabled. /
jamesadevine	0:e1a608bb55e8	5516
jamesadevine	0:e1a608bb55e8	5517	/* Bit 4 : Enable or disable device address matching using device address 4. */
jamesadevine	0:e1a608bb55e8	5518	#define RADIO_DACNF_ENA4_Pos (4UL) /!< Position of ENA4 field. /
jamesadevine	0:e1a608bb55e8	5519	#define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos) /!< Bit mask of ENA4 field. /
jamesadevine	0:e1a608bb55e8	5520	#define RADIO_DACNF_ENA4_Disabled (0UL) /!< Disabled. /
jamesadevine	0:e1a608bb55e8	5521	#define RADIO_DACNF_ENA4_Enabled (1UL) /!< Enabled. /
jamesadevine	0:e1a608bb55e8	5522
jamesadevine	0:e1a608bb55e8	5523	/* Bit 3 : Enable or disable device address matching using device address 3. */
jamesadevine	0:e1a608bb55e8	5524	#define RADIO_DACNF_ENA3_Pos (3UL) /!< Position of ENA3 field. /
jamesadevine	0:e1a608bb55e8	5525	#define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos) /!< Bit mask of ENA3 field. /
jamesadevine	0:e1a608bb55e8	5526	#define RADIO_DACNF_ENA3_Disabled (0UL) /!< Disabled. /
jamesadevine	0:e1a608bb55e8	5527	#define RADIO_DACNF_ENA3_Enabled (1UL) /!< Enabled. /
jamesadevine	0:e1a608bb55e8	5528
jamesadevine	0:e1a608bb55e8	5529	/* Bit 2 : Enable or disable device address matching using device address 2. */
jamesadevine	0:e1a608bb55e8	5530	#define RADIO_DACNF_ENA2_Pos (2UL) /!< Position of ENA2 field. /
jamesadevine	0:e1a608bb55e8	5531	#define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos) /!< Bit mask of ENA2 field. /
jamesadevine	0:e1a608bb55e8	5532	#define RADIO_DACNF_ENA2_Disabled (0UL) /!< Disabled. /
jamesadevine	0:e1a608bb55e8	5533	#define RADIO_DACNF_ENA2_Enabled (1UL) /!< Enabled. /
jamesadevine	0:e1a608bb55e8	5534
jamesadevine	0:e1a608bb55e8	5535	/* Bit 1 : Enable or disable device address matching using device address 1. */
jamesadevine	0:e1a608bb55e8	5536	#define RADIO_DACNF_ENA1_Pos (1UL) /!< Position of ENA1 field. /
jamesadevine	0:e1a608bb55e8	5537	#define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos) /!< Bit mask of ENA1 field. /
jamesadevine	0:e1a608bb55e8	5538	#define RADIO_DACNF_ENA1_Disabled (0UL) /!< Disabled. /
jamesadevine	0:e1a608bb55e8	5539	#define RADIO_DACNF_ENA1_Enabled (1UL) /!< Enabled. /
jamesadevine	0:e1a608bb55e8	5540
jamesadevine	0:e1a608bb55e8	5541	/* Bit 0 : Enable or disable device address matching using device address 0. */
jamesadevine	0:e1a608bb55e8	5542	#define RADIO_DACNF_ENA0_Pos (0UL) /!< Position of ENA0 field. /
jamesadevine	0:e1a608bb55e8	5543	#define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos) /!< Bit mask of ENA0 field. /
jamesadevine	0:e1a608bb55e8	5544	#define RADIO_DACNF_ENA0_Disabled (0UL) /!< Disabled. /
jamesadevine	0:e1a608bb55e8	5545	#define RADIO_DACNF_ENA0_Enabled (1UL) /!< Enabled. /
jamesadevine	0:e1a608bb55e8	5546
jamesadevine	0:e1a608bb55e8	5547	/* Register: RADIO_OVERRIDE0 */
jamesadevine	0:e1a608bb55e8	5548	/* Description: Trim value override register 0. */
jamesadevine	0:e1a608bb55e8	5549
jamesadevine	0:e1a608bb55e8	5550	/* Bits 31..0 : Trim value override 0. */
jamesadevine	0:e1a608bb55e8	5551	#define RADIO_OVERRIDE0_OVERRIDE0_Pos (0UL) /!< Position of OVERRIDE0 field. /
jamesadevine	0:e1a608bb55e8	5552	#define RADIO_OVERRIDE0_OVERRIDE0_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE0_OVERRIDE0_Pos) /!< Bit mask of OVERRIDE0 field. /
jamesadevine	0:e1a608bb55e8	5553
jamesadevine	0:e1a608bb55e8	5554	/* Register: RADIO_OVERRIDE1 */
jamesadevine	0:e1a608bb55e8	5555	/* Description: Trim value override register 1. */
jamesadevine	0:e1a608bb55e8	5556
jamesadevine	0:e1a608bb55e8	5557	/* Bits 31..0 : Trim value override 1. */
jamesadevine	0:e1a608bb55e8	5558	#define RADIO_OVERRIDE1_OVERRIDE1_Pos (0UL) /!< Position of OVERRIDE1 field. /
jamesadevine	0:e1a608bb55e8	5559	#define RADIO_OVERRIDE1_OVERRIDE1_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE1_OVERRIDE1_Pos) /!< Bit mask of OVERRIDE1 field. /
jamesadevine	0:e1a608bb55e8	5560
jamesadevine	0:e1a608bb55e8	5561	/* Register: RADIO_OVERRIDE2 */
jamesadevine	0:e1a608bb55e8	5562	/* Description: Trim value override register 2. */
jamesadevine	0:e1a608bb55e8	5563
jamesadevine	0:e1a608bb55e8	5564	/* Bits 31..0 : Trim value override 2. */
jamesadevine	0:e1a608bb55e8	5565	#define RADIO_OVERRIDE2_OVERRIDE2_Pos (0UL) /!< Position of OVERRIDE2 field. /
jamesadevine	0:e1a608bb55e8	5566	#define RADIO_OVERRIDE2_OVERRIDE2_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE2_OVERRIDE2_Pos) /!< Bit mask of OVERRIDE2 field. /
jamesadevine	0:e1a608bb55e8	5567
jamesadevine	0:e1a608bb55e8	5568	/* Register: RADIO_OVERRIDE3 */
jamesadevine	0:e1a608bb55e8	5569	/* Description: Trim value override register 3. */
jamesadevine	0:e1a608bb55e8	5570
jamesadevine	0:e1a608bb55e8	5571	/* Bits 31..0 : Trim value override 3. */
jamesadevine	0:e1a608bb55e8	5572	#define RADIO_OVERRIDE3_OVERRIDE3_Pos (0UL) /!< Position of OVERRIDE3 field. /
jamesadevine	0:e1a608bb55e8	5573	#define RADIO_OVERRIDE3_OVERRIDE3_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE3_OVERRIDE3_Pos) /!< Bit mask of OVERRIDE3 field. /
jamesadevine	0:e1a608bb55e8	5574
jamesadevine	0:e1a608bb55e8	5575	/* Register: RADIO_OVERRIDE4 */
jamesadevine	0:e1a608bb55e8	5576	/* Description: Trim value override register 4. */
jamesadevine	0:e1a608bb55e8	5577
jamesadevine	0:e1a608bb55e8	5578	/* Bit 31 : Enable or disable override of default trim values. */
jamesadevine	0:e1a608bb55e8	5579	#define RADIO_OVERRIDE4_ENABLE_Pos (31UL) /!< Position of ENABLE field. /
jamesadevine	0:e1a608bb55e8	5580	#define RADIO_OVERRIDE4_ENABLE_Msk (0x1UL << RADIO_OVERRIDE4_ENABLE_Pos) /!< Bit mask of ENABLE field. /
jamesadevine	0:e1a608bb55e8	5581	#define RADIO_OVERRIDE4_ENABLE_Disabled (0UL) /!< Override trim values disabled. /
jamesadevine	0:e1a608bb55e8	5582	#define RADIO_OVERRIDE4_ENABLE_Enabled (1UL) /!< Override trim values enabled. /
jamesadevine	0:e1a608bb55e8	5583
jamesadevine	0:e1a608bb55e8	5584	/* Bits 27..0 : Trim value override 4. */
jamesadevine	0:e1a608bb55e8	5585	#define RADIO_OVERRIDE4_OVERRIDE4_Pos (0UL) /!< Position of OVERRIDE4 field. /
jamesadevine	0:e1a608bb55e8	5586	#define RADIO_OVERRIDE4_OVERRIDE4_Msk (0xFFFFFFFUL << RADIO_OVERRIDE4_OVERRIDE4_Pos) /!< Bit mask of OVERRIDE4 field. /
jamesadevine	0:e1a608bb55e8	5587
jamesadevine	0:e1a608bb55e8	5588	/* Register: RADIO_POWER */
jamesadevine	0:e1a608bb55e8	5589	/* Description: Peripheral power control. */
jamesadevine	0:e1a608bb55e8	5590
jamesadevine	0:e1a608bb55e8	5591	/* Bit 0 : Peripheral power control. */
jamesadevine	0:e1a608bb55e8	5592	#define RADIO_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
jamesadevine	0:e1a608bb55e8	5593	#define RADIO_POWER_POWER_Msk (0x1UL << RADIO_POWER_POWER_Pos) /!< Bit mask of POWER field. /
jamesadevine	0:e1a608bb55e8	5594	#define RADIO_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
jamesadevine	0:e1a608bb55e8	5595	#define RADIO_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
jamesadevine	0:e1a608bb55e8	5596
jamesadevine	0:e1a608bb55e8	5597
jamesadevine	0:e1a608bb55e8	5598	/* Peripheral: RNG */
jamesadevine	0:e1a608bb55e8	5599	/* Description: Random Number Generator. */
jamesadevine	0:e1a608bb55e8	5600
jamesadevine	0:e1a608bb55e8	5601	/* Register: RNG_SHORTS */
jamesadevine	0:e1a608bb55e8	5602	/* Description: Shortcuts for the RNG. */
jamesadevine	0:e1a608bb55e8	5603
jamesadevine	0:e1a608bb55e8	5604	/* Bit 0 : Shortcut between VALRDY event and STOP task. */
jamesadevine	0:e1a608bb55e8	5605	#define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /!< Position of VALRDY_STOP field. /
jamesadevine	0:e1a608bb55e8	5606	#define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /!< Bit mask of VALRDY_STOP field. /
jamesadevine	0:e1a608bb55e8	5607	#define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /!< Shortcut disabled. /
jamesadevine	0:e1a608bb55e8	5608	#define RNG_SHORTS_VALRDY_STOP_Enabled (1UL) /!< Shortcut enabled. /
jamesadevine	0:e1a608bb55e8	5609
jamesadevine	0:e1a608bb55e8	5610	/* Register: RNG_INTENSET */
jamesadevine	0:e1a608bb55e8	5611	/* Description: Interrupt enable set register */
jamesadevine	0:e1a608bb55e8	5612
jamesadevine	0:e1a608bb55e8	5613	/* Bit 0 : Enable interrupt on VALRDY event. */
jamesadevine	0:e1a608bb55e8	5614	#define RNG_INTENSET_VALRDY_Pos (0UL) /!< Position of VALRDY field. /
jamesadevine	0:e1a608bb55e8	5615	#define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /!< Bit mask of VALRDY field. /
jamesadevine	0:e1a608bb55e8	5616	#define RNG_INTENSET_VALRDY_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	5617	#define RNG_INTENSET_VALRDY_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	5618	#define RNG_INTENSET_VALRDY_Set (1UL) /!< Enable interrupt on write. /
jamesadevine	0:e1a608bb55e8	5619
jamesadevine	0:e1a608bb55e8	5620	/* Register: RNG_INTENCLR */
jamesadevine	0:e1a608bb55e8	5621	/* Description: Interrupt enable clear register */
jamesadevine	0:e1a608bb55e8	5622
jamesadevine	0:e1a608bb55e8	5623	/* Bit 0 : Disable interrupt on VALRDY event. */
jamesadevine	0:e1a608bb55e8	5624	#define RNG_INTENCLR_VALRDY_Pos (0UL) /!< Position of VALRDY field. /
jamesadevine	0:e1a608bb55e8	5625	#define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /!< Bit mask of VALRDY field. /
jamesadevine	0:e1a608bb55e8	5626	#define RNG_INTENCLR_VALRDY_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	5627	#define RNG_INTENCLR_VALRDY_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	5628	#define RNG_INTENCLR_VALRDY_Clear (1UL) /!< Disable interrupt on write. /
jamesadevine	0:e1a608bb55e8	5629
jamesadevine	0:e1a608bb55e8	5630	/* Register: RNG_CONFIG */
jamesadevine	0:e1a608bb55e8	5631	/* Description: Configuration register. */
jamesadevine	0:e1a608bb55e8	5632
jamesadevine	0:e1a608bb55e8	5633	/* Bit 0 : Digital error correction enable. */
jamesadevine	0:e1a608bb55e8	5634	#define RNG_CONFIG_DERCEN_Pos (0UL) /!< Position of DERCEN field. /
jamesadevine	0:e1a608bb55e8	5635	#define RNG_CONFIG_DERCEN_Msk (0x1UL << RNG_CONFIG_DERCEN_Pos) /!< Bit mask of DERCEN field. /
jamesadevine	0:e1a608bb55e8	5636	#define RNG_CONFIG_DERCEN_Disabled (0UL) /!< Digital error correction disabled. /
jamesadevine	0:e1a608bb55e8	5637	#define RNG_CONFIG_DERCEN_Enabled (1UL) /!< Digital error correction enabled. /
jamesadevine	0:e1a608bb55e8	5638
jamesadevine	0:e1a608bb55e8	5639	/* Register: RNG_VALUE */
jamesadevine	0:e1a608bb55e8	5640	/* Description: RNG random number. */
jamesadevine	0:e1a608bb55e8	5641
jamesadevine	0:e1a608bb55e8	5642	/* Bits 7..0 : Generated random number. */
jamesadevine	0:e1a608bb55e8	5643	#define RNG_VALUE_VALUE_Pos (0UL) /!< Position of VALUE field. /
jamesadevine	0:e1a608bb55e8	5644	#define RNG_VALUE_VALUE_Msk (0xFFUL << RNG_VALUE_VALUE_Pos) /!< Bit mask of VALUE field. /
jamesadevine	0:e1a608bb55e8	5645
jamesadevine	0:e1a608bb55e8	5646	/* Register: RNG_POWER */
jamesadevine	0:e1a608bb55e8	5647	/* Description: Peripheral power control. */
jamesadevine	0:e1a608bb55e8	5648
jamesadevine	0:e1a608bb55e8	5649	/* Bit 0 : Peripheral power control. */
jamesadevine	0:e1a608bb55e8	5650	#define RNG_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
jamesadevine	0:e1a608bb55e8	5651	#define RNG_POWER_POWER_Msk (0x1UL << RNG_POWER_POWER_Pos) /!< Bit mask of POWER field. /
jamesadevine	0:e1a608bb55e8	5652	#define RNG_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
jamesadevine	0:e1a608bb55e8	5653	#define RNG_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
jamesadevine	0:e1a608bb55e8	5654
jamesadevine	0:e1a608bb55e8	5655
jamesadevine	0:e1a608bb55e8	5656	/* Peripheral: RTC */
jamesadevine	0:e1a608bb55e8	5657	/* Description: Real time counter 0. */
jamesadevine	0:e1a608bb55e8	5658
jamesadevine	0:e1a608bb55e8	5659	/* Register: RTC_INTENSET */
jamesadevine	0:e1a608bb55e8	5660	/* Description: Interrupt enable set register. */
jamesadevine	0:e1a608bb55e8	5661
jamesadevine	0:e1a608bb55e8	5662	/* Bit 19 : Enable interrupt on COMPARE[3] event. */
jamesadevine	0:e1a608bb55e8	5663	#define RTC_INTENSET_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
jamesadevine	0:e1a608bb55e8	5664	#define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
jamesadevine	0:e1a608bb55e8	5665	#define RTC_INTENSET_COMPARE3_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	5666	#define RTC_INTENSET_COMPARE3_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	5667	#define RTC_INTENSET_COMPARE3_Set (1UL) /!< Enable interrupt on write. /
jamesadevine	0:e1a608bb55e8	5668
jamesadevine	0:e1a608bb55e8	5669	/* Bit 18 : Enable interrupt on COMPARE[2] event. */
jamesadevine	0:e1a608bb55e8	5670	#define RTC_INTENSET_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
jamesadevine	0:e1a608bb55e8	5671	#define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
jamesadevine	0:e1a608bb55e8	5672	#define RTC_INTENSET_COMPARE2_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	5673	#define RTC_INTENSET_COMPARE2_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	5674	#define RTC_INTENSET_COMPARE2_Set (1UL) /!< Enable interrupt on write. /
jamesadevine	0:e1a608bb55e8	5675
jamesadevine	0:e1a608bb55e8	5676	/* Bit 17 : Enable interrupt on COMPARE[1] event. */
jamesadevine	0:e1a608bb55e8	5677	#define RTC_INTENSET_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
jamesadevine	0:e1a608bb55e8	5678	#define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
jamesadevine	0:e1a608bb55e8	5679	#define RTC_INTENSET_COMPARE1_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	5680	#define RTC_INTENSET_COMPARE1_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	5681	#define RTC_INTENSET_COMPARE1_Set (1UL) /!< Enable interrupt on write. /
jamesadevine	0:e1a608bb55e8	5682
jamesadevine	0:e1a608bb55e8	5683	/* Bit 16 : Enable interrupt on COMPARE[0] event. */
jamesadevine	0:e1a608bb55e8	5684	#define RTC_INTENSET_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
jamesadevine	0:e1a608bb55e8	5685	#define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
jamesadevine	0:e1a608bb55e8	5686	#define RTC_INTENSET_COMPARE0_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	5687	#define RTC_INTENSET_COMPARE0_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	5688	#define RTC_INTENSET_COMPARE0_Set (1UL) /!< Enable interrupt on write. /
jamesadevine	0:e1a608bb55e8	5689
jamesadevine	0:e1a608bb55e8	5690	/* Bit 1 : Enable interrupt on OVRFLW event. */
jamesadevine	0:e1a608bb55e8	5691	#define RTC_INTENSET_OVRFLW_Pos (1UL) /!< Position of OVRFLW field. /
jamesadevine	0:e1a608bb55e8	5692	#define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /!< Bit mask of OVRFLW field. /
jamesadevine	0:e1a608bb55e8	5693	#define RTC_INTENSET_OVRFLW_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	5694	#define RTC_INTENSET_OVRFLW_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	5695	#define RTC_INTENSET_OVRFLW_Set (1UL) /!< Enable interrupt on write. /
jamesadevine	0:e1a608bb55e8	5696
jamesadevine	0:e1a608bb55e8	5697	/* Bit 0 : Enable interrupt on TICK event. */
jamesadevine	0:e1a608bb55e8	5698	#define RTC_INTENSET_TICK_Pos (0UL) /!< Position of TICK field. /
jamesadevine	0:e1a608bb55e8	5699	#define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /!< Bit mask of TICK field. /
jamesadevine	0:e1a608bb55e8	5700	#define RTC_INTENSET_TICK_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	5701	#define RTC_INTENSET_TICK_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	5702	#define RTC_INTENSET_TICK_Set (1UL) /!< Enable interrupt on write. /
jamesadevine	0:e1a608bb55e8	5703
jamesadevine	0:e1a608bb55e8	5704	/* Register: RTC_INTENCLR */
jamesadevine	0:e1a608bb55e8	5705	/* Description: Interrupt enable clear register. */
jamesadevine	0:e1a608bb55e8	5706
jamesadevine	0:e1a608bb55e8	5707	/* Bit 19 : Disable interrupt on COMPARE[3] event. */
jamesadevine	0:e1a608bb55e8	5708	#define RTC_INTENCLR_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
jamesadevine	0:e1a608bb55e8	5709	#define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
jamesadevine	0:e1a608bb55e8	5710	#define RTC_INTENCLR_COMPARE3_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	5711	#define RTC_INTENCLR_COMPARE3_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	5712	#define RTC_INTENCLR_COMPARE3_Clear (1UL) /!< Disable interrupt on write. /
jamesadevine	0:e1a608bb55e8	5713
jamesadevine	0:e1a608bb55e8	5714	/* Bit 18 : Disable interrupt on COMPARE[2] event. */
jamesadevine	0:e1a608bb55e8	5715	#define RTC_INTENCLR_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
jamesadevine	0:e1a608bb55e8	5716	#define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
jamesadevine	0:e1a608bb55e8	5717	#define RTC_INTENCLR_COMPARE2_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	5718	#define RTC_INTENCLR_COMPARE2_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	5719	#define RTC_INTENCLR_COMPARE2_Clear (1UL) /!< Disable interrupt on write. /
jamesadevine	0:e1a608bb55e8	5720
jamesadevine	0:e1a608bb55e8	5721	/* Bit 17 : Disable interrupt on COMPARE[1] event. */
jamesadevine	0:e1a608bb55e8	5722	#define RTC_INTENCLR_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
jamesadevine	0:e1a608bb55e8	5723	#define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
jamesadevine	0:e1a608bb55e8	5724	#define RTC_INTENCLR_COMPARE1_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	5725	#define RTC_INTENCLR_COMPARE1_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	5726	#define RTC_INTENCLR_COMPARE1_Clear (1UL) /!< Disable interrupt on write. /
jamesadevine	0:e1a608bb55e8	5727
jamesadevine	0:e1a608bb55e8	5728	/* Bit 16 : Disable interrupt on COMPARE[0] event. */
jamesadevine	0:e1a608bb55e8	5729	#define RTC_INTENCLR_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
jamesadevine	0:e1a608bb55e8	5730	#define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
jamesadevine	0:e1a608bb55e8	5731	#define RTC_INTENCLR_COMPARE0_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	5732	#define RTC_INTENCLR_COMPARE0_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	5733	#define RTC_INTENCLR_COMPARE0_Clear (1UL) /!< Disable interrupt on write. /
jamesadevine	0:e1a608bb55e8	5734
jamesadevine	0:e1a608bb55e8	5735	/* Bit 1 : Disable interrupt on OVRFLW event. */
jamesadevine	0:e1a608bb55e8	5736	#define RTC_INTENCLR_OVRFLW_Pos (1UL) /!< Position of OVRFLW field. /
jamesadevine	0:e1a608bb55e8	5737	#define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /!< Bit mask of OVRFLW field. /
jamesadevine	0:e1a608bb55e8	5738	#define RTC_INTENCLR_OVRFLW_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	5739	#define RTC_INTENCLR_OVRFLW_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	5740	#define RTC_INTENCLR_OVRFLW_Clear (1UL) /!< Disable interrupt on write. /
jamesadevine	0:e1a608bb55e8	5741
jamesadevine	0:e1a608bb55e8	5742	/* Bit 0 : Disable interrupt on TICK event. */
jamesadevine	0:e1a608bb55e8	5743	#define RTC_INTENCLR_TICK_Pos (0UL) /!< Position of TICK field. /
jamesadevine	0:e1a608bb55e8	5744	#define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /!< Bit mask of TICK field. /
jamesadevine	0:e1a608bb55e8	5745	#define RTC_INTENCLR_TICK_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	5746	#define RTC_INTENCLR_TICK_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	5747	#define RTC_INTENCLR_TICK_Clear (1UL) /!< Disable interrupt on write. /
jamesadevine	0:e1a608bb55e8	5748
jamesadevine	0:e1a608bb55e8	5749	/* Register: RTC_EVTEN */
jamesadevine	0:e1a608bb55e8	5750	/* Description: Configures event enable routing to PPI for each RTC event. */
jamesadevine	0:e1a608bb55e8	5751
jamesadevine	0:e1a608bb55e8	5752	/* Bit 19 : COMPARE[3] event enable. */
jamesadevine	0:e1a608bb55e8	5753	#define RTC_EVTEN_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
jamesadevine	0:e1a608bb55e8	5754	#define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
jamesadevine	0:e1a608bb55e8	5755	#define RTC_EVTEN_COMPARE3_Disabled (0UL) /!< Event disabled. /
jamesadevine	0:e1a608bb55e8	5756	#define RTC_EVTEN_COMPARE3_Enabled (1UL) /!< Event enabled. /
jamesadevine	0:e1a608bb55e8	5757
jamesadevine	0:e1a608bb55e8	5758	/* Bit 18 : COMPARE[2] event enable. */
jamesadevine	0:e1a608bb55e8	5759	#define RTC_EVTEN_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
jamesadevine	0:e1a608bb55e8	5760	#define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
jamesadevine	0:e1a608bb55e8	5761	#define RTC_EVTEN_COMPARE2_Disabled (0UL) /!< Event disabled. /
jamesadevine	0:e1a608bb55e8	5762	#define RTC_EVTEN_COMPARE2_Enabled (1UL) /!< Event enabled. /
jamesadevine	0:e1a608bb55e8	5763
jamesadevine	0:e1a608bb55e8	5764	/* Bit 17 : COMPARE[1] event enable. */
jamesadevine	0:e1a608bb55e8	5765	#define RTC_EVTEN_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
jamesadevine	0:e1a608bb55e8	5766	#define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
jamesadevine	0:e1a608bb55e8	5767	#define RTC_EVTEN_COMPARE1_Disabled (0UL) /!< Event disabled. /
jamesadevine	0:e1a608bb55e8	5768	#define RTC_EVTEN_COMPARE1_Enabled (1UL) /!< Event enabled. /
jamesadevine	0:e1a608bb55e8	5769
jamesadevine	0:e1a608bb55e8	5770	/* Bit 16 : COMPARE[0] event enable. */
jamesadevine	0:e1a608bb55e8	5771	#define RTC_EVTEN_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
jamesadevine	0:e1a608bb55e8	5772	#define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
jamesadevine	0:e1a608bb55e8	5773	#define RTC_EVTEN_COMPARE0_Disabled (0UL) /!< Event disabled. /
jamesadevine	0:e1a608bb55e8	5774	#define RTC_EVTEN_COMPARE0_Enabled (1UL) /!< Event enabled. /
jamesadevine	0:e1a608bb55e8	5775
jamesadevine	0:e1a608bb55e8	5776	/* Bit 1 : OVRFLW event enable. */
jamesadevine	0:e1a608bb55e8	5777	#define RTC_EVTEN_OVRFLW_Pos (1UL) /!< Position of OVRFLW field. /
jamesadevine	0:e1a608bb55e8	5778	#define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /!< Bit mask of OVRFLW field. /
jamesadevine	0:e1a608bb55e8	5779	#define RTC_EVTEN_OVRFLW_Disabled (0UL) /!< Event disabled. /
jamesadevine	0:e1a608bb55e8	5780	#define RTC_EVTEN_OVRFLW_Enabled (1UL) /!< Event enabled. /
jamesadevine	0:e1a608bb55e8	5781
jamesadevine	0:e1a608bb55e8	5782	/* Bit 0 : TICK event enable. */
jamesadevine	0:e1a608bb55e8	5783	#define RTC_EVTEN_TICK_Pos (0UL) /!< Position of TICK field. /
jamesadevine	0:e1a608bb55e8	5784	#define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /!< Bit mask of TICK field. /
jamesadevine	0:e1a608bb55e8	5785	#define RTC_EVTEN_TICK_Disabled (0UL) /!< Event disabled. /
jamesadevine	0:e1a608bb55e8	5786	#define RTC_EVTEN_TICK_Enabled (1UL) /!< Event enabled. /
jamesadevine	0:e1a608bb55e8	5787
jamesadevine	0:e1a608bb55e8	5788	/* Register: RTC_EVTENSET */
jamesadevine	0:e1a608bb55e8	5789	/* Description: Enable events routing to PPI. The reading of this register gives the value of EVTEN. */
jamesadevine	0:e1a608bb55e8	5790
jamesadevine	0:e1a608bb55e8	5791	/* Bit 19 : Enable routing to PPI of COMPARE[3] event. */
jamesadevine	0:e1a608bb55e8	5792	#define RTC_EVTENSET_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
jamesadevine	0:e1a608bb55e8	5793	#define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
jamesadevine	0:e1a608bb55e8	5794	#define RTC_EVTENSET_COMPARE3_Disabled (0UL) /!< Event disabled. /
jamesadevine	0:e1a608bb55e8	5795	#define RTC_EVTENSET_COMPARE3_Enabled (1UL) /!< Event enabled. /
jamesadevine	0:e1a608bb55e8	5796	#define RTC_EVTENSET_COMPARE3_Set (1UL) /!< Enable event on write. /
jamesadevine	0:e1a608bb55e8	5797
jamesadevine	0:e1a608bb55e8	5798	/* Bit 18 : Enable routing to PPI of COMPARE[2] event. */
jamesadevine	0:e1a608bb55e8	5799	#define RTC_EVTENSET_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
jamesadevine	0:e1a608bb55e8	5800	#define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
jamesadevine	0:e1a608bb55e8	5801	#define RTC_EVTENSET_COMPARE2_Disabled (0UL) /!< Event disabled. /
jamesadevine	0:e1a608bb55e8	5802	#define RTC_EVTENSET_COMPARE2_Enabled (1UL) /!< Event enabled. /
jamesadevine	0:e1a608bb55e8	5803	#define RTC_EVTENSET_COMPARE2_Set (1UL) /!< Enable event on write. /
jamesadevine	0:e1a608bb55e8	5804
jamesadevine	0:e1a608bb55e8	5805	/* Bit 17 : Enable routing to PPI of COMPARE[1] event. */
jamesadevine	0:e1a608bb55e8	5806	#define RTC_EVTENSET_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
jamesadevine	0:e1a608bb55e8	5807	#define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
jamesadevine	0:e1a608bb55e8	5808	#define RTC_EVTENSET_COMPARE1_Disabled (0UL) /!< Event disabled. /
jamesadevine	0:e1a608bb55e8	5809	#define RTC_EVTENSET_COMPARE1_Enabled (1UL) /!< Event enabled. /
jamesadevine	0:e1a608bb55e8	5810	#define RTC_EVTENSET_COMPARE1_Set (1UL) /!< Enable event on write. /
jamesadevine	0:e1a608bb55e8	5811
jamesadevine	0:e1a608bb55e8	5812	/* Bit 16 : Enable routing to PPI of COMPARE[0] event. */
jamesadevine	0:e1a608bb55e8	5813	#define RTC_EVTENSET_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
jamesadevine	0:e1a608bb55e8	5814	#define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
jamesadevine	0:e1a608bb55e8	5815	#define RTC_EVTENSET_COMPARE0_Disabled (0UL) /!< Event disabled. /
jamesadevine	0:e1a608bb55e8	5816	#define RTC_EVTENSET_COMPARE0_Enabled (1UL) /!< Event enabled. /
jamesadevine	0:e1a608bb55e8	5817	#define RTC_EVTENSET_COMPARE0_Set (1UL) /!< Enable event on write. /
jamesadevine	0:e1a608bb55e8	5818
jamesadevine	0:e1a608bb55e8	5819	/* Bit 1 : Enable routing to PPI of OVRFLW event. */
jamesadevine	0:e1a608bb55e8	5820	#define RTC_EVTENSET_OVRFLW_Pos (1UL) /!< Position of OVRFLW field. /
jamesadevine	0:e1a608bb55e8	5821	#define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /!< Bit mask of OVRFLW field. /
jamesadevine	0:e1a608bb55e8	5822	#define RTC_EVTENSET_OVRFLW_Disabled (0UL) /!< Event disabled. /
jamesadevine	0:e1a608bb55e8	5823	#define RTC_EVTENSET_OVRFLW_Enabled (1UL) /!< Event enabled. /
jamesadevine	0:e1a608bb55e8	5824	#define RTC_EVTENSET_OVRFLW_Set (1UL) /!< Enable event on write. /
jamesadevine	0:e1a608bb55e8	5825
jamesadevine	0:e1a608bb55e8	5826	/* Bit 0 : Enable routing to PPI of TICK event. */
jamesadevine	0:e1a608bb55e8	5827	#define RTC_EVTENSET_TICK_Pos (0UL) /!< Position of TICK field. /
jamesadevine	0:e1a608bb55e8	5828	#define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /!< Bit mask of TICK field. /
jamesadevine	0:e1a608bb55e8	5829	#define RTC_EVTENSET_TICK_Disabled (0UL) /!< Event disabled. /
jamesadevine	0:e1a608bb55e8	5830	#define RTC_EVTENSET_TICK_Enabled (1UL) /!< Event enabled. /
jamesadevine	0:e1a608bb55e8	5831	#define RTC_EVTENSET_TICK_Set (1UL) /!< Enable event on write. /
jamesadevine	0:e1a608bb55e8	5832
jamesadevine	0:e1a608bb55e8	5833	/* Register: RTC_EVTENCLR */
jamesadevine	0:e1a608bb55e8	5834	/* Description: Disable events routing to PPI. The reading of this register gives the value of EVTEN. */
jamesadevine	0:e1a608bb55e8	5835
jamesadevine	0:e1a608bb55e8	5836	/* Bit 19 : Disable routing to PPI of COMPARE[3] event. */
jamesadevine	0:e1a608bb55e8	5837	#define RTC_EVTENCLR_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
jamesadevine	0:e1a608bb55e8	5838	#define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
jamesadevine	0:e1a608bb55e8	5839	#define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /!< Event disabled. /
jamesadevine	0:e1a608bb55e8	5840	#define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /!< Event enabled. /
jamesadevine	0:e1a608bb55e8	5841	#define RTC_EVTENCLR_COMPARE3_Clear (1UL) /!< Disable event on write. /
jamesadevine	0:e1a608bb55e8	5842
jamesadevine	0:e1a608bb55e8	5843	/* Bit 18 : Disable routing to PPI of COMPARE[2] event. */
jamesadevine	0:e1a608bb55e8	5844	#define RTC_EVTENCLR_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
jamesadevine	0:e1a608bb55e8	5845	#define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
jamesadevine	0:e1a608bb55e8	5846	#define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /!< Event disabled. /
jamesadevine	0:e1a608bb55e8	5847	#define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /!< Event enabled. /
jamesadevine	0:e1a608bb55e8	5848	#define RTC_EVTENCLR_COMPARE2_Clear (1UL) /!< Disable event on write. /
jamesadevine	0:e1a608bb55e8	5849
jamesadevine	0:e1a608bb55e8	5850	/* Bit 17 : Disable routing to PPI of COMPARE[1] event. */
jamesadevine	0:e1a608bb55e8	5851	#define RTC_EVTENCLR_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
jamesadevine	0:e1a608bb55e8	5852	#define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
jamesadevine	0:e1a608bb55e8	5853	#define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /!< Event disabled. /
jamesadevine	0:e1a608bb55e8	5854	#define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /!< Event enabled. /
jamesadevine	0:e1a608bb55e8	5855	#define RTC_EVTENCLR_COMPARE1_Clear (1UL) /!< Disable event on write. /
jamesadevine	0:e1a608bb55e8	5856
jamesadevine	0:e1a608bb55e8	5857	/* Bit 16 : Disable routing to PPI of COMPARE[0] event. */
jamesadevine	0:e1a608bb55e8	5858	#define RTC_EVTENCLR_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
jamesadevine	0:e1a608bb55e8	5859	#define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
jamesadevine	0:e1a608bb55e8	5860	#define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /!< Event disabled. /
jamesadevine	0:e1a608bb55e8	5861	#define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /!< Event enabled. /
jamesadevine	0:e1a608bb55e8	5862	#define RTC_EVTENCLR_COMPARE0_Clear (1UL) /!< Disable event on write. /
jamesadevine	0:e1a608bb55e8	5863
jamesadevine	0:e1a608bb55e8	5864	/* Bit 1 : Disable routing to PPI of OVRFLW event. */
jamesadevine	0:e1a608bb55e8	5865	#define RTC_EVTENCLR_OVRFLW_Pos (1UL) /!< Position of OVRFLW field. /
jamesadevine	0:e1a608bb55e8	5866	#define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /!< Bit mask of OVRFLW field. /
jamesadevine	0:e1a608bb55e8	5867	#define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /!< Event disabled. /
jamesadevine	0:e1a608bb55e8	5868	#define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /!< Event enabled. /
jamesadevine	0:e1a608bb55e8	5869	#define RTC_EVTENCLR_OVRFLW_Clear (1UL) /!< Disable event on write. /
jamesadevine	0:e1a608bb55e8	5870
jamesadevine	0:e1a608bb55e8	5871	/* Bit 0 : Disable routing to PPI of TICK event. */
jamesadevine	0:e1a608bb55e8	5872	#define RTC_EVTENCLR_TICK_Pos (0UL) /!< Position of TICK field. /
jamesadevine	0:e1a608bb55e8	5873	#define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /!< Bit mask of TICK field. /
jamesadevine	0:e1a608bb55e8	5874	#define RTC_EVTENCLR_TICK_Disabled (0UL) /!< Event disabled. /
jamesadevine	0:e1a608bb55e8	5875	#define RTC_EVTENCLR_TICK_Enabled (1UL) /!< Event enabled. /
jamesadevine	0:e1a608bb55e8	5876	#define RTC_EVTENCLR_TICK_Clear (1UL) /!< Disable event on write. /
jamesadevine	0:e1a608bb55e8	5877
jamesadevine	0:e1a608bb55e8	5878	/* Register: RTC_COUNTER */
jamesadevine	0:e1a608bb55e8	5879	/* Description: Current COUNTER value. */
jamesadevine	0:e1a608bb55e8	5880
jamesadevine	0:e1a608bb55e8	5881	/* Bits 23..0 : Counter value. */
jamesadevine	0:e1a608bb55e8	5882	#define RTC_COUNTER_COUNTER_Pos (0UL) /!< Position of COUNTER field. /
jamesadevine	0:e1a608bb55e8	5883	#define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /!< Bit mask of COUNTER field. /
jamesadevine	0:e1a608bb55e8	5884
jamesadevine	0:e1a608bb55e8	5885	/* Register: RTC_PRESCALER */
jamesadevine	0:e1a608bb55e8	5886	/* Description: 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). Must be written when RTC is STOPed. */
jamesadevine	0:e1a608bb55e8	5887
jamesadevine	0:e1a608bb55e8	5888	/* Bits 11..0 : RTC PRESCALER value. */
jamesadevine	0:e1a608bb55e8	5889	#define RTC_PRESCALER_PRESCALER_Pos (0UL) /!< Position of PRESCALER field. /
jamesadevine	0:e1a608bb55e8	5890	#define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /!< Bit mask of PRESCALER field. /
jamesadevine	0:e1a608bb55e8	5891
jamesadevine	0:e1a608bb55e8	5892	/* Register: RTC_CC */
jamesadevine	0:e1a608bb55e8	5893	/* Description: Capture/compare registers. */
jamesadevine	0:e1a608bb55e8	5894
jamesadevine	0:e1a608bb55e8	5895	/* Bits 23..0 : Compare value. */
jamesadevine	0:e1a608bb55e8	5896	#define RTC_CC_COMPARE_Pos (0UL) /!< Position of COMPARE field. /
jamesadevine	0:e1a608bb55e8	5897	#define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /!< Bit mask of COMPARE field. /
jamesadevine	0:e1a608bb55e8	5898
jamesadevine	0:e1a608bb55e8	5899	/* Register: RTC_POWER */
jamesadevine	0:e1a608bb55e8	5900	/* Description: Peripheral power control. */
jamesadevine	0:e1a608bb55e8	5901
jamesadevine	0:e1a608bb55e8	5902	/* Bit 0 : Peripheral power control. */
jamesadevine	0:e1a608bb55e8	5903	#define RTC_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
jamesadevine	0:e1a608bb55e8	5904	#define RTC_POWER_POWER_Msk (0x1UL << RTC_POWER_POWER_Pos) /!< Bit mask of POWER field. /
jamesadevine	0:e1a608bb55e8	5905	#define RTC_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
jamesadevine	0:e1a608bb55e8	5906	#define RTC_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
jamesadevine	0:e1a608bb55e8	5907
jamesadevine	0:e1a608bb55e8	5908
jamesadevine	0:e1a608bb55e8	5909	/* Peripheral: SPI */
jamesadevine	0:e1a608bb55e8	5910	/* Description: SPI master 0. */
jamesadevine	0:e1a608bb55e8	5911
jamesadevine	0:e1a608bb55e8	5912	/* Register: SPI_INTENSET */
jamesadevine	0:e1a608bb55e8	5913	/* Description: Interrupt enable set register. */
jamesadevine	0:e1a608bb55e8	5914
jamesadevine	0:e1a608bb55e8	5915	/* Bit 2 : Enable interrupt on READY event. */
jamesadevine	0:e1a608bb55e8	5916	#define SPI_INTENSET_READY_Pos (2UL) /!< Position of READY field. /
jamesadevine	0:e1a608bb55e8	5917	#define SPI_INTENSET_READY_Msk (0x1UL << SPI_INTENSET_READY_Pos) /!< Bit mask of READY field. /
jamesadevine	0:e1a608bb55e8	5918	#define SPI_INTENSET_READY_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	5919	#define SPI_INTENSET_READY_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	5920	#define SPI_INTENSET_READY_Set (1UL) /!< Enable interrupt on write. /
jamesadevine	0:e1a608bb55e8	5921
jamesadevine	0:e1a608bb55e8	5922	/* Register: SPI_INTENCLR */
jamesadevine	0:e1a608bb55e8	5923	/* Description: Interrupt enable clear register. */
jamesadevine	0:e1a608bb55e8	5924
jamesadevine	0:e1a608bb55e8	5925	/* Bit 2 : Disable interrupt on READY event. */
jamesadevine	0:e1a608bb55e8	5926	#define SPI_INTENCLR_READY_Pos (2UL) /!< Position of READY field. /
jamesadevine	0:e1a608bb55e8	5927	#define SPI_INTENCLR_READY_Msk (0x1UL << SPI_INTENCLR_READY_Pos) /!< Bit mask of READY field. /
jamesadevine	0:e1a608bb55e8	5928	#define SPI_INTENCLR_READY_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	5929	#define SPI_INTENCLR_READY_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	5930	#define SPI_INTENCLR_READY_Clear (1UL) /!< Disable interrupt on write. /
jamesadevine	0:e1a608bb55e8	5931
jamesadevine	0:e1a608bb55e8	5932	/* Register: SPI_ENABLE */
jamesadevine	0:e1a608bb55e8	5933	/* Description: Enable SPI. */
jamesadevine	0:e1a608bb55e8	5934
jamesadevine	0:e1a608bb55e8	5935	/* Bits 2..0 : Enable or disable SPI. */
jamesadevine	0:e1a608bb55e8	5936	#define SPI_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
jamesadevine	0:e1a608bb55e8	5937	#define SPI_ENABLE_ENABLE_Msk (0x7UL << SPI_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
jamesadevine	0:e1a608bb55e8	5938	#define SPI_ENABLE_ENABLE_Disabled (0x00UL) /!< Disabled SPI. /
jamesadevine	0:e1a608bb55e8	5939	#define SPI_ENABLE_ENABLE_Enabled (0x01UL) /!< Enable SPI. /
jamesadevine	0:e1a608bb55e8	5940
jamesadevine	0:e1a608bb55e8	5941	/* Register: SPI_RXD */
jamesadevine	0:e1a608bb55e8	5942	/* Description: RX data. */
jamesadevine	0:e1a608bb55e8	5943
jamesadevine	0:e1a608bb55e8	5944	/* Bits 7..0 : RX data from last transfer. */
jamesadevine	0:e1a608bb55e8	5945	#define SPI_RXD_RXD_Pos (0UL) /!< Position of RXD field. /
jamesadevine	0:e1a608bb55e8	5946	#define SPI_RXD_RXD_Msk (0xFFUL << SPI_RXD_RXD_Pos) /!< Bit mask of RXD field. /
jamesadevine	0:e1a608bb55e8	5947
jamesadevine	0:e1a608bb55e8	5948	/* Register: SPI_TXD */
jamesadevine	0:e1a608bb55e8	5949	/* Description: TX data. */
jamesadevine	0:e1a608bb55e8	5950
jamesadevine	0:e1a608bb55e8	5951	/* Bits 7..0 : TX data for next transfer. */
jamesadevine	0:e1a608bb55e8	5952	#define SPI_TXD_TXD_Pos (0UL) /!< Position of TXD field. /
jamesadevine	0:e1a608bb55e8	5953	#define SPI_TXD_TXD_Msk (0xFFUL << SPI_TXD_TXD_Pos) /!< Bit mask of TXD field. /
jamesadevine	0:e1a608bb55e8	5954
jamesadevine	0:e1a608bb55e8	5955	/* Register: SPI_FREQUENCY */
jamesadevine	0:e1a608bb55e8	5956	/* Description: SPI frequency */
jamesadevine	0:e1a608bb55e8	5957
jamesadevine	0:e1a608bb55e8	5958	/* Bits 31..0 : SPI data rate. */
jamesadevine	0:e1a608bb55e8	5959	#define SPI_FREQUENCY_FREQUENCY_Pos (0UL) /!< Position of FREQUENCY field. /
jamesadevine	0:e1a608bb55e8	5960	#define SPI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPI_FREQUENCY_FREQUENCY_Pos) /!< Bit mask of FREQUENCY field. /
jamesadevine	0:e1a608bb55e8	5961	#define SPI_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /!< 125kbps. /
jamesadevine	0:e1a608bb55e8	5962	#define SPI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /!< 250kbps. /
jamesadevine	0:e1a608bb55e8	5963	#define SPI_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /!< 500kbps. /
jamesadevine	0:e1a608bb55e8	5964	#define SPI_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /!< 1Mbps. /
jamesadevine	0:e1a608bb55e8	5965	#define SPI_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /!< 2Mbps. /
jamesadevine	0:e1a608bb55e8	5966	#define SPI_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /!< 4Mbps. /
jamesadevine	0:e1a608bb55e8	5967	#define SPI_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /!< 8Mbps. /
jamesadevine	0:e1a608bb55e8	5968
jamesadevine	0:e1a608bb55e8	5969	/* Register: SPI_CONFIG */
jamesadevine	0:e1a608bb55e8	5970	/* Description: Configuration register. */
jamesadevine	0:e1a608bb55e8	5971
jamesadevine	0:e1a608bb55e8	5972	/* Bit 2 : Serial clock (SCK) polarity. */
jamesadevine	0:e1a608bb55e8	5973	#define SPI_CONFIG_CPOL_Pos (2UL) /!< Position of CPOL field. /
jamesadevine	0:e1a608bb55e8	5974	#define SPI_CONFIG_CPOL_Msk (0x1UL << SPI_CONFIG_CPOL_Pos) /!< Bit mask of CPOL field. /
jamesadevine	0:e1a608bb55e8	5975	#define SPI_CONFIG_CPOL_ActiveHigh (0UL) /!< Active high. /
jamesadevine	0:e1a608bb55e8	5976	#define SPI_CONFIG_CPOL_ActiveLow (1UL) /!< Active low. /
jamesadevine	0:e1a608bb55e8	5977
jamesadevine	0:e1a608bb55e8	5978	/* Bit 1 : Serial clock (SCK) phase. */
jamesadevine	0:e1a608bb55e8	5979	#define SPI_CONFIG_CPHA_Pos (1UL) /!< Position of CPHA field. /
jamesadevine	0:e1a608bb55e8	5980	#define SPI_CONFIG_CPHA_Msk (0x1UL << SPI_CONFIG_CPHA_Pos) /!< Bit mask of CPHA field. /
jamesadevine	0:e1a608bb55e8	5981	#define SPI_CONFIG_CPHA_Leading (0UL) /!< Sample on leading edge of the clock. Shift serial data on trailing edge. /
jamesadevine	0:e1a608bb55e8	5982	#define SPI_CONFIG_CPHA_Trailing (1UL) /!< Sample on trailing edge of the clock. Shift serial data on leading edge. /
jamesadevine	0:e1a608bb55e8	5983
jamesadevine	0:e1a608bb55e8	5984	/* Bit 0 : Bit order. */
jamesadevine	0:e1a608bb55e8	5985	#define SPI_CONFIG_ORDER_Pos (0UL) /!< Position of ORDER field. /
jamesadevine	0:e1a608bb55e8	5986	#define SPI_CONFIG_ORDER_Msk (0x1UL << SPI_CONFIG_ORDER_Pos) /!< Bit mask of ORDER field. /
jamesadevine	0:e1a608bb55e8	5987	#define SPI_CONFIG_ORDER_MsbFirst (0UL) /!< Most significant bit transmitted out first. /
jamesadevine	0:e1a608bb55e8	5988	#define SPI_CONFIG_ORDER_LsbFirst (1UL) /!< Least significant bit transmitted out first. /
jamesadevine	0:e1a608bb55e8	5989
jamesadevine	0:e1a608bb55e8	5990	/* Register: SPI_POWER */
jamesadevine	0:e1a608bb55e8	5991	/* Description: Peripheral power control. */
jamesadevine	0:e1a608bb55e8	5992
jamesadevine	0:e1a608bb55e8	5993	/* Bit 0 : Peripheral power control. */
jamesadevine	0:e1a608bb55e8	5994	#define SPI_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
jamesadevine	0:e1a608bb55e8	5995	#define SPI_POWER_POWER_Msk (0x1UL << SPI_POWER_POWER_Pos) /!< Bit mask of POWER field. /
jamesadevine	0:e1a608bb55e8	5996	#define SPI_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
jamesadevine	0:e1a608bb55e8	5997	#define SPI_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
jamesadevine	0:e1a608bb55e8	5998
jamesadevine	0:e1a608bb55e8	5999
jamesadevine	0:e1a608bb55e8	6000	/* Peripheral: SPIM */
jamesadevine	0:e1a608bb55e8	6001	/* Description: SPI master with easyDMA 1. */
jamesadevine	0:e1a608bb55e8	6002
jamesadevine	0:e1a608bb55e8	6003	/* Register: SPIM_SHORTS */
jamesadevine	0:e1a608bb55e8	6004	/* Description: Shortcuts for SPIM. */
jamesadevine	0:e1a608bb55e8	6005
jamesadevine	0:e1a608bb55e8	6006	/* Bit 17 : Shortcut between END event and START task. */
jamesadevine	0:e1a608bb55e8	6007	#define SPIM_SHORTS_END_START_Pos (17UL) /!< Position of END_START field. /
jamesadevine	0:e1a608bb55e8	6008	#define SPIM_SHORTS_END_START_Msk (0x1UL << SPIM_SHORTS_END_START_Pos) /!< Bit mask of END_START field. /
jamesadevine	0:e1a608bb55e8	6009	#define SPIM_SHORTS_END_START_Disabled (0UL) /!< Shortcut disabled. /
jamesadevine	0:e1a608bb55e8	6010	#define SPIM_SHORTS_END_START_Enabled (1UL) /!< Shortcut enabled. /
jamesadevine	0:e1a608bb55e8	6011
jamesadevine	0:e1a608bb55e8	6012	/* Register: SPIM_INTENSET */
jamesadevine	0:e1a608bb55e8	6013	/* Description: Interrupt enable set register. */
jamesadevine	0:e1a608bb55e8	6014
jamesadevine	0:e1a608bb55e8	6015	/* Bit 19 : Enable interrupt on STARTED event. */
jamesadevine	0:e1a608bb55e8	6016	#define SPIM_INTENSET_STARTED_Pos (19UL) /!< Position of STARTED field. /
jamesadevine	0:e1a608bb55e8	6017	#define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /!< Bit mask of STARTED field. /
jamesadevine	0:e1a608bb55e8	6018	#define SPIM_INTENSET_STARTED_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	6019	#define SPIM_INTENSET_STARTED_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	6020	#define SPIM_INTENSET_STARTED_Set (1UL) /!< Enable interrupt on write. /
jamesadevine	0:e1a608bb55e8	6021
jamesadevine	0:e1a608bb55e8	6022	/* Bit 8 : Enable interrupt on ENDTX event. */
jamesadevine	0:e1a608bb55e8	6023	#define SPIM_INTENSET_ENDTX_Pos (8UL) /!< Position of ENDTX field. /
jamesadevine	0:e1a608bb55e8	6024	#define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /!< Bit mask of ENDTX field. /
jamesadevine	0:e1a608bb55e8	6025	#define SPIM_INTENSET_ENDTX_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	6026	#define SPIM_INTENSET_ENDTX_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	6027	#define SPIM_INTENSET_ENDTX_Set (1UL) /!< Enable interrupt on write. /
jamesadevine	0:e1a608bb55e8	6028
jamesadevine	0:e1a608bb55e8	6029	/* Bit 6 : Enable interrupt on END event. */
jamesadevine	0:e1a608bb55e8	6030	#define SPIM_INTENSET_END_Pos (6UL) /!< Position of END field. /
jamesadevine	0:e1a608bb55e8	6031	#define SPIM_INTENSET_END_Msk (0x1UL << SPIM_INTENSET_END_Pos) /!< Bit mask of END field. /
jamesadevine	0:e1a608bb55e8	6032	#define SPIM_INTENSET_END_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	6033	#define SPIM_INTENSET_END_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	6034	#define SPIM_INTENSET_END_Set (1UL) /!< Enable interrupt on write. /
jamesadevine	0:e1a608bb55e8	6035
jamesadevine	0:e1a608bb55e8	6036	/* Bit 4 : Enable interrupt on ENDRX event. */
jamesadevine	0:e1a608bb55e8	6037	#define SPIM_INTENSET_ENDRX_Pos (4UL) /!< Position of ENDRX field. /
jamesadevine	0:e1a608bb55e8	6038	#define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /!< Bit mask of ENDRX field. /
jamesadevine	0:e1a608bb55e8	6039	#define SPIM_INTENSET_ENDRX_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	6040	#define SPIM_INTENSET_ENDRX_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	6041	#define SPIM_INTENSET_ENDRX_Set (1UL) /!< Enable interrupt on write. /
jamesadevine	0:e1a608bb55e8	6042
jamesadevine	0:e1a608bb55e8	6043	/* Bit 1 : Enable interrupt on STOPPED event. */
jamesadevine	0:e1a608bb55e8	6044	#define SPIM_INTENSET_STOPPED_Pos (1UL) /!< Position of STOPPED field. /
jamesadevine	0:e1a608bb55e8	6045	#define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /!< Bit mask of STOPPED field. /
jamesadevine	0:e1a608bb55e8	6046	#define SPIM_INTENSET_STOPPED_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	6047	#define SPIM_INTENSET_STOPPED_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	6048	#define SPIM_INTENSET_STOPPED_Set (1UL) /!< Enable interrupt on write. /
jamesadevine	0:e1a608bb55e8	6049
jamesadevine	0:e1a608bb55e8	6050	/* Register: SPIM_INTENCLR */
jamesadevine	0:e1a608bb55e8	6051	/* Description: Interrupt enable clear register. */
jamesadevine	0:e1a608bb55e8	6052
jamesadevine	0:e1a608bb55e8	6053	/* Bit 19 : Disable interrupt on STARTED event. */
jamesadevine	0:e1a608bb55e8	6054	#define SPIM_INTENCLR_STARTED_Pos (19UL) /!< Position of STARTED field. /
jamesadevine	0:e1a608bb55e8	6055	#define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /!< Bit mask of STARTED field. /
jamesadevine	0:e1a608bb55e8	6056	#define SPIM_INTENCLR_STARTED_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	6057	#define SPIM_INTENCLR_STARTED_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	6058	#define SPIM_INTENCLR_STARTED_Clear (1UL) /!< Disable interrupt on write. /
jamesadevine	0:e1a608bb55e8	6059
jamesadevine	0:e1a608bb55e8	6060	/* Bit 8 : Disable interrupt on ENDTX event. */
jamesadevine	0:e1a608bb55e8	6061	#define SPIM_INTENCLR_ENDTX_Pos (8UL) /!< Position of ENDTX field. /
jamesadevine	0:e1a608bb55e8	6062	#define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /!< Bit mask of ENDTX field. /
jamesadevine	0:e1a608bb55e8	6063	#define SPIM_INTENCLR_ENDTX_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	6064	#define SPIM_INTENCLR_ENDTX_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	6065	#define SPIM_INTENCLR_ENDTX_Clear (1UL) /!< Disable interrupt on write. /
jamesadevine	0:e1a608bb55e8	6066
jamesadevine	0:e1a608bb55e8	6067	/* Bit 6 : Disable interrupt on END event. */
jamesadevine	0:e1a608bb55e8	6068	#define SPIM_INTENCLR_END_Pos (6UL) /!< Position of END field. /
jamesadevine	0:e1a608bb55e8	6069	#define SPIM_INTENCLR_END_Msk (0x1UL << SPIM_INTENCLR_END_Pos) /!< Bit mask of END field. /
jamesadevine	0:e1a608bb55e8	6070	#define SPIM_INTENCLR_END_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	6071	#define SPIM_INTENCLR_END_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	6072	#define SPIM_INTENCLR_END_Clear (1UL) /!< Disable interrupt on write. /
jamesadevine	0:e1a608bb55e8	6073
jamesadevine	0:e1a608bb55e8	6074	/* Bit 4 : Disable interrupt on ENDRX event. */
jamesadevine	0:e1a608bb55e8	6075	#define SPIM_INTENCLR_ENDRX_Pos (4UL) /!< Position of ENDRX field. /
jamesadevine	0:e1a608bb55e8	6076	#define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /!< Bit mask of ENDRX field. /
jamesadevine	0:e1a608bb55e8	6077	#define SPIM_INTENCLR_ENDRX_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	6078	#define SPIM_INTENCLR_ENDRX_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	6079	#define SPIM_INTENCLR_ENDRX_Clear (1UL) /!< Disable interrupt on write. /
jamesadevine	0:e1a608bb55e8	6080
jamesadevine	0:e1a608bb55e8	6081	/* Bit 1 : Disable interrupt on STOPPED event. */
jamesadevine	0:e1a608bb55e8	6082	#define SPIM_INTENCLR_STOPPED_Pos (1UL) /!< Position of STOPPED field. /
jamesadevine	0:e1a608bb55e8	6083	#define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /!< Bit mask of STOPPED field. /
jamesadevine	0:e1a608bb55e8	6084	#define SPIM_INTENCLR_STOPPED_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	6085	#define SPIM_INTENCLR_STOPPED_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	6086	#define SPIM_INTENCLR_STOPPED_Clear (1UL) /!< Disable interrupt on write. /
jamesadevine	0:e1a608bb55e8	6087
jamesadevine	0:e1a608bb55e8	6088	/* Register: SPIM_ENABLE */
jamesadevine	0:e1a608bb55e8	6089	/* Description: Enable SPIM. */
jamesadevine	0:e1a608bb55e8	6090
jamesadevine	0:e1a608bb55e8	6091	/* Bits 3..0 : Enable or disable SPIM. */
jamesadevine	0:e1a608bb55e8	6092	#define SPIM_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
jamesadevine	0:e1a608bb55e8	6093	#define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
jamesadevine	0:e1a608bb55e8	6094	#define SPIM_ENABLE_ENABLE_Disabled (0x00UL) /!< Disabled SPIM. /
jamesadevine	0:e1a608bb55e8	6095	#define SPIM_ENABLE_ENABLE_Enabled (0x07UL) /!< Enable SPIM. /
jamesadevine	0:e1a608bb55e8	6096
jamesadevine	0:e1a608bb55e8	6097	/* Register: SPIM_RXDDATA */
jamesadevine	0:e1a608bb55e8	6098	/* Description: RXD register. */
jamesadevine	0:e1a608bb55e8	6099
jamesadevine	0:e1a608bb55e8	6100	/* Bits 7..0 : RX data received. Double buffered. */
jamesadevine	0:e1a608bb55e8	6101	#define SPIM_RXDDATA_RXD_Pos (0UL) /!< Position of RXD field. /
jamesadevine	0:e1a608bb55e8	6102	#define SPIM_RXDDATA_RXD_Msk (0xFFUL << SPIM_RXDDATA_RXD_Pos) /!< Bit mask of RXD field. /
jamesadevine	0:e1a608bb55e8	6103
jamesadevine	0:e1a608bb55e8	6104	/* Register: SPIM_TXDDATA */
jamesadevine	0:e1a608bb55e8	6105	/* Description: TXD register. */
jamesadevine	0:e1a608bb55e8	6106
jamesadevine	0:e1a608bb55e8	6107	/* Bits 7..0 : TX data to send. Double buffered. */
jamesadevine	0:e1a608bb55e8	6108	#define SPIM_TXDDATA_TXD_Pos (0UL) /!< Position of TXD field. /
jamesadevine	0:e1a608bb55e8	6109	#define SPIM_TXDDATA_TXD_Msk (0xFFUL << SPIM_TXDDATA_TXD_Pos) /!< Bit mask of TXD field. /
jamesadevine	0:e1a608bb55e8	6110
jamesadevine	0:e1a608bb55e8	6111	/* Register: SPIM_FREQUENCY */
jamesadevine	0:e1a608bb55e8	6112	/* Description: SPI frequency. */
jamesadevine	0:e1a608bb55e8	6113
jamesadevine	0:e1a608bb55e8	6114	/* Bits 31..0 : SPI master data rate. */
jamesadevine	0:e1a608bb55e8	6115	#define SPIM_FREQUENCY_FREQUENCY_Pos (0UL) /!< Position of FREQUENCY field. /
jamesadevine	0:e1a608bb55e8	6116	#define SPIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos) /!< Bit mask of FREQUENCY field. /
jamesadevine	0:e1a608bb55e8	6117	#define SPIM_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /!< 125 kbps. /
jamesadevine	0:e1a608bb55e8	6118	#define SPIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /!< 250 kbps. /
jamesadevine	0:e1a608bb55e8	6119	#define SPIM_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /!< 500 kbps. /
jamesadevine	0:e1a608bb55e8	6120	#define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /!< 1 Mbps. /
jamesadevine	0:e1a608bb55e8	6121	#define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /!< 2 Mbps. /
jamesadevine	0:e1a608bb55e8	6122	#define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /!< 4 Mbps. /
jamesadevine	0:e1a608bb55e8	6123	#define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /!< 8 Mbps. /
jamesadevine	0:e1a608bb55e8	6124
jamesadevine	0:e1a608bb55e8	6125	/* Register: SPIM_CONFIG */
jamesadevine	0:e1a608bb55e8	6126	/* Description: Configuration register. */
jamesadevine	0:e1a608bb55e8	6127
jamesadevine	0:e1a608bb55e8	6128	/* Bit 2 : Serial clock (SCK) polarity. */
jamesadevine	0:e1a608bb55e8	6129	#define SPIM_CONFIG_CPOL_Pos (2UL) /!< Position of CPOL field. /
jamesadevine	0:e1a608bb55e8	6130	#define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos) /!< Bit mask of CPOL field. /
jamesadevine	0:e1a608bb55e8	6131	#define SPIM_CONFIG_CPOL_ActiveHigh (0UL) /!< Active high. /
jamesadevine	0:e1a608bb55e8	6132	#define SPIM_CONFIG_CPOL_ActiveLow (1UL) /!< Active low. /
jamesadevine	0:e1a608bb55e8	6133
jamesadevine	0:e1a608bb55e8	6134	/* Bit 1 : Serial clock (SCK) phase. */
jamesadevine	0:e1a608bb55e8	6135	#define SPIM_CONFIG_CPHA_Pos (1UL) /!< Position of CPHA field. /
jamesadevine	0:e1a608bb55e8	6136	#define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos) /!< Bit mask of CPHA field. /
jamesadevine	0:e1a608bb55e8	6137	#define SPIM_CONFIG_CPHA_Leading (0UL) /!< Sample on leading edge of the clock. Shift serial data on trailing edge. /
jamesadevine	0:e1a608bb55e8	6138	#define SPIM_CONFIG_CPHA_Trailing (1UL) /!< Sample on trailing edge of the clock. Shift serial data on leading edge. /
jamesadevine	0:e1a608bb55e8	6139
jamesadevine	0:e1a608bb55e8	6140	/* Bit 0 : Bit order. */
jamesadevine	0:e1a608bb55e8	6141	#define SPIM_CONFIG_ORDER_Pos (0UL) /!< Position of ORDER field. /
jamesadevine	0:e1a608bb55e8	6142	#define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos) /!< Bit mask of ORDER field. /
jamesadevine	0:e1a608bb55e8	6143	#define SPIM_CONFIG_ORDER_MsbFirst (0UL) /!< Most significant bit transmitted out first. /
jamesadevine	0:e1a608bb55e8	6144	#define SPIM_CONFIG_ORDER_LsbFirst (1UL) /!< Least significant bit transmitted out first. /
jamesadevine	0:e1a608bb55e8	6145
jamesadevine	0:e1a608bb55e8	6146	/* Register: SPIM_ORC */
jamesadevine	0:e1a608bb55e8	6147	/* Description: Over-read character. */
jamesadevine	0:e1a608bb55e8	6148
jamesadevine	0:e1a608bb55e8	6149	/* Bits 7..0 : Over-read character. */
jamesadevine	0:e1a608bb55e8	6150	#define SPIM_ORC_ORC_Pos (0UL) /!< Position of ORC field. /
jamesadevine	0:e1a608bb55e8	6151	#define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos) /!< Bit mask of ORC field. /
jamesadevine	0:e1a608bb55e8	6152
jamesadevine	0:e1a608bb55e8	6153	/* Register: SPIM_POWER */
jamesadevine	0:e1a608bb55e8	6154	/* Description: Peripheral power control. */
jamesadevine	0:e1a608bb55e8	6155
jamesadevine	0:e1a608bb55e8	6156	/* Bit 0 : Peripheral power control. */
jamesadevine	0:e1a608bb55e8	6157	#define SPIM_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
jamesadevine	0:e1a608bb55e8	6158	#define SPIM_POWER_POWER_Msk (0x1UL << SPIM_POWER_POWER_Pos) /!< Bit mask of POWER field. /
jamesadevine	0:e1a608bb55e8	6159	#define SPIM_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
jamesadevine	0:e1a608bb55e8	6160	#define SPIM_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
jamesadevine	0:e1a608bb55e8	6161
jamesadevine	0:e1a608bb55e8	6162	/* Register: SPIM_RXD_PTR */
jamesadevine	0:e1a608bb55e8	6163	/* Description: Data pointer. */
jamesadevine	0:e1a608bb55e8	6164
jamesadevine	0:e1a608bb55e8	6165	/* Bits 31..0 : Data pointer. */
jamesadevine	0:e1a608bb55e8	6166	#define SPIM_RXD_PTR_PTR_Pos (0UL) /!< Position of PTR field. /
jamesadevine	0:e1a608bb55e8	6167	#define SPIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos) /!< Bit mask of PTR field. /
jamesadevine	0:e1a608bb55e8	6168
jamesadevine	0:e1a608bb55e8	6169	/* Register: SPIM_RXD_MAXCNT */
jamesadevine	0:e1a608bb55e8	6170	/* Description: Maximum number of buffer bytes to receive. */
jamesadevine	0:e1a608bb55e8	6171
jamesadevine	0:e1a608bb55e8	6172	/* Bits 7..0 : Maximum number of buffer bytes to receive. */
jamesadevine	0:e1a608bb55e8	6173	#define SPIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /!< Position of MAXCNT field. /
jamesadevine	0:e1a608bb55e8	6174	#define SPIM_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos) /!< Bit mask of MAXCNT field. /
jamesadevine	0:e1a608bb55e8	6175
jamesadevine	0:e1a608bb55e8	6176	/* Register: SPIM_RXD_AMOUNT */
jamesadevine	0:e1a608bb55e8	6177	/* Description: Number of bytes received in the last transaction. */
jamesadevine	0:e1a608bb55e8	6178
jamesadevine	0:e1a608bb55e8	6179	/* Bits 7..0 : Number of bytes received in the last transaction. */
jamesadevine	0:e1a608bb55e8	6180	#define SPIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /!< Position of AMOUNT field. /
jamesadevine	0:e1a608bb55e8	6181	#define SPIM_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos) /!< Bit mask of AMOUNT field. /
jamesadevine	0:e1a608bb55e8	6182
jamesadevine	0:e1a608bb55e8	6183	/* Register: SPIM_TXD_PTR */
jamesadevine	0:e1a608bb55e8	6184	/* Description: Data pointer. */
jamesadevine	0:e1a608bb55e8	6185
jamesadevine	0:e1a608bb55e8	6186	/* Bits 31..0 : Data pointer. */
jamesadevine	0:e1a608bb55e8	6187	#define SPIM_TXD_PTR_PTR_Pos (0UL) /!< Position of PTR field. /
jamesadevine	0:e1a608bb55e8	6188	#define SPIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos) /!< Bit mask of PTR field. /
jamesadevine	0:e1a608bb55e8	6189
jamesadevine	0:e1a608bb55e8	6190	/* Register: SPIM_TXD_MAXCNT */
jamesadevine	0:e1a608bb55e8	6191	/* Description: Maximum number of buffer bytes to send. */
jamesadevine	0:e1a608bb55e8	6192
jamesadevine	0:e1a608bb55e8	6193	/* Bits 7..0 : Maximum number of buffer bytes to send. */
jamesadevine	0:e1a608bb55e8	6194	#define SPIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /!< Position of MAXCNT field. /
jamesadevine	0:e1a608bb55e8	6195	#define SPIM_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos) /!< Bit mask of MAXCNT field. /
jamesadevine	0:e1a608bb55e8	6196
jamesadevine	0:e1a608bb55e8	6197	/* Register: SPIM_TXD_AMOUNT */
jamesadevine	0:e1a608bb55e8	6198	/* Description: Number of bytes sent in the last transaction. */
jamesadevine	0:e1a608bb55e8	6199
jamesadevine	0:e1a608bb55e8	6200	/* Bits 7..0 : Number of bytes sent in the last transaction. */
jamesadevine	0:e1a608bb55e8	6201	#define SPIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /!< Position of AMOUNT field. /
jamesadevine	0:e1a608bb55e8	6202	#define SPIM_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos) /!< Bit mask of AMOUNT field. /
jamesadevine	0:e1a608bb55e8	6203
jamesadevine	0:e1a608bb55e8	6204
jamesadevine	0:e1a608bb55e8	6205	/* Peripheral: SPIS */
jamesadevine	0:e1a608bb55e8	6206	/* Description: SPI slave 1. */
jamesadevine	0:e1a608bb55e8	6207
jamesadevine	0:e1a608bb55e8	6208	/* Register: SPIS_SHORTS */
jamesadevine	0:e1a608bb55e8	6209	/* Description: Shortcuts for SPIS. */
jamesadevine	0:e1a608bb55e8	6210
jamesadevine	0:e1a608bb55e8	6211	/* Bit 2 : Shortcut between END event and the ACQUIRE task. */
jamesadevine	0:e1a608bb55e8	6212	#define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /!< Position of END_ACQUIRE field. /
jamesadevine	0:e1a608bb55e8	6213	#define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /!< Bit mask of END_ACQUIRE field. /
jamesadevine	0:e1a608bb55e8	6214	#define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /!< Shortcut disabled. /
jamesadevine	0:e1a608bb55e8	6215	#define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /!< Shortcut enabled. /
jamesadevine	0:e1a608bb55e8	6216
jamesadevine	0:e1a608bb55e8	6217	/* Register: SPIS_INTENSET */
jamesadevine	0:e1a608bb55e8	6218	/* Description: Interrupt enable set register. */
jamesadevine	0:e1a608bb55e8	6219
jamesadevine	0:e1a608bb55e8	6220	/* Bit 10 : Enable interrupt on ACQUIRED event. */
jamesadevine	0:e1a608bb55e8	6221	#define SPIS_INTENSET_ACQUIRED_Pos (10UL) /!< Position of ACQUIRED field. /
jamesadevine	0:e1a608bb55e8	6222	#define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /!< Bit mask of ACQUIRED field. /
jamesadevine	0:e1a608bb55e8	6223	#define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	6224	#define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	6225	#define SPIS_INTENSET_ACQUIRED_Set (1UL) /!< Enable interrupt on write. /
jamesadevine	0:e1a608bb55e8	6226
jamesadevine	0:e1a608bb55e8	6227	/* Bit 1 : Enable interrupt on END event. */
jamesadevine	0:e1a608bb55e8	6228	#define SPIS_INTENSET_END_Pos (1UL) /!< Position of END field. /
jamesadevine	0:e1a608bb55e8	6229	#define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /!< Bit mask of END field. /
jamesadevine	0:e1a608bb55e8	6230	#define SPIS_INTENSET_END_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	6231	#define SPIS_INTENSET_END_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	6232	#define SPIS_INTENSET_END_Set (1UL) /!< Enable interrupt on write. /
jamesadevine	0:e1a608bb55e8	6233
jamesadevine	0:e1a608bb55e8	6234	/* Register: SPIS_INTENCLR */
jamesadevine	0:e1a608bb55e8	6235	/* Description: Interrupt enable clear register. */
jamesadevine	0:e1a608bb55e8	6236
jamesadevine	0:e1a608bb55e8	6237	/* Bit 10 : Disable interrupt on ACQUIRED event. */
jamesadevine	0:e1a608bb55e8	6238	#define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /!< Position of ACQUIRED field. /
jamesadevine	0:e1a608bb55e8	6239	#define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /!< Bit mask of ACQUIRED field. /
jamesadevine	0:e1a608bb55e8	6240	#define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	6241	#define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	6242	#define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /!< Disable interrupt on write. /
jamesadevine	0:e1a608bb55e8	6243
jamesadevine	0:e1a608bb55e8	6244	/* Bit 1 : Disable interrupt on END event. */
jamesadevine	0:e1a608bb55e8	6245	#define SPIS_INTENCLR_END_Pos (1UL) /!< Position of END field. /
jamesadevine	0:e1a608bb55e8	6246	#define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /!< Bit mask of END field. /
jamesadevine	0:e1a608bb55e8	6247	#define SPIS_INTENCLR_END_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	6248	#define SPIS_INTENCLR_END_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	6249	#define SPIS_INTENCLR_END_Clear (1UL) /!< Disable interrupt on write. /
jamesadevine	0:e1a608bb55e8	6250
jamesadevine	0:e1a608bb55e8	6251	/* Register: SPIS_SEMSTAT */
jamesadevine	0:e1a608bb55e8	6252	/* Description: Semaphore status. */
jamesadevine	0:e1a608bb55e8	6253
jamesadevine	0:e1a608bb55e8	6254	/* Bits 1..0 : Semaphore status. */
jamesadevine	0:e1a608bb55e8	6255	#define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /!< Position of SEMSTAT field. /
jamesadevine	0:e1a608bb55e8	6256	#define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /!< Bit mask of SEMSTAT field. /
jamesadevine	0:e1a608bb55e8	6257	#define SPIS_SEMSTAT_SEMSTAT_Free (0x00UL) /!< Semaphore is free. /
jamesadevine	0:e1a608bb55e8	6258	#define SPIS_SEMSTAT_SEMSTAT_CPU (0x01UL) /!< Semaphore is assigned to the CPU. /
jamesadevine	0:e1a608bb55e8	6259	#define SPIS_SEMSTAT_SEMSTAT_SPIS (0x02UL) /!< Semaphore is assigned to the SPIS. /
jamesadevine	0:e1a608bb55e8	6260	#define SPIS_SEMSTAT_SEMSTAT_CPUPending (0x03UL) /!< Semaphore is assigned to the SPIS, but a handover to the CPU is pending. /
jamesadevine	0:e1a608bb55e8	6261
jamesadevine	0:e1a608bb55e8	6262	/* Register: SPIS_STATUS */
jamesadevine	0:e1a608bb55e8	6263	/* Description: Status from last transaction. */
jamesadevine	0:e1a608bb55e8	6264
jamesadevine	0:e1a608bb55e8	6265	/* Bit 1 : RX buffer overflow detected, and prevented. */
jamesadevine	0:e1a608bb55e8	6266	#define SPIS_STATUS_OVERFLOW_Pos (1UL) /!< Position of OVERFLOW field. /
jamesadevine	0:e1a608bb55e8	6267	#define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /!< Bit mask of OVERFLOW field. /
jamesadevine	0:e1a608bb55e8	6268	#define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /!< Error not present. /
jamesadevine	0:e1a608bb55e8	6269	#define SPIS_STATUS_OVERFLOW_Present (1UL) /!< Error present. /
jamesadevine	0:e1a608bb55e8	6270	#define SPIS_STATUS_OVERFLOW_Clear (1UL) /!< Clear on write. /
jamesadevine	0:e1a608bb55e8	6271
jamesadevine	0:e1a608bb55e8	6272	/* Bit 0 : TX buffer overread detected, and prevented. */
jamesadevine	0:e1a608bb55e8	6273	#define SPIS_STATUS_OVERREAD_Pos (0UL) /!< Position of OVERREAD field. /
jamesadevine	0:e1a608bb55e8	6274	#define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /!< Bit mask of OVERREAD field. /
jamesadevine	0:e1a608bb55e8	6275	#define SPIS_STATUS_OVERREAD_NotPresent (0UL) /!< Error not present. /
jamesadevine	0:e1a608bb55e8	6276	#define SPIS_STATUS_OVERREAD_Present (1UL) /!< Error present. /
jamesadevine	0:e1a608bb55e8	6277	#define SPIS_STATUS_OVERREAD_Clear (1UL) /!< Clear on write. /
jamesadevine	0:e1a608bb55e8	6278
jamesadevine	0:e1a608bb55e8	6279	/* Register: SPIS_ENABLE */
jamesadevine	0:e1a608bb55e8	6280	/* Description: Enable SPIS. */
jamesadevine	0:e1a608bb55e8	6281
jamesadevine	0:e1a608bb55e8	6282	/* Bits 2..0 : Enable or disable SPIS. */
jamesadevine	0:e1a608bb55e8	6283	#define SPIS_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
jamesadevine	0:e1a608bb55e8	6284	#define SPIS_ENABLE_ENABLE_Msk (0x7UL << SPIS_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
jamesadevine	0:e1a608bb55e8	6285	#define SPIS_ENABLE_ENABLE_Disabled (0x00UL) /!< Disabled SPIS. /
jamesadevine	0:e1a608bb55e8	6286	#define SPIS_ENABLE_ENABLE_Enabled (0x02UL) /!< Enable SPIS. /
jamesadevine	0:e1a608bb55e8	6287
jamesadevine	0:e1a608bb55e8	6288	/* Register: SPIS_MAXRX */
jamesadevine	0:e1a608bb55e8	6289	/* Description: Maximum number of bytes in the receive buffer. */
jamesadevine	0:e1a608bb55e8	6290
jamesadevine	0:e1a608bb55e8	6291	/* Bits 7..0 : Maximum number of bytes in the receive buffer. */
jamesadevine	0:e1a608bb55e8	6292	#define SPIS_MAXRX_MAXRX_Pos (0UL) /!< Position of MAXRX field. /
jamesadevine	0:e1a608bb55e8	6293	#define SPIS_MAXRX_MAXRX_Msk (0xFFUL << SPIS_MAXRX_MAXRX_Pos) /!< Bit mask of MAXRX field. /
jamesadevine	0:e1a608bb55e8	6294
jamesadevine	0:e1a608bb55e8	6295	/* Register: SPIS_AMOUNTRX */
jamesadevine	0:e1a608bb55e8	6296	/* Description: Number of bytes received in last granted transaction. */
jamesadevine	0:e1a608bb55e8	6297
jamesadevine	0:e1a608bb55e8	6298	/* Bits 7..0 : Number of bytes received in last granted transaction. */
jamesadevine	0:e1a608bb55e8	6299	#define SPIS_AMOUNTRX_AMOUNTRX_Pos (0UL) /!< Position of AMOUNTRX field. /
jamesadevine	0:e1a608bb55e8	6300	#define SPIS_AMOUNTRX_AMOUNTRX_Msk (0xFFUL << SPIS_AMOUNTRX_AMOUNTRX_Pos) /!< Bit mask of AMOUNTRX field. /
jamesadevine	0:e1a608bb55e8	6301
jamesadevine	0:e1a608bb55e8	6302	/* Register: SPIS_MAXTX */
jamesadevine	0:e1a608bb55e8	6303	/* Description: Maximum number of bytes in the transmit buffer. */
jamesadevine	0:e1a608bb55e8	6304
jamesadevine	0:e1a608bb55e8	6305	/* Bits 7..0 : Maximum number of bytes in the transmit buffer. */
jamesadevine	0:e1a608bb55e8	6306	#define SPIS_MAXTX_MAXTX_Pos (0UL) /!< Position of MAXTX field. /
jamesadevine	0:e1a608bb55e8	6307	#define SPIS_MAXTX_MAXTX_Msk (0xFFUL << SPIS_MAXTX_MAXTX_Pos) /!< Bit mask of MAXTX field. /
jamesadevine	0:e1a608bb55e8	6308
jamesadevine	0:e1a608bb55e8	6309	/* Register: SPIS_AMOUNTTX */
jamesadevine	0:e1a608bb55e8	6310	/* Description: Number of bytes transmitted in last granted transaction. */
jamesadevine	0:e1a608bb55e8	6311
jamesadevine	0:e1a608bb55e8	6312	/* Bits 7..0 : Number of bytes transmitted in last granted transaction. */
jamesadevine	0:e1a608bb55e8	6313	#define SPIS_AMOUNTTX_AMOUNTTX_Pos (0UL) /!< Position of AMOUNTTX field. /
jamesadevine	0:e1a608bb55e8	6314	#define SPIS_AMOUNTTX_AMOUNTTX_Msk (0xFFUL << SPIS_AMOUNTTX_AMOUNTTX_Pos) /!< Bit mask of AMOUNTTX field. /
jamesadevine	0:e1a608bb55e8	6315
jamesadevine	0:e1a608bb55e8	6316	/* Register: SPIS_CONFIG */
jamesadevine	0:e1a608bb55e8	6317	/* Description: Configuration register. */
jamesadevine	0:e1a608bb55e8	6318
jamesadevine	0:e1a608bb55e8	6319	/* Bit 2 : Serial clock (SCK) polarity. */
jamesadevine	0:e1a608bb55e8	6320	#define SPIS_CONFIG_CPOL_Pos (2UL) /!< Position of CPOL field. /
jamesadevine	0:e1a608bb55e8	6321	#define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /!< Bit mask of CPOL field. /
jamesadevine	0:e1a608bb55e8	6322	#define SPIS_CONFIG_CPOL_ActiveHigh (0UL) /!< Active high. /
jamesadevine	0:e1a608bb55e8	6323	#define SPIS_CONFIG_CPOL_ActiveLow (1UL) /!< Active low. /
jamesadevine	0:e1a608bb55e8	6324
jamesadevine	0:e1a608bb55e8	6325	/* Bit 1 : Serial clock (SCK) phase. */
jamesadevine	0:e1a608bb55e8	6326	#define SPIS_CONFIG_CPHA_Pos (1UL) /!< Position of CPHA field. /
jamesadevine	0:e1a608bb55e8	6327	#define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /!< Bit mask of CPHA field. /
jamesadevine	0:e1a608bb55e8	6328	#define SPIS_CONFIG_CPHA_Leading (0UL) /!< Sample on leading edge of the clock. Shift serial data on trailing edge. /
jamesadevine	0:e1a608bb55e8	6329	#define SPIS_CONFIG_CPHA_Trailing (1UL) /!< Sample on trailing edge of the clock. Shift serial data on leading edge. /
jamesadevine	0:e1a608bb55e8	6330
jamesadevine	0:e1a608bb55e8	6331	/* Bit 0 : Bit order. */
jamesadevine	0:e1a608bb55e8	6332	#define SPIS_CONFIG_ORDER_Pos (0UL) /!< Position of ORDER field. /
jamesadevine	0:e1a608bb55e8	6333	#define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /!< Bit mask of ORDER field. /
jamesadevine	0:e1a608bb55e8	6334	#define SPIS_CONFIG_ORDER_MsbFirst (0UL) /!< Most significant bit transmitted out first. /
jamesadevine	0:e1a608bb55e8	6335	#define SPIS_CONFIG_ORDER_LsbFirst (1UL) /!< Least significant bit transmitted out first. /
jamesadevine	0:e1a608bb55e8	6336
jamesadevine	0:e1a608bb55e8	6337	/* Register: SPIS_DEF */
jamesadevine	0:e1a608bb55e8	6338	/* Description: Default character. */
jamesadevine	0:e1a608bb55e8	6339
jamesadevine	0:e1a608bb55e8	6340	/* Bits 7..0 : Default character. */
jamesadevine	0:e1a608bb55e8	6341	#define SPIS_DEF_DEF_Pos (0UL) /!< Position of DEF field. /
jamesadevine	0:e1a608bb55e8	6342	#define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /!< Bit mask of DEF field. /
jamesadevine	0:e1a608bb55e8	6343
jamesadevine	0:e1a608bb55e8	6344	/* Register: SPIS_ORC */
jamesadevine	0:e1a608bb55e8	6345	/* Description: Over-read character. */
jamesadevine	0:e1a608bb55e8	6346
jamesadevine	0:e1a608bb55e8	6347	/* Bits 7..0 : Over-read character. */
jamesadevine	0:e1a608bb55e8	6348	#define SPIS_ORC_ORC_Pos (0UL) /!< Position of ORC field. /
jamesadevine	0:e1a608bb55e8	6349	#define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /!< Bit mask of ORC field. /
jamesadevine	0:e1a608bb55e8	6350
jamesadevine	0:e1a608bb55e8	6351	/* Register: SPIS_POWER */
jamesadevine	0:e1a608bb55e8	6352	/* Description: Peripheral power control. */
jamesadevine	0:e1a608bb55e8	6353
jamesadevine	0:e1a608bb55e8	6354	/* Bit 0 : Peripheral power control. */
jamesadevine	0:e1a608bb55e8	6355	#define SPIS_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
jamesadevine	0:e1a608bb55e8	6356	#define SPIS_POWER_POWER_Msk (0x1UL << SPIS_POWER_POWER_Pos) /!< Bit mask of POWER field. /
jamesadevine	0:e1a608bb55e8	6357	#define SPIS_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
jamesadevine	0:e1a608bb55e8	6358	#define SPIS_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
jamesadevine	0:e1a608bb55e8	6359
jamesadevine	0:e1a608bb55e8	6360
jamesadevine	0:e1a608bb55e8	6361	/* Peripheral: TEMP */
jamesadevine	0:e1a608bb55e8	6362	/* Description: Temperature Sensor. */
jamesadevine	0:e1a608bb55e8	6363
jamesadevine	0:e1a608bb55e8	6364	/* Register: TEMP_INTENSET */
jamesadevine	0:e1a608bb55e8	6365	/* Description: Interrupt enable set register. */
jamesadevine	0:e1a608bb55e8	6366
jamesadevine	0:e1a608bb55e8	6367	/* Bit 0 : Enable interrupt on DATARDY event. */
jamesadevine	0:e1a608bb55e8	6368	#define TEMP_INTENSET_DATARDY_Pos (0UL) /!< Position of DATARDY field. /
jamesadevine	0:e1a608bb55e8	6369	#define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /!< Bit mask of DATARDY field. /
jamesadevine	0:e1a608bb55e8	6370	#define TEMP_INTENSET_DATARDY_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	6371	#define TEMP_INTENSET_DATARDY_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	6372	#define TEMP_INTENSET_DATARDY_Set (1UL) /!< Enable interrupt on write. /
jamesadevine	0:e1a608bb55e8	6373
jamesadevine	0:e1a608bb55e8	6374	/* Register: TEMP_INTENCLR */
jamesadevine	0:e1a608bb55e8	6375	/* Description: Interrupt enable clear register. */
jamesadevine	0:e1a608bb55e8	6376
jamesadevine	0:e1a608bb55e8	6377	/* Bit 0 : Disable interrupt on DATARDY event. */
jamesadevine	0:e1a608bb55e8	6378	#define TEMP_INTENCLR_DATARDY_Pos (0UL) /!< Position of DATARDY field. /
jamesadevine	0:e1a608bb55e8	6379	#define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /!< Bit mask of DATARDY field. /
jamesadevine	0:e1a608bb55e8	6380	#define TEMP_INTENCLR_DATARDY_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	6381	#define TEMP_INTENCLR_DATARDY_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	6382	#define TEMP_INTENCLR_DATARDY_Clear (1UL) /!< Disable interrupt on write. /
jamesadevine	0:e1a608bb55e8	6383
jamesadevine	0:e1a608bb55e8	6384	/* Register: TEMP_POWER */
jamesadevine	0:e1a608bb55e8	6385	/* Description: Peripheral power control. */
jamesadevine	0:e1a608bb55e8	6386
jamesadevine	0:e1a608bb55e8	6387	/* Bit 0 : Peripheral power control. */
jamesadevine	0:e1a608bb55e8	6388	#define TEMP_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
jamesadevine	0:e1a608bb55e8	6389	#define TEMP_POWER_POWER_Msk (0x1UL << TEMP_POWER_POWER_Pos) /!< Bit mask of POWER field. /
jamesadevine	0:e1a608bb55e8	6390	#define TEMP_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
jamesadevine	0:e1a608bb55e8	6391	#define TEMP_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
jamesadevine	0:e1a608bb55e8	6392
jamesadevine	0:e1a608bb55e8	6393
jamesadevine	0:e1a608bb55e8	6394	/* Peripheral: TIMER */
jamesadevine	0:e1a608bb55e8	6395	/* Description: Timer 0. */
jamesadevine	0:e1a608bb55e8	6396
jamesadevine	0:e1a608bb55e8	6397	/* Register: TIMER_SHORTS */
jamesadevine	0:e1a608bb55e8	6398	/* Description: Shortcuts for Timer. */
jamesadevine	0:e1a608bb55e8	6399
jamesadevine	0:e1a608bb55e8	6400	/* Bit 11 : Shortcut between CC[3] event and the STOP task. */
jamesadevine	0:e1a608bb55e8	6401	#define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /!< Position of COMPARE3_STOP field. /
jamesadevine	0:e1a608bb55e8	6402	#define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /!< Bit mask of COMPARE3_STOP field. /
jamesadevine	0:e1a608bb55e8	6403	#define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /!< Shortcut disabled. /
jamesadevine	0:e1a608bb55e8	6404	#define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /!< Shortcut enabled. /
jamesadevine	0:e1a608bb55e8	6405
jamesadevine	0:e1a608bb55e8	6406	/* Bit 10 : Shortcut between CC[2] event and the STOP task. */
jamesadevine	0:e1a608bb55e8	6407	#define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /!< Position of COMPARE2_STOP field. /
jamesadevine	0:e1a608bb55e8	6408	#define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /!< Bit mask of COMPARE2_STOP field. /
jamesadevine	0:e1a608bb55e8	6409	#define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /!< Shortcut disabled. /
jamesadevine	0:e1a608bb55e8	6410	#define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /!< Shortcut enabled. /
jamesadevine	0:e1a608bb55e8	6411
jamesadevine	0:e1a608bb55e8	6412	/* Bit 9 : Shortcut between CC[1] event and the STOP task. */
jamesadevine	0:e1a608bb55e8	6413	#define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /!< Position of COMPARE1_STOP field. /
jamesadevine	0:e1a608bb55e8	6414	#define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /!< Bit mask of COMPARE1_STOP field. /
jamesadevine	0:e1a608bb55e8	6415	#define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /!< Shortcut disabled. /
jamesadevine	0:e1a608bb55e8	6416	#define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /!< Shortcut enabled. /
jamesadevine	0:e1a608bb55e8	6417
jamesadevine	0:e1a608bb55e8	6418	/* Bit 8 : Shortcut between CC[0] event and the STOP task. */
jamesadevine	0:e1a608bb55e8	6419	#define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /!< Position of COMPARE0_STOP field. /
jamesadevine	0:e1a608bb55e8	6420	#define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /!< Bit mask of COMPARE0_STOP field. /
jamesadevine	0:e1a608bb55e8	6421	#define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /!< Shortcut disabled. /
jamesadevine	0:e1a608bb55e8	6422	#define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /!< Shortcut enabled. /
jamesadevine	0:e1a608bb55e8	6423
jamesadevine	0:e1a608bb55e8	6424	/* Bit 3 : Shortcut between CC[3] event and the CLEAR task. */
jamesadevine	0:e1a608bb55e8	6425	#define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /!< Position of COMPARE3_CLEAR field. /
jamesadevine	0:e1a608bb55e8	6426	#define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /!< Bit mask of COMPARE3_CLEAR field. /
jamesadevine	0:e1a608bb55e8	6427	#define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /!< Shortcut disabled. /
jamesadevine	0:e1a608bb55e8	6428	#define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /!< Shortcut enabled. /
jamesadevine	0:e1a608bb55e8	6429
jamesadevine	0:e1a608bb55e8	6430	/* Bit 2 : Shortcut between CC[2] event and the CLEAR task. */
jamesadevine	0:e1a608bb55e8	6431	#define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /!< Position of COMPARE2_CLEAR field. /
jamesadevine	0:e1a608bb55e8	6432	#define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /!< Bit mask of COMPARE2_CLEAR field. /
jamesadevine	0:e1a608bb55e8	6433	#define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /!< Shortcut disabled. /
jamesadevine	0:e1a608bb55e8	6434	#define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /!< Shortcut enabled. /
jamesadevine	0:e1a608bb55e8	6435
jamesadevine	0:e1a608bb55e8	6436	/* Bit 1 : Shortcut between CC[1] event and the CLEAR task. */
jamesadevine	0:e1a608bb55e8	6437	#define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /!< Position of COMPARE1_CLEAR field. /
jamesadevine	0:e1a608bb55e8	6438	#define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /!< Bit mask of COMPARE1_CLEAR field. /
jamesadevine	0:e1a608bb55e8	6439	#define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /!< Shortcut disabled. /
jamesadevine	0:e1a608bb55e8	6440	#define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /!< Shortcut enabled. /
jamesadevine	0:e1a608bb55e8	6441
jamesadevine	0:e1a608bb55e8	6442	/* Bit 0 : Shortcut between CC[0] event and the CLEAR task. */
jamesadevine	0:e1a608bb55e8	6443	#define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /!< Position of COMPARE0_CLEAR field. /
jamesadevine	0:e1a608bb55e8	6444	#define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /!< Bit mask of COMPARE0_CLEAR field. /
jamesadevine	0:e1a608bb55e8	6445	#define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /!< Shortcut disabled. /
jamesadevine	0:e1a608bb55e8	6446	#define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /!< Shortcut enabled. /
jamesadevine	0:e1a608bb55e8	6447
jamesadevine	0:e1a608bb55e8	6448	/* Register: TIMER_INTENSET */
jamesadevine	0:e1a608bb55e8	6449	/* Description: Interrupt enable set register. */
jamesadevine	0:e1a608bb55e8	6450
jamesadevine	0:e1a608bb55e8	6451	/* Bit 19 : Enable interrupt on COMPARE[3] */
jamesadevine	0:e1a608bb55e8	6452	#define TIMER_INTENSET_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
jamesadevine	0:e1a608bb55e8	6453	#define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
jamesadevine	0:e1a608bb55e8	6454	#define TIMER_INTENSET_COMPARE3_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	6455	#define TIMER_INTENSET_COMPARE3_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	6456	#define TIMER_INTENSET_COMPARE3_Set (1UL) /!< Enable interrupt on write. /
jamesadevine	0:e1a608bb55e8	6457
jamesadevine	0:e1a608bb55e8	6458	/* Bit 18 : Enable interrupt on COMPARE[2] */
jamesadevine	0:e1a608bb55e8	6459	#define TIMER_INTENSET_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
jamesadevine	0:e1a608bb55e8	6460	#define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
jamesadevine	0:e1a608bb55e8	6461	#define TIMER_INTENSET_COMPARE2_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	6462	#define TIMER_INTENSET_COMPARE2_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	6463	#define TIMER_INTENSET_COMPARE2_Set (1UL) /!< Enable interrupt on write. /
jamesadevine	0:e1a608bb55e8	6464
jamesadevine	0:e1a608bb55e8	6465	/* Bit 17 : Enable interrupt on COMPARE[1] */
jamesadevine	0:e1a608bb55e8	6466	#define TIMER_INTENSET_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
jamesadevine	0:e1a608bb55e8	6467	#define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
jamesadevine	0:e1a608bb55e8	6468	#define TIMER_INTENSET_COMPARE1_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	6469	#define TIMER_INTENSET_COMPARE1_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	6470	#define TIMER_INTENSET_COMPARE1_Set (1UL) /!< Enable interrupt on write. /
jamesadevine	0:e1a608bb55e8	6471
jamesadevine	0:e1a608bb55e8	6472	/* Bit 16 : Enable interrupt on COMPARE[0] */
jamesadevine	0:e1a608bb55e8	6473	#define TIMER_INTENSET_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
jamesadevine	0:e1a608bb55e8	6474	#define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
jamesadevine	0:e1a608bb55e8	6475	#define TIMER_INTENSET_COMPARE0_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	6476	#define TIMER_INTENSET_COMPARE0_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	6477	#define TIMER_INTENSET_COMPARE0_Set (1UL) /!< Enable interrupt on write. /
jamesadevine	0:e1a608bb55e8	6478
jamesadevine	0:e1a608bb55e8	6479	/* Register: TIMER_INTENCLR */
jamesadevine	0:e1a608bb55e8	6480	/* Description: Interrupt enable clear register. */
jamesadevine	0:e1a608bb55e8	6481
jamesadevine	0:e1a608bb55e8	6482	/* Bit 19 : Disable interrupt on COMPARE[3] */
jamesadevine	0:e1a608bb55e8	6483	#define TIMER_INTENCLR_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
jamesadevine	0:e1a608bb55e8	6484	#define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
jamesadevine	0:e1a608bb55e8	6485	#define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	6486	#define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	6487	#define TIMER_INTENCLR_COMPARE3_Clear (1UL) /!< Disable interrupt on write. /
jamesadevine	0:e1a608bb55e8	6488
jamesadevine	0:e1a608bb55e8	6489	/* Bit 18 : Disable interrupt on COMPARE[2] */
jamesadevine	0:e1a608bb55e8	6490	#define TIMER_INTENCLR_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
jamesadevine	0:e1a608bb55e8	6491	#define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
jamesadevine	0:e1a608bb55e8	6492	#define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	6493	#define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	6494	#define TIMER_INTENCLR_COMPARE2_Clear (1UL) /!< Disable interrupt on write. /
jamesadevine	0:e1a608bb55e8	6495
jamesadevine	0:e1a608bb55e8	6496	/* Bit 17 : Disable interrupt on COMPARE[1] */
jamesadevine	0:e1a608bb55e8	6497	#define TIMER_INTENCLR_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
jamesadevine	0:e1a608bb55e8	6498	#define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
jamesadevine	0:e1a608bb55e8	6499	#define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	6500	#define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	6501	#define TIMER_INTENCLR_COMPARE1_Clear (1UL) /!< Disable interrupt on write. /
jamesadevine	0:e1a608bb55e8	6502
jamesadevine	0:e1a608bb55e8	6503	/* Bit 16 : Disable interrupt on COMPARE[0] */
jamesadevine	0:e1a608bb55e8	6504	#define TIMER_INTENCLR_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
jamesadevine	0:e1a608bb55e8	6505	#define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
jamesadevine	0:e1a608bb55e8	6506	#define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	6507	#define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	6508	#define TIMER_INTENCLR_COMPARE0_Clear (1UL) /!< Disable interrupt on write. /
jamesadevine	0:e1a608bb55e8	6509
jamesadevine	0:e1a608bb55e8	6510	/* Register: TIMER_MODE */
jamesadevine	0:e1a608bb55e8	6511	/* Description: Timer Mode selection. */
jamesadevine	0:e1a608bb55e8	6512
jamesadevine	0:e1a608bb55e8	6513	/* Bit 0 : Select Normal or Counter mode. */
jamesadevine	0:e1a608bb55e8	6514	#define TIMER_MODE_MODE_Pos (0UL) /!< Position of MODE field. /
jamesadevine	0:e1a608bb55e8	6515	#define TIMER_MODE_MODE_Msk (0x1UL << TIMER_MODE_MODE_Pos) /!< Bit mask of MODE field. /
jamesadevine	0:e1a608bb55e8	6516	#define TIMER_MODE_MODE_Timer (0UL) /!< Timer in Normal mode. /
jamesadevine	0:e1a608bb55e8	6517	#define TIMER_MODE_MODE_Counter (1UL) /!< Timer in Counter mode. /
jamesadevine	0:e1a608bb55e8	6518
jamesadevine	0:e1a608bb55e8	6519	/* Register: TIMER_BITMODE */
jamesadevine	0:e1a608bb55e8	6520	/* Description: Sets timer behaviour. */
jamesadevine	0:e1a608bb55e8	6521
jamesadevine	0:e1a608bb55e8	6522	/* Bits 1..0 : Sets timer behaviour ro be like the implementation of a timer with width as indicated. */
jamesadevine	0:e1a608bb55e8	6523	#define TIMER_BITMODE_BITMODE_Pos (0UL) /!< Position of BITMODE field. /
jamesadevine	0:e1a608bb55e8	6524	#define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /!< Bit mask of BITMODE field. /
jamesadevine	0:e1a608bb55e8	6525	#define TIMER_BITMODE_BITMODE_16Bit (0x00UL) /!< 16-bit timer behaviour. /
jamesadevine	0:e1a608bb55e8	6526	#define TIMER_BITMODE_BITMODE_08Bit (0x01UL) /!< 8-bit timer behaviour. /
jamesadevine	0:e1a608bb55e8	6527	#define TIMER_BITMODE_BITMODE_24Bit (0x02UL) /!< 24-bit timer behaviour. /
jamesadevine	0:e1a608bb55e8	6528	#define TIMER_BITMODE_BITMODE_32Bit (0x03UL) /!< 32-bit timer behaviour. /
jamesadevine	0:e1a608bb55e8	6529
jamesadevine	0:e1a608bb55e8	6530	/* Register: TIMER_PRESCALER */
jamesadevine	0:e1a608bb55e8	6531	/* Description: 4-bit prescaler to source clock frequency (max value 9). Source clock frequency is divided by 2^SCALE. */
jamesadevine	0:e1a608bb55e8	6532
jamesadevine	0:e1a608bb55e8	6533	/* Bits 3..0 : Timer PRESCALER value. Max value is 9. */
jamesadevine	0:e1a608bb55e8	6534	#define TIMER_PRESCALER_PRESCALER_Pos (0UL) /!< Position of PRESCALER field. /
jamesadevine	0:e1a608bb55e8	6535	#define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /!< Bit mask of PRESCALER field. /
jamesadevine	0:e1a608bb55e8	6536
jamesadevine	0:e1a608bb55e8	6537	/* Register: TIMER_POWER */
jamesadevine	0:e1a608bb55e8	6538	/* Description: Peripheral power control. */
jamesadevine	0:e1a608bb55e8	6539
jamesadevine	0:e1a608bb55e8	6540	/* Bit 0 : Peripheral power control. */
jamesadevine	0:e1a608bb55e8	6541	#define TIMER_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
jamesadevine	0:e1a608bb55e8	6542	#define TIMER_POWER_POWER_Msk (0x1UL << TIMER_POWER_POWER_Pos) /!< Bit mask of POWER field. /
jamesadevine	0:e1a608bb55e8	6543	#define TIMER_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
jamesadevine	0:e1a608bb55e8	6544	#define TIMER_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
jamesadevine	0:e1a608bb55e8	6545
jamesadevine	0:e1a608bb55e8	6546
jamesadevine	0:e1a608bb55e8	6547	/* Peripheral: TWI */
jamesadevine	0:e1a608bb55e8	6548	/* Description: Two-wire interface master 0. */
jamesadevine	0:e1a608bb55e8	6549
jamesadevine	0:e1a608bb55e8	6550	/* Register: TWI_SHORTS */
jamesadevine	0:e1a608bb55e8	6551	/* Description: Shortcuts for TWI. */
jamesadevine	0:e1a608bb55e8	6552
jamesadevine	0:e1a608bb55e8	6553	/* Bit 1 : Shortcut between BB event and the STOP task. */
jamesadevine	0:e1a608bb55e8	6554	#define TWI_SHORTS_BB_STOP_Pos (1UL) /!< Position of BB_STOP field. /
jamesadevine	0:e1a608bb55e8	6555	#define TWI_SHORTS_BB_STOP_Msk (0x1UL << TWI_SHORTS_BB_STOP_Pos) /!< Bit mask of BB_STOP field. /
jamesadevine	0:e1a608bb55e8	6556	#define TWI_SHORTS_BB_STOP_Disabled (0UL) /!< Shortcut disabled. /
jamesadevine	0:e1a608bb55e8	6557	#define TWI_SHORTS_BB_STOP_Enabled (1UL) /!< Shortcut enabled. /
jamesadevine	0:e1a608bb55e8	6558
jamesadevine	0:e1a608bb55e8	6559	/* Bit 0 : Shortcut between BB event and the SUSPEND task. */
jamesadevine	0:e1a608bb55e8	6560	#define TWI_SHORTS_BB_SUSPEND_Pos (0UL) /!< Position of BB_SUSPEND field. /
jamesadevine	0:e1a608bb55e8	6561	#define TWI_SHORTS_BB_SUSPEND_Msk (0x1UL << TWI_SHORTS_BB_SUSPEND_Pos) /!< Bit mask of BB_SUSPEND field. /
jamesadevine	0:e1a608bb55e8	6562	#define TWI_SHORTS_BB_SUSPEND_Disabled (0UL) /!< Shortcut disabled. /
jamesadevine	0:e1a608bb55e8	6563	#define TWI_SHORTS_BB_SUSPEND_Enabled (1UL) /!< Shortcut enabled. /
jamesadevine	0:e1a608bb55e8	6564
jamesadevine	0:e1a608bb55e8	6565	/* Register: TWI_INTENSET */
jamesadevine	0:e1a608bb55e8	6566	/* Description: Interrupt enable set register. */
jamesadevine	0:e1a608bb55e8	6567
jamesadevine	0:e1a608bb55e8	6568	/* Bit 18 : Enable interrupt on SUSPENDED event. */
jamesadevine	0:e1a608bb55e8	6569	#define TWI_INTENSET_SUSPENDED_Pos (18UL) /!< Position of SUSPENDED field. /
jamesadevine	0:e1a608bb55e8	6570	#define TWI_INTENSET_SUSPENDED_Msk (0x1UL << TWI_INTENSET_SUSPENDED_Pos) /!< Bit mask of SUSPENDED field. /
jamesadevine	0:e1a608bb55e8	6571	#define TWI_INTENSET_SUSPENDED_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	6572	#define TWI_INTENSET_SUSPENDED_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	6573	#define TWI_INTENSET_SUSPENDED_Set (1UL) /!< Enable interrupt on write. /
jamesadevine	0:e1a608bb55e8	6574
jamesadevine	0:e1a608bb55e8	6575	/* Bit 14 : Enable interrupt on BB event. */
jamesadevine	0:e1a608bb55e8	6576	#define TWI_INTENSET_BB_Pos (14UL) /!< Position of BB field. /
jamesadevine	0:e1a608bb55e8	6577	#define TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos) /!< Bit mask of BB field. /
jamesadevine	0:e1a608bb55e8	6578	#define TWI_INTENSET_BB_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	6579	#define TWI_INTENSET_BB_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	6580	#define TWI_INTENSET_BB_Set (1UL) /!< Enable interrupt on write. /
jamesadevine	0:e1a608bb55e8	6581
jamesadevine	0:e1a608bb55e8	6582	/* Bit 9 : Enable interrupt on ERROR event. */
jamesadevine	0:e1a608bb55e8	6583	#define TWI_INTENSET_ERROR_Pos (9UL) /!< Position of ERROR field. /
jamesadevine	0:e1a608bb55e8	6584	#define TWI_INTENSET_ERROR_Msk (0x1UL << TWI_INTENSET_ERROR_Pos) /!< Bit mask of ERROR field. /
jamesadevine	0:e1a608bb55e8	6585	#define TWI_INTENSET_ERROR_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	6586	#define TWI_INTENSET_ERROR_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	6587	#define TWI_INTENSET_ERROR_Set (1UL) /!< Enable interrupt on write. /
jamesadevine	0:e1a608bb55e8	6588
jamesadevine	0:e1a608bb55e8	6589	/* Bit 7 : Enable interrupt on TXDSENT event. */
jamesadevine	0:e1a608bb55e8	6590	#define TWI_INTENSET_TXDSENT_Pos (7UL) /!< Position of TXDSENT field. /
jamesadevine	0:e1a608bb55e8	6591	#define TWI_INTENSET_TXDSENT_Msk (0x1UL << TWI_INTENSET_TXDSENT_Pos) /!< Bit mask of TXDSENT field. /
jamesadevine	0:e1a608bb55e8	6592	#define TWI_INTENSET_TXDSENT_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	6593	#define TWI_INTENSET_TXDSENT_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	6594	#define TWI_INTENSET_TXDSENT_Set (1UL) /!< Enable interrupt on write. /
jamesadevine	0:e1a608bb55e8	6595
jamesadevine	0:e1a608bb55e8	6596	/* Bit 2 : Enable interrupt on READY event. */
jamesadevine	0:e1a608bb55e8	6597	#define TWI_INTENSET_RXDREADY_Pos (2UL) /!< Position of RXDREADY field. /
jamesadevine	0:e1a608bb55e8	6598	#define TWI_INTENSET_RXDREADY_Msk (0x1UL << TWI_INTENSET_RXDREADY_Pos) /!< Bit mask of RXDREADY field. /
jamesadevine	0:e1a608bb55e8	6599	#define TWI_INTENSET_RXDREADY_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	6600	#define TWI_INTENSET_RXDREADY_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	6601	#define TWI_INTENSET_RXDREADY_Set (1UL) /!< Enable interrupt on write. /
jamesadevine	0:e1a608bb55e8	6602
jamesadevine	0:e1a608bb55e8	6603	/* Bit 1 : Enable interrupt on STOPPED event. */
jamesadevine	0:e1a608bb55e8	6604	#define TWI_INTENSET_STOPPED_Pos (1UL) /!< Position of STOPPED field. /
jamesadevine	0:e1a608bb55e8	6605	#define TWI_INTENSET_STOPPED_Msk (0x1UL << TWI_INTENSET_STOPPED_Pos) /!< Bit mask of STOPPED field. /
jamesadevine	0:e1a608bb55e8	6606	#define TWI_INTENSET_STOPPED_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	6607	#define TWI_INTENSET_STOPPED_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	6608	#define TWI_INTENSET_STOPPED_Set (1UL) /!< Enable interrupt on write. /
jamesadevine	0:e1a608bb55e8	6609
jamesadevine	0:e1a608bb55e8	6610	/* Register: TWI_INTENCLR */
jamesadevine	0:e1a608bb55e8	6611	/* Description: Interrupt enable clear register. */
jamesadevine	0:e1a608bb55e8	6612
jamesadevine	0:e1a608bb55e8	6613	/* Bit 18 : Disable interrupt on SUSPENDED event. */
jamesadevine	0:e1a608bb55e8	6614	#define TWI_INTENCLR_SUSPENDED_Pos (18UL) /!< Position of SUSPENDED field. /
jamesadevine	0:e1a608bb55e8	6615	#define TWI_INTENCLR_SUSPENDED_Msk (0x1UL << TWI_INTENCLR_SUSPENDED_Pos) /!< Bit mask of SUSPENDED field. /
jamesadevine	0:e1a608bb55e8	6616	#define TWI_INTENCLR_SUSPENDED_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	6617	#define TWI_INTENCLR_SUSPENDED_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	6618	#define TWI_INTENCLR_SUSPENDED_Clear (1UL) /!< Disable interrupt on write. /
jamesadevine	0:e1a608bb55e8	6619
jamesadevine	0:e1a608bb55e8	6620	/* Bit 14 : Disable interrupt on BB event. */
jamesadevine	0:e1a608bb55e8	6621	#define TWI_INTENCLR_BB_Pos (14UL) /!< Position of BB field. /
jamesadevine	0:e1a608bb55e8	6622	#define TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos) /!< Bit mask of BB field. /
jamesadevine	0:e1a608bb55e8	6623	#define TWI_INTENCLR_BB_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	6624	#define TWI_INTENCLR_BB_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	6625	#define TWI_INTENCLR_BB_Clear (1UL) /!< Disable interrupt on write. /
jamesadevine	0:e1a608bb55e8	6626
jamesadevine	0:e1a608bb55e8	6627	/* Bit 9 : Disable interrupt on ERROR event. */
jamesadevine	0:e1a608bb55e8	6628	#define TWI_INTENCLR_ERROR_Pos (9UL) /!< Position of ERROR field. /
jamesadevine	0:e1a608bb55e8	6629	#define TWI_INTENCLR_ERROR_Msk (0x1UL << TWI_INTENCLR_ERROR_Pos) /!< Bit mask of ERROR field. /
jamesadevine	0:e1a608bb55e8	6630	#define TWI_INTENCLR_ERROR_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	6631	#define TWI_INTENCLR_ERROR_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	6632	#define TWI_INTENCLR_ERROR_Clear (1UL) /!< Disable interrupt on write. /
jamesadevine	0:e1a608bb55e8	6633
jamesadevine	0:e1a608bb55e8	6634	/* Bit 7 : Disable interrupt on TXDSENT event. */
jamesadevine	0:e1a608bb55e8	6635	#define TWI_INTENCLR_TXDSENT_Pos (7UL) /!< Position of TXDSENT field. /
jamesadevine	0:e1a608bb55e8	6636	#define TWI_INTENCLR_TXDSENT_Msk (0x1UL << TWI_INTENCLR_TXDSENT_Pos) /!< Bit mask of TXDSENT field. /
jamesadevine	0:e1a608bb55e8	6637	#define TWI_INTENCLR_TXDSENT_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	6638	#define TWI_INTENCLR_TXDSENT_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	6639	#define TWI_INTENCLR_TXDSENT_Clear (1UL) /!< Disable interrupt on write. /
jamesadevine	0:e1a608bb55e8	6640
jamesadevine	0:e1a608bb55e8	6641	/* Bit 2 : Disable interrupt on RXDREADY event. */
jamesadevine	0:e1a608bb55e8	6642	#define TWI_INTENCLR_RXDREADY_Pos (2UL) /!< Position of RXDREADY field. /
jamesadevine	0:e1a608bb55e8	6643	#define TWI_INTENCLR_RXDREADY_Msk (0x1UL << TWI_INTENCLR_RXDREADY_Pos) /!< Bit mask of RXDREADY field. /
jamesadevine	0:e1a608bb55e8	6644	#define TWI_INTENCLR_RXDREADY_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	6645	#define TWI_INTENCLR_RXDREADY_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	6646	#define TWI_INTENCLR_RXDREADY_Clear (1UL) /!< Disable interrupt on write. /
jamesadevine	0:e1a608bb55e8	6647
jamesadevine	0:e1a608bb55e8	6648	/* Bit 1 : Disable interrupt on STOPPED event. */
jamesadevine	0:e1a608bb55e8	6649	#define TWI_INTENCLR_STOPPED_Pos (1UL) /!< Position of STOPPED field. /
jamesadevine	0:e1a608bb55e8	6650	#define TWI_INTENCLR_STOPPED_Msk (0x1UL << TWI_INTENCLR_STOPPED_Pos) /!< Bit mask of STOPPED field. /
jamesadevine	0:e1a608bb55e8	6651	#define TWI_INTENCLR_STOPPED_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	6652	#define TWI_INTENCLR_STOPPED_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	6653	#define TWI_INTENCLR_STOPPED_Clear (1UL) /!< Disable interrupt on write. /
jamesadevine	0:e1a608bb55e8	6654
jamesadevine	0:e1a608bb55e8	6655	/* Register: TWI_ERRORSRC */
jamesadevine	0:e1a608bb55e8	6656	/* Description: Two-wire error source. Write error field to 1 to clear error. */
jamesadevine	0:e1a608bb55e8	6657
jamesadevine	0:e1a608bb55e8	6658	/* Bit 2 : NACK received after sending a data byte. */
jamesadevine	0:e1a608bb55e8	6659	#define TWI_ERRORSRC_DNACK_Pos (2UL) /!< Position of DNACK field. /
jamesadevine	0:e1a608bb55e8	6660	#define TWI_ERRORSRC_DNACK_Msk (0x1UL << TWI_ERRORSRC_DNACK_Pos) /!< Bit mask of DNACK field. /
jamesadevine	0:e1a608bb55e8	6661	#define TWI_ERRORSRC_DNACK_NotPresent (0UL) /!< Error not present. /
jamesadevine	0:e1a608bb55e8	6662	#define TWI_ERRORSRC_DNACK_Present (1UL) /!< Error present. /
jamesadevine	0:e1a608bb55e8	6663	#define TWI_ERRORSRC_DNACK_Clear (1UL) /!< Clear error on write. /
jamesadevine	0:e1a608bb55e8	6664
jamesadevine	0:e1a608bb55e8	6665	/* Bit 1 : NACK received after sending the address. */
jamesadevine	0:e1a608bb55e8	6666	#define TWI_ERRORSRC_ANACK_Pos (1UL) /!< Position of ANACK field. /
jamesadevine	0:e1a608bb55e8	6667	#define TWI_ERRORSRC_ANACK_Msk (0x1UL << TWI_ERRORSRC_ANACK_Pos) /!< Bit mask of ANACK field. /
jamesadevine	0:e1a608bb55e8	6668	#define TWI_ERRORSRC_ANACK_NotPresent (0UL) /!< Error not present. /
jamesadevine	0:e1a608bb55e8	6669	#define TWI_ERRORSRC_ANACK_Present (1UL) /!< Error present. /
jamesadevine	0:e1a608bb55e8	6670	#define TWI_ERRORSRC_ANACK_Clear (1UL) /!< Clear error on write. /
jamesadevine	0:e1a608bb55e8	6671
jamesadevine	0:e1a608bb55e8	6672	/* Register: TWI_ENABLE */
jamesadevine	0:e1a608bb55e8	6673	/* Description: Enable two-wire master. */
jamesadevine	0:e1a608bb55e8	6674
jamesadevine	0:e1a608bb55e8	6675	/* Bits 2..0 : Enable or disable W2M */
jamesadevine	0:e1a608bb55e8	6676	#define TWI_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
jamesadevine	0:e1a608bb55e8	6677	#define TWI_ENABLE_ENABLE_Msk (0x7UL << TWI_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
jamesadevine	0:e1a608bb55e8	6678	#define TWI_ENABLE_ENABLE_Disabled (0x00UL) /!< Disabled. /
jamesadevine	0:e1a608bb55e8	6679	#define TWI_ENABLE_ENABLE_Enabled (0x05UL) /!< Enabled. /
jamesadevine	0:e1a608bb55e8	6680
jamesadevine	0:e1a608bb55e8	6681	/* Register: TWI_RXD */
jamesadevine	0:e1a608bb55e8	6682	/* Description: RX data register. */
jamesadevine	0:e1a608bb55e8	6683
jamesadevine	0:e1a608bb55e8	6684	/* Bits 7..0 : RX data from last transfer. */
jamesadevine	0:e1a608bb55e8	6685	#define TWI_RXD_RXD_Pos (0UL) /!< Position of RXD field. /
jamesadevine	0:e1a608bb55e8	6686	#define TWI_RXD_RXD_Msk (0xFFUL << TWI_RXD_RXD_Pos) /!< Bit mask of RXD field. /
jamesadevine	0:e1a608bb55e8	6687
jamesadevine	0:e1a608bb55e8	6688	/* Register: TWI_TXD */
jamesadevine	0:e1a608bb55e8	6689	/* Description: TX data register. */
jamesadevine	0:e1a608bb55e8	6690
jamesadevine	0:e1a608bb55e8	6691	/* Bits 7..0 : TX data for next transfer. */
jamesadevine	0:e1a608bb55e8	6692	#define TWI_TXD_TXD_Pos (0UL) /!< Position of TXD field. /
jamesadevine	0:e1a608bb55e8	6693	#define TWI_TXD_TXD_Msk (0xFFUL << TWI_TXD_TXD_Pos) /!< Bit mask of TXD field. /
jamesadevine	0:e1a608bb55e8	6694
jamesadevine	0:e1a608bb55e8	6695	/* Register: TWI_FREQUENCY */
jamesadevine	0:e1a608bb55e8	6696	/* Description: Two-wire frequency. */
jamesadevine	0:e1a608bb55e8	6697
jamesadevine	0:e1a608bb55e8	6698	/* Bits 31..0 : Two-wire master clock frequency. */
jamesadevine	0:e1a608bb55e8	6699	#define TWI_FREQUENCY_FREQUENCY_Pos (0UL) /!< Position of FREQUENCY field. /
jamesadevine	0:e1a608bb55e8	6700	#define TWI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWI_FREQUENCY_FREQUENCY_Pos) /!< Bit mask of FREQUENCY field. /
jamesadevine	0:e1a608bb55e8	6701	#define TWI_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /!< 100 kbps. /
jamesadevine	0:e1a608bb55e8	6702	#define TWI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /!< 250 kbps. /
jamesadevine	0:e1a608bb55e8	6703	#define TWI_FREQUENCY_FREQUENCY_K400 (0x06680000UL) /!< 400 kbps. /
jamesadevine	0:e1a608bb55e8	6704
jamesadevine	0:e1a608bb55e8	6705	/* Register: TWI_ADDRESS */
jamesadevine	0:e1a608bb55e8	6706	/* Description: Address used in the two-wire transfer. */
jamesadevine	0:e1a608bb55e8	6707
jamesadevine	0:e1a608bb55e8	6708	/* Bits 6..0 : Two-wire address. */
jamesadevine	0:e1a608bb55e8	6709	#define TWI_ADDRESS_ADDRESS_Pos (0UL) /!< Position of ADDRESS field. /
jamesadevine	0:e1a608bb55e8	6710	#define TWI_ADDRESS_ADDRESS_Msk (0x7FUL << TWI_ADDRESS_ADDRESS_Pos) /!< Bit mask of ADDRESS field. /
jamesadevine	0:e1a608bb55e8	6711
jamesadevine	0:e1a608bb55e8	6712	/* Register: TWI_POWER */
jamesadevine	0:e1a608bb55e8	6713	/* Description: Peripheral power control. */
jamesadevine	0:e1a608bb55e8	6714
jamesadevine	0:e1a608bb55e8	6715	/* Bit 0 : Peripheral power control. */
jamesadevine	0:e1a608bb55e8	6716	#define TWI_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
jamesadevine	0:e1a608bb55e8	6717	#define TWI_POWER_POWER_Msk (0x1UL << TWI_POWER_POWER_Pos) /!< Bit mask of POWER field. /
jamesadevine	0:e1a608bb55e8	6718	#define TWI_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
jamesadevine	0:e1a608bb55e8	6719	#define TWI_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
jamesadevine	0:e1a608bb55e8	6720
jamesadevine	0:e1a608bb55e8	6721
jamesadevine	0:e1a608bb55e8	6722	/* Peripheral: UART */
jamesadevine	0:e1a608bb55e8	6723	/* Description: Universal Asynchronous Receiver/Transmitter. */
jamesadevine	0:e1a608bb55e8	6724
jamesadevine	0:e1a608bb55e8	6725	/* Register: UART_SHORTS */
jamesadevine	0:e1a608bb55e8	6726	/* Description: Shortcuts for UART. */
jamesadevine	0:e1a608bb55e8	6727
jamesadevine	0:e1a608bb55e8	6728	/* Bit 4 : Shortcut between NCTS event and the STOPRX task. */
jamesadevine	0:e1a608bb55e8	6729	#define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /!< Position of NCTS_STOPRX field. /
jamesadevine	0:e1a608bb55e8	6730	#define UART_SHORTS_NCTS_STOPRX_Msk (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos) /!< Bit mask of NCTS_STOPRX field. /
jamesadevine	0:e1a608bb55e8	6731	#define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /!< Shortcut disabled. /
jamesadevine	0:e1a608bb55e8	6732	#define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /!< Shortcut enabled. /
jamesadevine	0:e1a608bb55e8	6733
jamesadevine	0:e1a608bb55e8	6734	/* Bit 3 : Shortcut between CTS event and the STARTRX task. */
jamesadevine	0:e1a608bb55e8	6735	#define UART_SHORTS_CTS_STARTRX_Pos (3UL) /!< Position of CTS_STARTRX field. /
jamesadevine	0:e1a608bb55e8	6736	#define UART_SHORTS_CTS_STARTRX_Msk (0x1UL << UART_SHORTS_CTS_STARTRX_Pos) /!< Bit mask of CTS_STARTRX field. /
jamesadevine	0:e1a608bb55e8	6737	#define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /!< Shortcut disabled. /
jamesadevine	0:e1a608bb55e8	6738	#define UART_SHORTS_CTS_STARTRX_Enabled (1UL) /!< Shortcut enabled. /
jamesadevine	0:e1a608bb55e8	6739
jamesadevine	0:e1a608bb55e8	6740	/* Register: UART_INTENSET */
jamesadevine	0:e1a608bb55e8	6741	/* Description: Interrupt enable set register. */
jamesadevine	0:e1a608bb55e8	6742
jamesadevine	0:e1a608bb55e8	6743	/* Bit 17 : Enable interrupt on RXTO event. */
jamesadevine	0:e1a608bb55e8	6744	#define UART_INTENSET_RXTO_Pos (17UL) /!< Position of RXTO field. /
jamesadevine	0:e1a608bb55e8	6745	#define UART_INTENSET_RXTO_Msk (0x1UL << UART_INTENSET_RXTO_Pos) /!< Bit mask of RXTO field. /
jamesadevine	0:e1a608bb55e8	6746	#define UART_INTENSET_RXTO_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	6747	#define UART_INTENSET_RXTO_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	6748	#define UART_INTENSET_RXTO_Set (1UL) /!< Enable interrupt on write. /
jamesadevine	0:e1a608bb55e8	6749
jamesadevine	0:e1a608bb55e8	6750	/* Bit 9 : Enable interrupt on ERROR event. */
jamesadevine	0:e1a608bb55e8	6751	#define UART_INTENSET_ERROR_Pos (9UL) /!< Position of ERROR field. /
jamesadevine	0:e1a608bb55e8	6752	#define UART_INTENSET_ERROR_Msk (0x1UL << UART_INTENSET_ERROR_Pos) /!< Bit mask of ERROR field. /
jamesadevine	0:e1a608bb55e8	6753	#define UART_INTENSET_ERROR_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	6754	#define UART_INTENSET_ERROR_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	6755	#define UART_INTENSET_ERROR_Set (1UL) /!< Enable interrupt on write. /
jamesadevine	0:e1a608bb55e8	6756
jamesadevine	0:e1a608bb55e8	6757	/* Bit 7 : Enable interrupt on TXRDY event. */
jamesadevine	0:e1a608bb55e8	6758	#define UART_INTENSET_TXDRDY_Pos (7UL) /!< Position of TXDRDY field. /
jamesadevine	0:e1a608bb55e8	6759	#define UART_INTENSET_TXDRDY_Msk (0x1UL << UART_INTENSET_TXDRDY_Pos) /!< Bit mask of TXDRDY field. /
jamesadevine	0:e1a608bb55e8	6760	#define UART_INTENSET_TXDRDY_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	6761	#define UART_INTENSET_TXDRDY_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	6762	#define UART_INTENSET_TXDRDY_Set (1UL) /!< Enable interrupt on write. /
jamesadevine	0:e1a608bb55e8	6763
jamesadevine	0:e1a608bb55e8	6764	/* Bit 2 : Enable interrupt on RXRDY event. */
jamesadevine	0:e1a608bb55e8	6765	#define UART_INTENSET_RXDRDY_Pos (2UL) /!< Position of RXDRDY field. /
jamesadevine	0:e1a608bb55e8	6766	#define UART_INTENSET_RXDRDY_Msk (0x1UL << UART_INTENSET_RXDRDY_Pos) /!< Bit mask of RXDRDY field. /
jamesadevine	0:e1a608bb55e8	6767	#define UART_INTENSET_RXDRDY_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	6768	#define UART_INTENSET_RXDRDY_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	6769	#define UART_INTENSET_RXDRDY_Set (1UL) /!< Enable interrupt on write. /
jamesadevine	0:e1a608bb55e8	6770
jamesadevine	0:e1a608bb55e8	6771	/* Bit 1 : Enable interrupt on NCTS event. */
jamesadevine	0:e1a608bb55e8	6772	#define UART_INTENSET_NCTS_Pos (1UL) /!< Position of NCTS field. /
jamesadevine	0:e1a608bb55e8	6773	#define UART_INTENSET_NCTS_Msk (0x1UL << UART_INTENSET_NCTS_Pos) /!< Bit mask of NCTS field. /
jamesadevine	0:e1a608bb55e8	6774	#define UART_INTENSET_NCTS_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	6775	#define UART_INTENSET_NCTS_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	6776	#define UART_INTENSET_NCTS_Set (1UL) /!< Enable interrupt on write. /
jamesadevine	0:e1a608bb55e8	6777
jamesadevine	0:e1a608bb55e8	6778	/* Bit 0 : Enable interrupt on CTS event. */
jamesadevine	0:e1a608bb55e8	6779	#define UART_INTENSET_CTS_Pos (0UL) /!< Position of CTS field. /
jamesadevine	0:e1a608bb55e8	6780	#define UART_INTENSET_CTS_Msk (0x1UL << UART_INTENSET_CTS_Pos) /!< Bit mask of CTS field. /
jamesadevine	0:e1a608bb55e8	6781	#define UART_INTENSET_CTS_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	6782	#define UART_INTENSET_CTS_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	6783	#define UART_INTENSET_CTS_Set (1UL) /!< Enable interrupt on write. /
jamesadevine	0:e1a608bb55e8	6784
jamesadevine	0:e1a608bb55e8	6785	/* Register: UART_INTENCLR */
jamesadevine	0:e1a608bb55e8	6786	/* Description: Interrupt enable clear register. */
jamesadevine	0:e1a608bb55e8	6787
jamesadevine	0:e1a608bb55e8	6788	/* Bit 17 : Disable interrupt on RXTO event. */
jamesadevine	0:e1a608bb55e8	6789	#define UART_INTENCLR_RXTO_Pos (17UL) /!< Position of RXTO field. /
jamesadevine	0:e1a608bb55e8	6790	#define UART_INTENCLR_RXTO_Msk (0x1UL << UART_INTENCLR_RXTO_Pos) /!< Bit mask of RXTO field. /
jamesadevine	0:e1a608bb55e8	6791	#define UART_INTENCLR_RXTO_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	6792	#define UART_INTENCLR_RXTO_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	6793	#define UART_INTENCLR_RXTO_Clear (1UL) /!< Disable interrupt on write. /
jamesadevine	0:e1a608bb55e8	6794
jamesadevine	0:e1a608bb55e8	6795	/* Bit 9 : Disable interrupt on ERROR event. */
jamesadevine	0:e1a608bb55e8	6796	#define UART_INTENCLR_ERROR_Pos (9UL) /!< Position of ERROR field. /
jamesadevine	0:e1a608bb55e8	6797	#define UART_INTENCLR_ERROR_Msk (0x1UL << UART_INTENCLR_ERROR_Pos) /!< Bit mask of ERROR field. /
jamesadevine	0:e1a608bb55e8	6798	#define UART_INTENCLR_ERROR_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	6799	#define UART_INTENCLR_ERROR_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	6800	#define UART_INTENCLR_ERROR_Clear (1UL) /!< Disable interrupt on write. /
jamesadevine	0:e1a608bb55e8	6801
jamesadevine	0:e1a608bb55e8	6802	/* Bit 7 : Disable interrupt on TXRDY event. */
jamesadevine	0:e1a608bb55e8	6803	#define UART_INTENCLR_TXDRDY_Pos (7UL) /!< Position of TXDRDY field. /
jamesadevine	0:e1a608bb55e8	6804	#define UART_INTENCLR_TXDRDY_Msk (0x1UL << UART_INTENCLR_TXDRDY_Pos) /!< Bit mask of TXDRDY field. /
jamesadevine	0:e1a608bb55e8	6805	#define UART_INTENCLR_TXDRDY_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	6806	#define UART_INTENCLR_TXDRDY_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	6807	#define UART_INTENCLR_TXDRDY_Clear (1UL) /!< Disable interrupt on write. /
jamesadevine	0:e1a608bb55e8	6808
jamesadevine	0:e1a608bb55e8	6809	/* Bit 2 : Disable interrupt on RXRDY event. */
jamesadevine	0:e1a608bb55e8	6810	#define UART_INTENCLR_RXDRDY_Pos (2UL) /!< Position of RXDRDY field. /
jamesadevine	0:e1a608bb55e8	6811	#define UART_INTENCLR_RXDRDY_Msk (0x1UL << UART_INTENCLR_RXDRDY_Pos) /!< Bit mask of RXDRDY field. /
jamesadevine	0:e1a608bb55e8	6812	#define UART_INTENCLR_RXDRDY_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	6813	#define UART_INTENCLR_RXDRDY_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	6814	#define UART_INTENCLR_RXDRDY_Clear (1UL) /!< Disable interrupt on write. /
jamesadevine	0:e1a608bb55e8	6815
jamesadevine	0:e1a608bb55e8	6816	/* Bit 1 : Disable interrupt on NCTS event. */
jamesadevine	0:e1a608bb55e8	6817	#define UART_INTENCLR_NCTS_Pos (1UL) /!< Position of NCTS field. /
jamesadevine	0:e1a608bb55e8	6818	#define UART_INTENCLR_NCTS_Msk (0x1UL << UART_INTENCLR_NCTS_Pos) /!< Bit mask of NCTS field. /
jamesadevine	0:e1a608bb55e8	6819	#define UART_INTENCLR_NCTS_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	6820	#define UART_INTENCLR_NCTS_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	6821	#define UART_INTENCLR_NCTS_Clear (1UL) /!< Disable interrupt on write. /
jamesadevine	0:e1a608bb55e8	6822
jamesadevine	0:e1a608bb55e8	6823	/* Bit 0 : Disable interrupt on CTS event. */
jamesadevine	0:e1a608bb55e8	6824	#define UART_INTENCLR_CTS_Pos (0UL) /!< Position of CTS field. /
jamesadevine	0:e1a608bb55e8	6825	#define UART_INTENCLR_CTS_Msk (0x1UL << UART_INTENCLR_CTS_Pos) /!< Bit mask of CTS field. /
jamesadevine	0:e1a608bb55e8	6826	#define UART_INTENCLR_CTS_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	6827	#define UART_INTENCLR_CTS_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	6828	#define UART_INTENCLR_CTS_Clear (1UL) /!< Disable interrupt on write. /
jamesadevine	0:e1a608bb55e8	6829
jamesadevine	0:e1a608bb55e8	6830	/* Register: UART_ERRORSRC */
jamesadevine	0:e1a608bb55e8	6831	/* Description: Error source. Write error field to 1 to clear error. */
jamesadevine	0:e1a608bb55e8	6832
jamesadevine	0:e1a608bb55e8	6833	/* Bit 3 : The serial data input is '0' for longer than the length of a data frame. */
jamesadevine	0:e1a608bb55e8	6834	#define UART_ERRORSRC_BREAK_Pos (3UL) /!< Position of BREAK field. /
jamesadevine	0:e1a608bb55e8	6835	#define UART_ERRORSRC_BREAK_Msk (0x1UL << UART_ERRORSRC_BREAK_Pos) /!< Bit mask of BREAK field. /
jamesadevine	0:e1a608bb55e8	6836	#define UART_ERRORSRC_BREAK_NotPresent (0UL) /!< Error not present. /
jamesadevine	0:e1a608bb55e8	6837	#define UART_ERRORSRC_BREAK_Present (1UL) /!< Error present. /
jamesadevine	0:e1a608bb55e8	6838	#define UART_ERRORSRC_BREAK_Clear (1UL) /!< Clear error on write. /
jamesadevine	0:e1a608bb55e8	6839
jamesadevine	0:e1a608bb55e8	6840	/* Bit 2 : A valid stop bit is not detected on the serial data input after all bits in a character have been received. */
jamesadevine	0:e1a608bb55e8	6841	#define UART_ERRORSRC_FRAMING_Pos (2UL) /!< Position of FRAMING field. /
jamesadevine	0:e1a608bb55e8	6842	#define UART_ERRORSRC_FRAMING_Msk (0x1UL << UART_ERRORSRC_FRAMING_Pos) /!< Bit mask of FRAMING field. /
jamesadevine	0:e1a608bb55e8	6843	#define UART_ERRORSRC_FRAMING_NotPresent (0UL) /!< Error not present. /
jamesadevine	0:e1a608bb55e8	6844	#define UART_ERRORSRC_FRAMING_Present (1UL) /!< Error present. /
jamesadevine	0:e1a608bb55e8	6845	#define UART_ERRORSRC_FRAMING_Clear (1UL) /!< Clear error on write. /
jamesadevine	0:e1a608bb55e8	6846
jamesadevine	0:e1a608bb55e8	6847	/* Bit 1 : A character with bad parity is received. Only checked if HW parity control is enabled. */
jamesadevine	0:e1a608bb55e8	6848	#define UART_ERRORSRC_PARITY_Pos (1UL) /!< Position of PARITY field. /
jamesadevine	0:e1a608bb55e8	6849	#define UART_ERRORSRC_PARITY_Msk (0x1UL << UART_ERRORSRC_PARITY_Pos) /!< Bit mask of PARITY field. /
jamesadevine	0:e1a608bb55e8	6850	#define UART_ERRORSRC_PARITY_NotPresent (0UL) /!< Error not present. /
jamesadevine	0:e1a608bb55e8	6851	#define UART_ERRORSRC_PARITY_Present (1UL) /!< Error present. /
jamesadevine	0:e1a608bb55e8	6852	#define UART_ERRORSRC_PARITY_Clear (1UL) /!< Clear error on write. /
jamesadevine	0:e1a608bb55e8	6853
jamesadevine	0:e1a608bb55e8	6854	/* Bit 0 : A start bit is received while the previous data still lies in RXD. (Data loss). */
jamesadevine	0:e1a608bb55e8	6855	#define UART_ERRORSRC_OVERRUN_Pos (0UL) /!< Position of OVERRUN field. /
jamesadevine	0:e1a608bb55e8	6856	#define UART_ERRORSRC_OVERRUN_Msk (0x1UL << UART_ERRORSRC_OVERRUN_Pos) /!< Bit mask of OVERRUN field. /
jamesadevine	0:e1a608bb55e8	6857	#define UART_ERRORSRC_OVERRUN_NotPresent (0UL) /!< Error not present. /
jamesadevine	0:e1a608bb55e8	6858	#define UART_ERRORSRC_OVERRUN_Present (1UL) /!< Error present. /
jamesadevine	0:e1a608bb55e8	6859	#define UART_ERRORSRC_OVERRUN_Clear (1UL) /!< Clear error on write. /
jamesadevine	0:e1a608bb55e8	6860
jamesadevine	0:e1a608bb55e8	6861	/* Register: UART_ENABLE */
jamesadevine	0:e1a608bb55e8	6862	/* Description: Enable UART and acquire IOs. */
jamesadevine	0:e1a608bb55e8	6863
jamesadevine	0:e1a608bb55e8	6864	/* Bits 2..0 : Enable or disable UART and acquire IOs. */
jamesadevine	0:e1a608bb55e8	6865	#define UART_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
jamesadevine	0:e1a608bb55e8	6866	#define UART_ENABLE_ENABLE_Msk (0x7UL << UART_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
jamesadevine	0:e1a608bb55e8	6867	#define UART_ENABLE_ENABLE_Disabled (0x00UL) /!< UART disabled. /
jamesadevine	0:e1a608bb55e8	6868	#define UART_ENABLE_ENABLE_Enabled (0x04UL) /!< UART enabled. /
jamesadevine	0:e1a608bb55e8	6869
jamesadevine	0:e1a608bb55e8	6870	/* Register: UART_RXD */
jamesadevine	0:e1a608bb55e8	6871	/* Description: RXD register. On read action the buffer pointer is displaced. Once read the character is consumed. If read when no character available, the UART will stop working. */
jamesadevine	0:e1a608bb55e8	6872
jamesadevine	0:e1a608bb55e8	6873	/* Bits 7..0 : RX data from previous transfer. Double buffered. */
jamesadevine	0:e1a608bb55e8	6874	#define UART_RXD_RXD_Pos (0UL) /!< Position of RXD field. /
jamesadevine	0:e1a608bb55e8	6875	#define UART_RXD_RXD_Msk (0xFFUL << UART_RXD_RXD_Pos) /!< Bit mask of RXD field. /
jamesadevine	0:e1a608bb55e8	6876
jamesadevine	0:e1a608bb55e8	6877	/* Register: UART_TXD */
jamesadevine	0:e1a608bb55e8	6878	/* Description: TXD register. */
jamesadevine	0:e1a608bb55e8	6879
jamesadevine	0:e1a608bb55e8	6880	/* Bits 7..0 : TX data for transfer. */
jamesadevine	0:e1a608bb55e8	6881	#define UART_TXD_TXD_Pos (0UL) /!< Position of TXD field. /
jamesadevine	0:e1a608bb55e8	6882	#define UART_TXD_TXD_Msk (0xFFUL << UART_TXD_TXD_Pos) /!< Bit mask of TXD field. /
jamesadevine	0:e1a608bb55e8	6883
jamesadevine	0:e1a608bb55e8	6884	/* Register: UART_BAUDRATE */
jamesadevine	0:e1a608bb55e8	6885	/* Description: UART Baudrate. */
jamesadevine	0:e1a608bb55e8	6886
jamesadevine	0:e1a608bb55e8	6887	/* Bits 31..0 : UART baudrate. */
jamesadevine	0:e1a608bb55e8	6888	#define UART_BAUDRATE_BAUDRATE_Pos (0UL) /!< Position of BAUDRATE field. /
jamesadevine	0:e1a608bb55e8	6889	#define UART_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UART_BAUDRATE_BAUDRATE_Pos) /!< Bit mask of BAUDRATE field. /
jamesadevine	0:e1a608bb55e8	6890	#define UART_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /!< 1200 baud. /
jamesadevine	0:e1a608bb55e8	6891	#define UART_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /!< 2400 baud. /
jamesadevine	0:e1a608bb55e8	6892	#define UART_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /!< 4800 baud. /
jamesadevine	0:e1a608bb55e8	6893	#define UART_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /!< 9600 baud. /
jamesadevine	0:e1a608bb55e8	6894	#define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL) /!< 14400 baud. /
jamesadevine	0:e1a608bb55e8	6895	#define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /!< 19200 baud. /
jamesadevine	0:e1a608bb55e8	6896	#define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL) /!< 28800 baud. /
jamesadevine	0:e1a608bb55e8	6897	#define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL) /!< 38400 baud. /
jamesadevine	0:e1a608bb55e8	6898	#define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL) /!< 57600 baud. /
jamesadevine	0:e1a608bb55e8	6899	#define UART_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /!< 76800 baud. /
jamesadevine	0:e1a608bb55e8	6900	#define UART_BAUDRATE_BAUDRATE_Baud115200 (0x01D7E000UL) /!< 115200 baud. /
jamesadevine	0:e1a608bb55e8	6901	#define UART_BAUDRATE_BAUDRATE_Baud230400 (0x03AFB000UL) /!< 230400 baud. /
jamesadevine	0:e1a608bb55e8	6902	#define UART_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /!< 250000 baud. /
jamesadevine	0:e1a608bb55e8	6903	#define UART_BAUDRATE_BAUDRATE_Baud460800 (0x075F7000UL) /!< 460800 baud. /
jamesadevine	0:e1a608bb55e8	6904	#define UART_BAUDRATE_BAUDRATE_Baud921600 (0x0EBEDFA4UL) /!< 921600 baud. /
jamesadevine	0:e1a608bb55e8	6905	#define UART_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /!< 1M baud. /
jamesadevine	0:e1a608bb55e8	6906
jamesadevine	0:e1a608bb55e8	6907	/* Register: UART_CONFIG */
jamesadevine	0:e1a608bb55e8	6908	/* Description: Configuration of parity and hardware flow control register. */
jamesadevine	0:e1a608bb55e8	6909
jamesadevine	0:e1a608bb55e8	6910	/* Bits 3..1 : Include parity bit. */
jamesadevine	0:e1a608bb55e8	6911	#define UART_CONFIG_PARITY_Pos (1UL) /!< Position of PARITY field. /
jamesadevine	0:e1a608bb55e8	6912	#define UART_CONFIG_PARITY_Msk (0x7UL << UART_CONFIG_PARITY_Pos) /!< Bit mask of PARITY field. /
jamesadevine	0:e1a608bb55e8	6913	#define UART_CONFIG_PARITY_Excluded (0UL) /!< Parity bit excluded. /
jamesadevine	0:e1a608bb55e8	6914	#define UART_CONFIG_PARITY_Included (7UL) /!< Parity bit included. /
jamesadevine	0:e1a608bb55e8	6915
jamesadevine	0:e1a608bb55e8	6916	/* Bit 0 : Hardware flow control. */
jamesadevine	0:e1a608bb55e8	6917	#define UART_CONFIG_HWFC_Pos (0UL) /!< Position of HWFC field. /
jamesadevine	0:e1a608bb55e8	6918	#define UART_CONFIG_HWFC_Msk (0x1UL << UART_CONFIG_HWFC_Pos) /!< Bit mask of HWFC field. /
jamesadevine	0:e1a608bb55e8	6919	#define UART_CONFIG_HWFC_Disabled (0UL) /!< Hardware flow control disabled. /
jamesadevine	0:e1a608bb55e8	6920	#define UART_CONFIG_HWFC_Enabled (1UL) /!< Hardware flow control enabled. /
jamesadevine	0:e1a608bb55e8	6921
jamesadevine	0:e1a608bb55e8	6922	/* Register: UART_POWER */
jamesadevine	0:e1a608bb55e8	6923	/* Description: Peripheral power control. */
jamesadevine	0:e1a608bb55e8	6924
jamesadevine	0:e1a608bb55e8	6925	/* Bit 0 : Peripheral power control. */
jamesadevine	0:e1a608bb55e8	6926	#define UART_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
jamesadevine	0:e1a608bb55e8	6927	#define UART_POWER_POWER_Msk (0x1UL << UART_POWER_POWER_Pos) /!< Bit mask of POWER field. /
jamesadevine	0:e1a608bb55e8	6928	#define UART_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
jamesadevine	0:e1a608bb55e8	6929	#define UART_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
jamesadevine	0:e1a608bb55e8	6930
jamesadevine	0:e1a608bb55e8	6931
jamesadevine	0:e1a608bb55e8	6932	/* Peripheral: UICR */
jamesadevine	0:e1a608bb55e8	6933	/* Description: User Information Configuration. */
jamesadevine	0:e1a608bb55e8	6934
jamesadevine	0:e1a608bb55e8	6935	/* Register: UICR_RBPCONF */
jamesadevine	0:e1a608bb55e8	6936	/* Description: Readback protection configuration. */
jamesadevine	0:e1a608bb55e8	6937
jamesadevine	0:e1a608bb55e8	6938	/* Bits 15..8 : Readback protect all code in the device. */
jamesadevine	0:e1a608bb55e8	6939	#define UICR_RBPCONF_PALL_Pos (8UL) /!< Position of PALL field. /
jamesadevine	0:e1a608bb55e8	6940	#define UICR_RBPCONF_PALL_Msk (0xFFUL << UICR_RBPCONF_PALL_Pos) /!< Bit mask of PALL field. /
jamesadevine	0:e1a608bb55e8	6941	#define UICR_RBPCONF_PALL_Disabled (0xFFUL) /!< Disabled. /
jamesadevine	0:e1a608bb55e8	6942	#define UICR_RBPCONF_PALL_Enabled (0x00UL) /!< Enabled. /
jamesadevine	0:e1a608bb55e8	6943
jamesadevine	0:e1a608bb55e8	6944	/* Bits 7..0 : Readback protect region 0. Will be ignored if pre-programmed factory code is present on the chip. */
jamesadevine	0:e1a608bb55e8	6945	#define UICR_RBPCONF_PR0_Pos (0UL) /!< Position of PR0 field. /
jamesadevine	0:e1a608bb55e8	6946	#define UICR_RBPCONF_PR0_Msk (0xFFUL << UICR_RBPCONF_PR0_Pos) /!< Bit mask of PR0 field. /
jamesadevine	0:e1a608bb55e8	6947	#define UICR_RBPCONF_PR0_Disabled (0xFFUL) /!< Disabled. /
jamesadevine	0:e1a608bb55e8	6948	#define UICR_RBPCONF_PR0_Enabled (0x00UL) /!< Enabled. /
jamesadevine	0:e1a608bb55e8	6949
jamesadevine	0:e1a608bb55e8	6950	/* Register: UICR_XTALFREQ */
jamesadevine	0:e1a608bb55e8	6951	/* Description: Reset value for CLOCK XTALFREQ register. */
jamesadevine	0:e1a608bb55e8	6952
jamesadevine	0:e1a608bb55e8	6953	/* Bits 7..0 : Reset value for CLOCK XTALFREQ register. */
jamesadevine	0:e1a608bb55e8	6954	#define UICR_XTALFREQ_XTALFREQ_Pos (0UL) /!< Position of XTALFREQ field. /
jamesadevine	0:e1a608bb55e8	6955	#define UICR_XTALFREQ_XTALFREQ_Msk (0xFFUL << UICR_XTALFREQ_XTALFREQ_Pos) /!< Bit mask of XTALFREQ field. /
jamesadevine	0:e1a608bb55e8	6956	#define UICR_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /!< 16MHz Xtal is used. /
jamesadevine	0:e1a608bb55e8	6957	#define UICR_XTALFREQ_XTALFREQ_32MHz (0x00UL) /!< 32MHz Xtal is used. /
jamesadevine	0:e1a608bb55e8	6958
jamesadevine	0:e1a608bb55e8	6959	/* Register: UICR_FWID */
jamesadevine	0:e1a608bb55e8	6960	/* Description: Firmware ID. */
jamesadevine	0:e1a608bb55e8	6961
jamesadevine	0:e1a608bb55e8	6962	/* Bits 15..0 : Identification number for the firmware loaded into the chip. */
jamesadevine	0:e1a608bb55e8	6963	#define UICR_FWID_FWID_Pos (0UL) /!< Position of FWID field. /
jamesadevine	0:e1a608bb55e8	6964	#define UICR_FWID_FWID_Msk (0xFFFFUL << UICR_FWID_FWID_Pos) /!< Bit mask of FWID field. /
jamesadevine	0:e1a608bb55e8	6965
jamesadevine	0:e1a608bb55e8	6966
jamesadevine	0:e1a608bb55e8	6967	/* Peripheral: WDT */
jamesadevine	0:e1a608bb55e8	6968	/* Description: Watchdog Timer. */
jamesadevine	0:e1a608bb55e8	6969
jamesadevine	0:e1a608bb55e8	6970	/* Register: WDT_INTENSET */
jamesadevine	0:e1a608bb55e8	6971	/* Description: Interrupt enable set register. */
jamesadevine	0:e1a608bb55e8	6972
jamesadevine	0:e1a608bb55e8	6973	/* Bit 0 : Enable interrupt on TIMEOUT event. */
jamesadevine	0:e1a608bb55e8	6974	#define WDT_INTENSET_TIMEOUT_Pos (0UL) /!< Position of TIMEOUT field. /
jamesadevine	0:e1a608bb55e8	6975	#define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /!< Bit mask of TIMEOUT field. /
jamesadevine	0:e1a608bb55e8	6976	#define WDT_INTENSET_TIMEOUT_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	6977	#define WDT_INTENSET_TIMEOUT_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	6978	#define WDT_INTENSET_TIMEOUT_Set (1UL) /!< Enable interrupt on write. /
jamesadevine	0:e1a608bb55e8	6979
jamesadevine	0:e1a608bb55e8	6980	/* Register: WDT_INTENCLR */
jamesadevine	0:e1a608bb55e8	6981	/* Description: Interrupt enable clear register. */
jamesadevine	0:e1a608bb55e8	6982
jamesadevine	0:e1a608bb55e8	6983	/* Bit 0 : Disable interrupt on TIMEOUT event. */
jamesadevine	0:e1a608bb55e8	6984	#define WDT_INTENCLR_TIMEOUT_Pos (0UL) /!< Position of TIMEOUT field. /
jamesadevine	0:e1a608bb55e8	6985	#define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /!< Bit mask of TIMEOUT field. /
jamesadevine	0:e1a608bb55e8	6986	#define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /!< Interrupt disabled. /
jamesadevine	0:e1a608bb55e8	6987	#define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /!< Interrupt enabled. /
jamesadevine	0:e1a608bb55e8	6988	#define WDT_INTENCLR_TIMEOUT_Clear (1UL) /!< Disable interrupt on write. /
jamesadevine	0:e1a608bb55e8	6989
jamesadevine	0:e1a608bb55e8	6990	/* Register: WDT_RUNSTATUS */
jamesadevine	0:e1a608bb55e8	6991	/* Description: Watchdog running status. */
jamesadevine	0:e1a608bb55e8	6992
jamesadevine	0:e1a608bb55e8	6993	/* Bit 0 : Watchdog running status. */
jamesadevine	0:e1a608bb55e8	6994	#define WDT_RUNSTATUS_RUNSTATUS_Pos (0UL) /!< Position of RUNSTATUS field. /
jamesadevine	0:e1a608bb55e8	6995	#define WDT_RUNSTATUS_RUNSTATUS_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUS_Pos) /!< Bit mask of RUNSTATUS field. /
jamesadevine	0:e1a608bb55e8	6996	#define WDT_RUNSTATUS_RUNSTATUS_NotRunning (0UL) /!< Watchdog timer is not running. /
jamesadevine	0:e1a608bb55e8	6997	#define WDT_RUNSTATUS_RUNSTATUS_Running (1UL) /!< Watchdog timer is running. /
jamesadevine	0:e1a608bb55e8	6998
jamesadevine	0:e1a608bb55e8	6999	/* Register: WDT_REQSTATUS */
jamesadevine	0:e1a608bb55e8	7000	/* Description: Request status. */
jamesadevine	0:e1a608bb55e8	7001
jamesadevine	0:e1a608bb55e8	7002	/* Bit 7 : Request status for RR[7]. */
jamesadevine	0:e1a608bb55e8	7003	#define WDT_REQSTATUS_RR7_Pos (7UL) /!< Position of RR7 field. /
jamesadevine	0:e1a608bb55e8	7004	#define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /!< Bit mask of RR7 field. /
jamesadevine	0:e1a608bb55e8	7005	#define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /!< RR[7] register is not enabled or has already requested reload. /
jamesadevine	0:e1a608bb55e8	7006	#define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /!< RR[7] register is enabled and has not jet requested. /
jamesadevine	0:e1a608bb55e8	7007
jamesadevine	0:e1a608bb55e8	7008	/* Bit 6 : Request status for RR[6]. */
jamesadevine	0:e1a608bb55e8	7009	#define WDT_REQSTATUS_RR6_Pos (6UL) /!< Position of RR6 field. /
jamesadevine	0:e1a608bb55e8	7010	#define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /!< Bit mask of RR6 field. /
jamesadevine	0:e1a608bb55e8	7011	#define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /!< RR[6] register is not enabled or has already requested reload. /
jamesadevine	0:e1a608bb55e8	7012	#define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /!< RR[6] register is enabled and has not jet requested. /
jamesadevine	0:e1a608bb55e8	7013
jamesadevine	0:e1a608bb55e8	7014	/* Bit 5 : Request status for RR[5]. */
jamesadevine	0:e1a608bb55e8	7015	#define WDT_REQSTATUS_RR5_Pos (5UL) /!< Position of RR5 field. /
jamesadevine	0:e1a608bb55e8	7016	#define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /!< Bit mask of RR5 field. /
jamesadevine	0:e1a608bb55e8	7017	#define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /!< RR[5] register is not enabled or has already requested reload. /
jamesadevine	0:e1a608bb55e8	7018	#define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /!< RR[5] register is enabled and has not jet requested. /
jamesadevine	0:e1a608bb55e8	7019
jamesadevine	0:e1a608bb55e8	7020	/* Bit 4 : Request status for RR[4]. */
jamesadevine	0:e1a608bb55e8	7021	#define WDT_REQSTATUS_RR4_Pos (4UL) /!< Position of RR4 field. /
jamesadevine	0:e1a608bb55e8	7022	#define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /!< Bit mask of RR4 field. /
jamesadevine	0:e1a608bb55e8	7023	#define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /!< RR[4] register is not enabled or has already requested reload. /
jamesadevine	0:e1a608bb55e8	7024	#define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /!< RR[4] register is enabled and has not jet requested. /
jamesadevine	0:e1a608bb55e8	7025
jamesadevine	0:e1a608bb55e8	7026	/* Bit 3 : Request status for RR[3]. */
jamesadevine	0:e1a608bb55e8	7027	#define WDT_REQSTATUS_RR3_Pos (3UL) /!< Position of RR3 field. /
jamesadevine	0:e1a608bb55e8	7028	#define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /!< Bit mask of RR3 field. /
jamesadevine	0:e1a608bb55e8	7029	#define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /!< RR[3] register is not enabled or has already requested reload. /
jamesadevine	0:e1a608bb55e8	7030	#define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /!< RR[3] register is enabled and has not jet requested. /
jamesadevine	0:e1a608bb55e8	7031
jamesadevine	0:e1a608bb55e8	7032	/* Bit 2 : Request status for RR[2]. */
jamesadevine	0:e1a608bb55e8	7033	#define WDT_REQSTATUS_RR2_Pos (2UL) /!< Position of RR2 field. /
jamesadevine	0:e1a608bb55e8	7034	#define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /!< Bit mask of RR2 field. /
jamesadevine	0:e1a608bb55e8	7035	#define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /!< RR[2] register is not enabled or has already requested reload. /
jamesadevine	0:e1a608bb55e8	7036	#define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /!< RR[2] register is enabled and has not jet requested. /
jamesadevine	0:e1a608bb55e8	7037
jamesadevine	0:e1a608bb55e8	7038	/* Bit 1 : Request status for RR[1]. */
jamesadevine	0:e1a608bb55e8	7039	#define WDT_REQSTATUS_RR1_Pos (1UL) /!< Position of RR1 field. /
jamesadevine	0:e1a608bb55e8	7040	#define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /!< Bit mask of RR1 field. /
jamesadevine	0:e1a608bb55e8	7041	#define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /!< RR[1] register is not enabled or has already requested reload. /
jamesadevine	0:e1a608bb55e8	7042	#define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /!< RR[1] register is enabled and has not jet requested. /
jamesadevine	0:e1a608bb55e8	7043
jamesadevine	0:e1a608bb55e8	7044	/* Bit 0 : Request status for RR[0]. */
jamesadevine	0:e1a608bb55e8	7045	#define WDT_REQSTATUS_RR0_Pos (0UL) /!< Position of RR0 field. /
jamesadevine	0:e1a608bb55e8	7046	#define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /!< Bit mask of RR0 field. /
jamesadevine	0:e1a608bb55e8	7047	#define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /!< RR[0] register is not enabled or has already requested reload. /
jamesadevine	0:e1a608bb55e8	7048	#define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /!< RR[0] register is enabled and has not jet requested. /
jamesadevine	0:e1a608bb55e8	7049
jamesadevine	0:e1a608bb55e8	7050	/* Register: WDT_RREN */
jamesadevine	0:e1a608bb55e8	7051	/* Description: Reload request enable. */
jamesadevine	0:e1a608bb55e8	7052
jamesadevine	0:e1a608bb55e8	7053	/* Bit 7 : Enable or disable RR[7] register. */
jamesadevine	0:e1a608bb55e8	7054	#define WDT_RREN_RR7_Pos (7UL) /!< Position of RR7 field. /
jamesadevine	0:e1a608bb55e8	7055	#define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /!< Bit mask of RR7 field. /
jamesadevine	0:e1a608bb55e8	7056	#define WDT_RREN_RR7_Disabled (0UL) /!< RR[7] register is disabled. /
jamesadevine	0:e1a608bb55e8	7057	#define WDT_RREN_RR7_Enabled (1UL) /!< RR[7] register is enabled. /
jamesadevine	0:e1a608bb55e8	7058
jamesadevine	0:e1a608bb55e8	7059	/* Bit 6 : Enable or disable RR[6] register. */
jamesadevine	0:e1a608bb55e8	7060	#define WDT_RREN_RR6_Pos (6UL) /!< Position of RR6 field. /
jamesadevine	0:e1a608bb55e8	7061	#define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /!< Bit mask of RR6 field. /
jamesadevine	0:e1a608bb55e8	7062	#define WDT_RREN_RR6_Disabled (0UL) /!< RR[6] register is disabled. /
jamesadevine	0:e1a608bb55e8	7063	#define WDT_RREN_RR6_Enabled (1UL) /!< RR[6] register is enabled. /
jamesadevine	0:e1a608bb55e8	7064
jamesadevine	0:e1a608bb55e8	7065	/* Bit 5 : Enable or disable RR[5] register. */
jamesadevine	0:e1a608bb55e8	7066	#define WDT_RREN_RR5_Pos (5UL) /!< Position of RR5 field. /
jamesadevine	0:e1a608bb55e8	7067	#define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /!< Bit mask of RR5 field. /
jamesadevine	0:e1a608bb55e8	7068	#define WDT_RREN_RR5_Disabled (0UL) /!< RR[5] register is disabled. /
jamesadevine	0:e1a608bb55e8	7069	#define WDT_RREN_RR5_Enabled (1UL) /!< RR[5] register is enabled. /
jamesadevine	0:e1a608bb55e8	7070
jamesadevine	0:e1a608bb55e8	7071	/* Bit 4 : Enable or disable RR[4] register. */
jamesadevine	0:e1a608bb55e8	7072	#define WDT_RREN_RR4_Pos (4UL) /!< Position of RR4 field. /
jamesadevine	0:e1a608bb55e8	7073	#define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /!< Bit mask of RR4 field. /
jamesadevine	0:e1a608bb55e8	7074	#define WDT_RREN_RR4_Disabled (0UL) /!< RR[4] register is disabled. /
jamesadevine	0:e1a608bb55e8	7075	#define WDT_RREN_RR4_Enabled (1UL) /!< RR[4] register is enabled. /
jamesadevine	0:e1a608bb55e8	7076
jamesadevine	0:e1a608bb55e8	7077	/* Bit 3 : Enable or disable RR[3] register. */
jamesadevine	0:e1a608bb55e8	7078	#define WDT_RREN_RR3_Pos (3UL) /!< Position of RR3 field. /
jamesadevine	0:e1a608bb55e8	7079	#define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /!< Bit mask of RR3 field. /
jamesadevine	0:e1a608bb55e8	7080	#define WDT_RREN_RR3_Disabled (0UL) /!< RR[3] register is disabled. /
jamesadevine	0:e1a608bb55e8	7081	#define WDT_RREN_RR3_Enabled (1UL) /!< RR[3] register is enabled. /
jamesadevine	0:e1a608bb55e8	7082
jamesadevine	0:e1a608bb55e8	7083	/* Bit 2 : Enable or disable RR[2] register. */
jamesadevine	0:e1a608bb55e8	7084	#define WDT_RREN_RR2_Pos (2UL) /!< Position of RR2 field. /
jamesadevine	0:e1a608bb55e8	7085	#define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /!< Bit mask of RR2 field. /
jamesadevine	0:e1a608bb55e8	7086	#define WDT_RREN_RR2_Disabled (0UL) /!< RR[2] register is disabled. /
jamesadevine	0:e1a608bb55e8	7087	#define WDT_RREN_RR2_Enabled (1UL) /!< RR[2] register is enabled. /
jamesadevine	0:e1a608bb55e8	7088
jamesadevine	0:e1a608bb55e8	7089	/* Bit 1 : Enable or disable RR[1] register. */
jamesadevine	0:e1a608bb55e8	7090	#define WDT_RREN_RR1_Pos (1UL) /!< Position of RR1 field. /
jamesadevine	0:e1a608bb55e8	7091	#define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /!< Bit mask of RR1 field. /
jamesadevine	0:e1a608bb55e8	7092	#define WDT_RREN_RR1_Disabled (0UL) /!< RR[1] register is disabled. /
jamesadevine	0:e1a608bb55e8	7093	#define WDT_RREN_RR1_Enabled (1UL) /!< RR[1] register is enabled. /
jamesadevine	0:e1a608bb55e8	7094
jamesadevine	0:e1a608bb55e8	7095	/* Bit 0 : Enable or disable RR[0] register. */
jamesadevine	0:e1a608bb55e8	7096	#define WDT_RREN_RR0_Pos (0UL) /!< Position of RR0 field. /
jamesadevine	0:e1a608bb55e8	7097	#define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /!< Bit mask of RR0 field. /
jamesadevine	0:e1a608bb55e8	7098	#define WDT_RREN_RR0_Disabled (0UL) /!< RR[0] register is disabled. /
jamesadevine	0:e1a608bb55e8	7099	#define WDT_RREN_RR0_Enabled (1UL) /!< RR[0] register is enabled. /
jamesadevine	0:e1a608bb55e8	7100
jamesadevine	0:e1a608bb55e8	7101	/* Register: WDT_CONFIG */
jamesadevine	0:e1a608bb55e8	7102	/* Description: Configuration register. */
jamesadevine	0:e1a608bb55e8	7103
jamesadevine	0:e1a608bb55e8	7104	/* Bit 3 : Configure the watchdog to pause or not while the CPU is halted by the debugger. */
jamesadevine	0:e1a608bb55e8	7105	#define WDT_CONFIG_HALT_Pos (3UL) /!< Position of HALT field. /
jamesadevine	0:e1a608bb55e8	7106	#define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /!< Bit mask of HALT field. /
jamesadevine	0:e1a608bb55e8	7107	#define WDT_CONFIG_HALT_Pause (0UL) /!< Pause watchdog while the CPU is halted by the debugger. /
jamesadevine	0:e1a608bb55e8	7108	#define WDT_CONFIG_HALT_Run (1UL) /!< Do not pause watchdog while the CPU is halted by the debugger. /
jamesadevine	0:e1a608bb55e8	7109
jamesadevine	0:e1a608bb55e8	7110	/* Bit 0 : Configure the watchdog to pause or not while the CPU is sleeping. */
jamesadevine	0:e1a608bb55e8	7111	#define WDT_CONFIG_SLEEP_Pos (0UL) /!< Position of SLEEP field. /
jamesadevine	0:e1a608bb55e8	7112	#define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /!< Bit mask of SLEEP field. /
jamesadevine	0:e1a608bb55e8	7113	#define WDT_CONFIG_SLEEP_Pause (0UL) /!< Pause watchdog while the CPU is asleep. /
jamesadevine	0:e1a608bb55e8	7114	#define WDT_CONFIG_SLEEP_Run (1UL) /!< Do not pause watchdog while the CPU is asleep. /
jamesadevine	0:e1a608bb55e8	7115
jamesadevine	0:e1a608bb55e8	7116	/* Register: WDT_RR */
jamesadevine	0:e1a608bb55e8	7117	/* Description: Reload requests registers. */
jamesadevine	0:e1a608bb55e8	7118
jamesadevine	0:e1a608bb55e8	7119	/* Bits 31..0 : Reload register. */
jamesadevine	0:e1a608bb55e8	7120	#define WDT_RR_RR_Pos (0UL) /!< Position of RR field. /
jamesadevine	0:e1a608bb55e8	7121	#define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /!< Bit mask of RR field. /
jamesadevine	0:e1a608bb55e8	7122	#define WDT_RR_RR_Reload (0x6E524635UL) /!< Value to request a reload of the watchdog timer. /
jamesadevine	0:e1a608bb55e8	7123
jamesadevine	0:e1a608bb55e8	7124	/* Register: WDT_POWER */
jamesadevine	0:e1a608bb55e8	7125	/* Description: Peripheral power control. */
jamesadevine	0:e1a608bb55e8	7126
jamesadevine	0:e1a608bb55e8	7127	/* Bit 0 : Peripheral power control. */
jamesadevine	0:e1a608bb55e8	7128	#define WDT_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
jamesadevine	0:e1a608bb55e8	7129	#define WDT_POWER_POWER_Msk (0x1UL << WDT_POWER_POWER_Pos) /!< Bit mask of POWER field. /
jamesadevine	0:e1a608bb55e8	7130	#define WDT_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
jamesadevine	0:e1a608bb55e8	7131	#define WDT_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
jamesadevine	0:e1a608bb55e8	7132
jamesadevine	0:e1a608bb55e8	7133
jamesadevine	0:e1a608bb55e8	7134	/lint --flb "Leave library region" /
jamesadevine	0:e1a608bb55e8	7135	#endif

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Type:	Library
Created:	23 May 2017
Imports:	0
Forks:	0
Commits:	5
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TARGET_NRF51_MICROBIT/nrf51_bitfields.h@4:98796b85dcf3, 2017-05-23 (annotated)

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