R1 code for micro:bit based train controller code, requires second micro:bit running tx code to operate - see https://meanderingpi.wordpress.com/ for more information
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Diff: TARGET_NRF51_MICROBIT/TOOLCHAIN_ARM_STD/nRF51822.sct
- Revision:
- 2:e32c8485c88f
- Parent:
- 1:a7c51b5e0534
diff -r a7c51b5e0534 -r e32c8485c88f TARGET_NRF51_MICROBIT/TOOLCHAIN_ARM_STD/nRF51822.sct --- a/TARGET_NRF51_MICROBIT/TOOLCHAIN_ARM_STD/nRF51822.sct Thu Apr 07 17:50:29 2016 +0000 +++ b/TARGET_NRF51_MICROBIT/TOOLCHAIN_ARM_STD/nRF51822.sct Wed Jul 13 15:09:26 2016 +0100 @@ -1,26 +1,24 @@ -;WITHOUT SOFTDEVICE: -;LR_IROM1 0x00000000 0x00040000 { -; ER_IROM1 0x00000000 0x00040000 { -; *.o (RESET, +First) -; *(InRoot$$Sections) -; .ANY (+RO) -; } -; RW_IRAM1 0x20000000 0x00004000 { -; .ANY (+RW +ZI) -; } -;} -; -;WITH SOFTDEVICE: - -LR_IROM1 0x18000 0x0028000 { - ER_IROM1 0x18000 0x0028000 { - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - RW_IRAM1 0x20002000 0x00002000 { - .ANY (+RW +ZI) - } -} - +;WITHOUT SOFTDEVICE: +;LR_IROM1 0x00000000 0x00040000 { +; ER_IROM1 0x00000000 0x00040000 { +; *.o (RESET, +First) +; *(InRoot$$Sections) +; .ANY (+RO) +; } +; RW_IRAM1 0x20000000 0x00004000 { +; .ANY (+RW +ZI) +; } +;} +; +;WITH SOFTDEVICE: +LR_IROM1 0x18000 0x0028000 { + ER_IROM1 0x18000 0x0028000 { + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM1 0x20002000 0x00002000 { + .ANY (+RW +ZI) + } +}