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test fork
Fork of LG by
Parameters.h@20:e56d63c1ca05, 2016-02-03 (annotated)
- Committer:
- DarkPatrick
- Date:
- Wed Feb 03 09:33:19 2016 +0400
- Revision:
- 20:e56d63c1ca05
- Parent:
- 0:8ad47e2b6f00
test
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
igor_v | 0:8ad47e2b6f00 | 1 | #ifndef UHOST |
igor_v | 0:8ad47e2b6f00 | 2 | #define UHOST |
igor_v | 0:8ad47e2b6f00 | 3 | /*e.**************************************************** |
igor_v | 0:8ad47e2b6f00 | 4 | * Constants for the uHost card * |
igor_v | 0:8ad47e2b6f00 | 5 | ********************************************************/ |
igor_v | 0:8ad47e2b6f00 | 6 | /*r.**************************************************** |
igor_v | 0:8ad47e2b6f00 | 7 | * ��������� ��� ����� uHost * |
igor_v | 0:8ad47e2b6f00 | 8 | ********************************************************/ |
igor_v | 0:8ad47e2b6f00 | 9 | /*e. file for the C code */ |
igor_v | 0:8ad47e2b6f00 | 10 | /*r. ���� ��� ���� �� � */ |
igor_v | 0:8ad47e2b6f00 | 11 | |
igor_v | 0:8ad47e2b6f00 | 12 | #define FIRMWARE_VER 0x00 //e. firmware version number //r. ����� ������ �������������� |
igor_v | 0:8ad47e2b6f00 | 13 | |
igor_v | 0:8ad47e2b6f00 | 14 | //e. ====================== registers of the system controller of the DSP card ================ //r. ====================== �������� ���������� ����������� ����� DSP ================ |
igor_v | 0:8ad47e2b6f00 | 15 | #define Sys_RgE 0x07fb //e. the line1_err register of line errors //r. ������� ������ ����� line1_err |
igor_v | 0:8ad47e2b6f00 | 16 | #define Sys_RgR 0x07fc //e. the register of a mode of the system (only write) //r. ������� ������ ������� (������ ������) |
igor_v | 0:8ad47e2b6f00 | 17 | #define Sys_RgS 0x07fc //e. the register of a status of the system (only read) //r. ������� ������� ������� (������ ������) |
igor_v | 0:8ad47e2b6f00 | 18 | #define Trm_data 0x07fd //e. the data stack of the transmitter //r. ���� ������ ����������� |
igor_v | 0:8ad47e2b6f00 | 19 | #define Rcv_data 0x07fd //e. the data stack of the receiver //r. ���� ������ ��������� |
igor_v | 0:8ad47e2b6f00 | 20 | #define Rcv_cntr 0x07fe //e. the counter of the received bytes //r. ������� �������� ���� ��������� |
igor_v | 0:8ad47e2b6f00 | 21 | |
igor_v | 0:8ad47e2b6f00 | 22 | //e. ====================== bits of the Sys_RgS status register ========================= //r. ====================== ���� �������� ��������� Sys_RgS ========================= |
igor_v | 0:8ad47e2b6f00 | 23 | #define RCV_RDY_MASK 0x0040 //e. a mask of the readiness bit of the receiver //r. ����� ���� ���������� ��������� |
igor_v | 0:8ad47e2b6f00 | 24 | #define RCV_FERR_MASK 0x0020 //e. a mask of the "format error" bit //r. ����� ���� "������ �������" |
igor_v | 0:8ad47e2b6f00 | 25 | #define RCV_TOUT_MASK 0x0010 //e. a mask of the "time-out" bit //r. ����� ���� "����-���" |
igor_v | 0:8ad47e2b6f00 | 26 | #define RCV_RFUL_MASK 0x0008 //e. a mask of the "stack is full" bit//r. ����� ���� "���� �����" |
igor_v | 0:8ad47e2b6f00 | 27 | #define RCV_FERR 0x0020 //e. a mask of the "format error" bit //r. ����� ���� "������ �������" |
igor_v | 0:8ad47e2b6f00 | 28 | #define RCV_TOUT 0x0010 //e. a mask of the "time-out" bit //r. ����� ���� "����-���" |
igor_v | 0:8ad47e2b6f00 | 29 | #define RCV_RFUL 0x0008 //e. a mask of the "stack is full" bit//r. ����� ���� "���� �����" |
igor_v | 0:8ad47e2b6f00 | 30 | |
igor_v | 0:8ad47e2b6f00 | 31 | #define INT_ERR_TC 0x00000008 |
igor_v | 0:8ad47e2b6f00 | 32 | |
igor_v | 0:8ad47e2b6f00 | 33 | #define FromFLASH 0x00003 |
igor_v | 0:8ad47e2b6f00 | 34 | #define ByDefault 0x00001 |
igor_v | 0:8ad47e2b6f00 | 35 | |
igor_v | 0:8ad47e2b6f00 | 36 | |
igor_v | 0:8ad47e2b6f00 | 37 | |
igor_v | 0:8ad47e2b6f00 | 38 | #define SetV1 LPC_GPIO1->FIOSET=(1<<25); |
igor_v | 0:8ad47e2b6f00 | 39 | #define ClrV1 LPC_GPIO1->FIOCLR = (1<<25); |
igor_v | 0:8ad47e2b6f00 | 40 | |
igor_v | 0:8ad47e2b6f00 | 41 | #define SetV2 LPC_GPIO1->FIOSET = (1<<28); |
igor_v | 0:8ad47e2b6f00 | 42 | #define ClrV2 LPC_GPIO1->FIOCLR = (1<<28); |
igor_v | 0:8ad47e2b6f00 | 43 | #define LoopOn LPC_GPIO1->FIOSET = (1<<30); |
igor_v | 0:8ad47e2b6f00 | 44 | #define LoopOff LPC_GPIO1->FIOCLR = (1<<30); |
igor_v | 0:8ad47e2b6f00 | 45 | #define StartV1 0 |
igor_v | 0:8ad47e2b6f00 | 46 | #define StartV2 15 |
igor_v | 0:8ad47e2b6f00 | 47 | #define TIME_INTERVAL (7812) |
igor_v | 0:8ad47e2b6f00 | 48 | |
igor_v | 0:8ad47e2b6f00 | 49 | |
igor_v | 0:8ad47e2b6f00 | 50 | |
igor_v | 0:8ad47e2b6f00 | 51 | extern uint32_t blt_in_test; |
igor_v | 0:8ad47e2b6f00 | 52 | |
igor_v | 0:8ad47e2b6f00 | 53 | void LoadFlashParam(unsigned ); |
igor_v | 0:8ad47e2b6f00 | 54 | void FlashDMA_Init(void); |
igor_v | 0:8ad47e2b6f00 | 55 | void init_DefaultParam(void); |
igor_v | 0:8ad47e2b6f00 | 56 | #endif |
igor_v | 0:8ad47e2b6f00 | 57 | |
igor_v | 0:8ad47e2b6f00 | 58 |