Egor Syomin
/
LG
test fork
Fork of LG by
CyclesSync.h@20:e56d63c1ca05, 2016-02-03 (annotated)
- Committer:
- DarkPatrick
- Date:
- Wed Feb 03 09:33:19 2016 +0400
- Revision:
- 20:e56d63c1ca05
- Parent:
- 0:8ad47e2b6f00
test
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
igor_v | 0:8ad47e2b6f00 | 1 | /**--------------File Info--------------------------------------------------------------------------------- |
igor_v | 0:8ad47e2b6f00 | 2 | ** File name: CycleSync.h |
igor_v | 0:8ad47e2b6f00 | 3 | ** Last modified Date: 2011-09-06 |
igor_v | 0:8ad47e2b6f00 | 4 | ** Last Version: V1.00 |
igor_v | 0:8ad47e2b6f00 | 5 | ** Descriptions: |
igor_v | 0:8ad47e2b6f00 | 6 | ** |
igor_v | 0:8ad47e2b6f00 | 7 | **-------------------------------------------------------------------------------------------------------- |
igor_v | 0:8ad47e2b6f00 | 8 | ** Created by: Electrooptica Inc. |
igor_v | 0:8ad47e2b6f00 | 9 | ** Created date: 2011-09-06 |
igor_v | 0:8ad47e2b6f00 | 10 | ** Version: V1.00 |
igor_v | 0:8ad47e2b6f00 | 11 | ** Descriptions: There is the routines for device synchronization |
igor_v | 0:8ad47e2b6f00 | 12 | ** |
igor_v | 0:8ad47e2b6f00 | 13 | **-------------------------------------------------------------------------------------------------------- |
igor_v | 0:8ad47e2b6f00 | 14 | *********************************************************************************************************/ |
igor_v | 0:8ad47e2b6f00 | 15 | #include "LPC17xx.h" |
igor_v | 0:8ad47e2b6f00 | 16 | #include "CntrlGLD.h" |
igor_v | 0:8ad47e2b6f00 | 17 | |
igor_v | 0:8ad47e2b6f00 | 18 | //#define PERFOMANCE |
igor_v | 0:8ad47e2b6f00 | 19 | |
igor_v | 0:8ad47e2b6f00 | 20 | #define DEVICE_SAMPLE_RATE_HZ 10000 //e. sampling frequency 10 kHz //r. ������� ������������� 10 ��� |
igor_v | 0:8ad47e2b6f00 | 21 | #define DEVICE_SAMPLE_RATE_uks 100000000 //e. sampling frequency 10 kHz //r. ������� ������������� 10 ��� |
igor_v | 0:8ad47e2b6f00 | 22 | #define DELAY_UART_ENBL 4000 //e. delay = DELAY_UART_ENBL*8/CLCK |
igor_v | 0:8ad47e2b6f00 | 23 | #define DELAY_UART_DISBL 2500 //e. delay = DELAY_UART_ENBL*8/CLCK |
igor_v | 0:8ad47e2b6f00 | 24 | #define RATE_REPER_OR_REFMEANDR 0x0000 //e. difference of general counters (not dither counters), latched by Reper or by Sign Meander //r. �������� ������� ��������� (�� �������), ����������� �� Reper`� ��� �� RefMeandr`� |
igor_v | 0:8ad47e2b6f00 | 25 | #define RATE_VIBRO_1 0x0001 //e. difference of dither counters after the filter of moving average //r. �������� �������������� ����� ������� ������.�������� |
igor_v | 0:8ad47e2b6f00 | 26 | |
igor_v | 0:8ad47e2b6f00 | 27 | #define HALF_PERIOD 0x00000004 |
igor_v | 0:8ad47e2b6f00 | 28 | #define WHOLE_PERIOD 0x00000008 |
igor_v | 0:8ad47e2b6f00 | 29 | #define RESET_PERIOD 0x0000000C |
igor_v | 0:8ad47e2b6f00 | 30 | //-----------------------------PWM Registers---------------------------------------- |
igor_v | 0:8ad47e2b6f00 | 31 | |
igor_v | 0:8ad47e2b6f00 | 32 | #define TCR_CNT_EN 0x00000001 |
igor_v | 0:8ad47e2b6f00 | 33 | #define TCR_RESET 0x00000002 |
igor_v | 0:8ad47e2b6f00 | 34 | #define TCR_PWM_EN 0x00000008 |
igor_v | 0:8ad47e2b6f00 | 35 | |
igor_v | 0:8ad47e2b6f00 | 36 | #define PWMMR0I (1 << 0) |
igor_v | 0:8ad47e2b6f00 | 37 | #define PWMMR0R (1 << 1) |
igor_v | 0:8ad47e2b6f00 | 38 | #define PWMMR0S (1 << 2) |
igor_v | 0:8ad47e2b6f00 | 39 | #define PWMENA1 (1 << 9) |
igor_v | 0:8ad47e2b6f00 | 40 | #define LER0_EN (1 << 0) |
igor_v | 0:8ad47e2b6f00 | 41 | |
igor_v | 0:8ad47e2b6f00 | 42 | //-----------------------Drive cycle registers------------------------------------ |
igor_v | 0:8ad47e2b6f00 | 43 | #define MR0_RESET 0x00000002 |
igor_v | 0:8ad47e2b6f00 | 44 | #define MR1_RESET 0x00000010 |
igor_v | 0:8ad47e2b6f00 | 45 | #define MR1_STOP 0x00000020 |
igor_v | 0:8ad47e2b6f00 | 46 | #define MR0_STOP 0x00000004 |
igor_v | 0:8ad47e2b6f00 | 47 | #define MR0_NO_STOP 0x00000000 |
igor_v | 0:8ad47e2b6f00 | 48 | #define MR0_INT_EN 0x00000001 |
igor_v | 0:8ad47e2b6f00 | 49 | #define SYNC_CLCK4 0xffff3fff |
igor_v | 0:8ad47e2b6f00 | 50 | #define SYNC_CLCK 0xfffffff |
igor_v | 0:8ad47e2b6f00 | 51 | |
igor_v | 0:8ad47e2b6f00 | 52 | //------------------------WDT registers-------------------------------------------- |
igor_v | 0:8ad47e2b6f00 | 53 | #define WDEN (0x1<<0) |
igor_v | 0:8ad47e2b6f00 | 54 | #define WDRESET (0x1<<1) |
igor_v | 0:8ad47e2b6f00 | 55 | #define WDTOF (0x1<<2) |
igor_v | 0:8ad47e2b6f00 | 56 | #define WDINT (0x1<<3) |
igor_v | 0:8ad47e2b6f00 | 57 | #define WDT_FEED_VALUE 0x003FFFFF |
igor_v | 0:8ad47e2b6f00 | 58 | |
igor_v | 0:8ad47e2b6f00 | 59 | extern uint32_t WDTInit( void ); |
igor_v | 0:8ad47e2b6f00 | 60 | extern void WDTFeed( void ); |
igor_v | 0:8ad47e2b6f00 | 61 | extern uint32_t Sys_Clock; |
igor_v | 0:8ad47e2b6f00 | 62 | extern int32_t time_1_Sec; |
igor_v | 0:8ad47e2b6f00 | 63 | extern uint32_t trm_cycl; |
igor_v | 0:8ad47e2b6f00 | 64 | extern int32_t PrevPeriod; |
igor_v | 0:8ad47e2b6f00 | 65 | extern uint32_t Ext_Latch_ResetEnable; |
igor_v | 0:8ad47e2b6f00 | 66 | extern volatile uint32_t Latch_Rdy; |
igor_v | 0:8ad47e2b6f00 | 67 | extern volatile uint32_t data_Rdy; |
igor_v | 0:8ad47e2b6f00 | 68 | extern int32_t LatchPhase; |
igor_v | 0:8ad47e2b6f00 | 69 | extern uint32_t PeriodElapsed; |
igor_v | 0:8ad47e2b6f00 | 70 | extern uint32_t count; |
igor_v | 0:8ad47e2b6f00 | 71 | extern uint32_t main_cycle_latch; |
igor_v | 0:8ad47e2b6f00 | 72 | extern uint32_t Out_main_cycle_latch; //e. counter of main cycles between external latch pulse appearence |
igor_v | 0:8ad47e2b6f00 | 73 | extern uint32_t T_latch, Out_T_latch, temp_T_latch; |
igor_v | 0:8ad47e2b6f00 | 74 | |
igor_v | 0:8ad47e2b6f00 | 75 | extern void CounterIquiryCycle_Init(uint32_t); |
igor_v | 0:8ad47e2b6f00 | 76 | extern void ExtLatch_Init(void); |
igor_v | 0:8ad47e2b6f00 | 77 | extern void IntLatch_Init(void); |
igor_v | 0:8ad47e2b6f00 | 78 | extern void Latch_Event(void); |
igor_v | 0:8ad47e2b6f00 | 79 | extern void SetIntLatch(uint32_t); |
igor_v | 0:8ad47e2b6f00 | 80 | extern void SwitchRefMeandInt(uint32_t); |
igor_v | 0:8ad47e2b6f00 | 81 | extern int SwitchMode(void); |
igor_v | 0:8ad47e2b6f00 | 82 | |
igor_v | 0:8ad47e2b6f00 | 83 | #if defined PERFOMANCE |
igor_v | 0:8ad47e2b6f00 | 84 | void IntLatch(void); |
igor_v | 0:8ad47e2b6f00 | 85 | #endif |
igor_v | 0:8ad47e2b6f00 | 86 | |
igor_v | 0:8ad47e2b6f00 | 87 | void ServiceTime(void); |
igor_v | 0:8ad47e2b6f00 | 88 | |
igor_v | 0:8ad47e2b6f00 | 89 | /***************************************************************************** |
igor_v | 0:8ad47e2b6f00 | 90 | ** End Of File |
igor_v | 0:8ad47e2b6f00 | 91 | ******************************************************************************/ |
igor_v | 0:8ad47e2b6f00 | 92 |