Egor Syomin
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LG
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core_cmFunc.h@0:8ad47e2b6f00, 2016-01-30 (annotated)
- Committer:
- igor_v
- Date:
- Sat Jan 30 13:00:39 2016 +0000
- Revision:
- 0:8ad47e2b6f00
2016_01_30;
Who changed what in which revision?
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igor_v | 0:8ad47e2b6f00 | 1 | /**************************************************************************//** |
igor_v | 0:8ad47e2b6f00 | 2 | * @file core_cmFunc.h |
igor_v | 0:8ad47e2b6f00 | 3 | * @brief CMSIS Cortex-M Core Function Access Header File |
igor_v | 0:8ad47e2b6f00 | 4 | * @version V2.01 |
igor_v | 0:8ad47e2b6f00 | 5 | * @date 06. December 2010 |
igor_v | 0:8ad47e2b6f00 | 6 | * |
igor_v | 0:8ad47e2b6f00 | 7 | * @note |
igor_v | 0:8ad47e2b6f00 | 8 | * Copyright (C) 2009-2010 ARM Limited. All rights reserved. |
igor_v | 0:8ad47e2b6f00 | 9 | * |
igor_v | 0:8ad47e2b6f00 | 10 | * @par |
igor_v | 0:8ad47e2b6f00 | 11 | * ARM Limited (ARM) is supplying this software for use with Cortex-M |
igor_v | 0:8ad47e2b6f00 | 12 | * processor based microcontrollers. This file can be freely distributed |
igor_v | 0:8ad47e2b6f00 | 13 | * within development tools that are supporting such ARM based processors. |
igor_v | 0:8ad47e2b6f00 | 14 | * |
igor_v | 0:8ad47e2b6f00 | 15 | * @par |
igor_v | 0:8ad47e2b6f00 | 16 | * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED |
igor_v | 0:8ad47e2b6f00 | 17 | * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF |
igor_v | 0:8ad47e2b6f00 | 18 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. |
igor_v | 0:8ad47e2b6f00 | 19 | * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR |
igor_v | 0:8ad47e2b6f00 | 20 | * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
igor_v | 0:8ad47e2b6f00 | 21 | * |
igor_v | 0:8ad47e2b6f00 | 22 | ******************************************************************************/ |
igor_v | 0:8ad47e2b6f00 | 23 | |
igor_v | 0:8ad47e2b6f00 | 24 | #ifndef __CORE_CMFUNC_H__ |
igor_v | 0:8ad47e2b6f00 | 25 | #define __CORE_CMFUNC_H__ |
igor_v | 0:8ad47e2b6f00 | 26 | |
igor_v | 0:8ad47e2b6f00 | 27 | /* ########################### Core Function Access ########################### */ |
igor_v | 0:8ad47e2b6f00 | 28 | /** \ingroup CMSIS_Core_FunctionInterface |
igor_v | 0:8ad47e2b6f00 | 29 | \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions |
igor_v | 0:8ad47e2b6f00 | 30 | @{ |
igor_v | 0:8ad47e2b6f00 | 31 | */ |
igor_v | 0:8ad47e2b6f00 | 32 | |
igor_v | 0:8ad47e2b6f00 | 33 | #if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/ |
igor_v | 0:8ad47e2b6f00 | 34 | /* ARM armcc specific functions */ |
igor_v | 0:8ad47e2b6f00 | 35 | |
igor_v | 0:8ad47e2b6f00 | 36 | /* intrinsic void __enable_irq(); */ |
igor_v | 0:8ad47e2b6f00 | 37 | /* intrinsic void __disable_irq(); */ |
igor_v | 0:8ad47e2b6f00 | 38 | |
igor_v | 0:8ad47e2b6f00 | 39 | /** \brief Get Control Register |
igor_v | 0:8ad47e2b6f00 | 40 | |
igor_v | 0:8ad47e2b6f00 | 41 | This function returns the content of the Control Register. |
igor_v | 0:8ad47e2b6f00 | 42 | |
igor_v | 0:8ad47e2b6f00 | 43 | \return Control Register value |
igor_v | 0:8ad47e2b6f00 | 44 | */ |
igor_v | 0:8ad47e2b6f00 | 45 | #if (__ARMCC_VERSION < 400000) |
igor_v | 0:8ad47e2b6f00 | 46 | extern uint32_t __get_CONTROL(void); |
igor_v | 0:8ad47e2b6f00 | 47 | #else /* (__ARMCC_VERSION >= 400000) */ |
igor_v | 0:8ad47e2b6f00 | 48 | static __INLINE uint32_t __get_CONTROL(void) |
igor_v | 0:8ad47e2b6f00 | 49 | { |
igor_v | 0:8ad47e2b6f00 | 50 | register uint32_t __regControl __ASM("control"); |
igor_v | 0:8ad47e2b6f00 | 51 | return(__regControl); |
igor_v | 0:8ad47e2b6f00 | 52 | } |
igor_v | 0:8ad47e2b6f00 | 53 | #endif /* __ARMCC_VERSION */ |
igor_v | 0:8ad47e2b6f00 | 54 | |
igor_v | 0:8ad47e2b6f00 | 55 | |
igor_v | 0:8ad47e2b6f00 | 56 | /** \brief Set Control Register |
igor_v | 0:8ad47e2b6f00 | 57 | |
igor_v | 0:8ad47e2b6f00 | 58 | This function writes the given value to the Control Register. |
igor_v | 0:8ad47e2b6f00 | 59 | |
igor_v | 0:8ad47e2b6f00 | 60 | \param [in] control Control Register value to set |
igor_v | 0:8ad47e2b6f00 | 61 | */ |
igor_v | 0:8ad47e2b6f00 | 62 | #if (__ARMCC_VERSION < 400000) |
igor_v | 0:8ad47e2b6f00 | 63 | extern void __set_CONTROL(uint32_t control); |
igor_v | 0:8ad47e2b6f00 | 64 | #else /* (__ARMCC_VERSION >= 400000) */ |
igor_v | 0:8ad47e2b6f00 | 65 | static __INLINE void __set_CONTROL(uint32_t control) |
igor_v | 0:8ad47e2b6f00 | 66 | { |
igor_v | 0:8ad47e2b6f00 | 67 | register uint32_t __regControl __ASM("control"); |
igor_v | 0:8ad47e2b6f00 | 68 | __regControl = control; |
igor_v | 0:8ad47e2b6f00 | 69 | } |
igor_v | 0:8ad47e2b6f00 | 70 | #endif /* __ARMCC_VERSION */ |
igor_v | 0:8ad47e2b6f00 | 71 | |
igor_v | 0:8ad47e2b6f00 | 72 | |
igor_v | 0:8ad47e2b6f00 | 73 | /** \brief Get ISPR Register |
igor_v | 0:8ad47e2b6f00 | 74 | |
igor_v | 0:8ad47e2b6f00 | 75 | This function returns the content of the ISPR Register. |
igor_v | 0:8ad47e2b6f00 | 76 | |
igor_v | 0:8ad47e2b6f00 | 77 | \return ISPR Register value |
igor_v | 0:8ad47e2b6f00 | 78 | */ |
igor_v | 0:8ad47e2b6f00 | 79 | #if (__ARMCC_VERSION < 400000) |
igor_v | 0:8ad47e2b6f00 | 80 | extern uint32_t __get_IPSR(void); |
igor_v | 0:8ad47e2b6f00 | 81 | #else /* (__ARMCC_VERSION >= 400000) */ |
igor_v | 0:8ad47e2b6f00 | 82 | static __INLINE uint32_t __get_IPSR(void) |
igor_v | 0:8ad47e2b6f00 | 83 | { |
igor_v | 0:8ad47e2b6f00 | 84 | register uint32_t __regIPSR __ASM("ipsr"); |
igor_v | 0:8ad47e2b6f00 | 85 | return(__regIPSR); |
igor_v | 0:8ad47e2b6f00 | 86 | } |
igor_v | 0:8ad47e2b6f00 | 87 | #endif /* __ARMCC_VERSION */ |
igor_v | 0:8ad47e2b6f00 | 88 | |
igor_v | 0:8ad47e2b6f00 | 89 | |
igor_v | 0:8ad47e2b6f00 | 90 | /** \brief Get APSR Register |
igor_v | 0:8ad47e2b6f00 | 91 | |
igor_v | 0:8ad47e2b6f00 | 92 | This function returns the content of the APSR Register. |
igor_v | 0:8ad47e2b6f00 | 93 | |
igor_v | 0:8ad47e2b6f00 | 94 | \return APSR Register value |
igor_v | 0:8ad47e2b6f00 | 95 | */ |
igor_v | 0:8ad47e2b6f00 | 96 | #if (__ARMCC_VERSION < 400000) |
igor_v | 0:8ad47e2b6f00 | 97 | extern uint32_t __get_APSR(void); |
igor_v | 0:8ad47e2b6f00 | 98 | #else /* (__ARMCC_VERSION >= 400000) */ |
igor_v | 0:8ad47e2b6f00 | 99 | static __INLINE uint32_t __get_APSR(void) |
igor_v | 0:8ad47e2b6f00 | 100 | { |
igor_v | 0:8ad47e2b6f00 | 101 | register uint32_t __regAPSR __ASM("apsr"); |
igor_v | 0:8ad47e2b6f00 | 102 | return(__regAPSR); |
igor_v | 0:8ad47e2b6f00 | 103 | } |
igor_v | 0:8ad47e2b6f00 | 104 | #endif /* __ARMCC_VERSION */ |
igor_v | 0:8ad47e2b6f00 | 105 | |
igor_v | 0:8ad47e2b6f00 | 106 | |
igor_v | 0:8ad47e2b6f00 | 107 | /** \brief Get xPSR Register |
igor_v | 0:8ad47e2b6f00 | 108 | |
igor_v | 0:8ad47e2b6f00 | 109 | This function returns the content of the xPSR Register. |
igor_v | 0:8ad47e2b6f00 | 110 | |
igor_v | 0:8ad47e2b6f00 | 111 | \return xPSR Register value |
igor_v | 0:8ad47e2b6f00 | 112 | */ |
igor_v | 0:8ad47e2b6f00 | 113 | #if (__ARMCC_VERSION < 400000) |
igor_v | 0:8ad47e2b6f00 | 114 | extern uint32_t __get_xPSR(void); |
igor_v | 0:8ad47e2b6f00 | 115 | #else /* (__ARMCC_VERSION >= 400000) */ |
igor_v | 0:8ad47e2b6f00 | 116 | static __INLINE uint32_t __get_xPSR(void) |
igor_v | 0:8ad47e2b6f00 | 117 | { |
igor_v | 0:8ad47e2b6f00 | 118 | register uint32_t __regXPSR __ASM("xpsr"); |
igor_v | 0:8ad47e2b6f00 | 119 | return(__regXPSR); |
igor_v | 0:8ad47e2b6f00 | 120 | } |
igor_v | 0:8ad47e2b6f00 | 121 | #endif /* __ARMCC_VERSION */ |
igor_v | 0:8ad47e2b6f00 | 122 | |
igor_v | 0:8ad47e2b6f00 | 123 | |
igor_v | 0:8ad47e2b6f00 | 124 | /** \brief Get Process Stack Pointer |
igor_v | 0:8ad47e2b6f00 | 125 | |
igor_v | 0:8ad47e2b6f00 | 126 | This function returns the current value of the Process Stack Pointer (PSP). |
igor_v | 0:8ad47e2b6f00 | 127 | |
igor_v | 0:8ad47e2b6f00 | 128 | \return PSP Register value |
igor_v | 0:8ad47e2b6f00 | 129 | */ |
igor_v | 0:8ad47e2b6f00 | 130 | #if (__ARMCC_VERSION < 400000) |
igor_v | 0:8ad47e2b6f00 | 131 | extern uint32_t __get_PSP(void); |
igor_v | 0:8ad47e2b6f00 | 132 | #else /* (__ARMCC_VERSION >= 400000) */ |
igor_v | 0:8ad47e2b6f00 | 133 | static __INLINE uint32_t __get_PSP(void) |
igor_v | 0:8ad47e2b6f00 | 134 | { |
igor_v | 0:8ad47e2b6f00 | 135 | register uint32_t __regProcessStackPointer __ASM("psp"); |
igor_v | 0:8ad47e2b6f00 | 136 | return(__regProcessStackPointer); |
igor_v | 0:8ad47e2b6f00 | 137 | } |
igor_v | 0:8ad47e2b6f00 | 138 | #endif /* __ARMCC_VERSION */ |
igor_v | 0:8ad47e2b6f00 | 139 | |
igor_v | 0:8ad47e2b6f00 | 140 | |
igor_v | 0:8ad47e2b6f00 | 141 | /** \brief Set Process Stack Pointer |
igor_v | 0:8ad47e2b6f00 | 142 | |
igor_v | 0:8ad47e2b6f00 | 143 | This function assigns the given value to the Process Stack Pointer (PSP). |
igor_v | 0:8ad47e2b6f00 | 144 | |
igor_v | 0:8ad47e2b6f00 | 145 | \param [in] topOfProcStack Process Stack Pointer value to set |
igor_v | 0:8ad47e2b6f00 | 146 | */ |
igor_v | 0:8ad47e2b6f00 | 147 | #if (__ARMCC_VERSION < 400000) |
igor_v | 0:8ad47e2b6f00 | 148 | extern void __set_PSP(uint32_t topOfProcStack); |
igor_v | 0:8ad47e2b6f00 | 149 | #else /* (__ARMCC_VERSION >= 400000) */ |
igor_v | 0:8ad47e2b6f00 | 150 | static __INLINE void __set_PSP(uint32_t topOfProcStack) |
igor_v | 0:8ad47e2b6f00 | 151 | { |
igor_v | 0:8ad47e2b6f00 | 152 | register uint32_t __regProcessStackPointer __ASM("psp"); |
igor_v | 0:8ad47e2b6f00 | 153 | __regProcessStackPointer = topOfProcStack; |
igor_v | 0:8ad47e2b6f00 | 154 | } |
igor_v | 0:8ad47e2b6f00 | 155 | #endif /* __ARMCC_VERSION */ |
igor_v | 0:8ad47e2b6f00 | 156 | |
igor_v | 0:8ad47e2b6f00 | 157 | |
igor_v | 0:8ad47e2b6f00 | 158 | /** \brief Get Main Stack Pointer |
igor_v | 0:8ad47e2b6f00 | 159 | |
igor_v | 0:8ad47e2b6f00 | 160 | This function returns the current value of the Main Stack Pointer (MSP). |
igor_v | 0:8ad47e2b6f00 | 161 | |
igor_v | 0:8ad47e2b6f00 | 162 | \return MSP Register value |
igor_v | 0:8ad47e2b6f00 | 163 | */ |
igor_v | 0:8ad47e2b6f00 | 164 | #if (__ARMCC_VERSION < 400000) |
igor_v | 0:8ad47e2b6f00 | 165 | extern uint32_t __get_MSP(void); |
igor_v | 0:8ad47e2b6f00 | 166 | #else /* (__ARMCC_VERSION >= 400000) */ |
igor_v | 0:8ad47e2b6f00 | 167 | static __INLINE uint32_t __get_MSP(void) |
igor_v | 0:8ad47e2b6f00 | 168 | { |
igor_v | 0:8ad47e2b6f00 | 169 | register uint32_t __regMainStackPointer __ASM("msp"); |
igor_v | 0:8ad47e2b6f00 | 170 | return(__regMainStackPointer); |
igor_v | 0:8ad47e2b6f00 | 171 | } |
igor_v | 0:8ad47e2b6f00 | 172 | #endif /* __ARMCC_VERSION */ |
igor_v | 0:8ad47e2b6f00 | 173 | |
igor_v | 0:8ad47e2b6f00 | 174 | |
igor_v | 0:8ad47e2b6f00 | 175 | /** \brief Set Main Stack Pointer |
igor_v | 0:8ad47e2b6f00 | 176 | |
igor_v | 0:8ad47e2b6f00 | 177 | This function assigns the given value to the Main Stack Pointer (MSP). |
igor_v | 0:8ad47e2b6f00 | 178 | |
igor_v | 0:8ad47e2b6f00 | 179 | \param [in] topOfMainStack Main Stack Pointer value to set |
igor_v | 0:8ad47e2b6f00 | 180 | */ |
igor_v | 0:8ad47e2b6f00 | 181 | #if (__ARMCC_VERSION < 400000) |
igor_v | 0:8ad47e2b6f00 | 182 | extern void __set_MSP(uint32_t topOfMainStack); |
igor_v | 0:8ad47e2b6f00 | 183 | #else /* (__ARMCC_VERSION >= 400000) */ |
igor_v | 0:8ad47e2b6f00 | 184 | static __INLINE void __set_MSP(uint32_t topOfMainStack) |
igor_v | 0:8ad47e2b6f00 | 185 | { |
igor_v | 0:8ad47e2b6f00 | 186 | register uint32_t __regMainStackPointer __ASM("msp"); |
igor_v | 0:8ad47e2b6f00 | 187 | __regMainStackPointer = topOfMainStack; |
igor_v | 0:8ad47e2b6f00 | 188 | } |
igor_v | 0:8ad47e2b6f00 | 189 | #endif /* __ARMCC_VERSION */ |
igor_v | 0:8ad47e2b6f00 | 190 | |
igor_v | 0:8ad47e2b6f00 | 191 | |
igor_v | 0:8ad47e2b6f00 | 192 | /** \brief Get Priority Mask |
igor_v | 0:8ad47e2b6f00 | 193 | |
igor_v | 0:8ad47e2b6f00 | 194 | This function returns the current state of the priority mask bit from the Priority Mask Register. |
igor_v | 0:8ad47e2b6f00 | 195 | |
igor_v | 0:8ad47e2b6f00 | 196 | \return Priority Mask value |
igor_v | 0:8ad47e2b6f00 | 197 | */ |
igor_v | 0:8ad47e2b6f00 | 198 | #if (__ARMCC_VERSION < 400000) |
igor_v | 0:8ad47e2b6f00 | 199 | extern uint32_t __get_PRIMASK(void); |
igor_v | 0:8ad47e2b6f00 | 200 | #else /* (__ARMCC_VERSION >= 400000) */ |
igor_v | 0:8ad47e2b6f00 | 201 | static __INLINE uint32_t __get_PRIMASK(void) |
igor_v | 0:8ad47e2b6f00 | 202 | { |
igor_v | 0:8ad47e2b6f00 | 203 | register uint32_t __regPriMask __ASM("primask"); |
igor_v | 0:8ad47e2b6f00 | 204 | return(__regPriMask); |
igor_v | 0:8ad47e2b6f00 | 205 | } |
igor_v | 0:8ad47e2b6f00 | 206 | #endif /* __ARMCC_VERSION */ |
igor_v | 0:8ad47e2b6f00 | 207 | |
igor_v | 0:8ad47e2b6f00 | 208 | |
igor_v | 0:8ad47e2b6f00 | 209 | /** \brief Set Priority Mask |
igor_v | 0:8ad47e2b6f00 | 210 | |
igor_v | 0:8ad47e2b6f00 | 211 | This function assigns the given value to the Priority Mask Register. |
igor_v | 0:8ad47e2b6f00 | 212 | |
igor_v | 0:8ad47e2b6f00 | 213 | \param [in] priMask Priority Mask |
igor_v | 0:8ad47e2b6f00 | 214 | */ |
igor_v | 0:8ad47e2b6f00 | 215 | #if (__ARMCC_VERSION < 400000) |
igor_v | 0:8ad47e2b6f00 | 216 | extern void __set_PRIMASK(uint32_t priMask); |
igor_v | 0:8ad47e2b6f00 | 217 | #else /* (__ARMCC_VERSION >= 400000) */ |
igor_v | 0:8ad47e2b6f00 | 218 | static __INLINE void __set_PRIMASK(uint32_t priMask) |
igor_v | 0:8ad47e2b6f00 | 219 | { |
igor_v | 0:8ad47e2b6f00 | 220 | register uint32_t __regPriMask __ASM("primask"); |
igor_v | 0:8ad47e2b6f00 | 221 | __regPriMask = (priMask); |
igor_v | 0:8ad47e2b6f00 | 222 | } |
igor_v | 0:8ad47e2b6f00 | 223 | #endif /* __ARMCC_VERSION */ |
igor_v | 0:8ad47e2b6f00 | 224 | |
igor_v | 0:8ad47e2b6f00 | 225 | |
igor_v | 0:8ad47e2b6f00 | 226 | #if (__CORTEX_M >= 0x03) |
igor_v | 0:8ad47e2b6f00 | 227 | |
igor_v | 0:8ad47e2b6f00 | 228 | /** \brief Enable FIQ |
igor_v | 0:8ad47e2b6f00 | 229 | |
igor_v | 0:8ad47e2b6f00 | 230 | This function enables FIQ interrupts by clearing the F-bit in the CPSR. |
igor_v | 0:8ad47e2b6f00 | 231 | Can only be executed in Privileged modes. |
igor_v | 0:8ad47e2b6f00 | 232 | */ |
igor_v | 0:8ad47e2b6f00 | 233 | #define __enable_fault_irq __enable_fiq |
igor_v | 0:8ad47e2b6f00 | 234 | |
igor_v | 0:8ad47e2b6f00 | 235 | |
igor_v | 0:8ad47e2b6f00 | 236 | /** \brief Disable FIQ |
igor_v | 0:8ad47e2b6f00 | 237 | |
igor_v | 0:8ad47e2b6f00 | 238 | This function disables FIQ interrupts by setting the F-bit in the CPSR. |
igor_v | 0:8ad47e2b6f00 | 239 | Can only be executed in Privileged modes. |
igor_v | 0:8ad47e2b6f00 | 240 | */ |
igor_v | 0:8ad47e2b6f00 | 241 | #define __disable_fault_irq __disable_fiq |
igor_v | 0:8ad47e2b6f00 | 242 | |
igor_v | 0:8ad47e2b6f00 | 243 | |
igor_v | 0:8ad47e2b6f00 | 244 | /** \brief Get Base Priority |
igor_v | 0:8ad47e2b6f00 | 245 | |
igor_v | 0:8ad47e2b6f00 | 246 | This function returns the current value of the Base Priority register. |
igor_v | 0:8ad47e2b6f00 | 247 | |
igor_v | 0:8ad47e2b6f00 | 248 | \return Base Priority register value |
igor_v | 0:8ad47e2b6f00 | 249 | */ |
igor_v | 0:8ad47e2b6f00 | 250 | #if (__ARMCC_VERSION < 400000) |
igor_v | 0:8ad47e2b6f00 | 251 | extern uint32_t __get_BASEPRI(void); |
igor_v | 0:8ad47e2b6f00 | 252 | #else /* (__ARMCC_VERSION >= 400000) */ |
igor_v | 0:8ad47e2b6f00 | 253 | static __INLINE uint32_t __get_BASEPRI(void) |
igor_v | 0:8ad47e2b6f00 | 254 | { |
igor_v | 0:8ad47e2b6f00 | 255 | register uint32_t __regBasePri __ASM("basepri"); |
igor_v | 0:8ad47e2b6f00 | 256 | return(__regBasePri); |
igor_v | 0:8ad47e2b6f00 | 257 | } |
igor_v | 0:8ad47e2b6f00 | 258 | #endif /* __ARMCC_VERSION */ |
igor_v | 0:8ad47e2b6f00 | 259 | |
igor_v | 0:8ad47e2b6f00 | 260 | |
igor_v | 0:8ad47e2b6f00 | 261 | /** \brief Set Base Priority |
igor_v | 0:8ad47e2b6f00 | 262 | |
igor_v | 0:8ad47e2b6f00 | 263 | This function assigns the given value to the Base Priority register. |
igor_v | 0:8ad47e2b6f00 | 264 | |
igor_v | 0:8ad47e2b6f00 | 265 | \param [in] basePri Base Priority value to set |
igor_v | 0:8ad47e2b6f00 | 266 | */ |
igor_v | 0:8ad47e2b6f00 | 267 | #if (__ARMCC_VERSION < 400000) |
igor_v | 0:8ad47e2b6f00 | 268 | extern void __set_BASEPRI(uint32_t basePri); |
igor_v | 0:8ad47e2b6f00 | 269 | #else /* (__ARMCC_VERSION >= 400000) */ |
igor_v | 0:8ad47e2b6f00 | 270 | static __INLINE void __set_BASEPRI(uint32_t basePri) |
igor_v | 0:8ad47e2b6f00 | 271 | { |
igor_v | 0:8ad47e2b6f00 | 272 | register uint32_t __regBasePri __ASM("basepri"); |
igor_v | 0:8ad47e2b6f00 | 273 | __regBasePri = (basePri & 0xff); |
igor_v | 0:8ad47e2b6f00 | 274 | } |
igor_v | 0:8ad47e2b6f00 | 275 | #endif /* __ARMCC_VERSION */ |
igor_v | 0:8ad47e2b6f00 | 276 | |
igor_v | 0:8ad47e2b6f00 | 277 | |
igor_v | 0:8ad47e2b6f00 | 278 | /** \brief Get Fault Mask |
igor_v | 0:8ad47e2b6f00 | 279 | |
igor_v | 0:8ad47e2b6f00 | 280 | This function returns the current value of the Fault Mask register. |
igor_v | 0:8ad47e2b6f00 | 281 | |
igor_v | 0:8ad47e2b6f00 | 282 | \return Fault Mask register value |
igor_v | 0:8ad47e2b6f00 | 283 | */ |
igor_v | 0:8ad47e2b6f00 | 284 | #if (__ARMCC_VERSION < 400000) |
igor_v | 0:8ad47e2b6f00 | 285 | extern uint32_t __get_FAULTMASK(void); |
igor_v | 0:8ad47e2b6f00 | 286 | #else /* (__ARMCC_VERSION >= 400000) */ |
igor_v | 0:8ad47e2b6f00 | 287 | static __INLINE uint32_t __get_FAULTMASK(void) |
igor_v | 0:8ad47e2b6f00 | 288 | { |
igor_v | 0:8ad47e2b6f00 | 289 | register uint32_t __regFaultMask __ASM("faultmask"); |
igor_v | 0:8ad47e2b6f00 | 290 | return(__regFaultMask); |
igor_v | 0:8ad47e2b6f00 | 291 | } |
igor_v | 0:8ad47e2b6f00 | 292 | #endif /* __ARMCC_VERSION */ |
igor_v | 0:8ad47e2b6f00 | 293 | |
igor_v | 0:8ad47e2b6f00 | 294 | |
igor_v | 0:8ad47e2b6f00 | 295 | /** \brief Set Fault Mask |
igor_v | 0:8ad47e2b6f00 | 296 | |
igor_v | 0:8ad47e2b6f00 | 297 | This function assigns the given value to the Fault Mask register. |
igor_v | 0:8ad47e2b6f00 | 298 | |
igor_v | 0:8ad47e2b6f00 | 299 | \param [in] faultMask Fault Mask value to set |
igor_v | 0:8ad47e2b6f00 | 300 | */ |
igor_v | 0:8ad47e2b6f00 | 301 | #if (__ARMCC_VERSION < 400000) |
igor_v | 0:8ad47e2b6f00 | 302 | extern void __set_FAULTMASK(uint32_t faultMask); |
igor_v | 0:8ad47e2b6f00 | 303 | #else /* (__ARMCC_VERSION >= 400000) */ |
igor_v | 0:8ad47e2b6f00 | 304 | static __INLINE void __set_FAULTMASK(uint32_t faultMask) |
igor_v | 0:8ad47e2b6f00 | 305 | { |
igor_v | 0:8ad47e2b6f00 | 306 | register uint32_t __regFaultMask __ASM("faultmask"); |
igor_v | 0:8ad47e2b6f00 | 307 | __regFaultMask = (faultMask & 1); |
igor_v | 0:8ad47e2b6f00 | 308 | } |
igor_v | 0:8ad47e2b6f00 | 309 | #endif /* __ARMCC_VERSION */ |
igor_v | 0:8ad47e2b6f00 | 310 | |
igor_v | 0:8ad47e2b6f00 | 311 | #endif /* (__CORTEX_M >= 0x03) */ |
igor_v | 0:8ad47e2b6f00 | 312 | |
igor_v | 0:8ad47e2b6f00 | 313 | |
igor_v | 0:8ad47e2b6f00 | 314 | #if (__CORTEX_M == 0x04) |
igor_v | 0:8ad47e2b6f00 | 315 | |
igor_v | 0:8ad47e2b6f00 | 316 | /** \brief Get FPSCR |
igor_v | 0:8ad47e2b6f00 | 317 | |
igor_v | 0:8ad47e2b6f00 | 318 | This function returns the current value of the Floating Point Status/Control register. |
igor_v | 0:8ad47e2b6f00 | 319 | |
igor_v | 0:8ad47e2b6f00 | 320 | \return Floating Point Status/Control register value |
igor_v | 0:8ad47e2b6f00 | 321 | */ |
igor_v | 0:8ad47e2b6f00 | 322 | static __INLINE uint32_t __get_FPSCR(void) |
igor_v | 0:8ad47e2b6f00 | 323 | { |
igor_v | 0:8ad47e2b6f00 | 324 | #if (__FPU_PRESENT == 1) |
igor_v | 0:8ad47e2b6f00 | 325 | register uint32_t __regfpscr __ASM("fpscr"); |
igor_v | 0:8ad47e2b6f00 | 326 | return(__regfpscr); |
igor_v | 0:8ad47e2b6f00 | 327 | #else |
igor_v | 0:8ad47e2b6f00 | 328 | return(0); |
igor_v | 0:8ad47e2b6f00 | 329 | #endif |
igor_v | 0:8ad47e2b6f00 | 330 | } |
igor_v | 0:8ad47e2b6f00 | 331 | |
igor_v | 0:8ad47e2b6f00 | 332 | |
igor_v | 0:8ad47e2b6f00 | 333 | /** \brief Set FPSCR |
igor_v | 0:8ad47e2b6f00 | 334 | |
igor_v | 0:8ad47e2b6f00 | 335 | This function assigns the given value to the Floating Point Status/Control register. |
igor_v | 0:8ad47e2b6f00 | 336 | |
igor_v | 0:8ad47e2b6f00 | 337 | \param [in] fpscr Floating Point Status/Control value to set |
igor_v | 0:8ad47e2b6f00 | 338 | */ |
igor_v | 0:8ad47e2b6f00 | 339 | static __INLINE void __set_FPSCR(uint32_t fpscr) |
igor_v | 0:8ad47e2b6f00 | 340 | { |
igor_v | 0:8ad47e2b6f00 | 341 | #if (__FPU_PRESENT == 1) |
igor_v | 0:8ad47e2b6f00 | 342 | register uint32_t __regfpscr __ASM("fpscr"); |
igor_v | 0:8ad47e2b6f00 | 343 | __regfpscr = (fpscr); |
igor_v | 0:8ad47e2b6f00 | 344 | #endif |
igor_v | 0:8ad47e2b6f00 | 345 | } |
igor_v | 0:8ad47e2b6f00 | 346 | |
igor_v | 0:8ad47e2b6f00 | 347 | #endif /* (__CORTEX_M == 0x04) */ |
igor_v | 0:8ad47e2b6f00 | 348 | |
igor_v | 0:8ad47e2b6f00 | 349 | |
igor_v | 0:8ad47e2b6f00 | 350 | #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/ |
igor_v | 0:8ad47e2b6f00 | 351 | /* IAR iccarm specific functions */ |
igor_v | 0:8ad47e2b6f00 | 352 | |
igor_v | 0:8ad47e2b6f00 | 353 | #if defined (__ICCARM__) |
igor_v | 0:8ad47e2b6f00 | 354 | #include <intrinsics.h> /* IAR Intrinsics */ |
igor_v | 0:8ad47e2b6f00 | 355 | #endif |
igor_v | 0:8ad47e2b6f00 | 356 | |
igor_v | 0:8ad47e2b6f00 | 357 | #pragma diag_suppress=Pe940 |
igor_v | 0:8ad47e2b6f00 | 358 | |
igor_v | 0:8ad47e2b6f00 | 359 | /** \brief Enable IRQ Interrupts |
igor_v | 0:8ad47e2b6f00 | 360 | |
igor_v | 0:8ad47e2b6f00 | 361 | This function enables IRQ interrupts by clearing the I-bit in the CPSR. |
igor_v | 0:8ad47e2b6f00 | 362 | Can only be executed in Privileged modes. |
igor_v | 0:8ad47e2b6f00 | 363 | */ |
igor_v | 0:8ad47e2b6f00 | 364 | #define __enable_irq __enable_interrupt |
igor_v | 0:8ad47e2b6f00 | 365 | |
igor_v | 0:8ad47e2b6f00 | 366 | |
igor_v | 0:8ad47e2b6f00 | 367 | /** \brief Disable IRQ Interrupts |
igor_v | 0:8ad47e2b6f00 | 368 | |
igor_v | 0:8ad47e2b6f00 | 369 | This function disables IRQ interrupts by setting the I-bit in the CPSR. |
igor_v | 0:8ad47e2b6f00 | 370 | Can only be executed in Privileged modes. |
igor_v | 0:8ad47e2b6f00 | 371 | */ |
igor_v | 0:8ad47e2b6f00 | 372 | #define __disable_irq __disable_interrupt |
igor_v | 0:8ad47e2b6f00 | 373 | |
igor_v | 0:8ad47e2b6f00 | 374 | |
igor_v | 0:8ad47e2b6f00 | 375 | /* intrinsic unsigned long __get_CONTROL( void ); (see intrinsic.h) */ |
igor_v | 0:8ad47e2b6f00 | 376 | /* intrinsic void __set_CONTROL( unsigned long ); (see intrinsic.h) */ |
igor_v | 0:8ad47e2b6f00 | 377 | |
igor_v | 0:8ad47e2b6f00 | 378 | |
igor_v | 0:8ad47e2b6f00 | 379 | /** \brief Get ISPR Register |
igor_v | 0:8ad47e2b6f00 | 380 | |
igor_v | 0:8ad47e2b6f00 | 381 | This function returns the content of the ISPR Register. |
igor_v | 0:8ad47e2b6f00 | 382 | |
igor_v | 0:8ad47e2b6f00 | 383 | \return ISPR Register value |
igor_v | 0:8ad47e2b6f00 | 384 | */ |
igor_v | 0:8ad47e2b6f00 | 385 | static uint32_t __get_IPSR(void) |
igor_v | 0:8ad47e2b6f00 | 386 | { |
igor_v | 0:8ad47e2b6f00 | 387 | __ASM("mrs r0, ipsr"); |
igor_v | 0:8ad47e2b6f00 | 388 | } |
igor_v | 0:8ad47e2b6f00 | 389 | |
igor_v | 0:8ad47e2b6f00 | 390 | |
igor_v | 0:8ad47e2b6f00 | 391 | /** \brief Get APSR Register |
igor_v | 0:8ad47e2b6f00 | 392 | |
igor_v | 0:8ad47e2b6f00 | 393 | This function returns the content of the APSR Register. |
igor_v | 0:8ad47e2b6f00 | 394 | |
igor_v | 0:8ad47e2b6f00 | 395 | \return APSR Register value |
igor_v | 0:8ad47e2b6f00 | 396 | */ |
igor_v | 0:8ad47e2b6f00 | 397 | static uint32_t __get_APSR(void) |
igor_v | 0:8ad47e2b6f00 | 398 | { |
igor_v | 0:8ad47e2b6f00 | 399 | __ASM("mrs r0, apsr"); |
igor_v | 0:8ad47e2b6f00 | 400 | } |
igor_v | 0:8ad47e2b6f00 | 401 | |
igor_v | 0:8ad47e2b6f00 | 402 | |
igor_v | 0:8ad47e2b6f00 | 403 | /** \brief Get xPSR Register |
igor_v | 0:8ad47e2b6f00 | 404 | |
igor_v | 0:8ad47e2b6f00 | 405 | This function returns the content of the xPSR Register. |
igor_v | 0:8ad47e2b6f00 | 406 | |
igor_v | 0:8ad47e2b6f00 | 407 | \return xPSR Register value |
igor_v | 0:8ad47e2b6f00 | 408 | */ |
igor_v | 0:8ad47e2b6f00 | 409 | static uint32_t __get_xPSR(void) |
igor_v | 0:8ad47e2b6f00 | 410 | { |
igor_v | 0:8ad47e2b6f00 | 411 | __ASM("mrs r0, psr"); // assembler does not know "xpsr" |
igor_v | 0:8ad47e2b6f00 | 412 | } |
igor_v | 0:8ad47e2b6f00 | 413 | |
igor_v | 0:8ad47e2b6f00 | 414 | |
igor_v | 0:8ad47e2b6f00 | 415 | /** \brief Get Process Stack Pointer |
igor_v | 0:8ad47e2b6f00 | 416 | |
igor_v | 0:8ad47e2b6f00 | 417 | This function returns the current value of the Process Stack Pointer (PSP). |
igor_v | 0:8ad47e2b6f00 | 418 | |
igor_v | 0:8ad47e2b6f00 | 419 | \return PSP Register value |
igor_v | 0:8ad47e2b6f00 | 420 | */ |
igor_v | 0:8ad47e2b6f00 | 421 | static uint32_t __get_PSP(void) |
igor_v | 0:8ad47e2b6f00 | 422 | { |
igor_v | 0:8ad47e2b6f00 | 423 | __ASM("mrs r0, psp"); |
igor_v | 0:8ad47e2b6f00 | 424 | } |
igor_v | 0:8ad47e2b6f00 | 425 | |
igor_v | 0:8ad47e2b6f00 | 426 | |
igor_v | 0:8ad47e2b6f00 | 427 | /** \brief Set Process Stack Pointer |
igor_v | 0:8ad47e2b6f00 | 428 | |
igor_v | 0:8ad47e2b6f00 | 429 | This function assigns the given value to the Process Stack Pointer (PSP). |
igor_v | 0:8ad47e2b6f00 | 430 | |
igor_v | 0:8ad47e2b6f00 | 431 | \param [in] topOfProcStack Process Stack Pointer value to set |
igor_v | 0:8ad47e2b6f00 | 432 | */ |
igor_v | 0:8ad47e2b6f00 | 433 | static void __set_PSP(uint32_t topOfProcStack) |
igor_v | 0:8ad47e2b6f00 | 434 | { |
igor_v | 0:8ad47e2b6f00 | 435 | __ASM("msr psp, r0"); |
igor_v | 0:8ad47e2b6f00 | 436 | } |
igor_v | 0:8ad47e2b6f00 | 437 | |
igor_v | 0:8ad47e2b6f00 | 438 | |
igor_v | 0:8ad47e2b6f00 | 439 | /** \brief Get Main Stack Pointer |
igor_v | 0:8ad47e2b6f00 | 440 | |
igor_v | 0:8ad47e2b6f00 | 441 | This function returns the current value of the Main Stack Pointer (MSP). |
igor_v | 0:8ad47e2b6f00 | 442 | |
igor_v | 0:8ad47e2b6f00 | 443 | \return MSP Register value |
igor_v | 0:8ad47e2b6f00 | 444 | */ |
igor_v | 0:8ad47e2b6f00 | 445 | static uint32_t __get_MSP(void) |
igor_v | 0:8ad47e2b6f00 | 446 | { |
igor_v | 0:8ad47e2b6f00 | 447 | __ASM("mrs r0, msp"); |
igor_v | 0:8ad47e2b6f00 | 448 | } |
igor_v | 0:8ad47e2b6f00 | 449 | |
igor_v | 0:8ad47e2b6f00 | 450 | |
igor_v | 0:8ad47e2b6f00 | 451 | /** \brief Set Main Stack Pointer |
igor_v | 0:8ad47e2b6f00 | 452 | |
igor_v | 0:8ad47e2b6f00 | 453 | This function assigns the given value to the Main Stack Pointer (MSP). |
igor_v | 0:8ad47e2b6f00 | 454 | |
igor_v | 0:8ad47e2b6f00 | 455 | \param [in] topOfMainStack Main Stack Pointer value to set |
igor_v | 0:8ad47e2b6f00 | 456 | */ |
igor_v | 0:8ad47e2b6f00 | 457 | static void __set_MSP(uint32_t topOfMainStack) |
igor_v | 0:8ad47e2b6f00 | 458 | { |
igor_v | 0:8ad47e2b6f00 | 459 | __ASM("msr msp, r0"); |
igor_v | 0:8ad47e2b6f00 | 460 | } |
igor_v | 0:8ad47e2b6f00 | 461 | |
igor_v | 0:8ad47e2b6f00 | 462 | |
igor_v | 0:8ad47e2b6f00 | 463 | /* intrinsic unsigned long __get_PRIMASK( void ); (see intrinsic.h) */ |
igor_v | 0:8ad47e2b6f00 | 464 | /* intrinsic void __set_PRIMASK( unsigned long ); (see intrinsic.h) */ |
igor_v | 0:8ad47e2b6f00 | 465 | |
igor_v | 0:8ad47e2b6f00 | 466 | |
igor_v | 0:8ad47e2b6f00 | 467 | #if (__CORTEX_M >= 0x03) |
igor_v | 0:8ad47e2b6f00 | 468 | |
igor_v | 0:8ad47e2b6f00 | 469 | /** \brief Enable FIQ |
igor_v | 0:8ad47e2b6f00 | 470 | |
igor_v | 0:8ad47e2b6f00 | 471 | This function enables FIQ interrupts by clearing the F-bit in the CPSR. |
igor_v | 0:8ad47e2b6f00 | 472 | Can only be executed in Privileged modes. |
igor_v | 0:8ad47e2b6f00 | 473 | */ |
igor_v | 0:8ad47e2b6f00 | 474 | static __INLINE void __enable_fault_irq(void) |
igor_v | 0:8ad47e2b6f00 | 475 | { |
igor_v | 0:8ad47e2b6f00 | 476 | __ASM ("cpsie f"); |
igor_v | 0:8ad47e2b6f00 | 477 | } |
igor_v | 0:8ad47e2b6f00 | 478 | |
igor_v | 0:8ad47e2b6f00 | 479 | |
igor_v | 0:8ad47e2b6f00 | 480 | /** \brief Disable FIQ |
igor_v | 0:8ad47e2b6f00 | 481 | |
igor_v | 0:8ad47e2b6f00 | 482 | This function disables FIQ interrupts by setting the F-bit in the CPSR. |
igor_v | 0:8ad47e2b6f00 | 483 | Can only be executed in Privileged modes. |
igor_v | 0:8ad47e2b6f00 | 484 | */ |
igor_v | 0:8ad47e2b6f00 | 485 | static __INLINE void __disable_fault_irq(void) |
igor_v | 0:8ad47e2b6f00 | 486 | { |
igor_v | 0:8ad47e2b6f00 | 487 | __ASM ("cpsid f"); |
igor_v | 0:8ad47e2b6f00 | 488 | } |
igor_v | 0:8ad47e2b6f00 | 489 | |
igor_v | 0:8ad47e2b6f00 | 490 | |
igor_v | 0:8ad47e2b6f00 | 491 | /* intrinsic unsigned long __get_BASEPRI( void ); (see intrinsic.h) */ |
igor_v | 0:8ad47e2b6f00 | 492 | /* intrinsic void __set_BASEPRI( unsigned long ); (see intrinsic.h) */ |
igor_v | 0:8ad47e2b6f00 | 493 | /* intrinsic unsigned long __get_FAULTMASK( void ); (see intrinsic.h) */ |
igor_v | 0:8ad47e2b6f00 | 494 | /* intrinsic void __set_FAULTMASK(unsigned long); (see intrinsic.h) */ |
igor_v | 0:8ad47e2b6f00 | 495 | |
igor_v | 0:8ad47e2b6f00 | 496 | #endif /* (__CORTEX_M >= 0x03) */ |
igor_v | 0:8ad47e2b6f00 | 497 | |
igor_v | 0:8ad47e2b6f00 | 498 | |
igor_v | 0:8ad47e2b6f00 | 499 | #if (__CORTEX_M == 0x04) |
igor_v | 0:8ad47e2b6f00 | 500 | |
igor_v | 0:8ad47e2b6f00 | 501 | /** \brief Get FPSCR |
igor_v | 0:8ad47e2b6f00 | 502 | |
igor_v | 0:8ad47e2b6f00 | 503 | This function returns the current value of the Floating Point Status/Control register. |
igor_v | 0:8ad47e2b6f00 | 504 | |
igor_v | 0:8ad47e2b6f00 | 505 | \return Floating Point Status/Control register value |
igor_v | 0:8ad47e2b6f00 | 506 | */ |
igor_v | 0:8ad47e2b6f00 | 507 | static uint32_t __get_FPSCR(void) |
igor_v | 0:8ad47e2b6f00 | 508 | { |
igor_v | 0:8ad47e2b6f00 | 509 | #if (__FPU_PRESENT == 1) |
igor_v | 0:8ad47e2b6f00 | 510 | __ASM("vmrs r0, fpscr"); |
igor_v | 0:8ad47e2b6f00 | 511 | #else |
igor_v | 0:8ad47e2b6f00 | 512 | return(0); |
igor_v | 0:8ad47e2b6f00 | 513 | #endif |
igor_v | 0:8ad47e2b6f00 | 514 | } |
igor_v | 0:8ad47e2b6f00 | 515 | |
igor_v | 0:8ad47e2b6f00 | 516 | |
igor_v | 0:8ad47e2b6f00 | 517 | /** \brief Set FPSCR |
igor_v | 0:8ad47e2b6f00 | 518 | |
igor_v | 0:8ad47e2b6f00 | 519 | This function assigns the given value to the Floating Point Status/Control register. |
igor_v | 0:8ad47e2b6f00 | 520 | |
igor_v | 0:8ad47e2b6f00 | 521 | \param [in] fpscr Floating Point Status/Control value to set |
igor_v | 0:8ad47e2b6f00 | 522 | */ |
igor_v | 0:8ad47e2b6f00 | 523 | static void __set_FPSCR(uint32_t fpscr) |
igor_v | 0:8ad47e2b6f00 | 524 | { |
igor_v | 0:8ad47e2b6f00 | 525 | #if (__FPU_PRESENT == 1) |
igor_v | 0:8ad47e2b6f00 | 526 | __ASM("vmsr fpscr, r0"); |
igor_v | 0:8ad47e2b6f00 | 527 | #endif |
igor_v | 0:8ad47e2b6f00 | 528 | } |
igor_v | 0:8ad47e2b6f00 | 529 | |
igor_v | 0:8ad47e2b6f00 | 530 | #endif /* (__CORTEX_M == 0x04) */ |
igor_v | 0:8ad47e2b6f00 | 531 | |
igor_v | 0:8ad47e2b6f00 | 532 | #pragma diag_default=Pe940 |
igor_v | 0:8ad47e2b6f00 | 533 | |
igor_v | 0:8ad47e2b6f00 | 534 | |
igor_v | 0:8ad47e2b6f00 | 535 | #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ |
igor_v | 0:8ad47e2b6f00 | 536 | /* GNU gcc specific functions */ |
igor_v | 0:8ad47e2b6f00 | 537 | |
igor_v | 0:8ad47e2b6f00 | 538 | /** \brief Enable IRQ Interrupts |
igor_v | 0:8ad47e2b6f00 | 539 | |
igor_v | 0:8ad47e2b6f00 | 540 | This function enables IRQ interrupts by clearing the I-bit in the CPSR. |
igor_v | 0:8ad47e2b6f00 | 541 | Can only be executed in Privileged modes. |
igor_v | 0:8ad47e2b6f00 | 542 | */ |
igor_v | 0:8ad47e2b6f00 | 543 | __attribute__( ( always_inline ) ) static __INLINE void __enable_irq(void) |
igor_v | 0:8ad47e2b6f00 | 544 | { |
igor_v | 0:8ad47e2b6f00 | 545 | __ASM volatile ("cpsie i"); |
igor_v | 0:8ad47e2b6f00 | 546 | } |
igor_v | 0:8ad47e2b6f00 | 547 | |
igor_v | 0:8ad47e2b6f00 | 548 | |
igor_v | 0:8ad47e2b6f00 | 549 | /** \brief Disable IRQ Interrupts |
igor_v | 0:8ad47e2b6f00 | 550 | |
igor_v | 0:8ad47e2b6f00 | 551 | This function disables IRQ interrupts by setting the I-bit in the CPSR. |
igor_v | 0:8ad47e2b6f00 | 552 | Can only be executed in Privileged modes. |
igor_v | 0:8ad47e2b6f00 | 553 | */ |
igor_v | 0:8ad47e2b6f00 | 554 | __attribute__( ( always_inline ) ) static __INLINE void __disable_irq(void) |
igor_v | 0:8ad47e2b6f00 | 555 | { |
igor_v | 0:8ad47e2b6f00 | 556 | __ASM volatile ("cpsid i"); |
igor_v | 0:8ad47e2b6f00 | 557 | } |
igor_v | 0:8ad47e2b6f00 | 558 | |
igor_v | 0:8ad47e2b6f00 | 559 | |
igor_v | 0:8ad47e2b6f00 | 560 | /** \brief Get Control Register |
igor_v | 0:8ad47e2b6f00 | 561 | |
igor_v | 0:8ad47e2b6f00 | 562 | This function returns the content of the Control Register. |
igor_v | 0:8ad47e2b6f00 | 563 | |
igor_v | 0:8ad47e2b6f00 | 564 | \return Control Register value |
igor_v | 0:8ad47e2b6f00 | 565 | */ |
igor_v | 0:8ad47e2b6f00 | 566 | __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_CONTROL(void) |
igor_v | 0:8ad47e2b6f00 | 567 | { |
igor_v | 0:8ad47e2b6f00 | 568 | uint32_t result; |
igor_v | 0:8ad47e2b6f00 | 569 | |
igor_v | 0:8ad47e2b6f00 | 570 | __ASM volatile ("MRS %0, control" : "=r" (result) ); |
igor_v | 0:8ad47e2b6f00 | 571 | return(result); |
igor_v | 0:8ad47e2b6f00 | 572 | } |
igor_v | 0:8ad47e2b6f00 | 573 | |
igor_v | 0:8ad47e2b6f00 | 574 | |
igor_v | 0:8ad47e2b6f00 | 575 | /** \brief Set Control Register |
igor_v | 0:8ad47e2b6f00 | 576 | |
igor_v | 0:8ad47e2b6f00 | 577 | This function writes the given value to the Control Register. |
igor_v | 0:8ad47e2b6f00 | 578 | |
igor_v | 0:8ad47e2b6f00 | 579 | \param [in] control Control Register value to set |
igor_v | 0:8ad47e2b6f00 | 580 | */ |
igor_v | 0:8ad47e2b6f00 | 581 | __attribute__( ( always_inline ) ) static __INLINE void __set_CONTROL(uint32_t control) |
igor_v | 0:8ad47e2b6f00 | 582 | { |
igor_v | 0:8ad47e2b6f00 | 583 | __ASM volatile ("MSR control, %0" : : "r" (control) ); |
igor_v | 0:8ad47e2b6f00 | 584 | } |
igor_v | 0:8ad47e2b6f00 | 585 | |
igor_v | 0:8ad47e2b6f00 | 586 | |
igor_v | 0:8ad47e2b6f00 | 587 | /** \brief Get ISPR Register |
igor_v | 0:8ad47e2b6f00 | 588 | |
igor_v | 0:8ad47e2b6f00 | 589 | This function returns the content of the ISPR Register. |
igor_v | 0:8ad47e2b6f00 | 590 | |
igor_v | 0:8ad47e2b6f00 | 591 | \return ISPR Register value |
igor_v | 0:8ad47e2b6f00 | 592 | */ |
igor_v | 0:8ad47e2b6f00 | 593 | __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void) |
igor_v | 0:8ad47e2b6f00 | 594 | { |
igor_v | 0:8ad47e2b6f00 | 595 | uint32_t result; |
igor_v | 0:8ad47e2b6f00 | 596 | |
igor_v | 0:8ad47e2b6f00 | 597 | __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); |
igor_v | 0:8ad47e2b6f00 | 598 | return(result); |
igor_v | 0:8ad47e2b6f00 | 599 | } |
igor_v | 0:8ad47e2b6f00 | 600 | |
igor_v | 0:8ad47e2b6f00 | 601 | |
igor_v | 0:8ad47e2b6f00 | 602 | /** \brief Get APSR Register |
igor_v | 0:8ad47e2b6f00 | 603 | |
igor_v | 0:8ad47e2b6f00 | 604 | This function returns the content of the APSR Register. |
igor_v | 0:8ad47e2b6f00 | 605 | |
igor_v | 0:8ad47e2b6f00 | 606 | \return APSR Register value |
igor_v | 0:8ad47e2b6f00 | 607 | */ |
igor_v | 0:8ad47e2b6f00 | 608 | __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_APSR(void) |
igor_v | 0:8ad47e2b6f00 | 609 | { |
igor_v | 0:8ad47e2b6f00 | 610 | uint32_t result; |
igor_v | 0:8ad47e2b6f00 | 611 | |
igor_v | 0:8ad47e2b6f00 | 612 | __ASM volatile ("MRS %0, apsr" : "=r" (result) ); |
igor_v | 0:8ad47e2b6f00 | 613 | return(result); |
igor_v | 0:8ad47e2b6f00 | 614 | } |
igor_v | 0:8ad47e2b6f00 | 615 | |
igor_v | 0:8ad47e2b6f00 | 616 | |
igor_v | 0:8ad47e2b6f00 | 617 | /** \brief Get xPSR Register |
igor_v | 0:8ad47e2b6f00 | 618 | |
igor_v | 0:8ad47e2b6f00 | 619 | This function returns the content of the xPSR Register. |
igor_v | 0:8ad47e2b6f00 | 620 | |
igor_v | 0:8ad47e2b6f00 | 621 | \return xPSR Register value |
igor_v | 0:8ad47e2b6f00 | 622 | */ |
igor_v | 0:8ad47e2b6f00 | 623 | __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_xPSR(void) |
igor_v | 0:8ad47e2b6f00 | 624 | { |
igor_v | 0:8ad47e2b6f00 | 625 | uint32_t result; |
igor_v | 0:8ad47e2b6f00 | 626 | |
igor_v | 0:8ad47e2b6f00 | 627 | __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); |
igor_v | 0:8ad47e2b6f00 | 628 | return(result); |
igor_v | 0:8ad47e2b6f00 | 629 | } |
igor_v | 0:8ad47e2b6f00 | 630 | |
igor_v | 0:8ad47e2b6f00 | 631 | |
igor_v | 0:8ad47e2b6f00 | 632 | /** \brief Get Process Stack Pointer |
igor_v | 0:8ad47e2b6f00 | 633 | |
igor_v | 0:8ad47e2b6f00 | 634 | This function returns the current value of the Process Stack Pointer (PSP). |
igor_v | 0:8ad47e2b6f00 | 635 | |
igor_v | 0:8ad47e2b6f00 | 636 | \return PSP Register value |
igor_v | 0:8ad47e2b6f00 | 637 | */ |
igor_v | 0:8ad47e2b6f00 | 638 | __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PSP(void) |
igor_v | 0:8ad47e2b6f00 | 639 | { |
igor_v | 0:8ad47e2b6f00 | 640 | register uint32_t result; |
igor_v | 0:8ad47e2b6f00 | 641 | |
igor_v | 0:8ad47e2b6f00 | 642 | __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); |
igor_v | 0:8ad47e2b6f00 | 643 | return(result); |
igor_v | 0:8ad47e2b6f00 | 644 | } |
igor_v | 0:8ad47e2b6f00 | 645 | |
igor_v | 0:8ad47e2b6f00 | 646 | |
igor_v | 0:8ad47e2b6f00 | 647 | /** \brief Set Process Stack Pointer |
igor_v | 0:8ad47e2b6f00 | 648 | |
igor_v | 0:8ad47e2b6f00 | 649 | This function assigns the given value to the Process Stack Pointer (PSP). |
igor_v | 0:8ad47e2b6f00 | 650 | |
igor_v | 0:8ad47e2b6f00 | 651 | \param [in] topOfProcStack Process Stack Pointer value to set |
igor_v | 0:8ad47e2b6f00 | 652 | */ |
igor_v | 0:8ad47e2b6f00 | 653 | __attribute__( ( always_inline ) ) static __INLINE void __set_PSP(uint32_t topOfProcStack) |
igor_v | 0:8ad47e2b6f00 | 654 | { |
igor_v | 0:8ad47e2b6f00 | 655 | __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) ); |
igor_v | 0:8ad47e2b6f00 | 656 | } |
igor_v | 0:8ad47e2b6f00 | 657 | |
igor_v | 0:8ad47e2b6f00 | 658 | |
igor_v | 0:8ad47e2b6f00 | 659 | /** \brief Get Main Stack Pointer |
igor_v | 0:8ad47e2b6f00 | 660 | |
igor_v | 0:8ad47e2b6f00 | 661 | This function returns the current value of the Main Stack Pointer (MSP). |
igor_v | 0:8ad47e2b6f00 | 662 | |
igor_v | 0:8ad47e2b6f00 | 663 | \return MSP Register value |
igor_v | 0:8ad47e2b6f00 | 664 | */ |
igor_v | 0:8ad47e2b6f00 | 665 | __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_MSP(void) |
igor_v | 0:8ad47e2b6f00 | 666 | { |
igor_v | 0:8ad47e2b6f00 | 667 | register uint32_t result; |
igor_v | 0:8ad47e2b6f00 | 668 | |
igor_v | 0:8ad47e2b6f00 | 669 | __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); |
igor_v | 0:8ad47e2b6f00 | 670 | return(result); |
igor_v | 0:8ad47e2b6f00 | 671 | } |
igor_v | 0:8ad47e2b6f00 | 672 | |
igor_v | 0:8ad47e2b6f00 | 673 | |
igor_v | 0:8ad47e2b6f00 | 674 | /** \brief Set Main Stack Pointer |
igor_v | 0:8ad47e2b6f00 | 675 | |
igor_v | 0:8ad47e2b6f00 | 676 | This function assigns the given value to the Main Stack Pointer (MSP). |
igor_v | 0:8ad47e2b6f00 | 677 | |
igor_v | 0:8ad47e2b6f00 | 678 | \param [in] topOfMainStack Main Stack Pointer value to set |
igor_v | 0:8ad47e2b6f00 | 679 | */ |
igor_v | 0:8ad47e2b6f00 | 680 | __attribute__( ( always_inline ) ) static __INLINE void __set_MSP(uint32_t topOfMainStack) |
igor_v | 0:8ad47e2b6f00 | 681 | { |
igor_v | 0:8ad47e2b6f00 | 682 | __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) ); |
igor_v | 0:8ad47e2b6f00 | 683 | } |
igor_v | 0:8ad47e2b6f00 | 684 | |
igor_v | 0:8ad47e2b6f00 | 685 | |
igor_v | 0:8ad47e2b6f00 | 686 | /** \brief Get Priority Mask |
igor_v | 0:8ad47e2b6f00 | 687 | |
igor_v | 0:8ad47e2b6f00 | 688 | This function returns the current state of the priority mask bit from the Priority Mask Register. |
igor_v | 0:8ad47e2b6f00 | 689 | |
igor_v | 0:8ad47e2b6f00 | 690 | \return Priority Mask value |
igor_v | 0:8ad47e2b6f00 | 691 | */ |
igor_v | 0:8ad47e2b6f00 | 692 | __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PRIMASK(void) |
igor_v | 0:8ad47e2b6f00 | 693 | { |
igor_v | 0:8ad47e2b6f00 | 694 | uint32_t result; |
igor_v | 0:8ad47e2b6f00 | 695 | |
igor_v | 0:8ad47e2b6f00 | 696 | __ASM volatile ("MRS %0, primask" : "=r" (result) ); |
igor_v | 0:8ad47e2b6f00 | 697 | return(result); |
igor_v | 0:8ad47e2b6f00 | 698 | } |
igor_v | 0:8ad47e2b6f00 | 699 | |
igor_v | 0:8ad47e2b6f00 | 700 | |
igor_v | 0:8ad47e2b6f00 | 701 | /** \brief Set Priority Mask |
igor_v | 0:8ad47e2b6f00 | 702 | |
igor_v | 0:8ad47e2b6f00 | 703 | This function assigns the given value to the Priority Mask Register. |
igor_v | 0:8ad47e2b6f00 | 704 | |
igor_v | 0:8ad47e2b6f00 | 705 | \param [in] priMask Priority Mask |
igor_v | 0:8ad47e2b6f00 | 706 | */ |
igor_v | 0:8ad47e2b6f00 | 707 | __attribute__( ( always_inline ) ) static __INLINE void __set_PRIMASK(uint32_t priMask) |
igor_v | 0:8ad47e2b6f00 | 708 | { |
igor_v | 0:8ad47e2b6f00 | 709 | __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); |
igor_v | 0:8ad47e2b6f00 | 710 | } |
igor_v | 0:8ad47e2b6f00 | 711 | |
igor_v | 0:8ad47e2b6f00 | 712 | |
igor_v | 0:8ad47e2b6f00 | 713 | #if (__CORTEX_M >= 0x03) |
igor_v | 0:8ad47e2b6f00 | 714 | |
igor_v | 0:8ad47e2b6f00 | 715 | /** \brief Enable FIQ |
igor_v | 0:8ad47e2b6f00 | 716 | |
igor_v | 0:8ad47e2b6f00 | 717 | This function enables FIQ interrupts by clearing the F-bit in the CPSR. |
igor_v | 0:8ad47e2b6f00 | 718 | Can only be executed in Privileged modes. |
igor_v | 0:8ad47e2b6f00 | 719 | */ |
igor_v | 0:8ad47e2b6f00 | 720 | __attribute__( ( always_inline ) ) static __INLINE void __enable_fault_irq(void) |
igor_v | 0:8ad47e2b6f00 | 721 | { |
igor_v | 0:8ad47e2b6f00 | 722 | __ASM volatile ("cpsie f"); |
igor_v | 0:8ad47e2b6f00 | 723 | } |
igor_v | 0:8ad47e2b6f00 | 724 | |
igor_v | 0:8ad47e2b6f00 | 725 | |
igor_v | 0:8ad47e2b6f00 | 726 | /** \brief Disable FIQ |
igor_v | 0:8ad47e2b6f00 | 727 | |
igor_v | 0:8ad47e2b6f00 | 728 | This function disables FIQ interrupts by setting the F-bit in the CPSR. |
igor_v | 0:8ad47e2b6f00 | 729 | Can only be executed in Privileged modes. |
igor_v | 0:8ad47e2b6f00 | 730 | */ |
igor_v | 0:8ad47e2b6f00 | 731 | __attribute__( ( always_inline ) ) static __INLINE void __disable_fault_irq(void) |
igor_v | 0:8ad47e2b6f00 | 732 | { |
igor_v | 0:8ad47e2b6f00 | 733 | __ASM volatile ("cpsid f"); |
igor_v | 0:8ad47e2b6f00 | 734 | } |
igor_v | 0:8ad47e2b6f00 | 735 | |
igor_v | 0:8ad47e2b6f00 | 736 | |
igor_v | 0:8ad47e2b6f00 | 737 | /** \brief Get Base Priority |
igor_v | 0:8ad47e2b6f00 | 738 | |
igor_v | 0:8ad47e2b6f00 | 739 | This function returns the current value of the Base Priority register. |
igor_v | 0:8ad47e2b6f00 | 740 | |
igor_v | 0:8ad47e2b6f00 | 741 | \return Base Priority register value |
igor_v | 0:8ad47e2b6f00 | 742 | */ |
igor_v | 0:8ad47e2b6f00 | 743 | __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_BASEPRI(void) |
igor_v | 0:8ad47e2b6f00 | 744 | { |
igor_v | 0:8ad47e2b6f00 | 745 | uint32_t result; |
igor_v | 0:8ad47e2b6f00 | 746 | |
igor_v | 0:8ad47e2b6f00 | 747 | __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); |
igor_v | 0:8ad47e2b6f00 | 748 | return(result); |
igor_v | 0:8ad47e2b6f00 | 749 | } |
igor_v | 0:8ad47e2b6f00 | 750 | |
igor_v | 0:8ad47e2b6f00 | 751 | |
igor_v | 0:8ad47e2b6f00 | 752 | /** \brief Set Base Priority |
igor_v | 0:8ad47e2b6f00 | 753 | |
igor_v | 0:8ad47e2b6f00 | 754 | This function assigns the given value to the Base Priority register. |
igor_v | 0:8ad47e2b6f00 | 755 | |
igor_v | 0:8ad47e2b6f00 | 756 | \param [in] basePri Base Priority value to set |
igor_v | 0:8ad47e2b6f00 | 757 | */ |
igor_v | 0:8ad47e2b6f00 | 758 | __attribute__( ( always_inline ) ) static __INLINE void __set_BASEPRI(uint32_t value) |
igor_v | 0:8ad47e2b6f00 | 759 | { |
igor_v | 0:8ad47e2b6f00 | 760 | __ASM volatile ("MSR basepri, %0" : : "r" (value) ); |
igor_v | 0:8ad47e2b6f00 | 761 | } |
igor_v | 0:8ad47e2b6f00 | 762 | |
igor_v | 0:8ad47e2b6f00 | 763 | |
igor_v | 0:8ad47e2b6f00 | 764 | /** \brief Get Fault Mask |
igor_v | 0:8ad47e2b6f00 | 765 | |
igor_v | 0:8ad47e2b6f00 | 766 | This function returns the current value of the Fault Mask register. |
igor_v | 0:8ad47e2b6f00 | 767 | |
igor_v | 0:8ad47e2b6f00 | 768 | \return Fault Mask register value |
igor_v | 0:8ad47e2b6f00 | 769 | */ |
igor_v | 0:8ad47e2b6f00 | 770 | __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FAULTMASK(void) |
igor_v | 0:8ad47e2b6f00 | 771 | { |
igor_v | 0:8ad47e2b6f00 | 772 | uint32_t result; |
igor_v | 0:8ad47e2b6f00 | 773 | |
igor_v | 0:8ad47e2b6f00 | 774 | __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); |
igor_v | 0:8ad47e2b6f00 | 775 | return(result); |
igor_v | 0:8ad47e2b6f00 | 776 | } |
igor_v | 0:8ad47e2b6f00 | 777 | |
igor_v | 0:8ad47e2b6f00 | 778 | |
igor_v | 0:8ad47e2b6f00 | 779 | /** \brief Set Fault Mask |
igor_v | 0:8ad47e2b6f00 | 780 | |
igor_v | 0:8ad47e2b6f00 | 781 | This function assigns the given value to the Fault Mask register. |
igor_v | 0:8ad47e2b6f00 | 782 | |
igor_v | 0:8ad47e2b6f00 | 783 | \param [in] faultMask Fault Mask value to set |
igor_v | 0:8ad47e2b6f00 | 784 | */ |
igor_v | 0:8ad47e2b6f00 | 785 | __attribute__( ( always_inline ) ) static __INLINE void __set_FAULTMASK(uint32_t faultMask) |
igor_v | 0:8ad47e2b6f00 | 786 | { |
igor_v | 0:8ad47e2b6f00 | 787 | __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); |
igor_v | 0:8ad47e2b6f00 | 788 | } |
igor_v | 0:8ad47e2b6f00 | 789 | |
igor_v | 0:8ad47e2b6f00 | 790 | #endif /* (__CORTEX_M >= 0x03) */ |
igor_v | 0:8ad47e2b6f00 | 791 | |
igor_v | 0:8ad47e2b6f00 | 792 | |
igor_v | 0:8ad47e2b6f00 | 793 | #if (__CORTEX_M == 0x04) |
igor_v | 0:8ad47e2b6f00 | 794 | |
igor_v | 0:8ad47e2b6f00 | 795 | /** \brief Get FPSCR |
igor_v | 0:8ad47e2b6f00 | 796 | |
igor_v | 0:8ad47e2b6f00 | 797 | This function returns the current value of the Floating Point Status/Control register. |
igor_v | 0:8ad47e2b6f00 | 798 | |
igor_v | 0:8ad47e2b6f00 | 799 | \return Floating Point Status/Control register value |
igor_v | 0:8ad47e2b6f00 | 800 | */ |
igor_v | 0:8ad47e2b6f00 | 801 | __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void) |
igor_v | 0:8ad47e2b6f00 | 802 | { |
igor_v | 0:8ad47e2b6f00 | 803 | #if (__FPU_PRESENT == 1) |
igor_v | 0:8ad47e2b6f00 | 804 | uint32_t result; |
igor_v | 0:8ad47e2b6f00 | 805 | |
igor_v | 0:8ad47e2b6f00 | 806 | __ASM volatile ("MRS %0, fpscr" : "=r" (result) ); |
igor_v | 0:8ad47e2b6f00 | 807 | return(result); |
igor_v | 0:8ad47e2b6f00 | 808 | #else |
igor_v | 0:8ad47e2b6f00 | 809 | return(0); |
igor_v | 0:8ad47e2b6f00 | 810 | #endif |
igor_v | 0:8ad47e2b6f00 | 811 | } |
igor_v | 0:8ad47e2b6f00 | 812 | |
igor_v | 0:8ad47e2b6f00 | 813 | |
igor_v | 0:8ad47e2b6f00 | 814 | /** \brief Set FPSCR |
igor_v | 0:8ad47e2b6f00 | 815 | |
igor_v | 0:8ad47e2b6f00 | 816 | This function assigns the given value to the Floating Point Status/Control register. |
igor_v | 0:8ad47e2b6f00 | 817 | |
igor_v | 0:8ad47e2b6f00 | 818 | \param [in] fpscr Floating Point Status/Control value to set |
igor_v | 0:8ad47e2b6f00 | 819 | */ |
igor_v | 0:8ad47e2b6f00 | 820 | __attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr) |
igor_v | 0:8ad47e2b6f00 | 821 | { |
igor_v | 0:8ad47e2b6f00 | 822 | #if (__FPU_PRESENT == 1) |
igor_v | 0:8ad47e2b6f00 | 823 | __ASM volatile ("MSR fpscr, %0" : : "r" (fpscr) ); |
igor_v | 0:8ad47e2b6f00 | 824 | #endif |
igor_v | 0:8ad47e2b6f00 | 825 | } |
igor_v | 0:8ad47e2b6f00 | 826 | |
igor_v | 0:8ad47e2b6f00 | 827 | #endif /* (__CORTEX_M == 0x04) */ |
igor_v | 0:8ad47e2b6f00 | 828 | |
igor_v | 0:8ad47e2b6f00 | 829 | |
igor_v | 0:8ad47e2b6f00 | 830 | #elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/ |
igor_v | 0:8ad47e2b6f00 | 831 | /* TASKING carm specific functions */ |
igor_v | 0:8ad47e2b6f00 | 832 | |
igor_v | 0:8ad47e2b6f00 | 833 | /* |
igor_v | 0:8ad47e2b6f00 | 834 | * The CMSIS functions have been implemented as intrinsics in the compiler. |
igor_v | 0:8ad47e2b6f00 | 835 | * Please use "carm -?i" to get an up to date list of all instrinsics, |
igor_v | 0:8ad47e2b6f00 | 836 | * Including the CMSIS ones. |
igor_v | 0:8ad47e2b6f00 | 837 | */ |
igor_v | 0:8ad47e2b6f00 | 838 | |
igor_v | 0:8ad47e2b6f00 | 839 | #endif |
igor_v | 0:8ad47e2b6f00 | 840 | |
igor_v | 0:8ad47e2b6f00 | 841 | /*@} end of CMSIS_Core_RegAccFunctions */ |
igor_v | 0:8ad47e2b6f00 | 842 | |
igor_v | 0:8ad47e2b6f00 | 843 | |
igor_v | 0:8ad47e2b6f00 | 844 | #endif /* __CORE_CMFUNC_H__ */ |
igor_v | 0:8ad47e2b6f00 | 845 |