stm32f413h_discovery_psram.c

00001 /**
00002   ******************************************************************************
00003   * @file    stm32f413h_discovery_psram.c
00004   * @author  MCD Application Team
00005   * @brief   This file includes the PSRAM driver for the IS61WV51216BLL-10MLI memory 
00006   *          device mounted on STM32F413H-DISCOVERY boards.
00007   @verbatim
00008   How To use this driver:
00009   -----------------------
00010    - This driver is used to drive the IS61WV51216BLL-10M PSRAM external memory mounted
00011      on STM32F413H-DisCovERYevaluation board.
00012    - This driver does not need a specific component driver for the PSRAM device
00013      to be included with.
00014 
00015   Driver description:
00016   ------------------
00017   + Initialization steps:
00018      o Initialize the PSRAM external memory using the BSP_PSRAM_Init() function. This 
00019        function includes the MSP layer hardware resources initialization and the
00020        FSMC controller configuration to interface with the external PSRAM memory.
00021   
00022   + PSRAM read/write operations
00023      o PSRAM external memory can be accessed with read/write operations once it is
00024        initialized.
00025        Read/write operation can be performed with AHB access using the functions
00026        BSP_PSRAM_ReadData()/BSP_PSRAM_WriteData(), or by DMA transfer using the functions
00027        BSP_PSRAM_ReadData_DMA()/BSP_PSRAM_WriteData_DMA().
00028      o The AHB access is performed with 16-bit width transaction, the DMA transfer
00029        configuration is fixed at single (no burst) halfword transfer 
00030        (see the PSRAM_MspInit() static function).
00031      o User can implement his own functions for read/write access with his desired 
00032        configurations.
00033      o If interrupt mode is used for DMA transfer, the function BSP_PSRAM_DMA_IRQHandler()
00034        is called in IRQ handler file, to serve the generated interrupt once the DMA 
00035        transfer is complete.
00036   @endverbatim
00037   ******************************************************************************
00038   * @attention
00039   *
00040   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00041   *
00042   * Redistribution and use in source and binary forms, with or without modification,
00043   * are permitted provided that the following conditions are met:
00044   *   1. Redistributions of source code must retain the above copyright notice,
00045   *      this list of conditions and the following disclaimer.
00046   *   2. Redistributions in binary form must reproduce the above copyright notice,
00047   *      this list of conditions and the following disclaimer in the documentation
00048   *      and/or other materials provided with the distribution.
00049   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00050   *      may be used to endorse or promote products derived from this software
00051   *      without specific prior written permission.
00052   *
00053   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00054   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00055   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00056   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00057   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00058   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00059   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00060   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00061   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00062   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00063   *
00064   ******************************************************************************
00065   */
00066 
00067 /* Includes ------------------------------------------------------------------*/
00068 #include "stm32f413h_discovery_psram.h"
00069 
00070 /** @addtogroup BSP
00071   * @{
00072   */
00073 
00074 /** @addtogroup STM32F413H_DISCOVERY
00075   * @{
00076   */ 
00077   
00078 /** @defgroup STM32F413H_DISCOVERY_PSRAM STM32F413H_DISCOVERY PSRAM
00079   * @{
00080   */ 
00081 
00082 /** @defgroup STM32F413H_DISCOVERY_PSRAM_Private_Variables STM32F413H DISCOVERY PSRAM Private Variables
00083   * @{
00084   */       
00085 SRAM_HandleTypeDef psramHandle;
00086 static FSMC_NORSRAM_TimingTypeDef Timing;
00087 
00088 /**
00089   * @}
00090   */ 
00091     
00092 /** @defgroup STM32F413H_DISCOVERY_PSRAM_Private_Functions STM32F413H DISCOVERY PSRAM Private Functions
00093   * @{
00094   */ 
00095 
00096 /**
00097   * @brief  Initializes the PSRAM device.
00098   * @retval PSRAM status
00099   */
00100 uint8_t BSP_PSRAM_Init(void)
00101 { 
00102   static uint8_t psram_status = PSRAM_ERROR;
00103   /* SRAM device configuration */
00104   psramHandle.Instance = FSMC_NORSRAM_DEVICE;
00105   psramHandle.Extended = FSMC_NORSRAM_EXTENDED_DEVICE;
00106   
00107   /* PSRAM device configuration */
00108   /* Timing configuration derived from system clock (up to 100Mhz)*/
00109   Timing.AddressSetupTime      = 3;
00110   Timing.AddressHoldTime       = 1;
00111   Timing.DataSetupTime         = 4;
00112   Timing.BusTurnAroundDuration = 1;
00113   Timing.CLKDivision           = 2;
00114   Timing.DataLatency           = 2;
00115   Timing.AccessMode            = FSMC_ACCESS_MODE_A;
00116   
00117   psramHandle.Init.NSBank             = FSMC_NORSRAM_BANK1;
00118   psramHandle.Init.DataAddressMux     = FSMC_DATA_ADDRESS_MUX_DISABLE;
00119   psramHandle.Init.MemoryType         = FSMC_MEMORY_TYPE_SRAM;
00120   psramHandle.Init.MemoryDataWidth    = PSRAM_MEMORY_WIDTH;
00121   psramHandle.Init.BurstAccessMode    = PSRAM_BURSTACCESS;
00122   psramHandle.Init.WaitSignalPolarity = FSMC_WAIT_SIGNAL_POLARITY_LOW;
00123   psramHandle.Init.WaitSignalActive   = FSMC_WAIT_TIMING_BEFORE_WS;
00124   psramHandle.Init.WriteOperation     = FSMC_WRITE_OPERATION_ENABLE;
00125   psramHandle.Init.WaitSignal         = FSMC_WAIT_SIGNAL_DISABLE;
00126   psramHandle.Init.ExtendedMode       = FSMC_EXTENDED_MODE_DISABLE;
00127   psramHandle.Init.AsynchronousWait   = FSMC_ASYNCHRONOUS_WAIT_DISABLE;
00128   psramHandle.Init.WriteBurst         = PSRAM_WRITEBURST;
00129   psramHandle.Init.ContinuousClock    = CONTINUOUSCLOCK_FEATURE;
00130     
00131   /* PSRAM controller initialization */
00132   BSP_PSRAM_MspInit(&psramHandle, NULL); /* __weak function can be rewritten by the application */
00133   if(HAL_SRAM_Init(&psramHandle, &Timing, &Timing) != HAL_OK)
00134   {
00135     psram_status = PSRAM_ERROR;
00136   }
00137   else
00138   {
00139     psram_status = PSRAM_OK;
00140   }
00141   return psram_status;
00142 }
00143 
00144 /**
00145   * @brief  DeInitializes the PSRAM device.
00146   * @retval PSRAM status
00147   */
00148 uint8_t BSP_PSRAM_DeInit(void)
00149 { 
00150   static uint8_t psram_status = PSRAM_ERROR;
00151   /* PSRAM device de-initialization */
00152   psramHandle.Instance = FSMC_NORSRAM_DEVICE;
00153   psramHandle.Extended = FSMC_NORSRAM_EXTENDED_DEVICE;
00154 
00155   if(HAL_SRAM_DeInit(&psramHandle) != HAL_OK)
00156   {
00157     psram_status = PSRAM_ERROR;
00158   }
00159   else
00160   {
00161     psram_status = PSRAM_OK;
00162   }
00163   
00164   /* PSRAM controller de-initialization */
00165   BSP_PSRAM_MspDeInit(&psramHandle, NULL);
00166   
00167   return psram_status;
00168 }
00169 
00170 /**
00171   * @brief  Reads an amount of data from the PSRAM device in polling mode.
00172   * @param  uwStartAddress: Read start address
00173   * @param  pData: Pointer to data to be read
00174   * @param  uwDataSize: Size of read data from the memory   
00175   * @retval PSRAM status
00176   */
00177 uint8_t BSP_PSRAM_ReadData(uint32_t uwStartAddress, uint16_t *pData, uint32_t uwDataSize)
00178 { 
00179   if(HAL_SRAM_Read_16b(&psramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)
00180   {
00181     return PSRAM_ERROR;
00182   }
00183   else
00184   {
00185     return PSRAM_OK;
00186   }
00187 }
00188 
00189 /**
00190   * @brief  Reads an amount of data from the PSRAM device in DMA mode.
00191   * @param  uwStartAddress: Read start address
00192   * @param  pData: Pointer to data to be read
00193   * @param  uwDataSize: Size of read data from the memory   
00194   * @retval PSRAM status
00195   */
00196 uint8_t BSP_PSRAM_ReadData_DMA(uint32_t uwStartAddress, uint16_t *pData, uint32_t uwDataSize)
00197 {
00198   if(HAL_SRAM_Read_DMA(&psramHandle, (uint32_t *)uwStartAddress, (uint32_t *)pData, uwDataSize) != HAL_OK)
00199   {
00200     return PSRAM_ERROR;
00201   }
00202   else
00203   {
00204     return PSRAM_OK;
00205   }
00206 }
00207 
00208 /**
00209   * @brief  Writes an amount of data from the PSRAM device in polling mode.
00210   * @param  uwStartAddress: Write start address
00211   * @param  pData: Pointer to data to be written
00212   * @param  uwDataSize: Size of written data from the memory   
00213   * @retval PSRAM status
00214   */
00215 uint8_t BSP_PSRAM_WriteData(uint32_t uwStartAddress, uint16_t *pData, uint32_t uwDataSize) 
00216 { 
00217   if(HAL_SRAM_Write_16b(&psramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)
00218   {
00219     return PSRAM_ERROR;
00220   }
00221   else
00222   {
00223     return PSRAM_OK;
00224   }
00225 }
00226 
00227 /**
00228   * @brief  Writes an amount of data from the PSRAM device in DMA mode.
00229   * @param  uwStartAddress: Write start address
00230   * @param  pData: Pointer to data to be written
00231   * @param  uwDataSize: Size of written data from the memory   
00232   * @retval PSRAM status
00233   */
00234 uint8_t BSP_PSRAM_WriteData_DMA(uint32_t uwStartAddress, uint16_t *pData, uint32_t uwDataSize) 
00235 {
00236   if(HAL_SRAM_Write_DMA(&psramHandle, (uint32_t *)uwStartAddress, (uint32_t *)pData, uwDataSize) != HAL_OK)
00237   {
00238     return PSRAM_ERROR;
00239   }
00240   else
00241   {
00242     return PSRAM_OK;
00243   } 
00244 }
00245 
00246 /**
00247   * @brief  Initializes PSRAM MSP.
00248   * @param  hsram: PSRAM handle
00249   * @param  Params : pointer on additional configuration parameters, can be NULL.
00250   */
00251 __weak void BSP_PSRAM_MspInit(SRAM_HandleTypeDef  *hsram, void *Params)
00252 {  
00253   static DMA_HandleTypeDef dma_handle;
00254   GPIO_InitTypeDef gpio_init_structure;
00255   
00256   /* Prevent unused argument(s) compilation warning */
00257   UNUSED(Params);
00258 
00259   /* Enable FSMC clock */
00260   __HAL_RCC_FSMC_CLK_ENABLE();
00261   
00262   /* Enable chosen DMAx clock */
00263   PSRAM_DMAx_CLK_ENABLE();
00264   
00265   /* Enable GPIOs clock */
00266   __HAL_RCC_GPIOD_CLK_ENABLE();
00267   __HAL_RCC_GPIOE_CLK_ENABLE();
00268   __HAL_RCC_GPIOF_CLK_ENABLE();
00269   __HAL_RCC_GPIOG_CLK_ENABLE();
00270   
00271   /* Common GPIO configuration */
00272   gpio_init_structure.Mode      = GPIO_MODE_AF_PP;
00273   gpio_init_structure.Pull      = GPIO_PULLUP;
00274   gpio_init_structure.Speed     = GPIO_SPEED_FREQ_VERY_HIGH;
00275   gpio_init_structure.Alternate = GPIO_AF12_FSMC;
00276   
00277   /* GPIOD configuration */
00278   gpio_init_structure.Pin   = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_7      |\
00279                               GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12   |\
00280                               GPIO_PIN_14 | GPIO_PIN_15;
00281   HAL_GPIO_Init(GPIOD, &gpio_init_structure);
00282 
00283   /* GPIOE configuration */  
00284   gpio_init_structure.Pin   = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_7  | GPIO_PIN_8 | GPIO_PIN_9     |\
00285                               GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\
00286                               GPIO_PIN_15;
00287   HAL_GPIO_Init(GPIOE, &gpio_init_structure);
00288   
00289   /* GPIOF configuration */  
00290   gpio_init_structure.Pin   = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2| GPIO_PIN_3 | GPIO_PIN_4       |\
00291                               GPIO_PIN_5 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15;
00292   HAL_GPIO_Init(GPIOF, &gpio_init_structure);
00293   
00294   /* GPIOG configuration */  
00295   gpio_init_structure.Pin   = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2| GPIO_PIN_3 | GPIO_PIN_4       |\
00296                               GPIO_PIN_5;
00297   HAL_GPIO_Init(GPIOG, &gpio_init_structure);
00298   
00299   /* Configure common DMA parameters */
00300   dma_handle.Init.Channel             = PSRAM_DMAx_CHANNEL;
00301   dma_handle.Init.Direction           = DMA_MEMORY_TO_MEMORY;
00302   dma_handle.Init.PeriphInc           = DMA_PINC_ENABLE;
00303   dma_handle.Init.MemInc              = DMA_MINC_ENABLE;
00304   dma_handle.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;
00305   dma_handle.Init.MemDataAlignment    = DMA_MDATAALIGN_HALFWORD;
00306   dma_handle.Init.Mode                = DMA_NORMAL;
00307   dma_handle.Init.Priority            = DMA_PRIORITY_HIGH;
00308   dma_handle.Init.FIFOMode            = DMA_FIFOMODE_DISABLE;
00309   dma_handle.Init.FIFOThreshold       = DMA_FIFO_THRESHOLD_FULL;
00310   dma_handle.Init.MemBurst            = DMA_MBURST_SINGLE;
00311   dma_handle.Init.PeriphBurst         = DMA_PBURST_SINGLE;
00312   
00313   dma_handle.Instance = PSRAM_DMAx_STREAM;
00314   
00315    /* Associate the DMA handle */
00316   __HAL_LINKDMA(hsram, hdma, dma_handle);
00317   
00318   /* Deinitialize the Stream for new transfer */
00319   HAL_DMA_DeInit(&dma_handle);
00320   
00321   /* Configure the DMA Stream */
00322   HAL_DMA_Init(&dma_handle);
00323   
00324   /* NVIC configuration for DMA transfer complete interrupt */
00325   HAL_NVIC_SetPriority(PSRAM_DMAx_IRQn, 0x0F, 0);
00326   HAL_NVIC_EnableIRQ(PSRAM_DMAx_IRQn);   
00327 }
00328 
00329 /**
00330   * @brief  DeInitializes SRAM MSP.
00331   * @param  hsram: SRAM handle
00332   * @param  Params : pointer on additional configuration parameters, can be NULL.
00333   * @retval None
00334   */
00335 __weak void BSP_PSRAM_MspDeInit(SRAM_HandleTypeDef *hsram, void *Params)
00336 {  
00337   /* Prevent unused argument(s) compilation warning */
00338   UNUSED(Params);
00339 
00340   /* Disable NVIC configuration for DMA interrupt */
00341   HAL_NVIC_DisableIRQ(PSRAM_DMAx_IRQn);
00342   
00343   if(hsram->Instance != NULL)
00344   {
00345     /* Deinitialize the stream for new transfer */
00346     HAL_DMA_DeInit(hsram->hdma);
00347   }
00348   
00349   /* GPIO pins clock, FSMC clock and DMA clock can be shut down in the applications
00350   by surcharging this __weak function */ 
00351 }
00352 /**
00353   * @}
00354   */  
00355   
00356 /**
00357   * @}
00358   */ 
00359   
00360 /**
00361   * @}
00362   */ 
00363   
00364 /**
00365   * @}
00366   */ 
00367 
00368 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/