mbed-dev - mbed library sources. With a patch for the can_api

Users » DangerousElectrician » Code » mbed-dev

mbed library sources. With a patch for the can_api

targets/cmsis/TARGET_NXP/TARGET_LPC43XX/LPC43xx.h@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:: <>
Date:: Fri Sep 02 15:07:44 2016 +0100
Revision:: 144:ef7eb2e8f9f7
Parent:: 0:9b334a45a8ff

This updates the lib to the mbed lib v125

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	144:ef7eb2e8f9f7	1	/*
<>	144:ef7eb2e8f9f7	2	* LPC43xx/LPC18xx MCU header
<>	144:ef7eb2e8f9f7	3	*
<>	144:ef7eb2e8f9f7	4	* Copyright(C) NXP Semiconductors, 2012
<>	144:ef7eb2e8f9f7	5	* All rights reserved.
<>	144:ef7eb2e8f9f7	6	*
<>	144:ef7eb2e8f9f7	7	* Software that is described herein is for illustrative purposes only
<>	144:ef7eb2e8f9f7	8	* which provides customers with programming information regarding the
<>	144:ef7eb2e8f9f7	9	* LPC products. This software is supplied "AS IS" without any warranties of
<>	144:ef7eb2e8f9f7	10	* any kind, and NXP Semiconductors and its licensor disclaim any and
<>	144:ef7eb2e8f9f7	11	* all warranties, express or implied, including all implied warranties of
<>	144:ef7eb2e8f9f7	12	* merchantability, fitness for a particular purpose and non-infringement of
<>	144:ef7eb2e8f9f7	13	* intellectual property rights. NXP Semiconductors assumes no responsibility
<>	144:ef7eb2e8f9f7	14	* or liability for the use of the software, conveys no license or rights under any
<>	144:ef7eb2e8f9f7	15	* patent, copyright, mask work right, or any other intellectual property rights in
<>	144:ef7eb2e8f9f7	16	* or to any products. NXP Semiconductors reserves the right to make changes
<>	144:ef7eb2e8f9f7	17	* in the software without notification. NXP Semiconductors also makes no
<>	144:ef7eb2e8f9f7	18	* representation or warranty that such application will be suitable for the
<>	144:ef7eb2e8f9f7	19	* specified use without further testing or modification.
<>	144:ef7eb2e8f9f7	20	*
<>	144:ef7eb2e8f9f7	21	* Permission to use, copy, modify, and distribute this software and its
<>	144:ef7eb2e8f9f7	22	* documentation is hereby granted, under NXP Semiconductors' and its
<>	144:ef7eb2e8f9f7	23	* licensor's relevant copyrights in the software, without fee, provided that it
<>	144:ef7eb2e8f9f7	24	* is used in conjunction with NXP Semiconductors microcontrollers. This
<>	144:ef7eb2e8f9f7	25	* copyright, permission, and disclaimer notice must appear in all copies of
<>	144:ef7eb2e8f9f7	26	* this code.
<>	144:ef7eb2e8f9f7	27	*
<>	144:ef7eb2e8f9f7	28	* Simplified version of NXP LPCOPEN LPC43XX/LPC18XX headers
<>	144:ef7eb2e8f9f7	29	* 05/15/13 Micromint USA <support@micromint.com>
<>	144:ef7eb2e8f9f7	30	*/
<>	144:ef7eb2e8f9f7	31
<>	144:ef7eb2e8f9f7	32	#ifndef __LPC43XX_H
<>	144:ef7eb2e8f9f7	33	#define __LPC43XX_H
<>	144:ef7eb2e8f9f7	34
<>	144:ef7eb2e8f9f7	35	#ifdef __cplusplus
<>	144:ef7eb2e8f9f7	36	extern "C" {
<>	144:ef7eb2e8f9f7	37	#endif
<>	144:ef7eb2e8f9f7	38
<>	144:ef7eb2e8f9f7	39	/* Treat __CORE_Mx as CORE_Mx */
<>	144:ef7eb2e8f9f7	40	#if defined(__CORTEX_M0) && !defined(CORE_M0)
<>	144:ef7eb2e8f9f7	41	#define CORE_M0
<>	144:ef7eb2e8f9f7	42	#endif
<>	144:ef7eb2e8f9f7	43	#if defined(__CORTEX_M3) && !defined(CORE_M3)
<>	144:ef7eb2e8f9f7	44	#define CORE_M3
<>	144:ef7eb2e8f9f7	45	#endif
<>	144:ef7eb2e8f9f7	46	/* Default to M4 core if no core explicitly declared */
<>	144:ef7eb2e8f9f7	47	#if !defined(CORE_M0) && !defined(CORE_M3)
<>	144:ef7eb2e8f9f7	48	#define CORE_M4
<>	144:ef7eb2e8f9f7	49	#endif
<>	144:ef7eb2e8f9f7	50
<>	144:ef7eb2e8f9f7	51	/* Define LPC18XX or LPC43XX according to core type */
<>	144:ef7eb2e8f9f7	52	#if (defined(CORE_M4) \|\| defined(CORE_M0)) && !defined(__LPC43XX__)
<>	144:ef7eb2e8f9f7	53	#define __LPC43XX__
<>	144:ef7eb2e8f9f7	54	#endif
<>	144:ef7eb2e8f9f7	55	#if defined(CORE_M3) && !defined(__LPC18XX__)
<>	144:ef7eb2e8f9f7	56	#define __LPC18XX__
<>	144:ef7eb2e8f9f7	57	#endif
<>	144:ef7eb2e8f9f7	58
<>	144:ef7eb2e8f9f7	59	/* Start of section using anonymous unions */
<>	144:ef7eb2e8f9f7	60	#if defined(__ARMCC_VERSION)
<>	144:ef7eb2e8f9f7	61	// Kill warning "#pragma push with no matching #pragma pop"
<>	144:ef7eb2e8f9f7	62	#pragma diag_suppress 2525
<>	144:ef7eb2e8f9f7	63	#pragma push
<>	144:ef7eb2e8f9f7	64	#pragma anon_unions
<>	144:ef7eb2e8f9f7	65	#elif defined(__CWCC__)
<>	144:ef7eb2e8f9f7	66	#pragma push
<>	144:ef7eb2e8f9f7	67	#pragma cpp_extensions on
<>	144:ef7eb2e8f9f7	68	#elif defined(__IAR_SYSTEMS_ICC__)
<>	144:ef7eb2e8f9f7	69	//#pragma push // FIXME not usable for IAR
<>	144:ef7eb2e8f9f7	70	#pragma language=extended
<>	144:ef7eb2e8f9f7	71	#else /* defined(__GNUC__) and others */
<>	144:ef7eb2e8f9f7	72	/* Assume anonymous unions are enabled by default */
<>	144:ef7eb2e8f9f7	73	#endif
<>	144:ef7eb2e8f9f7	74
<>	144:ef7eb2e8f9f7	75	#if defined(CORE_M4)
<>	144:ef7eb2e8f9f7	76	/* ---------------------------------------------------------------------------
<>	144:ef7eb2e8f9f7	77	* LPC43xx (M4 Core) Cortex CMSIS definitions
<>	144:ef7eb2e8f9f7	78	*/
<>	144:ef7eb2e8f9f7	79
<>	144:ef7eb2e8f9f7	80	#define __CM4_REV 0x0000 /* Cortex-M4 Core Revision */
<>	144:ef7eb2e8f9f7	81	#define __MPU_PRESENT 1 /* MPU present or not */
<>	144:ef7eb2e8f9f7	82	#define __NVIC_PRIO_BITS 3 /* Number of Bits used for Priority Levels */
<>	144:ef7eb2e8f9f7	83	#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
<>	144:ef7eb2e8f9f7	84	#define __FPU_PRESENT 1 /* FPU present or not */
<>	144:ef7eb2e8f9f7	85	#define CHIP_LPC43XX /* LPCOPEN compatibility */
<>	144:ef7eb2e8f9f7	86
<>	144:ef7eb2e8f9f7	87	/* ---------------------------------------------------------------------------
<>	144:ef7eb2e8f9f7	88	* LPC43xx peripheral interrupt numbers
<>	144:ef7eb2e8f9f7	89	*/
<>	144:ef7eb2e8f9f7	90
<>	144:ef7eb2e8f9f7	91	typedef enum {
<>	144:ef7eb2e8f9f7	92	/* --------------- Cortex-M4 Processor Exceptions Numbers ------------------- */
<>	144:ef7eb2e8f9f7	93	Reset_IRQn = -15,/* 1 Reset Vector, invoked on Power up and warm reset */
<>	144:ef7eb2e8f9f7	94	NonMaskableInt_IRQn = -14,/* 2 Non maskable Interrupt, cannot be stopped or preempted */
<>	144:ef7eb2e8f9f7	95	HardFault_IRQn = -13,/* 3 Hard Fault, all classes of Fault */
<>	144:ef7eb2e8f9f7	96	MemoryManagement_IRQn = -12,/* 4 Memory Management, MPU mismatch, including Access Violation and No Match */
<>	144:ef7eb2e8f9f7	97	BusFault_IRQn = -11,/* 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
<>	144:ef7eb2e8f9f7	98	UsageFault_IRQn = -10,/* 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
<>	144:ef7eb2e8f9f7	99	SVCall_IRQn = -5,/* 11 System Service Call via SVC instruction */
<>	144:ef7eb2e8f9f7	100	DebugMonitor_IRQn = -4,/* 12 Debug Monitor */
<>	144:ef7eb2e8f9f7	101	PendSV_IRQn = -2,/* 14 Pendable request for system service */
<>	144:ef7eb2e8f9f7	102	SysTick_IRQn = -1,/* 15 System Tick Timer */
<>	144:ef7eb2e8f9f7	103
<>	144:ef7eb2e8f9f7	104	/* ----------------- LPC18xx/43xx Specific Interrupt Numbers --------------------- */
<>	144:ef7eb2e8f9f7	105	DAC_IRQn = 0,/* 0 DAC */
<>	144:ef7eb2e8f9f7	106	M0CORE_IRQn = 1,/* 1 M0a */
<>	144:ef7eb2e8f9f7	107	DMA_IRQn = 2,/* 2 DMA */
<>	144:ef7eb2e8f9f7	108	RESERVED1_IRQn = 3,/* 3 EZH/EDM */
<>	144:ef7eb2e8f9f7	109	RESERVED2_IRQn = 4,
<>	144:ef7eb2e8f9f7	110	ETHERNET_IRQn = 5,/* 5 ETHERNET */
<>	144:ef7eb2e8f9f7	111	SDIO_IRQn = 6,/* 6 SDIO */
<>	144:ef7eb2e8f9f7	112	LCD_IRQn = 7,/* 7 LCD */
<>	144:ef7eb2e8f9f7	113	USB0_IRQn = 8,/* 8 USB0 */
<>	144:ef7eb2e8f9f7	114	USB1_IRQn = 9,/* 9 USB1 */
<>	144:ef7eb2e8f9f7	115	SCT_IRQn = 10,/* 10 SCT */
<>	144:ef7eb2e8f9f7	116	RITIMER_IRQn = 11,/* 11 RITIMER */
<>	144:ef7eb2e8f9f7	117	TIMER0_IRQn = 12,/* 12 TIMER0 */
<>	144:ef7eb2e8f9f7	118	TIMER1_IRQn = 13,/* 13 TIMER1 */
<>	144:ef7eb2e8f9f7	119	TIMER2_IRQn = 14,/* 14 TIMER2 */
<>	144:ef7eb2e8f9f7	120	TIMER3_IRQn = 15,/* 15 TIMER3 */
<>	144:ef7eb2e8f9f7	121	MCPWM_IRQn = 16,/* 16 MCPWM */
<>	144:ef7eb2e8f9f7	122	ADC0_IRQn = 17,/* 17 ADC0 */
<>	144:ef7eb2e8f9f7	123	I2C0_IRQn = 18,/* 18 I2C0 */
<>	144:ef7eb2e8f9f7	124	I2C1_IRQn = 19,/* 19 I2C1 */
<>	144:ef7eb2e8f9f7	125	SPI_INT_IRQn = 20,/* 20 SPI_INT */
<>	144:ef7eb2e8f9f7	126	ADC1_IRQn = 21,/* 21 ADC1 */
<>	144:ef7eb2e8f9f7	127	SSP0_IRQn = 22,/* 22 SSP0 */
<>	144:ef7eb2e8f9f7	128	SSP1_IRQn = 23,/* 23 SSP1 */
<>	144:ef7eb2e8f9f7	129	USART0_IRQn = 24,/* 24 USART0 */
<>	144:ef7eb2e8f9f7	130	UART1_IRQn = 25,/* 25 UART1 */
<>	144:ef7eb2e8f9f7	131	USART2_IRQn = 26,/* 26 USART2 */
<>	144:ef7eb2e8f9f7	132	USART3_IRQn = 27,/* 27 USART3 */
<>	144:ef7eb2e8f9f7	133	I2S0_IRQn = 28,/* 28 I2S0 */
<>	144:ef7eb2e8f9f7	134	I2S1_IRQn = 29,/* 29 I2S1 */
<>	144:ef7eb2e8f9f7	135	RESERVED4_IRQn = 30,
<>	144:ef7eb2e8f9f7	136	SGPIO_INT_IRQn = 31,/* 31 SGPIO_IINT */
<>	144:ef7eb2e8f9f7	137	PIN_INT0_IRQn = 32,/* 32 PIN_INT0 */
<>	144:ef7eb2e8f9f7	138	PIN_INT1_IRQn = 33,/* 33 PIN_INT1 */
<>	144:ef7eb2e8f9f7	139	PIN_INT2_IRQn = 34,/* 34 PIN_INT2 */
<>	144:ef7eb2e8f9f7	140	PIN_INT3_IRQn = 35,/* 35 PIN_INT3 */
<>	144:ef7eb2e8f9f7	141	PIN_INT4_IRQn = 36,/* 36 PIN_INT4 */
<>	144:ef7eb2e8f9f7	142	PIN_INT5_IRQn = 37,/* 37 PIN_INT5 */
<>	144:ef7eb2e8f9f7	143	PIN_INT6_IRQn = 38,/* 38 PIN_INT6 */
<>	144:ef7eb2e8f9f7	144	PIN_INT7_IRQn = 39,/* 39 PIN_INT7 */
<>	144:ef7eb2e8f9f7	145	GINT0_IRQn = 40,/* 40 GINT0 */
<>	144:ef7eb2e8f9f7	146	GINT1_IRQn = 41,/* 41 GINT1 */
<>	144:ef7eb2e8f9f7	147	EVENTROUTER_IRQn = 42,/* 42 EVENTROUTER */
<>	144:ef7eb2e8f9f7	148	C_CAN1_IRQn = 43,/* 43 C_CAN1 */
<>	144:ef7eb2e8f9f7	149	RESERVED6_IRQn = 44,
<>	144:ef7eb2e8f9f7	150	RESERVED7_IRQn = 45,/* 45 VADC */
<>	144:ef7eb2e8f9f7	151	ATIMER_IRQn = 46,/* 46 ATIMER */
<>	144:ef7eb2e8f9f7	152	RTC_IRQn = 47,/* 47 RTC */
<>	144:ef7eb2e8f9f7	153	RESERVED8_IRQn = 48,
<>	144:ef7eb2e8f9f7	154	WWDT_IRQn = 49,/* 49 WWDT */
<>	144:ef7eb2e8f9f7	155	RESERVED9_IRQn = 50,
<>	144:ef7eb2e8f9f7	156	C_CAN0_IRQn = 51,/* 51 C_CAN0 */
<>	144:ef7eb2e8f9f7	157	QEI_IRQn = 52,/* 52 QEI */
<>	144:ef7eb2e8f9f7	158	} IRQn_Type;
<>	144:ef7eb2e8f9f7	159
<>	144:ef7eb2e8f9f7	160	#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
<>	144:ef7eb2e8f9f7	161
<>	144:ef7eb2e8f9f7	162	#elif defined(CORE_M3)
<>	144:ef7eb2e8f9f7	163	/* ---------------------------------------------------------------------------
<>	144:ef7eb2e8f9f7	164	* LPC18xx (M3 Core) Cortex CMSIS definitions
<>	144:ef7eb2e8f9f7	165	*/
<>	144:ef7eb2e8f9f7	166	#define __MPU_PRESENT 1 /* MPU present or not */
<>	144:ef7eb2e8f9f7	167	#define __NVIC_PRIO_BITS 3 /* Number of Bits used for Priority Levels */
<>	144:ef7eb2e8f9f7	168	#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
<>	144:ef7eb2e8f9f7	169	#define __FPU_PRESENT 0 /* FPU present or not */
<>	144:ef7eb2e8f9f7	170	#define CHIP_LPC18XX /* LPCOPEN compatibility */
<>	144:ef7eb2e8f9f7	171
<>	144:ef7eb2e8f9f7	172	/* ---------------------------------------------------------------------------
<>	144:ef7eb2e8f9f7	173	* LPC18xx peripheral interrupt numbers
<>	144:ef7eb2e8f9f7	174	*/
<>	144:ef7eb2e8f9f7	175
<>	144:ef7eb2e8f9f7	176	typedef enum {
<>	144:ef7eb2e8f9f7	177	/* --------------- Cortex-M3 Processor Exceptions Numbers ------------------- */
<>	144:ef7eb2e8f9f7	178	Reset_IRQn = -15,/* 1 Reset Vector, invoked on Power up and warm reset */
<>	144:ef7eb2e8f9f7	179	NonMaskableInt_IRQn = -14,/* 2 Non maskable Interrupt, cannot be stopped or preempted */
<>	144:ef7eb2e8f9f7	180	HardFault_IRQn = -13,/* 3 Hard Fault, all classes of Fault */
<>	144:ef7eb2e8f9f7	181	MemoryManagement_IRQn = -12,/* 4 Memory Management, MPU mismatch, including Access Violation and No Match */
<>	144:ef7eb2e8f9f7	182	BusFault_IRQn = -11,/* 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
<>	144:ef7eb2e8f9f7	183	UsageFault_IRQn = -10,/* 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
<>	144:ef7eb2e8f9f7	184	SVCall_IRQn = -5,/* 11 System Service Call via SVC instruction */
<>	144:ef7eb2e8f9f7	185	DebugMonitor_IRQn = -4,/* 12 Debug Monitor */
<>	144:ef7eb2e8f9f7	186	PendSV_IRQn = -2,/* 14 Pendable request for system service */
<>	144:ef7eb2e8f9f7	187	SysTick_IRQn = -1,/* 15 System Tick Timer */
<>	144:ef7eb2e8f9f7	188
<>	144:ef7eb2e8f9f7	189	/* ----------------- LPC18xx/43xx Specific Interrupt Numbers --------------------- */
<>	144:ef7eb2e8f9f7	190	DAC_IRQn = 0,/* 0 DAC */
<>	144:ef7eb2e8f9f7	191	RESERVED0_IRQn = 1,
<>	144:ef7eb2e8f9f7	192	DMA_IRQn = 2,/* 2 DMA */
<>	144:ef7eb2e8f9f7	193	RESERVED1_IRQn = 3,/* 3 EZH/EDM */
<>	144:ef7eb2e8f9f7	194	RESERVED2_IRQn = 4,
<>	144:ef7eb2e8f9f7	195	ETHERNET_IRQn = 5,/* 5 ETHERNET */
<>	144:ef7eb2e8f9f7	196	SDIO_IRQn = 6,/* 6 SDIO */
<>	144:ef7eb2e8f9f7	197	LCD_IRQn = 7,/* 7 LCD */
<>	144:ef7eb2e8f9f7	198	USB0_IRQn = 8,/* 8 USB0 */
<>	144:ef7eb2e8f9f7	199	USB1_IRQn = 9,/* 9 USB1 */
<>	144:ef7eb2e8f9f7	200	SCT_IRQn = 10,/* 10 SCT */
<>	144:ef7eb2e8f9f7	201	RITIMER_IRQn = 11,/* 11 RITIMER */
<>	144:ef7eb2e8f9f7	202	TIMER0_IRQn = 12,/* 12 TIMER0 */
<>	144:ef7eb2e8f9f7	203	TIMER1_IRQn = 13,/* 13 TIMER1 */
<>	144:ef7eb2e8f9f7	204	TIMER2_IRQn = 14,/* 14 TIMER2 */
<>	144:ef7eb2e8f9f7	205	TIMER3_IRQn = 15,/* 15 TIMER3 */
<>	144:ef7eb2e8f9f7	206	MCPWM_IRQn = 16,/* 16 MCPWM */
<>	144:ef7eb2e8f9f7	207	ADC0_IRQn = 17,/* 17 ADC0 */
<>	144:ef7eb2e8f9f7	208	I2C0_IRQn = 18,/* 18 I2C0 */
<>	144:ef7eb2e8f9f7	209	I2C1_IRQn = 19,/* 19 I2C1 */
<>	144:ef7eb2e8f9f7	210	RESERVED3_IRQn = 20,
<>	144:ef7eb2e8f9f7	211	ADC1_IRQn = 21,/* 21 ADC1 */
<>	144:ef7eb2e8f9f7	212	SSP0_IRQn = 22,/* 22 SSP0 */
<>	144:ef7eb2e8f9f7	213	SSP1_IRQn = 23,/* 23 SSP1 */
<>	144:ef7eb2e8f9f7	214	USART0_IRQn = 24,/* 24 USART0 */
<>	144:ef7eb2e8f9f7	215	UART1_IRQn = 25,/* 25 UART1 */
<>	144:ef7eb2e8f9f7	216	USART2_IRQn = 26,/* 26 USART2 */
<>	144:ef7eb2e8f9f7	217	USART3_IRQn = 27,/* 27 USART3 */
<>	144:ef7eb2e8f9f7	218	I2S0_IRQn = 28,/* 28 I2S0 */
<>	144:ef7eb2e8f9f7	219	I2S1_IRQn = 29,/* 29 I2S1 */
<>	144:ef7eb2e8f9f7	220	RESERVED4_IRQn = 30,
<>	144:ef7eb2e8f9f7	221	RESERVED5_IRQn = 31,
<>	144:ef7eb2e8f9f7	222	PIN_INT0_IRQn = 32,/* 32 PIN_INT0 */
<>	144:ef7eb2e8f9f7	223	PIN_INT1_IRQn = 33,/* 33 PIN_INT1 */
<>	144:ef7eb2e8f9f7	224	PIN_INT2_IRQn = 34,/* 34 PIN_INT2 */
<>	144:ef7eb2e8f9f7	225	PIN_INT3_IRQn = 35,/* 35 PIN_INT3 */
<>	144:ef7eb2e8f9f7	226	PIN_INT4_IRQn = 36,/* 36 PIN_INT4 */
<>	144:ef7eb2e8f9f7	227	PIN_INT5_IRQn = 37,/* 37 PIN_INT5 */
<>	144:ef7eb2e8f9f7	228	PIN_INT6_IRQn = 38,/* 38 PIN_INT6 */
<>	144:ef7eb2e8f9f7	229	PIN_INT7_IRQn = 39,/* 39 PIN_INT7 */
<>	144:ef7eb2e8f9f7	230	GINT0_IRQn = 40,/* 40 GINT0 */
<>	144:ef7eb2e8f9f7	231	GINT1_IRQn = 41,/* 41 GINT1 */
<>	144:ef7eb2e8f9f7	232	EVENTROUTER_IRQn = 42,/* 42 EVENTROUTER */
<>	144:ef7eb2e8f9f7	233	C_CAN1_IRQn = 43,/* 43 C_CAN1 */
<>	144:ef7eb2e8f9f7	234	RESERVED6_IRQn = 44,
<>	144:ef7eb2e8f9f7	235	RESERVED7_IRQn = 45,/* 45 VADC */
<>	144:ef7eb2e8f9f7	236	ATIMER_IRQn = 46,/* 46 ATIMER */
<>	144:ef7eb2e8f9f7	237	RTC_IRQn = 47,/* 47 RTC */
<>	144:ef7eb2e8f9f7	238	RESERVED8_IRQn = 48,
<>	144:ef7eb2e8f9f7	239	WWDT_IRQn = 49,/* 49 WWDT */
<>	144:ef7eb2e8f9f7	240	RESERVED9_IRQn = 50,
<>	144:ef7eb2e8f9f7	241	C_CAN0_IRQn = 51,/* 51 C_CAN0 */
<>	144:ef7eb2e8f9f7	242	QEI_IRQn = 52,/* 52 QEI */
<>	144:ef7eb2e8f9f7	243	} IRQn_Type;
<>	144:ef7eb2e8f9f7	244
<>	144:ef7eb2e8f9f7	245	#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
<>	144:ef7eb2e8f9f7	246
<>	144:ef7eb2e8f9f7	247	#elif defined(CORE_M0)
<>	144:ef7eb2e8f9f7	248	/* ---------------------------------------------------------------------------
<>	144:ef7eb2e8f9f7	249	* LPC43xx (M0 Core) Cortex CMSIS definitions
<>	144:ef7eb2e8f9f7	250	*/
<>	144:ef7eb2e8f9f7	251
<>	144:ef7eb2e8f9f7	252	#define __MPU_PRESENT 0 /* MPU present or not */
<>	144:ef7eb2e8f9f7	253	#define __NVIC_PRIO_BITS 2 /* Number of Bits used for Priority Levels */
<>	144:ef7eb2e8f9f7	254	#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
<>	144:ef7eb2e8f9f7	255	#define __FPU_PRESENT 0 /* FPU present or not */
<>	144:ef7eb2e8f9f7	256	#define CHIP_LPC43XX /* LPCOPEN compatibility */
<>	144:ef7eb2e8f9f7	257
<>	144:ef7eb2e8f9f7	258	/* ---------------------------------------------------------------------------
<>	144:ef7eb2e8f9f7	259	* LPC43xx (M0 Core) peripheral interrupt numbers
<>	144:ef7eb2e8f9f7	260	*/
<>	144:ef7eb2e8f9f7	261
<>	144:ef7eb2e8f9f7	262	typedef enum {
<>	144:ef7eb2e8f9f7	263	/* --------------- Cortex-M0 Processor Exceptions Numbers ------------------- */
<>	144:ef7eb2e8f9f7	264	Reset_IRQn = -15,/* 1 Reset Vector, invoked on Power up and warm reset */
<>	144:ef7eb2e8f9f7	265	NonMaskableInt_IRQn = -14,/* 2 Non maskable Interrupt, cannot be stopped or preempted */
<>	144:ef7eb2e8f9f7	266	HardFault_IRQn = -13,/* 3 Hard Fault, all classes of Fault */
<>	144:ef7eb2e8f9f7	267	SVCall_IRQn = -5,/* 11 System Service Call via SVC instruction */
<>	144:ef7eb2e8f9f7	268	DebugMonitor_IRQn = -4,/* 12 Debug Monitor */
<>	144:ef7eb2e8f9f7	269	PendSV_IRQn = -2,/* 14 Pendable request for system service */
<>	144:ef7eb2e8f9f7	270	SysTick_IRQn = -1,/* 15 System Tick Timer */
<>	144:ef7eb2e8f9f7	271
<>	144:ef7eb2e8f9f7	272	/* ----------------- LPC18xx/43xx Specific Interrupt Numbers --------------------- */
<>	144:ef7eb2e8f9f7	273	DAC_IRQn = 0,/* 0 DAC */
<>	144:ef7eb2e8f9f7	274	M0_M4CORE_IRQn = 1,/* 1 M0a */
<>	144:ef7eb2e8f9f7	275	DMA_IRQn = 2,/* 2 DMA r */
<>	144:ef7eb2e8f9f7	276	RESERVED1_IRQn = 3,/* 3 EZH/EDM */
<>	144:ef7eb2e8f9f7	277	FLASHEEPROM_IRQn = 4,/* 4 ORed Flash EEPROM Bank A, B, EEPROM */
<>	144:ef7eb2e8f9f7	278	ETHERNET_IRQn = 5,/* 5 ETHERNET */
<>	144:ef7eb2e8f9f7	279	SDIO_IRQn = 6,/* 6 SDIO */
<>	144:ef7eb2e8f9f7	280	LCD_IRQn = 7,/* 7 LCD */
<>	144:ef7eb2e8f9f7	281	USB0_IRQn = 8,/* 8 USB0 */
<>	144:ef7eb2e8f9f7	282	USB1_IRQn = 9,/* 9 USB1 */
<>	144:ef7eb2e8f9f7	283	SCT_IRQn = 10,/* 10 SCT */
<>	144:ef7eb2e8f9f7	284	RITIMER_IRQn = 11,/* 11 ORed RITIMER, WDT */
<>	144:ef7eb2e8f9f7	285	TIMER0_IRQn = 12,/* 12 TIMER0 */
<>	144:ef7eb2e8f9f7	286	GINT1_IRQn = 13,/* 13 GINT1 */
<>	144:ef7eb2e8f9f7	287	PIN_INT4_IRQn = 14,/* 14 GPIO 4 */
<>	144:ef7eb2e8f9f7	288	TIMER3_IRQn = 15,/* 15 TIMER3 */
<>	144:ef7eb2e8f9f7	289	MCPWM_IRQn = 16,/* 16 MCPWM */
<>	144:ef7eb2e8f9f7	290	ADC0_IRQn = 17,/* 17 ADC0 */
<>	144:ef7eb2e8f9f7	291	I2C0_IRQn = 18,/* 18 ORed I2C0, I2C1 */
<>	144:ef7eb2e8f9f7	292	SGPIO_INT_IRQn = 19,/* 19 SGPIO */
<>	144:ef7eb2e8f9f7	293	SPI_INT_IRQn = 20,/* 20 SPI_INT */
<>	144:ef7eb2e8f9f7	294	ADC1_IRQn = 21,/* 21 ADC1 */
<>	144:ef7eb2e8f9f7	295	SSP0_IRQn = 22,/* 22 ORed SSP0, SSP1 */
<>	144:ef7eb2e8f9f7	296	EVENTROUTER_IRQn = 23,/* 23 EVENTROUTER */
<>	144:ef7eb2e8f9f7	297	USART0_IRQn = 24,/* 24 USART0 */
<>	144:ef7eb2e8f9f7	298	UART1_IRQn = 25,/* 25 UART1 */
<>	144:ef7eb2e8f9f7	299	USART2_IRQn = 26,/* 26 USART2 */
<>	144:ef7eb2e8f9f7	300	USART3_IRQn = 27,/* 27 USART3 */
<>	144:ef7eb2e8f9f7	301	I2S0_IRQn = 28,/* 28 ORed I2S0, I2S1 */
<>	144:ef7eb2e8f9f7	302	C_CAN0_IRQn = 29,/* 29 C_CAN0 */
<>	144:ef7eb2e8f9f7	303	I2S1_IRQn = 29,/* 29 I2S1 */
<>	144:ef7eb2e8f9f7	304	RESERVED2_IRQn = 30,
<>	144:ef7eb2e8f9f7	305	RESERVED3_IRQn = 31,
<>	144:ef7eb2e8f9f7	306	} IRQn_Type;
<>	144:ef7eb2e8f9f7	307
<>	144:ef7eb2e8f9f7	308	#include "core_cm0.h" /* Cortex-M4 processor and core peripherals */
<>	144:ef7eb2e8f9f7	309	#else
<>	144:ef7eb2e8f9f7	310	#error Please #define CORE_M0, CORE_M3 or CORE_M4
<>	144:ef7eb2e8f9f7	311	#endif
<>	144:ef7eb2e8f9f7	312
<>	144:ef7eb2e8f9f7	313	#include "system_LPC43xx.h"
<>	144:ef7eb2e8f9f7	314
<>	144:ef7eb2e8f9f7	315	/* ---------------------------------------------------------------------------
<>	144:ef7eb2e8f9f7	316	* State Configurable Timer register block structure
<>	144:ef7eb2e8f9f7	317	*/
<>	144:ef7eb2e8f9f7	318	#define LPC_SCT_BASE 0x40000000
<>	144:ef7eb2e8f9f7	319	#define CONFIG_SCT_nEV (16) /* Number of events */
<>	144:ef7eb2e8f9f7	320	#define CONFIG_SCT_nRG (16) /* Number of match/compare registers */
<>	144:ef7eb2e8f9f7	321	#define CONFIG_SCT_nOU (16) /* Number of outputs */
<>	144:ef7eb2e8f9f7	322
<>	144:ef7eb2e8f9f7	323	typedef struct {
<>	144:ef7eb2e8f9f7	324	__IO uint32_t CONFIG; /* Configuration Register */
<>	144:ef7eb2e8f9f7	325	union {
<>	144:ef7eb2e8f9f7	326	__IO uint32_t CTRL_U; /* Control Register */
<>	144:ef7eb2e8f9f7	327	struct {
<>	144:ef7eb2e8f9f7	328	__IO uint16_t CTRL_L; /* Low control register */
<>	144:ef7eb2e8f9f7	329	__IO uint16_t CTRL_H; /* High control register */
<>	144:ef7eb2e8f9f7	330	};
<>	144:ef7eb2e8f9f7	331
<>	144:ef7eb2e8f9f7	332	};
<>	144:ef7eb2e8f9f7	333
<>	144:ef7eb2e8f9f7	334	__IO uint16_t LIMIT_L; /* limit register for counter L */
<>	144:ef7eb2e8f9f7	335	__IO uint16_t LIMIT_H; /* limit register for counter H */
<>	144:ef7eb2e8f9f7	336	__IO uint16_t HALT_L; /* halt register for counter L */
<>	144:ef7eb2e8f9f7	337	__IO uint16_t HALT_H; /* halt register for counter H */
<>	144:ef7eb2e8f9f7	338	__IO uint16_t STOP_L; /* stop register for counter L */
<>	144:ef7eb2e8f9f7	339	__IO uint16_t STOP_H; /* stop register for counter H */
<>	144:ef7eb2e8f9f7	340	__IO uint16_t START_L; /* start register for counter L */
<>	144:ef7eb2e8f9f7	341	__IO uint16_t START_H; /* start register for counter H */
<>	144:ef7eb2e8f9f7	342	uint32_t RESERVED1[10]; /* 0x03C reserved */
<>	144:ef7eb2e8f9f7	343	union {
<>	144:ef7eb2e8f9f7	344	__IO uint32_t COUNT_U; /* counter register */
<>	144:ef7eb2e8f9f7	345	struct {
<>	144:ef7eb2e8f9f7	346	__IO uint16_t COUNT_L; /* counter register for counter L */
<>	144:ef7eb2e8f9f7	347	__IO uint16_t COUNT_H; /* counter register for counter H */
<>	144:ef7eb2e8f9f7	348	};
<>	144:ef7eb2e8f9f7	349
<>	144:ef7eb2e8f9f7	350	};
<>	144:ef7eb2e8f9f7	351
<>	144:ef7eb2e8f9f7	352	__IO uint16_t STATE_L; /* state register for counter L */
<>	144:ef7eb2e8f9f7	353	__IO uint16_t STATE_H; /* state register for counter H */
<>	144:ef7eb2e8f9f7	354	__I uint32_t INPUT; /* input register */
<>	144:ef7eb2e8f9f7	355	__IO uint16_t REGMODE_L; /* match - capture registers mode register L */
<>	144:ef7eb2e8f9f7	356	__IO uint16_t REGMODE_H; /* match - capture registers mode register H */
<>	144:ef7eb2e8f9f7	357	__IO uint32_t OUTPUT; /* output register */
<>	144:ef7eb2e8f9f7	358	__IO uint32_t OUTPUTDIRCTRL; /* output counter direction Control Register */
<>	144:ef7eb2e8f9f7	359	__IO uint32_t RES; /* conflict resolution register */
<>	144:ef7eb2e8f9f7	360	__IO uint32_t DMA0REQUEST; /* DMA0 Request Register */
<>	144:ef7eb2e8f9f7	361	__IO uint32_t DMA1REQUEST; /* DMA1 Request Register */
<>	144:ef7eb2e8f9f7	362	uint32_t RESERVED2[35];
<>	144:ef7eb2e8f9f7	363	__IO uint32_t EVEN; /* event enable register */
<>	144:ef7eb2e8f9f7	364	__IO uint32_t EVFLAG; /* event flag register */
<>	144:ef7eb2e8f9f7	365	__IO uint32_t CONEN; /* conflict enable register */
<>	144:ef7eb2e8f9f7	366	__IO uint32_t CONFLAG; /* conflict flag register */
<>	144:ef7eb2e8f9f7	367	union {
<>	144:ef7eb2e8f9f7	368	__IO union { /* ... Match / Capture value */
<>	144:ef7eb2e8f9f7	369	uint32_t U; /* SCTMATCH[i].U Unified 32-bit register */
<>	144:ef7eb2e8f9f7	370	struct {
<>	144:ef7eb2e8f9f7	371	uint16_t L; /* SCTMATCH[i].L Access to L value */
<>	144:ef7eb2e8f9f7	372	uint16_t H; /* SCTMATCH[i].H Access to H value */
<>	144:ef7eb2e8f9f7	373	};
<>	144:ef7eb2e8f9f7	374
<>	144:ef7eb2e8f9f7	375	} MATCH[CONFIG_SCT_nRG];
<>	144:ef7eb2e8f9f7	376
<>	144:ef7eb2e8f9f7	377	__I union {
<>	144:ef7eb2e8f9f7	378	uint32_t U; /* SCTCAP[i].U Unified 32-bit register */
<>	144:ef7eb2e8f9f7	379	struct {
<>	144:ef7eb2e8f9f7	380	uint16_t L; /* SCTCAP[i].L Access to L value */
<>	144:ef7eb2e8f9f7	381	uint16_t H; /* SCTCAP[i].H Access to H value */
<>	144:ef7eb2e8f9f7	382	};
<>	144:ef7eb2e8f9f7	383
<>	144:ef7eb2e8f9f7	384	} CAP[CONFIG_SCT_nRG];
<>	144:ef7eb2e8f9f7	385
<>	144:ef7eb2e8f9f7	386	};
<>	144:ef7eb2e8f9f7	387
<>	144:ef7eb2e8f9f7	388	uint32_t RESERVED3[32 - CONFIG_SCT_nRG]; /* ...-0x17C reserved */
<>	144:ef7eb2e8f9f7	389	union {
<>	144:ef7eb2e8f9f7	390	__IO uint16_t MATCH_L[CONFIG_SCT_nRG]; /* 0x180-... Match Value L counter */
<>	144:ef7eb2e8f9f7	391	__I uint16_t CAP_L[CONFIG_SCT_nRG]; /* 0x180-... Capture Value L counter */
<>	144:ef7eb2e8f9f7	392	};
<>	144:ef7eb2e8f9f7	393
<>	144:ef7eb2e8f9f7	394	uint16_t RESERVED4[32 - CONFIG_SCT_nRG]; /* ...-0x1BE reserved */
<>	144:ef7eb2e8f9f7	395	union {
<>	144:ef7eb2e8f9f7	396	__IO uint16_t MATCH_H[CONFIG_SCT_nRG]; /* 0x1C0-... Match Value H counter */
<>	144:ef7eb2e8f9f7	397	__I uint16_t CAP_H[CONFIG_SCT_nRG]; /* 0x1C0-... Capture Value H counter */
<>	144:ef7eb2e8f9f7	398	};
<>	144:ef7eb2e8f9f7	399
<>	144:ef7eb2e8f9f7	400	uint16_t RESERVED5[32 - CONFIG_SCT_nRG]; /* ...-0x1FE reserved */
<>	144:ef7eb2e8f9f7	401	union {
<>	144:ef7eb2e8f9f7	402	__IO union { /* 0x200-... Match Reload / Capture Control value */
<>	144:ef7eb2e8f9f7	403	uint32_t U; /* SCTMATCHREL[i].U Unified 32-bit register */
<>	144:ef7eb2e8f9f7	404	struct {
<>	144:ef7eb2e8f9f7	405	uint16_t L; /* SCTMATCHREL[i].L Access to L value */
<>	144:ef7eb2e8f9f7	406	uint16_t H; /* SCTMATCHREL[i].H Access to H value */
<>	144:ef7eb2e8f9f7	407	};
<>	144:ef7eb2e8f9f7	408
<>	144:ef7eb2e8f9f7	409	} MATCHREL[CONFIG_SCT_nRG];
<>	144:ef7eb2e8f9f7	410
<>	144:ef7eb2e8f9f7	411	__IO union {
<>	144:ef7eb2e8f9f7	412	uint32_t U; /* SCTCAPCTRL[i].U Unified 32-bit register */
<>	144:ef7eb2e8f9f7	413	struct {
<>	144:ef7eb2e8f9f7	414	uint16_t L; /* SCTCAPCTRL[i].L Access to L value */
<>	144:ef7eb2e8f9f7	415	uint16_t H; /* SCTCAPCTRL[i].H Access to H value */
<>	144:ef7eb2e8f9f7	416	};
<>	144:ef7eb2e8f9f7	417
<>	144:ef7eb2e8f9f7	418	} CAPCTRL[CONFIG_SCT_nRG];
<>	144:ef7eb2e8f9f7	419
<>	144:ef7eb2e8f9f7	420	};
<>	144:ef7eb2e8f9f7	421
<>	144:ef7eb2e8f9f7	422	uint32_t RESERVED6[32 - CONFIG_SCT_nRG]; /* ...-0x27C reserved */
<>	144:ef7eb2e8f9f7	423	union {
<>	144:ef7eb2e8f9f7	424	__IO uint16_t MATCHREL_L[CONFIG_SCT_nRG]; /* 0x280-... Match Reload value L counter */
<>	144:ef7eb2e8f9f7	425	__IO uint16_t CAPCTRL_L[CONFIG_SCT_nRG]; /* 0x280-... Capture Control value L counter */
<>	144:ef7eb2e8f9f7	426	};
<>	144:ef7eb2e8f9f7	427
<>	144:ef7eb2e8f9f7	428	uint16_t RESERVED7[32 - CONFIG_SCT_nRG]; /* ...-0x2BE reserved */
<>	144:ef7eb2e8f9f7	429	union {
<>	144:ef7eb2e8f9f7	430	__IO uint16_t MATCHREL_H[CONFIG_SCT_nRG]; /* 0x2C0-... Match Reload value H counter */
<>	144:ef7eb2e8f9f7	431	__IO uint16_t CAPCTRL_H[CONFIG_SCT_nRG]; /* 0x2C0-... Capture Control value H counter */
<>	144:ef7eb2e8f9f7	432	};
<>	144:ef7eb2e8f9f7	433
<>	144:ef7eb2e8f9f7	434	uint16_t RESERVED8[32 - CONFIG_SCT_nRG]; /* ...-0x2FE reserved */
<>	144:ef7eb2e8f9f7	435	__IO struct { /* 0x300-0x3FC SCTEVENT[i].STATE / SCTEVENT[i].CTRL*/
<>	144:ef7eb2e8f9f7	436	uint32_t STATE; /* Event State Register */
<>	144:ef7eb2e8f9f7	437	uint32_t CTRL; /* Event Control Register */
<>	144:ef7eb2e8f9f7	438	} EVENT[CONFIG_SCT_nEV];
<>	144:ef7eb2e8f9f7	439
<>	144:ef7eb2e8f9f7	440	uint32_t RESERVED9[128 - 2 * CONFIG_SCT_nEV]; /* ...-0x4FC reserved */
<>	144:ef7eb2e8f9f7	441	__IO struct { /* 0x500-0x57C SCTOUT[i].SET / SCTOUT[i].CLR */
<>	144:ef7eb2e8f9f7	442	uint32_t SET; /* Output n Set Register */
<>	144:ef7eb2e8f9f7	443	uint32_t CLR; /* Output n Clear Register */
<>	144:ef7eb2e8f9f7	444	} OUT[CONFIG_SCT_nOU];
<>	144:ef7eb2e8f9f7	445
<>	144:ef7eb2e8f9f7	446	uint32_t RESERVED10[191 - 2 * CONFIG_SCT_nOU]; /* ...-0x7F8 reserved */
<>	144:ef7eb2e8f9f7	447	__I uint32_t MODULECONTENT; /* 0x7FC Module Content */
<>	144:ef7eb2e8f9f7	448	} LPC_SCT_T;
<>	144:ef7eb2e8f9f7	449
<>	144:ef7eb2e8f9f7	450	/* Macro defines for SCT configuration register */
<>	144:ef7eb2e8f9f7	451	#define SCT_CONFIG_16BIT_COUNTER 0x00000000 /* Operate as 2 16-bit counters */
<>	144:ef7eb2e8f9f7	452	#define SCT_CONFIG_32BIT_COUNTER 0x00000001 /* Operate as 1 32-bit counter */
<>	144:ef7eb2e8f9f7	453
<>	144:ef7eb2e8f9f7	454	#define SCT_CONFIG_CLKMODE_BUSCLK (0x0 << 1) /* Bus clock */
<>	144:ef7eb2e8f9f7	455	#define SCT_CONFIG_CLKMODE_SCTCLK (0x1 << 1) /* SCT clock */
<>	144:ef7eb2e8f9f7	456	#define SCT_CONFIG_CLKMODE_INCLK (0x2 << 1) /* Input clock selected in CLKSEL field */
<>	144:ef7eb2e8f9f7	457	#define SCT_CONFIG_CLKMODE_INEDGECLK (0x3 << 1) /* Input clock edge selected in CLKSEL field */
<>	144:ef7eb2e8f9f7	458
<>	144:ef7eb2e8f9f7	459	#define SCT_CONFIG_NORELOADL_U (0x1 << 7) /* Operate as 1 32-bit counter */
<>	144:ef7eb2e8f9f7	460	#define SCT_CONFIG_NORELOADH (0x1 << 8) /* Operate as 1 32-bit counter */
<>	144:ef7eb2e8f9f7	461
<>	144:ef7eb2e8f9f7	462	/* Macro defines for SCT control register */
<>	144:ef7eb2e8f9f7	463	#define COUNTUP_TO_LIMIT_THEN_CLEAR_TO_ZERO 0 /* Direction for low or unified counter */
<>	144:ef7eb2e8f9f7	464	#define COUNTUP_TO LIMIT_THEN_COUNTDOWN_TO_ZERO 1
<>	144:ef7eb2e8f9f7	465
<>	144:ef7eb2e8f9f7	466	#define SCT_CTRL_STOP_L (1 << 1) /* Stop low counter */
<>	144:ef7eb2e8f9f7	467	#define SCT_CTRL_HALT_L (1 << 2) /* Halt low counter */
<>	144:ef7eb2e8f9f7	468	#define SCT_CTRL_CLRCTR_L (1 << 3) /* Clear low or unified counter */
<>	144:ef7eb2e8f9f7	469	#define SCT_CTRL_BIDIR_L(x) (((x) & 0x01) << 4) /* Bidirectional bit */
<>	144:ef7eb2e8f9f7	470	#define SCT_CTRL_PRE_L(x) (((x) & 0xFF) << 5) /* Prescale clock for low or unified counter */
<>	144:ef7eb2e8f9f7	471
<>	144:ef7eb2e8f9f7	472	#define COUNTUP_TO_LIMIT_THEN_CLEAR_TO_ZERO 0 /* Direction for high counter */
<>	144:ef7eb2e8f9f7	473	#define COUNTUP_TO LIMIT_THEN_COUNTDOWN_TO_ZERO 1
<>	144:ef7eb2e8f9f7	474	#define SCT_CTRL_STOP_H (1 << 17) /* Stop high counter */
<>	144:ef7eb2e8f9f7	475	#define SCT_CTRL_HALT_H (1 << 18) /* Halt high counter */
<>	144:ef7eb2e8f9f7	476	#define SCT_CTRL_CLRCTR_H (1 << 19) /* Clear high counter */
<>	144:ef7eb2e8f9f7	477	#define SCT_CTRL_BIDIR_H(x) (((x) & 0x01) << 20)
<>	144:ef7eb2e8f9f7	478	#define SCT_CTRL_PRE_H(x) (((x) & 0xFF) << 21) /* Prescale clock for high counter */
<>	144:ef7eb2e8f9f7	479
<>	144:ef7eb2e8f9f7	480	/* Macro defines for SCT Conflict resolution register */
<>	144:ef7eb2e8f9f7	481	#define SCT_RES_NOCHANGE (0)
<>	144:ef7eb2e8f9f7	482	#define SCT_RES_SET_OUTPUT (1)
<>	144:ef7eb2e8f9f7	483	#define SCT_RES_CLEAR_OUTPUT (2)
<>	144:ef7eb2e8f9f7	484	#define SCT_RES_TOGGLE_OUTPUT (3)
<>	144:ef7eb2e8f9f7	485
<>	144:ef7eb2e8f9f7	486	/* ---------------------------------------------------------------------------
<>	144:ef7eb2e8f9f7	487	* GPDMA Channel register block structure
<>	144:ef7eb2e8f9f7	488	*/
<>	144:ef7eb2e8f9f7	489	#define LPC_GPDMA_BASE 0x40002000
<>	144:ef7eb2e8f9f7	490
<>	144:ef7eb2e8f9f7	491	typedef struct {
<>	144:ef7eb2e8f9f7	492	__IO uint32_t SRCADDR; /* DMA Channel Source Address Register */
<>	144:ef7eb2e8f9f7	493	__IO uint32_t DESTADDR; /* DMA Channel Destination Address Register */
<>	144:ef7eb2e8f9f7	494	__IO uint32_t LLI; /* DMA Channel Linked List Item Register */
<>	144:ef7eb2e8f9f7	495	__IO uint32_t CONTROL; /* DMA Channel Control Register */
<>	144:ef7eb2e8f9f7	496	__IO uint32_t CONFIG; /* DMA Channel Configuration Register */
<>	144:ef7eb2e8f9f7	497	__I uint32_t RESERVED1[3];
<>	144:ef7eb2e8f9f7	498	} LPC_GPDMA_CH_T;
<>	144:ef7eb2e8f9f7	499
<>	144:ef7eb2e8f9f7	500	#define GPDMA_CHANNELS 8
<>	144:ef7eb2e8f9f7	501
<>	144:ef7eb2e8f9f7	502	/* ---------------------------------------------------------------------------
<>	144:ef7eb2e8f9f7	503	* GPDMA register block
<>	144:ef7eb2e8f9f7	504	*/
<>	144:ef7eb2e8f9f7	505	typedef struct { /* GPDMA Structure */
<>	144:ef7eb2e8f9f7	506	__I uint32_t INTSTAT; /* DMA Interrupt Status Register */
<>	144:ef7eb2e8f9f7	507	__I uint32_t INTTCSTAT; /* DMA Interrupt Terminal Count Request Status Register */
<>	144:ef7eb2e8f9f7	508	__O uint32_t INTTCCLEAR; /* DMA Interrupt Terminal Count Request Clear Register */
<>	144:ef7eb2e8f9f7	509	__I uint32_t INTERRSTAT; /* DMA Interrupt Error Status Register */
<>	144:ef7eb2e8f9f7	510	__O uint32_t INTERRCLR; /* DMA Interrupt Error Clear Register */
<>	144:ef7eb2e8f9f7	511	__I uint32_t RAWINTTCSTAT; /* DMA Raw Interrupt Terminal Count Status Register */
<>	144:ef7eb2e8f9f7	512	__I uint32_t RAWINTERRSTAT; /* DMA Raw Error Interrupt Status Register */
<>	144:ef7eb2e8f9f7	513	__I uint32_t ENBLDCHNS; /* DMA Enabled Channel Register */
<>	144:ef7eb2e8f9f7	514	__IO uint32_t SOFTBREQ; /* DMA Software Burst Request Register */
<>	144:ef7eb2e8f9f7	515	__IO uint32_t SOFTSREQ; /* DMA Software Single Request Register */
<>	144:ef7eb2e8f9f7	516	__IO uint32_t SOFTLBREQ; /* DMA Software Last Burst Request Register */
<>	144:ef7eb2e8f9f7	517	__IO uint32_t SOFTLSREQ; /* DMA Software Last Single Request Register */
<>	144:ef7eb2e8f9f7	518	__IO uint32_t CONFIG; /* DMA Configuration Register */
<>	144:ef7eb2e8f9f7	519	__IO uint32_t SYNC; /* DMA Synchronization Register */
<>	144:ef7eb2e8f9f7	520	__I uint32_t RESERVED0[50];
<>	144:ef7eb2e8f9f7	521	LPC_GPDMA_CH_T CH[GPDMA_CHANNELS];
<>	144:ef7eb2e8f9f7	522	} LPC_GPDMA_T;
<>	144:ef7eb2e8f9f7	523
<>	144:ef7eb2e8f9f7	524	/* ---------------------------------------------------------------------------
<>	144:ef7eb2e8f9f7	525	* SPIFI register block structure
<>	144:ef7eb2e8f9f7	526	*/
<>	144:ef7eb2e8f9f7	527	#define LPC_SPIFI_BASE 0x40003000
<>	144:ef7eb2e8f9f7	528
<>	144:ef7eb2e8f9f7	529	typedef struct { /* SPIFI Structure */
<>	144:ef7eb2e8f9f7	530	__IO uint32_t CTRL; /* Control register */
<>	144:ef7eb2e8f9f7	531	__IO uint32_t CMD; /* Command register */
<>	144:ef7eb2e8f9f7	532	__IO uint32_t ADDR; /* Address register */
<>	144:ef7eb2e8f9f7	533	__IO uint32_t IDATA; /* Intermediate data register */
<>	144:ef7eb2e8f9f7	534	__IO uint32_t CLIMIT; /* Cache limit register */
<>	144:ef7eb2e8f9f7	535	union {
<>	144:ef7eb2e8f9f7	536	__IO uint32_t DATA;
<>	144:ef7eb2e8f9f7	537	__IO uint16_t DATA_HWORD;
<>	144:ef7eb2e8f9f7	538	__IO uint8_t DATA_BYTE;
<>	144:ef7eb2e8f9f7	539	}; /* Data register */
<>	144:ef7eb2e8f9f7	540	__IO uint32_t MCMD; /* Memory command register */
<>	144:ef7eb2e8f9f7	541	__IO uint32_t STAT; /* Status register */
<>	144:ef7eb2e8f9f7	542	} LPC_SPIFI_T;
<>	144:ef7eb2e8f9f7	543
<>	144:ef7eb2e8f9f7	544	/* ---------------------------------------------------------------------------
<>	144:ef7eb2e8f9f7	545	* SD/MMC & SDIO register block structure
<>	144:ef7eb2e8f9f7	546	*/
<>	144:ef7eb2e8f9f7	547	#define LPC_SDMMC_BASE 0x40004000
<>	144:ef7eb2e8f9f7	548
<>	144:ef7eb2e8f9f7	549	typedef struct { /* SDMMC Structure */
<>	144:ef7eb2e8f9f7	550	__IO uint32_t CTRL; /* Control Register */
<>	144:ef7eb2e8f9f7	551	__IO uint32_t PWREN; /* Power Enable Register */
<>	144:ef7eb2e8f9f7	552	__IO uint32_t CLKDIV; /* Clock Divider Register */
<>	144:ef7eb2e8f9f7	553	__IO uint32_t CLKSRC; /* SD Clock Source Register */
<>	144:ef7eb2e8f9f7	554	__IO uint32_t CLKENA; /* Clock Enable Register */
<>	144:ef7eb2e8f9f7	555	__IO uint32_t TMOUT; /* Timeout Register */
<>	144:ef7eb2e8f9f7	556	__IO uint32_t CTYPE; /* Card Type Register */
<>	144:ef7eb2e8f9f7	557	__IO uint32_t BLKSIZ; /* Block Size Register */
<>	144:ef7eb2e8f9f7	558	__IO uint32_t BYTCNT; /* Byte Count Register */
<>	144:ef7eb2e8f9f7	559	__IO uint32_t INTMASK; /* Interrupt Mask Register */
<>	144:ef7eb2e8f9f7	560	__IO uint32_t CMDARG; /* Command Argument Register */
<>	144:ef7eb2e8f9f7	561	__IO uint32_t CMD; /* Command Register */
<>	144:ef7eb2e8f9f7	562	__I uint32_t RESP0; /* Response Register 0 */
<>	144:ef7eb2e8f9f7	563	__I uint32_t RESP1; /* Response Register 1 */
<>	144:ef7eb2e8f9f7	564	__I uint32_t RESP2; /* Response Register 2 */
<>	144:ef7eb2e8f9f7	565	__I uint32_t RESP3; /* Response Register 3 */
<>	144:ef7eb2e8f9f7	566	__I uint32_t MINTSTS; /* Masked Interrupt Status Register */
<>	144:ef7eb2e8f9f7	567	__IO uint32_t RINTSTS; /* Raw Interrupt Status Register */
<>	144:ef7eb2e8f9f7	568	__I uint32_t STATUS; /* Status Register */
<>	144:ef7eb2e8f9f7	569	__IO uint32_t FIFOTH; /* FIFO Threshold Watermark Register */
<>	144:ef7eb2e8f9f7	570	__I uint32_t CDETECT; /* Card Detect Register */
<>	144:ef7eb2e8f9f7	571	__I uint32_t WRTPRT; /* Write Protect Register */
<>	144:ef7eb2e8f9f7	572	__IO uint32_t GPIO; /* General Purpose Input/Output Register */
<>	144:ef7eb2e8f9f7	573	__I uint32_t TCBCNT; /* Transferred CIU Card Byte Count Register */
<>	144:ef7eb2e8f9f7	574	__I uint32_t TBBCNT; /* Transferred Host to BIU-FIFO Byte Count Register */
<>	144:ef7eb2e8f9f7	575	__IO uint32_t DEBNCE; /* Debounce Count Register */
<>	144:ef7eb2e8f9f7	576	__IO uint32_t USRID; /* User ID Register */
<>	144:ef7eb2e8f9f7	577	__I uint32_t VERID; /* Version ID Register */
<>	144:ef7eb2e8f9f7	578	__I uint32_t RESERVED0;
<>	144:ef7eb2e8f9f7	579	__IO uint32_t UHS_REG; /* UHS-1 Register */
<>	144:ef7eb2e8f9f7	580	__IO uint32_t RST_N; /* Hardware Reset */
<>	144:ef7eb2e8f9f7	581	__I uint32_t RESERVED1;
<>	144:ef7eb2e8f9f7	582	__IO uint32_t BMOD; /* Bus Mode Register */
<>	144:ef7eb2e8f9f7	583	__O uint32_t PLDMND; /* Poll Demand Register */
<>	144:ef7eb2e8f9f7	584	__IO uint32_t DBADDR; /* Descriptor List Base Address Register */
<>	144:ef7eb2e8f9f7	585	__IO uint32_t IDSTS; /* Internal DMAC Status Register */
<>	144:ef7eb2e8f9f7	586	__IO uint32_t IDINTEN; /* Internal DMAC Interrupt Enable Register */
<>	144:ef7eb2e8f9f7	587	__I uint32_t DSCADDR; /* Current Host Descriptor Address Register */
<>	144:ef7eb2e8f9f7	588	__I uint32_t BUFADDR; /* Current Buffer Descriptor Address Register */
<>	144:ef7eb2e8f9f7	589	} LPC_SDMMC_T;
<>	144:ef7eb2e8f9f7	590
<>	144:ef7eb2e8f9f7	591	/* ---------------------------------------------------------------------------
<>	144:ef7eb2e8f9f7	592	* External Memory Controller (EMC) register block structure
<>	144:ef7eb2e8f9f7	593	*/
<>	144:ef7eb2e8f9f7	594	#define LPC_EMC_BASE 0x40005000
<>	144:ef7eb2e8f9f7	595
<>	144:ef7eb2e8f9f7	596	typedef struct { /* EMC Structure */
<>	144:ef7eb2e8f9f7	597	__IO uint32_t CONTROL; /* Controls operation of the memory controller. */
<>	144:ef7eb2e8f9f7	598	__I uint32_t STATUS; /* Provides EMC status information. */
<>	144:ef7eb2e8f9f7	599	__IO uint32_t CONFIG; /* Configures operation of the memory controller. */
<>	144:ef7eb2e8f9f7	600	__I uint32_t RESERVED0[5];
<>	144:ef7eb2e8f9f7	601	__IO uint32_t DYNAMICCONTROL; /* Controls dynamic memory operation. */
<>	144:ef7eb2e8f9f7	602	__IO uint32_t DYNAMICREFRESH; /* Configures dynamic memory refresh operation. */
<>	144:ef7eb2e8f9f7	603	__IO uint32_t DYNAMICREADCONFIG; /* Configures the dynamic memory read strategy. */
<>	144:ef7eb2e8f9f7	604	__I uint32_t RESERVED1;
<>	144:ef7eb2e8f9f7	605	__IO uint32_t DYNAMICRP; /* Selects the precharge command period. */
<>	144:ef7eb2e8f9f7	606	__IO uint32_t DYNAMICRAS; /* Selects the active to precharge command period. */
<>	144:ef7eb2e8f9f7	607	__IO uint32_t DYNAMICSREX; /* Selects the self-refresh exit time. */
<>	144:ef7eb2e8f9f7	608	__IO uint32_t DYNAMICAPR; /* Selects the last-data-out to active command time. */
<>	144:ef7eb2e8f9f7	609	__IO uint32_t DYNAMICDAL; /* Selects the data-in to active command time. */
<>	144:ef7eb2e8f9f7	610	__IO uint32_t DYNAMICWR; /* Selects the write recovery time. */
<>	144:ef7eb2e8f9f7	611	__IO uint32_t DYNAMICRC; /* Selects the active to active command period. */
<>	144:ef7eb2e8f9f7	612	__IO uint32_t DYNAMICRFC; /* Selects the auto-refresh period. */
<>	144:ef7eb2e8f9f7	613	__IO uint32_t DYNAMICXSR; /* Selects the exit self-refresh to active command time. */
<>	144:ef7eb2e8f9f7	614	__IO uint32_t DYNAMICRRD; /* Selects the active bank A to active bank B latency. */
<>	144:ef7eb2e8f9f7	615	__IO uint32_t DYNAMICMRD; /* Selects the load mode register to active command time. */
<>	144:ef7eb2e8f9f7	616	__I uint32_t RESERVED2[9];
<>	144:ef7eb2e8f9f7	617	__IO uint32_t STATICEXTENDEDWAIT; /* Selects time for long static memory read and write transfers. */
<>	144:ef7eb2e8f9f7	618	__I uint32_t RESERVED3[31];
<>	144:ef7eb2e8f9f7	619	__IO uint32_t DYNAMICCONFIG0; /* Selects the configuration information for dynamic memory chip select n. */
<>	144:ef7eb2e8f9f7	620	__IO uint32_t DYNAMICRASCAS0; /* Selects the RAS and CAS latencies for dynamic memory chip select n. */
<>	144:ef7eb2e8f9f7	621	__I uint32_t RESERVED4[6];
<>	144:ef7eb2e8f9f7	622	__IO uint32_t DYNAMICCONFIG1; /* Selects the configuration information for dynamic memory chip select n. */
<>	144:ef7eb2e8f9f7	623	__IO uint32_t DYNAMICRASCAS1; /* Selects the RAS and CAS latencies for dynamic memory chip select n. */
<>	144:ef7eb2e8f9f7	624	__I uint32_t RESERVED5[6];
<>	144:ef7eb2e8f9f7	625	__IO uint32_t DYNAMICCONFIG2; /* Selects the configuration information for dynamic memory chip select n. */
<>	144:ef7eb2e8f9f7	626	__IO uint32_t DYNAMICRASCAS2; /* Selects the RAS and CAS latencies for dynamic memory chip select n. */
<>	144:ef7eb2e8f9f7	627	__I uint32_t RESERVED6[6];
<>	144:ef7eb2e8f9f7	628	__IO uint32_t DYNAMICCONFIG3; /* Selects the configuration information for dynamic memory chip select n. */
<>	144:ef7eb2e8f9f7	629	__IO uint32_t DYNAMICRASCAS3; /* Selects the RAS and CAS latencies for dynamic memory chip select n. */
<>	144:ef7eb2e8f9f7	630	__I uint32_t RESERVED7[38];
<>	144:ef7eb2e8f9f7	631	__IO uint32_t STATICCONFIG0; /* Selects the memory configuration for static chip select n. */
<>	144:ef7eb2e8f9f7	632	__IO uint32_t STATICWAITWEN0; /* Selects the delay from chip select n to write enable. */
<>	144:ef7eb2e8f9f7	633	__IO uint32_t STATICWAITOEN0; /* Selects the delay from chip select n or address change, whichever is later, to output enable. */
<>	144:ef7eb2e8f9f7	634	__IO uint32_t STATICWAITRD0; /* Selects the delay from chip select n to a read access. */
<>	144:ef7eb2e8f9f7	635	__IO uint32_t STATICWAITPAG0; /* Selects the delay for asynchronous page mode sequential accesses for chip select n. */
<>	144:ef7eb2e8f9f7	636	__IO uint32_t STATICWAITWR0; /* Selects the delay from chip select n to a write access. */
<>	144:ef7eb2e8f9f7	637	__IO uint32_t STATICWAITTURN0; /* Selects bus turnaround cycles */
<>	144:ef7eb2e8f9f7	638	__I uint32_t RESERVED8;
<>	144:ef7eb2e8f9f7	639	__IO uint32_t STATICCONFIG1; /* Selects the memory configuration for static chip select n. */
<>	144:ef7eb2e8f9f7	640	__IO uint32_t STATICWAITWEN1; /* Selects the delay from chip select n to write enable. */
<>	144:ef7eb2e8f9f7	641	__IO uint32_t STATICWAITOEN1; /* Selects the delay from chip select n or address change, whichever is later, to output enable. */
<>	144:ef7eb2e8f9f7	642	__IO uint32_t STATICWAITRD1; /* Selects the delay from chip select n to a read access. */
<>	144:ef7eb2e8f9f7	643	__IO uint32_t STATICWAITPAG1; /* Selects the delay for asynchronous page mode sequential accesses for chip select n. */
<>	144:ef7eb2e8f9f7	644	__IO uint32_t STATICWAITWR1; /* Selects the delay from chip select n to a write access. */
<>	144:ef7eb2e8f9f7	645	__IO uint32_t STATICWAITTURN1; /* Selects bus turnaround cycles */
<>	144:ef7eb2e8f9f7	646	__I uint32_t RESERVED9;
<>	144:ef7eb2e8f9f7	647	__IO uint32_t STATICCONFIG2; /* Selects the memory configuration for static chip select n. */
<>	144:ef7eb2e8f9f7	648	__IO uint32_t STATICWAITWEN2; /* Selects the delay from chip select n to write enable. */
<>	144:ef7eb2e8f9f7	649	__IO uint32_t STATICWAITOEN2; /* Selects the delay from chip select n or address change, whichever is later, to output enable. */
<>	144:ef7eb2e8f9f7	650	__IO uint32_t STATICWAITRD2; /* Selects the delay from chip select n to a read access. */
<>	144:ef7eb2e8f9f7	651	__IO uint32_t STATICWAITPAG2; /* Selects the delay for asynchronous page mode sequential accesses for chip select n. */
<>	144:ef7eb2e8f9f7	652	__IO uint32_t STATICWAITWR2; /* Selects the delay from chip select n to a write access. */
<>	144:ef7eb2e8f9f7	653	__IO uint32_t STATICWAITTURN2; /* Selects bus turnaround cycles */
<>	144:ef7eb2e8f9f7	654	__I uint32_t RESERVED10;
<>	144:ef7eb2e8f9f7	655	__IO uint32_t STATICCONFIG3; /* Selects the memory configuration for static chip select n. */
<>	144:ef7eb2e8f9f7	656	__IO uint32_t STATICWAITWEN3; /* Selects the delay from chip select n to write enable. */
<>	144:ef7eb2e8f9f7	657	__IO uint32_t STATICWAITOEN3; /* Selects the delay from chip select n or address change, whichever is later, to output enable. */
<>	144:ef7eb2e8f9f7	658	__IO uint32_t STATICWAITRD3; /* Selects the delay from chip select n to a read access. */
<>	144:ef7eb2e8f9f7	659	__IO uint32_t STATICWAITPAG3; /* Selects the delay for asynchronous page mode sequential accesses for chip select n. */
<>	144:ef7eb2e8f9f7	660	__IO uint32_t STATICWAITWR3; /* Selects the delay from chip select n to a write access. */
<>	144:ef7eb2e8f9f7	661	__IO uint32_t STATICWAITTURN3; /* Selects bus turnaround cycles */
<>	144:ef7eb2e8f9f7	662	} LPC_EMC_T;
<>	144:ef7eb2e8f9f7	663
<>	144:ef7eb2e8f9f7	664	/* ---------------------------------------------------------------------------
<>	144:ef7eb2e8f9f7	665	* USB High-Speed register block structure
<>	144:ef7eb2e8f9f7	666	*/
<>	144:ef7eb2e8f9f7	667	#define LPC_USB0_BASE 0x40006000
<>	144:ef7eb2e8f9f7	668	#define LPC_USB1_BASE 0x40007000
<>	144:ef7eb2e8f9f7	669
<>	144:ef7eb2e8f9f7	670	typedef struct { /* USB Structure */
<>	144:ef7eb2e8f9f7	671	__I uint32_t RESERVED0[64];
<>	144:ef7eb2e8f9f7	672	__I uint32_t CAPLENGTH; /* Capability register length */
<>	144:ef7eb2e8f9f7	673	__I uint32_t HCSPARAMS; /* Host controller structural parameters */
<>	144:ef7eb2e8f9f7	674	__I uint32_t HCCPARAMS; /* Host controller capability parameters */
<>	144:ef7eb2e8f9f7	675	__I uint32_t RESERVED1[5];
<>	144:ef7eb2e8f9f7	676	__I uint32_t DCIVERSION; /* Device interface version number */
<>	144:ef7eb2e8f9f7	677	__I uint32_t RESERVED2[7];
<>	144:ef7eb2e8f9f7	678	union {
<>	144:ef7eb2e8f9f7	679	__IO uint32_t USBCMD_H; /* USB command (host mode) */
<>	144:ef7eb2e8f9f7	680	__IO uint32_t USBCMD_D; /* USB command (device mode) */
<>	144:ef7eb2e8f9f7	681	};
<>	144:ef7eb2e8f9f7	682
<>	144:ef7eb2e8f9f7	683	union {
<>	144:ef7eb2e8f9f7	684	__IO uint32_t USBSTS_H; /* USB status (host mode) */
<>	144:ef7eb2e8f9f7	685	__IO uint32_t USBSTS_D; /* USB status (device mode) */
<>	144:ef7eb2e8f9f7	686	};
<>	144:ef7eb2e8f9f7	687
<>	144:ef7eb2e8f9f7	688	union {
<>	144:ef7eb2e8f9f7	689	__IO uint32_t USBINTR_H; /* USB interrupt enable (host mode) */
<>	144:ef7eb2e8f9f7	690	__IO uint32_t USBINTR_D; /* USB interrupt enable (device mode) */
<>	144:ef7eb2e8f9f7	691	};
<>	144:ef7eb2e8f9f7	692
<>	144:ef7eb2e8f9f7	693	union {
<>	144:ef7eb2e8f9f7	694	__IO uint32_t FRINDEX_H; /* USB frame index (host mode) */
<>	144:ef7eb2e8f9f7	695	__I uint32_t FRINDEX_D; /* USB frame index (device mode) */
<>	144:ef7eb2e8f9f7	696	};
<>	144:ef7eb2e8f9f7	697
<>	144:ef7eb2e8f9f7	698	__I uint32_t RESERVED3;
<>	144:ef7eb2e8f9f7	699	union {
<>	144:ef7eb2e8f9f7	700	__IO uint32_t PERIODICLISTBASE; /* Frame list base address */
<>	144:ef7eb2e8f9f7	701	__IO uint32_t DEVICEADDR; /* USB device address */
<>	144:ef7eb2e8f9f7	702	};
<>	144:ef7eb2e8f9f7	703
<>	144:ef7eb2e8f9f7	704	union {
<>	144:ef7eb2e8f9f7	705	__IO uint32_t ASYNCLISTADDR; /* Address of endpoint list in memory (host mode) */
<>	144:ef7eb2e8f9f7	706	__IO uint32_t ENDPOINTLISTADDR; /* Address of endpoint list in memory (device mode) */
<>	144:ef7eb2e8f9f7	707	};
<>	144:ef7eb2e8f9f7	708
<>	144:ef7eb2e8f9f7	709	__IO uint32_t TTCTRL; /* Asynchronous buffer status for embedded TT (host mode) */
<>	144:ef7eb2e8f9f7	710	__IO uint32_t BURSTSIZE; /* Programmable burst size */
<>	144:ef7eb2e8f9f7	711	__IO uint32_t TXFILLTUNING; /* Host transmit pre-buffer packet tuning (host mode) */
<>	144:ef7eb2e8f9f7	712	__I uint32_t RESERVED4[2];
<>	144:ef7eb2e8f9f7	713	__IO uint32_t ULPIVIEWPORT; /* ULPI viewport */
<>	144:ef7eb2e8f9f7	714	__IO uint32_t BINTERVAL; /* Length of virtual frame */
<>	144:ef7eb2e8f9f7	715	__IO uint32_t ENDPTNAK; /* Endpoint NAK (device mode) */
<>	144:ef7eb2e8f9f7	716	__IO uint32_t ENDPTNAKEN; /* Endpoint NAK Enable (device mode) */
<>	144:ef7eb2e8f9f7	717	__I uint32_t RESERVED5;
<>	144:ef7eb2e8f9f7	718	union {
<>	144:ef7eb2e8f9f7	719	__IO uint32_t PORTSC1_H; /* Port 1 status/control (host mode) */
<>	144:ef7eb2e8f9f7	720	__IO uint32_t PORTSC1_D; /* Port 1 status/control (device mode) */
<>	144:ef7eb2e8f9f7	721	};
<>	144:ef7eb2e8f9f7	722
<>	144:ef7eb2e8f9f7	723	__I uint32_t RESERVED6[7];
<>	144:ef7eb2e8f9f7	724	__IO uint32_t OTGSC; /* OTG status and control */
<>	144:ef7eb2e8f9f7	725	union {
<>	144:ef7eb2e8f9f7	726	__IO uint32_t USBMODE_H; /* USB mode (host mode) */
<>	144:ef7eb2e8f9f7	727	__IO uint32_t USBMODE_D; /* USB mode (device mode) */
<>	144:ef7eb2e8f9f7	728	};
<>	144:ef7eb2e8f9f7	729
<>	144:ef7eb2e8f9f7	730	__IO uint32_t ENDPTSETUPSTAT; /* Endpoint setup status */
<>	144:ef7eb2e8f9f7	731	__IO uint32_t ENDPTPRIME; /* Endpoint initialization */
<>	144:ef7eb2e8f9f7	732	__IO uint32_t ENDPTFLUSH; /* Endpoint de-initialization */
<>	144:ef7eb2e8f9f7	733	__I uint32_t ENDPTSTAT; /* Endpoint status */
<>	144:ef7eb2e8f9f7	734	__IO uint32_t ENDPTCOMPLETE; /* Endpoint complete */
<>	144:ef7eb2e8f9f7	735	__IO uint32_t ENDPTCTRL[6]; /* Endpoint control 0 */
<>	144:ef7eb2e8f9f7	736	} LPC_USBHS_T;
<>	144:ef7eb2e8f9f7	737
<>	144:ef7eb2e8f9f7	738	/* ---------------------------------------------------------------------------
<>	144:ef7eb2e8f9f7	739	* LCD Controller register block structure
<>	144:ef7eb2e8f9f7	740	*/
<>	144:ef7eb2e8f9f7	741	#define LPC_LCD_BASE 0x40008000
<>	144:ef7eb2e8f9f7	742
<>	144:ef7eb2e8f9f7	743	typedef struct { /* LCD Structure */
<>	144:ef7eb2e8f9f7	744	__IO uint32_t TIMH; /* Horizontal Timing Control register */
<>	144:ef7eb2e8f9f7	745	__IO uint32_t TIMV; /* Vertical Timing Control register */
<>	144:ef7eb2e8f9f7	746	__IO uint32_t POL; /* Clock and Signal Polarity Control register */
<>	144:ef7eb2e8f9f7	747	__IO uint32_t LE; /* Line End Control register */
<>	144:ef7eb2e8f9f7	748	__IO uint32_t UPBASE; /* Upper Panel Frame Base Address register */
<>	144:ef7eb2e8f9f7	749	__IO uint32_t LPBASE; /* Lower Panel Frame Base Address register */
<>	144:ef7eb2e8f9f7	750	__IO uint32_t CTRL; /* LCD Control register */
<>	144:ef7eb2e8f9f7	751	__IO uint32_t INTMSK; /* Interrupt Mask register */
<>	144:ef7eb2e8f9f7	752	__I uint32_t INTRAW; /* Raw Interrupt Status register */
<>	144:ef7eb2e8f9f7	753	__I uint32_t INTSTAT; /* Masked Interrupt Status register */
<>	144:ef7eb2e8f9f7	754	__O uint32_t INTCLR; /* Interrupt Clear register */
<>	144:ef7eb2e8f9f7	755	__I uint32_t UPCURR; /* Upper Panel Current Address Value register */
<>	144:ef7eb2e8f9f7	756	__I uint32_t LPCURR; /* Lower Panel Current Address Value register */
<>	144:ef7eb2e8f9f7	757	__I uint32_t RESERVED0[115];
<>	144:ef7eb2e8f9f7	758	__IO uint16_t PAL[256]; /* 256x16-bit Color Palette registers */
<>	144:ef7eb2e8f9f7	759	__I uint32_t RESERVED1[256];
<>	144:ef7eb2e8f9f7	760	__IO uint32_t CRSR_IMG[256];/* Cursor Image registers */
<>	144:ef7eb2e8f9f7	761	__IO uint32_t CRSR_CTRL; /* Cursor Control register */
<>	144:ef7eb2e8f9f7	762	__IO uint32_t CRSR_CFG; /* Cursor Configuration register */
<>	144:ef7eb2e8f9f7	763	__IO uint32_t CRSR_PAL0; /* Cursor Palette register 0 */
<>	144:ef7eb2e8f9f7	764	__IO uint32_t CRSR_PAL1; /* Cursor Palette register 1 */
<>	144:ef7eb2e8f9f7	765	__IO uint32_t CRSR_XY; /* Cursor XY Position register */
<>	144:ef7eb2e8f9f7	766	__IO uint32_t CRSR_CLIP; /* Cursor Clip Position register */
<>	144:ef7eb2e8f9f7	767	__I uint32_t RESERVED2[2];
<>	144:ef7eb2e8f9f7	768	__IO uint32_t CRSR_INTMSK; /* Cursor Interrupt Mask register */
<>	144:ef7eb2e8f9f7	769	__O uint32_t CRSR_INTCLR; /* Cursor Interrupt Clear register */
<>	144:ef7eb2e8f9f7	770	__I uint32_t CRSR_INTRAW; /* Cursor Raw Interrupt Status register */
<>	144:ef7eb2e8f9f7	771	__I uint32_t CRSR_INTSTAT;/* Cursor Masked Interrupt Status register */
<>	144:ef7eb2e8f9f7	772	} LPC_LCD_T;
<>	144:ef7eb2e8f9f7	773
<>	144:ef7eb2e8f9f7	774	/* ---------------------------------------------------------------------------
<>	144:ef7eb2e8f9f7	775	* EEPROM register block structure
<>	144:ef7eb2e8f9f7	776	*/
<>	144:ef7eb2e8f9f7	777	#define LPC_EEPROM_BASE 0x4000E000
<>	144:ef7eb2e8f9f7	778
<>	144:ef7eb2e8f9f7	779	typedef struct { /* EEPROM Structure */
<>	144:ef7eb2e8f9f7	780	__IO uint32_t CMD; /* EEPROM command register */
<>	144:ef7eb2e8f9f7	781	uint32_t RESERVED0;
<>	144:ef7eb2e8f9f7	782	__IO uint32_t RWSTATE; /* EEPROM read wait state register */
<>	144:ef7eb2e8f9f7	783	__IO uint32_t AUTOPROG; /* EEPROM auto programming register */
<>	144:ef7eb2e8f9f7	784	__IO uint32_t WSTATE; /* EEPROM wait state register */
<>	144:ef7eb2e8f9f7	785	__IO uint32_t CLKDIV; /* EEPROM clock divider register */
<>	144:ef7eb2e8f9f7	786	__IO uint32_t PWRDWN; /* EEPROM power-down register */
<>	144:ef7eb2e8f9f7	787	uint32_t RESERVED2[1007];
<>	144:ef7eb2e8f9f7	788	__O uint32_t INTENCLR; /* EEPROM interrupt enable clear */
<>	144:ef7eb2e8f9f7	789	__O uint32_t INTENSET; /* EEPROM interrupt enable set */
<>	144:ef7eb2e8f9f7	790	__I uint32_t INTSTAT; /* EEPROM interrupt status */
<>	144:ef7eb2e8f9f7	791	__I uint32_t INTEN; /* EEPROM interrupt enable */
<>	144:ef7eb2e8f9f7	792	__O uint32_t INTSTATCLR; /* EEPROM interrupt status clear */
<>	144:ef7eb2e8f9f7	793	__O uint32_t INTSTATSET; /* EEPROM interrupt status set */
<>	144:ef7eb2e8f9f7	794	} LPC_EEPROM_T;
<>	144:ef7eb2e8f9f7	795
<>	144:ef7eb2e8f9f7	796	/* ---------------------------------------------------------------------------
<>	144:ef7eb2e8f9f7	797	* 10/100 MII & RMII Ethernet with timestamping register block structure
<>	144:ef7eb2e8f9f7	798	*/
<>	144:ef7eb2e8f9f7	799	#define LPC_ETHERNET_BASE 0x40010000
<>	144:ef7eb2e8f9f7	800
<>	144:ef7eb2e8f9f7	801	typedef struct { /* ETHERNET Structure */
<>	144:ef7eb2e8f9f7	802	__IO uint32_t MAC_CONFIG; /* MAC configuration register */
<>	144:ef7eb2e8f9f7	803	__IO uint32_t MAC_FRAME_FILTER; /* MAC frame filter */
<>	144:ef7eb2e8f9f7	804	__IO uint32_t MAC_HASHTABLE_HIGH; /* Hash table high register */
<>	144:ef7eb2e8f9f7	805	__IO uint32_t MAC_HASHTABLE_LOW; /* Hash table low register */
<>	144:ef7eb2e8f9f7	806	__IO uint32_t MAC_MII_ADDR; /* MII address register */
<>	144:ef7eb2e8f9f7	807	__IO uint32_t MAC_MII_DATA; /* MII data register */
<>	144:ef7eb2e8f9f7	808	__IO uint32_t MAC_FLOW_CTRL; /* Flow control register */
<>	144:ef7eb2e8f9f7	809	__IO uint32_t MAC_VLAN_TAG; /* VLAN tag register */
<>	144:ef7eb2e8f9f7	810	__I uint32_t RESERVED0;
<>	144:ef7eb2e8f9f7	811	__I uint32_t MAC_DEBUG; /* Debug register */
<>	144:ef7eb2e8f9f7	812	__IO uint32_t MAC_RWAKE_FRFLT; /* Remote wake-up frame filter */
<>	144:ef7eb2e8f9f7	813	__IO uint32_t MAC_PMT_CTRL_STAT; /* PMT control and status */
<>	144:ef7eb2e8f9f7	814	__I uint32_t RESERVED1[2];
<>	144:ef7eb2e8f9f7	815	__I uint32_t MAC_INTR; /* Interrupt status register */
<>	144:ef7eb2e8f9f7	816	__IO uint32_t MAC_INTR_MASK; /* Interrupt mask register */
<>	144:ef7eb2e8f9f7	817	__IO uint32_t MAC_ADDR0_HIGH; /* MAC address 0 high register */
<>	144:ef7eb2e8f9f7	818	__IO uint32_t MAC_ADDR0_LOW; /* MAC address 0 low register */
<>	144:ef7eb2e8f9f7	819	__I uint32_t RESERVED2[430];
<>	144:ef7eb2e8f9f7	820	__IO uint32_t MAC_TIMESTP_CTRL; /* Time stamp control register */
<>	144:ef7eb2e8f9f7	821	__IO uint32_t SUBSECOND_INCR; /* Sub-second increment register */
<>	144:ef7eb2e8f9f7	822	__I uint32_t SECONDS; /* System time seconds register */
<>	144:ef7eb2e8f9f7	823	__I uint32_t NANOSECONDS; /* System time nanoseconds register */
<>	144:ef7eb2e8f9f7	824	__IO uint32_t SECONDSUPDATE; /* System time seconds update register */
<>	144:ef7eb2e8f9f7	825	__IO uint32_t NANOSECONDSUPDATE; /* System time nanoseconds update register */
<>	144:ef7eb2e8f9f7	826	__IO uint32_t ADDEND; /* Time stamp addend register */
<>	144:ef7eb2e8f9f7	827	__IO uint32_t TARGETSECONDS; /* Target time seconds register */
<>	144:ef7eb2e8f9f7	828	__IO uint32_t TARGETNANOSECONDS; /* Target time nanoseconds register */
<>	144:ef7eb2e8f9f7	829	__IO uint32_t HIGHWORD; /* System time higher word seconds register */
<>	144:ef7eb2e8f9f7	830	__I uint32_t TIMESTAMPSTAT; /* Time stamp status register */
<>	144:ef7eb2e8f9f7	831	__IO uint32_t PPSCTRL; /* PPS control register */
<>	144:ef7eb2e8f9f7	832	__I uint32_t AUXNANOSECONDS; /* Auxiliary time stamp nanoseconds register */
<>	144:ef7eb2e8f9f7	833	__I uint32_t AUXSECONDS; /* Auxiliary time stamp seconds register */
<>	144:ef7eb2e8f9f7	834	__I uint32_t RESERVED3[562];
<>	144:ef7eb2e8f9f7	835	__IO uint32_t DMA_BUS_MODE; /* Bus Mode Register */
<>	144:ef7eb2e8f9f7	836	__IO uint32_t DMA_TRANS_POLL_DEMAND; /* Transmit poll demand register */
<>	144:ef7eb2e8f9f7	837	__IO uint32_t DMA_REC_POLL_DEMAND; /* Receive poll demand register */
<>	144:ef7eb2e8f9f7	838	__IO uint32_t DMA_REC_DES_ADDR; /* Receive descriptor list address register */
<>	144:ef7eb2e8f9f7	839	__IO uint32_t DMA_TRANS_DES_ADDR; /* Transmit descriptor list address register */
<>	144:ef7eb2e8f9f7	840	__IO uint32_t DMA_STAT; /* Status register */
<>	144:ef7eb2e8f9f7	841	__IO uint32_t DMA_OP_MODE; /* Operation mode register */
<>	144:ef7eb2e8f9f7	842	__IO uint32_t DMA_INT_EN; /* Interrupt enable register */
<>	144:ef7eb2e8f9f7	843	__I uint32_t DMA_MFRM_BUFOF; /* Missed frame and buffer overflow register */
<>	144:ef7eb2e8f9f7	844	__IO uint32_t DMA_REC_INT_WDT; /* Receive interrupt watchdog timer register */
<>	144:ef7eb2e8f9f7	845	__I uint32_t RESERVED4[8];
<>	144:ef7eb2e8f9f7	846	__I uint32_t DMA_CURHOST_TRANS_DES; /* Current host transmit descriptor register */
<>	144:ef7eb2e8f9f7	847	__I uint32_t DMA_CURHOST_REC_DES; /* Current host receive descriptor register */
<>	144:ef7eb2e8f9f7	848	__I uint32_t DMA_CURHOST_TRANS_BUF; /* Current host transmit buffer address register */
<>	144:ef7eb2e8f9f7	849	__I uint32_t DMA_CURHOST_REC_BUF; /* Current host receive buffer address register */
<>	144:ef7eb2e8f9f7	850	} LPC_ENET_T;
<>	144:ef7eb2e8f9f7	851
<>	144:ef7eb2e8f9f7	852	/* ---------------------------------------------------------------------------
<>	144:ef7eb2e8f9f7	853	* Alarm Timer register block structure
<>	144:ef7eb2e8f9f7	854	*/
<>	144:ef7eb2e8f9f7	855	#define LPC_ATIMER_BASE 0x40040000
<>	144:ef7eb2e8f9f7	856
<>	144:ef7eb2e8f9f7	857	typedef struct { /* ATIMER Structure */
<>	144:ef7eb2e8f9f7	858	__IO uint32_t DOWNCOUNTER; /* Downcounter register */
<>	144:ef7eb2e8f9f7	859	__IO uint32_t PRESET; /* Preset value register */
<>	144:ef7eb2e8f9f7	860	__I uint32_t RESERVED0[1012];
<>	144:ef7eb2e8f9f7	861	__O uint32_t CLR_EN; /* Interrupt clear enable register */
<>	144:ef7eb2e8f9f7	862	__O uint32_t SET_EN; /* Interrupt set enable register */
<>	144:ef7eb2e8f9f7	863	__I uint32_t STATUS; /* Status register */
<>	144:ef7eb2e8f9f7	864	__I uint32_t ENABLE; /* Enable register */
<>	144:ef7eb2e8f9f7	865	__O uint32_t CLR_STAT; /* Clear register */
<>	144:ef7eb2e8f9f7	866	__O uint32_t SET_STAT; /* Set register */
<>	144:ef7eb2e8f9f7	867	} LPC_ATIMER_T;
<>	144:ef7eb2e8f9f7	868
<>	144:ef7eb2e8f9f7	869	/* ---------------------------------------------------------------------------
<>	144:ef7eb2e8f9f7	870	* Register File register block structure
<>	144:ef7eb2e8f9f7	871	*/
<>	144:ef7eb2e8f9f7	872	#define LPC_REGFILE_BASE 0x40041000
<>	144:ef7eb2e8f9f7	873
<>	144:ef7eb2e8f9f7	874	typedef struct {
<>	144:ef7eb2e8f9f7	875	__IO uint32_t REGFILE[64]; /* General purpose storage register */
<>	144:ef7eb2e8f9f7	876	} LPC_REGFILE_T;
<>	144:ef7eb2e8f9f7	877
<>	144:ef7eb2e8f9f7	878	/* ---------------------------------------------------------------------------
<>	144:ef7eb2e8f9f7	879	* Power Management Controller register block structure
<>	144:ef7eb2e8f9f7	880	*/
<>	144:ef7eb2e8f9f7	881	#define LPC_PMC_BASE 0x40042000
<>	144:ef7eb2e8f9f7	882
<>	144:ef7eb2e8f9f7	883	typedef struct { /* PMC Structure */
<>	144:ef7eb2e8f9f7	884	__IO uint32_t PD0_SLEEP0_HW_ENA; /* Hardware sleep event enable register */
<>	144:ef7eb2e8f9f7	885	__I uint32_t RESERVED0[6];
<>	144:ef7eb2e8f9f7	886	__IO uint32_t PD0_SLEEP0_MODE; /* Sleep power mode register */
<>	144:ef7eb2e8f9f7	887	} LPC_PMC_T;
<>	144:ef7eb2e8f9f7	888
<>	144:ef7eb2e8f9f7	889	/* ---------------------------------------------------------------------------
<>	144:ef7eb2e8f9f7	890	* CREG Register Block
<>	144:ef7eb2e8f9f7	891	*/
<>	144:ef7eb2e8f9f7	892	#define LPC_CREG_BASE 0x40043000
<>	144:ef7eb2e8f9f7	893
<>	144:ef7eb2e8f9f7	894	typedef struct { /* CREG Structure */
<>	144:ef7eb2e8f9f7	895	__I uint32_t RESERVED0;
<>	144:ef7eb2e8f9f7	896	__IO uint32_t CREG0; /* Chip configuration register 32 kHz oscillator output and BOD control register. */
<>	144:ef7eb2e8f9f7	897	__I uint32_t RESERVED1[62];
<>	144:ef7eb2e8f9f7	898	__IO uint32_t MXMEMMAP; /* ARM Cortex-M3/M4 memory mapping */
<>	144:ef7eb2e8f9f7	899	#if defined(CHIP_LPC18XX)
<>	144:ef7eb2e8f9f7	900	__I uint32_t RESERVED2[5];
<>	144:ef7eb2e8f9f7	901	#else
<>	144:ef7eb2e8f9f7	902	__I uint32_t RESERVED2;
<>	144:ef7eb2e8f9f7	903	__I uint32_t CREG1; /* Configuration Register 1 */
<>	144:ef7eb2e8f9f7	904	__I uint32_t CREG2; /* Configuration Register 2 */
<>	144:ef7eb2e8f9f7	905	__I uint32_t CREG3; /* Configuration Register 3 */
<>	144:ef7eb2e8f9f7	906	__I uint32_t CREG4; /* Configuration Register 4 */
<>	144:ef7eb2e8f9f7	907	#endif
<>	144:ef7eb2e8f9f7	908	__IO uint32_t CREG5; /* Chip configuration register 5. Controls JTAG access. */
<>	144:ef7eb2e8f9f7	909	__IO uint32_t DMAMUX; /* DMA muxing control */
<>	144:ef7eb2e8f9f7	910	__IO uint32_t FLASHCFGA; /* Flash accelerator configuration register for flash bank A */
<>	144:ef7eb2e8f9f7	911	__IO uint32_t FLASHCFGB; /* Flash accelerator configuration register for flash bank B */
<>	144:ef7eb2e8f9f7	912	__IO uint32_t ETBCFG; /* ETB RAM configuration */
<>	144:ef7eb2e8f9f7	913	__IO uint32_t CREG6; /* Chip configuration register 6. */
<>	144:ef7eb2e8f9f7	914	#if defined(CHIP_LPC18XX)
<>	144:ef7eb2e8f9f7	915	__I uint32_t RESERVED4[52];
<>	144:ef7eb2e8f9f7	916	#else
<>	144:ef7eb2e8f9f7	917	__IO uint32_t M4TXEVENT; /* M4 IPC event register */
<>	144:ef7eb2e8f9f7	918	__I uint32_t RESERVED4[51];
<>	144:ef7eb2e8f9f7	919	#endif
<>	144:ef7eb2e8f9f7	920	__I uint32_t CHIPID; /* Part ID */
<>	144:ef7eb2e8f9f7	921	#if defined(CHIP_LPC18XX)
<>	144:ef7eb2e8f9f7	922	__I uint32_t RESERVED5[191];
<>	144:ef7eb2e8f9f7	923	#else
<>	144:ef7eb2e8f9f7	924	__I uint32_t RESERVED5[127];
<>	144:ef7eb2e8f9f7	925	__IO uint32_t M0TXEVENT; /* M0 IPC Event register */
<>	144:ef7eb2e8f9f7	926	__IO uint32_t M0APPMEMMAP; /* ARM Cortex M0 memory mapping */
<>	144:ef7eb2e8f9f7	927	__I uint32_t RESERVED6[62];
<>	144:ef7eb2e8f9f7	928	#endif
<>	144:ef7eb2e8f9f7	929	__IO uint32_t USB0FLADJ; /* USB0 frame length adjust register */
<>	144:ef7eb2e8f9f7	930	__I uint32_t RESERVED7[63];
<>	144:ef7eb2e8f9f7	931	__IO uint32_t USB1FLADJ; /* USB1 frame length adjust register */
<>	144:ef7eb2e8f9f7	932	} LPC_CREG_T;
<>	144:ef7eb2e8f9f7	933
<>	144:ef7eb2e8f9f7	934	/* ---------------------------------------------------------------------------
<>	144:ef7eb2e8f9f7	935	* Event Router register structure
<>	144:ef7eb2e8f9f7	936	*/
<>	144:ef7eb2e8f9f7	937	#define LPC_EVRT_BASE 0x40044000
<>	144:ef7eb2e8f9f7	938
<>	144:ef7eb2e8f9f7	939	typedef struct { /* EVENTROUTER Structure */
<>	144:ef7eb2e8f9f7	940	__IO uint32_t HILO; /* Level configuration register */
<>	144:ef7eb2e8f9f7	941	__IO uint32_t EDGE; /* Edge configuration */
<>	144:ef7eb2e8f9f7	942	__I uint32_t RESERVED0[1012];
<>	144:ef7eb2e8f9f7	943	__O uint32_t CLR_EN; /* Event clear enable register */
<>	144:ef7eb2e8f9f7	944	__O uint32_t SET_EN; /* Event set enable register */
<>	144:ef7eb2e8f9f7	945	__I uint32_t STATUS; /* Status register */
<>	144:ef7eb2e8f9f7	946	__I uint32_t ENABLE; /* Enable register */
<>	144:ef7eb2e8f9f7	947	__O uint32_t CLR_STAT; /* Clear register */
<>	144:ef7eb2e8f9f7	948	__O uint32_t SET_STAT; /* Set register */
<>	144:ef7eb2e8f9f7	949	} LPC_EVRT_T;
<>	144:ef7eb2e8f9f7	950
<>	144:ef7eb2e8f9f7	951	/* ---------------------------------------------------------------------------
<>	144:ef7eb2e8f9f7	952	* Real Time Clock register block structure
<>	144:ef7eb2e8f9f7	953	*/
<>	144:ef7eb2e8f9f7	954	#define LPC_RTC_BASE 0x40046000
<>	144:ef7eb2e8f9f7	955	#define RTC_EV_SUPPORT 1 /* Event Monitor/Recorder support */
<>	144:ef7eb2e8f9f7	956
<>	144:ef7eb2e8f9f7	957	typedef enum RTC_TIMEINDEX {
<>	144:ef7eb2e8f9f7	958	RTC_TIMETYPE_SECOND, /* Second */
<>	144:ef7eb2e8f9f7	959	RTC_TIMETYPE_MINUTE, /* Month */
<>	144:ef7eb2e8f9f7	960	RTC_TIMETYPE_HOUR, /* Hour */
<>	144:ef7eb2e8f9f7	961	RTC_TIMETYPE_DAYOFMONTH, /* Day of month */
<>	144:ef7eb2e8f9f7	962	RTC_TIMETYPE_DAYOFWEEK, /* Day of week */
<>	144:ef7eb2e8f9f7	963	RTC_TIMETYPE_DAYOFYEAR, /* Day of year */
<>	144:ef7eb2e8f9f7	964	RTC_TIMETYPE_MONTH, /* Month */
<>	144:ef7eb2e8f9f7	965	RTC_TIMETYPE_YEAR, /* Year */
<>	144:ef7eb2e8f9f7	966	RTC_TIMETYPE_LAST
<>	144:ef7eb2e8f9f7	967	} RTC_TIMEINDEX_T;
<>	144:ef7eb2e8f9f7	968
<>	144:ef7eb2e8f9f7	969	#if RTC_EV_SUPPORT
<>	144:ef7eb2e8f9f7	970	typedef enum LPC_RTC_EV_CHANNEL {
<>	144:ef7eb2e8f9f7	971	RTC_EV_CHANNEL_1 = 0,
<>	144:ef7eb2e8f9f7	972	RTC_EV_CHANNEL_2,
<>	144:ef7eb2e8f9f7	973	RTC_EV_CHANNEL_3,
<>	144:ef7eb2e8f9f7	974	RTC_EV_CHANNEL_NUM,
<>	144:ef7eb2e8f9f7	975	} LPC_RTC_EV_CHANNEL_T;
<>	144:ef7eb2e8f9f7	976	#endif /RTC_EV_SUPPORT/
<>	144:ef7eb2e8f9f7	977
<>	144:ef7eb2e8f9f7	978	typedef struct { /* RTC Structure */
<>	144:ef7eb2e8f9f7	979	__IO uint32_t ILR; /* Interrupt Location Register */
<>	144:ef7eb2e8f9f7	980	__I uint32_t RESERVED0;
<>	144:ef7eb2e8f9f7	981	__IO uint32_t CCR; /* Clock Control Register */
<>	144:ef7eb2e8f9f7	982	__IO uint32_t CIIR; /* Counter Increment Interrupt Register */
<>	144:ef7eb2e8f9f7	983	__IO uint32_t AMR; /* Alarm Mask Register */
<>	144:ef7eb2e8f9f7	984	__I uint32_t CTIME[3]; /* Consolidated Time Register 0,1,2 */
<>	144:ef7eb2e8f9f7	985	__IO uint32_t TIME[RTC_TIMETYPE_LAST]; /* Timer field registers */
<>	144:ef7eb2e8f9f7	986	__IO uint32_t CALIBRATION; /* Calibration Value Register */
<>	144:ef7eb2e8f9f7	987	__I uint32_t RESERVED1[7];
<>	144:ef7eb2e8f9f7	988	__IO uint32_t ALRM[RTC_TIMETYPE_LAST]; /* Alarm field registers */
<>	144:ef7eb2e8f9f7	989	#if RTC_EV_SUPPORT
<>	144:ef7eb2e8f9f7	990	__IO uint32_t ERSTATUS; /* Event Monitor/Recorder Status register*/
<>	144:ef7eb2e8f9f7	991	__IO uint32_t ERCONTROL; /* Event Monitor/Recorder Control register*/
<>	144:ef7eb2e8f9f7	992	__I uint32_t ERCOUNTERS; /* Event Monitor/Recorder Counters register*/
<>	144:ef7eb2e8f9f7	993	__I uint32_t RESERVED2;
<>	144:ef7eb2e8f9f7	994	__I uint32_t ERFIRSTSTAMP[RTC_EV_CHANNEL_NUM]; /* Event Monitor/Recorder First Stamp registers*/
<>	144:ef7eb2e8f9f7	995	__I uint32_t RESERVED3;
<>	144:ef7eb2e8f9f7	996	__I uint32_t ERLASTSTAMP[RTC_EV_CHANNEL_NUM]; /* Event Monitor/Recorder Last Stamp registers*/
<>	144:ef7eb2e8f9f7	997	#endif /RTC_EV_SUPPORT/
<>	144:ef7eb2e8f9f7	998	} LPC_RTC_T;
<>	144:ef7eb2e8f9f7	999
<>	144:ef7eb2e8f9f7	1000	/* ---------------------------------------------------------------------------
<>	144:ef7eb2e8f9f7	1001	* LPC18XX/43XX CGU register block structure
<>	144:ef7eb2e8f9f7	1002	*/
<>	144:ef7eb2e8f9f7	1003	#define LPC_CGU_BASE 0x40050000
<>	144:ef7eb2e8f9f7	1004	#define LPC_CCU1_BASE 0x40051000
<>	144:ef7eb2e8f9f7	1005	#define LPC_CCU2_BASE 0x40052000
<>	144:ef7eb2e8f9f7	1006	/*
<>	144:ef7eb2e8f9f7	1007	* Input clocks for the CGU and can come from both external (crystal) and
<>	144:ef7eb2e8f9f7	1008	* internal (PLL) sources. Can be routed to the base clocks.
<>	144:ef7eb2e8f9f7	1009	*/
<>	144:ef7eb2e8f9f7	1010	typedef enum CGU_CLKIN {
<>	144:ef7eb2e8f9f7	1011	CLKIN_32K, /* External 32KHz input */
<>	144:ef7eb2e8f9f7	1012	CLKIN_IRC, /* Internal IRC (12MHz) input */
<>	144:ef7eb2e8f9f7	1013	CLKIN_ENET_RX, /* External ENET_RX pin input */
<>	144:ef7eb2e8f9f7	1014	CLKIN_ENET_TX, /* External ENET_TX pin input */
<>	144:ef7eb2e8f9f7	1015	CLKIN_CLKIN, /* External GPCLKIN pin input */
<>	144:ef7eb2e8f9f7	1016	CLKIN_RESERVED1,
<>	144:ef7eb2e8f9f7	1017	CLKIN_CRYSTAL, /* External (main) crystal pin input */
<>	144:ef7eb2e8f9f7	1018	CLKIN_USBPLL, /* Internal USB PLL input */
<>	144:ef7eb2e8f9f7	1019	CLKIN_AUDIOPLL, /* Internal Audio PLL input */
<>	144:ef7eb2e8f9f7	1020	CLKIN_MAINPLL, /* Internal Main PLL input */
<>	144:ef7eb2e8f9f7	1021	CLKIN_RESERVED2,
<>	144:ef7eb2e8f9f7	1022	CLKIN_RESERVED3,
<>	144:ef7eb2e8f9f7	1023	CLKIN_IDIVA, /* Internal divider A input */
<>	144:ef7eb2e8f9f7	1024	CLKIN_IDIVB, /* Internal divider B input */
<>	144:ef7eb2e8f9f7	1025	CLKIN_IDIVC, /* Internal divider C input */
<>	144:ef7eb2e8f9f7	1026	CLKIN_IDIVD, /* Internal divider D input */
<>	144:ef7eb2e8f9f7	1027	CLKIN_IDIVE, /* Internal divider E input */
<>	144:ef7eb2e8f9f7	1028	CLKINPUT_PD /* External 32KHz input */
<>	144:ef7eb2e8f9f7	1029	} CGU_CLKIN_T;
<>	144:ef7eb2e8f9f7	1030
<>	144:ef7eb2e8f9f7	1031	#define CLKIN_PLL0USB CLKIN_USBPLL
<>	144:ef7eb2e8f9f7	1032	#define CLKIN_PLL0AUDIO CLKIN_AUDIOPLL
<>	144:ef7eb2e8f9f7	1033	#define CLKIN_PLL1 CLKIN_MAINPLL
<>	144:ef7eb2e8f9f7	1034
<>	144:ef7eb2e8f9f7	1035	/*
<>	144:ef7eb2e8f9f7	1036	* CGU base clocks are clocks that are associated with a single input clock
<>	144:ef7eb2e8f9f7	1037	* and are routed out to 1 or more peripherals. For example, the CLK_BASE_PERIPH
<>	144:ef7eb2e8f9f7	1038	* clock can be configured to use the CLKIN_MAINPLL input clock, which will in
<>	144:ef7eb2e8f9f7	1039	* turn route that clock to the CLK_PERIPH_BUS, CLK_PERIPH_CORE, and
<>	144:ef7eb2e8f9f7	1040	* CLK_PERIPH_SGPIO periphral clocks.
<>	144:ef7eb2e8f9f7	1041	*/
<>	144:ef7eb2e8f9f7	1042	typedef enum CGU_BASE_CLK {
<>	144:ef7eb2e8f9f7	1043	CLK_BASE_SAFE, /* Base clock for WDT oscillator, IRC input only */
<>	144:ef7eb2e8f9f7	1044	CLK_BASE_USB0, /* Base USB clock for USB0, USB PLL input only */
<>	144:ef7eb2e8f9f7	1045	#if defined(CHIP_LPC43XX)
<>	144:ef7eb2e8f9f7	1046	CLK_BASE_PERIPH, /* Base clock for SGPIO */
<>	144:ef7eb2e8f9f7	1047	#else
<>	144:ef7eb2e8f9f7	1048	CLK_BASE_RESERVED1,
<>	144:ef7eb2e8f9f7	1049	#endif
<>	144:ef7eb2e8f9f7	1050	CLK_BASE_USB1, /* Base USB clock for USB1 */
<>	144:ef7eb2e8f9f7	1051	CLK_BASE_MX, /* Base clock for CPU core */
<>	144:ef7eb2e8f9f7	1052	CLK_BASE_SPIFI, /* Base clock for SPIFI */
<>	144:ef7eb2e8f9f7	1053	#if defined(CHIP_LPC43XX)
<>	144:ef7eb2e8f9f7	1054	CLK_BASE_SPI, /* Base clock for SPI */
<>	144:ef7eb2e8f9f7	1055	#else
<>	144:ef7eb2e8f9f7	1056	CLK_BASE_RESERVED2,
<>	144:ef7eb2e8f9f7	1057	#endif
<>	144:ef7eb2e8f9f7	1058	CLK_BASE_PHY_RX, /* Base clock for PHY RX */
<>	144:ef7eb2e8f9f7	1059	CLK_BASE_PHY_TX, /* Base clock for PHY TX */
<>	144:ef7eb2e8f9f7	1060	CLK_BASE_APB1, /* Base clock for APB1 group */
<>	144:ef7eb2e8f9f7	1061	CLK_BASE_APB3, /* Base clock for APB3 group */
<>	144:ef7eb2e8f9f7	1062	CLK_BASE_LCD, /* Base clock for LCD pixel clock */
<>	144:ef7eb2e8f9f7	1063	#if defined(CHIP_LPC43XX)
<>	144:ef7eb2e8f9f7	1064	CLK_BASE_VADC, /* Base clock for VADC */
<>	144:ef7eb2e8f9f7	1065	#else
<>	144:ef7eb2e8f9f7	1066	CLK_BASE_RESERVED3,
<>	144:ef7eb2e8f9f7	1067	#endif
<>	144:ef7eb2e8f9f7	1068	CLK_BASE_SDIO, /* Base clock for SDIO */
<>	144:ef7eb2e8f9f7	1069	CLK_BASE_SSP0, /* Base clock for SSP0 */
<>	144:ef7eb2e8f9f7	1070	CLK_BASE_SSP1, /* Base clock for SSP1 */
<>	144:ef7eb2e8f9f7	1071	CLK_BASE_UART0, /* Base clock for UART0 */
<>	144:ef7eb2e8f9f7	1072	CLK_BASE_UART1, /* Base clock for UART1 */
<>	144:ef7eb2e8f9f7	1073	CLK_BASE_UART2, /* Base clock for UART2 */
<>	144:ef7eb2e8f9f7	1074	CLK_BASE_UART3, /* Base clock for UART3 */
<>	144:ef7eb2e8f9f7	1075	CLK_BASE_OUT, /* Base clock for CLKOUT pin */
<>	144:ef7eb2e8f9f7	1076	CLK_BASE_RESERVED4,
<>	144:ef7eb2e8f9f7	1077	CLK_BASE_RESERVED5,
<>	144:ef7eb2e8f9f7	1078	CLK_BASE_RESERVED6,
<>	144:ef7eb2e8f9f7	1079	CLK_BASE_RESERVED7,
<>	144:ef7eb2e8f9f7	1080	CLK_BASE_APLL, /* Base clock for audio PLL */
<>	144:ef7eb2e8f9f7	1081	CLK_BASE_CGU_OUT0, /* Base clock for CGUOUT0 pin */
<>	144:ef7eb2e8f9f7	1082	CLK_BASE_CGU_OUT1, /* Base clock for CGUOUT1 pin */
<>	144:ef7eb2e8f9f7	1083	CLK_BASE_LAST,
<>	144:ef7eb2e8f9f7	1084	CLK_BASE_NONE = CLK_BASE_LAST
<>	144:ef7eb2e8f9f7	1085	} CGU_BASE_CLK_T;
<>	144:ef7eb2e8f9f7	1086
<>	144:ef7eb2e8f9f7	1087	/*
<>	144:ef7eb2e8f9f7	1088	* CGU dividers provide an extra clock state where a specific clock can be
<>	144:ef7eb2e8f9f7	1089	* divided before being routed to a peripheral group. A divider accepts an
<>	144:ef7eb2e8f9f7	1090	* input clock and then divides it. To use the divided clock for a base clock
<>	144:ef7eb2e8f9f7	1091	* group, use the divider as the input clock for the base clock (for example,
<>	144:ef7eb2e8f9f7	1092	* use CLKIN_IDIVB, where CLKIN_MAINPLL might be the input into the divider).
<>	144:ef7eb2e8f9f7	1093	*/
<>	144:ef7eb2e8f9f7	1094	typedef enum CGU_IDIV {
<>	144:ef7eb2e8f9f7	1095	CLK_IDIV_A, /* CGU clock divider A */
<>	144:ef7eb2e8f9f7	1096	CLK_IDIV_B, /* CGU clock divider B */
<>	144:ef7eb2e8f9f7	1097	CLK_IDIV_C, /* CGU clock divider A */
<>	144:ef7eb2e8f9f7	1098	CLK_IDIV_D, /* CGU clock divider D */
<>	144:ef7eb2e8f9f7	1099	CLK_IDIV_E, /* CGU clock divider E */
<>	144:ef7eb2e8f9f7	1100	CLK_IDIV_LAST
<>	144:ef7eb2e8f9f7	1101	} CGU_IDIV_T;
<>	144:ef7eb2e8f9f7	1102
<>	144:ef7eb2e8f9f7	1103	/*
<>	144:ef7eb2e8f9f7	1104	* Peripheral clocks are individual clocks routed to peripherals. Although
<>	144:ef7eb2e8f9f7	1105	* multiple peripherals may share a same base clock, each peripheral's clock
<>	144:ef7eb2e8f9f7	1106	* can be enabled or disabled individually. Some peripheral clocks also have
<>	144:ef7eb2e8f9f7	1107	* additional dividers associated with them.
<>	144:ef7eb2e8f9f7	1108	*/
<>	144:ef7eb2e8f9f7	1109	typedef enum CCU_CLK {
<>	144:ef7eb2e8f9f7	1110	/* CCU1 clocks */
<>	144:ef7eb2e8f9f7	1111	CLK_APB3_BUS, /* APB3 bus clock from base clock CLK_BASE_APB3 */
<>	144:ef7eb2e8f9f7	1112	CLK_APB3_I2C1, /* I2C1 register/perigheral clock from base clock CLK_BASE_APB3 */
<>	144:ef7eb2e8f9f7	1113	CLK_APB3_DAC, /* DAC peripheral clock from base clock CLK_BASE_APB3 */
<>	144:ef7eb2e8f9f7	1114	CLK_APB3_ADC0, /* ADC0 register/perigheral clock from base clock CLK_BASE_APB3 */
<>	144:ef7eb2e8f9f7	1115	CLK_APB3_ADC1, /* ADC1 register/perigheral clock from base clock CLK_BASE_APB3 */
<>	144:ef7eb2e8f9f7	1116	CLK_APB3_CAN0, /* CAN0 register/perigheral clock from base clock CLK_BASE_APB3 */
<>	144:ef7eb2e8f9f7	1117	CLK_APB1_BUS = 32, /* APB1 bus clock clock from base clock CLK_BASE_APB1 */
<>	144:ef7eb2e8f9f7	1118	CLK_APB1_MOTOCON, /* Motor controller register/perigheral clock from base clock CLK_BASE_APB1 */
<>	144:ef7eb2e8f9f7	1119	CLK_APB1_I2C0, /* I2C0 register/perigheral clock from base clock CLK_BASE_APB1 */
<>	144:ef7eb2e8f9f7	1120	CLK_APB1_I2S, /* I2S register/perigheral clock from base clock CLK_BASE_APB1 */
<>	144:ef7eb2e8f9f7	1121	CLK_APB1_CAN1, /* CAN1 register/perigheral clock from base clock CLK_BASE_APB1 */
<>	144:ef7eb2e8f9f7	1122	CLK_SPIFI = 64, /* SPIFI SCKI input clock from base clock CLK_BASE_SPIFI */
<>	144:ef7eb2e8f9f7	1123	CLK_MX_BUS = 96, /* M3/M4 BUS core clock from base clock CLK_BASE_MX */
<>	144:ef7eb2e8f9f7	1124	CLK_MX_SPIFI, /* SPIFI register clock from base clock CLK_BASE_MX */
<>	144:ef7eb2e8f9f7	1125	CLK_MX_GPIO, /* GPIO register clock from base clock CLK_BASE_MX */
<>	144:ef7eb2e8f9f7	1126	CLK_MX_LCD, /* LCD register clock from base clock CLK_BASE_MX */
<>	144:ef7eb2e8f9f7	1127	CLK_MX_ETHERNET, /* ETHERNET register clock from base clock CLK_BASE_MX */
<>	144:ef7eb2e8f9f7	1128	CLK_MX_USB0, /* USB0 register clock from base clock CLK_BASE_MX */
<>	144:ef7eb2e8f9f7	1129	CLK_MX_EMC, /* EMC clock from base clock CLK_BASE_MX */
<>	144:ef7eb2e8f9f7	1130	CLK_MX_SDIO, /* SDIO register clock from base clock CLK_BASE_MX */
<>	144:ef7eb2e8f9f7	1131	CLK_MX_DMA, /* DMA register clock from base clock CLK_BASE_MX */
<>	144:ef7eb2e8f9f7	1132	CLK_MX_MXCORE, /* M3/M4 CPU core clock from base clock CLK_BASE_MX */
<>	144:ef7eb2e8f9f7	1133	RESERVED_ALIGN = CLK_MX_MXCORE + 3,
<>	144:ef7eb2e8f9f7	1134	CLK_MX_SCT, /* SCT register clock from base clock CLK_BASE_MX */
<>	144:ef7eb2e8f9f7	1135	CLK_MX_USB1, /* USB1 register clock from base clock CLK_BASE_MX */
<>	144:ef7eb2e8f9f7	1136	CLK_MX_EMC_DIV, /* ENC divider clock from base clock CLK_BASE_MX */
<>	144:ef7eb2e8f9f7	1137	CLK_MX_FLASHA, /* FLASHA bank clock from base clock CLK_BASE_MX */
<>	144:ef7eb2e8f9f7	1138	CLK_MX_FLASHB, /* FLASHB bank clock from base clock CLK_BASE_MX */
<>	144:ef7eb2e8f9f7	1139	#if defined(CHIP_LPC43XX)
<>	144:ef7eb2e8f9f7	1140	CLK_M4_M0APP, /* M0 app CPU core clock from base clock CLK_BASE_MX */
<>	144:ef7eb2e8f9f7	1141	CLK_MX_VADC, /* VADC clock from base clock CLK_BASE_MX */
<>	144:ef7eb2e8f9f7	1142	#else
<>	144:ef7eb2e8f9f7	1143	CLK_RESERVED1,
<>	144:ef7eb2e8f9f7	1144	CLK_RESERVED2,
<>	144:ef7eb2e8f9f7	1145	#endif
<>	144:ef7eb2e8f9f7	1146	CLK_MX_EEPROM, /* EEPROM clock from base clock CLK_BASE_MX */
<>	144:ef7eb2e8f9f7	1147	CLK_MX_WWDT = 128, /* WWDT register clock from base clock CLK_BASE_MX */
<>	144:ef7eb2e8f9f7	1148	CLK_MX_UART0, /* UART0 register clock from base clock CLK_BASE_MX */
<>	144:ef7eb2e8f9f7	1149	CLK_MX_UART1, /* UART1 register clock from base clock CLK_BASE_MX */
<>	144:ef7eb2e8f9f7	1150	CLK_MX_SSP0, /* SSP0 register clock from base clock CLK_BASE_MX */
<>	144:ef7eb2e8f9f7	1151	CLK_MX_TIMER0, /* TIMER0 register/perigheral clock from base clock CLK_BASE_MX */
<>	144:ef7eb2e8f9f7	1152	CLK_MX_TIMER1, /* TIMER1 register/perigheral clock from base clock CLK_BASE_MX */
<>	144:ef7eb2e8f9f7	1153	CLK_MX_SCU, /* SCU register/perigheral clock from base clock CLK_BASE_MX */
<>	144:ef7eb2e8f9f7	1154	CLK_MX_CREG, /* CREG clock from base clock CLK_BASE_MX */
<>	144:ef7eb2e8f9f7	1155	CLK_MX_RITIMER = 160, /* RITIMER register/perigheral clock from base clock CLK_BASE_MX */
<>	144:ef7eb2e8f9f7	1156	CLK_MX_UART2, /* UART3 register clock from base clock CLK_BASE_MX */
<>	144:ef7eb2e8f9f7	1157	CLK_MX_UART3, /* UART4 register clock from base clock CLK_BASE_MX */
<>	144:ef7eb2e8f9f7	1158	CLK_MX_TIMER2, /* TIMER2 register/perigheral clock from base clock CLK_BASE_MX */
<>	144:ef7eb2e8f9f7	1159	CLK_MX_TIMER3, /* TIMER3 register/perigheral clock from base clock CLK_BASE_MX */
<>	144:ef7eb2e8f9f7	1160	CLK_MX_SSP1, /* SSP1 register clock from base clock CLK_BASE_MX */
<>	144:ef7eb2e8f9f7	1161	CLK_MX_QEI, /* QEI register/perigheral clock from base clock CLK_BASE_MX */
<>	144:ef7eb2e8f9f7	1162	#if defined(CHIP_LPC43XX)
<>	144:ef7eb2e8f9f7	1163	CLK_PERIPH_BUS = 192, /* Peripheral bus clock from base clock CLK_BASE_PERIPH */
<>	144:ef7eb2e8f9f7	1164	CLK_RESERVED3,
<>	144:ef7eb2e8f9f7	1165	CLK_PERIPH_CORE, /* Peripheral core clock from base clock CLK_BASE_PERIPH */
<>	144:ef7eb2e8f9f7	1166	CLK_PERIPH_SGPIO, /* SGPIO clock from base clock CLK_BASE_PERIPH */
<>	144:ef7eb2e8f9f7	1167	#else
<>	144:ef7eb2e8f9f7	1168	CLK_RESERVED3 = 192,
<>	144:ef7eb2e8f9f7	1169	CLK_RESERVED3A,
<>	144:ef7eb2e8f9f7	1170	CLK_RESERVED4,
<>	144:ef7eb2e8f9f7	1171	CLK_RESERVED5,
<>	144:ef7eb2e8f9f7	1172	#endif
<>	144:ef7eb2e8f9f7	1173	CLK_USB0 = 224, /* USB0 clock from base clock CLK_BASE_USB0 */
<>	144:ef7eb2e8f9f7	1174	CLK_USB1 = 256, /* USB1 clock from base clock CLK_BASE_USB1 */
<>	144:ef7eb2e8f9f7	1175	#if defined(CHIP_LPC43XX)
<>	144:ef7eb2e8f9f7	1176	CLK_SPI = 288, /* SPI clock from base clock CLK_BASE_SPI */
<>	144:ef7eb2e8f9f7	1177	CLK_VADC, /* VADC clock from base clock CLK_BASE_VADC */
<>	144:ef7eb2e8f9f7	1178	#else
<>	144:ef7eb2e8f9f7	1179	CLK_RESERVED7 = 320,
<>	144:ef7eb2e8f9f7	1180	CLK_RESERVED8,
<>	144:ef7eb2e8f9f7	1181	#endif
<>	144:ef7eb2e8f9f7	1182	CLK_CCU1_LAST,
<>	144:ef7eb2e8f9f7	1183
<>	144:ef7eb2e8f9f7	1184	/* CCU2 clocks */
<>	144:ef7eb2e8f9f7	1185	CLK_CCU2_START,
<>	144:ef7eb2e8f9f7	1186	CLK_APLL = CLK_CCU2_START, /* Audio PLL clock from base clock CLK_BASE_APLL */
<>	144:ef7eb2e8f9f7	1187	RESERVED_ALIGNB = CLK_CCU2_START + 31,
<>	144:ef7eb2e8f9f7	1188	CLK_APB2_UART3, /* UART3 clock from base clock CLK_BASE_UART3 */
<>	144:ef7eb2e8f9f7	1189	RESERVED_ALIGNC = CLK_CCU2_START + 63,
<>	144:ef7eb2e8f9f7	1190	CLK_APB2_UART2, /* UART2 clock from base clock CLK_BASE_UART2 */
<>	144:ef7eb2e8f9f7	1191	RESERVED_ALIGND = CLK_CCU2_START + 95,
<>	144:ef7eb2e8f9f7	1192	CLK_APB0_UART1, /* UART1 clock from base clock CLK_BASE_UART1 */
<>	144:ef7eb2e8f9f7	1193	RESERVED_ALIGNE = CLK_CCU2_START + 127,
<>	144:ef7eb2e8f9f7	1194	CLK_APB0_UART0, /* UART0 clock from base clock CLK_BASE_UART0 */
<>	144:ef7eb2e8f9f7	1195	RESERVED_ALIGNF = CLK_CCU2_START + 159,
<>	144:ef7eb2e8f9f7	1196	CLK_APB2_SSP1, /* SSP1 clock from base clock CLK_BASE_SSP1 */
<>	144:ef7eb2e8f9f7	1197	RESERVED_ALIGNG = CLK_CCU2_START + 191,
<>	144:ef7eb2e8f9f7	1198	CLK_APB0_SSP0, /* SSP0 clock from base clock CLK_BASE_SSP0 */
<>	144:ef7eb2e8f9f7	1199	RESERVED_ALIGNH = CLK_CCU2_START + 223,
<>	144:ef7eb2e8f9f7	1200	CLK_APB2_SDIO, /* SDIO clock from base clock CLK_BASE_SDIO */
<>	144:ef7eb2e8f9f7	1201	CLK_CCU2_LAST
<>	144:ef7eb2e8f9f7	1202	} CCU_CLK_T;
<>	144:ef7eb2e8f9f7	1203
<>	144:ef7eb2e8f9f7	1204	/*
<>	144:ef7eb2e8f9f7	1205	* Audio or USB PLL selection
<>	144:ef7eb2e8f9f7	1206	*/
<>	144:ef7eb2e8f9f7	1207	typedef enum CGU_USB_AUDIO_PLL {
<>	144:ef7eb2e8f9f7	1208	CGU_USB_PLL,
<>	144:ef7eb2e8f9f7	1209	CGU_AUDIO_PLL
<>	144:ef7eb2e8f9f7	1210	} CGU_USB_AUDIO_PLL_T;
<>	144:ef7eb2e8f9f7	1211
<>	144:ef7eb2e8f9f7	1212	/*
<>	144:ef7eb2e8f9f7	1213	* PLL register block
<>	144:ef7eb2e8f9f7	1214	*/
<>	144:ef7eb2e8f9f7	1215	typedef struct {
<>	144:ef7eb2e8f9f7	1216	__I uint32_t PLL_STAT; /* PLL status register */
<>	144:ef7eb2e8f9f7	1217	__IO uint32_t PLL_CTRL; /* PLL control register */
<>	144:ef7eb2e8f9f7	1218	__IO uint32_t PLL_MDIV; /* PLL M-divider register */
<>	144:ef7eb2e8f9f7	1219	__IO uint32_t PLL_NP_DIV; /* PLL N/P-divider register */
<>	144:ef7eb2e8f9f7	1220	} CGU_PLL_REG_T;
<>	144:ef7eb2e8f9f7	1221
<>	144:ef7eb2e8f9f7	1222	typedef struct { /* (@ 0x40050000) CGU Structure */
<>	144:ef7eb2e8f9f7	1223	__I uint32_t RESERVED0[5];
<>	144:ef7eb2e8f9f7	1224	__IO uint32_t FREQ_MON; /* (@ 0x40050014) Frequency monitor register */
<>	144:ef7eb2e8f9f7	1225	__IO uint32_t XTAL_OSC_CTRL; /* (@ 0x40050018) Crystal oscillator control register */
<>	144:ef7eb2e8f9f7	1226	CGU_PLL_REG_T PLL[CGU_AUDIO_PLL + 1]; /* (@ 0x4005001C) USB and audio PLL blocks */
<>	144:ef7eb2e8f9f7	1227	__IO uint32_t PLL0AUDIO_FRAC; /* (@ 0x4005003C) PLL0 (audio) */
<>	144:ef7eb2e8f9f7	1228	__I uint32_t PLL1_STAT; /* (@ 0x40050040) PLL1 status register */
<>	144:ef7eb2e8f9f7	1229	__IO uint32_t PLL1_CTRL; /* (@ 0x40050044) PLL1 control register */
<>	144:ef7eb2e8f9f7	1230	__IO uint32_t IDIV_CTRL[CLK_IDIV_LAST];/* (@ 0x40050048) Integer divider A-E control registers */
<>	144:ef7eb2e8f9f7	1231	__IO uint32_t BASE_CLK[CLK_BASE_LAST]; /* (@ 0x4005005C) Start of base clock registers */
<>	144:ef7eb2e8f9f7	1232	} LPC_CGU_T;
<>	144:ef7eb2e8f9f7	1233
<>	144:ef7eb2e8f9f7	1234	/* ---------------------------------------------------------------------------
<>	144:ef7eb2e8f9f7	1235	* CCU clock config/status register pair
<>	144:ef7eb2e8f9f7	1236	*/
<>	144:ef7eb2e8f9f7	1237	typedef struct {
<>	144:ef7eb2e8f9f7	1238	__IO uint32_t CFG; /* CCU clock configuration register */
<>	144:ef7eb2e8f9f7	1239	__I uint32_t STAT; /* CCU clock status register */
<>	144:ef7eb2e8f9f7	1240	} CCU_CFGSTAT_T;
<>	144:ef7eb2e8f9f7	1241
<>	144:ef7eb2e8f9f7	1242	/* ---------------------------------------------------------------------------
<>	144:ef7eb2e8f9f7	1243	* CCU1 register block structure
<>	144:ef7eb2e8f9f7	1244	*/
<>	144:ef7eb2e8f9f7	1245	typedef struct { /* (@ 0x40051000) CCU1 Structure */
<>	144:ef7eb2e8f9f7	1246	__IO uint32_t PM; /* (@ 0x40051000) CCU1 power mode register */
<>	144:ef7eb2e8f9f7	1247	__I uint32_t BASE_STAT; /* (@ 0x40051004) CCU1 base clocks status register */
<>	144:ef7eb2e8f9f7	1248	__I uint32_t RESERVED0[62];
<>	144:ef7eb2e8f9f7	1249	CCU_CFGSTAT_T CLKCCU[CLK_CCU1_LAST]; /* (@ 0x40051100) Start of CCU1 clock registers */
<>	144:ef7eb2e8f9f7	1250	} LPC_CCU1_T;
<>	144:ef7eb2e8f9f7	1251
<>	144:ef7eb2e8f9f7	1252	/* ---------------------------------------------------------------------------
<>	144:ef7eb2e8f9f7	1253	* CCU2 register block structure
<>	144:ef7eb2e8f9f7	1254	*/
<>	144:ef7eb2e8f9f7	1255	typedef struct { /* (@ 0x40052000) CCU2 Structure */
<>	144:ef7eb2e8f9f7	1256	__IO uint32_t PM; /* (@ 0x40052000) Power mode register */
<>	144:ef7eb2e8f9f7	1257	__I uint32_t BASE_STAT; /* (@ 0x40052004) CCU base clocks status register */
<>	144:ef7eb2e8f9f7	1258	__I uint32_t RESERVED0[62];
<>	144:ef7eb2e8f9f7	1259	CCU_CFGSTAT_T CLKCCU[CLK_CCU2_LAST - CLK_CCU1_LAST]; /* (@ 0x40052100) Start of CCU2 clock registers */
<>	144:ef7eb2e8f9f7	1260	} LPC_CCU2_T;
<>	144:ef7eb2e8f9f7	1261
<>	144:ef7eb2e8f9f7	1262	/* ---------------------------------------------------------------------------
<>	144:ef7eb2e8f9f7	1263	* RGU register structure
<>	144:ef7eb2e8f9f7	1264	*/
<>	144:ef7eb2e8f9f7	1265	#define LPC_RGU_BASE 0x40053000
<>	144:ef7eb2e8f9f7	1266
<>	144:ef7eb2e8f9f7	1267	typedef enum RGU_RST {
<>	144:ef7eb2e8f9f7	1268	RGU_CORE_RST,
<>	144:ef7eb2e8f9f7	1269	RGU_PERIPH_RST,
<>	144:ef7eb2e8f9f7	1270	RGU_MASTER_RST,
<>	144:ef7eb2e8f9f7	1271	RGU_WWDT_RST = 4,
<>	144:ef7eb2e8f9f7	1272	RGU_CREG_RST,
<>	144:ef7eb2e8f9f7	1273	RGU_BUS_RST = 8,
<>	144:ef7eb2e8f9f7	1274	RGU_SCU_RST,
<>	144:ef7eb2e8f9f7	1275	RGU_M3_RST = 13,
<>	144:ef7eb2e8f9f7	1276	RGU_LCD_RST = 16,
<>	144:ef7eb2e8f9f7	1277	RGU_USB0_RST,
<>	144:ef7eb2e8f9f7	1278	RGU_USB1_RST,
<>	144:ef7eb2e8f9f7	1279	RGU_DMA_RST,
<>	144:ef7eb2e8f9f7	1280	RGU_SDIO_RST,
<>	144:ef7eb2e8f9f7	1281	RGU_EMC_RST,
<>	144:ef7eb2e8f9f7	1282	RGU_ETHERNET_RST,
<>	144:ef7eb2e8f9f7	1283	RGU_FLASHA_RST = 25,
<>	144:ef7eb2e8f9f7	1284	RGU_EEPROM_RST = 27,
<>	144:ef7eb2e8f9f7	1285	RGU_GPIO_RST,
<>	144:ef7eb2e8f9f7	1286	RGU_FLASHB_RST,
<>	144:ef7eb2e8f9f7	1287	RGU_TIMER0_RST = 32,
<>	144:ef7eb2e8f9f7	1288	RGU_TIMER1_RST,
<>	144:ef7eb2e8f9f7	1289	RGU_TIMER2_RST,
<>	144:ef7eb2e8f9f7	1290	RGU_TIMER3_RST,
<>	144:ef7eb2e8f9f7	1291	RGU_RITIMER_RST,
<>	144:ef7eb2e8f9f7	1292	RGU_SCT_RST,
<>	144:ef7eb2e8f9f7	1293	RGU_MOTOCONPWM_RST,
<>	144:ef7eb2e8f9f7	1294	RGU_QEI_RST,
<>	144:ef7eb2e8f9f7	1295	RGU_ADC0_RST,
<>	144:ef7eb2e8f9f7	1296	RGU_ADC1_RST,
<>	144:ef7eb2e8f9f7	1297	RGU_DAC_RST,
<>	144:ef7eb2e8f9f7	1298	RGU_UART0_RST = 44,
<>	144:ef7eb2e8f9f7	1299	RGU_UART1_RST,
<>	144:ef7eb2e8f9f7	1300	RGU_UART2_RST,
<>	144:ef7eb2e8f9f7	1301	RGU_UART3_RST,
<>	144:ef7eb2e8f9f7	1302	RGU_I2C0_RST,
<>	144:ef7eb2e8f9f7	1303	RGU_I2C1_RST,
<>	144:ef7eb2e8f9f7	1304	RGU_SSP0_RST,
<>	144:ef7eb2e8f9f7	1305	RGU_SSP1_RST,
<>	144:ef7eb2e8f9f7	1306	RGU_I2S_RST,
<>	144:ef7eb2e8f9f7	1307	RGU_SPIFI_RST,
<>	144:ef7eb2e8f9f7	1308	RGU_CAN1_RST,
<>	144:ef7eb2e8f9f7	1309	RGU_CAN0_RST,
<>	144:ef7eb2e8f9f7	1310	#ifdef CHIP_LPC43XX
<>	144:ef7eb2e8f9f7	1311	RGU_M0APP_RST,
<>	144:ef7eb2e8f9f7	1312	RGU_SGPIO_RST,
<>	144:ef7eb2e8f9f7	1313	RGU_SPI_RST,
<>	144:ef7eb2e8f9f7	1314	#endif
<>	144:ef7eb2e8f9f7	1315	RGU_LAST_RST = 63,
<>	144:ef7eb2e8f9f7	1316	} RGU_RST_T;
<>	144:ef7eb2e8f9f7	1317
<>	144:ef7eb2e8f9f7	1318	typedef struct { /* RGU Structure */
<>	144:ef7eb2e8f9f7	1319	__I uint32_t RESERVED0[64];
<>	144:ef7eb2e8f9f7	1320	__O uint32_t RESET_CTRL0; /* Reset control register 0 */
<>	144:ef7eb2e8f9f7	1321	__O uint32_t RESET_CTRL1; /* Reset control register 1 */
<>	144:ef7eb2e8f9f7	1322	__I uint32_t RESERVED1[2];
<>	144:ef7eb2e8f9f7	1323	__IO uint32_t RESET_STATUS0; /* Reset status register 0 */
<>	144:ef7eb2e8f9f7	1324	__IO uint32_t RESET_STATUS1; /* Reset status register 1 */
<>	144:ef7eb2e8f9f7	1325	__IO uint32_t RESET_STATUS2; /* Reset status register 2 */
<>	144:ef7eb2e8f9f7	1326	__IO uint32_t RESET_STATUS3; /* Reset status register 3 */
<>	144:ef7eb2e8f9f7	1327	__I uint32_t RESERVED2[12];
<>	144:ef7eb2e8f9f7	1328	__I uint32_t RESET_ACTIVE_STATUS0;/* Reset active status register 0 */
<>	144:ef7eb2e8f9f7	1329	__I uint32_t RESET_ACTIVE_STATUS1;/* Reset active status register 1 */
<>	144:ef7eb2e8f9f7	1330	__I uint32_t RESERVED3[170];
<>	144:ef7eb2e8f9f7	1331	__IO uint32_t RESET_EXT_STAT[RGU_LAST_RST + 1];/* Reset external status registers */
<>	144:ef7eb2e8f9f7	1332	} LPC_RGU_T;
<>	144:ef7eb2e8f9f7	1333
<>	144:ef7eb2e8f9f7	1334	/* ---------------------------------------------------------------------------
<>	144:ef7eb2e8f9f7	1335	* Windowed Watchdog register block structure
<>	144:ef7eb2e8f9f7	1336	*/
<>	144:ef7eb2e8f9f7	1337	#define LPC_WWDT_BASE 0x40080000
<>	144:ef7eb2e8f9f7	1338
<>	144:ef7eb2e8f9f7	1339	typedef struct { /* WWDT Structure */
<>	144:ef7eb2e8f9f7	1340	__IO uint32_t MOD; /* Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */
<>	144:ef7eb2e8f9f7	1341	__IO uint32_t TC; /* Watchdog timer constant register. This register determines the time-out value. */
<>	144:ef7eb2e8f9f7	1342	__O uint32_t FEED; /* Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC. */
<>	144:ef7eb2e8f9f7	1343	__I uint32_t TV; /* Watchdog timer value register. This register reads out the current value of the Watchdog timer. */
<>	144:ef7eb2e8f9f7	1344	#ifdef WATCHDOG_CLKSEL_SUPPORT
<>	144:ef7eb2e8f9f7	1345	__IO uint32_t CLKSEL; /* Watchdog clock select register. */
<>	144:ef7eb2e8f9f7	1346	#else
<>	144:ef7eb2e8f9f7	1347	__I uint32_t RESERVED0;
<>	144:ef7eb2e8f9f7	1348	#endif
<>	144:ef7eb2e8f9f7	1349	#ifdef WATCHDOG_WINDOW_SUPPORT
<>	144:ef7eb2e8f9f7	1350	__IO uint32_t WARNINT; /* Watchdog warning interrupt register. This register contains the Watchdog warning interrupt compare value. */
<>	144:ef7eb2e8f9f7	1351	__IO uint32_t WINDOW; /* Watchdog timer window register. This register contains the Watchdog window value. */
<>	144:ef7eb2e8f9f7	1352	#endif
<>	144:ef7eb2e8f9f7	1353	} LPC_WWDT_T;
<>	144:ef7eb2e8f9f7	1354
<>	144:ef7eb2e8f9f7	1355	/* ---------------------------------------------------------------------------
<>	144:ef7eb2e8f9f7	1356	* USART register block structure
<>	144:ef7eb2e8f9f7	1357	*/
<>	144:ef7eb2e8f9f7	1358	#define LPC_USART0_BASE 0x40081000
<>	144:ef7eb2e8f9f7	1359	#define LPC_UART1_BASE 0x40082000
<>	144:ef7eb2e8f9f7	1360	#define LPC_USART2_BASE 0x400C1000
<>	144:ef7eb2e8f9f7	1361	#define LPC_USART3_BASE 0x400C2000
<>	144:ef7eb2e8f9f7	1362
<>	144:ef7eb2e8f9f7	1363	typedef struct { /* USARTn Structure */
<>	144:ef7eb2e8f9f7	1364
<>	144:ef7eb2e8f9f7	1365	union {
<>	144:ef7eb2e8f9f7	1366	__IO uint32_t DLL; /* Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). */
<>	144:ef7eb2e8f9f7	1367	__O uint32_t THR; /* Transmit Holding Register. The next character to be transmitted is written here (DLAB = 0). */
<>	144:ef7eb2e8f9f7	1368	__I uint32_t RBR; /* Receiver Buffer Register. Contains the next received character to be read (DLAB = 0). */
<>	144:ef7eb2e8f9f7	1369	};
<>	144:ef7eb2e8f9f7	1370
<>	144:ef7eb2e8f9f7	1371	union {
<>	144:ef7eb2e8f9f7	1372	__IO uint32_t IER; /* Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB = 0). */
<>	144:ef7eb2e8f9f7	1373	__IO uint32_t DLM; /* Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). */
<>	144:ef7eb2e8f9f7	1374	};
<>	144:ef7eb2e8f9f7	1375
<>	144:ef7eb2e8f9f7	1376	union {
<>	144:ef7eb2e8f9f7	1377	__O uint32_t FCR; /* FIFO Control Register. Controls UART FIFO usage and modes. */
<>	144:ef7eb2e8f9f7	1378	__I uint32_t IIR; /* Interrupt ID Register. Identifies which interrupt(s) are pending. */
<>	144:ef7eb2e8f9f7	1379	};
<>	144:ef7eb2e8f9f7	1380
<>	144:ef7eb2e8f9f7	1381	__IO uint32_t LCR; /* Line Control Register. Contains controls for frame formatting and break generation. */
<>	144:ef7eb2e8f9f7	1382	__IO uint32_t MCR; /* Modem Control Register. Only present on USART ports with full modem support. */
<>	144:ef7eb2e8f9f7	1383	__I uint32_t LSR; /* Line Status Register. Contains flags for transmit and receive status, including line errors. */
<>	144:ef7eb2e8f9f7	1384	__I uint32_t MSR; /* Modem Status Register. Only present on USART ports with full modem support. */
<>	144:ef7eb2e8f9f7	1385	__IO uint32_t SCR; /* Scratch Pad Register. Eight-bit temporary storage for software. */
<>	144:ef7eb2e8f9f7	1386	__IO uint32_t ACR; /* Auto-baud Control Register. Contains controls for the auto-baud feature. */
<>	144:ef7eb2e8f9f7	1387	__IO uint32_t ICR; /* IrDA control register (not all UARTS) */
<>	144:ef7eb2e8f9f7	1388	__IO uint32_t FDR; /* Fractional Divider Register. Generates a clock input for the baud rate divider. */
<>	144:ef7eb2e8f9f7	1389	__IO uint32_t OSR; /* Oversampling Register. Controls the degree of oversampling during each bit time. Only on some UARTS. */
<>	144:ef7eb2e8f9f7	1390	__IO uint32_t TER1; /* Transmit Enable Register. Turns off USART transmitter for use with software flow control. */
<>	144:ef7eb2e8f9f7	1391	uint32_t RESERVED0[3];
<>	144:ef7eb2e8f9f7	1392	__IO uint32_t HDEN; /* Half-duplex enable Register- only on some UARTs */
<>	144:ef7eb2e8f9f7	1393	__I uint32_t RESERVED1[1];
<>	144:ef7eb2e8f9f7	1394	__IO uint32_t SCICTRL; /* Smart card interface control register- only on some UARTs */
<>	144:ef7eb2e8f9f7	1395	__IO uint32_t RS485CTRL; /* RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */
<>	144:ef7eb2e8f9f7	1396	__IO uint32_t RS485ADRMATCH; /* RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */
<>	144:ef7eb2e8f9f7	1397	__IO uint32_t RS485DLY; /* RS-485/EIA-485 direction control delay. */
<>	144:ef7eb2e8f9f7	1398	union {
<>	144:ef7eb2e8f9f7	1399	__IO uint32_t SYNCCTRL; /* Synchronous mode control register. Only on USARTs. */
<>	144:ef7eb2e8f9f7	1400	__I uint32_t FIFOLVL; /* FIFO Level register. Provides the current fill levels of the transmit and receive FIFOs. */
<>	144:ef7eb2e8f9f7	1401	};
<>	144:ef7eb2e8f9f7	1402
<>	144:ef7eb2e8f9f7	1403	__IO uint32_t TER2; /* Transmit Enable Register. Only on LPC177X_8X UART4 and LPC18XX/43XX USART0/2/3. */
<>	144:ef7eb2e8f9f7	1404	} LPC_USART_T;
<>	144:ef7eb2e8f9f7	1405
<>	144:ef7eb2e8f9f7	1406	/* ---------------------------------------------------------------------------
<>	144:ef7eb2e8f9f7	1407	* SSP register block structure
<>	144:ef7eb2e8f9f7	1408	*/
<>	144:ef7eb2e8f9f7	1409	#define LPC_SSP0_BASE 0x40083000
<>	144:ef7eb2e8f9f7	1410	#define LPC_SSP1_BASE 0x400C5000
<>	144:ef7eb2e8f9f7	1411
<>	144:ef7eb2e8f9f7	1412	typedef struct { /* SSPn Structure */
<>	144:ef7eb2e8f9f7	1413	__IO uint32_t CR0; /* Control Register 0. Selects the serial clock rate, bus type, and data size. */
<>	144:ef7eb2e8f9f7	1414	__IO uint32_t CR1; /* Control Register 1. Selects master/slave and other modes. */
<>	144:ef7eb2e8f9f7	1415	__IO uint32_t DR; /* Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */
<>	144:ef7eb2e8f9f7	1416	__I uint32_t SR; /* Status Register */
<>	144:ef7eb2e8f9f7	1417	__IO uint32_t CPSR; /* Clock Prescale Register */
<>	144:ef7eb2e8f9f7	1418	__IO uint32_t IMSC; /* Interrupt Mask Set and Clear Register */
<>	144:ef7eb2e8f9f7	1419	__I uint32_t RIS; /* Raw Interrupt Status Register */
<>	144:ef7eb2e8f9f7	1420	__I uint32_t MIS; /* Masked Interrupt Status Register */
<>	144:ef7eb2e8f9f7	1421	__O uint32_t ICR; /* SSPICR Interrupt Clear Register */
<>	144:ef7eb2e8f9f7	1422	__IO uint32_t DMACR; /* SSPn DMA control register */
<>	144:ef7eb2e8f9f7	1423	} LPC_SSP_T;
<>	144:ef7eb2e8f9f7	1424
<>	144:ef7eb2e8f9f7	1425	/* ---------------------------------------------------------------------------
<>	144:ef7eb2e8f9f7	1426	* 32-bit Standard timer register block structure
<>	144:ef7eb2e8f9f7	1427	*/
<>	144:ef7eb2e8f9f7	1428	#define LPC_TIMER0_BASE 0x40084000
<>	144:ef7eb2e8f9f7	1429	#define LPC_TIMER1_BASE 0x40085000
<>	144:ef7eb2e8f9f7	1430	#define LPC_TIMER2_BASE 0x400C3000
<>	144:ef7eb2e8f9f7	1431	#define LPC_TIMER3_BASE 0x400C4000
<>	144:ef7eb2e8f9f7	1432
<>	144:ef7eb2e8f9f7	1433	typedef struct { /* TIMERn Structure */
<>	144:ef7eb2e8f9f7	1434	__IO uint32_t IR; /* Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
<>	144:ef7eb2e8f9f7	1435	__IO uint32_t TCR; /* Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
<>	144:ef7eb2e8f9f7	1436	__IO uint32_t TC; /* Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
<>	144:ef7eb2e8f9f7	1437	__IO uint32_t PR; /* Prescale Register. The Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
<>	144:ef7eb2e8f9f7	1438	__IO uint32_t PC; /* Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
<>	144:ef7eb2e8f9f7	1439	__IO uint32_t MCR; /* Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
<>	144:ef7eb2e8f9f7	1440	__IO uint32_t MR[4]; /* Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
<>	144:ef7eb2e8f9f7	1441	__IO uint32_t CCR; /* Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
<>	144:ef7eb2e8f9f7	1442	__IO uint32_t CR[4]; /* Capture Register. CR is loaded with the value of TC when there is an event on the CAPn.0 input. */
<>	144:ef7eb2e8f9f7	1443	__IO uint32_t EMR; /* External Match Register. The EMR controls the external match pins MATn.0-3 (MAT0.0-3 and MAT1.0-3 respectively). */
<>	144:ef7eb2e8f9f7	1444	__I uint32_t RESERVED0[12];
<>	144:ef7eb2e8f9f7	1445	__IO uint32_t CTCR; /* Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
<>	144:ef7eb2e8f9f7	1446	} LPC_TIMER_T;
<>	144:ef7eb2e8f9f7	1447
<>	144:ef7eb2e8f9f7	1448	/* ---------------------------------------------------------------------------
<>	144:ef7eb2e8f9f7	1449	* System Control Unit register block
<>	144:ef7eb2e8f9f7	1450	*/
<>	144:ef7eb2e8f9f7	1451	#define LPC_SCU_BASE 0x40086000
<>	144:ef7eb2e8f9f7	1452
<>	144:ef7eb2e8f9f7	1453	typedef struct {
<>	144:ef7eb2e8f9f7	1454	__IO uint32_t SFSP[16][32];
<>	144:ef7eb2e8f9f7	1455	__I uint32_t RESERVED0[256];
<>	144:ef7eb2e8f9f7	1456	__IO uint32_t SFSCLK[4]; /* Pin configuration register for pins CLK0-3 */
<>	144:ef7eb2e8f9f7	1457	__I uint32_t RESERVED16[28];
<>	144:ef7eb2e8f9f7	1458	__IO uint32_t SFSUSB; /* Pin configuration register for USB */
<>	144:ef7eb2e8f9f7	1459	__IO uint32_t SFSI2C0; /* Pin configuration register for I2C0-bus pins */
<>	144:ef7eb2e8f9f7	1460	__IO uint32_t ENAIO[3]; /* Analog function select registers */
<>	144:ef7eb2e8f9f7	1461	__I uint32_t RESERVED17[27];
<>	144:ef7eb2e8f9f7	1462	__IO uint32_t EMCDELAYCLK; /* EMC clock delay register */
<>	144:ef7eb2e8f9f7	1463	__I uint32_t RESERVED18[63];
<>	144:ef7eb2e8f9f7	1464	__IO uint32_t PINTSEL0; /* Pin interrupt select register for pin interrupts 0 to 3. */
<>	144:ef7eb2e8f9f7	1465	__IO uint32_t PINTSEL1; /* Pin interrupt select register for pin interrupts 4 to 7. */
<>	144:ef7eb2e8f9f7	1466	} LPC_SCU_T;
<>	144:ef7eb2e8f9f7	1467
<>	144:ef7eb2e8f9f7	1468	/*
<>	144:ef7eb2e8f9f7	1469	* SCU function and mode selection definitions
<>	144:ef7eb2e8f9f7	1470	* See the User Manual for specific modes and functions supoprted by the
<>	144:ef7eb2e8f9f7	1471	* various LPC18xx/43xx devices. Functionality can vary per device.
<>	144:ef7eb2e8f9f7	1472	*/
<>	144:ef7eb2e8f9f7	1473	#define SCU_MODE_PULLUP (0x0 << 3) /* Enable pull-up resistor at pad */
<>	144:ef7eb2e8f9f7	1474	#define SCU_MODE_REPEATER (0x1 << 3) /* Enable pull-down and pull-up resistor at resistor at pad (repeater mode) */
<>	144:ef7eb2e8f9f7	1475	#define SCU_MODE_INACT (0x2 << 3) /* Disable pull-down and pull-up resistor at resistor at pad */
<>	144:ef7eb2e8f9f7	1476	#define SCU_MODE_PULLDOWN (0x3 << 3) /* Enable pull-down resistor at pad */
<>	144:ef7eb2e8f9f7	1477	#define SCU_MODE_HIGHSPEEDSLEW_EN (0x1 << 5) /* Enable high-speed slew */
<>	144:ef7eb2e8f9f7	1478	#define SCU_MODE_INBUFF_EN (0x1 << 6) /* Enable Input buffer */
<>	144:ef7eb2e8f9f7	1479	#define SCU_MODE_ZIF_DIS (0x1 << 7) /* Disable input glitch filter */
<>	144:ef7eb2e8f9f7	1480	#define SCU_MODE_4MA_DRIVESTR (0x0 << 8) /* Normal drive: 4mA drive strength */
<>	144:ef7eb2e8f9f7	1481	#define SCU_MODE_8MA_DRIVESTR (0x1 << 8) /* Medium drive: 8mA drive strength */
<>	144:ef7eb2e8f9f7	1482	#define SCU_MODE_14MA_DRIVESTR (0x2 << 8) /* High drive: 14mA drive strength */
<>	144:ef7eb2e8f9f7	1483	#define SCU_MODE_20MA_DRIVESTR (0x3 << 8) /* Ultra high- drive: 20mA drive strength */
<>	144:ef7eb2e8f9f7	1484
<>	144:ef7eb2e8f9f7	1485	#define SCU_MODE_FUNC0 0x0 /* Selects pin function 0 */
<>	144:ef7eb2e8f9f7	1486	#define SCU_MODE_FUNC1 0x1 /* Selects pin function 1 */
<>	144:ef7eb2e8f9f7	1487	#define SCU_MODE_FUNC2 0x2 /* Selects pin function 2 */
<>	144:ef7eb2e8f9f7	1488	#define SCU_MODE_FUNC3 0x3 /* Selects pin function 3 */
<>	144:ef7eb2e8f9f7	1489	#define SCU_MODE_FUNC4 0x4 /* Selects pin function 4 */
<>	144:ef7eb2e8f9f7	1490	#define SCU_MODE_FUNC5 0x5 /* Selects pin function 5 */
<>	144:ef7eb2e8f9f7	1491	#define SCU_MODE_FUNC6 0x6 /* Selects pin function 6 */
<>	144:ef7eb2e8f9f7	1492	#define SCU_MODE_FUNC7 0x7 /* Selects pin function 7 */
<>	144:ef7eb2e8f9f7	1493
<>	144:ef7eb2e8f9f7	1494	/* Common SCU configurations */
<>	144:ef7eb2e8f9f7	1495	#define SCU_PINIO_FAST (SCU_MODE_INACT \| SCU_MODE_HIGHSPEEDSLEW_EN \| SCU_MODE_INBUFF_EN \| SCU_MODE_ZIF_DIS)
<>	144:ef7eb2e8f9f7	1496	#define SCU_PINIO_PULLUP (SCU_MODE_INBUFF_EN)
<>	144:ef7eb2e8f9f7	1497	#define SCU_PINIO_PULLDOWN (SCU_MODE_PULLDOWN \| SCU_MODE_INACT \| SCU_MODE_INBUFF_EN)
<>	144:ef7eb2e8f9f7	1498	#define SCU_PINIO_PULLNONE (SCU_MODE_INACT \| SCU_MODE_INBUFF_EN)
<>	144:ef7eb2e8f9f7	1499
<>	144:ef7eb2e8f9f7	1500	/* Calculate SCU offset and register address from group and pin number */
<>	144:ef7eb2e8f9f7	1501	#define SCU_OFF(group, num) ((group << 7) + (num << 2))
<>	144:ef7eb2e8f9f7	1502	#define SCU_REG(group, num) ((__IO uint32_t *)(LPC_SCU_BASE + SCU_OFF(group, num)))
<>	144:ef7eb2e8f9f7	1503
<>	144:ef7eb2e8f9f7	1504	/**
<>	144:ef7eb2e8f9f7	1505	* SCU function and mode selection definitions (old)
<>	144:ef7eb2e8f9f7	1506	* For backwards compatibility.
<>	144:ef7eb2e8f9f7	1507	*/
<>	144:ef7eb2e8f9f7	1508	#define MD_PUP (0x0 << 3) /* Enable pull-up resistor at pad */
<>	144:ef7eb2e8f9f7	1509	#define MD_BUK (0x1 << 3) /* Enable pull-down and pull-up resistor at resistor at pad (repeater mode) */
<>	144:ef7eb2e8f9f7	1510	#define MD_PLN (0x2 << 3) /* Disable pull-down and pull-up resistor at resistor at pad */
<>	144:ef7eb2e8f9f7	1511	#define MD_PDN (0x3 << 3) /* Enable pull-down resistor at pad */
<>	144:ef7eb2e8f9f7	1512	#define MD_EHS (0x1 << 5) /* Enable fast slew rate */
<>	144:ef7eb2e8f9f7	1513	#define MD_EZI (0x1 << 6) /* Input buffer enable */
<>	144:ef7eb2e8f9f7	1514	#define MD_ZI (0x1 << 7) /* Disable input glitch filter */
<>	144:ef7eb2e8f9f7	1515	#define MD_EHD0 (0x1 << 8) /* EHD driver strength low bit */
<>	144:ef7eb2e8f9f7	1516	#define MD_EHD1 (0x1 << 8) /* EHD driver strength high bit */
<>	144:ef7eb2e8f9f7	1517	#define MD_PLN_FAST (MD_PLN \| MD_EZI \| MD_ZI \| MD_EHS)
<>	144:ef7eb2e8f9f7	1518	#define I2C0_STANDARD_FAST_MODE (1 << 3 \| 1 << 11) /* Pin configuration for STANDARD/FAST mode I2C */
<>	144:ef7eb2e8f9f7	1519	#define I2C0_FAST_MODE_PLUS (2 << 1 \| 1 << 3 \| 1 << 7 \| 1 << 10 \| 1 << 11) /* Pin configuration for Fast-mode Plus I2C */
<>	144:ef7eb2e8f9f7	1520
<>	144:ef7eb2e8f9f7	1521	#define FUNC0 0x0 /* Pin function 0 */
<>	144:ef7eb2e8f9f7	1522	#define FUNC1 0x1 /* Pin function 1 */
<>	144:ef7eb2e8f9f7	1523	#define FUNC2 0x2 /* Pin function 2 */
<>	144:ef7eb2e8f9f7	1524	#define FUNC3 0x3 /* Pin function 3 */
<>	144:ef7eb2e8f9f7	1525	#define FUNC4 0x4 /* Pin function 4 */
<>	144:ef7eb2e8f9f7	1526	#define FUNC5 0x5 /* Pin function 5 */
<>	144:ef7eb2e8f9f7	1527	#define FUNC6 0x6 /* Pin function 6 */
<>	144:ef7eb2e8f9f7	1528	#define FUNC7 0x7 /* Pin function 7 */
<>	144:ef7eb2e8f9f7	1529
<>	144:ef7eb2e8f9f7	1530	#define PORT_OFFSET 0x80 /* Port offset definition */
<>	144:ef7eb2e8f9f7	1531	#define PIN_OFFSET 0x04 /* Pin offset definition */
<>	144:ef7eb2e8f9f7	1532
<>	144:ef7eb2e8f9f7	1533	/* Returns the SFSP register address in the SCU for a pin and port,
<>	144:ef7eb2e8f9f7	1534	recommend using ((volatile int ) &LPC_SCU->SFSP[po][pi];) */
<>	144:ef7eb2e8f9f7	1535	#define LPC_SCU_PIN(LPC_SCU_BASE, po, pi) \
<>	144:ef7eb2e8f9f7	1536	((volatile int ) ((LPC_SCU_BASE) + ((po) * 0x80) + ((pi) * 0x4))
<>	144:ef7eb2e8f9f7	1537
<>	144:ef7eb2e8f9f7	1538	/* Returns the address in the SCU for a SFSCLK clock register,
<>	144:ef7eb2e8f9f7	1539	recommend using ((volatile int ) &LPC_SCU->SFSCLK[c];) */
<>	144:ef7eb2e8f9f7	1540	#define LPC_SCU_CLK(LPC_SCU_BASE, c) \
<>	144:ef7eb2e8f9f7	1541	((volatile int ) ((LPC_SCU_BASE) +0xC00 + ((c) * 0x4)))
<>	144:ef7eb2e8f9f7	1542
<>	144:ef7eb2e8f9f7	1543	/* ---------------------------------------------------------------------------
<>	144:ef7eb2e8f9f7	1544	* GPIO pin interrupt register block structure
<>	144:ef7eb2e8f9f7	1545	*/
<>	144:ef7eb2e8f9f7	1546	#define LPC_GPIO_PIN_INT_BASE 0x40087000
<>	144:ef7eb2e8f9f7	1547
<>	144:ef7eb2e8f9f7	1548	typedef struct { /* GPIO_PIN_INT Structure */
<>	144:ef7eb2e8f9f7	1549	__IO uint32_t ISEL; /* Pin Interrupt Mode register */
<>	144:ef7eb2e8f9f7	1550	__IO uint32_t IENR; /* Pin Interrupt Enable (Rising) register */
<>	144:ef7eb2e8f9f7	1551	__O uint32_t SIENR; /* Set Pin Interrupt Enable (Rising) register */
<>	144:ef7eb2e8f9f7	1552	__O uint32_t CIENR; /* Clear Pin Interrupt Enable (Rising) register */
<>	144:ef7eb2e8f9f7	1553	__IO uint32_t IENF; /* Pin Interrupt Enable Falling Edge / Active Level register */
<>	144:ef7eb2e8f9f7	1554	__O uint32_t SIENF; /* Set Pin Interrupt Enable Falling Edge / Active Level register */
<>	144:ef7eb2e8f9f7	1555	__O uint32_t CIENF; /* Clear Pin Interrupt Enable Falling Edge / Active Level address */
<>	144:ef7eb2e8f9f7	1556	__IO uint32_t RISE; /* Pin Interrupt Rising Edge register */
<>	144:ef7eb2e8f9f7	1557	__IO uint32_t FALL; /* Pin Interrupt Falling Edge register */
<>	144:ef7eb2e8f9f7	1558	__IO uint32_t IST; /* Pin Interrupt Status register */
<>	144:ef7eb2e8f9f7	1559	} LPC_GPIOPININT_T;
<>	144:ef7eb2e8f9f7	1560
<>	144:ef7eb2e8f9f7	1561	typedef enum LPC_GPIOPININT_MODE {
<>	144:ef7eb2e8f9f7	1562	GPIOPININT_RISING_EDGE = 0x01,
<>	144:ef7eb2e8f9f7	1563	GPIOPININT_FALLING_EDGE = 0x02,
<>	144:ef7eb2e8f9f7	1564	GPIOPININT_ACTIVE_HIGH_LEVEL = 0x04,
<>	144:ef7eb2e8f9f7	1565	GPIOPININT_ACTIVE_LOW_LEVEL = 0x08
<>	144:ef7eb2e8f9f7	1566	} LPC_GPIOPININT_MODE_T;
<>	144:ef7eb2e8f9f7	1567
<>	144:ef7eb2e8f9f7	1568	/* ---------------------------------------------------------------------------
<>	144:ef7eb2e8f9f7	1569	* GPIO grouped interrupt register block structure
<>	144:ef7eb2e8f9f7	1570	*/
<>	144:ef7eb2e8f9f7	1571	#define LPC_GPIO_GROUP_INT0_BASE 0x40088000
<>	144:ef7eb2e8f9f7	1572	#define LPC_GPIO_GROUP_INT1_BASE 0x40089000
<>	144:ef7eb2e8f9f7	1573
<>	144:ef7eb2e8f9f7	1574	typedef struct { /* GPIO_GROUP_INTn Structure */
<>	144:ef7eb2e8f9f7	1575	__IO uint32_t CTRL; /* GPIO grouped interrupt control register */
<>	144:ef7eb2e8f9f7	1576	__I uint32_t RESERVED0[7];
<>	144:ef7eb2e8f9f7	1577	__IO uint32_t PORT_POL[8]; /* GPIO grouped interrupt port polarity register */
<>	144:ef7eb2e8f9f7	1578	__IO uint32_t PORT_ENA[8]; /* GPIO grouped interrupt port m enable register */
<>	144:ef7eb2e8f9f7	1579	} LPC_GPIOGROUPINT_T;
<>	144:ef7eb2e8f9f7	1580
<>	144:ef7eb2e8f9f7	1581	/* ---------------------------------------------------------------------------
<>	144:ef7eb2e8f9f7	1582	* Motor Control PWM register block structure
<>	144:ef7eb2e8f9f7	1583	*/
<>	144:ef7eb2e8f9f7	1584	#define LPC_MCPWM_BASE 0x400A0000
<>	144:ef7eb2e8f9f7	1585
<>	144:ef7eb2e8f9f7	1586	typedef struct { /* MCPWM Structure */
<>	144:ef7eb2e8f9f7	1587	__I uint32_t CON; /* PWM Control read address */
<>	144:ef7eb2e8f9f7	1588	__O uint32_t CON_SET; /* PWM Control set address */
<>	144:ef7eb2e8f9f7	1589	__O uint32_t CON_CLR; /* PWM Control clear address */
<>	144:ef7eb2e8f9f7	1590	__I uint32_t CAPCON; /* Capture Control read address */
<>	144:ef7eb2e8f9f7	1591	__O uint32_t CAPCON_SET; /* Capture Control set address */
<>	144:ef7eb2e8f9f7	1592	__O uint32_t CAPCON_CLR; /* Event Control clear address */
<>	144:ef7eb2e8f9f7	1593	__IO uint32_t TC[3]; /* Timer Counter register */
<>	144:ef7eb2e8f9f7	1594	__IO uint32_t LIM[3]; /* Limit register */
<>	144:ef7eb2e8f9f7	1595	__IO uint32_t MAT[3]; /* Match register */
<>	144:ef7eb2e8f9f7	1596	__IO uint32_t DT; /* Dead time register */
<>	144:ef7eb2e8f9f7	1597	__IO uint32_t CCP; /* Communication Pattern register */
<>	144:ef7eb2e8f9f7	1598	__I uint32_t CAP[3]; /* Capture register */
<>	144:ef7eb2e8f9f7	1599	__I uint32_t INTEN; /* Interrupt Enable read address */
<>	144:ef7eb2e8f9f7	1600	__O uint32_t INTEN_SET; /* Interrupt Enable set address */
<>	144:ef7eb2e8f9f7	1601	__O uint32_t INTEN_CLR; /* Interrupt Enable clear address */
<>	144:ef7eb2e8f9f7	1602	__I uint32_t CNTCON; /* Count Control read address */
<>	144:ef7eb2e8f9f7	1603	__O uint32_t CNTCON_SET; /* Count Control set address */
<>	144:ef7eb2e8f9f7	1604	__O uint32_t CNTCON_CLR; /* Count Control clear address */
<>	144:ef7eb2e8f9f7	1605	__I uint32_t INTF; /* Interrupt flags read address */
<>	144:ef7eb2e8f9f7	1606	__O uint32_t INTF_SET; /* Interrupt flags set address */
<>	144:ef7eb2e8f9f7	1607	__O uint32_t INTF_CLR; /* Interrupt flags clear address */
<>	144:ef7eb2e8f9f7	1608	__O uint32_t CAP_CLR; /* Capture clear address */
<>	144:ef7eb2e8f9f7	1609	} LPC_MCPWM_T;
<>	144:ef7eb2e8f9f7	1610
<>	144:ef7eb2e8f9f7	1611	/* ---------------------------------------------------------------------------
<>	144:ef7eb2e8f9f7	1612	* I2C register block structure
<>	144:ef7eb2e8f9f7	1613	*/
<>	144:ef7eb2e8f9f7	1614	#define LPC_I2C0_BASE 0x400A1000
<>	144:ef7eb2e8f9f7	1615	#define LPC_I2C1_BASE 0x400E0000
<>	144:ef7eb2e8f9f7	1616
<>	144:ef7eb2e8f9f7	1617	typedef struct { /* I2C0 Structure */
<>	144:ef7eb2e8f9f7	1618	__IO uint32_t CONSET; /* I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register. */
<>	144:ef7eb2e8f9f7	1619	__I uint32_t STAT; /* I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed. */
<>	144:ef7eb2e8f9f7	1620	__IO uint32_t DAT; /* I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register. */
<>	144:ef7eb2e8f9f7	1621	__IO uint32_t ADR0; /* I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
<>	144:ef7eb2e8f9f7	1622	__IO uint32_t SCLH; /* SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock. */
<>	144:ef7eb2e8f9f7	1623	__IO uint32_t SCLL; /* SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode. */
<>	144:ef7eb2e8f9f7	1624	__O uint32_t CONCLR; /* I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register. */
<>	144:ef7eb2e8f9f7	1625	__IO uint32_t MMCTRL; /* Monitor mode control register. */
<>	144:ef7eb2e8f9f7	1626	__IO uint32_t ADR1; /* I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
<>	144:ef7eb2e8f9f7	1627	__IO uint32_t ADR2; /* I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
<>	144:ef7eb2e8f9f7	1628	__IO uint32_t ADR3; /* I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
<>	144:ef7eb2e8f9f7	1629	__I uint32_t DATA_BUFFER; /* Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus. */
<>	144:ef7eb2e8f9f7	1630	__IO uint32_t MASK[4]; /* I2C Slave address mask register */
<>	144:ef7eb2e8f9f7	1631	} LPC_I2C_T;
<>	144:ef7eb2e8f9f7	1632
<>	144:ef7eb2e8f9f7	1633	/* ---------------------------------------------------------------------------
<>	144:ef7eb2e8f9f7	1634	* I2S register block structure
<>	144:ef7eb2e8f9f7	1635	*/
<>	144:ef7eb2e8f9f7	1636	#define LPC_I2S0_BASE 0x400A2000
<>	144:ef7eb2e8f9f7	1637	#define LPC_I2S1_BASE 0x400A3000
<>	144:ef7eb2e8f9f7	1638
<>	144:ef7eb2e8f9f7	1639	typedef struct { /* I2S Structure */
<>	144:ef7eb2e8f9f7	1640	__IO uint32_t DAO; /* I2S Digital Audio Output Register. Contains control bits for the I2S transmit channel */
<>	144:ef7eb2e8f9f7	1641	__IO uint32_t DAI; /* I2S Digital Audio Input Register. Contains control bits for the I2S receive channel */
<>	144:ef7eb2e8f9f7	1642	__O uint32_t TXFIFO; /* I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter FIFO */
<>	144:ef7eb2e8f9f7	1643	__I uint32_t RXFIFO; /* I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO */
<>	144:ef7eb2e8f9f7	1644	__I uint32_t STATE; /* I2S Status Feedback Register. Contains status information about the I2S interface */
<>	144:ef7eb2e8f9f7	1645	__IO uint32_t DMA1; /* I2S DMA Configuration Register 1. Contains control information for DMA request 1 */
<>	144:ef7eb2e8f9f7	1646	__IO uint32_t DMA2; /* I2S DMA Configuration Register 2. Contains control information for DMA request 2 */
<>	144:ef7eb2e8f9f7	1647	__IO uint32_t IRQ; /* I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated */
<>	144:ef7eb2e8f9f7	1648	__IO uint32_t TXRATE; /* I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK */
<>	144:ef7eb2e8f9f7	1649	__IO uint32_t RXRATE; /* I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK */
<>	144:ef7eb2e8f9f7	1650	__IO uint32_t TXBITRATE; /* I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock */
<>	144:ef7eb2e8f9f7	1651	__IO uint32_t RXBITRATE; /* I2S Receive bit rate divider. This register determines the I2S receive bit rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock */
<>	144:ef7eb2e8f9f7	1652	__IO uint32_t TXMODE; /* I2S Transmit mode control */
<>	144:ef7eb2e8f9f7	1653	__IO uint32_t RXMODE; /* I2S Receive mode control */
<>	144:ef7eb2e8f9f7	1654	} LPC_I2S_T;
<>	144:ef7eb2e8f9f7	1655
<>	144:ef7eb2e8f9f7	1656	/* ---------------------------------------------------------------------------
<>	144:ef7eb2e8f9f7	1657	* CCAN Controller Area Network register block structure
<>	144:ef7eb2e8f9f7	1658	*/
<>	144:ef7eb2e8f9f7	1659	#define LPC_C_CAN1_BASE 0x400A4000
<>	144:ef7eb2e8f9f7	1660	#define LPC_C_CAN0_BASE 0x400E2000
<>	144:ef7eb2e8f9f7	1661
<>	144:ef7eb2e8f9f7	1662	typedef struct { /* C_CAN message interface Structure */
<>	144:ef7eb2e8f9f7	1663	__IO uint32_t IF_CMDREQ; /* Message interface command request */
<>	144:ef7eb2e8f9f7	1664	union {
<>	144:ef7eb2e8f9f7	1665	__IO uint32_t IF_CMDMSK_R; /* Message interface command mask (read direction) */
<>	144:ef7eb2e8f9f7	1666	__IO uint32_t IF_CMDMSK_W; /* Message interface command mask (write direction) */
<>	144:ef7eb2e8f9f7	1667	};
<>	144:ef7eb2e8f9f7	1668
<>	144:ef7eb2e8f9f7	1669	__IO uint32_t IF_MSK1; /* Message interface mask 1 */
<>	144:ef7eb2e8f9f7	1670	__IO uint32_t IF_MSK2; /* Message interface mask 2 */
<>	144:ef7eb2e8f9f7	1671	__IO uint32_t IF_ARB1; /* Message interface arbitration 1 */
<>	144:ef7eb2e8f9f7	1672	__IO uint32_t IF_ARB2; /* Message interface arbitration 2 */
<>	144:ef7eb2e8f9f7	1673	__IO uint32_t IF_MCTRL; /* Message interface message control */
<>	144:ef7eb2e8f9f7	1674	__IO uint32_t IF_DA1; /* Message interface data A1 */
<>	144:ef7eb2e8f9f7	1675	__IO uint32_t IF_DA2; /* Message interface data A2 */
<>	144:ef7eb2e8f9f7	1676	__IO uint32_t IF_DB1; /* Message interface data B1 */
<>	144:ef7eb2e8f9f7	1677	__IO uint32_t IF_DB2; /* Message interface data B2 */
<>	144:ef7eb2e8f9f7	1678	__I uint32_t RESERVED[13];
<>	144:ef7eb2e8f9f7	1679	} LPC_CCAN_IF_T;
<>	144:ef7eb2e8f9f7	1680
<>	144:ef7eb2e8f9f7	1681	typedef struct { /* C_CAN Structure */
<>	144:ef7eb2e8f9f7	1682	__IO uint32_t CNTL; /* CAN control */
<>	144:ef7eb2e8f9f7	1683	__IO uint32_t STAT; /* Status register */
<>	144:ef7eb2e8f9f7	1684	__I uint32_t EC; /* Error counter */
<>	144:ef7eb2e8f9f7	1685	__IO uint32_t BT; /* Bit timing register */
<>	144:ef7eb2e8f9f7	1686	__I uint32_t INT; /* Interrupt register */
<>	144:ef7eb2e8f9f7	1687	__IO uint32_t TEST; /* Test register */
<>	144:ef7eb2e8f9f7	1688	__IO uint32_t BRPE; /* Baud rate prescaler extension register */
<>	144:ef7eb2e8f9f7	1689	__I uint32_t RESERVED0;
<>	144:ef7eb2e8f9f7	1690	LPC_CCAN_IF_T IF[2];
<>	144:ef7eb2e8f9f7	1691	__I uint32_t RESERVED2[8];
<>	144:ef7eb2e8f9f7	1692	__I uint32_t TXREQ1; /* Transmission request 1 */
<>	144:ef7eb2e8f9f7	1693	__I uint32_t TXREQ2; /* Transmission request 2 */
<>	144:ef7eb2e8f9f7	1694	__I uint32_t RESERVED3[6];
<>	144:ef7eb2e8f9f7	1695	__I uint32_t ND1; /* New data 1 */
<>	144:ef7eb2e8f9f7	1696	__I uint32_t ND2; /* New data 2 */
<>	144:ef7eb2e8f9f7	1697	__I uint32_t RESERVED4[6];
<>	144:ef7eb2e8f9f7	1698	__I uint32_t IR1; /* Interrupt pending 1 */
<>	144:ef7eb2e8f9f7	1699	__I uint32_t IR2; /* Interrupt pending 2 */
<>	144:ef7eb2e8f9f7	1700	__I uint32_t RESERVED5[6];
<>	144:ef7eb2e8f9f7	1701	__I uint32_t MSGV1; /* Message valid 1 */
<>	144:ef7eb2e8f9f7	1702	__I uint32_t MSGV2; /* Message valid 2 */
<>	144:ef7eb2e8f9f7	1703	__I uint32_t RESERVED6[6];
<>	144:ef7eb2e8f9f7	1704	__IO uint32_t CLKDIV; /* CAN clock divider register */
<>	144:ef7eb2e8f9f7	1705	} LPC_CCAN_T;
<>	144:ef7eb2e8f9f7	1706
<>	144:ef7eb2e8f9f7	1707	/* ---------------------------------------------------------------------------
<>	144:ef7eb2e8f9f7	1708	* Repetitive Interrupt Timer register block structure
<>	144:ef7eb2e8f9f7	1709	*/
<>	144:ef7eb2e8f9f7	1710	#define LPC_RITIMER_BASE 0x400C0000
<>	144:ef7eb2e8f9f7	1711
<>	144:ef7eb2e8f9f7	1712	typedef struct { /* RITIMER Structure */
<>	144:ef7eb2e8f9f7	1713	__IO uint32_t COMPVAL; /* Compare register */
<>	144:ef7eb2e8f9f7	1714	__IO uint32_t MASK; /* Mask register. This register holds the 32-bit mask value. A 1 written to any bit will force a compare on the corresponding bit of the counter and compare register. */
<>	144:ef7eb2e8f9f7	1715	__IO uint32_t CTRL; /* Control register. */
<>	144:ef7eb2e8f9f7	1716	__IO uint32_t COUNTER; /* 32-bit counter */
<>	144:ef7eb2e8f9f7	1717	} LPC_RITIMER_T;
<>	144:ef7eb2e8f9f7	1718
<>	144:ef7eb2e8f9f7	1719	/* ---------------------------------------------------------------------------
<>	144:ef7eb2e8f9f7	1720	* Quadrature Encoder Interface register block structure
<>	144:ef7eb2e8f9f7	1721	*/
<>	144:ef7eb2e8f9f7	1722	#define LPC_QEI_BASE 0x400C6000
<>	144:ef7eb2e8f9f7	1723
<>	144:ef7eb2e8f9f7	1724	typedef struct { /* QEI Structure */
<>	144:ef7eb2e8f9f7	1725	__O uint32_t CON; /* Control register */
<>	144:ef7eb2e8f9f7	1726	__I uint32_t STAT; /* Encoder status register */
<>	144:ef7eb2e8f9f7	1727	__IO uint32_t CONF; /* Configuration register */
<>	144:ef7eb2e8f9f7	1728	__I uint32_t POS; /* Position register */
<>	144:ef7eb2e8f9f7	1729	__IO uint32_t MAXPOS; /* Maximum position register */
<>	144:ef7eb2e8f9f7	1730	__IO uint32_t CMPOS0; /* position compare register 0 */
<>	144:ef7eb2e8f9f7	1731	__IO uint32_t CMPOS1; /* position compare register 1 */
<>	144:ef7eb2e8f9f7	1732	__IO uint32_t CMPOS2; /* position compare register 2 */
<>	144:ef7eb2e8f9f7	1733	__I uint32_t INXCNT; /* Index count register */
<>	144:ef7eb2e8f9f7	1734	__IO uint32_t INXCMP0; /* Index compare register 0 */
<>	144:ef7eb2e8f9f7	1735	__IO uint32_t LOAD; /* Velocity timer reload register */
<>	144:ef7eb2e8f9f7	1736	__I uint32_t TIME; /* Velocity timer register */
<>	144:ef7eb2e8f9f7	1737	__I uint32_t VEL; /* Velocity counter register */
<>	144:ef7eb2e8f9f7	1738	__I uint32_t CAP; /* Velocity capture register */
<>	144:ef7eb2e8f9f7	1739	__IO uint32_t VELCOMP; /* Velocity compare register */
<>	144:ef7eb2e8f9f7	1740	__IO uint32_t FILTERPHA; /* Digital filter register on input phase A (QEI_A) */
<>	144:ef7eb2e8f9f7	1741	__IO uint32_t FILTERPHB; /* Digital filter register on input phase B (QEI_B) */
<>	144:ef7eb2e8f9f7	1742	__IO uint32_t FILTERINX; /* Digital filter register on input index (QEI_IDX) */
<>	144:ef7eb2e8f9f7	1743	__IO uint32_t WINDOW; /* Index acceptance window register */
<>	144:ef7eb2e8f9f7	1744	__IO uint32_t INXCMP1; /* Index compare register 1 */
<>	144:ef7eb2e8f9f7	1745	__IO uint32_t INXCMP2; /* Index compare register 2 */
<>	144:ef7eb2e8f9f7	1746	__I uint32_t RESERVED0[993];
<>	144:ef7eb2e8f9f7	1747	__O uint32_t IEC; /* Interrupt enable clear register */
<>	144:ef7eb2e8f9f7	1748	__O uint32_t IES; /* Interrupt enable set register */
<>	144:ef7eb2e8f9f7	1749	__I uint32_t INTSTAT; /* Interrupt status register */
<>	144:ef7eb2e8f9f7	1750	__I uint32_t IE; /* Interrupt enable register */
<>	144:ef7eb2e8f9f7	1751	__O uint32_t CLR; /* Interrupt status clear register */
<>	144:ef7eb2e8f9f7	1752	__O uint32_t SET; /* Interrupt status set register */
<>	144:ef7eb2e8f9f7	1753	} LPC_QEI_T;
<>	144:ef7eb2e8f9f7	1754
<>	144:ef7eb2e8f9f7	1755	/* ---------------------------------------------------------------------------
<>	144:ef7eb2e8f9f7	1756	* Global Input Multiplexer Array (GIMA) register block structure
<>	144:ef7eb2e8f9f7	1757	*/
<>	144:ef7eb2e8f9f7	1758	#define LPC_GIMA_BASE 0x400C7000
<>	144:ef7eb2e8f9f7	1759
<>	144:ef7eb2e8f9f7	1760	typedef struct { /* GIMA Structure */
<>	144:ef7eb2e8f9f7	1761	__IO uint32_t CAP0_IN[4][4]; /* Timer x CAP0_y capture input multiplexer (GIMA output ((x4)+y)) /
<>	144:ef7eb2e8f9f7	1762	__IO uint32_t CTIN_IN[8]; /* SCT CTIN_x capture input multiplexer (GIMA output (16+x)) */
<>	144:ef7eb2e8f9f7	1763	__IO uint32_t VADC_TRIGGER_IN; /* VADC trigger input multiplexer (GIMA output 24) */
<>	144:ef7eb2e8f9f7	1764	__IO uint32_t EVENTROUTER_13_IN; /* Event router input 13 multiplexer (GIMA output 25) */
<>	144:ef7eb2e8f9f7	1765	__IO uint32_t EVENTROUTER_14_IN; /* Event router input 14 multiplexer (GIMA output 26) */
<>	144:ef7eb2e8f9f7	1766	__IO uint32_t EVENTROUTER_16_IN; /* Event router input 16 multiplexer (GIMA output 27) */
<>	144:ef7eb2e8f9f7	1767	__IO uint32_t ADCSTART0_IN; /* ADC start0 input multiplexer (GIMA output 28) */
<>	144:ef7eb2e8f9f7	1768	__IO uint32_t ADCSTART1_IN; /* ADC start1 input multiplexer (GIMA output 29) */
<>	144:ef7eb2e8f9f7	1769	} LPC_GIMA_T;
<>	144:ef7eb2e8f9f7	1770
<>	144:ef7eb2e8f9f7	1771	/* ---------------------------------------------------------------------------
<>	144:ef7eb2e8f9f7	1772	* DAC register block structure
<>	144:ef7eb2e8f9f7	1773	*/
<>	144:ef7eb2e8f9f7	1774	#define LPC_DAC_BASE 0x400E1000
<>	144:ef7eb2e8f9f7	1775
<>	144:ef7eb2e8f9f7	1776	typedef struct { /* DAC Structure */
<>	144:ef7eb2e8f9f7	1777	__IO uint32_t CR; /* DAC register. Holds the conversion data. */
<>	144:ef7eb2e8f9f7	1778	__IO uint32_t CTRL; /* DAC control register. */
<>	144:ef7eb2e8f9f7	1779	__IO uint32_t CNTVAL; /* DAC counter value register. */
<>	144:ef7eb2e8f9f7	1780	} LPC_DAC_T;
<>	144:ef7eb2e8f9f7	1781
<>	144:ef7eb2e8f9f7	1782	/* After the selected settling time after this field is written with a
<>	144:ef7eb2e8f9f7	1783	* new VALUE, the voltage on the AOUT pin (with respect to VSSA)
<>	144:ef7eb2e8f9f7	1784	* is VALUE/1024 ? VREF
<>	144:ef7eb2e8f9f7	1785	*/
<>	144:ef7eb2e8f9f7	1786	#define DAC_RANGE 0x3FF
<>	144:ef7eb2e8f9f7	1787	#define DAC_SET(n) ((uint32_t) ((n & DAC_RANGE) << 6))
<>	144:ef7eb2e8f9f7	1788	#define DAC_GET(n) ((uint32_t) ((n >> 6) & DAC_RANGE))
<>	144:ef7eb2e8f9f7	1789	#define DAC_VALUE(n) DAC_SET(n)
<>	144:ef7eb2e8f9f7	1790	/* If this bit = 0: The settling time of the DAC is 1 microsecond max,
<>	144:ef7eb2e8f9f7	1791	* and the maximum current is 700 microAmpere
<>	144:ef7eb2e8f9f7	1792	* If this bit = 1: The settling time of the DAC is 2.5 microsecond
<>	144:ef7eb2e8f9f7	1793	* and the maximum current is 350 microAmpere
<>	144:ef7eb2e8f9f7	1794	*/
<>	144:ef7eb2e8f9f7	1795	#define DAC_BIAS_EN ((uint32_t) (1 << 16))
<>	144:ef7eb2e8f9f7	1796	/* Value to reload interrupt DMA counter */
<>	144:ef7eb2e8f9f7	1797	#define DAC_CCNT_VALUE(n) ((uint32_t) (n & 0xffff))
<>	144:ef7eb2e8f9f7	1798
<>	144:ef7eb2e8f9f7	1799	#define DAC_DBLBUF_ENA ((uint32_t) (1 << 1))
<>	144:ef7eb2e8f9f7	1800	#define DAC_CNT_ENA ((uint32_t) (1 << 2))
<>	144:ef7eb2e8f9f7	1801	#define DAC_DMA_ENA ((uint32_t) (1 << 3))
<>	144:ef7eb2e8f9f7	1802	#define DAC_DACCTRL_MASK ((uint32_t) (0x0F))
<>	144:ef7eb2e8f9f7	1803
<>	144:ef7eb2e8f9f7	1804	/* Current option in DAC configuration option */
<>	144:ef7eb2e8f9f7	1805	typedef enum DAC_CURRENT_OPT {
<>	144:ef7eb2e8f9f7	1806	DAC_MAX_UPDATE_RATE_1MHz = 0, /* Shorter settling times and higher power consumption;
<>	144:ef7eb2e8f9f7	1807	allows for a maximum update rate of 1 MHz */
<>	144:ef7eb2e8f9f7	1808	DAC_MAX_UPDATE_RATE_400kHz /* Longer settling times and lower power consumption;
<>	144:ef7eb2e8f9f7	1809	allows for a maximum update rate of 400 kHz */
<>	144:ef7eb2e8f9f7	1810	} DAC_CURRENT_OPT_T;
<>	144:ef7eb2e8f9f7	1811
<>	144:ef7eb2e8f9f7	1812	/* ---------------------------------------------------------------------------
<>	144:ef7eb2e8f9f7	1813	* ADC register block structure
<>	144:ef7eb2e8f9f7	1814	*/
<>	144:ef7eb2e8f9f7	1815	#define LPC_ADC0_BASE 0x400E3000
<>	144:ef7eb2e8f9f7	1816	#define LPC_ADC1_BASE 0x400E4000
<>	144:ef7eb2e8f9f7	1817	#define ADC_ACC_10BITS
<>	144:ef7eb2e8f9f7	1818
<>	144:ef7eb2e8f9f7	1819	/* ---------------------------------------------------------------------------
<>	144:ef7eb2e8f9f7	1820	* 10 or 12-bit ADC register block structure
<>	144:ef7eb2e8f9f7	1821	*/
<>	144:ef7eb2e8f9f7	1822	typedef struct { /* ADCn Structure */
<>	144:ef7eb2e8f9f7	1823	__IO uint32_t CR; /* A/D Control Register. The AD0CR register must be written to select the operating mode before A/D conversion can occur. */
<>	144:ef7eb2e8f9f7	1824	__I uint32_t GDR; /* A/D Global Data Register. Contains the result of the most recent A/D conversion. */
<>	144:ef7eb2e8f9f7	1825	__I uint32_t RESERVED0;
<>	144:ef7eb2e8f9f7	1826	__IO uint32_t INTEN; /* A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt. */
<>	144:ef7eb2e8f9f7	1827	__I uint32_t DR[8]; /* A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n. */
<>	144:ef7eb2e8f9f7	1828	__I uint32_t STAT; /* A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag. */
<>	144:ef7eb2e8f9f7	1829	} LPC_ADC_T;
<>	144:ef7eb2e8f9f7	1830
<>	144:ef7eb2e8f9f7	1831	/* ADC register support bitfields and mask */
<>	144:ef7eb2e8f9f7	1832	#define ADC_RANGE 0x3FF
<>	144:ef7eb2e8f9f7	1833	#define ADC_DR_RESULT(n) ((((n) >> 6) & 0x3FF)) /* Mask for getting the 10 bits ADC data read value */
<>	144:ef7eb2e8f9f7	1834	#define ADC_CR_BITACC(n) ((((n) & 0x7) << 17)) /* Number of ADC accuracy bits */
<>	144:ef7eb2e8f9f7	1835	#define ADC_DR_DONE(n) (((n) >> 31)) /* Mask for reading the ADC done status */
<>	144:ef7eb2e8f9f7	1836	#define ADC_DR_OVERRUN(n) ((((n) >> 30) & (1UL))) /* Mask for reading the ADC overrun status */
<>	144:ef7eb2e8f9f7	1837	#define ADC_CR_CH_SEL(n) ((1UL << (n))) /* Selects which of the AD0.0:7 pins is (are) to be sampled and converted */
<>	144:ef7eb2e8f9f7	1838	#define ADC_CR_CLKDIV(n) ((((n) & 0xFF) << 8)) /* The APB clock (PCLK) is divided by (this value plus one) to produce the clock for the A/D */
<>	144:ef7eb2e8f9f7	1839	#define ADC_CR_BURST ((1UL << 16)) /* Repeated conversions A/D enable bit */
<>	144:ef7eb2e8f9f7	1840	#define ADC_CR_PDN ((1UL << 21)) /* ADC convert is operational */
<>	144:ef7eb2e8f9f7	1841	#define ADC_CR_START_MASK ((7UL << 24)) /* ADC start mask bits */
<>	144:ef7eb2e8f9f7	1842	#define ADC_CR_START_MODE_SEL(SEL) ((SEL << 24)) /* Select Start Mode */
<>	144:ef7eb2e8f9f7	1843	#define ADC_CR_START_NOW ((1UL << 24)) /* Start conversion now */
<>	144:ef7eb2e8f9f7	1844	#define ADC_CR_START_CTOUT15 ((2UL << 24)) /* Start conversion when the edge selected by bit 27 occurs on CTOUT_15 */
<>	144:ef7eb2e8f9f7	1845	#define ADC_CR_START_CTOUT8 ((3UL << 24)) /* Start conversion when the edge selected by bit 27 occurs on CTOUT_8 */
<>	144:ef7eb2e8f9f7	1846	#define ADC_CR_START_ADCTRIG0 ((4UL << 24)) /* Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 */
<>	144:ef7eb2e8f9f7	1847	#define ADC_CR_START_ADCTRIG1 ((5UL << 24)) /* Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 */
<>	144:ef7eb2e8f9f7	1848	#define ADC_CR_START_MCOA2 ((6UL << 24)) /* Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2 */
<>	144:ef7eb2e8f9f7	1849	#define ADC_CR_EDGE ((1UL << 27)) /* Start conversion on a falling edge on the selected CAP/MAT signal */
<>	144:ef7eb2e8f9f7	1850	#define ADC_CONFIG_MASK (ADC_CR_CLKDIV(0xFF) \| ADC_CR_BITACC(0x07) \| ADC_CR_PDN)
<>	144:ef7eb2e8f9f7	1851
<>	144:ef7eb2e8f9f7	1852	/* ADC status register used for IP drivers */
<>	144:ef7eb2e8f9f7	1853	typedef enum ADC_STATUS {
<>	144:ef7eb2e8f9f7	1854	ADC_DR_DONE_STAT, /* ADC data register staus */
<>	144:ef7eb2e8f9f7	1855	ADC_DR_OVERRUN_STAT,/* ADC data overrun staus */
<>	144:ef7eb2e8f9f7	1856	ADC_DR_ADINT_STAT /* ADC interrupt status */
<>	144:ef7eb2e8f9f7	1857	} ADC_STATUS_T;
<>	144:ef7eb2e8f9f7	1858
<>	144:ef7eb2e8f9f7	1859	/** Start mode, which controls the start of an A/D conversion when the BURST bit is 0. */
<>	144:ef7eb2e8f9f7	1860	typedef enum ADC_START_MODE {
<>	144:ef7eb2e8f9f7	1861	ADC_NO_START = 0,
<>	144:ef7eb2e8f9f7	1862	ADC_START_NOW, /* Start conversion now */
<>	144:ef7eb2e8f9f7	1863	ADC_START_ON_CTOUT15, /* Start conversion when the edge selected by bit 27 occurs on CTOUT_15 */
<>	144:ef7eb2e8f9f7	1864	ADC_START_ON_CTOUT8, /* Start conversion when the edge selected by bit 27 occurs on CTOUT_8 */
<>	144:ef7eb2e8f9f7	1865	ADC_START_ON_ADCTRIG0, /* Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 */
<>	144:ef7eb2e8f9f7	1866	ADC_START_ON_ADCTRIG1, /* Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 */
<>	144:ef7eb2e8f9f7	1867	ADC_START_ON_MCOA2 /* Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2 */
<>	144:ef7eb2e8f9f7	1868	} ADC_START_MODE_T;
<>	144:ef7eb2e8f9f7	1869
<>	144:ef7eb2e8f9f7	1870	/* ---------------------------------------------------------------------------
<>	144:ef7eb2e8f9f7	1871	* GPIO port register block structure
<>	144:ef7eb2e8f9f7	1872	*/
<>	144:ef7eb2e8f9f7	1873	#define LPC_GPIO_PORT_BASE 0x400F4000
<>	144:ef7eb2e8f9f7	1874	#define LPC_GPIO0_BASE (LPC_GPIO_PORT_BASE)
<>	144:ef7eb2e8f9f7	1875	#define LPC_GPIO1_BASE (LPC_GPIO_PORT_BASE + 0x04)
<>	144:ef7eb2e8f9f7	1876	#define LPC_GPIO2_BASE (LPC_GPIO_PORT_BASE + 0x08)
<>	144:ef7eb2e8f9f7	1877	#define LPC_GPIO3_BASE (LPC_GPIO_PORT_BASE + 0x0C)
<>	144:ef7eb2e8f9f7	1878	#define LPC_GPIO4_BASE (LPC_GPIO_PORT_BASE + 0x10)
<>	144:ef7eb2e8f9f7	1879	#define LPC_GPIO5_BASE (LPC_GPIO_PORT_BASE + 0x14)
<>	144:ef7eb2e8f9f7	1880	#define LPC_GPIO6_BASE (LPC_GPIO_PORT_BASE + 0x18)
<>	144:ef7eb2e8f9f7	1881	#define LPC_GPIO7_BASE (LPC_GPIO_PORT_BASE + 0x1C)
<>	144:ef7eb2e8f9f7	1882
<>	144:ef7eb2e8f9f7	1883	typedef struct { /* GPIO_PORT Structure */
<>	144:ef7eb2e8f9f7	1884	__IO uint8_t B[128][32]; /* Offset 0x0000: Byte pin registers ports 0 to n; pins PIOn_0 to PIOn_31 */
<>	144:ef7eb2e8f9f7	1885	__IO uint32_t W[32][32]; /* Offset 0x1000: Word pin registers port 0 to n */
<>	144:ef7eb2e8f9f7	1886	__IO uint32_t DIR[32]; /* Offset 0x2000: Direction registers port n */
<>	144:ef7eb2e8f9f7	1887	__IO uint32_t MASK[32]; /* Offset 0x2080: Mask register port n */
<>	144:ef7eb2e8f9f7	1888	__IO uint32_t PIN[32]; /* Offset 0x2100: Portpin register port n */
<>	144:ef7eb2e8f9f7	1889	__IO uint32_t MPIN[32]; /* Offset 0x2180: Masked port register port n */
<>	144:ef7eb2e8f9f7	1890	__IO uint32_t SET[32]; /* Offset 0x2200: Write: Set register for port n Read: output bits for port n */
<>	144:ef7eb2e8f9f7	1891	__O uint32_t CLR[32]; /* Offset 0x2280: Clear port n */
<>	144:ef7eb2e8f9f7	1892	__O uint32_t NOT[32]; /* Offset 0x2300: Toggle port n */
<>	144:ef7eb2e8f9f7	1893	} LPC_GPIO_T;
<>	144:ef7eb2e8f9f7	1894
<>	144:ef7eb2e8f9f7	1895	/* Calculate GPIO offset and port register address from group and pin number */
<>	144:ef7eb2e8f9f7	1896	#define GPIO_OFF(port, pin) ((port << 5) + pin)
<>	144:ef7eb2e8f9f7	1897	#define GPIO_REG(port, pin) ((__IO uint32_t *)(LPC_GPIO_PORT_BASE + 0x2000 + GPIO_OFF(port, pin)))
<>	144:ef7eb2e8f9f7	1898
<>	144:ef7eb2e8f9f7	1899	/* ---------------------------------------------------------------------------
<>	144:ef7eb2e8f9f7	1900	* SPI register block structure
<>	144:ef7eb2e8f9f7	1901	*/
<>	144:ef7eb2e8f9f7	1902	#define LPC_SPI_BASE 0x40100000
<>	144:ef7eb2e8f9f7	1903
<>	144:ef7eb2e8f9f7	1904	typedef struct { /* SPI Structure */
<>	144:ef7eb2e8f9f7	1905	__IO uint32_t CR; /* SPI Control Register. This register controls the operation of the SPI. */
<>	144:ef7eb2e8f9f7	1906	__I uint32_t SR; /* SPI Status Register. This register shows the status of the SPI. */
<>	144:ef7eb2e8f9f7	1907	__IO uint32_t DR; /* SPI Data Register. This bi-directional register provides the transmit and receive data for the SPI. */
<>	144:ef7eb2e8f9f7	1908	__IO uint32_t CCR; /* SPI Clock Counter Register. This register controls the frequency of a master's SCK0. */
<>	144:ef7eb2e8f9f7	1909	__I uint32_t RESERVED0[3];
<>	144:ef7eb2e8f9f7	1910	__IO uint32_t INT; /* SPI Interrupt Flag. This register contains the interrupt flag for the SPI interface. */
<>	144:ef7eb2e8f9f7	1911	} LPC_SPI_T;
<>	144:ef7eb2e8f9f7	1912
<>	144:ef7eb2e8f9f7	1913	/* SPI CFG Register BitMask */
<>	144:ef7eb2e8f9f7	1914	#define SPI_CR_BITMASK ((uint32_t) 0xFFC)
<>	144:ef7eb2e8f9f7	1915	/* Enable of controlling the number of bits per transfer */
<>	144:ef7eb2e8f9f7	1916	#define SPI_CR_BIT_EN ((uint32_t) (1 << 2))
<>	144:ef7eb2e8f9f7	1917	/* Mask of field of bit controlling */
<>	144:ef7eb2e8f9f7	1918	#define SPI_CR_BITS_MASK ((uint32_t) 0xF00)
<>	144:ef7eb2e8f9f7	1919	/* Set the number of bits per a transfer */
<>	144:ef7eb2e8f9f7	1920	#define SPI_CR_BITS(n) ((uint32_t) ((n << 8) & 0xF00)) /* n is in range 8-16 */
<>	144:ef7eb2e8f9f7	1921	/* SPI Clock Phase Select*/
<>	144:ef7eb2e8f9f7	1922	#define SPI_CR_CPHA_FIRST ((uint32_t) (0)) /Capture data on the first edge, Change data on the following edge/
<>	144:ef7eb2e8f9f7	1923	#define SPI_CR_CPHA_SECOND ((uint32_t) (1 << 3)) /* Change data on the first edge, Capture data on the following edge*/
<>	144:ef7eb2e8f9f7	1924	/* SPI Clock Polarity Select*/
<>	144:ef7eb2e8f9f7	1925	#define SPI_CR_CPOL_LO ((uint32_t) (0)) /* The rest state of the clock (between frames) is low.*/
<>	144:ef7eb2e8f9f7	1926	#define SPI_CR_CPOL_HI ((uint32_t) (1 << 4)) /* The rest state of the clock (between frames) is high.*/
<>	144:ef7eb2e8f9f7	1927	/* SPI Slave Mode Select */
<>	144:ef7eb2e8f9f7	1928	#define SPI_CR_SLAVE_EN ((uint32_t) 0)
<>	144:ef7eb2e8f9f7	1929	/* SPI Master Mode Select */
<>	144:ef7eb2e8f9f7	1930	#define SPI_CR_MASTER_EN ((uint32_t) (1 << 5))
<>	144:ef7eb2e8f9f7	1931	/* SPI MSB First mode enable */
<>	144:ef7eb2e8f9f7	1932	#define SPI_CR_MSB_FIRST_EN ((uint32_t) 0) /* Data will be transmitted and received in standard order (MSB first).*/
<>	144:ef7eb2e8f9f7	1933	/* SPI LSB First mode enable */
<>	144:ef7eb2e8f9f7	1934	#define SPI_CR_LSB_FIRST_EN ((uint32_t) (1 << 6)) /* Data will be transmitted and received in reverse order (LSB first).*/
<>	144:ef7eb2e8f9f7	1935	/* SPI interrupt enable */
<>	144:ef7eb2e8f9f7	1936	#define SPI_CR_INT_EN ((uint32_t) (1 << 7))
<>	144:ef7eb2e8f9f7	1937	/* SPI STAT Register BitMask */
<>	144:ef7eb2e8f9f7	1938	#define SPI_SR_BITMASK ((uint32_t) 0xF8)
<>	144:ef7eb2e8f9f7	1939	/* Slave abort Flag */
<>	144:ef7eb2e8f9f7	1940	#define SPI_SR_ABRT ((uint32_t) (1 << 3)) /* When 1, this bit indicates that a slave abort has occurred. */
<>	144:ef7eb2e8f9f7	1941	/* Mode fault Flag */
<>	144:ef7eb2e8f9f7	1942	#define SPI_SR_MODF ((uint32_t) (1 << 4)) /* when 1, this bit indicates that a Mode fault error has occurred. */
<>	144:ef7eb2e8f9f7	1943	/* Read overrun flag*/
<>	144:ef7eb2e8f9f7	1944	#define SPI_SR_ROVR ((uint32_t) (1 << 5)) /* When 1, this bit indicates that a read overrun has occurred. */
<>	144:ef7eb2e8f9f7	1945	/* Write collision flag. */
<>	144:ef7eb2e8f9f7	1946	#define SPI_SR_WCOL ((uint32_t) (1 << 6)) /* When 1, this bit indicates that a write collision has occurred.. */
<>	144:ef7eb2e8f9f7	1947	/* SPI transfer complete flag. */
<>	144:ef7eb2e8f9f7	1948	#define SPI_SR_SPIF ((uint32_t) (1 << 7)) /* When 1, this bit indicates when a SPI data transfer is complete.. */
<>	144:ef7eb2e8f9f7	1949	/* SPI error flag */
<>	144:ef7eb2e8f9f7	1950	#define SPI_SR_ERROR (SPI_SR_ABRT \| SPI_SR_MODF \| SPI_SR_ROVR \| SPI_SR_WCOL)
<>	144:ef7eb2e8f9f7	1951	/* Enable SPI Test Mode */
<>	144:ef7eb2e8f9f7	1952	#define SPI_TCR_TEST(n) ((uint32_t) ((n & 0x3F) << 1))
<>	144:ef7eb2e8f9f7	1953	/* SPI interrupt flag */
<>	144:ef7eb2e8f9f7	1954	#define SPI_INT_SPIF ((uint32_t) (1 << 0))
<>	144:ef7eb2e8f9f7	1955	/* Receiver Data */
<>	144:ef7eb2e8f9f7	1956	#define SPI_DR_DATA(n) ((uint32_t) ((n) & 0xFFFF))
<>	144:ef7eb2e8f9f7	1957
<>	144:ef7eb2e8f9f7	1958	/* SPI Mode*/
<>	144:ef7eb2e8f9f7	1959	typedef enum LPC_SPI_MODE {
<>	144:ef7eb2e8f9f7	1960	SPI_MODE_MASTER = SPI_CR_MASTER_EN, /* Master Mode */
<>	144:ef7eb2e8f9f7	1961	SPI_MODE_SLAVE = SPI_CR_SLAVE_EN, /* Slave Mode */
<>	144:ef7eb2e8f9f7	1962	} LPC_SPI_MODE_T;
<>	144:ef7eb2e8f9f7	1963
<>	144:ef7eb2e8f9f7	1964	/* SPI Clock Mode*/
<>	144:ef7eb2e8f9f7	1965	typedef enum LPC_SPI_CLOCK_MODE {
<>	144:ef7eb2e8f9f7	1966	SPI_CLOCK_CPHA0_CPOL0 = SPI_CR_CPOL_LO \| SPI_CR_CPHA_FIRST, /* CPHA = 0, CPOL = 0 */
<>	144:ef7eb2e8f9f7	1967	SPI_CLOCK_CPHA0_CPOL1 = SPI_CR_CPOL_HI \| SPI_CR_CPHA_FIRST, /* CPHA = 0, CPOL = 1 */
<>	144:ef7eb2e8f9f7	1968	SPI_CLOCK_CPHA1_CPOL0 = SPI_CR_CPOL_LO \| SPI_CR_CPHA_SECOND, /* CPHA = 1, CPOL = 0 */
<>	144:ef7eb2e8f9f7	1969	SPI_CLOCK_CPHA1_CPOL1 = SPI_CR_CPOL_HI \| SPI_CR_CPHA_SECOND, /* CPHA = 1, CPOL = 1 */
<>	144:ef7eb2e8f9f7	1970	SPI_CLOCK_MODE0 = SPI_CLOCK_CPHA0_CPOL0, /* alias */
<>	144:ef7eb2e8f9f7	1971	SPI_CLOCK_MODE1 = SPI_CLOCK_CPHA1_CPOL0, /* alias */
<>	144:ef7eb2e8f9f7	1972	SPI_CLOCK_MODE2 = SPI_CLOCK_CPHA0_CPOL1, /* alias */
<>	144:ef7eb2e8f9f7	1973	SPI_CLOCK_MODE3 = SPI_CLOCK_CPHA1_CPOL1, /* alias */
<>	144:ef7eb2e8f9f7	1974	} LPC_SPI_CLOCK_MODE_T;
<>	144:ef7eb2e8f9f7	1975
<>	144:ef7eb2e8f9f7	1976	/* SPI Data Order Mode*/
<>	144:ef7eb2e8f9f7	1977	typedef enum LPC_SPI_DATA_ORDER {
<>	144:ef7eb2e8f9f7	1978	SPI_DATA_MSB_FIRST = SPI_CR_MSB_FIRST_EN, /* Standard Order */
<>	144:ef7eb2e8f9f7	1979	SPI_DATA_LSB_FIRST = SPI_CR_LSB_FIRST_EN, /* Reverse Order */
<>	144:ef7eb2e8f9f7	1980	} LPC_SPI_DATA_ORDER_T;
<>	144:ef7eb2e8f9f7	1981
<>	144:ef7eb2e8f9f7	1982	/* ---------------------------------------------------------------------------
<>	144:ef7eb2e8f9f7	1983	* Serial GPIO register block structure
<>	144:ef7eb2e8f9f7	1984	*/
<>	144:ef7eb2e8f9f7	1985	#define LPC_SGPIO_BASE 0x40101000
<>	144:ef7eb2e8f9f7	1986
<>	144:ef7eb2e8f9f7	1987	typedef struct { /* SGPIO Structure */
<>	144:ef7eb2e8f9f7	1988	__IO uint32_t OUT_MUX_CFG[16]; /* Pin multiplexer configurationregisters. */
<>	144:ef7eb2e8f9f7	1989	__IO uint32_t SGPIO_MUX_CFG[16]; /* SGPIO multiplexer configuration registers. */
<>	144:ef7eb2e8f9f7	1990	__IO uint32_t SLICE_MUX_CFG[16]; /* Slice multiplexer configuration registers. */
<>	144:ef7eb2e8f9f7	1991	__IO uint32_t REG[16]; /* Slice data registers. Eachtime COUNT0 reaches 0x0 the register shifts loading bit 31 withdata captured from DIN(n). DOUT(n) is set to REG(0) */
<>	144:ef7eb2e8f9f7	1992	__IO uint32_t REG_SS[16]; /* Slice data shadow registers. Each time POSreaches 0x0 the contents of REG_SS is exchanged with the contentof REG */
<>	144:ef7eb2e8f9f7	1993	__IO uint32_t PRESET[16]; /* Reload valueof COUNT0, loaded when COUNT0 reaches 0x0 */
<>	144:ef7eb2e8f9f7	1994	__IO uint32_t COUNT[16]; /* Down counter, counts down each clock cycle. */
<>	144:ef7eb2e8f9f7	1995	__IO uint32_t POS[16]; /* Each time COUNT0 reaches 0x0 */
<>	144:ef7eb2e8f9f7	1996	__IO uint32_t MASK_A; /* Mask for pattern match function of slice A */
<>	144:ef7eb2e8f9f7	1997	__IO uint32_t MASK_H; /* Mask for pattern match function of slice H */
<>	144:ef7eb2e8f9f7	1998	__IO uint32_t MASK_I; /* Mask for pattern match function of slice I */
<>	144:ef7eb2e8f9f7	1999	__IO uint32_t MASK_P; /* Mask for pattern match function of slice P */
<>	144:ef7eb2e8f9f7	2000	__I uint32_t GPIO_INREG; /* GPIO input status register */
<>	144:ef7eb2e8f9f7	2001	__IO uint32_t GPIO_OUTREG; /* GPIO output control register */
<>	144:ef7eb2e8f9f7	2002	__IO uint32_t GPIO_OENREG; /* GPIO OE control register */
<>	144:ef7eb2e8f9f7	2003	__IO uint32_t CTRL_ENABLED; /* Enables the slice COUNT counter */
<>	144:ef7eb2e8f9f7	2004	__IO uint32_t CTRL_DISABLED; /* Disables the slice COUNT counter */
<>	144:ef7eb2e8f9f7	2005	__I uint32_t RESERVED0[823];
<>	144:ef7eb2e8f9f7	2006	__O uint32_t CLR_EN_0; /* Shift clock interrupt clear mask */
<>	144:ef7eb2e8f9f7	2007	__O uint32_t SET_EN_0; /* Shift clock interrupt set mask */
<>	144:ef7eb2e8f9f7	2008	__I uint32_t ENABLE_0; /* Shift clock interrupt enable */
<>	144:ef7eb2e8f9f7	2009	__I uint32_t STATUS_0; /* Shift clock interrupt status */
<>	144:ef7eb2e8f9f7	2010	__O uint32_t CTR_STATUS_0; /* Shift clock interrupt clear status */
<>	144:ef7eb2e8f9f7	2011	__O uint32_t SET_STATUS_0; /* Shift clock interrupt set status */
<>	144:ef7eb2e8f9f7	2012	__I uint32_t RESERVED1[2];
<>	144:ef7eb2e8f9f7	2013	__O uint32_t CLR_EN_1; /* Capture clock interrupt clear mask */
<>	144:ef7eb2e8f9f7	2014	__O uint32_t SET_EN_1; /* Capture clock interrupt set mask */
<>	144:ef7eb2e8f9f7	2015	__I uint32_t ENABLE_1; /* Capture clock interrupt enable */
<>	144:ef7eb2e8f9f7	2016	__I uint32_t STATUS_1; /* Capture clock interrupt status */
<>	144:ef7eb2e8f9f7	2017	__O uint32_t CTR_STATUS_1; /* Capture clock interrupt clear status */
<>	144:ef7eb2e8f9f7	2018	__O uint32_t SET_STATUS_1; /* Capture clock interrupt set status */
<>	144:ef7eb2e8f9f7	2019	__I uint32_t RESERVED2[2];
<>	144:ef7eb2e8f9f7	2020	__O uint32_t CLR_EN_2; /* Pattern match interrupt clear mask */
<>	144:ef7eb2e8f9f7	2021	__O uint32_t SET_EN_2; /* Pattern match interrupt set mask */
<>	144:ef7eb2e8f9f7	2022	__I uint32_t ENABLE_2; /* Pattern match interrupt enable */
<>	144:ef7eb2e8f9f7	2023	__I uint32_t STATUS_2; /* Pattern match interrupt status */
<>	144:ef7eb2e8f9f7	2024	__O uint32_t CTR_STATUS_2; /* Pattern match interrupt clear status */
<>	144:ef7eb2e8f9f7	2025	__O uint32_t SET_STATUS_2; /* Pattern match interrupt set status */
<>	144:ef7eb2e8f9f7	2026	__I uint32_t RESERVED3[2];
<>	144:ef7eb2e8f9f7	2027	__O uint32_t CLR_EN_3; /* Input interrupt clear mask */
<>	144:ef7eb2e8f9f7	2028	__O uint32_t SET_EN_3; /* Input bit match interrupt set mask */
<>	144:ef7eb2e8f9f7	2029	__I uint32_t ENABLE_3; /* Input bit match interrupt enable */
<>	144:ef7eb2e8f9f7	2030	__I uint32_t STATUS_3; /* Input bit match interrupt status */
<>	144:ef7eb2e8f9f7	2031	__O uint32_t CTR_STATUS_3; /* Input bit match interrupt clear status */
<>	144:ef7eb2e8f9f7	2032	__O uint32_t SET_STATUS_3; /* Shift clock interrupt set status */
<>	144:ef7eb2e8f9f7	2033	} LPC_SGPIO_T;
<>	144:ef7eb2e8f9f7	2034
<>	144:ef7eb2e8f9f7	2035	/* End of section using anonymous unions */
<>	144:ef7eb2e8f9f7	2036	#if defined(__ARMCC_VERSION)
<>	144:ef7eb2e8f9f7	2037	#pragma pop
<>	144:ef7eb2e8f9f7	2038	#elif defined(__CWCC__)
<>	144:ef7eb2e8f9f7	2039	#pragma pop
<>	144:ef7eb2e8f9f7	2040	#elif defined(__IAR_SYSTEMS_ICC__)
<>	144:ef7eb2e8f9f7	2041	//#pragma pop // FIXME not usable for IAR
<>	144:ef7eb2e8f9f7	2042	#else /* defined(__GNUC__) and others */
<>	144:ef7eb2e8f9f7	2043	/* Leave anonymous unions enabled */
<>	144:ef7eb2e8f9f7	2044	#endif
<>	144:ef7eb2e8f9f7	2045
<>	144:ef7eb2e8f9f7	2046	/* ---------------------------------------------------------------------------
<>	144:ef7eb2e8f9f7	2047	* LPC43xx Peripheral register set declarations
<>	144:ef7eb2e8f9f7	2048	*/
<>	144:ef7eb2e8f9f7	2049	#define LPC_SCT ((LPC_SCT_T *) LPC_SCT_BASE)
<>	144:ef7eb2e8f9f7	2050	#define LPC_GPDMA ((LPC_GPDMA_T *) LPC_GPDMA_BASE)
<>	144:ef7eb2e8f9f7	2051	#define LPC_SPIFI ((LPC_SPIFI_T *) LPC_SPIFI_BASE)
<>	144:ef7eb2e8f9f7	2052	#define LPC_SDMMC ((LPC_SDMMC_T *) LPC_SDMMC_BASE)
<>	144:ef7eb2e8f9f7	2053	#define LPC_EMC ((LPC_EMC_T *) LPC_EMC_BASE)
<>	144:ef7eb2e8f9f7	2054	#define LPC_USB0 ((LPC_USBHS_T *) LPC_USB0_BASE)
<>	144:ef7eb2e8f9f7	2055	#define LPC_USB1 ((LPC_USBHS_T *) LPC_USB1_BASE)
<>	144:ef7eb2e8f9f7	2056	#define LPC_LCD ((LPC_LCD_T *) LPC_LCD_BASE)
<>	144:ef7eb2e8f9f7	2057	#define LPC_EEPROM ((LPC_EEPROM_T *) LPC_EEPROM_BASE)
<>	144:ef7eb2e8f9f7	2058	#define LPC_ETHERNET ((LPC_ENET_T *) LPC_ETHERNET_BASE)
<>	144:ef7eb2e8f9f7	2059	#define LPC_ATIMER ((LPC_ATIMER_T *) LPC_ATIMER_BASE)
<>	144:ef7eb2e8f9f7	2060	#define LPC_REGFILE ((LPC_REGFILE_T *) LPC_REGFILE_BASE)
<>	144:ef7eb2e8f9f7	2061	#define LPC_PMC ((LPC_PMC_T *) LPC_PMC_BASE)
<>	144:ef7eb2e8f9f7	2062	#define LPC_CREG ((LPC_CREG_T *) LPC_CREG_BASE)
<>	144:ef7eb2e8f9f7	2063	#define LPC_EVRT ((LPC_EVRT_T *) LPC_EVRT_BASE)
<>	144:ef7eb2e8f9f7	2064	#define LPC_RTC ((LPC_RTC_T *) LPC_RTC_BASE)
<>	144:ef7eb2e8f9f7	2065	#define LPC_CGU ((LPC_CGU_T *) LPC_CGU_BASE)
<>	144:ef7eb2e8f9f7	2066	#define LPC_CCU1 ((LPC_CCU1_T *) LPC_CCU1_BASE)
<>	144:ef7eb2e8f9f7	2067	#define LPC_CCU2 ((LPC_CCU2_T *) LPC_CCU2_BASE)
<>	144:ef7eb2e8f9f7	2068	#define LPC_RGU ((LPC_RGU_T *) LPC_RGU_BASE)
<>	144:ef7eb2e8f9f7	2069	#define LPC_WWDT ((LPC_WWDT_T *) LPC_WWDT_BASE)
<>	144:ef7eb2e8f9f7	2070	#define LPC_USART0 ((LPC_USART_T *) LPC_USART0_BASE)
<>	144:ef7eb2e8f9f7	2071	#define LPC_USART2 ((LPC_USART_T *) LPC_USART2_BASE)
<>	144:ef7eb2e8f9f7	2072	#define LPC_USART3 ((LPC_USART_T *) LPC_USART3_BASE)
<>	144:ef7eb2e8f9f7	2073	#define LPC_UART1 ((LPC_USART_T *) LPC_UART1_BASE)
<>	144:ef7eb2e8f9f7	2074	#define LPC_SSP0 ((LPC_SSP_T *) LPC_SSP0_BASE)
<>	144:ef7eb2e8f9f7	2075	#define LPC_SSP1 ((LPC_SSP_T *) LPC_SSP1_BASE)
<>	144:ef7eb2e8f9f7	2076	#define LPC_TIMER0 ((LPC_TIMER_T *) LPC_TIMER0_BASE)
<>	144:ef7eb2e8f9f7	2077	#define LPC_TIMER1 ((LPC_TIMER_T *) LPC_TIMER1_BASE)
<>	144:ef7eb2e8f9f7	2078	#define LPC_TIMER2 ((LPC_TIMER_T *) LPC_TIMER2_BASE)
<>	144:ef7eb2e8f9f7	2079	#define LPC_TIMER3 ((LPC_TIMER_T *) LPC_TIMER3_BASE)
<>	144:ef7eb2e8f9f7	2080	#define LPC_SCU ((LPC_SCU_T *) LPC_SCU_BASE)
<>	144:ef7eb2e8f9f7	2081	#define LPC_GPIO_PIN_INT ((LPC_GPIOPININT_T *) LPC_GPIO_PIN_INT_BASE)
<>	144:ef7eb2e8f9f7	2082	#define LPC_GPIO_GROUP_INT0 ((IP_GPIOGROUPINT_T *) LPC_GPIO_GROUP_INT0_BASE)
<>	144:ef7eb2e8f9f7	2083	#define LPC_GPIO_GROUP_INT1 ((IP_GPIOGROUPINT_T *) LPC_GPIO_GROUP_INT1_BASE)
<>	144:ef7eb2e8f9f7	2084	#define LPC_MCPWM ((LPC_MCPWM_T *) LPC_MCPWM_BASE)
<>	144:ef7eb2e8f9f7	2085	#define LPC_I2C0 ((LPC_I2C_T *) LPC_I2C0_BASE)
<>	144:ef7eb2e8f9f7	2086	#define LPC_I2C1 ((LPC_I2C_T *) LPC_I2C1_BASE)
<>	144:ef7eb2e8f9f7	2087	#define LPC_I2S0 ((LPC_I2S_T *) LPC_I2S0_BASE)
<>	144:ef7eb2e8f9f7	2088	#define LPC_I2S1 ((LPC_I2S_T *) LPC_I2S1_BASE)
<>	144:ef7eb2e8f9f7	2089	#define LPC_C_CAN1 ((LPC_CCAN_T *) LPC_C_CAN1_BASE)
<>	144:ef7eb2e8f9f7	2090	#define LPC_RITIMER ((LPC_RITIMER_T *) LPC_RITIMER_BASE)
<>	144:ef7eb2e8f9f7	2091	#define LPC_QEI ((LPC_QEI_T *) LPC_QEI_BASE)
<>	144:ef7eb2e8f9f7	2092	#define LPC_GIMA ((LPC_GIMA_T *) LPC_GIMA_BASE)
<>	144:ef7eb2e8f9f7	2093	#define LPC_DAC ((LPC_DAC_T *) LPC_DAC_BASE)
<>	144:ef7eb2e8f9f7	2094	#define LPC_C_CAN0 ((LPC_CCAN_T *) LPC_C_CAN0_BASE)
<>	144:ef7eb2e8f9f7	2095	#define LPC_ADC0 ((LPC_ADC_T *) LPC_ADC0_BASE)
<>	144:ef7eb2e8f9f7	2096	#define LPC_ADC1 ((LPC_ADC_T *) LPC_ADC1_BASE)
<>	144:ef7eb2e8f9f7	2097	#define LPC_GPIO_PORT ((LPC_GPIO_T *) LPC_GPIO_PORT_BASE)
<>	144:ef7eb2e8f9f7	2098	#define LPC_GPIO0 ((LPC_GPIO_T *) LPC_GPIO0_BASE)
<>	144:ef7eb2e8f9f7	2099	#define LPC_GPIO1 ((LPC_GPIO_T *) LPC_GPIO1_BASE)
<>	144:ef7eb2e8f9f7	2100	#define LPC_GPIO2 ((LPC_GPIO_T *) LPC_GPIO2_BASE)
<>	144:ef7eb2e8f9f7	2101	#define LPC_GPIO3 ((LPC_GPIO_T *) LPC_GPIO3_BASE)
<>	144:ef7eb2e8f9f7	2102	#define LPC_GPIO4 ((LPC_GPIO_T *) LPC_GPIO4_BASE)
<>	144:ef7eb2e8f9f7	2103	#define LPC_GPIO5 ((LPC_GPIO_T *) LPC_GPIO5_BASE)
<>	144:ef7eb2e8f9f7	2104	#define LPC_GPIO6 ((LPC_GPIO_T *) LPC_GPIO6_BASE)
<>	144:ef7eb2e8f9f7	2105	#define LPC_GPIO7 ((LPC_GPIO_T *) LPC_GPIO7_BASE)
<>	144:ef7eb2e8f9f7	2106	#define LPC_SPI ((LPC_SPI_T *) LPC_SPI_BASE)
<>	144:ef7eb2e8f9f7	2107	#define LPC_SGPIO ((LPC_SGPIO_T *) LPC_SGPIO_BASE)
<>	144:ef7eb2e8f9f7	2108
<>	144:ef7eb2e8f9f7	2109	#ifdef __cplusplus
<>	144:ef7eb2e8f9f7	2110	}
<>	144:ef7eb2e8f9f7	2111	#endif
<>	144:ef7eb2e8f9f7	2112
<>	144:ef7eb2e8f9f7	2113	#endif /* __LPC43XX_H */

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Type:	Library
Created:	14 Nov 2016
Imports:	2
Forks:	0
Commits:	152
Dependents:	0
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Followers:	1

targets/cmsis/TARGET_NXP/TARGET_LPC43XX/LPC43xx.h@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

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