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targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_burtc.h@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
50:a417edff4437 
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**************************************************************************//**
<> 144:ef7eb2e8f9f7 2 * @file efm32gg_burtc.h
<> 144:ef7eb2e8f9f7 3 * @brief EFM32GG_BURTC register and bit field definitions
<> 144:ef7eb2e8f9f7 4 * @version 4.2.0
<> 144:ef7eb2e8f9f7 5 ******************************************************************************
<> 144:ef7eb2e8f9f7 6 * @section License
<> 144:ef7eb2e8f9f7 7 * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * Permission is granted to anyone to use this software for any purpose,
<> 144:ef7eb2e8f9f7 11 * including commercial applications, and to alter it and redistribute it
<> 144:ef7eb2e8f9f7 12 * freely, subject to the following restrictions:
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * 1. The origin of this software must not be misrepresented; you must not
<> 144:ef7eb2e8f9f7 15 * claim that you wrote the original software.@n
<> 144:ef7eb2e8f9f7 16 * 2. Altered source versions must be plainly marked as such, and must not be
<> 144:ef7eb2e8f9f7 17 * misrepresented as being the original software.@n
<> 144:ef7eb2e8f9f7 18 * 3. This notice may not be removed or altered from any source distribution.
<> 144:ef7eb2e8f9f7 19 *
<> 144:ef7eb2e8f9f7 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
<> 144:ef7eb2e8f9f7 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
<> 144:ef7eb2e8f9f7 22 * providing the Software "AS IS", with no express or implied warranties of any
<> 144:ef7eb2e8f9f7 23 * kind, including, but not limited to, any implied warranties of
<> 144:ef7eb2e8f9f7 24 * merchantability or fitness for any particular purpose or warranties against
<> 144:ef7eb2e8f9f7 25 * infringement of any proprietary rights of a third party.
<> 144:ef7eb2e8f9f7 26 *
<> 144:ef7eb2e8f9f7 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
<> 144:ef7eb2e8f9f7 28 * incidental, or special damages, or any other relief, or for any claim by
<> 144:ef7eb2e8f9f7 29 * any third party, arising from your use of this Software.
<> 144:ef7eb2e8f9f7 30 *
<> 144:ef7eb2e8f9f7 31 *****************************************************************************/
<> 144:ef7eb2e8f9f7 32 /**************************************************************************//**
<> 144:ef7eb2e8f9f7 33 * @addtogroup Parts
<> 144:ef7eb2e8f9f7 34 * @{
<> 144:ef7eb2e8f9f7 35 ******************************************************************************/
<> 144:ef7eb2e8f9f7 36 /**************************************************************************//**
<> 144:ef7eb2e8f9f7 37 * @defgroup EFM32GG_BURTC
<> 144:ef7eb2e8f9f7 38 * @{
<> 144:ef7eb2e8f9f7 39 * @brief EFM32GG_BURTC Register Declaration
<> 144:ef7eb2e8f9f7 40 *****************************************************************************/
<> 144:ef7eb2e8f9f7 41 typedef struct
<> 144:ef7eb2e8f9f7 42 {
<> 144:ef7eb2e8f9f7 43 __IO uint32_t CTRL; /**< Control Register */
<> 144:ef7eb2e8f9f7 44 __IO uint32_t LPMODE; /**< Low power mode configuration */
<> 144:ef7eb2e8f9f7 45 __I uint32_t CNT; /**< Counter Value Register */
<> 144:ef7eb2e8f9f7 46 __IO uint32_t COMP0; /**< Counter Compare Value */
<> 144:ef7eb2e8f9f7 47 __I uint32_t TIMESTAMP; /**< Backup mode timestamp */
<> 144:ef7eb2e8f9f7 48 __IO uint32_t LFXOFDET; /**< LFXO */
<> 144:ef7eb2e8f9f7 49 __I uint32_t STATUS; /**< Status Register */
<> 144:ef7eb2e8f9f7 50 __IO uint32_t CMD; /**< Command Register */
<> 144:ef7eb2e8f9f7 51 __IO uint32_t POWERDOWN; /**< Retention RAM power-down Register */
<> 144:ef7eb2e8f9f7 52 __IO uint32_t LOCK; /**< Configuration Lock Register */
<> 144:ef7eb2e8f9f7 53 __I uint32_t IF; /**< Interrupt Flag Register */
<> 144:ef7eb2e8f9f7 54 __IO uint32_t IFS; /**< Interrupt Flag Set Register */
<> 144:ef7eb2e8f9f7 55 __IO uint32_t IFC; /**< Interrupt Flag Clear Register */
<> 144:ef7eb2e8f9f7 56 __IO uint32_t IEN; /**< Interrupt Enable Register */
<> 144:ef7eb2e8f9f7 57
<> 144:ef7eb2e8f9f7 58 __IO uint32_t FREEZE; /**< Freeze Register */
<> 144:ef7eb2e8f9f7 59 __I uint32_t SYNCBUSY; /**< Synchronization Busy Register */
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 uint32_t RESERVED0[48]; /**< Reserved registers */
<> 144:ef7eb2e8f9f7 62 BURTC_RET_TypeDef RET[128]; /**< RetentionReg */
<> 144:ef7eb2e8f9f7 63 } BURTC_TypeDef; /** @} */
<> 144:ef7eb2e8f9f7 64
<> 144:ef7eb2e8f9f7 65 /**************************************************************************//**
<> 144:ef7eb2e8f9f7 66 * @defgroup EFM32GG_BURTC_BitFields
<> 144:ef7eb2e8f9f7 67 * @{
<> 144:ef7eb2e8f9f7 68 *****************************************************************************/
<> 144:ef7eb2e8f9f7 69
<> 144:ef7eb2e8f9f7 70 /* Bit fields for BURTC CTRL */
<> 144:ef7eb2e8f9f7 71 #define _BURTC_CTRL_RESETVALUE 0x00000008UL /**< Default value for BURTC_CTRL */
<> 144:ef7eb2e8f9f7 72 #define _BURTC_CTRL_MASK 0x000077FFUL /**< Mask for BURTC_CTRL */
<> 144:ef7eb2e8f9f7 73 #define _BURTC_CTRL_MODE_SHIFT 0 /**< Shift value for BURTC_MODE */
<> 144:ef7eb2e8f9f7 74 #define _BURTC_CTRL_MODE_MASK 0x3UL /**< Bit mask for BURTC_MODE */
<> 144:ef7eb2e8f9f7 75 #define _BURTC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CTRL */
<> 144:ef7eb2e8f9f7 76 #define _BURTC_CTRL_MODE_DISABLE 0x00000000UL /**< Mode DISABLE for BURTC_CTRL */
<> 144:ef7eb2e8f9f7 77 #define _BURTC_CTRL_MODE_EM2EN 0x00000001UL /**< Mode EM2EN for BURTC_CTRL */
<> 144:ef7eb2e8f9f7 78 #define _BURTC_CTRL_MODE_EM3EN 0x00000002UL /**< Mode EM3EN for BURTC_CTRL */
<> 144:ef7eb2e8f9f7 79 #define _BURTC_CTRL_MODE_EM4EN 0x00000003UL /**< Mode EM4EN for BURTC_CTRL */
<> 144:ef7eb2e8f9f7 80 #define BURTC_CTRL_MODE_DEFAULT (_BURTC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_CTRL */
<> 144:ef7eb2e8f9f7 81 #define BURTC_CTRL_MODE_DISABLE (_BURTC_CTRL_MODE_DISABLE << 0) /**< Shifted mode DISABLE for BURTC_CTRL */
<> 144:ef7eb2e8f9f7 82 #define BURTC_CTRL_MODE_EM2EN (_BURTC_CTRL_MODE_EM2EN << 0) /**< Shifted mode EM2EN for BURTC_CTRL */
<> 144:ef7eb2e8f9f7 83 #define BURTC_CTRL_MODE_EM3EN (_BURTC_CTRL_MODE_EM3EN << 0) /**< Shifted mode EM3EN for BURTC_CTRL */
<> 144:ef7eb2e8f9f7 84 #define BURTC_CTRL_MODE_EM4EN (_BURTC_CTRL_MODE_EM4EN << 0) /**< Shifted mode EM4EN for BURTC_CTRL */
<> 144:ef7eb2e8f9f7 85 #define BURTC_CTRL_DEBUGRUN (0x1UL << 2) /**< Debug Mode Run Enable */
<> 144:ef7eb2e8f9f7 86 #define _BURTC_CTRL_DEBUGRUN_SHIFT 2 /**< Shift value for BURTC_DEBUGRUN */
<> 144:ef7eb2e8f9f7 87 #define _BURTC_CTRL_DEBUGRUN_MASK 0x4UL /**< Bit mask for BURTC_DEBUGRUN */
<> 144:ef7eb2e8f9f7 88 #define _BURTC_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CTRL */
<> 144:ef7eb2e8f9f7 89 #define BURTC_CTRL_DEBUGRUN_DEFAULT (_BURTC_CTRL_DEBUGRUN_DEFAULT << 2) /**< Shifted mode DEFAULT for BURTC_CTRL */
<> 144:ef7eb2e8f9f7 90 #define BURTC_CTRL_RSTEN (0x1UL << 3) /**< Enable BURTC reset */
<> 144:ef7eb2e8f9f7 91 #define _BURTC_CTRL_RSTEN_SHIFT 3 /**< Shift value for BURTC_RSTEN */
<> 144:ef7eb2e8f9f7 92 #define _BURTC_CTRL_RSTEN_MASK 0x8UL /**< Bit mask for BURTC_RSTEN */
<> 144:ef7eb2e8f9f7 93 #define _BURTC_CTRL_RSTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for BURTC_CTRL */
<> 144:ef7eb2e8f9f7 94 #define BURTC_CTRL_RSTEN_DEFAULT (_BURTC_CTRL_RSTEN_DEFAULT << 3) /**< Shifted mode DEFAULT for BURTC_CTRL */
<> 144:ef7eb2e8f9f7 95 #define BURTC_CTRL_COMP0TOP (0x1UL << 4) /**< Compare clear enable */
<> 144:ef7eb2e8f9f7 96 #define _BURTC_CTRL_COMP0TOP_SHIFT 4 /**< Shift value for BURTC_COMP0TOP */
<> 144:ef7eb2e8f9f7 97 #define _BURTC_CTRL_COMP0TOP_MASK 0x10UL /**< Bit mask for BURTC_COMP0TOP */
<> 144:ef7eb2e8f9f7 98 #define _BURTC_CTRL_COMP0TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CTRL */
<> 144:ef7eb2e8f9f7 99 #define BURTC_CTRL_COMP0TOP_DEFAULT (_BURTC_CTRL_COMP0TOP_DEFAULT << 4) /**< Shifted mode DEFAULT for BURTC_CTRL */
<> 144:ef7eb2e8f9f7 100 #define _BURTC_CTRL_LPCOMP_SHIFT 5 /**< Shift value for BURTC_LPCOMP */
<> 144:ef7eb2e8f9f7 101 #define _BURTC_CTRL_LPCOMP_MASK 0xE0UL /**< Bit mask for BURTC_LPCOMP */
<> 144:ef7eb2e8f9f7 102 #define _BURTC_CTRL_LPCOMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CTRL */
<> 144:ef7eb2e8f9f7 103 #define _BURTC_CTRL_LPCOMP_IGN0LSB 0x00000000UL /**< Mode IGN0LSB for BURTC_CTRL */
<> 144:ef7eb2e8f9f7 104 #define _BURTC_CTRL_LPCOMP_IGN1LSB 0x00000001UL /**< Mode IGN1LSB for BURTC_CTRL */
<> 144:ef7eb2e8f9f7 105 #define _BURTC_CTRL_LPCOMP_IGN2LSB 0x00000002UL /**< Mode IGN2LSB for BURTC_CTRL */
<> 144:ef7eb2e8f9f7 106 #define _BURTC_CTRL_LPCOMP_IGN3LSB 0x00000003UL /**< Mode IGN3LSB for BURTC_CTRL */
<> 144:ef7eb2e8f9f7 107 #define _BURTC_CTRL_LPCOMP_IGN4LSB 0x00000004UL /**< Mode IGN4LSB for BURTC_CTRL */
<> 144:ef7eb2e8f9f7 108 #define _BURTC_CTRL_LPCOMP_IGN5LSB 0x00000005UL /**< Mode IGN5LSB for BURTC_CTRL */
<> 144:ef7eb2e8f9f7 109 #define _BURTC_CTRL_LPCOMP_IGN6LSB 0x00000006UL /**< Mode IGN6LSB for BURTC_CTRL */
<> 144:ef7eb2e8f9f7 110 #define _BURTC_CTRL_LPCOMP_IGN7LSB 0x00000007UL /**< Mode IGN7LSB for BURTC_CTRL */
<> 144:ef7eb2e8f9f7 111 #define BURTC_CTRL_LPCOMP_DEFAULT (_BURTC_CTRL_LPCOMP_DEFAULT << 5) /**< Shifted mode DEFAULT for BURTC_CTRL */
<> 144:ef7eb2e8f9f7 112 #define BURTC_CTRL_LPCOMP_IGN0LSB (_BURTC_CTRL_LPCOMP_IGN0LSB << 5) /**< Shifted mode IGN0LSB for BURTC_CTRL */
<> 144:ef7eb2e8f9f7 113 #define BURTC_CTRL_LPCOMP_IGN1LSB (_BURTC_CTRL_LPCOMP_IGN1LSB << 5) /**< Shifted mode IGN1LSB for BURTC_CTRL */
<> 144:ef7eb2e8f9f7 114 #define BURTC_CTRL_LPCOMP_IGN2LSB (_BURTC_CTRL_LPCOMP_IGN2LSB << 5) /**< Shifted mode IGN2LSB for BURTC_CTRL */
<> 144:ef7eb2e8f9f7 115 #define BURTC_CTRL_LPCOMP_IGN3LSB (_BURTC_CTRL_LPCOMP_IGN3LSB << 5) /**< Shifted mode IGN3LSB for BURTC_CTRL */
<> 144:ef7eb2e8f9f7 116 #define BURTC_CTRL_LPCOMP_IGN4LSB (_BURTC_CTRL_LPCOMP_IGN4LSB << 5) /**< Shifted mode IGN4LSB for BURTC_CTRL */
<> 144:ef7eb2e8f9f7 117 #define BURTC_CTRL_LPCOMP_IGN5LSB (_BURTC_CTRL_LPCOMP_IGN5LSB << 5) /**< Shifted mode IGN5LSB for BURTC_CTRL */
<> 144:ef7eb2e8f9f7 118 #define BURTC_CTRL_LPCOMP_IGN6LSB (_BURTC_CTRL_LPCOMP_IGN6LSB << 5) /**< Shifted mode IGN6LSB for BURTC_CTRL */
<> 144:ef7eb2e8f9f7 119 #define BURTC_CTRL_LPCOMP_IGN7LSB (_BURTC_CTRL_LPCOMP_IGN7LSB << 5) /**< Shifted mode IGN7LSB for BURTC_CTRL */
<> 144:ef7eb2e8f9f7 120 #define _BURTC_CTRL_PRESC_SHIFT 8 /**< Shift value for BURTC_PRESC */
<> 144:ef7eb2e8f9f7 121 #define _BURTC_CTRL_PRESC_MASK 0x700UL /**< Bit mask for BURTC_PRESC */
<> 144:ef7eb2e8f9f7 122 #define _BURTC_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CTRL */
<> 144:ef7eb2e8f9f7 123 #define _BURTC_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for BURTC_CTRL */
<> 144:ef7eb2e8f9f7 124 #define _BURTC_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for BURTC_CTRL */
<> 144:ef7eb2e8f9f7 125 #define _BURTC_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for BURTC_CTRL */
<> 144:ef7eb2e8f9f7 126 #define _BURTC_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for BURTC_CTRL */
<> 144:ef7eb2e8f9f7 127 #define _BURTC_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for BURTC_CTRL */
<> 144:ef7eb2e8f9f7 128 #define _BURTC_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for BURTC_CTRL */
<> 144:ef7eb2e8f9f7 129 #define _BURTC_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for BURTC_CTRL */
<> 144:ef7eb2e8f9f7 130 #define _BURTC_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for BURTC_CTRL */
<> 144:ef7eb2e8f9f7 131 #define BURTC_CTRL_PRESC_DEFAULT (_BURTC_CTRL_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for BURTC_CTRL */
<> 144:ef7eb2e8f9f7 132 #define BURTC_CTRL_PRESC_DIV1 (_BURTC_CTRL_PRESC_DIV1 << 8) /**< Shifted mode DIV1 for BURTC_CTRL */
<> 144:ef7eb2e8f9f7 133 #define BURTC_CTRL_PRESC_DIV2 (_BURTC_CTRL_PRESC_DIV2 << 8) /**< Shifted mode DIV2 for BURTC_CTRL */
<> 144:ef7eb2e8f9f7 134 #define BURTC_CTRL_PRESC_DIV4 (_BURTC_CTRL_PRESC_DIV4 << 8) /**< Shifted mode DIV4 for BURTC_CTRL */
<> 144:ef7eb2e8f9f7 135 #define BURTC_CTRL_PRESC_DIV8 (_BURTC_CTRL_PRESC_DIV8 << 8) /**< Shifted mode DIV8 for BURTC_CTRL */
<> 144:ef7eb2e8f9f7 136 #define BURTC_CTRL_PRESC_DIV16 (_BURTC_CTRL_PRESC_DIV16 << 8) /**< Shifted mode DIV16 for BURTC_CTRL */
<> 144:ef7eb2e8f9f7 137 #define BURTC_CTRL_PRESC_DIV32 (_BURTC_CTRL_PRESC_DIV32 << 8) /**< Shifted mode DIV32 for BURTC_CTRL */
<> 144:ef7eb2e8f9f7 138 #define BURTC_CTRL_PRESC_DIV64 (_BURTC_CTRL_PRESC_DIV64 << 8) /**< Shifted mode DIV64 for BURTC_CTRL */
<> 144:ef7eb2e8f9f7 139 #define BURTC_CTRL_PRESC_DIV128 (_BURTC_CTRL_PRESC_DIV128 << 8) /**< Shifted mode DIV128 for BURTC_CTRL */
<> 144:ef7eb2e8f9f7 140 #define _BURTC_CTRL_CLKSEL_SHIFT 12 /**< Shift value for BURTC_CLKSEL */
<> 144:ef7eb2e8f9f7 141 #define _BURTC_CTRL_CLKSEL_MASK 0x3000UL /**< Bit mask for BURTC_CLKSEL */
<> 144:ef7eb2e8f9f7 142 #define _BURTC_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CTRL */
<> 144:ef7eb2e8f9f7 143 #define _BURTC_CTRL_CLKSEL_NONE 0x00000000UL /**< Mode NONE for BURTC_CTRL */
<> 144:ef7eb2e8f9f7 144 #define _BURTC_CTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for BURTC_CTRL */
<> 144:ef7eb2e8f9f7 145 #define _BURTC_CTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for BURTC_CTRL */
<> 144:ef7eb2e8f9f7 146 #define _BURTC_CTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for BURTC_CTRL */
<> 144:ef7eb2e8f9f7 147 #define BURTC_CTRL_CLKSEL_DEFAULT (_BURTC_CTRL_CLKSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for BURTC_CTRL */
<> 144:ef7eb2e8f9f7 148 #define BURTC_CTRL_CLKSEL_NONE (_BURTC_CTRL_CLKSEL_NONE << 12) /**< Shifted mode NONE for BURTC_CTRL */
<> 144:ef7eb2e8f9f7 149 #define BURTC_CTRL_CLKSEL_LFRCO (_BURTC_CTRL_CLKSEL_LFRCO << 12) /**< Shifted mode LFRCO for BURTC_CTRL */
<> 144:ef7eb2e8f9f7 150 #define BURTC_CTRL_CLKSEL_LFXO (_BURTC_CTRL_CLKSEL_LFXO << 12) /**< Shifted mode LFXO for BURTC_CTRL */
<> 144:ef7eb2e8f9f7 151 #define BURTC_CTRL_CLKSEL_ULFRCO (_BURTC_CTRL_CLKSEL_ULFRCO << 12) /**< Shifted mode ULFRCO for BURTC_CTRL */
<> 144:ef7eb2e8f9f7 152 #define BURTC_CTRL_BUMODETSEN (0x1UL << 14) /**< Backup mode timestamp enable */
<> 144:ef7eb2e8f9f7 153 #define _BURTC_CTRL_BUMODETSEN_SHIFT 14 /**< Shift value for BURTC_BUMODETSEN */
<> 144:ef7eb2e8f9f7 154 #define _BURTC_CTRL_BUMODETSEN_MASK 0x4000UL /**< Bit mask for BURTC_BUMODETSEN */
<> 144:ef7eb2e8f9f7 155 #define _BURTC_CTRL_BUMODETSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CTRL */
<> 144:ef7eb2e8f9f7 156 #define BURTC_CTRL_BUMODETSEN_DEFAULT (_BURTC_CTRL_BUMODETSEN_DEFAULT << 14) /**< Shifted mode DEFAULT for BURTC_CTRL */
<> 144:ef7eb2e8f9f7 157
<> 144:ef7eb2e8f9f7 158 /* Bit fields for BURTC LPMODE */
<> 144:ef7eb2e8f9f7 159 #define _BURTC_LPMODE_RESETVALUE 0x00000000UL /**< Default value for BURTC_LPMODE */
<> 144:ef7eb2e8f9f7 160 #define _BURTC_LPMODE_MASK 0x00000003UL /**< Mask for BURTC_LPMODE */
<> 144:ef7eb2e8f9f7 161 #define _BURTC_LPMODE_LPMODE_SHIFT 0 /**< Shift value for BURTC_LPMODE */
<> 144:ef7eb2e8f9f7 162 #define _BURTC_LPMODE_LPMODE_MASK 0x3UL /**< Bit mask for BURTC_LPMODE */
<> 144:ef7eb2e8f9f7 163 #define _BURTC_LPMODE_LPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_LPMODE */
<> 144:ef7eb2e8f9f7 164 #define _BURTC_LPMODE_LPMODE_DISABLE 0x00000000UL /**< Mode DISABLE for BURTC_LPMODE */
<> 144:ef7eb2e8f9f7 165 #define _BURTC_LPMODE_LPMODE_ENABLE 0x00000001UL /**< Mode ENABLE for BURTC_LPMODE */
<> 144:ef7eb2e8f9f7 166 #define _BURTC_LPMODE_LPMODE_BUEN 0x00000002UL /**< Mode BUEN for BURTC_LPMODE */
<> 144:ef7eb2e8f9f7 167 #define BURTC_LPMODE_LPMODE_DEFAULT (_BURTC_LPMODE_LPMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_LPMODE */
<> 144:ef7eb2e8f9f7 168 #define BURTC_LPMODE_LPMODE_DISABLE (_BURTC_LPMODE_LPMODE_DISABLE << 0) /**< Shifted mode DISABLE for BURTC_LPMODE */
<> 144:ef7eb2e8f9f7 169 #define BURTC_LPMODE_LPMODE_ENABLE (_BURTC_LPMODE_LPMODE_ENABLE << 0) /**< Shifted mode ENABLE for BURTC_LPMODE */
<> 144:ef7eb2e8f9f7 170 #define BURTC_LPMODE_LPMODE_BUEN (_BURTC_LPMODE_LPMODE_BUEN << 0) /**< Shifted mode BUEN for BURTC_LPMODE */
<> 144:ef7eb2e8f9f7 171
<> 144:ef7eb2e8f9f7 172 /* Bit fields for BURTC CNT */
<> 144:ef7eb2e8f9f7 173 #define _BURTC_CNT_RESETVALUE 0x00000000UL /**< Default value for BURTC_CNT */
<> 144:ef7eb2e8f9f7 174 #define _BURTC_CNT_MASK 0xFFFFFFFFUL /**< Mask for BURTC_CNT */
<> 144:ef7eb2e8f9f7 175 #define _BURTC_CNT_CNT_SHIFT 0 /**< Shift value for BURTC_CNT */
<> 144:ef7eb2e8f9f7 176 #define _BURTC_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for BURTC_CNT */
<> 144:ef7eb2e8f9f7 177 #define _BURTC_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CNT */
<> 144:ef7eb2e8f9f7 178 #define BURTC_CNT_CNT_DEFAULT (_BURTC_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_CNT */
<> 144:ef7eb2e8f9f7 179
<> 144:ef7eb2e8f9f7 180 /* Bit fields for BURTC COMP0 */
<> 144:ef7eb2e8f9f7 181 #define _BURTC_COMP0_RESETVALUE 0x00000000UL /**< Default value for BURTC_COMP0 */
<> 144:ef7eb2e8f9f7 182 #define _BURTC_COMP0_MASK 0xFFFFFFFFUL /**< Mask for BURTC_COMP0 */
<> 144:ef7eb2e8f9f7 183 #define _BURTC_COMP0_COMP0_SHIFT 0 /**< Shift value for BURTC_COMP0 */
<> 144:ef7eb2e8f9f7 184 #define _BURTC_COMP0_COMP0_MASK 0xFFFFFFFFUL /**< Bit mask for BURTC_COMP0 */
<> 144:ef7eb2e8f9f7 185 #define _BURTC_COMP0_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_COMP0 */
<> 144:ef7eb2e8f9f7 186 #define BURTC_COMP0_COMP0_DEFAULT (_BURTC_COMP0_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_COMP0 */
<> 144:ef7eb2e8f9f7 187
<> 144:ef7eb2e8f9f7 188 /* Bit fields for BURTC TIMESTAMP */
<> 144:ef7eb2e8f9f7 189 #define _BURTC_TIMESTAMP_RESETVALUE 0x00000000UL /**< Default value for BURTC_TIMESTAMP */
<> 144:ef7eb2e8f9f7 190 #define _BURTC_TIMESTAMP_MASK 0xFFFFFFFFUL /**< Mask for BURTC_TIMESTAMP */
<> 144:ef7eb2e8f9f7 191 #define _BURTC_TIMESTAMP_TIMESTAMP_SHIFT 0 /**< Shift value for BURTC_TIMESTAMP */
<> 144:ef7eb2e8f9f7 192 #define _BURTC_TIMESTAMP_TIMESTAMP_MASK 0xFFFFFFFFUL /**< Bit mask for BURTC_TIMESTAMP */
<> 144:ef7eb2e8f9f7 193 #define _BURTC_TIMESTAMP_TIMESTAMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_TIMESTAMP */
<> 144:ef7eb2e8f9f7 194 #define BURTC_TIMESTAMP_TIMESTAMP_DEFAULT (_BURTC_TIMESTAMP_TIMESTAMP_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_TIMESTAMP */
<> 144:ef7eb2e8f9f7 195
<> 144:ef7eb2e8f9f7 196 /* Bit fields for BURTC LFXOFDET */
<> 144:ef7eb2e8f9f7 197 #define _BURTC_LFXOFDET_RESETVALUE 0x00000000UL /**< Default value for BURTC_LFXOFDET */
<> 144:ef7eb2e8f9f7 198 #define _BURTC_LFXOFDET_MASK 0x000001F3UL /**< Mask for BURTC_LFXOFDET */
<> 144:ef7eb2e8f9f7 199 #define _BURTC_LFXOFDET_OSC_SHIFT 0 /**< Shift value for BURTC_OSC */
<> 144:ef7eb2e8f9f7 200 #define _BURTC_LFXOFDET_OSC_MASK 0x3UL /**< Bit mask for BURTC_OSC */
<> 144:ef7eb2e8f9f7 201 #define _BURTC_LFXOFDET_OSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_LFXOFDET */
<> 144:ef7eb2e8f9f7 202 #define _BURTC_LFXOFDET_OSC_DISABLE 0x00000000UL /**< Mode DISABLE for BURTC_LFXOFDET */
<> 144:ef7eb2e8f9f7 203 #define _BURTC_LFXOFDET_OSC_LFRCO 0x00000001UL /**< Mode LFRCO for BURTC_LFXOFDET */
<> 144:ef7eb2e8f9f7 204 #define _BURTC_LFXOFDET_OSC_ULFRCO 0x00000002UL /**< Mode ULFRCO for BURTC_LFXOFDET */
<> 144:ef7eb2e8f9f7 205 #define BURTC_LFXOFDET_OSC_DEFAULT (_BURTC_LFXOFDET_OSC_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_LFXOFDET */
<> 144:ef7eb2e8f9f7 206 #define BURTC_LFXOFDET_OSC_DISABLE (_BURTC_LFXOFDET_OSC_DISABLE << 0) /**< Shifted mode DISABLE for BURTC_LFXOFDET */
<> 144:ef7eb2e8f9f7 207 #define BURTC_LFXOFDET_OSC_LFRCO (_BURTC_LFXOFDET_OSC_LFRCO << 0) /**< Shifted mode LFRCO for BURTC_LFXOFDET */
<> 144:ef7eb2e8f9f7 208 #define BURTC_LFXOFDET_OSC_ULFRCO (_BURTC_LFXOFDET_OSC_ULFRCO << 0) /**< Shifted mode ULFRCO for BURTC_LFXOFDET */
<> 144:ef7eb2e8f9f7 209 #define _BURTC_LFXOFDET_TOP_SHIFT 4 /**< Shift value for BURTC_TOP */
<> 144:ef7eb2e8f9f7 210 #define _BURTC_LFXOFDET_TOP_MASK 0x1F0UL /**< Bit mask for BURTC_TOP */
<> 144:ef7eb2e8f9f7 211 #define _BURTC_LFXOFDET_TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_LFXOFDET */
<> 144:ef7eb2e8f9f7 212 #define BURTC_LFXOFDET_TOP_DEFAULT (_BURTC_LFXOFDET_TOP_DEFAULT << 4) /**< Shifted mode DEFAULT for BURTC_LFXOFDET */
<> 144:ef7eb2e8f9f7 213
<> 144:ef7eb2e8f9f7 214 /* Bit fields for BURTC STATUS */
<> 144:ef7eb2e8f9f7 215 #define _BURTC_STATUS_RESETVALUE 0x00000000UL /**< Default value for BURTC_STATUS */
<> 144:ef7eb2e8f9f7 216 #define _BURTC_STATUS_MASK 0x00000007UL /**< Mask for BURTC_STATUS */
<> 144:ef7eb2e8f9f7 217 #define BURTC_STATUS_LPMODEACT (0x1UL << 0) /**< Low power mode active */
<> 144:ef7eb2e8f9f7 218 #define _BURTC_STATUS_LPMODEACT_SHIFT 0 /**< Shift value for BURTC_LPMODEACT */
<> 144:ef7eb2e8f9f7 219 #define _BURTC_STATUS_LPMODEACT_MASK 0x1UL /**< Bit mask for BURTC_LPMODEACT */
<> 144:ef7eb2e8f9f7 220 #define _BURTC_STATUS_LPMODEACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_STATUS */
<> 144:ef7eb2e8f9f7 221 #define BURTC_STATUS_LPMODEACT_DEFAULT (_BURTC_STATUS_LPMODEACT_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_STATUS */
<> 144:ef7eb2e8f9f7 222 #define BURTC_STATUS_BUMODETS (0x1UL << 1) /**< Timestamp for backup mode entry stored. */
<> 144:ef7eb2e8f9f7 223 #define _BURTC_STATUS_BUMODETS_SHIFT 1 /**< Shift value for BURTC_BUMODETS */
<> 144:ef7eb2e8f9f7 224 #define _BURTC_STATUS_BUMODETS_MASK 0x2UL /**< Bit mask for BURTC_BUMODETS */
<> 144:ef7eb2e8f9f7 225 #define _BURTC_STATUS_BUMODETS_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_STATUS */
<> 144:ef7eb2e8f9f7 226 #define BURTC_STATUS_BUMODETS_DEFAULT (_BURTC_STATUS_BUMODETS_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_STATUS */
<> 144:ef7eb2e8f9f7 227 #define BURTC_STATUS_RAMWERR (0x1UL << 2) /**< RAM write error. */
<> 144:ef7eb2e8f9f7 228 #define _BURTC_STATUS_RAMWERR_SHIFT 2 /**< Shift value for BURTC_RAMWERR */
<> 144:ef7eb2e8f9f7 229 #define _BURTC_STATUS_RAMWERR_MASK 0x4UL /**< Bit mask for BURTC_RAMWERR */
<> 144:ef7eb2e8f9f7 230 #define _BURTC_STATUS_RAMWERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_STATUS */
<> 144:ef7eb2e8f9f7 231 #define BURTC_STATUS_RAMWERR_DEFAULT (_BURTC_STATUS_RAMWERR_DEFAULT << 2) /**< Shifted mode DEFAULT for BURTC_STATUS */
<> 144:ef7eb2e8f9f7 232
<> 144:ef7eb2e8f9f7 233 /* Bit fields for BURTC CMD */
<> 144:ef7eb2e8f9f7 234 #define _BURTC_CMD_RESETVALUE 0x00000000UL /**< Default value for BURTC_CMD */
<> 144:ef7eb2e8f9f7 235 #define _BURTC_CMD_MASK 0x00000001UL /**< Mask for BURTC_CMD */
<> 144:ef7eb2e8f9f7 236 #define BURTC_CMD_CLRSTATUS (0x1UL << 0) /**< Clear BURTC_STATUS register. */
<> 144:ef7eb2e8f9f7 237 #define _BURTC_CMD_CLRSTATUS_SHIFT 0 /**< Shift value for BURTC_CLRSTATUS */
<> 144:ef7eb2e8f9f7 238 #define _BURTC_CMD_CLRSTATUS_MASK 0x1UL /**< Bit mask for BURTC_CLRSTATUS */
<> 144:ef7eb2e8f9f7 239 #define _BURTC_CMD_CLRSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CMD */
<> 144:ef7eb2e8f9f7 240 #define BURTC_CMD_CLRSTATUS_DEFAULT (_BURTC_CMD_CLRSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_CMD */
<> 144:ef7eb2e8f9f7 241
<> 144:ef7eb2e8f9f7 242 /* Bit fields for BURTC POWERDOWN */
<> 144:ef7eb2e8f9f7 243 #define _BURTC_POWERDOWN_RESETVALUE 0x00000000UL /**< Default value for BURTC_POWERDOWN */
<> 144:ef7eb2e8f9f7 244 #define _BURTC_POWERDOWN_MASK 0x00000001UL /**< Mask for BURTC_POWERDOWN */
<> 144:ef7eb2e8f9f7 245 #define BURTC_POWERDOWN_RAM (0x1UL << 0) /**< Retention RAM power-down */
<> 144:ef7eb2e8f9f7 246 #define _BURTC_POWERDOWN_RAM_SHIFT 0 /**< Shift value for BURTC_RAM */
<> 144:ef7eb2e8f9f7 247 #define _BURTC_POWERDOWN_RAM_MASK 0x1UL /**< Bit mask for BURTC_RAM */
<> 144:ef7eb2e8f9f7 248 #define _BURTC_POWERDOWN_RAM_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_POWERDOWN */
<> 144:ef7eb2e8f9f7 249 #define BURTC_POWERDOWN_RAM_DEFAULT (_BURTC_POWERDOWN_RAM_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_POWERDOWN */
<> 144:ef7eb2e8f9f7 250
<> 144:ef7eb2e8f9f7 251 /* Bit fields for BURTC LOCK */
<> 144:ef7eb2e8f9f7 252 #define _BURTC_LOCK_RESETVALUE 0x00000000UL /**< Default value for BURTC_LOCK */
<> 144:ef7eb2e8f9f7 253 #define _BURTC_LOCK_MASK 0x0000FFFFUL /**< Mask for BURTC_LOCK */
<> 144:ef7eb2e8f9f7 254 #define _BURTC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for BURTC_LOCKKEY */
<> 144:ef7eb2e8f9f7 255 #define _BURTC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for BURTC_LOCKKEY */
<> 144:ef7eb2e8f9f7 256 #define _BURTC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_LOCK */
<> 144:ef7eb2e8f9f7 257 #define _BURTC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for BURTC_LOCK */
<> 144:ef7eb2e8f9f7 258 #define _BURTC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for BURTC_LOCK */
<> 144:ef7eb2e8f9f7 259 #define _BURTC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for BURTC_LOCK */
<> 144:ef7eb2e8f9f7 260 #define _BURTC_LOCK_LOCKKEY_UNLOCK 0x0000AEE8UL /**< Mode UNLOCK for BURTC_LOCK */
<> 144:ef7eb2e8f9f7 261 #define BURTC_LOCK_LOCKKEY_DEFAULT (_BURTC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_LOCK */
<> 144:ef7eb2e8f9f7 262 #define BURTC_LOCK_LOCKKEY_LOCK (_BURTC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for BURTC_LOCK */
<> 144:ef7eb2e8f9f7 263 #define BURTC_LOCK_LOCKKEY_UNLOCKED (_BURTC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for BURTC_LOCK */
<> 144:ef7eb2e8f9f7 264 #define BURTC_LOCK_LOCKKEY_LOCKED (_BURTC_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for BURTC_LOCK */
<> 144:ef7eb2e8f9f7 265 #define BURTC_LOCK_LOCKKEY_UNLOCK (_BURTC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for BURTC_LOCK */
<> 144:ef7eb2e8f9f7 266
<> 144:ef7eb2e8f9f7 267 /* Bit fields for BURTC IF */
<> 144:ef7eb2e8f9f7 268 #define _BURTC_IF_RESETVALUE 0x00000000UL /**< Default value for BURTC_IF */
<> 144:ef7eb2e8f9f7 269 #define _BURTC_IF_MASK 0x00000007UL /**< Mask for BURTC_IF */
<> 144:ef7eb2e8f9f7 270 #define BURTC_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */
<> 144:ef7eb2e8f9f7 271 #define _BURTC_IF_OF_SHIFT 0 /**< Shift value for BURTC_OF */
<> 144:ef7eb2e8f9f7 272 #define _BURTC_IF_OF_MASK 0x1UL /**< Bit mask for BURTC_OF */
<> 144:ef7eb2e8f9f7 273 #define _BURTC_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IF */
<> 144:ef7eb2e8f9f7 274 #define BURTC_IF_OF_DEFAULT (_BURTC_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_IF */
<> 144:ef7eb2e8f9f7 275 #define BURTC_IF_COMP0 (0x1UL << 1) /**< Compare match Interrupt Flag */
<> 144:ef7eb2e8f9f7 276 #define _BURTC_IF_COMP0_SHIFT 1 /**< Shift value for BURTC_COMP0 */
<> 144:ef7eb2e8f9f7 277 #define _BURTC_IF_COMP0_MASK 0x2UL /**< Bit mask for BURTC_COMP0 */
<> 144:ef7eb2e8f9f7 278 #define _BURTC_IF_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IF */
<> 144:ef7eb2e8f9f7 279 #define BURTC_IF_COMP0_DEFAULT (_BURTC_IF_COMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_IF */
<> 144:ef7eb2e8f9f7 280 #define BURTC_IF_LFXOFAIL (0x1UL << 2) /**< LFXO failure Interrupt Flag */
<> 144:ef7eb2e8f9f7 281 #define _BURTC_IF_LFXOFAIL_SHIFT 2 /**< Shift value for BURTC_LFXOFAIL */
<> 144:ef7eb2e8f9f7 282 #define _BURTC_IF_LFXOFAIL_MASK 0x4UL /**< Bit mask for BURTC_LFXOFAIL */
<> 144:ef7eb2e8f9f7 283 #define _BURTC_IF_LFXOFAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IF */
<> 144:ef7eb2e8f9f7 284 #define BURTC_IF_LFXOFAIL_DEFAULT (_BURTC_IF_LFXOFAIL_DEFAULT << 2) /**< Shifted mode DEFAULT for BURTC_IF */
<> 144:ef7eb2e8f9f7 285
<> 144:ef7eb2e8f9f7 286 /* Bit fields for BURTC IFS */
<> 144:ef7eb2e8f9f7 287 #define _BURTC_IFS_RESETVALUE 0x00000000UL /**< Default value for BURTC_IFS */
<> 144:ef7eb2e8f9f7 288 #define _BURTC_IFS_MASK 0x00000007UL /**< Mask for BURTC_IFS */
<> 144:ef7eb2e8f9f7 289 #define BURTC_IFS_OF (0x1UL << 0) /**< Set Overflow Interrupt Flag */
<> 144:ef7eb2e8f9f7 290 #define _BURTC_IFS_OF_SHIFT 0 /**< Shift value for BURTC_OF */
<> 144:ef7eb2e8f9f7 291 #define _BURTC_IFS_OF_MASK 0x1UL /**< Bit mask for BURTC_OF */
<> 144:ef7eb2e8f9f7 292 #define _BURTC_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IFS */
<> 144:ef7eb2e8f9f7 293 #define BURTC_IFS_OF_DEFAULT (_BURTC_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_IFS */
<> 144:ef7eb2e8f9f7 294 #define BURTC_IFS_COMP0 (0x1UL << 1) /**< Set compare match Interrupt Flag */
<> 144:ef7eb2e8f9f7 295 #define _BURTC_IFS_COMP0_SHIFT 1 /**< Shift value for BURTC_COMP0 */
<> 144:ef7eb2e8f9f7 296 #define _BURTC_IFS_COMP0_MASK 0x2UL /**< Bit mask for BURTC_COMP0 */
<> 144:ef7eb2e8f9f7 297 #define _BURTC_IFS_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IFS */
<> 144:ef7eb2e8f9f7 298 #define BURTC_IFS_COMP0_DEFAULT (_BURTC_IFS_COMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_IFS */
<> 144:ef7eb2e8f9f7 299 #define BURTC_IFS_LFXOFAIL (0x1UL << 2) /**< Set LFXO fail Interrupt Flag */
<> 144:ef7eb2e8f9f7 300 #define _BURTC_IFS_LFXOFAIL_SHIFT 2 /**< Shift value for BURTC_LFXOFAIL */
<> 144:ef7eb2e8f9f7 301 #define _BURTC_IFS_LFXOFAIL_MASK 0x4UL /**< Bit mask for BURTC_LFXOFAIL */
<> 144:ef7eb2e8f9f7 302 #define _BURTC_IFS_LFXOFAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IFS */
<> 144:ef7eb2e8f9f7 303 #define BURTC_IFS_LFXOFAIL_DEFAULT (_BURTC_IFS_LFXOFAIL_DEFAULT << 2) /**< Shifted mode DEFAULT for BURTC_IFS */
<> 144:ef7eb2e8f9f7 304
<> 144:ef7eb2e8f9f7 305 /* Bit fields for BURTC IFC */
<> 144:ef7eb2e8f9f7 306 #define _BURTC_IFC_RESETVALUE 0x00000000UL /**< Default value for BURTC_IFC */
<> 144:ef7eb2e8f9f7 307 #define _BURTC_IFC_MASK 0x00000007UL /**< Mask for BURTC_IFC */
<> 144:ef7eb2e8f9f7 308 #define BURTC_IFC_OF (0x1UL << 0) /**< Clear Overflow Interrupt Flag */
<> 144:ef7eb2e8f9f7 309 #define _BURTC_IFC_OF_SHIFT 0 /**< Shift value for BURTC_OF */
<> 144:ef7eb2e8f9f7 310 #define _BURTC_IFC_OF_MASK 0x1UL /**< Bit mask for BURTC_OF */
<> 144:ef7eb2e8f9f7 311 #define _BURTC_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IFC */
<> 144:ef7eb2e8f9f7 312 #define BURTC_IFC_OF_DEFAULT (_BURTC_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_IFC */
<> 144:ef7eb2e8f9f7 313 #define BURTC_IFC_COMP0 (0x1UL << 1) /**< Clear compare match Interrupt Flag */
<> 144:ef7eb2e8f9f7 314 #define _BURTC_IFC_COMP0_SHIFT 1 /**< Shift value for BURTC_COMP0 */
<> 144:ef7eb2e8f9f7 315 #define _BURTC_IFC_COMP0_MASK 0x2UL /**< Bit mask for BURTC_COMP0 */
<> 144:ef7eb2e8f9f7 316 #define _BURTC_IFC_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IFC */
<> 144:ef7eb2e8f9f7 317 #define BURTC_IFC_COMP0_DEFAULT (_BURTC_IFC_COMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_IFC */
<> 144:ef7eb2e8f9f7 318 #define BURTC_IFC_LFXOFAIL (0x1UL << 2) /**< Clear LFXO failure Interrupt Flag */
<> 144:ef7eb2e8f9f7 319 #define _BURTC_IFC_LFXOFAIL_SHIFT 2 /**< Shift value for BURTC_LFXOFAIL */
<> 144:ef7eb2e8f9f7 320 #define _BURTC_IFC_LFXOFAIL_MASK 0x4UL /**< Bit mask for BURTC_LFXOFAIL */
<> 144:ef7eb2e8f9f7 321 #define _BURTC_IFC_LFXOFAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IFC */
<> 144:ef7eb2e8f9f7 322 #define BURTC_IFC_LFXOFAIL_DEFAULT (_BURTC_IFC_LFXOFAIL_DEFAULT << 2) /**< Shifted mode DEFAULT for BURTC_IFC */
<> 144:ef7eb2e8f9f7 323
<> 144:ef7eb2e8f9f7 324 /* Bit fields for BURTC IEN */
<> 144:ef7eb2e8f9f7 325 #define _BURTC_IEN_RESETVALUE 0x00000000UL /**< Default value for BURTC_IEN */
<> 144:ef7eb2e8f9f7 326 #define _BURTC_IEN_MASK 0x00000007UL /**< Mask for BURTC_IEN */
<> 144:ef7eb2e8f9f7 327 #define BURTC_IEN_OF (0x1UL << 0) /**< Overflow Interrupt Enable */
<> 144:ef7eb2e8f9f7 328 #define _BURTC_IEN_OF_SHIFT 0 /**< Shift value for BURTC_OF */
<> 144:ef7eb2e8f9f7 329 #define _BURTC_IEN_OF_MASK 0x1UL /**< Bit mask for BURTC_OF */
<> 144:ef7eb2e8f9f7 330 #define _BURTC_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IEN */
<> 144:ef7eb2e8f9f7 331 #define BURTC_IEN_OF_DEFAULT (_BURTC_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_IEN */
<> 144:ef7eb2e8f9f7 332 #define BURTC_IEN_COMP0 (0x1UL << 1) /**< Compare match Interrupt Enable */
<> 144:ef7eb2e8f9f7 333 #define _BURTC_IEN_COMP0_SHIFT 1 /**< Shift value for BURTC_COMP0 */
<> 144:ef7eb2e8f9f7 334 #define _BURTC_IEN_COMP0_MASK 0x2UL /**< Bit mask for BURTC_COMP0 */
<> 144:ef7eb2e8f9f7 335 #define _BURTC_IEN_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IEN */
<> 144:ef7eb2e8f9f7 336 #define BURTC_IEN_COMP0_DEFAULT (_BURTC_IEN_COMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_IEN */
<> 144:ef7eb2e8f9f7 337 #define BURTC_IEN_LFXOFAIL (0x1UL << 2) /**< LFXO failure Interrupt Enable */
<> 144:ef7eb2e8f9f7 338 #define _BURTC_IEN_LFXOFAIL_SHIFT 2 /**< Shift value for BURTC_LFXOFAIL */
<> 144:ef7eb2e8f9f7 339 #define _BURTC_IEN_LFXOFAIL_MASK 0x4UL /**< Bit mask for BURTC_LFXOFAIL */
<> 144:ef7eb2e8f9f7 340 #define _BURTC_IEN_LFXOFAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IEN */
<> 144:ef7eb2e8f9f7 341 #define BURTC_IEN_LFXOFAIL_DEFAULT (_BURTC_IEN_LFXOFAIL_DEFAULT << 2) /**< Shifted mode DEFAULT for BURTC_IEN */
<> 144:ef7eb2e8f9f7 342
<> 144:ef7eb2e8f9f7 343 /* Bit fields for BURTC FREEZE */
<> 144:ef7eb2e8f9f7 344 #define _BURTC_FREEZE_RESETVALUE 0x00000000UL /**< Default value for BURTC_FREEZE */
<> 144:ef7eb2e8f9f7 345 #define _BURTC_FREEZE_MASK 0x00000001UL /**< Mask for BURTC_FREEZE */
<> 144:ef7eb2e8f9f7 346 #define BURTC_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */
<> 144:ef7eb2e8f9f7 347 #define _BURTC_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for BURTC_REGFREEZE */
<> 144:ef7eb2e8f9f7 348 #define _BURTC_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for BURTC_REGFREEZE */
<> 144:ef7eb2e8f9f7 349 #define _BURTC_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_FREEZE */
<> 144:ef7eb2e8f9f7 350 #define _BURTC_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for BURTC_FREEZE */
<> 144:ef7eb2e8f9f7 351 #define _BURTC_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for BURTC_FREEZE */
<> 144:ef7eb2e8f9f7 352 #define BURTC_FREEZE_REGFREEZE_DEFAULT (_BURTC_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_FREEZE */
<> 144:ef7eb2e8f9f7 353 #define BURTC_FREEZE_REGFREEZE_UPDATE (_BURTC_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for BURTC_FREEZE */
<> 144:ef7eb2e8f9f7 354 #define BURTC_FREEZE_REGFREEZE_FREEZE (_BURTC_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for BURTC_FREEZE */
<> 144:ef7eb2e8f9f7 355
<> 144:ef7eb2e8f9f7 356 /* Bit fields for BURTC SYNCBUSY */
<> 144:ef7eb2e8f9f7 357 #define _BURTC_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for BURTC_SYNCBUSY */
<> 144:ef7eb2e8f9f7 358 #define _BURTC_SYNCBUSY_MASK 0x00000003UL /**< Mask for BURTC_SYNCBUSY */
<> 144:ef7eb2e8f9f7 359 #define BURTC_SYNCBUSY_LPMODE (0x1UL << 0) /**< LPMODE Register Busy */
<> 144:ef7eb2e8f9f7 360 #define _BURTC_SYNCBUSY_LPMODE_SHIFT 0 /**< Shift value for BURTC_LPMODE */
<> 144:ef7eb2e8f9f7 361 #define _BURTC_SYNCBUSY_LPMODE_MASK 0x1UL /**< Bit mask for BURTC_LPMODE */
<> 144:ef7eb2e8f9f7 362 #define _BURTC_SYNCBUSY_LPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */
<> 144:ef7eb2e8f9f7 363 #define BURTC_SYNCBUSY_LPMODE_DEFAULT (_BURTC_SYNCBUSY_LPMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */
<> 144:ef7eb2e8f9f7 364 #define BURTC_SYNCBUSY_COMP0 (0x1UL << 1) /**< COMP0 Register Busy */
<> 144:ef7eb2e8f9f7 365 #define _BURTC_SYNCBUSY_COMP0_SHIFT 1 /**< Shift value for BURTC_COMP0 */
<> 144:ef7eb2e8f9f7 366 #define _BURTC_SYNCBUSY_COMP0_MASK 0x2UL /**< Bit mask for BURTC_COMP0 */
<> 144:ef7eb2e8f9f7 367 #define _BURTC_SYNCBUSY_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */
<> 144:ef7eb2e8f9f7 368 #define BURTC_SYNCBUSY_COMP0_DEFAULT (_BURTC_SYNCBUSY_COMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */
<> 144:ef7eb2e8f9f7 369
<> 144:ef7eb2e8f9f7 370 /* Bit fields for BURTC RET_REG */
<> 144:ef7eb2e8f9f7 371 #define _BURTC_RET_REG_RESETVALUE 0x00000000UL /**< Default value for BURTC_RET_REG */
<> 144:ef7eb2e8f9f7 372 #define _BURTC_RET_REG_MASK 0xFFFFFFFFUL /**< Mask for BURTC_RET_REG */
<> 144:ef7eb2e8f9f7 373 #define _BURTC_RET_REG_REG_SHIFT 0 /**< Shift value for REG */
<> 144:ef7eb2e8f9f7 374 #define _BURTC_RET_REG_REG_MASK 0xFFFFFFFFUL /**< Bit mask for REG */
<> 144:ef7eb2e8f9f7 375 #define _BURTC_RET_REG_REG_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_RET_REG */
<> 144:ef7eb2e8f9f7 376 #define BURTC_RET_REG_REG_DEFAULT (_BURTC_RET_REG_REG_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_RET_REG */
<> 144:ef7eb2e8f9f7 377
<> 144:ef7eb2e8f9f7 378 /** @} End of group EFM32GG_BURTC */
<> 144:ef7eb2e8f9f7 379 /** @} End of group Parts */
<> 144:ef7eb2e8f9f7 380