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mbed official
targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_osc32kctrl.h@18:da299f395b9e, 2015-11-09 (annotated)
- Committer:
- mbed_official
- Date:
- Mon Nov 09 13:30:11 2015 +0000
- Revision:
- 18:da299f395b9e
Synchronized with git revision f605825f66bb2e462ff7dbc5fb4ed2dbe979d1c3
Full URL: https://github.com/mbedmicro/mbed/commit/f605825f66bb2e462ff7dbc5fb4ed2dbe979d1c3/
Added support for SAML21
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 18:da299f395b9e | 1 | /** |
| mbed_official | 18:da299f395b9e | 2 | * \file |
| mbed_official | 18:da299f395b9e | 3 | * |
| mbed_official | 18:da299f395b9e | 4 | * \brief Component description for OSC32KCTRL |
| mbed_official | 18:da299f395b9e | 5 | * |
| mbed_official | 18:da299f395b9e | 6 | * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. |
| mbed_official | 18:da299f395b9e | 7 | * |
| mbed_official | 18:da299f395b9e | 8 | * \asf_license_start |
| mbed_official | 18:da299f395b9e | 9 | * |
| mbed_official | 18:da299f395b9e | 10 | * \page License |
| mbed_official | 18:da299f395b9e | 11 | * |
| mbed_official | 18:da299f395b9e | 12 | * Redistribution and use in source and binary forms, with or without |
| mbed_official | 18:da299f395b9e | 13 | * modification, are permitted provided that the following conditions are met: |
| mbed_official | 18:da299f395b9e | 14 | * |
| mbed_official | 18:da299f395b9e | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
| mbed_official | 18:da299f395b9e | 16 | * this list of conditions and the following disclaimer. |
| mbed_official | 18:da299f395b9e | 17 | * |
| mbed_official | 18:da299f395b9e | 18 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| mbed_official | 18:da299f395b9e | 19 | * this list of conditions and the following disclaimer in the documentation |
| mbed_official | 18:da299f395b9e | 20 | * and/or other materials provided with the distribution. |
| mbed_official | 18:da299f395b9e | 21 | * |
| mbed_official | 18:da299f395b9e | 22 | * 3. The name of Atmel may not be used to endorse or promote products derived |
| mbed_official | 18:da299f395b9e | 23 | * from this software without specific prior written permission. |
| mbed_official | 18:da299f395b9e | 24 | * |
| mbed_official | 18:da299f395b9e | 25 | * 4. This software may only be redistributed and used in connection with an |
| mbed_official | 18:da299f395b9e | 26 | * Atmel microcontroller product. |
| mbed_official | 18:da299f395b9e | 27 | * |
| mbed_official | 18:da299f395b9e | 28 | * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED |
| mbed_official | 18:da299f395b9e | 29 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| mbed_official | 18:da299f395b9e | 30 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE |
| mbed_official | 18:da299f395b9e | 31 | * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR |
| mbed_official | 18:da299f395b9e | 32 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| mbed_official | 18:da299f395b9e | 33 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
| mbed_official | 18:da299f395b9e | 34 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
| mbed_official | 18:da299f395b9e | 35 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, |
| mbed_official | 18:da299f395b9e | 36 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN |
| mbed_official | 18:da299f395b9e | 37 | * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| mbed_official | 18:da299f395b9e | 38 | * POSSIBILITY OF SUCH DAMAGE. |
| mbed_official | 18:da299f395b9e | 39 | * |
| mbed_official | 18:da299f395b9e | 40 | * \asf_license_stop |
| mbed_official | 18:da299f395b9e | 41 | * |
| mbed_official | 18:da299f395b9e | 42 | */ |
| mbed_official | 18:da299f395b9e | 43 | /* |
| mbed_official | 18:da299f395b9e | 44 | * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> |
| mbed_official | 18:da299f395b9e | 45 | */ |
| mbed_official | 18:da299f395b9e | 46 | |
| mbed_official | 18:da299f395b9e | 47 | #ifndef _SAML21_OSC32KCTRL_COMPONENT_ |
| mbed_official | 18:da299f395b9e | 48 | #define _SAML21_OSC32KCTRL_COMPONENT_ |
| mbed_official | 18:da299f395b9e | 49 | |
| mbed_official | 18:da299f395b9e | 50 | /* ========================================================================== */ |
| mbed_official | 18:da299f395b9e | 51 | /** SOFTWARE API DEFINITION FOR OSC32KCTRL */ |
| mbed_official | 18:da299f395b9e | 52 | /* ========================================================================== */ |
| mbed_official | 18:da299f395b9e | 53 | /** \addtogroup SAML21_OSC32KCTRL 32k Oscillators Control */ |
| mbed_official | 18:da299f395b9e | 54 | /*@{*/ |
| mbed_official | 18:da299f395b9e | 55 | |
| mbed_official | 18:da299f395b9e | 56 | #define OSC32KCTRL_U2246 |
| mbed_official | 18:da299f395b9e | 57 | #define REV_OSC32KCTRL 0x110 |
| mbed_official | 18:da299f395b9e | 58 | |
| mbed_official | 18:da299f395b9e | 59 | /* -------- OSC32KCTRL_INTENCLR : (OSC32KCTRL Offset: 0x00) (R/W 32) Interrupt Enable Clear -------- */ |
| mbed_official | 18:da299f395b9e | 60 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 18:da299f395b9e | 61 | typedef union { |
| mbed_official | 18:da299f395b9e | 62 | struct { |
| mbed_official | 18:da299f395b9e | 63 | uint32_t XOSC32KRDY:1; /*!< bit: 0 XOSC32K Ready Interrupt Enable */ |
| mbed_official | 18:da299f395b9e | 64 | uint32_t OSC32KRDY:1; /*!< bit: 1 OSC32K Ready Interrupt Enable */ |
| mbed_official | 18:da299f395b9e | 65 | uint32_t :30; /*!< bit: 2..31 Reserved */ |
| mbed_official | 18:da299f395b9e | 66 | } bit; /*!< Structure used for bit access */ |
| mbed_official | 18:da299f395b9e | 67 | uint32_t reg; /*!< Type used for register access */ |
| mbed_official | 18:da299f395b9e | 68 | } OSC32KCTRL_INTENCLR_Type; |
| mbed_official | 18:da299f395b9e | 69 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 18:da299f395b9e | 70 | |
| mbed_official | 18:da299f395b9e | 71 | #define OSC32KCTRL_INTENCLR_OFFSET 0x00 /**< \brief (OSC32KCTRL_INTENCLR offset) Interrupt Enable Clear */ |
| mbed_official | 18:da299f395b9e | 72 | #define OSC32KCTRL_INTENCLR_RESETVALUE 0x00000000ul /**< \brief (OSC32KCTRL_INTENCLR reset_value) Interrupt Enable Clear */ |
| mbed_official | 18:da299f395b9e | 73 | |
| mbed_official | 18:da299f395b9e | 74 | #define OSC32KCTRL_INTENCLR_XOSC32KRDY_Pos 0 /**< \brief (OSC32KCTRL_INTENCLR) XOSC32K Ready Interrupt Enable */ |
| mbed_official | 18:da299f395b9e | 75 | #define OSC32KCTRL_INTENCLR_XOSC32KRDY (0x1ul << OSC32KCTRL_INTENCLR_XOSC32KRDY_Pos) |
| mbed_official | 18:da299f395b9e | 76 | #define OSC32KCTRL_INTENCLR_OSC32KRDY_Pos 1 /**< \brief (OSC32KCTRL_INTENCLR) OSC32K Ready Interrupt Enable */ |
| mbed_official | 18:da299f395b9e | 77 | #define OSC32KCTRL_INTENCLR_OSC32KRDY (0x1ul << OSC32KCTRL_INTENCLR_OSC32KRDY_Pos) |
| mbed_official | 18:da299f395b9e | 78 | #define OSC32KCTRL_INTENCLR_MASK 0x00000003ul /**< \brief (OSC32KCTRL_INTENCLR) MASK Register */ |
| mbed_official | 18:da299f395b9e | 79 | |
| mbed_official | 18:da299f395b9e | 80 | /* -------- OSC32KCTRL_INTENSET : (OSC32KCTRL Offset: 0x04) (R/W 32) Interrupt Enable Set -------- */ |
| mbed_official | 18:da299f395b9e | 81 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 18:da299f395b9e | 82 | typedef union { |
| mbed_official | 18:da299f395b9e | 83 | struct { |
| mbed_official | 18:da299f395b9e | 84 | uint32_t XOSC32KRDY:1; /*!< bit: 0 XOSC32K Ready Interrupt Enable */ |
| mbed_official | 18:da299f395b9e | 85 | uint32_t OSC32KRDY:1; /*!< bit: 1 OSC32K Ready Interrupt Enable */ |
| mbed_official | 18:da299f395b9e | 86 | uint32_t :30; /*!< bit: 2..31 Reserved */ |
| mbed_official | 18:da299f395b9e | 87 | } bit; /*!< Structure used for bit access */ |
| mbed_official | 18:da299f395b9e | 88 | uint32_t reg; /*!< Type used for register access */ |
| mbed_official | 18:da299f395b9e | 89 | } OSC32KCTRL_INTENSET_Type; |
| mbed_official | 18:da299f395b9e | 90 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 18:da299f395b9e | 91 | |
| mbed_official | 18:da299f395b9e | 92 | #define OSC32KCTRL_INTENSET_OFFSET 0x04 /**< \brief (OSC32KCTRL_INTENSET offset) Interrupt Enable Set */ |
| mbed_official | 18:da299f395b9e | 93 | #define OSC32KCTRL_INTENSET_RESETVALUE 0x00000000ul /**< \brief (OSC32KCTRL_INTENSET reset_value) Interrupt Enable Set */ |
| mbed_official | 18:da299f395b9e | 94 | |
| mbed_official | 18:da299f395b9e | 95 | #define OSC32KCTRL_INTENSET_XOSC32KRDY_Pos 0 /**< \brief (OSC32KCTRL_INTENSET) XOSC32K Ready Interrupt Enable */ |
| mbed_official | 18:da299f395b9e | 96 | #define OSC32KCTRL_INTENSET_XOSC32KRDY (0x1ul << OSC32KCTRL_INTENSET_XOSC32KRDY_Pos) |
| mbed_official | 18:da299f395b9e | 97 | #define OSC32KCTRL_INTENSET_OSC32KRDY_Pos 1 /**< \brief (OSC32KCTRL_INTENSET) OSC32K Ready Interrupt Enable */ |
| mbed_official | 18:da299f395b9e | 98 | #define OSC32KCTRL_INTENSET_OSC32KRDY (0x1ul << OSC32KCTRL_INTENSET_OSC32KRDY_Pos) |
| mbed_official | 18:da299f395b9e | 99 | #define OSC32KCTRL_INTENSET_MASK 0x00000003ul /**< \brief (OSC32KCTRL_INTENSET) MASK Register */ |
| mbed_official | 18:da299f395b9e | 100 | |
| mbed_official | 18:da299f395b9e | 101 | /* -------- OSC32KCTRL_INTFLAG : (OSC32KCTRL Offset: 0x08) (R/W 32) Interrupt Flag Status and Clear -------- */ |
| mbed_official | 18:da299f395b9e | 102 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 18:da299f395b9e | 103 | typedef union { |
| mbed_official | 18:da299f395b9e | 104 | struct { |
| mbed_official | 18:da299f395b9e | 105 | uint32_t XOSC32KRDY:1; /*!< bit: 0 XOSC32K Ready */ |
| mbed_official | 18:da299f395b9e | 106 | uint32_t OSC32KRDY:1; /*!< bit: 1 OSC32K Ready */ |
| mbed_official | 18:da299f395b9e | 107 | uint32_t :30; /*!< bit: 2..31 Reserved */ |
| mbed_official | 18:da299f395b9e | 108 | } bit; /*!< Structure used for bit access */ |
| mbed_official | 18:da299f395b9e | 109 | uint32_t reg; /*!< Type used for register access */ |
| mbed_official | 18:da299f395b9e | 110 | } OSC32KCTRL_INTFLAG_Type; |
| mbed_official | 18:da299f395b9e | 111 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 18:da299f395b9e | 112 | |
| mbed_official | 18:da299f395b9e | 113 | #define OSC32KCTRL_INTFLAG_OFFSET 0x08 /**< \brief (OSC32KCTRL_INTFLAG offset) Interrupt Flag Status and Clear */ |
| mbed_official | 18:da299f395b9e | 114 | #define OSC32KCTRL_INTFLAG_RESETVALUE 0x00000000ul /**< \brief (OSC32KCTRL_INTFLAG reset_value) Interrupt Flag Status and Clear */ |
| mbed_official | 18:da299f395b9e | 115 | |
| mbed_official | 18:da299f395b9e | 116 | #define OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos 0 /**< \brief (OSC32KCTRL_INTFLAG) XOSC32K Ready */ |
| mbed_official | 18:da299f395b9e | 117 | #define OSC32KCTRL_INTFLAG_XOSC32KRDY (0x1ul << OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos) |
| mbed_official | 18:da299f395b9e | 118 | #define OSC32KCTRL_INTFLAG_OSC32KRDY_Pos 1 /**< \brief (OSC32KCTRL_INTFLAG) OSC32K Ready */ |
| mbed_official | 18:da299f395b9e | 119 | #define OSC32KCTRL_INTFLAG_OSC32KRDY (0x1ul << OSC32KCTRL_INTFLAG_OSC32KRDY_Pos) |
| mbed_official | 18:da299f395b9e | 120 | #define OSC32KCTRL_INTFLAG_MASK 0x00000003ul /**< \brief (OSC32KCTRL_INTFLAG) MASK Register */ |
| mbed_official | 18:da299f395b9e | 121 | |
| mbed_official | 18:da299f395b9e | 122 | /* -------- OSC32KCTRL_STATUS : (OSC32KCTRL Offset: 0x0C) (R/ 32) Power and Clocks Status -------- */ |
| mbed_official | 18:da299f395b9e | 123 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 18:da299f395b9e | 124 | typedef union { |
| mbed_official | 18:da299f395b9e | 125 | struct { |
| mbed_official | 18:da299f395b9e | 126 | uint32_t XOSC32KRDY:1; /*!< bit: 0 XOSC32K Ready */ |
| mbed_official | 18:da299f395b9e | 127 | uint32_t OSC32KRDY:1; /*!< bit: 1 OSC32K Ready */ |
| mbed_official | 18:da299f395b9e | 128 | uint32_t :30; /*!< bit: 2..31 Reserved */ |
| mbed_official | 18:da299f395b9e | 129 | } bit; /*!< Structure used for bit access */ |
| mbed_official | 18:da299f395b9e | 130 | uint32_t reg; /*!< Type used for register access */ |
| mbed_official | 18:da299f395b9e | 131 | } OSC32KCTRL_STATUS_Type; |
| mbed_official | 18:da299f395b9e | 132 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 18:da299f395b9e | 133 | |
| mbed_official | 18:da299f395b9e | 134 | #define OSC32KCTRL_STATUS_OFFSET 0x0C /**< \brief (OSC32KCTRL_STATUS offset) Power and Clocks Status */ |
| mbed_official | 18:da299f395b9e | 135 | #define OSC32KCTRL_STATUS_RESETVALUE 0x00000000ul /**< \brief (OSC32KCTRL_STATUS reset_value) Power and Clocks Status */ |
| mbed_official | 18:da299f395b9e | 136 | |
| mbed_official | 18:da299f395b9e | 137 | #define OSC32KCTRL_STATUS_XOSC32KRDY_Pos 0 /**< \brief (OSC32KCTRL_STATUS) XOSC32K Ready */ |
| mbed_official | 18:da299f395b9e | 138 | #define OSC32KCTRL_STATUS_XOSC32KRDY (0x1ul << OSC32KCTRL_STATUS_XOSC32KRDY_Pos) |
| mbed_official | 18:da299f395b9e | 139 | #define OSC32KCTRL_STATUS_OSC32KRDY_Pos 1 /**< \brief (OSC32KCTRL_STATUS) OSC32K Ready */ |
| mbed_official | 18:da299f395b9e | 140 | #define OSC32KCTRL_STATUS_OSC32KRDY (0x1ul << OSC32KCTRL_STATUS_OSC32KRDY_Pos) |
| mbed_official | 18:da299f395b9e | 141 | #define OSC32KCTRL_STATUS_MASK 0x00000003ul /**< \brief (OSC32KCTRL_STATUS) MASK Register */ |
| mbed_official | 18:da299f395b9e | 142 | |
| mbed_official | 18:da299f395b9e | 143 | /* -------- OSC32KCTRL_RTCCTRL : (OSC32KCTRL Offset: 0x10) (R/W 32) Clock selection -------- */ |
| mbed_official | 18:da299f395b9e | 144 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 18:da299f395b9e | 145 | typedef union { |
| mbed_official | 18:da299f395b9e | 146 | struct { |
| mbed_official | 18:da299f395b9e | 147 | uint32_t RTCSEL:3; /*!< bit: 0.. 2 RTC Clock Selection */ |
| mbed_official | 18:da299f395b9e | 148 | uint32_t :29; /*!< bit: 3..31 Reserved */ |
| mbed_official | 18:da299f395b9e | 149 | } bit; /*!< Structure used for bit access */ |
| mbed_official | 18:da299f395b9e | 150 | uint32_t reg; /*!< Type used for register access */ |
| mbed_official | 18:da299f395b9e | 151 | } OSC32KCTRL_RTCCTRL_Type; |
| mbed_official | 18:da299f395b9e | 152 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 18:da299f395b9e | 153 | |
| mbed_official | 18:da299f395b9e | 154 | #define OSC32KCTRL_RTCCTRL_OFFSET 0x10 /**< \brief (OSC32KCTRL_RTCCTRL offset) Clock selection */ |
| mbed_official | 18:da299f395b9e | 155 | #define OSC32KCTRL_RTCCTRL_RESETVALUE 0x00000000ul /**< \brief (OSC32KCTRL_RTCCTRL reset_value) Clock selection */ |
| mbed_official | 18:da299f395b9e | 156 | |
| mbed_official | 18:da299f395b9e | 157 | #define OSC32KCTRL_RTCCTRL_RTCSEL_Pos 0 /**< \brief (OSC32KCTRL_RTCCTRL) RTC Clock Selection */ |
| mbed_official | 18:da299f395b9e | 158 | #define OSC32KCTRL_RTCCTRL_RTCSEL_Msk (0x7ul << OSC32KCTRL_RTCCTRL_RTCSEL_Pos) |
| mbed_official | 18:da299f395b9e | 159 | #define OSC32KCTRL_RTCCTRL_RTCSEL(value) ((OSC32KCTRL_RTCCTRL_RTCSEL_Msk & ((value) << OSC32KCTRL_RTCCTRL_RTCSEL_Pos))) |
| mbed_official | 18:da299f395b9e | 160 | #define OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val 0x0ul /**< \brief (OSC32KCTRL_RTCCTRL) 1.024kHz from 32kHz internal ULP oscillator */ |
| mbed_official | 18:da299f395b9e | 161 | #define OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val 0x1ul /**< \brief (OSC32KCTRL_RTCCTRL) 32.768kHz from 32kHz internal ULP oscillator */ |
| mbed_official | 18:da299f395b9e | 162 | #define OSC32KCTRL_RTCCTRL_RTCSEL_OSC1K_Val 0x2ul /**< \brief (OSC32KCTRL_RTCCTRL) 1.024kHz from 32.768kHz internal oscillator */ |
| mbed_official | 18:da299f395b9e | 163 | #define OSC32KCTRL_RTCCTRL_RTCSEL_OSC32K_Val 0x3ul /**< \brief (OSC32KCTRL_RTCCTRL) 32.768kHz from 32.768kHz internal oscillator */ |
| mbed_official | 18:da299f395b9e | 164 | #define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val 0x4ul /**< \brief (OSC32KCTRL_RTCCTRL) 1.024kHz from 32.768kHz internal oscillator */ |
| mbed_official | 18:da299f395b9e | 165 | #define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val 0x5ul /**< \brief (OSC32KCTRL_RTCCTRL) 32.768kHz from 32.768kHz external crystal oscillator */ |
| mbed_official | 18:da299f395b9e | 166 | #define OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K (OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos) |
| mbed_official | 18:da299f395b9e | 167 | #define OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K (OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos) |
| mbed_official | 18:da299f395b9e | 168 | #define OSC32KCTRL_RTCCTRL_RTCSEL_OSC1K (OSC32KCTRL_RTCCTRL_RTCSEL_OSC1K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos) |
| mbed_official | 18:da299f395b9e | 169 | #define OSC32KCTRL_RTCCTRL_RTCSEL_OSC32K (OSC32KCTRL_RTCCTRL_RTCSEL_OSC32K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos) |
| mbed_official | 18:da299f395b9e | 170 | #define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K (OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos) |
| mbed_official | 18:da299f395b9e | 171 | #define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K (OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos) |
| mbed_official | 18:da299f395b9e | 172 | #define OSC32KCTRL_RTCCTRL_MASK 0x00000007ul /**< \brief (OSC32KCTRL_RTCCTRL) MASK Register */ |
| mbed_official | 18:da299f395b9e | 173 | |
| mbed_official | 18:da299f395b9e | 174 | /* -------- OSC32KCTRL_XOSC32K : (OSC32KCTRL Offset: 0x14) (R/W 32) 32kHz External Crystal Oscillator (XOSC32K) Control -------- */ |
| mbed_official | 18:da299f395b9e | 175 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 18:da299f395b9e | 176 | typedef union { |
| mbed_official | 18:da299f395b9e | 177 | struct { |
| mbed_official | 18:da299f395b9e | 178 | uint32_t :1; /*!< bit: 0 Reserved */ |
| mbed_official | 18:da299f395b9e | 179 | uint32_t ENABLE:1; /*!< bit: 1 Oscillator Enable */ |
| mbed_official | 18:da299f395b9e | 180 | uint32_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */ |
| mbed_official | 18:da299f395b9e | 181 | uint32_t EN32K:1; /*!< bit: 3 32kHz Output Enable */ |
| mbed_official | 18:da299f395b9e | 182 | uint32_t EN1K:1; /*!< bit: 4 1kHz Output Enable */ |
| mbed_official | 18:da299f395b9e | 183 | uint32_t :1; /*!< bit: 5 Reserved */ |
| mbed_official | 18:da299f395b9e | 184 | uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ |
| mbed_official | 18:da299f395b9e | 185 | uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ |
| mbed_official | 18:da299f395b9e | 186 | uint32_t STARTUP:3; /*!< bit: 8..10 Oscillator Start-Up Time */ |
| mbed_official | 18:da299f395b9e | 187 | uint32_t :1; /*!< bit: 11 Reserved */ |
| mbed_official | 18:da299f395b9e | 188 | uint32_t WRTLOCK:1; /*!< bit: 12 Write Lock */ |
| mbed_official | 18:da299f395b9e | 189 | uint32_t :19; /*!< bit: 13..31 Reserved */ |
| mbed_official | 18:da299f395b9e | 190 | } bit; /*!< Structure used for bit access */ |
| mbed_official | 18:da299f395b9e | 191 | uint32_t reg; /*!< Type used for register access */ |
| mbed_official | 18:da299f395b9e | 192 | } OSC32KCTRL_XOSC32K_Type; |
| mbed_official | 18:da299f395b9e | 193 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 18:da299f395b9e | 194 | |
| mbed_official | 18:da299f395b9e | 195 | #define OSC32KCTRL_XOSC32K_OFFSET 0x14 /**< \brief (OSC32KCTRL_XOSC32K offset) 32kHz External Crystal Oscillator (XOSC32K) Control */ |
| mbed_official | 18:da299f395b9e | 196 | #define OSC32KCTRL_XOSC32K_RESETVALUE 0x00000080ul /**< \brief (OSC32KCTRL_XOSC32K reset_value) 32kHz External Crystal Oscillator (XOSC32K) Control */ |
| mbed_official | 18:da299f395b9e | 197 | |
| mbed_official | 18:da299f395b9e | 198 | #define OSC32KCTRL_XOSC32K_ENABLE_Pos 1 /**< \brief (OSC32KCTRL_XOSC32K) Oscillator Enable */ |
| mbed_official | 18:da299f395b9e | 199 | #define OSC32KCTRL_XOSC32K_ENABLE (0x1ul << OSC32KCTRL_XOSC32K_ENABLE_Pos) |
| mbed_official | 18:da299f395b9e | 200 | #define OSC32KCTRL_XOSC32K_XTALEN_Pos 2 /**< \brief (OSC32KCTRL_XOSC32K) Crystal Oscillator Enable */ |
| mbed_official | 18:da299f395b9e | 201 | #define OSC32KCTRL_XOSC32K_XTALEN (0x1ul << OSC32KCTRL_XOSC32K_XTALEN_Pos) |
| mbed_official | 18:da299f395b9e | 202 | #define OSC32KCTRL_XOSC32K_EN32K_Pos 3 /**< \brief (OSC32KCTRL_XOSC32K) 32kHz Output Enable */ |
| mbed_official | 18:da299f395b9e | 203 | #define OSC32KCTRL_XOSC32K_EN32K (0x1ul << OSC32KCTRL_XOSC32K_EN32K_Pos) |
| mbed_official | 18:da299f395b9e | 204 | #define OSC32KCTRL_XOSC32K_EN1K_Pos 4 /**< \brief (OSC32KCTRL_XOSC32K) 1kHz Output Enable */ |
| mbed_official | 18:da299f395b9e | 205 | #define OSC32KCTRL_XOSC32K_EN1K (0x1ul << OSC32KCTRL_XOSC32K_EN1K_Pos) |
| mbed_official | 18:da299f395b9e | 206 | #define OSC32KCTRL_XOSC32K_RUNSTDBY_Pos 6 /**< \brief (OSC32KCTRL_XOSC32K) Run in Standby */ |
| mbed_official | 18:da299f395b9e | 207 | #define OSC32KCTRL_XOSC32K_RUNSTDBY (0x1ul << OSC32KCTRL_XOSC32K_RUNSTDBY_Pos) |
| mbed_official | 18:da299f395b9e | 208 | #define OSC32KCTRL_XOSC32K_ONDEMAND_Pos 7 /**< \brief (OSC32KCTRL_XOSC32K) On Demand Control */ |
| mbed_official | 18:da299f395b9e | 209 | #define OSC32KCTRL_XOSC32K_ONDEMAND (0x1ul << OSC32KCTRL_XOSC32K_ONDEMAND_Pos) |
| mbed_official | 18:da299f395b9e | 210 | #define OSC32KCTRL_XOSC32K_STARTUP_Pos 8 /**< \brief (OSC32KCTRL_XOSC32K) Oscillator Start-Up Time */ |
| mbed_official | 18:da299f395b9e | 211 | #define OSC32KCTRL_XOSC32K_STARTUP_Msk (0x7ul << OSC32KCTRL_XOSC32K_STARTUP_Pos) |
| mbed_official | 18:da299f395b9e | 212 | #define OSC32KCTRL_XOSC32K_STARTUP(value) ((OSC32KCTRL_XOSC32K_STARTUP_Msk & ((value) << OSC32KCTRL_XOSC32K_STARTUP_Pos))) |
| mbed_official | 18:da299f395b9e | 213 | #define OSC32KCTRL_XOSC32K_WRTLOCK_Pos 12 /**< \brief (OSC32KCTRL_XOSC32K) Write Lock */ |
| mbed_official | 18:da299f395b9e | 214 | #define OSC32KCTRL_XOSC32K_WRTLOCK (0x1ul << OSC32KCTRL_XOSC32K_WRTLOCK_Pos) |
| mbed_official | 18:da299f395b9e | 215 | #define OSC32KCTRL_XOSC32K_MASK 0x000017DEul /**< \brief (OSC32KCTRL_XOSC32K) MASK Register */ |
| mbed_official | 18:da299f395b9e | 216 | |
| mbed_official | 18:da299f395b9e | 217 | /* -------- OSC32KCTRL_OSC32K : (OSC32KCTRL Offset: 0x18) (R/W 32) 32kHz Internal Oscillator (OSC32K) Control -------- */ |
| mbed_official | 18:da299f395b9e | 218 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 18:da299f395b9e | 219 | typedef union { |
| mbed_official | 18:da299f395b9e | 220 | struct { |
| mbed_official | 18:da299f395b9e | 221 | uint32_t :1; /*!< bit: 0 Reserved */ |
| mbed_official | 18:da299f395b9e | 222 | uint32_t ENABLE:1; /*!< bit: 1 Oscillator Enable */ |
| mbed_official | 18:da299f395b9e | 223 | uint32_t EN32K:1; /*!< bit: 2 32kHz Output Enable */ |
| mbed_official | 18:da299f395b9e | 224 | uint32_t EN1K:1; /*!< bit: 3 1kHz Output Enable */ |
| mbed_official | 18:da299f395b9e | 225 | uint32_t :2; /*!< bit: 4.. 5 Reserved */ |
| mbed_official | 18:da299f395b9e | 226 | uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ |
| mbed_official | 18:da299f395b9e | 227 | uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ |
| mbed_official | 18:da299f395b9e | 228 | uint32_t STARTUP:3; /*!< bit: 8..10 Oscillator Start-Up Time */ |
| mbed_official | 18:da299f395b9e | 229 | uint32_t :1; /*!< bit: 11 Reserved */ |
| mbed_official | 18:da299f395b9e | 230 | uint32_t WRTLOCK:1; /*!< bit: 12 Write Lock */ |
| mbed_official | 18:da299f395b9e | 231 | uint32_t :3; /*!< bit: 13..15 Reserved */ |
| mbed_official | 18:da299f395b9e | 232 | uint32_t CALIB:7; /*!< bit: 16..22 Oscillator Calibration */ |
| mbed_official | 18:da299f395b9e | 233 | uint32_t :9; /*!< bit: 23..31 Reserved */ |
| mbed_official | 18:da299f395b9e | 234 | } bit; /*!< Structure used for bit access */ |
| mbed_official | 18:da299f395b9e | 235 | uint32_t reg; /*!< Type used for register access */ |
| mbed_official | 18:da299f395b9e | 236 | } OSC32KCTRL_OSC32K_Type; |
| mbed_official | 18:da299f395b9e | 237 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 18:da299f395b9e | 238 | |
| mbed_official | 18:da299f395b9e | 239 | #define OSC32KCTRL_OSC32K_OFFSET 0x18 /**< \brief (OSC32KCTRL_OSC32K offset) 32kHz Internal Oscillator (OSC32K) Control */ |
| mbed_official | 18:da299f395b9e | 240 | #define OSC32KCTRL_OSC32K_RESETVALUE 0x003F0080ul /**< \brief (OSC32KCTRL_OSC32K reset_value) 32kHz Internal Oscillator (OSC32K) Control */ |
| mbed_official | 18:da299f395b9e | 241 | |
| mbed_official | 18:da299f395b9e | 242 | #define OSC32KCTRL_OSC32K_ENABLE_Pos 1 /**< \brief (OSC32KCTRL_OSC32K) Oscillator Enable */ |
| mbed_official | 18:da299f395b9e | 243 | #define OSC32KCTRL_OSC32K_ENABLE (0x1ul << OSC32KCTRL_OSC32K_ENABLE_Pos) |
| mbed_official | 18:da299f395b9e | 244 | #define OSC32KCTRL_OSC32K_EN32K_Pos 2 /**< \brief (OSC32KCTRL_OSC32K) 32kHz Output Enable */ |
| mbed_official | 18:da299f395b9e | 245 | #define OSC32KCTRL_OSC32K_EN32K (0x1ul << OSC32KCTRL_OSC32K_EN32K_Pos) |
| mbed_official | 18:da299f395b9e | 246 | #define OSC32KCTRL_OSC32K_EN1K_Pos 3 /**< \brief (OSC32KCTRL_OSC32K) 1kHz Output Enable */ |
| mbed_official | 18:da299f395b9e | 247 | #define OSC32KCTRL_OSC32K_EN1K (0x1ul << OSC32KCTRL_OSC32K_EN1K_Pos) |
| mbed_official | 18:da299f395b9e | 248 | #define OSC32KCTRL_OSC32K_RUNSTDBY_Pos 6 /**< \brief (OSC32KCTRL_OSC32K) Run in Standby */ |
| mbed_official | 18:da299f395b9e | 249 | #define OSC32KCTRL_OSC32K_RUNSTDBY (0x1ul << OSC32KCTRL_OSC32K_RUNSTDBY_Pos) |
| mbed_official | 18:da299f395b9e | 250 | #define OSC32KCTRL_OSC32K_ONDEMAND_Pos 7 /**< \brief (OSC32KCTRL_OSC32K) On Demand Control */ |
| mbed_official | 18:da299f395b9e | 251 | #define OSC32KCTRL_OSC32K_ONDEMAND (0x1ul << OSC32KCTRL_OSC32K_ONDEMAND_Pos) |
| mbed_official | 18:da299f395b9e | 252 | #define OSC32KCTRL_OSC32K_STARTUP_Pos 8 /**< \brief (OSC32KCTRL_OSC32K) Oscillator Start-Up Time */ |
| mbed_official | 18:da299f395b9e | 253 | #define OSC32KCTRL_OSC32K_STARTUP_Msk (0x7ul << OSC32KCTRL_OSC32K_STARTUP_Pos) |
| mbed_official | 18:da299f395b9e | 254 | #define OSC32KCTRL_OSC32K_STARTUP(value) ((OSC32KCTRL_OSC32K_STARTUP_Msk & ((value) << OSC32KCTRL_OSC32K_STARTUP_Pos))) |
| mbed_official | 18:da299f395b9e | 255 | #define OSC32KCTRL_OSC32K_WRTLOCK_Pos 12 /**< \brief (OSC32KCTRL_OSC32K) Write Lock */ |
| mbed_official | 18:da299f395b9e | 256 | #define OSC32KCTRL_OSC32K_WRTLOCK (0x1ul << OSC32KCTRL_OSC32K_WRTLOCK_Pos) |
| mbed_official | 18:da299f395b9e | 257 | #define OSC32KCTRL_OSC32K_CALIB_Pos 16 /**< \brief (OSC32KCTRL_OSC32K) Oscillator Calibration */ |
| mbed_official | 18:da299f395b9e | 258 | #define OSC32KCTRL_OSC32K_CALIB_Msk (0x7Ful << OSC32KCTRL_OSC32K_CALIB_Pos) |
| mbed_official | 18:da299f395b9e | 259 | #define OSC32KCTRL_OSC32K_CALIB(value) ((OSC32KCTRL_OSC32K_CALIB_Msk & ((value) << OSC32KCTRL_OSC32K_CALIB_Pos))) |
| mbed_official | 18:da299f395b9e | 260 | #define OSC32KCTRL_OSC32K_MASK 0x007F17CEul /**< \brief (OSC32KCTRL_OSC32K) MASK Register */ |
| mbed_official | 18:da299f395b9e | 261 | |
| mbed_official | 18:da299f395b9e | 262 | /* -------- OSC32KCTRL_OSCULP32K : (OSC32KCTRL Offset: 0x1C) (R/W 32) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control -------- */ |
| mbed_official | 18:da299f395b9e | 263 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 18:da299f395b9e | 264 | typedef union { |
| mbed_official | 18:da299f395b9e | 265 | struct { |
| mbed_official | 18:da299f395b9e | 266 | uint32_t :8; /*!< bit: 0.. 7 Reserved */ |
| mbed_official | 18:da299f395b9e | 267 | uint32_t CALIB:5; /*!< bit: 8..12 Oscillator Calibration */ |
| mbed_official | 18:da299f395b9e | 268 | uint32_t :2; /*!< bit: 13..14 Reserved */ |
| mbed_official | 18:da299f395b9e | 269 | uint32_t WRTLOCK:1; /*!< bit: 15 Write Lock */ |
| mbed_official | 18:da299f395b9e | 270 | uint32_t :16; /*!< bit: 16..31 Reserved */ |
| mbed_official | 18:da299f395b9e | 271 | } bit; /*!< Structure used for bit access */ |
| mbed_official | 18:da299f395b9e | 272 | uint32_t reg; /*!< Type used for register access */ |
| mbed_official | 18:da299f395b9e | 273 | } OSC32KCTRL_OSCULP32K_Type; |
| mbed_official | 18:da299f395b9e | 274 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 18:da299f395b9e | 275 | |
| mbed_official | 18:da299f395b9e | 276 | #define OSC32KCTRL_OSCULP32K_OFFSET 0x1C /**< \brief (OSC32KCTRL_OSCULP32K offset) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */ |
| mbed_official | 18:da299f395b9e | 277 | |
| mbed_official | 18:da299f395b9e | 278 | #define OSC32KCTRL_OSCULP32K_CALIB_Pos 8 /**< \brief (OSC32KCTRL_OSCULP32K) Oscillator Calibration */ |
| mbed_official | 18:da299f395b9e | 279 | #define OSC32KCTRL_OSCULP32K_CALIB_Msk (0x1Ful << OSC32KCTRL_OSCULP32K_CALIB_Pos) |
| mbed_official | 18:da299f395b9e | 280 | #define OSC32KCTRL_OSCULP32K_CALIB(value) ((OSC32KCTRL_OSCULP32K_CALIB_Msk & ((value) << OSC32KCTRL_OSCULP32K_CALIB_Pos))) |
| mbed_official | 18:da299f395b9e | 281 | #define OSC32KCTRL_OSCULP32K_WRTLOCK_Pos 15 /**< \brief (OSC32KCTRL_OSCULP32K) Write Lock */ |
| mbed_official | 18:da299f395b9e | 282 | #define OSC32KCTRL_OSCULP32K_WRTLOCK (0x1ul << OSC32KCTRL_OSCULP32K_WRTLOCK_Pos) |
| mbed_official | 18:da299f395b9e | 283 | #define OSC32KCTRL_OSCULP32K_MASK 0x00009F00ul /**< \brief (OSC32KCTRL_OSCULP32K) MASK Register */ |
| mbed_official | 18:da299f395b9e | 284 | |
| mbed_official | 18:da299f395b9e | 285 | /** \brief OSC32KCTRL hardware registers */ |
| mbed_official | 18:da299f395b9e | 286 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 18:da299f395b9e | 287 | typedef struct { |
| mbed_official | 18:da299f395b9e | 288 | __IO OSC32KCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x00 (R/W 32) Interrupt Enable Clear */ |
| mbed_official | 18:da299f395b9e | 289 | __IO OSC32KCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x04 (R/W 32) Interrupt Enable Set */ |
| mbed_official | 18:da299f395b9e | 290 | __IO OSC32KCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 32) Interrupt Flag Status and Clear */ |
| mbed_official | 18:da299f395b9e | 291 | __I OSC32KCTRL_STATUS_Type STATUS; /**< \brief Offset: 0x0C (R/ 32) Power and Clocks Status */ |
| mbed_official | 18:da299f395b9e | 292 | __IO OSC32KCTRL_RTCCTRL_Type RTCCTRL; /**< \brief Offset: 0x10 (R/W 32) Clock selection */ |
| mbed_official | 18:da299f395b9e | 293 | __IO OSC32KCTRL_XOSC32K_Type XOSC32K; /**< \brief Offset: 0x14 (R/W 32) 32kHz External Crystal Oscillator (XOSC32K) Control */ |
| mbed_official | 18:da299f395b9e | 294 | __IO OSC32KCTRL_OSC32K_Type OSC32K; /**< \brief Offset: 0x18 (R/W 32) 32kHz Internal Oscillator (OSC32K) Control */ |
| mbed_official | 18:da299f395b9e | 295 | __IO OSC32KCTRL_OSCULP32K_Type OSCULP32K; /**< \brief Offset: 0x1C (R/W 32) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */ |
| mbed_official | 18:da299f395b9e | 296 | } Osc32kctrl; |
| mbed_official | 18:da299f395b9e | 297 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 18:da299f395b9e | 298 | |
| mbed_official | 18:da299f395b9e | 299 | /*@}*/ |
| mbed_official | 18:da299f395b9e | 300 | |
| mbed_official | 18:da299f395b9e | 301 | #endif /* _SAML21_OSC32KCTRL_COMPONENT_ */ |