b luo / mbed-dev

mbed library sources. With a patch for the can_api

Fork of mbed-dev by mbed official

targets/TARGET_NXP/TARGET_LPC2460/i2c_api.c@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
Parent:
targets/hal/TARGET_NXP/TARGET_LPC2460/i2c_api.c@144:ef7eb2e8f9f7 
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /* mbed Microcontroller Library
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2006-2015 ARM Limited
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Licensed under the Apache License, Version 2.0 (the "License");
<> 144:ef7eb2e8f9f7 5 * you may not use this file except in compliance with the License.
<> 144:ef7eb2e8f9f7 6 * You may obtain a copy of the License at
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * http://www.apache.org/licenses/LICENSE-2.0
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * Unless required by applicable law or agreed to in writing, software
<> 144:ef7eb2e8f9f7 11 * distributed under the License is distributed on an "AS IS" BASIS,
<> 144:ef7eb2e8f9f7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<> 144:ef7eb2e8f9f7 13 * See the License for the specific language governing permissions and
<> 144:ef7eb2e8f9f7 14 * limitations under the License.
<> 144:ef7eb2e8f9f7 15 */
<> 144:ef7eb2e8f9f7 16 #include "i2c_api.h"
<> 144:ef7eb2e8f9f7 17 #include "cmsis.h"
<> 144:ef7eb2e8f9f7 18 #include "pinmap.h"
<> 144:ef7eb2e8f9f7 19
<> 144:ef7eb2e8f9f7 20 static const PinMap PinMap_I2C_SDA[] = {
<> 144:ef7eb2e8f9f7 21 {P0_0 , I2C_1, 3},
<> 144:ef7eb2e8f9f7 22 {P0_10, I2C_2, 2},
<> 144:ef7eb2e8f9f7 23 {P0_19, I2C_1, 3},
<> 144:ef7eb2e8f9f7 24 {P0_27, I2C_0, 1},
<> 144:ef7eb2e8f9f7 25 {P2_14, I2C_1, 3},
<> 144:ef7eb2e8f9f7 26 {P2_30, I2C_2, 3},
<> 144:ef7eb2e8f9f7 27 {P4_20, I2C_2, 2},
<> 144:ef7eb2e8f9f7 28 {NC , NC , 0}
<> 144:ef7eb2e8f9f7 29 };
<> 144:ef7eb2e8f9f7 30
<> 144:ef7eb2e8f9f7 31 static const PinMap PinMap_I2C_SCL[] = {
<> 144:ef7eb2e8f9f7 32 {P0_1 , I2C_1, 3},
<> 144:ef7eb2e8f9f7 33 {P0_11, I2C_2, 2},
<> 144:ef7eb2e8f9f7 34 {P0_20, I2C_1, 3},
<> 144:ef7eb2e8f9f7 35 {P0_28, I2C_0, 1},
<> 144:ef7eb2e8f9f7 36 {P2_15, I2C_1, 3},
<> 144:ef7eb2e8f9f7 37 {P2_31, I2C_2, 3},
<> 144:ef7eb2e8f9f7 38 {P4_21, I2C_2, 2},
<> 144:ef7eb2e8f9f7 39 {NC , NC, 0}
<> 144:ef7eb2e8f9f7 40 };
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #define I2C_CONSET(x) (x->i2c->I2CONSET)
<> 144:ef7eb2e8f9f7 43 #define I2C_CONCLR(x) (x->i2c->I2CONCLR)
<> 144:ef7eb2e8f9f7 44 #define I2C_STAT(x) (x->i2c->I2STAT)
<> 144:ef7eb2e8f9f7 45 #define I2C_DAT(x) (x->i2c->I2DAT)
<> 144:ef7eb2e8f9f7 46 #define I2C_SCLL(x, val) (x->i2c->I2SCLL = val)
<> 144:ef7eb2e8f9f7 47 #define I2C_SCLH(x, val) (x->i2c->I2SCLH = val)
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 static const uint32_t I2C_addr_offset[2][4] = {
<> 144:ef7eb2e8f9f7 50 {0x0C, 0x20, 0x24, 0x28},
<> 144:ef7eb2e8f9f7 51 {0x30, 0x34, 0x38, 0x3C}
<> 144:ef7eb2e8f9f7 52 };
<> 144:ef7eb2e8f9f7 53
<> 144:ef7eb2e8f9f7 54 static inline void i2c_conclr(i2c_t *obj, int start, int stop, int interrupt, int acknowledge) {
<> 144:ef7eb2e8f9f7 55 I2C_CONCLR(obj) = (start << 5)
<> 144:ef7eb2e8f9f7 56 | (stop << 4)
<> 144:ef7eb2e8f9f7 57 | (interrupt << 3)
<> 144:ef7eb2e8f9f7 58 | (acknowledge << 2);
<> 144:ef7eb2e8f9f7 59 }
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 static inline void i2c_conset(i2c_t *obj, int start, int stop, int interrupt, int acknowledge) {
<> 144:ef7eb2e8f9f7 62 I2C_CONSET(obj) = (start << 5)
<> 144:ef7eb2e8f9f7 63 | (stop << 4)
<> 144:ef7eb2e8f9f7 64 | (interrupt << 3)
<> 144:ef7eb2e8f9f7 65 | (acknowledge << 2);
<> 144:ef7eb2e8f9f7 66 }
<> 144:ef7eb2e8f9f7 67
<> 144:ef7eb2e8f9f7 68 // Clear the Serial Interrupt (SI)
<> 144:ef7eb2e8f9f7 69 static inline void i2c_clear_SI(i2c_t *obj) {
<> 144:ef7eb2e8f9f7 70 i2c_conclr(obj, 0, 0, 1, 0);
<> 144:ef7eb2e8f9f7 71 }
<> 144:ef7eb2e8f9f7 72
<> 144:ef7eb2e8f9f7 73 static inline int i2c_status(i2c_t *obj) {
<> 144:ef7eb2e8f9f7 74 return I2C_STAT(obj);
<> 144:ef7eb2e8f9f7 75 }
<> 144:ef7eb2e8f9f7 76
<> 144:ef7eb2e8f9f7 77 // Wait until the Serial Interrupt (SI) is set
<> 144:ef7eb2e8f9f7 78 static int i2c_wait_SI(i2c_t *obj) {
<> 144:ef7eb2e8f9f7 79 int timeout = 0;
<> 144:ef7eb2e8f9f7 80 while (!(I2C_CONSET(obj) & (1 << 3))) {
<> 144:ef7eb2e8f9f7 81 timeout++;
<> 144:ef7eb2e8f9f7 82 if (timeout > 100000) return -1;
<> 144:ef7eb2e8f9f7 83 }
<> 144:ef7eb2e8f9f7 84 return 0;
<> 144:ef7eb2e8f9f7 85 }
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 static inline void i2c_interface_enable(i2c_t *obj) {
<> 144:ef7eb2e8f9f7 88 I2C_CONSET(obj) = 0x40;
<> 144:ef7eb2e8f9f7 89 }
<> 144:ef7eb2e8f9f7 90
<> 144:ef7eb2e8f9f7 91 static inline void i2c_power_enable(i2c_t *obj) {
<> 144:ef7eb2e8f9f7 92 switch ((int)obj->i2c) {
<> 144:ef7eb2e8f9f7 93 case I2C_0: LPC_SC->PCONP |= 1 << PCI2C0; break;
<> 144:ef7eb2e8f9f7 94 case I2C_1: LPC_SC->PCONP |= 1 << PCI2C1; break;
<> 144:ef7eb2e8f9f7 95 case I2C_2: LPC_SC->PCONP |= 1 << PCI2C2; break;
<> 144:ef7eb2e8f9f7 96 }
<> 144:ef7eb2e8f9f7 97 }
<> 144:ef7eb2e8f9f7 98
<> 144:ef7eb2e8f9f7 99 void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
<> 144:ef7eb2e8f9f7 100 // determine the SPI to use
<> 144:ef7eb2e8f9f7 101 I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
<> 144:ef7eb2e8f9f7 102 I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
<> 144:ef7eb2e8f9f7 103 obj->i2c = (LPC_I2C_TypeDef *)pinmap_merge(i2c_sda, i2c_scl);
<> 144:ef7eb2e8f9f7 104 MBED_ASSERT((int)obj->i2c != NC);
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 // enable power
<> 144:ef7eb2e8f9f7 107 i2c_power_enable(obj);
<> 144:ef7eb2e8f9f7 108
<> 144:ef7eb2e8f9f7 109 // set default frequency at 100k
<> 144:ef7eb2e8f9f7 110 i2c_frequency(obj, 100000);
<> 144:ef7eb2e8f9f7 111 i2c_conclr(obj, 1, 1, 1, 1);
<> 144:ef7eb2e8f9f7 112 i2c_interface_enable(obj);
<> 144:ef7eb2e8f9f7 113
<> 144:ef7eb2e8f9f7 114 pinmap_pinout(sda, PinMap_I2C_SDA);
<> 144:ef7eb2e8f9f7 115 pinmap_pinout(scl, PinMap_I2C_SCL);
<> 144:ef7eb2e8f9f7 116 }
<> 144:ef7eb2e8f9f7 117
<> 144:ef7eb2e8f9f7 118 inline int i2c_start(i2c_t *obj) {
<> 144:ef7eb2e8f9f7 119 int status = 0;
<> 144:ef7eb2e8f9f7 120 int isInterrupted = I2C_CONSET(obj) & (1 << 3);
<> 144:ef7eb2e8f9f7 121
<> 144:ef7eb2e8f9f7 122 // 8.1 Before master mode can be entered, I2CON must be initialised to:
<> 144:ef7eb2e8f9f7 123 // - I2EN STA STO SI AA - -
<> 144:ef7eb2e8f9f7 124 // - 1 0 0 x x - -
<> 144:ef7eb2e8f9f7 125 // if AA = 0, it can't enter slave mode
<> 144:ef7eb2e8f9f7 126 i2c_conclr(obj, 1, 1, 0, 1);
<> 144:ef7eb2e8f9f7 127
<> 144:ef7eb2e8f9f7 128 // The master mode may now be entered by setting the STA bit
<> 144:ef7eb2e8f9f7 129 // this will generate a start condition when the bus becomes free
<> 144:ef7eb2e8f9f7 130 i2c_conset(obj, 1, 0, 0, 1);
<> 144:ef7eb2e8f9f7 131 // Clearing SI bit when it wasn't set on entry can jump past state
<> 144:ef7eb2e8f9f7 132 // 0x10 or 0x08 and erroneously send uninitialized slave address.
<> 144:ef7eb2e8f9f7 133 if (isInterrupted)
<> 144:ef7eb2e8f9f7 134 i2c_clear_SI(obj);
<> 144:ef7eb2e8f9f7 135
<> 144:ef7eb2e8f9f7 136 i2c_wait_SI(obj);
<> 144:ef7eb2e8f9f7 137 status = i2c_status(obj);
<> 144:ef7eb2e8f9f7 138
<> 144:ef7eb2e8f9f7 139 // Clear start bit now that it's transmitted
<> 144:ef7eb2e8f9f7 140 i2c_conclr(obj, 1, 0, 0, 0);
<> 144:ef7eb2e8f9f7 141 return status;
<> 144:ef7eb2e8f9f7 142 }
<> 144:ef7eb2e8f9f7 143
<> 144:ef7eb2e8f9f7 144 inline int i2c_stop(i2c_t *obj) {
<> 144:ef7eb2e8f9f7 145 int timeout = 0;
<> 144:ef7eb2e8f9f7 146
<> 144:ef7eb2e8f9f7 147 // write the stop bit
<> 144:ef7eb2e8f9f7 148 i2c_conset(obj, 0, 1, 0, 0);
<> 144:ef7eb2e8f9f7 149 i2c_clear_SI(obj);
<> 144:ef7eb2e8f9f7 150
<> 144:ef7eb2e8f9f7 151 // wait for STO bit to reset
<> 144:ef7eb2e8f9f7 152 while (I2C_CONSET(obj) & (1 << 4)) {
<> 144:ef7eb2e8f9f7 153 timeout ++;
<> 144:ef7eb2e8f9f7 154 if (timeout > 100000) return 1;
<> 144:ef7eb2e8f9f7 155 }
<> 144:ef7eb2e8f9f7 156
<> 144:ef7eb2e8f9f7 157 return 0;
<> 144:ef7eb2e8f9f7 158 }
<> 144:ef7eb2e8f9f7 159
<> 144:ef7eb2e8f9f7 160 static inline int i2c_do_write(i2c_t *obj, int value, uint8_t addr) {
<> 144:ef7eb2e8f9f7 161 // write the data
<> 144:ef7eb2e8f9f7 162 I2C_DAT(obj) = value;
<> 144:ef7eb2e8f9f7 163
<> 144:ef7eb2e8f9f7 164 // clear SI to init a send
<> 144:ef7eb2e8f9f7 165 i2c_clear_SI(obj);
<> 144:ef7eb2e8f9f7 166
<> 144:ef7eb2e8f9f7 167 // wait and return status
<> 144:ef7eb2e8f9f7 168 i2c_wait_SI(obj);
<> 144:ef7eb2e8f9f7 169 return i2c_status(obj);
<> 144:ef7eb2e8f9f7 170 }
<> 144:ef7eb2e8f9f7 171
<> 144:ef7eb2e8f9f7 172 static inline int i2c_do_read(i2c_t *obj, int last) {
<> 144:ef7eb2e8f9f7 173 // we are in state 0x40 (SLA+R tx'd) or 0x50 (data rx'd and ack)
<> 144:ef7eb2e8f9f7 174 if (last) {
<> 144:ef7eb2e8f9f7 175 i2c_conclr(obj, 0, 0, 0, 1); // send a NOT ACK
<> 144:ef7eb2e8f9f7 176 } else {
<> 144:ef7eb2e8f9f7 177 i2c_conset(obj, 0, 0, 0, 1); // send a ACK
<> 144:ef7eb2e8f9f7 178 }
<> 144:ef7eb2e8f9f7 179
<> 144:ef7eb2e8f9f7 180 // accept byte
<> 144:ef7eb2e8f9f7 181 i2c_clear_SI(obj);
<> 144:ef7eb2e8f9f7 182
<> 144:ef7eb2e8f9f7 183 // wait for it to arrive
<> 144:ef7eb2e8f9f7 184 i2c_wait_SI(obj);
<> 144:ef7eb2e8f9f7 185
<> 144:ef7eb2e8f9f7 186 // return the data
<> 144:ef7eb2e8f9f7 187 return (I2C_DAT(obj) & 0xFF);
<> 144:ef7eb2e8f9f7 188 }
<> 144:ef7eb2e8f9f7 189
<> 144:ef7eb2e8f9f7 190 void i2c_frequency(i2c_t *obj, int hz) {
<> 144:ef7eb2e8f9f7 191 // [TODO] set pclk to /4
<> 144:ef7eb2e8f9f7 192 uint32_t PCLK = SystemCoreClock / 4;
<> 144:ef7eb2e8f9f7 193
<> 144:ef7eb2e8f9f7 194 uint32_t pulse = PCLK / (hz * 2);
<> 144:ef7eb2e8f9f7 195
<> 144:ef7eb2e8f9f7 196 // I2C Rate
<> 144:ef7eb2e8f9f7 197 I2C_SCLL(obj, pulse);
<> 144:ef7eb2e8f9f7 198 I2C_SCLH(obj, pulse);
<> 144:ef7eb2e8f9f7 199 }
<> 144:ef7eb2e8f9f7 200
<> 144:ef7eb2e8f9f7 201 // The I2C does a read or a write as a whole operation
<> 144:ef7eb2e8f9f7 202 // There are two types of error conditions it can encounter
<> 144:ef7eb2e8f9f7 203 // 1) it can not obtain the bus
<> 144:ef7eb2e8f9f7 204 // 2) it gets error responses at part of the transmission
<> 144:ef7eb2e8f9f7 205 //
<> 144:ef7eb2e8f9f7 206 // We tackle them as follows:
<> 144:ef7eb2e8f9f7 207 // 1) we retry until we get the bus. we could have a "timeout" if we can not get it
<> 144:ef7eb2e8f9f7 208 // which basically turns it in to a 2)
<> 144:ef7eb2e8f9f7 209 // 2) on error, we use the standard error mechanisms to report/debug
<> 144:ef7eb2e8f9f7 210 //
<> 144:ef7eb2e8f9f7 211 // Therefore an I2C transaction should always complete. If it doesn't it is usually
<> 144:ef7eb2e8f9f7 212 // because something is setup wrong (e.g. wiring), and we don't need to programatically
<> 144:ef7eb2e8f9f7 213 // check for that
<> 144:ef7eb2e8f9f7 214 int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
<> 144:ef7eb2e8f9f7 215 int count, status;
<> 144:ef7eb2e8f9f7 216
<> 144:ef7eb2e8f9f7 217 status = i2c_start(obj);
<> 144:ef7eb2e8f9f7 218
<> 144:ef7eb2e8f9f7 219 if ((status != 0x10) && (status != 0x08)) {
<> 144:ef7eb2e8f9f7 220 i2c_stop(obj);
<> 144:ef7eb2e8f9f7 221 return I2C_ERROR_BUS_BUSY;
<> 144:ef7eb2e8f9f7 222 }
<> 144:ef7eb2e8f9f7 223
<> 144:ef7eb2e8f9f7 224 status = i2c_do_write(obj, (address | 0x01), 1);
<> 144:ef7eb2e8f9f7 225 if (status != 0x40) {
<> 144:ef7eb2e8f9f7 226 i2c_stop(obj);
<> 144:ef7eb2e8f9f7 227 return I2C_ERROR_NO_SLAVE;
<> 144:ef7eb2e8f9f7 228 }
<> 144:ef7eb2e8f9f7 229
<> 144:ef7eb2e8f9f7 230 // Read in all except last byte
<> 144:ef7eb2e8f9f7 231 for (count = 0; count < (length - 1); count++) {
<> 144:ef7eb2e8f9f7 232 int value = i2c_do_read(obj, 0);
<> 144:ef7eb2e8f9f7 233 status = i2c_status(obj);
<> 144:ef7eb2e8f9f7 234 if (status != 0x50) {
<> 144:ef7eb2e8f9f7 235 i2c_stop(obj);
<> 144:ef7eb2e8f9f7 236 return count;
<> 144:ef7eb2e8f9f7 237 }
<> 144:ef7eb2e8f9f7 238 data[count] = (char) value;
<> 144:ef7eb2e8f9f7 239 }
<> 144:ef7eb2e8f9f7 240
<> 144:ef7eb2e8f9f7 241 // read in last byte
<> 144:ef7eb2e8f9f7 242 int value = i2c_do_read(obj, 1);
<> 144:ef7eb2e8f9f7 243 status = i2c_status(obj);
<> 144:ef7eb2e8f9f7 244 if (status != 0x58) {
<> 144:ef7eb2e8f9f7 245 i2c_stop(obj);
<> 144:ef7eb2e8f9f7 246 return length - 1;
<> 144:ef7eb2e8f9f7 247 }
<> 144:ef7eb2e8f9f7 248
<> 144:ef7eb2e8f9f7 249 data[count] = (char) value;
<> 144:ef7eb2e8f9f7 250
<> 144:ef7eb2e8f9f7 251 // If not repeated start, send stop.
<> 144:ef7eb2e8f9f7 252 if (stop) {
<> 144:ef7eb2e8f9f7 253 i2c_stop(obj);
<> 144:ef7eb2e8f9f7 254 }
<> 144:ef7eb2e8f9f7 255
<> 144:ef7eb2e8f9f7 256 return length;
<> 144:ef7eb2e8f9f7 257 }
<> 144:ef7eb2e8f9f7 258
<> 144:ef7eb2e8f9f7 259 int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
<> 144:ef7eb2e8f9f7 260 int i, status;
<> 144:ef7eb2e8f9f7 261
<> 144:ef7eb2e8f9f7 262 status = i2c_start(obj);
<> 144:ef7eb2e8f9f7 263
<> 144:ef7eb2e8f9f7 264 if ((status != 0x10) && (status != 0x08)) {
<> 144:ef7eb2e8f9f7 265 i2c_stop(obj);
<> 144:ef7eb2e8f9f7 266 return I2C_ERROR_BUS_BUSY;
<> 144:ef7eb2e8f9f7 267 }
<> 144:ef7eb2e8f9f7 268
<> 144:ef7eb2e8f9f7 269 status = i2c_do_write(obj, (address & 0xFE), 1);
<> 144:ef7eb2e8f9f7 270 if (status != 0x18) {
<> 144:ef7eb2e8f9f7 271 i2c_stop(obj);
<> 144:ef7eb2e8f9f7 272 return I2C_ERROR_NO_SLAVE;
<> 144:ef7eb2e8f9f7 273 }
<> 144:ef7eb2e8f9f7 274
<> 144:ef7eb2e8f9f7 275 for (i=0; i<length; i++) {
<> 144:ef7eb2e8f9f7 276 status = i2c_do_write(obj, data[i], 0);
<> 144:ef7eb2e8f9f7 277 if (status != 0x28) {
<> 144:ef7eb2e8f9f7 278 i2c_stop(obj);
<> 144:ef7eb2e8f9f7 279 return i;
<> 144:ef7eb2e8f9f7 280 }
<> 144:ef7eb2e8f9f7 281 }
<> 144:ef7eb2e8f9f7 282
<> 144:ef7eb2e8f9f7 283 // clearing the serial interrupt here might cause an unintended rewrite of the last byte
<> 144:ef7eb2e8f9f7 284 // see also issue report https://mbed.org/users/mbed_official/code/mbed/issues/1
<> 144:ef7eb2e8f9f7 285 // i2c_clear_SI(obj);
<> 144:ef7eb2e8f9f7 286
<> 144:ef7eb2e8f9f7 287 // If not repeated start, send stop.
<> 144:ef7eb2e8f9f7 288 if (stop) {
<> 144:ef7eb2e8f9f7 289 i2c_stop(obj);
<> 144:ef7eb2e8f9f7 290 }
<> 144:ef7eb2e8f9f7 291
<> 144:ef7eb2e8f9f7 292 return length;
<> 144:ef7eb2e8f9f7 293 }
<> 144:ef7eb2e8f9f7 294
<> 144:ef7eb2e8f9f7 295 void i2c_reset(i2c_t *obj) {
<> 144:ef7eb2e8f9f7 296 i2c_stop(obj);
<> 144:ef7eb2e8f9f7 297 }
<> 144:ef7eb2e8f9f7 298
<> 144:ef7eb2e8f9f7 299 int i2c_byte_read(i2c_t *obj, int last) {
<> 144:ef7eb2e8f9f7 300 return (i2c_do_read(obj, last) & 0xFF);
<> 144:ef7eb2e8f9f7 301 }
<> 144:ef7eb2e8f9f7 302
<> 144:ef7eb2e8f9f7 303 int i2c_byte_write(i2c_t *obj, int data) {
<> 144:ef7eb2e8f9f7 304 int ack;
<> 144:ef7eb2e8f9f7 305 int status = i2c_do_write(obj, (data & 0xFF), 0);
<> 144:ef7eb2e8f9f7 306
<> 144:ef7eb2e8f9f7 307 switch(status) {
<> 144:ef7eb2e8f9f7 308 case 0x18: case 0x28: // Master transmit ACKs
<> 144:ef7eb2e8f9f7 309 ack = 1;
<> 144:ef7eb2e8f9f7 310 break;
<> 144:ef7eb2e8f9f7 311
<> 144:ef7eb2e8f9f7 312 case 0x40: // Master receive address transmitted ACK
<> 144:ef7eb2e8f9f7 313 ack = 1;
<> 144:ef7eb2e8f9f7 314 break;
<> 144:ef7eb2e8f9f7 315
<> 144:ef7eb2e8f9f7 316 case 0xB8: // Slave transmit ACK
<> 144:ef7eb2e8f9f7 317 ack = 1;
<> 144:ef7eb2e8f9f7 318 break;
<> 144:ef7eb2e8f9f7 319
<> 144:ef7eb2e8f9f7 320 default:
<> 144:ef7eb2e8f9f7 321 ack = 0;
<> 144:ef7eb2e8f9f7 322 break;
<> 144:ef7eb2e8f9f7 323 }
<> 144:ef7eb2e8f9f7 324
<> 144:ef7eb2e8f9f7 325 return ack;
<> 144:ef7eb2e8f9f7 326 }
<> 144:ef7eb2e8f9f7 327
<> 144:ef7eb2e8f9f7 328 void i2c_slave_mode(i2c_t *obj, int enable_slave) {
<> 144:ef7eb2e8f9f7 329 if (enable_slave != 0) {
<> 144:ef7eb2e8f9f7 330 i2c_conclr(obj, 1, 1, 1, 0);
<> 144:ef7eb2e8f9f7 331 i2c_conset(obj, 0, 0, 0, 1);
<> 144:ef7eb2e8f9f7 332 } else {
<> 144:ef7eb2e8f9f7 333 i2c_conclr(obj, 1, 1, 1, 1);
<> 144:ef7eb2e8f9f7 334 }
<> 144:ef7eb2e8f9f7 335 }
<> 144:ef7eb2e8f9f7 336
<> 144:ef7eb2e8f9f7 337 int i2c_slave_receive(i2c_t *obj) {
<> 144:ef7eb2e8f9f7 338 int status;
<> 144:ef7eb2e8f9f7 339 int retval;
<> 144:ef7eb2e8f9f7 340
<> 144:ef7eb2e8f9f7 341 status = i2c_status(obj);
<> 144:ef7eb2e8f9f7 342 switch(status) {
<> 144:ef7eb2e8f9f7 343 case 0x60: retval = 3; break;
<> 144:ef7eb2e8f9f7 344 case 0x70: retval = 2; break;
<> 144:ef7eb2e8f9f7 345 case 0xA8: retval = 1; break;
<> 144:ef7eb2e8f9f7 346 default : retval = 0; break;
<> 144:ef7eb2e8f9f7 347 }
<> 144:ef7eb2e8f9f7 348
<> 144:ef7eb2e8f9f7 349 return(retval);
<> 144:ef7eb2e8f9f7 350 }
<> 144:ef7eb2e8f9f7 351
<> 144:ef7eb2e8f9f7 352 int i2c_slave_read(i2c_t *obj, char *data, int length) {
<> 144:ef7eb2e8f9f7 353 int count = 0;
<> 144:ef7eb2e8f9f7 354 int status;
<> 144:ef7eb2e8f9f7 355
<> 144:ef7eb2e8f9f7 356 do {
<> 144:ef7eb2e8f9f7 357 i2c_clear_SI(obj);
<> 144:ef7eb2e8f9f7 358 i2c_wait_SI(obj);
<> 144:ef7eb2e8f9f7 359 status = i2c_status(obj);
<> 144:ef7eb2e8f9f7 360 if((status == 0x80) || (status == 0x90)) {
<> 144:ef7eb2e8f9f7 361 data[count] = I2C_DAT(obj) & 0xFF;
<> 144:ef7eb2e8f9f7 362 }
<> 144:ef7eb2e8f9f7 363 count++;
<> 144:ef7eb2e8f9f7 364 } while (((status == 0x80) || (status == 0x90) ||
<> 144:ef7eb2e8f9f7 365 (status == 0x060) || (status == 0x70)) && (count < length));
<> 144:ef7eb2e8f9f7 366
<> 144:ef7eb2e8f9f7 367 if(status != 0xA0) {
<> 144:ef7eb2e8f9f7 368 i2c_stop(obj);
<> 144:ef7eb2e8f9f7 369 }
<> 144:ef7eb2e8f9f7 370
<> 144:ef7eb2e8f9f7 371 i2c_clear_SI(obj);
<> 144:ef7eb2e8f9f7 372
<> 144:ef7eb2e8f9f7 373 return count;
<> 144:ef7eb2e8f9f7 374 }
<> 144:ef7eb2e8f9f7 375
<> 144:ef7eb2e8f9f7 376 int i2c_slave_write(i2c_t *obj, const char *data, int length) {
<> 144:ef7eb2e8f9f7 377 int count = 0;
<> 144:ef7eb2e8f9f7 378 int status;
<> 144:ef7eb2e8f9f7 379
<> 144:ef7eb2e8f9f7 380 if(length <= 0) {
<> 144:ef7eb2e8f9f7 381 return(0);
<> 144:ef7eb2e8f9f7 382 }
<> 144:ef7eb2e8f9f7 383
<> 144:ef7eb2e8f9f7 384 do {
<> 144:ef7eb2e8f9f7 385 status = i2c_do_write(obj, data[count], 0);
<> 144:ef7eb2e8f9f7 386 count++;
<> 144:ef7eb2e8f9f7 387 } while ((count < length) && (status == 0xB8));
<> 144:ef7eb2e8f9f7 388
<> 144:ef7eb2e8f9f7 389 if((status != 0xC0) && (status != 0xC8)) {
<> 144:ef7eb2e8f9f7 390 i2c_stop(obj);
<> 144:ef7eb2e8f9f7 391 }
<> 144:ef7eb2e8f9f7 392
<> 144:ef7eb2e8f9f7 393 i2c_clear_SI(obj);
<> 144:ef7eb2e8f9f7 394
<> 144:ef7eb2e8f9f7 395 return(count);
<> 144:ef7eb2e8f9f7 396 }
<> 144:ef7eb2e8f9f7 397
<> 144:ef7eb2e8f9f7 398 void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) {
<> 144:ef7eb2e8f9f7 399 uint32_t addr;
<> 144:ef7eb2e8f9f7 400
<> 144:ef7eb2e8f9f7 401 if ((idx >= 0) && (idx <= 3)) {
<> 144:ef7eb2e8f9f7 402 addr = ((uint32_t)obj->i2c) + I2C_addr_offset[0][idx];
<> 144:ef7eb2e8f9f7 403 *((uint32_t *) addr) = address & 0xFF;
<> 144:ef7eb2e8f9f7 404 }
<> 144:ef7eb2e8f9f7 405 }