Darrel Weng / MMA8451Q

Fork of MMA8451Q by Antonio Quevedo

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MMA8451Q.cpp

00001 /* Copyright (c) 2010-2011 mbed.org, MIT License
00002 * Copyright (c) 2014 Antonio Quevedo, UNICAMP
00003 *
00004 * Permission is hereby granted, free of charge, to any person obtaining a copy of this software
00005 * and associated documentation files (the "Software"), to deal in the Software without
00006 * restriction, including without limitation the rights to use, copy, modify, merge, publish,
00007 * distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
00008 * Software is furnished to do so, subject to the following conditions:
00009 *
00010 * The above copyright notice and this permission notice shall be included in all copies or
00011 * substantial portions of the Software.
00012 *
00013 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
00014 * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
00015 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
00016 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
00017 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
00018 */
00019 
00020 #include "MMA8451Q.h"
00021 
00022 #define ACCEL_I2C_ADDRESS 0x1D<<1
00023 #define REG_STATUS        0x00
00024 #define REG_XYZ_DATA_CFG  0x0E
00025 #define REG_WHO_AM_I      0x0D
00026 #define REG_CTRL_REG1     0x2A
00027 #define REG_CTRL_REG2     0x2B
00028 #define REG_CTRL_REG3     0x2C
00029 #define REG_CTRL_REG4     0x2D
00030 #define REG_CTRL_REG5     0x2E
00031 #define REG_OUT_X_MSB     0x01
00032 #define REG_OUT_Y_MSB     0x03
00033 #define REG_OUT_Z_MSB     0x05
00034 
00035 MMA8451Q::MMA8451Q(PinName sda, PinName scl) : m_i2c(sda, scl) {
00036     uint8_t data[2] = {REG_CTRL_REG1, 0x00}; // Puts acc in standby for configuring
00037     writeRegs(data, 2);
00038     data[0] = REG_XYZ_DATA_CFG; // Writing 00 turns off high-pass filter and sets full scale range to 2g
00039                                 // data[1] = 0x01; for 4g
00040                                 // data[1] = 0x02; for 8g
00041     data[1] = 0x00;
00042     writeRegs(data, 2); 
00043     data[0] = REG_CTRL_REG2;
00044     data[1] = 0x00; // Disable self-test, software reset and auto-sleep; operates in normal mode
00045     writeRegs(data, 2);
00046     data[0] = REG_CTRL_REG3; // Interrupt polarity low, push-pull output
00047     writeRegs(data, 2);
00048     data[0] = REG_CTRL_REG4;
00049     data[1] = 0x01; // Enables interrupt for data Ready
00050     writeRegs(data, 2);
00051     data[0] = REG_CTRL_REG5;
00052     writeRegs(data, 2); // Routes Data Ready interrupt to INT1
00053     data[0] = REG_CTRL_REG1; 
00054     data[1] = 0x09; // Data rate is 400Hz
00055     writeRegs(data, 2);
00056 }
00057 
00058 MMA8451Q::~MMA8451Q() { }
00059 
00060 void MMA8451Q::getAccAllAxis(int16_t * res) {
00061     uint8_t temp[6];
00062     readRegs(REG_OUT_X_MSB, temp, 6);
00063     res[0] = ((temp[0] << 8) + temp[1]);
00064     res[1] = ((temp[2] << 8) + temp[3]);
00065     res[2] = ((temp[4] << 8) + temp[5]);
00066 }
00067 
00068 void MMA8451Q::readRegs(int addr, uint8_t * data, int len) {
00069     char t[1] = {addr};
00070     m_i2c.write(ACCEL_I2C_ADDRESS, t, 1, true);
00071     m_i2c.read(ACCEL_I2C_ADDRESS, (char *)data, len);
00072 }
00073 
00074 void MMA8451Q::writeRegs(uint8_t * data, int len) {
00075     m_i2c.write(ACCEL_I2C_ADDRESS, (char *)data, len);
00076 }