Viktor Zhezher
Library to control Silicon Labs SI570 10 MHZ TO 1.4 GHZ I2C PROGRAMMABLE XO/VCXO.
Fork of
SI570
by 
Gerrit Polder
BSP_F746NG/wm8994.c@1:1556bcaaf759, 2016-03-27 (annotated)
- Committer:
- DL3LD
- Date:
- Sun Mar 27 06:55:59 2016 +0000
- Revision:
- 1:1556bcaaf759
STM32F746NG SI570 VFO Test
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| DL3LD | 1:1556bcaaf759 | 1 | /** |
| DL3LD | 1:1556bcaaf759 | 2 | ****************************************************************************** |
| DL3LD | 1:1556bcaaf759 | 3 | * @file wm8994.c |
| DL3LD | 1:1556bcaaf759 | 4 | * @author MCD Application Team |
| DL3LD | 1:1556bcaaf759 | 5 | * @version V2.0.0 |
| DL3LD | 1:1556bcaaf759 | 6 | * @date 24-June-2015 |
| DL3LD | 1:1556bcaaf759 | 7 | * @brief This file provides the WM8994 Audio Codec driver. |
| DL3LD | 1:1556bcaaf759 | 8 | ****************************************************************************** |
| DL3LD | 1:1556bcaaf759 | 9 | * @attention |
| DL3LD | 1:1556bcaaf759 | 10 | * |
| DL3LD | 1:1556bcaaf759 | 11 | * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> |
| DL3LD | 1:1556bcaaf759 | 12 | * |
| DL3LD | 1:1556bcaaf759 | 13 | * Redistribution and use in source and binary forms, with or without modification, |
| DL3LD | 1:1556bcaaf759 | 14 | * are permitted provided that the following conditions are met: |
| DL3LD | 1:1556bcaaf759 | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
| DL3LD | 1:1556bcaaf759 | 16 | * this list of conditions and the following disclaimer. |
| DL3LD | 1:1556bcaaf759 | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| DL3LD | 1:1556bcaaf759 | 18 | * this list of conditions and the following disclaimer in the documentation |
| DL3LD | 1:1556bcaaf759 | 19 | * and/or other materials provided with the distribution. |
| DL3LD | 1:1556bcaaf759 | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| DL3LD | 1:1556bcaaf759 | 21 | * may be used to endorse or promote products derived from this software |
| DL3LD | 1:1556bcaaf759 | 22 | * without specific prior written permission. |
| DL3LD | 1:1556bcaaf759 | 23 | * |
| DL3LD | 1:1556bcaaf759 | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| DL3LD | 1:1556bcaaf759 | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| DL3LD | 1:1556bcaaf759 | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| DL3LD | 1:1556bcaaf759 | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| DL3LD | 1:1556bcaaf759 | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| DL3LD | 1:1556bcaaf759 | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| DL3LD | 1:1556bcaaf759 | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| DL3LD | 1:1556bcaaf759 | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| DL3LD | 1:1556bcaaf759 | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| DL3LD | 1:1556bcaaf759 | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| DL3LD | 1:1556bcaaf759 | 34 | * |
| DL3LD | 1:1556bcaaf759 | 35 | ****************************************************************************** |
| DL3LD | 1:1556bcaaf759 | 36 | */ |
| DL3LD | 1:1556bcaaf759 | 37 | |
| DL3LD | 1:1556bcaaf759 | 38 | /* Includes ------------------------------------------------------------------*/ |
| DL3LD | 1:1556bcaaf759 | 39 | #include "wm8994.h" |
| DL3LD | 1:1556bcaaf759 | 40 | |
| DL3LD | 1:1556bcaaf759 | 41 | /** @addtogroup BSP |
| DL3LD | 1:1556bcaaf759 | 42 | * @{ |
| DL3LD | 1:1556bcaaf759 | 43 | */ |
| DL3LD | 1:1556bcaaf759 | 44 | |
| DL3LD | 1:1556bcaaf759 | 45 | /** @addtogroup Components |
| DL3LD | 1:1556bcaaf759 | 46 | * @{ |
| DL3LD | 1:1556bcaaf759 | 47 | */ |
| DL3LD | 1:1556bcaaf759 | 48 | |
| DL3LD | 1:1556bcaaf759 | 49 | /** @addtogroup wm8994 |
| DL3LD | 1:1556bcaaf759 | 50 | * @brief This file provides a set of functions needed to drive the |
| DL3LD | 1:1556bcaaf759 | 51 | * WM8994 audio codec. |
| DL3LD | 1:1556bcaaf759 | 52 | * @{ |
| DL3LD | 1:1556bcaaf759 | 53 | */ |
| DL3LD | 1:1556bcaaf759 | 54 | |
| DL3LD | 1:1556bcaaf759 | 55 | /** @defgroup WM8994_Private_Types |
| DL3LD | 1:1556bcaaf759 | 56 | * @{ |
| DL3LD | 1:1556bcaaf759 | 57 | */ |
| DL3LD | 1:1556bcaaf759 | 58 | |
| DL3LD | 1:1556bcaaf759 | 59 | /** |
| DL3LD | 1:1556bcaaf759 | 60 | * @} |
| DL3LD | 1:1556bcaaf759 | 61 | */ |
| DL3LD | 1:1556bcaaf759 | 62 | |
| DL3LD | 1:1556bcaaf759 | 63 | /** @defgroup WM8994_Private_Defines |
| DL3LD | 1:1556bcaaf759 | 64 | * @{ |
| DL3LD | 1:1556bcaaf759 | 65 | */ |
| DL3LD | 1:1556bcaaf759 | 66 | /* Uncomment this line to enable verifying data sent to codec after each write |
| DL3LD | 1:1556bcaaf759 | 67 | operation (for debug purpose) */ |
| DL3LD | 1:1556bcaaf759 | 68 | #if !defined (VERIFY_WRITTENDATA) |
| DL3LD | 1:1556bcaaf759 | 69 | /* #define VERIFY_WRITTENDATA */ |
| DL3LD | 1:1556bcaaf759 | 70 | #endif /* VERIFY_WRITTENDATA */ |
| DL3LD | 1:1556bcaaf759 | 71 | /** |
| DL3LD | 1:1556bcaaf759 | 72 | * @} |
| DL3LD | 1:1556bcaaf759 | 73 | */ |
| DL3LD | 1:1556bcaaf759 | 74 | |
| DL3LD | 1:1556bcaaf759 | 75 | /** @defgroup WM8994_Private_Macros |
| DL3LD | 1:1556bcaaf759 | 76 | * @{ |
| DL3LD | 1:1556bcaaf759 | 77 | */ |
| DL3LD | 1:1556bcaaf759 | 78 | |
| DL3LD | 1:1556bcaaf759 | 79 | /** |
| DL3LD | 1:1556bcaaf759 | 80 | * @} |
| DL3LD | 1:1556bcaaf759 | 81 | */ |
| DL3LD | 1:1556bcaaf759 | 82 | |
| DL3LD | 1:1556bcaaf759 | 83 | /** @defgroup WM8994_Private_Variables |
| DL3LD | 1:1556bcaaf759 | 84 | * @{ |
| DL3LD | 1:1556bcaaf759 | 85 | */ |
| DL3LD | 1:1556bcaaf759 | 86 | |
| DL3LD | 1:1556bcaaf759 | 87 | /* Audio codec driver structure initialization */ |
| DL3LD | 1:1556bcaaf759 | 88 | AUDIO_DrvTypeDef wm8994_drv = |
| DL3LD | 1:1556bcaaf759 | 89 | { |
| DL3LD | 1:1556bcaaf759 | 90 | wm8994_Init, |
| DL3LD | 1:1556bcaaf759 | 91 | wm8994_DeInit, |
| DL3LD | 1:1556bcaaf759 | 92 | wm8994_ReadID, |
| DL3LD | 1:1556bcaaf759 | 93 | |
| DL3LD | 1:1556bcaaf759 | 94 | wm8994_Play, |
| DL3LD | 1:1556bcaaf759 | 95 | wm8994_Pause, |
| DL3LD | 1:1556bcaaf759 | 96 | wm8994_Resume, |
| DL3LD | 1:1556bcaaf759 | 97 | wm8994_Stop, |
| DL3LD | 1:1556bcaaf759 | 98 | |
| DL3LD | 1:1556bcaaf759 | 99 | wm8994_SetFrequency, |
| DL3LD | 1:1556bcaaf759 | 100 | wm8994_SetVolume, |
| DL3LD | 1:1556bcaaf759 | 101 | wm8994_SetMute, |
| DL3LD | 1:1556bcaaf759 | 102 | wm8994_SetOutputMode, |
| DL3LD | 1:1556bcaaf759 | 103 | |
| DL3LD | 1:1556bcaaf759 | 104 | wm8994_Reset |
| DL3LD | 1:1556bcaaf759 | 105 | }; |
| DL3LD | 1:1556bcaaf759 | 106 | |
| DL3LD | 1:1556bcaaf759 | 107 | static uint32_t outputEnabled = 0; |
| DL3LD | 1:1556bcaaf759 | 108 | static uint32_t inputEnabled = 0; |
| DL3LD | 1:1556bcaaf759 | 109 | /** |
| DL3LD | 1:1556bcaaf759 | 110 | * @} |
| DL3LD | 1:1556bcaaf759 | 111 | */ |
| DL3LD | 1:1556bcaaf759 | 112 | |
| DL3LD | 1:1556bcaaf759 | 113 | /** @defgroup WM8994_Function_Prototypes |
| DL3LD | 1:1556bcaaf759 | 114 | * @{ |
| DL3LD | 1:1556bcaaf759 | 115 | */ |
| DL3LD | 1:1556bcaaf759 | 116 | static uint8_t CODEC_IO_Write(uint8_t Addr, uint16_t Reg, uint16_t Value); |
| DL3LD | 1:1556bcaaf759 | 117 | /** |
| DL3LD | 1:1556bcaaf759 | 118 | * @} |
| DL3LD | 1:1556bcaaf759 | 119 | */ |
| DL3LD | 1:1556bcaaf759 | 120 | |
| DL3LD | 1:1556bcaaf759 | 121 | /** @defgroup WM8994_Private_Functions |
| DL3LD | 1:1556bcaaf759 | 122 | * @{ |
| DL3LD | 1:1556bcaaf759 | 123 | */ |
| DL3LD | 1:1556bcaaf759 | 124 | |
| DL3LD | 1:1556bcaaf759 | 125 | /** |
| DL3LD | 1:1556bcaaf759 | 126 | * @brief Initializes the audio codec and the control interface. |
| DL3LD | 1:1556bcaaf759 | 127 | * @param DeviceAddr: Device address on communication Bus. |
| DL3LD | 1:1556bcaaf759 | 128 | * @param OutputInputDevice: can be OUTPUT_DEVICE_SPEAKER, OUTPUT_DEVICE_HEADPHONE, |
| DL3LD | 1:1556bcaaf759 | 129 | * OUTPUT_DEVICE_BOTH, OUTPUT_DEVICE_AUTO, INPUT_DEVICE_DIGITAL_MICROPHONE_1, |
| DL3LD | 1:1556bcaaf759 | 130 | * INPUT_DEVICE_DIGITAL_MICROPHONE_2, INPUT_DEVICE_INPUT_LINE_1 or INPUT_DEVICE_INPUT_LINE_2. |
| DL3LD | 1:1556bcaaf759 | 131 | * @param Volume: Initial volume level (from 0 (Mute) to 100 (Max)) |
| DL3LD | 1:1556bcaaf759 | 132 | * @param AudioFreq: Audio Frequency |
| DL3LD | 1:1556bcaaf759 | 133 | * @retval 0 if correct communication, else wrong communication |
| DL3LD | 1:1556bcaaf759 | 134 | */ |
| DL3LD | 1:1556bcaaf759 | 135 | uint32_t wm8994_Init(uint16_t DeviceAddr, uint16_t OutputInputDevice, uint8_t Volume, uint32_t AudioFreq) |
| DL3LD | 1:1556bcaaf759 | 136 | { |
| DL3LD | 1:1556bcaaf759 | 137 | uint32_t counter = 0; |
| DL3LD | 1:1556bcaaf759 | 138 | uint16_t output_device = OutputInputDevice & 0xFF; |
| DL3LD | 1:1556bcaaf759 | 139 | uint16_t input_device = OutputInputDevice & 0xFF00; |
| DL3LD | 1:1556bcaaf759 | 140 | uint16_t power_mgnt_reg_1 = 0; |
| DL3LD | 1:1556bcaaf759 | 141 | |
| DL3LD | 1:1556bcaaf759 | 142 | /* Initialize the Control interface of the Audio Codec */ |
| DL3LD | 1:1556bcaaf759 | 143 | AUDIO_IO_Init(); |
| DL3LD | 1:1556bcaaf759 | 144 | /* wm8994 Errata Work-Arounds */ |
| DL3LD | 1:1556bcaaf759 | 145 | counter += CODEC_IO_Write(DeviceAddr, 0x102, 0x0003); |
| DL3LD | 1:1556bcaaf759 | 146 | counter += CODEC_IO_Write(DeviceAddr, 0x817, 0x0000); |
| DL3LD | 1:1556bcaaf759 | 147 | counter += CODEC_IO_Write(DeviceAddr, 0x102, 0x0000); |
| DL3LD | 1:1556bcaaf759 | 148 | |
| DL3LD | 1:1556bcaaf759 | 149 | /* Enable VMID soft start (fast), Start-up Bias Current Enabled */ |
| DL3LD | 1:1556bcaaf759 | 150 | counter += CODEC_IO_Write(DeviceAddr, 0x39, 0x006C); |
| DL3LD | 1:1556bcaaf759 | 151 | |
| DL3LD | 1:1556bcaaf759 | 152 | /* Enable bias generator, Enable VMID */ |
| DL3LD | 1:1556bcaaf759 | 153 | counter += CODEC_IO_Write(DeviceAddr, 0x01, 0x0003); |
| DL3LD | 1:1556bcaaf759 | 154 | |
| DL3LD | 1:1556bcaaf759 | 155 | /* Add Delay */ |
| DL3LD | 1:1556bcaaf759 | 156 | AUDIO_IO_Delay(50); |
| DL3LD | 1:1556bcaaf759 | 157 | |
| DL3LD | 1:1556bcaaf759 | 158 | /* Path Configurations for output */ |
| DL3LD | 1:1556bcaaf759 | 159 | if (output_device > 0) |
| DL3LD | 1:1556bcaaf759 | 160 | { |
| DL3LD | 1:1556bcaaf759 | 161 | outputEnabled = 1; |
| DL3LD | 1:1556bcaaf759 | 162 | switch (output_device) |
| DL3LD | 1:1556bcaaf759 | 163 | { |
| DL3LD | 1:1556bcaaf759 | 164 | case OUTPUT_DEVICE_SPEAKER: |
| DL3LD | 1:1556bcaaf759 | 165 | /* Enable DAC1 (Left), Enable DAC1 (Right), |
| DL3LD | 1:1556bcaaf759 | 166 | Disable DAC2 (Left), Disable DAC2 (Right)*/ |
| DL3LD | 1:1556bcaaf759 | 167 | counter += CODEC_IO_Write(DeviceAddr, 0x05, 0x0C0C); |
| DL3LD | 1:1556bcaaf759 | 168 | |
| DL3LD | 1:1556bcaaf759 | 169 | /* Enable the AIF1 Timeslot 0 (Left) to DAC 1 (Left) mixer path */ |
| DL3LD | 1:1556bcaaf759 | 170 | counter += CODEC_IO_Write(DeviceAddr, 0x601, 0x0000); |
| DL3LD | 1:1556bcaaf759 | 171 | |
| DL3LD | 1:1556bcaaf759 | 172 | /* Enable the AIF1 Timeslot 0 (Right) to DAC 1 (Right) mixer path */ |
| DL3LD | 1:1556bcaaf759 | 173 | counter += CODEC_IO_Write(DeviceAddr, 0x602, 0x0000); |
| DL3LD | 1:1556bcaaf759 | 174 | |
| DL3LD | 1:1556bcaaf759 | 175 | /* Disable the AIF1 Timeslot 1 (Left) to DAC 2 (Left) mixer path */ |
| DL3LD | 1:1556bcaaf759 | 176 | counter += CODEC_IO_Write(DeviceAddr, 0x604, 0x0002); |
| DL3LD | 1:1556bcaaf759 | 177 | |
| DL3LD | 1:1556bcaaf759 | 178 | /* Disable the AIF1 Timeslot 1 (Right) to DAC 2 (Right) mixer path */ |
| DL3LD | 1:1556bcaaf759 | 179 | counter += CODEC_IO_Write(DeviceAddr, 0x605, 0x0002); |
| DL3LD | 1:1556bcaaf759 | 180 | break; |
| DL3LD | 1:1556bcaaf759 | 181 | |
| DL3LD | 1:1556bcaaf759 | 182 | case OUTPUT_DEVICE_HEADPHONE: |
| DL3LD | 1:1556bcaaf759 | 183 | /* Disable DAC1 (Left), Disable DAC1 (Right), |
| DL3LD | 1:1556bcaaf759 | 184 | Enable DAC2 (Left), Enable DAC2 (Right)*/ |
| DL3LD | 1:1556bcaaf759 | 185 | counter += CODEC_IO_Write(DeviceAddr, 0x05, 0x0303); |
| DL3LD | 1:1556bcaaf759 | 186 | |
| DL3LD | 1:1556bcaaf759 | 187 | /* Enable the AIF1 Timeslot 0 (Left) to DAC 1 (Left) mixer path */ |
| DL3LD | 1:1556bcaaf759 | 188 | counter += CODEC_IO_Write(DeviceAddr, 0x601, 0x0001); |
| DL3LD | 1:1556bcaaf759 | 189 | |
| DL3LD | 1:1556bcaaf759 | 190 | /* Enable the AIF1 Timeslot 0 (Right) to DAC 1 (Right) mixer path */ |
| DL3LD | 1:1556bcaaf759 | 191 | counter += CODEC_IO_Write(DeviceAddr, 0x602, 0x0001); |
| DL3LD | 1:1556bcaaf759 | 192 | |
| DL3LD | 1:1556bcaaf759 | 193 | /* Disable the AIF1 Timeslot 1 (Left) to DAC 2 (Left) mixer path */ |
| DL3LD | 1:1556bcaaf759 | 194 | counter += CODEC_IO_Write(DeviceAddr, 0x604, 0x0000); |
| DL3LD | 1:1556bcaaf759 | 195 | |
| DL3LD | 1:1556bcaaf759 | 196 | /* Disable the AIF1 Timeslot 1 (Right) to DAC 2 (Right) mixer path */ |
| DL3LD | 1:1556bcaaf759 | 197 | counter += CODEC_IO_Write(DeviceAddr, 0x605, 0x0000); |
| DL3LD | 1:1556bcaaf759 | 198 | break; |
| DL3LD | 1:1556bcaaf759 | 199 | |
| DL3LD | 1:1556bcaaf759 | 200 | case OUTPUT_DEVICE_BOTH: |
| DL3LD | 1:1556bcaaf759 | 201 | /* Enable DAC1 (Left), Enable DAC1 (Right), |
| DL3LD | 1:1556bcaaf759 | 202 | also Enable DAC2 (Left), Enable DAC2 (Right)*/ |
| DL3LD | 1:1556bcaaf759 | 203 | counter += CODEC_IO_Write(DeviceAddr, 0x05, 0x0303 | 0x0C0C); |
| DL3LD | 1:1556bcaaf759 | 204 | |
| DL3LD | 1:1556bcaaf759 | 205 | /* Enable the AIF1 Timeslot 0 (Left) to DAC 1 (Left) mixer path */ |
| DL3LD | 1:1556bcaaf759 | 206 | counter += CODEC_IO_Write(DeviceAddr, 0x601, 0x0001); |
| DL3LD | 1:1556bcaaf759 | 207 | |
| DL3LD | 1:1556bcaaf759 | 208 | /* Enable the AIF1 Timeslot 0 (Right) to DAC 1 (Right) mixer path */ |
| DL3LD | 1:1556bcaaf759 | 209 | counter += CODEC_IO_Write(DeviceAddr, 0x602, 0x0001); |
| DL3LD | 1:1556bcaaf759 | 210 | |
| DL3LD | 1:1556bcaaf759 | 211 | /* Enable the AIF1 Timeslot 1 (Left) to DAC 2 (Left) mixer path */ |
| DL3LD | 1:1556bcaaf759 | 212 | counter += CODEC_IO_Write(DeviceAddr, 0x604, 0x0002); |
| DL3LD | 1:1556bcaaf759 | 213 | |
| DL3LD | 1:1556bcaaf759 | 214 | /* Enable the AIF1 Timeslot 1 (Right) to DAC 2 (Right) mixer path */ |
| DL3LD | 1:1556bcaaf759 | 215 | counter += CODEC_IO_Write(DeviceAddr, 0x605, 0x0002); |
| DL3LD | 1:1556bcaaf759 | 216 | break; |
| DL3LD | 1:1556bcaaf759 | 217 | |
| DL3LD | 1:1556bcaaf759 | 218 | case OUTPUT_DEVICE_AUTO : |
| DL3LD | 1:1556bcaaf759 | 219 | default: |
| DL3LD | 1:1556bcaaf759 | 220 | /* Disable DAC1 (Left), Disable DAC1 (Right), |
| DL3LD | 1:1556bcaaf759 | 221 | Enable DAC2 (Left), Enable DAC2 (Right)*/ |
| DL3LD | 1:1556bcaaf759 | 222 | counter += CODEC_IO_Write(DeviceAddr, 0x05, 0x0303); |
| DL3LD | 1:1556bcaaf759 | 223 | |
| DL3LD | 1:1556bcaaf759 | 224 | /* Enable the AIF1 Timeslot 0 (Left) to DAC 1 (Left) mixer path */ |
| DL3LD | 1:1556bcaaf759 | 225 | counter += CODEC_IO_Write(DeviceAddr, 0x601, 0x0001); |
| DL3LD | 1:1556bcaaf759 | 226 | |
| DL3LD | 1:1556bcaaf759 | 227 | /* Enable the AIF1 Timeslot 0 (Right) to DAC 1 (Right) mixer path */ |
| DL3LD | 1:1556bcaaf759 | 228 | counter += CODEC_IO_Write(DeviceAddr, 0x602, 0x0001); |
| DL3LD | 1:1556bcaaf759 | 229 | |
| DL3LD | 1:1556bcaaf759 | 230 | /* Disable the AIF1 Timeslot 1 (Left) to DAC 2 (Left) mixer path */ |
| DL3LD | 1:1556bcaaf759 | 231 | counter += CODEC_IO_Write(DeviceAddr, 0x604, 0x0000); |
| DL3LD | 1:1556bcaaf759 | 232 | |
| DL3LD | 1:1556bcaaf759 | 233 | /* Disable the AIF1 Timeslot 1 (Right) to DAC 2 (Right) mixer path */ |
| DL3LD | 1:1556bcaaf759 | 234 | counter += CODEC_IO_Write(DeviceAddr, 0x605, 0x0000); |
| DL3LD | 1:1556bcaaf759 | 235 | break; |
| DL3LD | 1:1556bcaaf759 | 236 | } |
| DL3LD | 1:1556bcaaf759 | 237 | } |
| DL3LD | 1:1556bcaaf759 | 238 | else |
| DL3LD | 1:1556bcaaf759 | 239 | { |
| DL3LD | 1:1556bcaaf759 | 240 | outputEnabled = 0; |
| DL3LD | 1:1556bcaaf759 | 241 | } |
| DL3LD | 1:1556bcaaf759 | 242 | |
| DL3LD | 1:1556bcaaf759 | 243 | /* Path Configurations for input */ |
| DL3LD | 1:1556bcaaf759 | 244 | if (input_device > 0) |
| DL3LD | 1:1556bcaaf759 | 245 | { |
| DL3LD | 1:1556bcaaf759 | 246 | inputEnabled = 1; |
| DL3LD | 1:1556bcaaf759 | 247 | switch (input_device) |
| DL3LD | 1:1556bcaaf759 | 248 | { |
| DL3LD | 1:1556bcaaf759 | 249 | case INPUT_DEVICE_DIGITAL_MICROPHONE_2 : |
| DL3LD | 1:1556bcaaf759 | 250 | /* Enable AIF1ADC2 (Left), Enable AIF1ADC2 (Right) |
| DL3LD | 1:1556bcaaf759 | 251 | * Enable DMICDAT2 (Left), Enable DMICDAT2 (Right) |
| DL3LD | 1:1556bcaaf759 | 252 | * Enable Left ADC, Enable Right ADC */ |
| DL3LD | 1:1556bcaaf759 | 253 | counter += CODEC_IO_Write(DeviceAddr, 0x04, 0x0C30); |
| DL3LD | 1:1556bcaaf759 | 254 | |
| DL3LD | 1:1556bcaaf759 | 255 | /* Enable AIF1 DRC2 Signal Detect & DRC in AIF1ADC2 Left/Right Timeslot 1 */ |
| DL3LD | 1:1556bcaaf759 | 256 | counter += CODEC_IO_Write(DeviceAddr, 0x450, 0x00DB); |
| DL3LD | 1:1556bcaaf759 | 257 | |
| DL3LD | 1:1556bcaaf759 | 258 | /* Disable IN1L, IN1R, IN2L, IN2R, Enable Thermal sensor & shutdown */ |
| DL3LD | 1:1556bcaaf759 | 259 | counter += CODEC_IO_Write(DeviceAddr, 0x02, 0x6000); |
| DL3LD | 1:1556bcaaf759 | 260 | |
| DL3LD | 1:1556bcaaf759 | 261 | /* Enable the DMIC2(Left) to AIF1 Timeslot 1 (Left) mixer path */ |
| DL3LD | 1:1556bcaaf759 | 262 | counter += CODEC_IO_Write(DeviceAddr, 0x608, 0x0002); |
| DL3LD | 1:1556bcaaf759 | 263 | |
| DL3LD | 1:1556bcaaf759 | 264 | /* Enable the DMIC2(Right) to AIF1 Timeslot 1 (Right) mixer path */ |
| DL3LD | 1:1556bcaaf759 | 265 | counter += CODEC_IO_Write(DeviceAddr, 0x609, 0x0002); |
| DL3LD | 1:1556bcaaf759 | 266 | |
| DL3LD | 1:1556bcaaf759 | 267 | /* GPIO1 pin configuration GP1_DIR = output, GP1_FN = AIF1 DRC2 signal detect */ |
| DL3LD | 1:1556bcaaf759 | 268 | counter += CODEC_IO_Write(DeviceAddr, 0x700, 0x000E); |
| DL3LD | 1:1556bcaaf759 | 269 | break; |
| DL3LD | 1:1556bcaaf759 | 270 | |
| DL3LD | 1:1556bcaaf759 | 271 | case INPUT_DEVICE_INPUT_LINE_1 : |
| DL3LD | 1:1556bcaaf759 | 272 | /* Enable AIF1ADC1 (Left), Enable AIF1ADC1 (Right) |
| DL3LD | 1:1556bcaaf759 | 273 | * Enable Left ADC, Enable Right ADC */ |
| DL3LD | 1:1556bcaaf759 | 274 | counter += CODEC_IO_Write(DeviceAddr, 0x04, 0x0303); |
| DL3LD | 1:1556bcaaf759 | 275 | |
| DL3LD | 1:1556bcaaf759 | 276 | /* Enable AIF1 DRC1 Signal Detect & DRC in AIF1ADC1 Left/Right Timeslot 0 */ |
| DL3LD | 1:1556bcaaf759 | 277 | counter += CODEC_IO_Write(DeviceAddr, 0x440, 0x00DB); |
| DL3LD | 1:1556bcaaf759 | 278 | |
| DL3LD | 1:1556bcaaf759 | 279 | /* Enable IN1L and IN1R, Disable IN2L and IN2R, Enable Thermal sensor & shutdown */ |
| DL3LD | 1:1556bcaaf759 | 280 | counter += CODEC_IO_Write(DeviceAddr, 0x02, 0x6350); |
| DL3LD | 1:1556bcaaf759 | 281 | |
| DL3LD | 1:1556bcaaf759 | 282 | /* Enable the ADCL(Left) to AIF1 Timeslot 0 (Left) mixer path */ |
| DL3LD | 1:1556bcaaf759 | 283 | counter += CODEC_IO_Write(DeviceAddr, 0x606, 0x0002); |
| DL3LD | 1:1556bcaaf759 | 284 | |
| DL3LD | 1:1556bcaaf759 | 285 | /* Enable the ADCR(Right) to AIF1 Timeslot 0 (Right) mixer path */ |
| DL3LD | 1:1556bcaaf759 | 286 | counter += CODEC_IO_Write(DeviceAddr, 0x607, 0x0002); |
| DL3LD | 1:1556bcaaf759 | 287 | |
| DL3LD | 1:1556bcaaf759 | 288 | /* GPIO1 pin configuration GP1_DIR = output, GP1_FN = AIF1 DRC1 signal detect */ |
| DL3LD | 1:1556bcaaf759 | 289 | counter += CODEC_IO_Write(DeviceAddr, 0x700, 0x000D); |
| DL3LD | 1:1556bcaaf759 | 290 | break; |
| DL3LD | 1:1556bcaaf759 | 291 | |
| DL3LD | 1:1556bcaaf759 | 292 | case INPUT_DEVICE_DIGITAL_MICROPHONE_1 : |
| DL3LD | 1:1556bcaaf759 | 293 | case INPUT_DEVICE_INPUT_LINE_2 : |
| DL3LD | 1:1556bcaaf759 | 294 | default: |
| DL3LD | 1:1556bcaaf759 | 295 | /* Actually, no other input devices supported */ |
| DL3LD | 1:1556bcaaf759 | 296 | counter++; |
| DL3LD | 1:1556bcaaf759 | 297 | break; |
| DL3LD | 1:1556bcaaf759 | 298 | } |
| DL3LD | 1:1556bcaaf759 | 299 | } |
| DL3LD | 1:1556bcaaf759 | 300 | else |
| DL3LD | 1:1556bcaaf759 | 301 | { |
| DL3LD | 1:1556bcaaf759 | 302 | inputEnabled = 0; |
| DL3LD | 1:1556bcaaf759 | 303 | } |
| DL3LD | 1:1556bcaaf759 | 304 | |
| DL3LD | 1:1556bcaaf759 | 305 | /* Clock Configurations */ |
| DL3LD | 1:1556bcaaf759 | 306 | switch (AudioFreq) |
| DL3LD | 1:1556bcaaf759 | 307 | { |
| DL3LD | 1:1556bcaaf759 | 308 | case AUDIO_FREQUENCY_8K: |
| DL3LD | 1:1556bcaaf759 | 309 | /* AIF1 Sample Rate = 8 (KHz), ratio=256 */ |
| DL3LD | 1:1556bcaaf759 | 310 | counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0003); |
| DL3LD | 1:1556bcaaf759 | 311 | break; |
| DL3LD | 1:1556bcaaf759 | 312 | |
| DL3LD | 1:1556bcaaf759 | 313 | case AUDIO_FREQUENCY_16K: |
| DL3LD | 1:1556bcaaf759 | 314 | /* AIF1 Sample Rate = 16 (KHz), ratio=256 */ |
| DL3LD | 1:1556bcaaf759 | 315 | counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0033); |
| DL3LD | 1:1556bcaaf759 | 316 | break; |
| DL3LD | 1:1556bcaaf759 | 317 | |
| DL3LD | 1:1556bcaaf759 | 318 | case AUDIO_FREQUENCY_48K: |
| DL3LD | 1:1556bcaaf759 | 319 | /* AIF1 Sample Rate = 48 (KHz), ratio=256 */ |
| DL3LD | 1:1556bcaaf759 | 320 | counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0083); |
| DL3LD | 1:1556bcaaf759 | 321 | break; |
| DL3LD | 1:1556bcaaf759 | 322 | |
| DL3LD | 1:1556bcaaf759 | 323 | case AUDIO_FREQUENCY_96K: |
| DL3LD | 1:1556bcaaf759 | 324 | /* AIF1 Sample Rate = 96 (KHz), ratio=256 */ |
| DL3LD | 1:1556bcaaf759 | 325 | counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x00A3); |
| DL3LD | 1:1556bcaaf759 | 326 | break; |
| DL3LD | 1:1556bcaaf759 | 327 | |
| DL3LD | 1:1556bcaaf759 | 328 | case AUDIO_FREQUENCY_11K: |
| DL3LD | 1:1556bcaaf759 | 329 | /* AIF1 Sample Rate = 11.025 (KHz), ratio=256 */ |
| DL3LD | 1:1556bcaaf759 | 330 | counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0013); |
| DL3LD | 1:1556bcaaf759 | 331 | break; |
| DL3LD | 1:1556bcaaf759 | 332 | |
| DL3LD | 1:1556bcaaf759 | 333 | case AUDIO_FREQUENCY_22K: |
| DL3LD | 1:1556bcaaf759 | 334 | /* AIF1 Sample Rate = 22.050 (KHz), ratio=256 */ |
| DL3LD | 1:1556bcaaf759 | 335 | counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0043); |
| DL3LD | 1:1556bcaaf759 | 336 | break; |
| DL3LD | 1:1556bcaaf759 | 337 | |
| DL3LD | 1:1556bcaaf759 | 338 | case AUDIO_FREQUENCY_44K: |
| DL3LD | 1:1556bcaaf759 | 339 | /* AIF1 Sample Rate = 44.1 (KHz), ratio=256 */ |
| DL3LD | 1:1556bcaaf759 | 340 | counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0073); |
| DL3LD | 1:1556bcaaf759 | 341 | break; |
| DL3LD | 1:1556bcaaf759 | 342 | |
| DL3LD | 1:1556bcaaf759 | 343 | default: |
| DL3LD | 1:1556bcaaf759 | 344 | /* AIF1 Sample Rate = 48 (KHz), ratio=256 */ |
| DL3LD | 1:1556bcaaf759 | 345 | counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0083); |
| DL3LD | 1:1556bcaaf759 | 346 | break; |
| DL3LD | 1:1556bcaaf759 | 347 | } |
| DL3LD | 1:1556bcaaf759 | 348 | /* AIF1 Word Length = 16-bits, AIF1 Format = I2S (Default Register Value) */ |
| DL3LD | 1:1556bcaaf759 | 349 | counter += CODEC_IO_Write(DeviceAddr, 0x300, 0x4010); |
| DL3LD | 1:1556bcaaf759 | 350 | |
| DL3LD | 1:1556bcaaf759 | 351 | /* slave mode */ |
| DL3LD | 1:1556bcaaf759 | 352 | counter += CODEC_IO_Write(DeviceAddr, 0x302, 0x0000); |
| DL3LD | 1:1556bcaaf759 | 353 | |
| DL3LD | 1:1556bcaaf759 | 354 | /* Enable the DSP processing clock for AIF1, Enable the core clock */ |
| DL3LD | 1:1556bcaaf759 | 355 | counter += CODEC_IO_Write(DeviceAddr, 0x208, 0x000A); |
| DL3LD | 1:1556bcaaf759 | 356 | |
| DL3LD | 1:1556bcaaf759 | 357 | /* Enable AIF1 Clock, AIF1 Clock Source = MCLK1 pin */ |
| DL3LD | 1:1556bcaaf759 | 358 | counter += CODEC_IO_Write(DeviceAddr, 0x200, 0x0001); |
| DL3LD | 1:1556bcaaf759 | 359 | |
| DL3LD | 1:1556bcaaf759 | 360 | if (output_device > 0) /* Audio output selected */ |
| DL3LD | 1:1556bcaaf759 | 361 | { |
| DL3LD | 1:1556bcaaf759 | 362 | /* Analog Output Configuration */ |
| DL3LD | 1:1556bcaaf759 | 363 | |
| DL3LD | 1:1556bcaaf759 | 364 | /* Enable SPKRVOL PGA, Enable SPKMIXR, Enable SPKLVOL PGA, Enable SPKMIXL */ |
| DL3LD | 1:1556bcaaf759 | 365 | counter += CODEC_IO_Write(DeviceAddr, 0x03, 0x0300); |
| DL3LD | 1:1556bcaaf759 | 366 | |
| DL3LD | 1:1556bcaaf759 | 367 | /* Left Speaker Mixer Volume = 0dB */ |
| DL3LD | 1:1556bcaaf759 | 368 | counter += CODEC_IO_Write(DeviceAddr, 0x22, 0x0000); |
| DL3LD | 1:1556bcaaf759 | 369 | |
| DL3LD | 1:1556bcaaf759 | 370 | /* Speaker output mode = Class D, Right Speaker Mixer Volume = 0dB ((0x23, 0x0100) = class AB)*/ |
| DL3LD | 1:1556bcaaf759 | 371 | counter += CODEC_IO_Write(DeviceAddr, 0x23, 0x0000); |
| DL3LD | 1:1556bcaaf759 | 372 | |
| DL3LD | 1:1556bcaaf759 | 373 | /* Unmute DAC2 (Left) to Left Speaker Mixer (SPKMIXL) path, |
| DL3LD | 1:1556bcaaf759 | 374 | Unmute DAC2 (Right) to Right Speaker Mixer (SPKMIXR) path */ |
| DL3LD | 1:1556bcaaf759 | 375 | counter += CODEC_IO_Write(DeviceAddr, 0x36, 0x0300); |
| DL3LD | 1:1556bcaaf759 | 376 | |
| DL3LD | 1:1556bcaaf759 | 377 | /* Enable bias generator, Enable VMID, Enable SPKOUTL, Enable SPKOUTR */ |
| DL3LD | 1:1556bcaaf759 | 378 | counter += CODEC_IO_Write(DeviceAddr, 0x01, 0x3003); |
| DL3LD | 1:1556bcaaf759 | 379 | |
| DL3LD | 1:1556bcaaf759 | 380 | /* Headphone/Speaker Enable */ |
| DL3LD | 1:1556bcaaf759 | 381 | |
| DL3LD | 1:1556bcaaf759 | 382 | /* Enable Class W, Class W Envelope Tracking = AIF1 Timeslot 0 */ |
| DL3LD | 1:1556bcaaf759 | 383 | counter += CODEC_IO_Write(DeviceAddr, 0x51, 0x0005); |
| DL3LD | 1:1556bcaaf759 | 384 | |
| DL3LD | 1:1556bcaaf759 | 385 | /* Enable bias generator, Enable VMID, Enable HPOUT1 (Left) and Enable HPOUT1 (Right) input stages */ |
| DL3LD | 1:1556bcaaf759 | 386 | /* idem for Speaker */ |
| DL3LD | 1:1556bcaaf759 | 387 | power_mgnt_reg_1 |= 0x0303 | 0x3003; |
| DL3LD | 1:1556bcaaf759 | 388 | counter += CODEC_IO_Write(DeviceAddr, 0x01, power_mgnt_reg_1); |
| DL3LD | 1:1556bcaaf759 | 389 | |
| DL3LD | 1:1556bcaaf759 | 390 | /* Enable HPOUT1 (Left) and HPOUT1 (Right) intermediate stages */ |
| DL3LD | 1:1556bcaaf759 | 391 | counter += CODEC_IO_Write(DeviceAddr, 0x60, 0x0022); |
| DL3LD | 1:1556bcaaf759 | 392 | |
| DL3LD | 1:1556bcaaf759 | 393 | /* Enable Charge Pump */ |
| DL3LD | 1:1556bcaaf759 | 394 | counter += CODEC_IO_Write(DeviceAddr, 0x4C, 0x9F25); |
| DL3LD | 1:1556bcaaf759 | 395 | |
| DL3LD | 1:1556bcaaf759 | 396 | /* Add Delay */ |
| DL3LD | 1:1556bcaaf759 | 397 | AUDIO_IO_Delay(15); |
| DL3LD | 1:1556bcaaf759 | 398 | |
| DL3LD | 1:1556bcaaf759 | 399 | /* Select DAC1 (Left) to Left Headphone Output PGA (HPOUT1LVOL) path */ |
| DL3LD | 1:1556bcaaf759 | 400 | counter += CODEC_IO_Write(DeviceAddr, 0x2D, 0x0001); |
| DL3LD | 1:1556bcaaf759 | 401 | |
| DL3LD | 1:1556bcaaf759 | 402 | /* Select DAC1 (Right) to Right Headphone Output PGA (HPOUT1RVOL) path */ |
| DL3LD | 1:1556bcaaf759 | 403 | counter += CODEC_IO_Write(DeviceAddr, 0x2E, 0x0001); |
| DL3LD | 1:1556bcaaf759 | 404 | |
| DL3LD | 1:1556bcaaf759 | 405 | /* Enable Left Output Mixer (MIXOUTL), Enable Right Output Mixer (MIXOUTR) */ |
| DL3LD | 1:1556bcaaf759 | 406 | /* idem for SPKOUTL and SPKOUTR */ |
| DL3LD | 1:1556bcaaf759 | 407 | counter += CODEC_IO_Write(DeviceAddr, 0x03, 0x0030 | 0x0300); |
| DL3LD | 1:1556bcaaf759 | 408 | |
| DL3LD | 1:1556bcaaf759 | 409 | /* Enable DC Servo and trigger start-up mode on left and right channels */ |
| DL3LD | 1:1556bcaaf759 | 410 | counter += CODEC_IO_Write(DeviceAddr, 0x54, 0x0033); |
| DL3LD | 1:1556bcaaf759 | 411 | |
| DL3LD | 1:1556bcaaf759 | 412 | /* Add Delay */ |
| DL3LD | 1:1556bcaaf759 | 413 | AUDIO_IO_Delay(250); |
| DL3LD | 1:1556bcaaf759 | 414 | |
| DL3LD | 1:1556bcaaf759 | 415 | /* Enable HPOUT1 (Left) and HPOUT1 (Right) intermediate and output stages. Remove clamps */ |
| DL3LD | 1:1556bcaaf759 | 416 | counter += CODEC_IO_Write(DeviceAddr, 0x60, 0x00EE); |
| DL3LD | 1:1556bcaaf759 | 417 | |
| DL3LD | 1:1556bcaaf759 | 418 | /* Unmutes */ |
| DL3LD | 1:1556bcaaf759 | 419 | |
| DL3LD | 1:1556bcaaf759 | 420 | /* Unmute DAC 1 (Left) */ |
| DL3LD | 1:1556bcaaf759 | 421 | counter += CODEC_IO_Write(DeviceAddr, 0x610, 0x00C0); |
| DL3LD | 1:1556bcaaf759 | 422 | |
| DL3LD | 1:1556bcaaf759 | 423 | /* Unmute DAC 1 (Right) */ |
| DL3LD | 1:1556bcaaf759 | 424 | counter += CODEC_IO_Write(DeviceAddr, 0x611, 0x00C0); |
| DL3LD | 1:1556bcaaf759 | 425 | |
| DL3LD | 1:1556bcaaf759 | 426 | /* Unmute the AIF1 Timeslot 0 DAC path */ |
| DL3LD | 1:1556bcaaf759 | 427 | counter += CODEC_IO_Write(DeviceAddr, 0x420, 0x0000); |
| DL3LD | 1:1556bcaaf759 | 428 | |
| DL3LD | 1:1556bcaaf759 | 429 | /* Unmute DAC 2 (Left) */ |
| DL3LD | 1:1556bcaaf759 | 430 | counter += CODEC_IO_Write(DeviceAddr, 0x612, 0x00C0); |
| DL3LD | 1:1556bcaaf759 | 431 | |
| DL3LD | 1:1556bcaaf759 | 432 | /* Unmute DAC 2 (Right) */ |
| DL3LD | 1:1556bcaaf759 | 433 | counter += CODEC_IO_Write(DeviceAddr, 0x613, 0x00C0); |
| DL3LD | 1:1556bcaaf759 | 434 | |
| DL3LD | 1:1556bcaaf759 | 435 | /* Unmute the AIF1 Timeslot 1 DAC2 path */ |
| DL3LD | 1:1556bcaaf759 | 436 | counter += CODEC_IO_Write(DeviceAddr, 0x422, 0x0000); |
| DL3LD | 1:1556bcaaf759 | 437 | |
| DL3LD | 1:1556bcaaf759 | 438 | /* Volume Control */ |
| DL3LD | 1:1556bcaaf759 | 439 | wm8994_SetVolume(DeviceAddr, Volume); |
| DL3LD | 1:1556bcaaf759 | 440 | } |
| DL3LD | 1:1556bcaaf759 | 441 | |
| DL3LD | 1:1556bcaaf759 | 442 | if (input_device > 0) /* Audio input selected */ |
| DL3LD | 1:1556bcaaf759 | 443 | { |
| DL3LD | 1:1556bcaaf759 | 444 | if ((input_device == INPUT_DEVICE_DIGITAL_MICROPHONE_1) || (input_device == INPUT_DEVICE_DIGITAL_MICROPHONE_2)) |
| DL3LD | 1:1556bcaaf759 | 445 | { |
| DL3LD | 1:1556bcaaf759 | 446 | /* Enable Microphone bias 1 generator, Enable VMID */ |
| DL3LD | 1:1556bcaaf759 | 447 | power_mgnt_reg_1 |= 0x0013; |
| DL3LD | 1:1556bcaaf759 | 448 | counter += CODEC_IO_Write(DeviceAddr, 0x01, power_mgnt_reg_1); |
| DL3LD | 1:1556bcaaf759 | 449 | |
| DL3LD | 1:1556bcaaf759 | 450 | /* ADC oversample enable */ |
| DL3LD | 1:1556bcaaf759 | 451 | counter += CODEC_IO_Write(DeviceAddr, 0x620, 0x0002); |
| DL3LD | 1:1556bcaaf759 | 452 | |
| DL3LD | 1:1556bcaaf759 | 453 | /* AIF ADC2 HPF enable, HPF cut = voice mode 1 fc=127Hz at fs=8kHz */ |
| DL3LD | 1:1556bcaaf759 | 454 | counter += CODEC_IO_Write(DeviceAddr, 0x411, 0x3800); |
| DL3LD | 1:1556bcaaf759 | 455 | } |
| DL3LD | 1:1556bcaaf759 | 456 | else if ((input_device == INPUT_DEVICE_INPUT_LINE_1) || (input_device == INPUT_DEVICE_INPUT_LINE_2)) |
| DL3LD | 1:1556bcaaf759 | 457 | { |
| DL3LD | 1:1556bcaaf759 | 458 | /* Enable normal bias generator, Enable VMID */ |
| DL3LD | 1:1556bcaaf759 | 459 | power_mgnt_reg_1 |= 0x0003; |
| DL3LD | 1:1556bcaaf759 | 460 | counter += CODEC_IO_Write(DeviceAddr, 0x01, power_mgnt_reg_1); |
| DL3LD | 1:1556bcaaf759 | 461 | |
| DL3LD | 1:1556bcaaf759 | 462 | /* Disable mute on IN1L, IN1L Volume = +0dB */ |
| DL3LD | 1:1556bcaaf759 | 463 | counter += CODEC_IO_Write(DeviceAddr, 0x18, 0x000B); |
| DL3LD | 1:1556bcaaf759 | 464 | |
| DL3LD | 1:1556bcaaf759 | 465 | /* Disable mute on IN1R, IN1R Volume = +0dB */ |
| DL3LD | 1:1556bcaaf759 | 466 | counter += CODEC_IO_Write(DeviceAddr, 0x1A, 0x000B); |
| DL3LD | 1:1556bcaaf759 | 467 | |
| DL3LD | 1:1556bcaaf759 | 468 | /* Disable mute on IN1L_TO_MIXINL, Gain = +0dB */ |
| DL3LD | 1:1556bcaaf759 | 469 | counter += CODEC_IO_Write(DeviceAddr, 0x29, 0x0025); |
| DL3LD | 1:1556bcaaf759 | 470 | |
| DL3LD | 1:1556bcaaf759 | 471 | /* Disable mute on IN1R_TO_MIXINL, Gain = +0dB */ |
| DL3LD | 1:1556bcaaf759 | 472 | counter += CODEC_IO_Write(DeviceAddr, 0x2A, 0x0025); |
| DL3LD | 1:1556bcaaf759 | 473 | |
| DL3LD | 1:1556bcaaf759 | 474 | /* IN1LN_TO_IN1L, IN1LP_TO_VMID, IN1RN_TO_IN1R, IN1RP_TO_VMID */ |
| DL3LD | 1:1556bcaaf759 | 475 | counter += CODEC_IO_Write(DeviceAddr, 0x28, 0x0011); |
| DL3LD | 1:1556bcaaf759 | 476 | |
| DL3LD | 1:1556bcaaf759 | 477 | /* AIF ADC1 HPF enable, HPF cut = hifi mode fc=4Hz at fs=48kHz */ |
| DL3LD | 1:1556bcaaf759 | 478 | counter += CODEC_IO_Write(DeviceAddr, 0x410, 0x1800); |
| DL3LD | 1:1556bcaaf759 | 479 | } |
| DL3LD | 1:1556bcaaf759 | 480 | /* Volume Control */ |
| DL3LD | 1:1556bcaaf759 | 481 | wm8994_SetVolume(DeviceAddr, Volume); |
| DL3LD | 1:1556bcaaf759 | 482 | } |
| DL3LD | 1:1556bcaaf759 | 483 | /* Return communication control value */ |
| DL3LD | 1:1556bcaaf759 | 484 | return counter; |
| DL3LD | 1:1556bcaaf759 | 485 | } |
| DL3LD | 1:1556bcaaf759 | 486 | |
| DL3LD | 1:1556bcaaf759 | 487 | /** |
| DL3LD | 1:1556bcaaf759 | 488 | * @brief Deinitializes the audio codec. |
| DL3LD | 1:1556bcaaf759 | 489 | * @param None |
| DL3LD | 1:1556bcaaf759 | 490 | * @retval None |
| DL3LD | 1:1556bcaaf759 | 491 | */ |
| DL3LD | 1:1556bcaaf759 | 492 | void wm8994_DeInit(void) |
| DL3LD | 1:1556bcaaf759 | 493 | { |
| DL3LD | 1:1556bcaaf759 | 494 | /* Deinitialize Audio Codec interface */ |
| DL3LD | 1:1556bcaaf759 | 495 | AUDIO_IO_DeInit(); |
| DL3LD | 1:1556bcaaf759 | 496 | } |
| DL3LD | 1:1556bcaaf759 | 497 | |
| DL3LD | 1:1556bcaaf759 | 498 | /** |
| DL3LD | 1:1556bcaaf759 | 499 | * @brief Get the WM8994 ID. |
| DL3LD | 1:1556bcaaf759 | 500 | * @param DeviceAddr: Device address on communication Bus. |
| DL3LD | 1:1556bcaaf759 | 501 | * @retval The WM8994 ID |
| DL3LD | 1:1556bcaaf759 | 502 | */ |
| DL3LD | 1:1556bcaaf759 | 503 | uint32_t wm8994_ReadID(uint16_t DeviceAddr) |
| DL3LD | 1:1556bcaaf759 | 504 | { |
| DL3LD | 1:1556bcaaf759 | 505 | /* Initialize the Control interface of the Audio Codec */ |
| DL3LD | 1:1556bcaaf759 | 506 | AUDIO_IO_Init(); |
| DL3LD | 1:1556bcaaf759 | 507 | |
| DL3LD | 1:1556bcaaf759 | 508 | return ((uint32_t)AUDIO_IO_Read(DeviceAddr, WM8994_CHIPID_ADDR)); |
| DL3LD | 1:1556bcaaf759 | 509 | } |
| DL3LD | 1:1556bcaaf759 | 510 | |
| DL3LD | 1:1556bcaaf759 | 511 | /** |
| DL3LD | 1:1556bcaaf759 | 512 | * @brief Start the audio Codec play feature. |
| DL3LD | 1:1556bcaaf759 | 513 | * @note For this codec no Play options are required. |
| DL3LD | 1:1556bcaaf759 | 514 | * @param DeviceAddr: Device address on communication Bus. |
| DL3LD | 1:1556bcaaf759 | 515 | * @retval 0 if correct communication, else wrong communication |
| DL3LD | 1:1556bcaaf759 | 516 | */ |
| DL3LD | 1:1556bcaaf759 | 517 | uint32_t wm8994_Play(uint16_t DeviceAddr, uint16_t* pBuffer, uint16_t Size) |
| DL3LD | 1:1556bcaaf759 | 518 | { |
| DL3LD | 1:1556bcaaf759 | 519 | uint32_t counter = 0; |
| DL3LD | 1:1556bcaaf759 | 520 | |
| DL3LD | 1:1556bcaaf759 | 521 | /* Resumes the audio file playing */ |
| DL3LD | 1:1556bcaaf759 | 522 | /* Unmute the output first */ |
| DL3LD | 1:1556bcaaf759 | 523 | counter += wm8994_SetMute(DeviceAddr, AUDIO_MUTE_OFF); |
| DL3LD | 1:1556bcaaf759 | 524 | |
| DL3LD | 1:1556bcaaf759 | 525 | return counter; |
| DL3LD | 1:1556bcaaf759 | 526 | } |
| DL3LD | 1:1556bcaaf759 | 527 | |
| DL3LD | 1:1556bcaaf759 | 528 | /** |
| DL3LD | 1:1556bcaaf759 | 529 | * @brief Pauses playing on the audio codec. |
| DL3LD | 1:1556bcaaf759 | 530 | * @param DeviceAddr: Device address on communication Bus. |
| DL3LD | 1:1556bcaaf759 | 531 | * @retval 0 if correct communication, else wrong communication |
| DL3LD | 1:1556bcaaf759 | 532 | */ |
| DL3LD | 1:1556bcaaf759 | 533 | uint32_t wm8994_Pause(uint16_t DeviceAddr) |
| DL3LD | 1:1556bcaaf759 | 534 | { |
| DL3LD | 1:1556bcaaf759 | 535 | uint32_t counter = 0; |
| DL3LD | 1:1556bcaaf759 | 536 | |
| DL3LD | 1:1556bcaaf759 | 537 | /* Pause the audio file playing */ |
| DL3LD | 1:1556bcaaf759 | 538 | /* Mute the output first */ |
| DL3LD | 1:1556bcaaf759 | 539 | counter += wm8994_SetMute(DeviceAddr, AUDIO_MUTE_ON); |
| DL3LD | 1:1556bcaaf759 | 540 | |
| DL3LD | 1:1556bcaaf759 | 541 | /* Put the Codec in Power save mode */ |
| DL3LD | 1:1556bcaaf759 | 542 | counter += CODEC_IO_Write(DeviceAddr, 0x02, 0x01); |
| DL3LD | 1:1556bcaaf759 | 543 | |
| DL3LD | 1:1556bcaaf759 | 544 | return counter; |
| DL3LD | 1:1556bcaaf759 | 545 | } |
| DL3LD | 1:1556bcaaf759 | 546 | |
| DL3LD | 1:1556bcaaf759 | 547 | /** |
| DL3LD | 1:1556bcaaf759 | 548 | * @brief Resumes playing on the audio codec. |
| DL3LD | 1:1556bcaaf759 | 549 | * @param DeviceAddr: Device address on communication Bus. |
| DL3LD | 1:1556bcaaf759 | 550 | * @retval 0 if correct communication, else wrong communication |
| DL3LD | 1:1556bcaaf759 | 551 | */ |
| DL3LD | 1:1556bcaaf759 | 552 | uint32_t wm8994_Resume(uint16_t DeviceAddr) |
| DL3LD | 1:1556bcaaf759 | 553 | { |
| DL3LD | 1:1556bcaaf759 | 554 | uint32_t counter = 0; |
| DL3LD | 1:1556bcaaf759 | 555 | |
| DL3LD | 1:1556bcaaf759 | 556 | /* Resumes the audio file playing */ |
| DL3LD | 1:1556bcaaf759 | 557 | /* Unmute the output first */ |
| DL3LD | 1:1556bcaaf759 | 558 | counter += wm8994_SetMute(DeviceAddr, AUDIO_MUTE_OFF); |
| DL3LD | 1:1556bcaaf759 | 559 | |
| DL3LD | 1:1556bcaaf759 | 560 | return counter; |
| DL3LD | 1:1556bcaaf759 | 561 | } |
| DL3LD | 1:1556bcaaf759 | 562 | |
| DL3LD | 1:1556bcaaf759 | 563 | /** |
| DL3LD | 1:1556bcaaf759 | 564 | * @brief Stops audio Codec playing. It powers down the codec. |
| DL3LD | 1:1556bcaaf759 | 565 | * @param DeviceAddr: Device address on communication Bus. |
| DL3LD | 1:1556bcaaf759 | 566 | * @param CodecPdwnMode: selects the power down mode. |
| DL3LD | 1:1556bcaaf759 | 567 | * - CODEC_PDWN_SW: only mutes the audio codec. When resuming from this |
| DL3LD | 1:1556bcaaf759 | 568 | * mode the codec keeps the previous initialization |
| DL3LD | 1:1556bcaaf759 | 569 | * (no need to re-Initialize the codec registers). |
| DL3LD | 1:1556bcaaf759 | 570 | * - CODEC_PDWN_HW: Physically power down the codec. When resuming from this |
| DL3LD | 1:1556bcaaf759 | 571 | * mode, the codec is set to default configuration |
| DL3LD | 1:1556bcaaf759 | 572 | * (user should re-Initialize the codec in order to |
| DL3LD | 1:1556bcaaf759 | 573 | * play again the audio stream). |
| DL3LD | 1:1556bcaaf759 | 574 | * @retval 0 if correct communication, else wrong communication |
| DL3LD | 1:1556bcaaf759 | 575 | */ |
| DL3LD | 1:1556bcaaf759 | 576 | uint32_t wm8994_Stop(uint16_t DeviceAddr, uint32_t CodecPdwnMode) |
| DL3LD | 1:1556bcaaf759 | 577 | { |
| DL3LD | 1:1556bcaaf759 | 578 | uint32_t counter = 0; |
| DL3LD | 1:1556bcaaf759 | 579 | |
| DL3LD | 1:1556bcaaf759 | 580 | if (outputEnabled != 0) |
| DL3LD | 1:1556bcaaf759 | 581 | { |
| DL3LD | 1:1556bcaaf759 | 582 | /* Mute the output first */ |
| DL3LD | 1:1556bcaaf759 | 583 | counter += wm8994_SetMute(DeviceAddr, AUDIO_MUTE_ON); |
| DL3LD | 1:1556bcaaf759 | 584 | |
| DL3LD | 1:1556bcaaf759 | 585 | if (CodecPdwnMode == CODEC_PDWN_SW) |
| DL3LD | 1:1556bcaaf759 | 586 | { |
| DL3LD | 1:1556bcaaf759 | 587 | /* Only output mute required*/ |
| DL3LD | 1:1556bcaaf759 | 588 | } |
| DL3LD | 1:1556bcaaf759 | 589 | else /* CODEC_PDWN_HW */ |
| DL3LD | 1:1556bcaaf759 | 590 | { |
| DL3LD | 1:1556bcaaf759 | 591 | /* Mute the AIF1 Timeslot 0 DAC1 path */ |
| DL3LD | 1:1556bcaaf759 | 592 | counter += CODEC_IO_Write(DeviceAddr, 0x420, 0x0200); |
| DL3LD | 1:1556bcaaf759 | 593 | |
| DL3LD | 1:1556bcaaf759 | 594 | /* Mute the AIF1 Timeslot 1 DAC2 path */ |
| DL3LD | 1:1556bcaaf759 | 595 | counter += CODEC_IO_Write(DeviceAddr, 0x422, 0x0200); |
| DL3LD | 1:1556bcaaf759 | 596 | |
| DL3LD | 1:1556bcaaf759 | 597 | /* Disable DAC1L_TO_HPOUT1L */ |
| DL3LD | 1:1556bcaaf759 | 598 | counter += CODEC_IO_Write(DeviceAddr, 0x2D, 0x0000); |
| DL3LD | 1:1556bcaaf759 | 599 | |
| DL3LD | 1:1556bcaaf759 | 600 | /* Disable DAC1R_TO_HPOUT1R */ |
| DL3LD | 1:1556bcaaf759 | 601 | counter += CODEC_IO_Write(DeviceAddr, 0x2E, 0x0000); |
| DL3LD | 1:1556bcaaf759 | 602 | |
| DL3LD | 1:1556bcaaf759 | 603 | /* Disable DAC1 and DAC2 */ |
| DL3LD | 1:1556bcaaf759 | 604 | counter += CODEC_IO_Write(DeviceAddr, 0x05, 0x0000); |
| DL3LD | 1:1556bcaaf759 | 605 | |
| DL3LD | 1:1556bcaaf759 | 606 | /* Reset Codec by writing in 0x0000 address register */ |
| DL3LD | 1:1556bcaaf759 | 607 | counter += CODEC_IO_Write(DeviceAddr, 0x0000, 0x0000); |
| DL3LD | 1:1556bcaaf759 | 608 | |
| DL3LD | 1:1556bcaaf759 | 609 | outputEnabled = 0; |
| DL3LD | 1:1556bcaaf759 | 610 | } |
| DL3LD | 1:1556bcaaf759 | 611 | } |
| DL3LD | 1:1556bcaaf759 | 612 | return counter; |
| DL3LD | 1:1556bcaaf759 | 613 | } |
| DL3LD | 1:1556bcaaf759 | 614 | |
| DL3LD | 1:1556bcaaf759 | 615 | /** |
| DL3LD | 1:1556bcaaf759 | 616 | * @brief Sets higher or lower the codec volume level. |
| DL3LD | 1:1556bcaaf759 | 617 | * @param DeviceAddr: Device address on communication Bus. |
| DL3LD | 1:1556bcaaf759 | 618 | * @param Volume: a byte value from 0 to 255 (refer to codec registers |
| DL3LD | 1:1556bcaaf759 | 619 | * description for more details). |
| DL3LD | 1:1556bcaaf759 | 620 | * @retval 0 if correct communication, else wrong communication |
| DL3LD | 1:1556bcaaf759 | 621 | */ |
| DL3LD | 1:1556bcaaf759 | 622 | uint32_t wm8994_SetVolume(uint16_t DeviceAddr, uint8_t Volume) |
| DL3LD | 1:1556bcaaf759 | 623 | { |
| DL3LD | 1:1556bcaaf759 | 624 | uint32_t counter = 0; |
| DL3LD | 1:1556bcaaf759 | 625 | uint8_t convertedvol = VOLUME_CONVERT(Volume); |
| DL3LD | 1:1556bcaaf759 | 626 | |
| DL3LD | 1:1556bcaaf759 | 627 | /* Output volume */ |
| DL3LD | 1:1556bcaaf759 | 628 | if (outputEnabled != 0) |
| DL3LD | 1:1556bcaaf759 | 629 | { |
| DL3LD | 1:1556bcaaf759 | 630 | if(convertedvol > 0x3E) |
| DL3LD | 1:1556bcaaf759 | 631 | { |
| DL3LD | 1:1556bcaaf759 | 632 | /* Unmute audio codec */ |
| DL3LD | 1:1556bcaaf759 | 633 | counter += wm8994_SetMute(DeviceAddr, AUDIO_MUTE_OFF); |
| DL3LD | 1:1556bcaaf759 | 634 | |
| DL3LD | 1:1556bcaaf759 | 635 | /* Left Headphone Volume */ |
| DL3LD | 1:1556bcaaf759 | 636 | counter += CODEC_IO_Write(DeviceAddr, 0x1C, 0x3F | 0x140); |
| DL3LD | 1:1556bcaaf759 | 637 | |
| DL3LD | 1:1556bcaaf759 | 638 | /* Right Headphone Volume */ |
| DL3LD | 1:1556bcaaf759 | 639 | counter += CODEC_IO_Write(DeviceAddr, 0x1D, 0x3F | 0x140); |
| DL3LD | 1:1556bcaaf759 | 640 | |
| DL3LD | 1:1556bcaaf759 | 641 | /* Left Speaker Volume */ |
| DL3LD | 1:1556bcaaf759 | 642 | counter += CODEC_IO_Write(DeviceAddr, 0x26, 0x3F | 0x140); |
| DL3LD | 1:1556bcaaf759 | 643 | |
| DL3LD | 1:1556bcaaf759 | 644 | /* Right Speaker Volume */ |
| DL3LD | 1:1556bcaaf759 | 645 | counter += CODEC_IO_Write(DeviceAddr, 0x27, 0x3F | 0x140); |
| DL3LD | 1:1556bcaaf759 | 646 | } |
| DL3LD | 1:1556bcaaf759 | 647 | else if (Volume == 0) |
| DL3LD | 1:1556bcaaf759 | 648 | { |
| DL3LD | 1:1556bcaaf759 | 649 | /* Mute audio codec */ |
| DL3LD | 1:1556bcaaf759 | 650 | counter += wm8994_SetMute(DeviceAddr, AUDIO_MUTE_ON); |
| DL3LD | 1:1556bcaaf759 | 651 | } |
| DL3LD | 1:1556bcaaf759 | 652 | else |
| DL3LD | 1:1556bcaaf759 | 653 | { |
| DL3LD | 1:1556bcaaf759 | 654 | /* Unmute audio codec */ |
| DL3LD | 1:1556bcaaf759 | 655 | counter += wm8994_SetMute(DeviceAddr, AUDIO_MUTE_OFF); |
| DL3LD | 1:1556bcaaf759 | 656 | |
| DL3LD | 1:1556bcaaf759 | 657 | /* Left Headphone Volume */ |
| DL3LD | 1:1556bcaaf759 | 658 | counter += CODEC_IO_Write(DeviceAddr, 0x1C, convertedvol | 0x140); |
| DL3LD | 1:1556bcaaf759 | 659 | |
| DL3LD | 1:1556bcaaf759 | 660 | /* Right Headphone Volume */ |
| DL3LD | 1:1556bcaaf759 | 661 | counter += CODEC_IO_Write(DeviceAddr, 0x1D, convertedvol | 0x140); |
| DL3LD | 1:1556bcaaf759 | 662 | |
| DL3LD | 1:1556bcaaf759 | 663 | /* Left Speaker Volume */ |
| DL3LD | 1:1556bcaaf759 | 664 | counter += CODEC_IO_Write(DeviceAddr, 0x26, convertedvol | 0x140); |
| DL3LD | 1:1556bcaaf759 | 665 | |
| DL3LD | 1:1556bcaaf759 | 666 | /* Right Speaker Volume */ |
| DL3LD | 1:1556bcaaf759 | 667 | counter += CODEC_IO_Write(DeviceAddr, 0x27, convertedvol | 0x140); |
| DL3LD | 1:1556bcaaf759 | 668 | } |
| DL3LD | 1:1556bcaaf759 | 669 | } |
| DL3LD | 1:1556bcaaf759 | 670 | |
| DL3LD | 1:1556bcaaf759 | 671 | /* Input volume */ |
| DL3LD | 1:1556bcaaf759 | 672 | if (inputEnabled != 0) |
| DL3LD | 1:1556bcaaf759 | 673 | { |
| DL3LD | 1:1556bcaaf759 | 674 | convertedvol = VOLUME_IN_CONVERT(Volume); |
| DL3LD | 1:1556bcaaf759 | 675 | |
| DL3LD | 1:1556bcaaf759 | 676 | /* Left AIF1 ADC1 volume */ |
| DL3LD | 1:1556bcaaf759 | 677 | counter += CODEC_IO_Write(DeviceAddr, 0x400, convertedvol | 0x100); |
| DL3LD | 1:1556bcaaf759 | 678 | |
| DL3LD | 1:1556bcaaf759 | 679 | /* Right AIF1 ADC1 volume */ |
| DL3LD | 1:1556bcaaf759 | 680 | counter += CODEC_IO_Write(DeviceAddr, 0x401, convertedvol | 0x100); |
| DL3LD | 1:1556bcaaf759 | 681 | |
| DL3LD | 1:1556bcaaf759 | 682 | /* Left AIF1 ADC2 volume */ |
| DL3LD | 1:1556bcaaf759 | 683 | counter += CODEC_IO_Write(DeviceAddr, 0x404, convertedvol | 0x100); |
| DL3LD | 1:1556bcaaf759 | 684 | |
| DL3LD | 1:1556bcaaf759 | 685 | /* Right AIF1 ADC2 volume */ |
| DL3LD | 1:1556bcaaf759 | 686 | counter += CODEC_IO_Write(DeviceAddr, 0x405, convertedvol | 0x100); |
| DL3LD | 1:1556bcaaf759 | 687 | } |
| DL3LD | 1:1556bcaaf759 | 688 | return counter; |
| DL3LD | 1:1556bcaaf759 | 689 | } |
| DL3LD | 1:1556bcaaf759 | 690 | |
| DL3LD | 1:1556bcaaf759 | 691 | /** |
| DL3LD | 1:1556bcaaf759 | 692 | * @brief Enables or disables the mute feature on the audio codec. |
| DL3LD | 1:1556bcaaf759 | 693 | * @param DeviceAddr: Device address on communication Bus. |
| DL3LD | 1:1556bcaaf759 | 694 | * @param Cmd: AUDIO_MUTE_ON to enable the mute or AUDIO_MUTE_OFF to disable the |
| DL3LD | 1:1556bcaaf759 | 695 | * mute mode. |
| DL3LD | 1:1556bcaaf759 | 696 | * @retval 0 if correct communication, else wrong communication |
| DL3LD | 1:1556bcaaf759 | 697 | */ |
| DL3LD | 1:1556bcaaf759 | 698 | uint32_t wm8994_SetMute(uint16_t DeviceAddr, uint32_t Cmd) |
| DL3LD | 1:1556bcaaf759 | 699 | { |
| DL3LD | 1:1556bcaaf759 | 700 | uint32_t counter = 0; |
| DL3LD | 1:1556bcaaf759 | 701 | |
| DL3LD | 1:1556bcaaf759 | 702 | if (outputEnabled != 0) |
| DL3LD | 1:1556bcaaf759 | 703 | { |
| DL3LD | 1:1556bcaaf759 | 704 | /* Set the Mute mode */ |
| DL3LD | 1:1556bcaaf759 | 705 | if(Cmd == AUDIO_MUTE_ON) |
| DL3LD | 1:1556bcaaf759 | 706 | { |
| DL3LD | 1:1556bcaaf759 | 707 | /* Soft Mute the AIF1 Timeslot 0 DAC1 path L&R */ |
| DL3LD | 1:1556bcaaf759 | 708 | counter += CODEC_IO_Write(DeviceAddr, 0x420, 0x0200); |
| DL3LD | 1:1556bcaaf759 | 709 | |
| DL3LD | 1:1556bcaaf759 | 710 | /* Soft Mute the AIF1 Timeslot 1 DAC2 path L&R */ |
| DL3LD | 1:1556bcaaf759 | 711 | counter += CODEC_IO_Write(DeviceAddr, 0x422, 0x0200); |
| DL3LD | 1:1556bcaaf759 | 712 | } |
| DL3LD | 1:1556bcaaf759 | 713 | else /* AUDIO_MUTE_OFF Disable the Mute */ |
| DL3LD | 1:1556bcaaf759 | 714 | { |
| DL3LD | 1:1556bcaaf759 | 715 | /* Unmute the AIF1 Timeslot 0 DAC1 path L&R */ |
| DL3LD | 1:1556bcaaf759 | 716 | counter += CODEC_IO_Write(DeviceAddr, 0x420, 0x0000); |
| DL3LD | 1:1556bcaaf759 | 717 | |
| DL3LD | 1:1556bcaaf759 | 718 | /* Unmute the AIF1 Timeslot 1 DAC2 path L&R */ |
| DL3LD | 1:1556bcaaf759 | 719 | counter += CODEC_IO_Write(DeviceAddr, 0x422, 0x0000); |
| DL3LD | 1:1556bcaaf759 | 720 | } |
| DL3LD | 1:1556bcaaf759 | 721 | } |
| DL3LD | 1:1556bcaaf759 | 722 | return counter; |
| DL3LD | 1:1556bcaaf759 | 723 | } |
| DL3LD | 1:1556bcaaf759 | 724 | |
| DL3LD | 1:1556bcaaf759 | 725 | /** |
| DL3LD | 1:1556bcaaf759 | 726 | * @brief Switch dynamically (while audio file is played) the output target |
| DL3LD | 1:1556bcaaf759 | 727 | * (speaker or headphone). |
| DL3LD | 1:1556bcaaf759 | 728 | * @param DeviceAddr: Device address on communication Bus. |
| DL3LD | 1:1556bcaaf759 | 729 | * @param Output: specifies the audio output target: OUTPUT_DEVICE_SPEAKER, |
| DL3LD | 1:1556bcaaf759 | 730 | * OUTPUT_DEVICE_HEADPHONE, OUTPUT_DEVICE_BOTH or OUTPUT_DEVICE_AUTO |
| DL3LD | 1:1556bcaaf759 | 731 | * @retval 0 if correct communication, else wrong communication |
| DL3LD | 1:1556bcaaf759 | 732 | */ |
| DL3LD | 1:1556bcaaf759 | 733 | uint32_t wm8994_SetOutputMode(uint16_t DeviceAddr, uint8_t Output) |
| DL3LD | 1:1556bcaaf759 | 734 | { |
| DL3LD | 1:1556bcaaf759 | 735 | uint32_t counter = 0; |
| DL3LD | 1:1556bcaaf759 | 736 | |
| DL3LD | 1:1556bcaaf759 | 737 | switch (Output) |
| DL3LD | 1:1556bcaaf759 | 738 | { |
| DL3LD | 1:1556bcaaf759 | 739 | case OUTPUT_DEVICE_SPEAKER: |
| DL3LD | 1:1556bcaaf759 | 740 | /* Enable DAC1 (Left), Enable DAC1 (Right), |
| DL3LD | 1:1556bcaaf759 | 741 | Disable DAC2 (Left), Disable DAC2 (Right)*/ |
| DL3LD | 1:1556bcaaf759 | 742 | counter += CODEC_IO_Write(DeviceAddr, 0x05, 0x0C0C); |
| DL3LD | 1:1556bcaaf759 | 743 | |
| DL3LD | 1:1556bcaaf759 | 744 | /* Enable the AIF1 Timeslot 0 (Left) to DAC 1 (Left) mixer path */ |
| DL3LD | 1:1556bcaaf759 | 745 | counter += CODEC_IO_Write(DeviceAddr, 0x601, 0x0000); |
| DL3LD | 1:1556bcaaf759 | 746 | |
| DL3LD | 1:1556bcaaf759 | 747 | /* Enable the AIF1 Timeslot 0 (Right) to DAC 1 (Right) mixer path */ |
| DL3LD | 1:1556bcaaf759 | 748 | counter += CODEC_IO_Write(DeviceAddr, 0x602, 0x0000); |
| DL3LD | 1:1556bcaaf759 | 749 | |
| DL3LD | 1:1556bcaaf759 | 750 | /* Disable the AIF1 Timeslot 1 (Left) to DAC 2 (Left) mixer path */ |
| DL3LD | 1:1556bcaaf759 | 751 | counter += CODEC_IO_Write(DeviceAddr, 0x604, 0x0002); |
| DL3LD | 1:1556bcaaf759 | 752 | |
| DL3LD | 1:1556bcaaf759 | 753 | /* Disable the AIF1 Timeslot 1 (Right) to DAC 2 (Right) mixer path */ |
| DL3LD | 1:1556bcaaf759 | 754 | counter += CODEC_IO_Write(DeviceAddr, 0x605, 0x0002); |
| DL3LD | 1:1556bcaaf759 | 755 | break; |
| DL3LD | 1:1556bcaaf759 | 756 | |
| DL3LD | 1:1556bcaaf759 | 757 | case OUTPUT_DEVICE_HEADPHONE: |
| DL3LD | 1:1556bcaaf759 | 758 | /* Disable DAC1 (Left), Disable DAC1 (Right), |
| DL3LD | 1:1556bcaaf759 | 759 | Enable DAC2 (Left), Enable DAC2 (Right)*/ |
| DL3LD | 1:1556bcaaf759 | 760 | counter += CODEC_IO_Write(DeviceAddr, 0x05, 0x0303); |
| DL3LD | 1:1556bcaaf759 | 761 | |
| DL3LD | 1:1556bcaaf759 | 762 | /* Enable the AIF1 Timeslot 0 (Left) to DAC 1 (Left) mixer path */ |
| DL3LD | 1:1556bcaaf759 | 763 | counter += CODEC_IO_Write(DeviceAddr, 0x601, 0x0001); |
| DL3LD | 1:1556bcaaf759 | 764 | |
| DL3LD | 1:1556bcaaf759 | 765 | /* Enable the AIF1 Timeslot 0 (Right) to DAC 1 (Right) mixer path */ |
| DL3LD | 1:1556bcaaf759 | 766 | counter += CODEC_IO_Write(DeviceAddr, 0x602, 0x0001); |
| DL3LD | 1:1556bcaaf759 | 767 | |
| DL3LD | 1:1556bcaaf759 | 768 | /* Disable the AIF1 Timeslot 1 (Left) to DAC 2 (Left) mixer path */ |
| DL3LD | 1:1556bcaaf759 | 769 | counter += CODEC_IO_Write(DeviceAddr, 0x604, 0x0000); |
| DL3LD | 1:1556bcaaf759 | 770 | |
| DL3LD | 1:1556bcaaf759 | 771 | /* Disable the AIF1 Timeslot 1 (Right) to DAC 2 (Right) mixer path */ |
| DL3LD | 1:1556bcaaf759 | 772 | counter += CODEC_IO_Write(DeviceAddr, 0x605, 0x0000); |
| DL3LD | 1:1556bcaaf759 | 773 | break; |
| DL3LD | 1:1556bcaaf759 | 774 | |
| DL3LD | 1:1556bcaaf759 | 775 | case OUTPUT_DEVICE_BOTH: |
| DL3LD | 1:1556bcaaf759 | 776 | /* Enable DAC1 (Left), Enable DAC1 (Right), |
| DL3LD | 1:1556bcaaf759 | 777 | also Enable DAC2 (Left), Enable DAC2 (Right)*/ |
| DL3LD | 1:1556bcaaf759 | 778 | counter += CODEC_IO_Write(DeviceAddr, 0x05, 0x0303 | 0x0C0C); |
| DL3LD | 1:1556bcaaf759 | 779 | |
| DL3LD | 1:1556bcaaf759 | 780 | /* Enable the AIF1 Timeslot 0 (Left) to DAC 1 (Left) mixer path */ |
| DL3LD | 1:1556bcaaf759 | 781 | counter += CODEC_IO_Write(DeviceAddr, 0x601, 0x0001); |
| DL3LD | 1:1556bcaaf759 | 782 | |
| DL3LD | 1:1556bcaaf759 | 783 | /* Enable the AIF1 Timeslot 0 (Right) to DAC 1 (Right) mixer path */ |
| DL3LD | 1:1556bcaaf759 | 784 | counter += CODEC_IO_Write(DeviceAddr, 0x602, 0x0001); |
| DL3LD | 1:1556bcaaf759 | 785 | |
| DL3LD | 1:1556bcaaf759 | 786 | /* Enable the AIF1 Timeslot 1 (Left) to DAC 2 (Left) mixer path */ |
| DL3LD | 1:1556bcaaf759 | 787 | counter += CODEC_IO_Write(DeviceAddr, 0x604, 0x0002); |
| DL3LD | 1:1556bcaaf759 | 788 | |
| DL3LD | 1:1556bcaaf759 | 789 | /* Enable the AIF1 Timeslot 1 (Right) to DAC 2 (Right) mixer path */ |
| DL3LD | 1:1556bcaaf759 | 790 | counter += CODEC_IO_Write(DeviceAddr, 0x605, 0x0002); |
| DL3LD | 1:1556bcaaf759 | 791 | break; |
| DL3LD | 1:1556bcaaf759 | 792 | |
| DL3LD | 1:1556bcaaf759 | 793 | default: |
| DL3LD | 1:1556bcaaf759 | 794 | /* Disable DAC1 (Left), Disable DAC1 (Right), |
| DL3LD | 1:1556bcaaf759 | 795 | Enable DAC2 (Left), Enable DAC2 (Right)*/ |
| DL3LD | 1:1556bcaaf759 | 796 | counter += CODEC_IO_Write(DeviceAddr, 0x05, 0x0303); |
| DL3LD | 1:1556bcaaf759 | 797 | |
| DL3LD | 1:1556bcaaf759 | 798 | /* Enable the AIF1 Timeslot 0 (Left) to DAC 1 (Left) mixer path */ |
| DL3LD | 1:1556bcaaf759 | 799 | counter += CODEC_IO_Write(DeviceAddr, 0x601, 0x0001); |
| DL3LD | 1:1556bcaaf759 | 800 | |
| DL3LD | 1:1556bcaaf759 | 801 | /* Enable the AIF1 Timeslot 0 (Right) to DAC 1 (Right) mixer path */ |
| DL3LD | 1:1556bcaaf759 | 802 | counter += CODEC_IO_Write(DeviceAddr, 0x602, 0x0001); |
| DL3LD | 1:1556bcaaf759 | 803 | |
| DL3LD | 1:1556bcaaf759 | 804 | /* Disable the AIF1 Timeslot 1 (Left) to DAC 2 (Left) mixer path */ |
| DL3LD | 1:1556bcaaf759 | 805 | counter += CODEC_IO_Write(DeviceAddr, 0x604, 0x0000); |
| DL3LD | 1:1556bcaaf759 | 806 | |
| DL3LD | 1:1556bcaaf759 | 807 | /* Disable the AIF1 Timeslot 1 (Right) to DAC 2 (Right) mixer path */ |
| DL3LD | 1:1556bcaaf759 | 808 | counter += CODEC_IO_Write(DeviceAddr, 0x605, 0x0000); |
| DL3LD | 1:1556bcaaf759 | 809 | break; |
| DL3LD | 1:1556bcaaf759 | 810 | } |
| DL3LD | 1:1556bcaaf759 | 811 | return counter; |
| DL3LD | 1:1556bcaaf759 | 812 | } |
| DL3LD | 1:1556bcaaf759 | 813 | |
| DL3LD | 1:1556bcaaf759 | 814 | /** |
| DL3LD | 1:1556bcaaf759 | 815 | * @brief Sets new frequency. |
| DL3LD | 1:1556bcaaf759 | 816 | * @param DeviceAddr: Device address on communication Bus. |
| DL3LD | 1:1556bcaaf759 | 817 | * @param AudioFreq: Audio frequency used to play the audio stream. |
| DL3LD | 1:1556bcaaf759 | 818 | * @retval 0 if correct communication, else wrong communication |
| DL3LD | 1:1556bcaaf759 | 819 | */ |
| DL3LD | 1:1556bcaaf759 | 820 | uint32_t wm8994_SetFrequency(uint16_t DeviceAddr, uint32_t AudioFreq) |
| DL3LD | 1:1556bcaaf759 | 821 | { |
| DL3LD | 1:1556bcaaf759 | 822 | uint32_t counter = 0; |
| DL3LD | 1:1556bcaaf759 | 823 | |
| DL3LD | 1:1556bcaaf759 | 824 | /* Clock Configurations */ |
| DL3LD | 1:1556bcaaf759 | 825 | switch (AudioFreq) |
| DL3LD | 1:1556bcaaf759 | 826 | { |
| DL3LD | 1:1556bcaaf759 | 827 | case AUDIO_FREQUENCY_8K: |
| DL3LD | 1:1556bcaaf759 | 828 | /* AIF1 Sample Rate = 8 (KHz), ratio=256 */ |
| DL3LD | 1:1556bcaaf759 | 829 | counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0003); |
| DL3LD | 1:1556bcaaf759 | 830 | break; |
| DL3LD | 1:1556bcaaf759 | 831 | |
| DL3LD | 1:1556bcaaf759 | 832 | case AUDIO_FREQUENCY_16K: |
| DL3LD | 1:1556bcaaf759 | 833 | /* AIF1 Sample Rate = 16 (KHz), ratio=256 */ |
| DL3LD | 1:1556bcaaf759 | 834 | counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0033); |
| DL3LD | 1:1556bcaaf759 | 835 | break; |
| DL3LD | 1:1556bcaaf759 | 836 | |
| DL3LD | 1:1556bcaaf759 | 837 | case AUDIO_FREQUENCY_48K: |
| DL3LD | 1:1556bcaaf759 | 838 | /* AIF1 Sample Rate = 48 (KHz), ratio=256 */ |
| DL3LD | 1:1556bcaaf759 | 839 | counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0083); |
| DL3LD | 1:1556bcaaf759 | 840 | break; |
| DL3LD | 1:1556bcaaf759 | 841 | |
| DL3LD | 1:1556bcaaf759 | 842 | case AUDIO_FREQUENCY_96K: |
| DL3LD | 1:1556bcaaf759 | 843 | /* AIF1 Sample Rate = 96 (KHz), ratio=256 */ |
| DL3LD | 1:1556bcaaf759 | 844 | counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x00A3); |
| DL3LD | 1:1556bcaaf759 | 845 | break; |
| DL3LD | 1:1556bcaaf759 | 846 | |
| DL3LD | 1:1556bcaaf759 | 847 | case AUDIO_FREQUENCY_11K: |
| DL3LD | 1:1556bcaaf759 | 848 | /* AIF1 Sample Rate = 11.025 (KHz), ratio=256 */ |
| DL3LD | 1:1556bcaaf759 | 849 | counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0013); |
| DL3LD | 1:1556bcaaf759 | 850 | break; |
| DL3LD | 1:1556bcaaf759 | 851 | |
| DL3LD | 1:1556bcaaf759 | 852 | case AUDIO_FREQUENCY_22K: |
| DL3LD | 1:1556bcaaf759 | 853 | /* AIF1 Sample Rate = 22.050 (KHz), ratio=256 */ |
| DL3LD | 1:1556bcaaf759 | 854 | counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0043); |
| DL3LD | 1:1556bcaaf759 | 855 | break; |
| DL3LD | 1:1556bcaaf759 | 856 | |
| DL3LD | 1:1556bcaaf759 | 857 | case AUDIO_FREQUENCY_44K: |
| DL3LD | 1:1556bcaaf759 | 858 | /* AIF1 Sample Rate = 44.1 (KHz), ratio=256 */ |
| DL3LD | 1:1556bcaaf759 | 859 | counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0073); |
| DL3LD | 1:1556bcaaf759 | 860 | break; |
| DL3LD | 1:1556bcaaf759 | 861 | |
| DL3LD | 1:1556bcaaf759 | 862 | default: |
| DL3LD | 1:1556bcaaf759 | 863 | /* AIF1 Sample Rate = 48 (KHz), ratio=256 */ |
| DL3LD | 1:1556bcaaf759 | 864 | counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0083); |
| DL3LD | 1:1556bcaaf759 | 865 | break; |
| DL3LD | 1:1556bcaaf759 | 866 | } |
| DL3LD | 1:1556bcaaf759 | 867 | return counter; |
| DL3LD | 1:1556bcaaf759 | 868 | } |
| DL3LD | 1:1556bcaaf759 | 869 | |
| DL3LD | 1:1556bcaaf759 | 870 | /** |
| DL3LD | 1:1556bcaaf759 | 871 | * @brief Resets wm8994 registers. |
| DL3LD | 1:1556bcaaf759 | 872 | * @param DeviceAddr: Device address on communication Bus. |
| DL3LD | 1:1556bcaaf759 | 873 | * @retval 0 if correct communication, else wrong communication |
| DL3LD | 1:1556bcaaf759 | 874 | */ |
| DL3LD | 1:1556bcaaf759 | 875 | uint32_t wm8994_Reset(uint16_t DeviceAddr) |
| DL3LD | 1:1556bcaaf759 | 876 | { |
| DL3LD | 1:1556bcaaf759 | 877 | uint32_t counter = 0; |
| DL3LD | 1:1556bcaaf759 | 878 | |
| DL3LD | 1:1556bcaaf759 | 879 | /* Reset Codec by writing in 0x0000 address register */ |
| DL3LD | 1:1556bcaaf759 | 880 | counter = CODEC_IO_Write(DeviceAddr, 0x0000, 0x0000); |
| DL3LD | 1:1556bcaaf759 | 881 | outputEnabled = 0; |
| DL3LD | 1:1556bcaaf759 | 882 | inputEnabled=0; |
| DL3LD | 1:1556bcaaf759 | 883 | |
| DL3LD | 1:1556bcaaf759 | 884 | return counter; |
| DL3LD | 1:1556bcaaf759 | 885 | } |
| DL3LD | 1:1556bcaaf759 | 886 | |
| DL3LD | 1:1556bcaaf759 | 887 | /** |
| DL3LD | 1:1556bcaaf759 | 888 | * @brief Writes/Read a single data. |
| DL3LD | 1:1556bcaaf759 | 889 | * @param Addr: I2C address |
| DL3LD | 1:1556bcaaf759 | 890 | * @param Reg: Reg address |
| DL3LD | 1:1556bcaaf759 | 891 | * @param Value: Data to be written |
| DL3LD | 1:1556bcaaf759 | 892 | * @retval None |
| DL3LD | 1:1556bcaaf759 | 893 | */ |
| DL3LD | 1:1556bcaaf759 | 894 | static uint8_t CODEC_IO_Write(uint8_t Addr, uint16_t Reg, uint16_t Value) |
| DL3LD | 1:1556bcaaf759 | 895 | { |
| DL3LD | 1:1556bcaaf759 | 896 | uint32_t result = 0; |
| DL3LD | 1:1556bcaaf759 | 897 | |
| DL3LD | 1:1556bcaaf759 | 898 | AUDIO_IO_Write(Addr, Reg, Value); |
| DL3LD | 1:1556bcaaf759 | 899 | |
| DL3LD | 1:1556bcaaf759 | 900 | #ifdef VERIFY_WRITTENDATA |
| DL3LD | 1:1556bcaaf759 | 901 | /* Verify that the data has been correctly written */ |
| DL3LD | 1:1556bcaaf759 | 902 | result = (AUDIO_IO_Read(Addr, Reg) == Value)? 0:1; |
| DL3LD | 1:1556bcaaf759 | 903 | #endif /* VERIFY_WRITTENDATA */ |
| DL3LD | 1:1556bcaaf759 | 904 | |
| DL3LD | 1:1556bcaaf759 | 905 | return result; |
| DL3LD | 1:1556bcaaf759 | 906 | } |
| DL3LD | 1:1556bcaaf759 | 907 | |
| DL3LD | 1:1556bcaaf759 | 908 | /** |
| DL3LD | 1:1556bcaaf759 | 909 | * @} |
| DL3LD | 1:1556bcaaf759 | 910 | */ |
| DL3LD | 1:1556bcaaf759 | 911 | |
| DL3LD | 1:1556bcaaf759 | 912 | /** |
| DL3LD | 1:1556bcaaf759 | 913 | * @} |
| DL3LD | 1:1556bcaaf759 | 914 | */ |
| DL3LD | 1:1556bcaaf759 | 915 | |
| DL3LD | 1:1556bcaaf759 | 916 | /** |
| DL3LD | 1:1556bcaaf759 | 917 | * @} |
| DL3LD | 1:1556bcaaf759 | 918 | */ |
| DL3LD | 1:1556bcaaf759 | 919 | |
| DL3LD | 1:1556bcaaf759 | 920 | /** |
| DL3LD | 1:1556bcaaf759 | 921 | * @} |
| DL3LD | 1:1556bcaaf759 | 922 | */ |
| DL3LD | 1:1556bcaaf759 | 923 | |
| DL3LD | 1:1556bcaaf759 | 924 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
| DL3LD | 1:1556bcaaf759 | 925 |