Viktor Zhezher / Mbed 2 deprecated SI570_VFO_F746NG

Library to control Silicon Labs SI570 10 MHZ TO 1.4 GHZ I2C PROGRAMMABLE XO/VCXO.

Dependencies:   mbed

Fork of SI570 by Gerrit Polder

BSP_F746NG/stm32746g_discovery_sdram.c@1:1556bcaaf759, 2016-03-27 (annotated)

Committer:
DL3LD
Date:
Sun Mar 27 06:55:59 2016 +0000
Revision:
1:1556bcaaf759
STM32F746NG SI570 VFO Test

Who changed what in which revision?

UserRevisionLine numberNew contents of line
DL3LD 1:1556bcaaf759 1 /**
DL3LD 1:1556bcaaf759 2 ******************************************************************************
DL3LD 1:1556bcaaf759 3 * @file stm32746g_discovery_sdram.c
DL3LD 1:1556bcaaf759 4 * @author MCD Application Team
DL3LD 1:1556bcaaf759 5 * @version V1.0.0
DL3LD 1:1556bcaaf759 6 * @date 25-June-2015
DL3LD 1:1556bcaaf759 7 * @brief This file includes the SDRAM driver for the MT48LC4M32B2B5-7 memory
DL3LD 1:1556bcaaf759 8 * device mounted on STM32746G-Discovery board.
DL3LD 1:1556bcaaf759 9 @verbatim
DL3LD 1:1556bcaaf759 10 1. How To use this driver:
DL3LD 1:1556bcaaf759 11 --------------------------
DL3LD 1:1556bcaaf759 12 - This driver is used to drive the MT48LC4M32B2B5-7 SDRAM external memory mounted
DL3LD 1:1556bcaaf759 13 on STM32746G-Discovery board.
DL3LD 1:1556bcaaf759 14 - This driver does not need a specific component driver for the SDRAM device
DL3LD 1:1556bcaaf759 15 to be included with.
DL3LD 1:1556bcaaf759 16
DL3LD 1:1556bcaaf759 17 2. Driver description:
DL3LD 1:1556bcaaf759 18 ---------------------
DL3LD 1:1556bcaaf759 19 + Initialization steps:
DL3LD 1:1556bcaaf759 20 o Initialize the SDRAM external memory using the BSP_SDRAM_Init() function. This
DL3LD 1:1556bcaaf759 21 function includes the MSP layer hardware resources initialization and the
DL3LD 1:1556bcaaf759 22 FMC controller configuration to interface with the external SDRAM memory.
DL3LD 1:1556bcaaf759 23 o It contains the SDRAM initialization sequence to program the SDRAM external
DL3LD 1:1556bcaaf759 24 device using the function BSP_SDRAM_Initialization_sequence(). Note that this
DL3LD 1:1556bcaaf759 25 sequence is standard for all SDRAM devices, but can include some differences
DL3LD 1:1556bcaaf759 26 from a device to another. If it is the case, the right sequence should be
DL3LD 1:1556bcaaf759 27 implemented separately.
DL3LD 1:1556bcaaf759 28
DL3LD 1:1556bcaaf759 29 + SDRAM read/write operations
DL3LD 1:1556bcaaf759 30 o SDRAM external memory can be accessed with read/write operations once it is
DL3LD 1:1556bcaaf759 31 initialized.
DL3LD 1:1556bcaaf759 32 Read/write operation can be performed with AHB access using the functions
DL3LD 1:1556bcaaf759 33 BSP_SDRAM_ReadData()/BSP_SDRAM_WriteData(), or by DMA transfer using the functions
DL3LD 1:1556bcaaf759 34 BSP_SDRAM_ReadData_DMA()/BSP_SDRAM_WriteData_DMA().
DL3LD 1:1556bcaaf759 35 o The AHB access is performed with 32-bit width transaction, the DMA transfer
DL3LD 1:1556bcaaf759 36 configuration is fixed at single (no burst) word transfer (see the
DL3LD 1:1556bcaaf759 37 SDRAM_MspInit() static function).
DL3LD 1:1556bcaaf759 38 o User can implement his own functions for read/write access with his desired
DL3LD 1:1556bcaaf759 39 configurations.
DL3LD 1:1556bcaaf759 40 o If interrupt mode is used for DMA transfer, the function BSP_SDRAM_DMA_IRQHandler()
DL3LD 1:1556bcaaf759 41 is called in IRQ handler file, to serve the generated interrupt once the DMA
DL3LD 1:1556bcaaf759 42 transfer is complete.
DL3LD 1:1556bcaaf759 43 o You can send a command to the SDRAM device in runtime using the function
DL3LD 1:1556bcaaf759 44 BSP_SDRAM_Sendcmd(), and giving the desired command as parameter chosen between
DL3LD 1:1556bcaaf759 45 the predefined commands of the "FMC_SDRAM_CommandTypeDef" structure.
DL3LD 1:1556bcaaf759 46
DL3LD 1:1556bcaaf759 47 @endverbatim
DL3LD 1:1556bcaaf759 48 ******************************************************************************
DL3LD 1:1556bcaaf759 49 * @attention
DL3LD 1:1556bcaaf759 50 *
DL3LD 1:1556bcaaf759 51 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
DL3LD 1:1556bcaaf759 52 *
DL3LD 1:1556bcaaf759 53 * Redistribution and use in source and binary forms, with or without modification,
DL3LD 1:1556bcaaf759 54 * are permitted provided that the following conditions are met:
DL3LD 1:1556bcaaf759 55 * 1. Redistributions of source code must retain the above copyright notice,
DL3LD 1:1556bcaaf759 56 * this list of conditions and the following disclaimer.
DL3LD 1:1556bcaaf759 57 * 2. Redistributions in binary form must reproduce the above copyright notice,
DL3LD 1:1556bcaaf759 58 * this list of conditions and the following disclaimer in the documentation
DL3LD 1:1556bcaaf759 59 * and/or other materials provided with the distribution.
DL3LD 1:1556bcaaf759 60 * 3. Neither the name of STMicroelectronics nor the names of its contributors
DL3LD 1:1556bcaaf759 61 * may be used to endorse or promote products derived from this software
DL3LD 1:1556bcaaf759 62 * without specific prior written permission.
DL3LD 1:1556bcaaf759 63 *
DL3LD 1:1556bcaaf759 64 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
DL3LD 1:1556bcaaf759 65 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
DL3LD 1:1556bcaaf759 66 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DL3LD 1:1556bcaaf759 67 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
DL3LD 1:1556bcaaf759 68 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DL3LD 1:1556bcaaf759 69 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
DL3LD 1:1556bcaaf759 70 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
DL3LD 1:1556bcaaf759 71 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
DL3LD 1:1556bcaaf759 72 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
DL3LD 1:1556bcaaf759 73 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
DL3LD 1:1556bcaaf759 74 *
DL3LD 1:1556bcaaf759 75 ******************************************************************************
DL3LD 1:1556bcaaf759 76 */
DL3LD 1:1556bcaaf759 77
DL3LD 1:1556bcaaf759 78 /* Includes ------------------------------------------------------------------*/
DL3LD 1:1556bcaaf759 79 #include "stm32746g_discovery_sdram.h"
DL3LD 1:1556bcaaf759 80
DL3LD 1:1556bcaaf759 81 // mbed function to replace HAL_Delay function
DL3LD 1:1556bcaaf759 82 void wait_ms(int ms);
DL3LD 1:1556bcaaf759 83
DL3LD 1:1556bcaaf759 84 /** @addtogroup BSP
DL3LD 1:1556bcaaf759 85 * @{
DL3LD 1:1556bcaaf759 86 */
DL3LD 1:1556bcaaf759 87
DL3LD 1:1556bcaaf759 88 /** @addtogroup STM32746G_DISCOVERY
DL3LD 1:1556bcaaf759 89 * @{
DL3LD 1:1556bcaaf759 90 */
DL3LD 1:1556bcaaf759 91
DL3LD 1:1556bcaaf759 92 /** @defgroup STM32746G_DISCOVERY_SDRAM STM32746G_DISCOVERY_SDRAM
DL3LD 1:1556bcaaf759 93 * @{
DL3LD 1:1556bcaaf759 94 */
DL3LD 1:1556bcaaf759 95
DL3LD 1:1556bcaaf759 96 /** @defgroup STM32746G_DISCOVERY_SDRAM_Private_Types_Definitions STM32746G_DISCOVERY_SDRAM Private Types Definitions
DL3LD 1:1556bcaaf759 97 * @{
DL3LD 1:1556bcaaf759 98 */
DL3LD 1:1556bcaaf759 99 /**
DL3LD 1:1556bcaaf759 100 * @}
DL3LD 1:1556bcaaf759 101 */
DL3LD 1:1556bcaaf759 102
DL3LD 1:1556bcaaf759 103 /** @defgroup STM32746G_DISCOVERY_SDRAM_Private_Defines STM32746G_DISCOVERY_SDRAM Private Defines
DL3LD 1:1556bcaaf759 104 * @{
DL3LD 1:1556bcaaf759 105 */
DL3LD 1:1556bcaaf759 106 /**
DL3LD 1:1556bcaaf759 107 * @}
DL3LD 1:1556bcaaf759 108 */
DL3LD 1:1556bcaaf759 109
DL3LD 1:1556bcaaf759 110 /** @defgroup STM32746G_DISCOVERY_SDRAM_Private_Macros STM32746G_DISCOVERY_SDRAM Private Macros
DL3LD 1:1556bcaaf759 111 * @{
DL3LD 1:1556bcaaf759 112 */
DL3LD 1:1556bcaaf759 113 /**
DL3LD 1:1556bcaaf759 114 * @}
DL3LD 1:1556bcaaf759 115 */
DL3LD 1:1556bcaaf759 116
DL3LD 1:1556bcaaf759 117 /** @defgroup STM32746G_DISCOVERY_SDRAM_Private_Variables STM32746G_DISCOVERY_SDRAM Private Variables
DL3LD 1:1556bcaaf759 118 * @{
DL3LD 1:1556bcaaf759 119 */
DL3LD 1:1556bcaaf759 120 static SDRAM_HandleTypeDef sdramHandle;
DL3LD 1:1556bcaaf759 121 static FMC_SDRAM_TimingTypeDef Timing;
DL3LD 1:1556bcaaf759 122 static FMC_SDRAM_CommandTypeDef Command;
DL3LD 1:1556bcaaf759 123 /**
DL3LD 1:1556bcaaf759 124 * @}
DL3LD 1:1556bcaaf759 125 */
DL3LD 1:1556bcaaf759 126
DL3LD 1:1556bcaaf759 127 /** @defgroup STM32746G_DISCOVERY_SDRAM_Private_Function_Prototypes STM32746G_DISCOVERY_SDRAM Private Function Prototypes
DL3LD 1:1556bcaaf759 128 * @{
DL3LD 1:1556bcaaf759 129 */
DL3LD 1:1556bcaaf759 130 /**
DL3LD 1:1556bcaaf759 131 * @}
DL3LD 1:1556bcaaf759 132 */
DL3LD 1:1556bcaaf759 133
DL3LD 1:1556bcaaf759 134 /** @defgroup STM32746G_DISCOVERY_SDRAM_Exported_Functions STM32746G_DISCOVERY_SDRAM Exported Functions
DL3LD 1:1556bcaaf759 135 * @{
DL3LD 1:1556bcaaf759 136 */
DL3LD 1:1556bcaaf759 137
DL3LD 1:1556bcaaf759 138 /**
DL3LD 1:1556bcaaf759 139 * @brief Initializes the SDRAM device.
DL3LD 1:1556bcaaf759 140 * @retval SDRAM status
DL3LD 1:1556bcaaf759 141 */
DL3LD 1:1556bcaaf759 142 uint8_t BSP_SDRAM_Init(void)
DL3LD 1:1556bcaaf759 143 {
DL3LD 1:1556bcaaf759 144 static uint8_t sdramstatus = SDRAM_ERROR;
DL3LD 1:1556bcaaf759 145 /* SDRAM device configuration */
DL3LD 1:1556bcaaf759 146 sdramHandle.Instance = FMC_SDRAM_DEVICE;
DL3LD 1:1556bcaaf759 147
DL3LD 1:1556bcaaf759 148 /* Timing configuration for 100Mhz as SD clock frequency (System clock is up to 200Mhz) */
DL3LD 1:1556bcaaf759 149 Timing.LoadToActiveDelay = 2;
DL3LD 1:1556bcaaf759 150 Timing.ExitSelfRefreshDelay = 7;
DL3LD 1:1556bcaaf759 151 Timing.SelfRefreshTime = 4;
DL3LD 1:1556bcaaf759 152 Timing.RowCycleDelay = 7;
DL3LD 1:1556bcaaf759 153 Timing.WriteRecoveryTime = 2;
DL3LD 1:1556bcaaf759 154 Timing.RPDelay = 2;
DL3LD 1:1556bcaaf759 155 Timing.RCDDelay = 2;
DL3LD 1:1556bcaaf759 156
DL3LD 1:1556bcaaf759 157 sdramHandle.Init.SDBank = FMC_SDRAM_BANK1;
DL3LD 1:1556bcaaf759 158 sdramHandle.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_8;
DL3LD 1:1556bcaaf759 159 sdramHandle.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12;
DL3LD 1:1556bcaaf759 160 sdramHandle.Init.MemoryDataWidth = SDRAM_MEMORY_WIDTH;
DL3LD 1:1556bcaaf759 161 sdramHandle.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4;
DL3LD 1:1556bcaaf759 162 sdramHandle.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_2;
DL3LD 1:1556bcaaf759 163 sdramHandle.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE;
DL3LD 1:1556bcaaf759 164 sdramHandle.Init.SDClockPeriod = SDCLOCK_PERIOD;
DL3LD 1:1556bcaaf759 165 sdramHandle.Init.ReadBurst = FMC_SDRAM_RBURST_ENABLE;
DL3LD 1:1556bcaaf759 166 sdramHandle.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_0;
DL3LD 1:1556bcaaf759 167
DL3LD 1:1556bcaaf759 168 /* SDRAM controller initialization */
DL3LD 1:1556bcaaf759 169
DL3LD 1:1556bcaaf759 170 BSP_SDRAM_MspInit(&sdramHandle, NULL); /* __weak function can be rewritten by the application */
DL3LD 1:1556bcaaf759 171
DL3LD 1:1556bcaaf759 172 if(HAL_SDRAM_Init(&sdramHandle, &Timing) != HAL_OK)
DL3LD 1:1556bcaaf759 173 {
DL3LD 1:1556bcaaf759 174 sdramstatus = SDRAM_ERROR;
DL3LD 1:1556bcaaf759 175 }
DL3LD 1:1556bcaaf759 176 else
DL3LD 1:1556bcaaf759 177 {
DL3LD 1:1556bcaaf759 178 sdramstatus = SDRAM_OK;
DL3LD 1:1556bcaaf759 179 }
DL3LD 1:1556bcaaf759 180
DL3LD 1:1556bcaaf759 181 /* SDRAM initialization sequence */
DL3LD 1:1556bcaaf759 182 BSP_SDRAM_Initialization_sequence(REFRESH_COUNT);
DL3LD 1:1556bcaaf759 183
DL3LD 1:1556bcaaf759 184 return sdramstatus;
DL3LD 1:1556bcaaf759 185 }
DL3LD 1:1556bcaaf759 186
DL3LD 1:1556bcaaf759 187 /**
DL3LD 1:1556bcaaf759 188 * @brief DeInitializes the SDRAM device.
DL3LD 1:1556bcaaf759 189 * @retval SDRAM status
DL3LD 1:1556bcaaf759 190 */
DL3LD 1:1556bcaaf759 191 uint8_t BSP_SDRAM_DeInit(void)
DL3LD 1:1556bcaaf759 192 {
DL3LD 1:1556bcaaf759 193 static uint8_t sdramstatus = SDRAM_ERROR;
DL3LD 1:1556bcaaf759 194 /* SDRAM device de-initialization */
DL3LD 1:1556bcaaf759 195 sdramHandle.Instance = FMC_SDRAM_DEVICE;
DL3LD 1:1556bcaaf759 196
DL3LD 1:1556bcaaf759 197 if(HAL_SDRAM_DeInit(&sdramHandle) != HAL_OK)
DL3LD 1:1556bcaaf759 198 {
DL3LD 1:1556bcaaf759 199 sdramstatus = SDRAM_ERROR;
DL3LD 1:1556bcaaf759 200 }
DL3LD 1:1556bcaaf759 201 else
DL3LD 1:1556bcaaf759 202 {
DL3LD 1:1556bcaaf759 203 sdramstatus = SDRAM_OK;
DL3LD 1:1556bcaaf759 204 }
DL3LD 1:1556bcaaf759 205
DL3LD 1:1556bcaaf759 206 /* SDRAM controller de-initialization */
DL3LD 1:1556bcaaf759 207 BSP_SDRAM_MspDeInit(&sdramHandle, NULL);
DL3LD 1:1556bcaaf759 208
DL3LD 1:1556bcaaf759 209 return sdramstatus;
DL3LD 1:1556bcaaf759 210 }
DL3LD 1:1556bcaaf759 211
DL3LD 1:1556bcaaf759 212 /**
DL3LD 1:1556bcaaf759 213 * @brief Programs the SDRAM device.
DL3LD 1:1556bcaaf759 214 * @param RefreshCount: SDRAM refresh counter value
DL3LD 1:1556bcaaf759 215 * @retval None
DL3LD 1:1556bcaaf759 216 */
DL3LD 1:1556bcaaf759 217 void BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount)
DL3LD 1:1556bcaaf759 218 {
DL3LD 1:1556bcaaf759 219 __IO uint32_t tmpmrd = 0;
DL3LD 1:1556bcaaf759 220
DL3LD 1:1556bcaaf759 221 /* Step 1: Configure a clock configuration enable command */
DL3LD 1:1556bcaaf759 222 Command.CommandMode = FMC_SDRAM_CMD_CLK_ENABLE;
DL3LD 1:1556bcaaf759 223 Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
DL3LD 1:1556bcaaf759 224 Command.AutoRefreshNumber = 1;
DL3LD 1:1556bcaaf759 225 Command.ModeRegisterDefinition = 0;
DL3LD 1:1556bcaaf759 226
DL3LD 1:1556bcaaf759 227 /* Send the command */
DL3LD 1:1556bcaaf759 228 HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
DL3LD 1:1556bcaaf759 229
DL3LD 1:1556bcaaf759 230 /* Step 2: Insert 100 us minimum delay */
DL3LD 1:1556bcaaf759 231 /* Inserted delay is equal to 1 ms due to systick time base unit (ms) */
DL3LD 1:1556bcaaf759 232 //HAL_Delay(1);
DL3LD 1:1556bcaaf759 233 wait_ms(1);
DL3LD 1:1556bcaaf759 234
DL3LD 1:1556bcaaf759 235 /* Step 3: Configure a PALL (precharge all) command */
DL3LD 1:1556bcaaf759 236 Command.CommandMode = FMC_SDRAM_CMD_PALL;
DL3LD 1:1556bcaaf759 237 Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
DL3LD 1:1556bcaaf759 238 Command.AutoRefreshNumber = 1;
DL3LD 1:1556bcaaf759 239 Command.ModeRegisterDefinition = 0;
DL3LD 1:1556bcaaf759 240
DL3LD 1:1556bcaaf759 241 /* Send the command */
DL3LD 1:1556bcaaf759 242 HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
DL3LD 1:1556bcaaf759 243
DL3LD 1:1556bcaaf759 244 /* Step 4: Configure an Auto Refresh command */
DL3LD 1:1556bcaaf759 245 Command.CommandMode = FMC_SDRAM_CMD_AUTOREFRESH_MODE;
DL3LD 1:1556bcaaf759 246 Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
DL3LD 1:1556bcaaf759 247 Command.AutoRefreshNumber = 8;
DL3LD 1:1556bcaaf759 248 Command.ModeRegisterDefinition = 0;
DL3LD 1:1556bcaaf759 249
DL3LD 1:1556bcaaf759 250 /* Send the command */
DL3LD 1:1556bcaaf759 251 HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
DL3LD 1:1556bcaaf759 252
DL3LD 1:1556bcaaf759 253 /* Step 5: Program the external memory mode register */
DL3LD 1:1556bcaaf759 254 tmpmrd = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_1 |\
DL3LD 1:1556bcaaf759 255 SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL |\
DL3LD 1:1556bcaaf759 256 SDRAM_MODEREG_CAS_LATENCY_2 |\
DL3LD 1:1556bcaaf759 257 SDRAM_MODEREG_OPERATING_MODE_STANDARD |\
DL3LD 1:1556bcaaf759 258 SDRAM_MODEREG_WRITEBURST_MODE_SINGLE;
DL3LD 1:1556bcaaf759 259
DL3LD 1:1556bcaaf759 260 Command.CommandMode = FMC_SDRAM_CMD_LOAD_MODE;
DL3LD 1:1556bcaaf759 261 Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
DL3LD 1:1556bcaaf759 262 Command.AutoRefreshNumber = 1;
DL3LD 1:1556bcaaf759 263 Command.ModeRegisterDefinition = tmpmrd;
DL3LD 1:1556bcaaf759 264
DL3LD 1:1556bcaaf759 265 /* Send the command */
DL3LD 1:1556bcaaf759 266 HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
DL3LD 1:1556bcaaf759 267
DL3LD 1:1556bcaaf759 268 /* Step 6: Set the refresh rate counter */
DL3LD 1:1556bcaaf759 269 /* Set the device refresh rate */
DL3LD 1:1556bcaaf759 270 HAL_SDRAM_ProgramRefreshRate(&sdramHandle, RefreshCount);
DL3LD 1:1556bcaaf759 271 }
DL3LD 1:1556bcaaf759 272
DL3LD 1:1556bcaaf759 273 /**
DL3LD 1:1556bcaaf759 274 * @brief Reads an amount of data from the SDRAM memory in polling mode.
DL3LD 1:1556bcaaf759 275 * @param uwStartAddress: Read start address
DL3LD 1:1556bcaaf759 276 * @param pData: Pointer to data to be read
DL3LD 1:1556bcaaf759 277 * @param uwDataSize: Size of read data from the memory
DL3LD 1:1556bcaaf759 278 * @retval SDRAM status
DL3LD 1:1556bcaaf759 279 */
DL3LD 1:1556bcaaf759 280 uint8_t BSP_SDRAM_ReadData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize)
DL3LD 1:1556bcaaf759 281 {
DL3LD 1:1556bcaaf759 282 if(HAL_SDRAM_Read_32b(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)
DL3LD 1:1556bcaaf759 283 {
DL3LD 1:1556bcaaf759 284 return SDRAM_ERROR;
DL3LD 1:1556bcaaf759 285 }
DL3LD 1:1556bcaaf759 286 else
DL3LD 1:1556bcaaf759 287 {
DL3LD 1:1556bcaaf759 288 return SDRAM_OK;
DL3LD 1:1556bcaaf759 289 }
DL3LD 1:1556bcaaf759 290 }
DL3LD 1:1556bcaaf759 291
DL3LD 1:1556bcaaf759 292 /**
DL3LD 1:1556bcaaf759 293 * @brief Reads an amount of data from the SDRAM memory in DMA mode.
DL3LD 1:1556bcaaf759 294 * @param uwStartAddress: Read start address
DL3LD 1:1556bcaaf759 295 * @param pData: Pointer to data to be read
DL3LD 1:1556bcaaf759 296 * @param uwDataSize: Size of read data from the memory
DL3LD 1:1556bcaaf759 297 * @retval SDRAM status
DL3LD 1:1556bcaaf759 298 */
DL3LD 1:1556bcaaf759 299 uint8_t BSP_SDRAM_ReadData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize)
DL3LD 1:1556bcaaf759 300 {
DL3LD 1:1556bcaaf759 301 if(HAL_SDRAM_Read_DMA(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)
DL3LD 1:1556bcaaf759 302 {
DL3LD 1:1556bcaaf759 303 return SDRAM_ERROR;
DL3LD 1:1556bcaaf759 304 }
DL3LD 1:1556bcaaf759 305 else
DL3LD 1:1556bcaaf759 306 {
DL3LD 1:1556bcaaf759 307 return SDRAM_OK;
DL3LD 1:1556bcaaf759 308 }
DL3LD 1:1556bcaaf759 309 }
DL3LD 1:1556bcaaf759 310
DL3LD 1:1556bcaaf759 311 /**
DL3LD 1:1556bcaaf759 312 * @brief Writes an amount of data to the SDRAM memory in polling mode.
DL3LD 1:1556bcaaf759 313 * @param uwStartAddress: Write start address
DL3LD 1:1556bcaaf759 314 * @param pData: Pointer to data to be written
DL3LD 1:1556bcaaf759 315 * @param uwDataSize: Size of written data from the memory
DL3LD 1:1556bcaaf759 316 * @retval SDRAM status
DL3LD 1:1556bcaaf759 317 */
DL3LD 1:1556bcaaf759 318 uint8_t BSP_SDRAM_WriteData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize)
DL3LD 1:1556bcaaf759 319 {
DL3LD 1:1556bcaaf759 320 if(HAL_SDRAM_Write_32b(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)
DL3LD 1:1556bcaaf759 321 {
DL3LD 1:1556bcaaf759 322 return SDRAM_ERROR;
DL3LD 1:1556bcaaf759 323 }
DL3LD 1:1556bcaaf759 324 else
DL3LD 1:1556bcaaf759 325 {
DL3LD 1:1556bcaaf759 326 return SDRAM_OK;
DL3LD 1:1556bcaaf759 327 }
DL3LD 1:1556bcaaf759 328 }
DL3LD 1:1556bcaaf759 329
DL3LD 1:1556bcaaf759 330 /**
DL3LD 1:1556bcaaf759 331 * @brief Writes an amount of data to the SDRAM memory in DMA mode.
DL3LD 1:1556bcaaf759 332 * @param uwStartAddress: Write start address
DL3LD 1:1556bcaaf759 333 * @param pData: Pointer to data to be written
DL3LD 1:1556bcaaf759 334 * @param uwDataSize: Size of written data from the memory
DL3LD 1:1556bcaaf759 335 * @retval SDRAM status
DL3LD 1:1556bcaaf759 336 */
DL3LD 1:1556bcaaf759 337 uint8_t BSP_SDRAM_WriteData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize)
DL3LD 1:1556bcaaf759 338 {
DL3LD 1:1556bcaaf759 339 if(HAL_SDRAM_Write_DMA(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)
DL3LD 1:1556bcaaf759 340 {
DL3LD 1:1556bcaaf759 341 return SDRAM_ERROR;
DL3LD 1:1556bcaaf759 342 }
DL3LD 1:1556bcaaf759 343 else
DL3LD 1:1556bcaaf759 344 {
DL3LD 1:1556bcaaf759 345 return SDRAM_OK;
DL3LD 1:1556bcaaf759 346 }
DL3LD 1:1556bcaaf759 347 }
DL3LD 1:1556bcaaf759 348
DL3LD 1:1556bcaaf759 349 /**
DL3LD 1:1556bcaaf759 350 * @brief Sends command to the SDRAM bank.
DL3LD 1:1556bcaaf759 351 * @param SdramCmd: Pointer to SDRAM command structure
DL3LD 1:1556bcaaf759 352 * @retval SDRAM status
DL3LD 1:1556bcaaf759 353 */
DL3LD 1:1556bcaaf759 354 uint8_t BSP_SDRAM_Sendcmd(FMC_SDRAM_CommandTypeDef *SdramCmd)
DL3LD 1:1556bcaaf759 355 {
DL3LD 1:1556bcaaf759 356 if(HAL_SDRAM_SendCommand(&sdramHandle, SdramCmd, SDRAM_TIMEOUT) != HAL_OK)
DL3LD 1:1556bcaaf759 357 {
DL3LD 1:1556bcaaf759 358 return SDRAM_ERROR;
DL3LD 1:1556bcaaf759 359 }
DL3LD 1:1556bcaaf759 360 else
DL3LD 1:1556bcaaf759 361 {
DL3LD 1:1556bcaaf759 362 return SDRAM_OK;
DL3LD 1:1556bcaaf759 363 }
DL3LD 1:1556bcaaf759 364 }
DL3LD 1:1556bcaaf759 365
DL3LD 1:1556bcaaf759 366 /**
DL3LD 1:1556bcaaf759 367 * @brief Handles SDRAM DMA transfer interrupt request.
DL3LD 1:1556bcaaf759 368 * @retval None
DL3LD 1:1556bcaaf759 369 */
DL3LD 1:1556bcaaf759 370 void BSP_SDRAM_DMA_IRQHandler(void)
DL3LD 1:1556bcaaf759 371 {
DL3LD 1:1556bcaaf759 372 HAL_DMA_IRQHandler(sdramHandle.hdma);
DL3LD 1:1556bcaaf759 373 }
DL3LD 1:1556bcaaf759 374
DL3LD 1:1556bcaaf759 375 /**
DL3LD 1:1556bcaaf759 376 * @brief Initializes SDRAM MSP.
DL3LD 1:1556bcaaf759 377 * @param hsdram: SDRAM handle
DL3LD 1:1556bcaaf759 378 * @param Params
DL3LD 1:1556bcaaf759 379 * @retval None
DL3LD 1:1556bcaaf759 380 */
DL3LD 1:1556bcaaf759 381 __weak void BSP_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram, void *Params)
DL3LD 1:1556bcaaf759 382 {
DL3LD 1:1556bcaaf759 383 static DMA_HandleTypeDef dma_handle;
DL3LD 1:1556bcaaf759 384 GPIO_InitTypeDef gpio_init_structure;
DL3LD 1:1556bcaaf759 385
DL3LD 1:1556bcaaf759 386 /* Enable FMC clock */
DL3LD 1:1556bcaaf759 387 __HAL_RCC_FMC_CLK_ENABLE();
DL3LD 1:1556bcaaf759 388
DL3LD 1:1556bcaaf759 389 /* Enable chosen DMAx clock */
DL3LD 1:1556bcaaf759 390 __DMAx_CLK_ENABLE();
DL3LD 1:1556bcaaf759 391
DL3LD 1:1556bcaaf759 392 /* Enable GPIOs clock */
DL3LD 1:1556bcaaf759 393 __HAL_RCC_GPIOC_CLK_ENABLE();
DL3LD 1:1556bcaaf759 394 __HAL_RCC_GPIOD_CLK_ENABLE();
DL3LD 1:1556bcaaf759 395 __HAL_RCC_GPIOE_CLK_ENABLE();
DL3LD 1:1556bcaaf759 396 __HAL_RCC_GPIOF_CLK_ENABLE();
DL3LD 1:1556bcaaf759 397 __HAL_RCC_GPIOG_CLK_ENABLE();
DL3LD 1:1556bcaaf759 398 __HAL_RCC_GPIOH_CLK_ENABLE();
DL3LD 1:1556bcaaf759 399
DL3LD 1:1556bcaaf759 400 /* Common GPIO configuration */
DL3LD 1:1556bcaaf759 401 gpio_init_structure.Mode = GPIO_MODE_AF_PP;
DL3LD 1:1556bcaaf759 402 gpio_init_structure.Pull = GPIO_PULLUP;
DL3LD 1:1556bcaaf759 403 gpio_init_structure.Speed = GPIO_SPEED_FAST;
DL3LD 1:1556bcaaf759 404 gpio_init_structure.Alternate = GPIO_AF12_FMC;
DL3LD 1:1556bcaaf759 405
DL3LD 1:1556bcaaf759 406 /* GPIOC configuration */
DL3LD 1:1556bcaaf759 407 gpio_init_structure.Pin = GPIO_PIN_3;
DL3LD 1:1556bcaaf759 408 HAL_GPIO_Init(GPIOC, &gpio_init_structure);
DL3LD 1:1556bcaaf759 409
DL3LD 1:1556bcaaf759 410 /* GPIOD configuration */
DL3LD 1:1556bcaaf759 411 gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_3 | GPIO_PIN_8 | GPIO_PIN_9 |
DL3LD 1:1556bcaaf759 412 GPIO_PIN_10 | GPIO_PIN_14 | GPIO_PIN_15;
DL3LD 1:1556bcaaf759 413 HAL_GPIO_Init(GPIOD, &gpio_init_structure);
DL3LD 1:1556bcaaf759 414
DL3LD 1:1556bcaaf759 415 /* GPIOE configuration */
DL3LD 1:1556bcaaf759 416 gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_7| GPIO_PIN_8 | GPIO_PIN_9 |\
DL3LD 1:1556bcaaf759 417 GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\
DL3LD 1:1556bcaaf759 418 GPIO_PIN_15;
DL3LD 1:1556bcaaf759 419 HAL_GPIO_Init(GPIOE, &gpio_init_structure);
DL3LD 1:1556bcaaf759 420
DL3LD 1:1556bcaaf759 421 /* GPIOF configuration */
DL3LD 1:1556bcaaf759 422 gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2| GPIO_PIN_3 | GPIO_PIN_4 |\
DL3LD 1:1556bcaaf759 423 GPIO_PIN_5 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\
DL3LD 1:1556bcaaf759 424 GPIO_PIN_15;
DL3LD 1:1556bcaaf759 425 HAL_GPIO_Init(GPIOF, &gpio_init_structure);
DL3LD 1:1556bcaaf759 426
DL3LD 1:1556bcaaf759 427 /* GPIOG configuration */
DL3LD 1:1556bcaaf759 428 gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_4| GPIO_PIN_5 | GPIO_PIN_8 |\
DL3LD 1:1556bcaaf759 429 GPIO_PIN_15;
DL3LD 1:1556bcaaf759 430 HAL_GPIO_Init(GPIOG, &gpio_init_structure);
DL3LD 1:1556bcaaf759 431
DL3LD 1:1556bcaaf759 432 /* GPIOH configuration */
DL3LD 1:1556bcaaf759 433 gpio_init_structure.Pin = GPIO_PIN_3 | GPIO_PIN_5;
DL3LD 1:1556bcaaf759 434 HAL_GPIO_Init(GPIOH, &gpio_init_structure);
DL3LD 1:1556bcaaf759 435
DL3LD 1:1556bcaaf759 436 /* Configure common DMA parameters */
DL3LD 1:1556bcaaf759 437 dma_handle.Init.Channel = SDRAM_DMAx_CHANNEL;
DL3LD 1:1556bcaaf759 438 dma_handle.Init.Direction = DMA_MEMORY_TO_MEMORY;
DL3LD 1:1556bcaaf759 439 dma_handle.Init.PeriphInc = DMA_PINC_ENABLE;
DL3LD 1:1556bcaaf759 440 dma_handle.Init.MemInc = DMA_MINC_ENABLE;
DL3LD 1:1556bcaaf759 441 dma_handle.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
DL3LD 1:1556bcaaf759 442 dma_handle.Init.MemDataAlignment = DMA_MDATAALIGN_WORD;
DL3LD 1:1556bcaaf759 443 dma_handle.Init.Mode = DMA_NORMAL;
DL3LD 1:1556bcaaf759 444 dma_handle.Init.Priority = DMA_PRIORITY_HIGH;
DL3LD 1:1556bcaaf759 445 dma_handle.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
DL3LD 1:1556bcaaf759 446 dma_handle.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
DL3LD 1:1556bcaaf759 447 dma_handle.Init.MemBurst = DMA_MBURST_SINGLE;
DL3LD 1:1556bcaaf759 448 dma_handle.Init.PeriphBurst = DMA_PBURST_SINGLE;
DL3LD 1:1556bcaaf759 449
DL3LD 1:1556bcaaf759 450 dma_handle.Instance = SDRAM_DMAx_STREAM;
DL3LD 1:1556bcaaf759 451
DL3LD 1:1556bcaaf759 452 /* Associate the DMA handle */
DL3LD 1:1556bcaaf759 453 __HAL_LINKDMA(hsdram, hdma, dma_handle);
DL3LD 1:1556bcaaf759 454
DL3LD 1:1556bcaaf759 455 /* Deinitialize the stream for new transfer */
DL3LD 1:1556bcaaf759 456 HAL_DMA_DeInit(&dma_handle);
DL3LD 1:1556bcaaf759 457
DL3LD 1:1556bcaaf759 458 /* Configure the DMA stream */
DL3LD 1:1556bcaaf759 459 HAL_DMA_Init(&dma_handle);
DL3LD 1:1556bcaaf759 460
DL3LD 1:1556bcaaf759 461 /* NVIC configuration for DMA transfer complete interrupt */
DL3LD 1:1556bcaaf759 462 HAL_NVIC_SetPriority(SDRAM_DMAx_IRQn, 5, 0);
DL3LD 1:1556bcaaf759 463 HAL_NVIC_EnableIRQ(SDRAM_DMAx_IRQn);
DL3LD 1:1556bcaaf759 464 }
DL3LD 1:1556bcaaf759 465
DL3LD 1:1556bcaaf759 466 /**
DL3LD 1:1556bcaaf759 467 * @brief DeInitializes SDRAM MSP.
DL3LD 1:1556bcaaf759 468 * @param hsdram: SDRAM handle
DL3LD 1:1556bcaaf759 469 * @param Params
DL3LD 1:1556bcaaf759 470 * @retval None
DL3LD 1:1556bcaaf759 471 */
DL3LD 1:1556bcaaf759 472 __weak void BSP_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram, void *Params)
DL3LD 1:1556bcaaf759 473 {
DL3LD 1:1556bcaaf759 474 static DMA_HandleTypeDef dma_handle;
DL3LD 1:1556bcaaf759 475
DL3LD 1:1556bcaaf759 476 /* Disable NVIC configuration for DMA interrupt */
DL3LD 1:1556bcaaf759 477 HAL_NVIC_DisableIRQ(SDRAM_DMAx_IRQn);
DL3LD 1:1556bcaaf759 478
DL3LD 1:1556bcaaf759 479 /* Deinitialize the stream for new transfer */
DL3LD 1:1556bcaaf759 480 dma_handle.Instance = SDRAM_DMAx_STREAM;
DL3LD 1:1556bcaaf759 481 HAL_DMA_DeInit(&dma_handle);
DL3LD 1:1556bcaaf759 482
DL3LD 1:1556bcaaf759 483 /* GPIO pins clock, FMC clock and DMA clock can be shut down in the applications
DL3LD 1:1556bcaaf759 484 by surcharging this __weak function */
DL3LD 1:1556bcaaf759 485 }
DL3LD 1:1556bcaaf759 486
DL3LD 1:1556bcaaf759 487 /**
DL3LD 1:1556bcaaf759 488 * @}
DL3LD 1:1556bcaaf759 489 */
DL3LD 1:1556bcaaf759 490
DL3LD 1:1556bcaaf759 491 /**
DL3LD 1:1556bcaaf759 492 * @}
DL3LD 1:1556bcaaf759 493 */
DL3LD 1:1556bcaaf759 494
DL3LD 1:1556bcaaf759 495 /**
DL3LD 1:1556bcaaf759 496 * @}
DL3LD 1:1556bcaaf759 497 */
DL3LD 1:1556bcaaf759 498
DL3LD 1:1556bcaaf759 499 /**
DL3LD 1:1556bcaaf759 500 * @}
DL3LD 1:1556bcaaf759 501 */
DL3LD 1:1556bcaaf759 502
DL3LD 1:1556bcaaf759 503 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
DL3LD 1:1556bcaaf759 504