Viktor Zhezher / Mbed 2 deprecated SI570_VFO_F746NG

Library to control Silicon Labs SI570 10 MHZ TO 1.4 GHZ I2C PROGRAMMABLE XO/VCXO.

Dependencies:   mbed

Fork of SI570 by Gerrit Polder

BSP_F746NG/stm32746g_discovery_qspi.c@1:1556bcaaf759, 2016-03-27 (annotated)

Committer:
DL3LD
Date:
Sun Mar 27 06:55:59 2016 +0000
Revision:
1:1556bcaaf759
STM32F746NG SI570 VFO Test

Who changed what in which revision?

UserRevisionLine numberNew contents of line
DL3LD 1:1556bcaaf759 1 /**
DL3LD 1:1556bcaaf759 2 ******************************************************************************
DL3LD 1:1556bcaaf759 3 * @file stm32746g_discovery_qspi.c
DL3LD 1:1556bcaaf759 4 * @author MCD Application Team
DL3LD 1:1556bcaaf759 5 * @version V1.0.0
DL3LD 1:1556bcaaf759 6 * @date 25-June-2015
DL3LD 1:1556bcaaf759 7 * @brief This file includes a standard driver for the N25Q128A QSPI
DL3LD 1:1556bcaaf759 8 * memory mounted on STM32746G-Discovery board.
DL3LD 1:1556bcaaf759 9 @verbatim
DL3LD 1:1556bcaaf759 10 ==============================================================================
DL3LD 1:1556bcaaf759 11 ##### How to use this driver #####
DL3LD 1:1556bcaaf759 12 ==============================================================================
DL3LD 1:1556bcaaf759 13 [..]
DL3LD 1:1556bcaaf759 14 (#) This driver is used to drive the N25Q128A QSPI external
DL3LD 1:1556bcaaf759 15 memory mounted on STM32746G-Discovery board.
DL3LD 1:1556bcaaf759 16
DL3LD 1:1556bcaaf759 17 (#) This driver need a specific component driver (N25Q128A) to be included with.
DL3LD 1:1556bcaaf759 18
DL3LD 1:1556bcaaf759 19 (#) Initialization steps:
DL3LD 1:1556bcaaf759 20 (++) Initialize the QPSI external memory using the BSP_QSPI_Init() function. This
DL3LD 1:1556bcaaf759 21 function includes the MSP layer hardware resources initialization and the
DL3LD 1:1556bcaaf759 22 QSPI interface with the external memory.
DL3LD 1:1556bcaaf759 23
DL3LD 1:1556bcaaf759 24 (#) QSPI memory operations
DL3LD 1:1556bcaaf759 25 (++) QSPI memory can be accessed with read/write operations once it is
DL3LD 1:1556bcaaf759 26 initialized.
DL3LD 1:1556bcaaf759 27 Read/write operation can be performed with AHB access using the functions
DL3LD 1:1556bcaaf759 28 BSP_QSPI_Read()/BSP_QSPI_Write().
DL3LD 1:1556bcaaf759 29 (++) The function BSP_QSPI_GetInfo() returns the configuration of the QSPI memory.
DL3LD 1:1556bcaaf759 30 (see the QSPI memory data sheet)
DL3LD 1:1556bcaaf759 31 (++) Perform erase block operation using the function BSP_QSPI_Erase_Block() and by
DL3LD 1:1556bcaaf759 32 specifying the block address. You can perform an erase operation of the whole
DL3LD 1:1556bcaaf759 33 chip by calling the function BSP_QSPI_Erase_Chip().
DL3LD 1:1556bcaaf759 34 (++) The function BSP_QSPI_GetStatus() returns the current status of the QSPI memory.
DL3LD 1:1556bcaaf759 35 (see the QSPI memory data sheet)
DL3LD 1:1556bcaaf759 36 @endverbatim
DL3LD 1:1556bcaaf759 37 ******************************************************************************
DL3LD 1:1556bcaaf759 38 * @attention
DL3LD 1:1556bcaaf759 39 *
DL3LD 1:1556bcaaf759 40 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
DL3LD 1:1556bcaaf759 41 *
DL3LD 1:1556bcaaf759 42 * Redistribution and use in source and binary forms, with or without modification,
DL3LD 1:1556bcaaf759 43 * are permitted provided that the following conditions are met:
DL3LD 1:1556bcaaf759 44 * 1. Redistributions of source code must retain the above copyright notice,
DL3LD 1:1556bcaaf759 45 * this list of conditions and the following disclaimer.
DL3LD 1:1556bcaaf759 46 * 2. Redistributions in binary form must reproduce the above copyright notice,
DL3LD 1:1556bcaaf759 47 * this list of conditions and the following disclaimer in the documentation
DL3LD 1:1556bcaaf759 48 * and/or other materials provided with the distribution.
DL3LD 1:1556bcaaf759 49 * 3. Neither the name of STMicroelectronics nor the names of its contributors
DL3LD 1:1556bcaaf759 50 * may be used to endorse or promote products derived from this software
DL3LD 1:1556bcaaf759 51 * without specific prior written permission.
DL3LD 1:1556bcaaf759 52 *
DL3LD 1:1556bcaaf759 53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
DL3LD 1:1556bcaaf759 54 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
DL3LD 1:1556bcaaf759 55 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DL3LD 1:1556bcaaf759 56 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
DL3LD 1:1556bcaaf759 57 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DL3LD 1:1556bcaaf759 58 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
DL3LD 1:1556bcaaf759 59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
DL3LD 1:1556bcaaf759 60 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
DL3LD 1:1556bcaaf759 61 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
DL3LD 1:1556bcaaf759 62 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
DL3LD 1:1556bcaaf759 63 *
DL3LD 1:1556bcaaf759 64 ******************************************************************************
DL3LD 1:1556bcaaf759 65 */
DL3LD 1:1556bcaaf759 66
DL3LD 1:1556bcaaf759 67 /* Includes ------------------------------------------------------------------*/
DL3LD 1:1556bcaaf759 68 #include "stm32746g_discovery_qspi.h"
DL3LD 1:1556bcaaf759 69
DL3LD 1:1556bcaaf759 70 /** @addtogroup BSP
DL3LD 1:1556bcaaf759 71 * @{
DL3LD 1:1556bcaaf759 72 */
DL3LD 1:1556bcaaf759 73
DL3LD 1:1556bcaaf759 74 /** @addtogroup STM32746G_DISCOVERY
DL3LD 1:1556bcaaf759 75 * @{
DL3LD 1:1556bcaaf759 76 */
DL3LD 1:1556bcaaf759 77
DL3LD 1:1556bcaaf759 78 /** @defgroup STM32746G_DISCOVERY_QSPI STM32746G-Discovery QSPI
DL3LD 1:1556bcaaf759 79 * @{
DL3LD 1:1556bcaaf759 80 */
DL3LD 1:1556bcaaf759 81
DL3LD 1:1556bcaaf759 82
DL3LD 1:1556bcaaf759 83 /* Private variables ---------------------------------------------------------*/
DL3LD 1:1556bcaaf759 84
DL3LD 1:1556bcaaf759 85 /** @defgroup STM32746G_DISCOVERY_QSPI_Private_Variables STM32746G_DISCOVERY QSPI Private Variables
DL3LD 1:1556bcaaf759 86 * @{
DL3LD 1:1556bcaaf759 87 */
DL3LD 1:1556bcaaf759 88 QSPI_HandleTypeDef QSPIHandle;
DL3LD 1:1556bcaaf759 89
DL3LD 1:1556bcaaf759 90 /**
DL3LD 1:1556bcaaf759 91 * @}
DL3LD 1:1556bcaaf759 92 */
DL3LD 1:1556bcaaf759 93
DL3LD 1:1556bcaaf759 94
DL3LD 1:1556bcaaf759 95
DL3LD 1:1556bcaaf759 96 /* Private functions ---------------------------------------------------------*/
DL3LD 1:1556bcaaf759 97
DL3LD 1:1556bcaaf759 98 /** @defgroup STM32746G_DISCOVERY_QSPI_Private_Functions STM32746G_DISCOVERY QSPI Private Functions
DL3LD 1:1556bcaaf759 99 * @{
DL3LD 1:1556bcaaf759 100 */
DL3LD 1:1556bcaaf759 101 static uint8_t QSPI_ResetMemory (QSPI_HandleTypeDef *hqspi);
DL3LD 1:1556bcaaf759 102 static uint8_t QSPI_DummyCyclesCfg (QSPI_HandleTypeDef *hqspi);
DL3LD 1:1556bcaaf759 103 static uint8_t QSPI_WriteEnable (QSPI_HandleTypeDef *hqspi);
DL3LD 1:1556bcaaf759 104 static uint8_t QSPI_AutoPollingMemReady (QSPI_HandleTypeDef *hqspi, uint32_t Timeout);
DL3LD 1:1556bcaaf759 105
DL3LD 1:1556bcaaf759 106 /**
DL3LD 1:1556bcaaf759 107 * @}
DL3LD 1:1556bcaaf759 108 */
DL3LD 1:1556bcaaf759 109
DL3LD 1:1556bcaaf759 110 /** @defgroup STM32746G_DISCOVERY_QSPI_Exported_Functions STM32746G_DISCOVERY QSPI Exported Functions
DL3LD 1:1556bcaaf759 111 * @{
DL3LD 1:1556bcaaf759 112 */
DL3LD 1:1556bcaaf759 113
DL3LD 1:1556bcaaf759 114 /**
DL3LD 1:1556bcaaf759 115 * @brief Initializes the QSPI interface.
DL3LD 1:1556bcaaf759 116 * @retval QSPI memory status
DL3LD 1:1556bcaaf759 117 */
DL3LD 1:1556bcaaf759 118 uint8_t BSP_QSPI_Init(void)
DL3LD 1:1556bcaaf759 119 {
DL3LD 1:1556bcaaf759 120 QSPIHandle.Instance = QUADSPI;
DL3LD 1:1556bcaaf759 121
DL3LD 1:1556bcaaf759 122 /* Call the DeInit function to reset the driver */
DL3LD 1:1556bcaaf759 123 if (HAL_QSPI_DeInit(&QSPIHandle) != HAL_OK)
DL3LD 1:1556bcaaf759 124 {
DL3LD 1:1556bcaaf759 125 return QSPI_ERROR;
DL3LD 1:1556bcaaf759 126 }
DL3LD 1:1556bcaaf759 127
DL3LD 1:1556bcaaf759 128 /* System level initialization */
DL3LD 1:1556bcaaf759 129 BSP_QSPI_MspInit(&QSPIHandle, NULL);
DL3LD 1:1556bcaaf759 130
DL3LD 1:1556bcaaf759 131 /* QSPI initialization */
DL3LD 1:1556bcaaf759 132 QSPIHandle.Init.ClockPrescaler = 1; /* QSPI freq = 216 MHz/(1+1) = 108 Mhz */
DL3LD 1:1556bcaaf759 133 QSPIHandle.Init.FifoThreshold = 4;
DL3LD 1:1556bcaaf759 134 QSPIHandle.Init.SampleShifting = QSPI_SAMPLE_SHIFTING_HALFCYCLE;
DL3LD 1:1556bcaaf759 135 QSPIHandle.Init.FlashSize = POSITION_VAL(N25Q128A_FLASH_SIZE) - 1;
DL3LD 1:1556bcaaf759 136 QSPIHandle.Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_2_CYCLE;
DL3LD 1:1556bcaaf759 137 QSPIHandle.Init.ClockMode = QSPI_CLOCK_MODE_0;
DL3LD 1:1556bcaaf759 138 QSPIHandle.Init.FlashID = QSPI_FLASH_ID_1;
DL3LD 1:1556bcaaf759 139 QSPIHandle.Init.DualFlash = QSPI_DUALFLASH_DISABLE;
DL3LD 1:1556bcaaf759 140
DL3LD 1:1556bcaaf759 141 if (HAL_QSPI_Init(&QSPIHandle) != HAL_OK)
DL3LD 1:1556bcaaf759 142 {
DL3LD 1:1556bcaaf759 143 return QSPI_ERROR;
DL3LD 1:1556bcaaf759 144 }
DL3LD 1:1556bcaaf759 145
DL3LD 1:1556bcaaf759 146 /* QSPI memory reset */
DL3LD 1:1556bcaaf759 147 if (QSPI_ResetMemory(&QSPIHandle) != QSPI_OK)
DL3LD 1:1556bcaaf759 148 {
DL3LD 1:1556bcaaf759 149 return QSPI_NOT_SUPPORTED;
DL3LD 1:1556bcaaf759 150 }
DL3LD 1:1556bcaaf759 151
DL3LD 1:1556bcaaf759 152 /* Configuration of the dummy cycles on QSPI memory side */
DL3LD 1:1556bcaaf759 153 if (QSPI_DummyCyclesCfg(&QSPIHandle) != QSPI_OK)
DL3LD 1:1556bcaaf759 154 {
DL3LD 1:1556bcaaf759 155 return QSPI_NOT_SUPPORTED;
DL3LD 1:1556bcaaf759 156 }
DL3LD 1:1556bcaaf759 157
DL3LD 1:1556bcaaf759 158 return QSPI_OK;
DL3LD 1:1556bcaaf759 159 }
DL3LD 1:1556bcaaf759 160
DL3LD 1:1556bcaaf759 161 /**
DL3LD 1:1556bcaaf759 162 * @brief De-Initializes the QSPI interface.
DL3LD 1:1556bcaaf759 163 * @retval QSPI memory status
DL3LD 1:1556bcaaf759 164 */
DL3LD 1:1556bcaaf759 165 uint8_t BSP_QSPI_DeInit(void)
DL3LD 1:1556bcaaf759 166 {
DL3LD 1:1556bcaaf759 167 QSPIHandle.Instance = QUADSPI;
DL3LD 1:1556bcaaf759 168
DL3LD 1:1556bcaaf759 169 /* Call the DeInit function to reset the driver */
DL3LD 1:1556bcaaf759 170 if (HAL_QSPI_DeInit(&QSPIHandle) != HAL_OK)
DL3LD 1:1556bcaaf759 171 {
DL3LD 1:1556bcaaf759 172 return QSPI_ERROR;
DL3LD 1:1556bcaaf759 173 }
DL3LD 1:1556bcaaf759 174
DL3LD 1:1556bcaaf759 175 /* System level De-initialization */
DL3LD 1:1556bcaaf759 176 BSP_QSPI_MspDeInit(&QSPIHandle, NULL);
DL3LD 1:1556bcaaf759 177
DL3LD 1:1556bcaaf759 178 return QSPI_OK;
DL3LD 1:1556bcaaf759 179 }
DL3LD 1:1556bcaaf759 180
DL3LD 1:1556bcaaf759 181 /**
DL3LD 1:1556bcaaf759 182 * @brief Reads an amount of data from the QSPI memory.
DL3LD 1:1556bcaaf759 183 * @param pData: Pointer to data to be read
DL3LD 1:1556bcaaf759 184 * @param ReadAddr: Read start address
DL3LD 1:1556bcaaf759 185 * @param Size: Size of data to read
DL3LD 1:1556bcaaf759 186 * @retval QSPI memory status
DL3LD 1:1556bcaaf759 187 */
DL3LD 1:1556bcaaf759 188 uint8_t BSP_QSPI_Read(uint8_t* pData, uint32_t ReadAddr, uint32_t Size)
DL3LD 1:1556bcaaf759 189 {
DL3LD 1:1556bcaaf759 190 QSPI_CommandTypeDef s_command;
DL3LD 1:1556bcaaf759 191
DL3LD 1:1556bcaaf759 192 /* Initialize the read command */
DL3LD 1:1556bcaaf759 193 s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE;
DL3LD 1:1556bcaaf759 194 s_command.Instruction = QUAD_INOUT_FAST_READ_CMD;
DL3LD 1:1556bcaaf759 195 s_command.AddressMode = QSPI_ADDRESS_4_LINES;
DL3LD 1:1556bcaaf759 196 s_command.AddressSize = QSPI_ADDRESS_24_BITS;
DL3LD 1:1556bcaaf759 197 s_command.Address = ReadAddr;
DL3LD 1:1556bcaaf759 198 s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
DL3LD 1:1556bcaaf759 199 s_command.DataMode = QSPI_DATA_4_LINES;
DL3LD 1:1556bcaaf759 200 s_command.DummyCycles = N25Q128A_DUMMY_CYCLES_READ_QUAD;
DL3LD 1:1556bcaaf759 201 s_command.NbData = Size;
DL3LD 1:1556bcaaf759 202 s_command.DdrMode = QSPI_DDR_MODE_DISABLE;
DL3LD 1:1556bcaaf759 203 s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
DL3LD 1:1556bcaaf759 204 s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
DL3LD 1:1556bcaaf759 205
DL3LD 1:1556bcaaf759 206 /* Configure the command */
DL3LD 1:1556bcaaf759 207 if (HAL_QSPI_Command(&QSPIHandle, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
DL3LD 1:1556bcaaf759 208 {
DL3LD 1:1556bcaaf759 209 return QSPI_ERROR;
DL3LD 1:1556bcaaf759 210 }
DL3LD 1:1556bcaaf759 211
DL3LD 1:1556bcaaf759 212 /* Reception of the data */
DL3LD 1:1556bcaaf759 213 if (HAL_QSPI_Receive(&QSPIHandle, pData, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
DL3LD 1:1556bcaaf759 214 {
DL3LD 1:1556bcaaf759 215 return QSPI_ERROR;
DL3LD 1:1556bcaaf759 216 }
DL3LD 1:1556bcaaf759 217
DL3LD 1:1556bcaaf759 218 return QSPI_OK;
DL3LD 1:1556bcaaf759 219 }
DL3LD 1:1556bcaaf759 220
DL3LD 1:1556bcaaf759 221 /**
DL3LD 1:1556bcaaf759 222 * @brief Writes an amount of data to the QSPI memory.
DL3LD 1:1556bcaaf759 223 * @param pData: Pointer to data to be written
DL3LD 1:1556bcaaf759 224 * @param WriteAddr: Write start address
DL3LD 1:1556bcaaf759 225 * @param Size: Size of data to write
DL3LD 1:1556bcaaf759 226 * @retval QSPI memory status
DL3LD 1:1556bcaaf759 227 */
DL3LD 1:1556bcaaf759 228 uint8_t BSP_QSPI_Write(uint8_t* pData, uint32_t WriteAddr, uint32_t Size)
DL3LD 1:1556bcaaf759 229 {
DL3LD 1:1556bcaaf759 230 QSPI_CommandTypeDef s_command;
DL3LD 1:1556bcaaf759 231 uint32_t end_addr, current_size, current_addr;
DL3LD 1:1556bcaaf759 232
DL3LD 1:1556bcaaf759 233 /* Calculation of the size between the write address and the end of the page */
DL3LD 1:1556bcaaf759 234 current_addr = 0;
DL3LD 1:1556bcaaf759 235
DL3LD 1:1556bcaaf759 236 while (current_addr <= WriteAddr)
DL3LD 1:1556bcaaf759 237 {
DL3LD 1:1556bcaaf759 238 current_addr += N25Q128A_PAGE_SIZE;
DL3LD 1:1556bcaaf759 239 }
DL3LD 1:1556bcaaf759 240 current_size = current_addr - WriteAddr;
DL3LD 1:1556bcaaf759 241
DL3LD 1:1556bcaaf759 242 /* Check if the size of the data is less than the remaining place in the page */
DL3LD 1:1556bcaaf759 243 if (current_size > Size)
DL3LD 1:1556bcaaf759 244 {
DL3LD 1:1556bcaaf759 245 current_size = Size;
DL3LD 1:1556bcaaf759 246 }
DL3LD 1:1556bcaaf759 247
DL3LD 1:1556bcaaf759 248 /* Initialize the adress variables */
DL3LD 1:1556bcaaf759 249 current_addr = WriteAddr;
DL3LD 1:1556bcaaf759 250 end_addr = WriteAddr + Size;
DL3LD 1:1556bcaaf759 251
DL3LD 1:1556bcaaf759 252 /* Initialize the program command */
DL3LD 1:1556bcaaf759 253 s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE;
DL3LD 1:1556bcaaf759 254 s_command.Instruction = EXT_QUAD_IN_FAST_PROG_CMD;
DL3LD 1:1556bcaaf759 255 s_command.AddressMode = QSPI_ADDRESS_4_LINES;
DL3LD 1:1556bcaaf759 256 s_command.AddressSize = QSPI_ADDRESS_24_BITS;
DL3LD 1:1556bcaaf759 257 s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
DL3LD 1:1556bcaaf759 258 s_command.DataMode = QSPI_DATA_4_LINES;
DL3LD 1:1556bcaaf759 259 s_command.DummyCycles = 0;
DL3LD 1:1556bcaaf759 260 s_command.DdrMode = QSPI_DDR_MODE_DISABLE;
DL3LD 1:1556bcaaf759 261 s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
DL3LD 1:1556bcaaf759 262 s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
DL3LD 1:1556bcaaf759 263
DL3LD 1:1556bcaaf759 264 /* Perform the write page by page */
DL3LD 1:1556bcaaf759 265 do
DL3LD 1:1556bcaaf759 266 {
DL3LD 1:1556bcaaf759 267 s_command.Address = current_addr;
DL3LD 1:1556bcaaf759 268 s_command.NbData = current_size;
DL3LD 1:1556bcaaf759 269
DL3LD 1:1556bcaaf759 270 /* Enable write operations */
DL3LD 1:1556bcaaf759 271 if (QSPI_WriteEnable(&QSPIHandle) != QSPI_OK)
DL3LD 1:1556bcaaf759 272 {
DL3LD 1:1556bcaaf759 273 return QSPI_ERROR;
DL3LD 1:1556bcaaf759 274 }
DL3LD 1:1556bcaaf759 275
DL3LD 1:1556bcaaf759 276 /* Configure the command */
DL3LD 1:1556bcaaf759 277 if (HAL_QSPI_Command(&QSPIHandle, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
DL3LD 1:1556bcaaf759 278 {
DL3LD 1:1556bcaaf759 279 return QSPI_ERROR;
DL3LD 1:1556bcaaf759 280 }
DL3LD 1:1556bcaaf759 281
DL3LD 1:1556bcaaf759 282 /* Transmission of the data */
DL3LD 1:1556bcaaf759 283 if (HAL_QSPI_Transmit(&QSPIHandle, pData, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
DL3LD 1:1556bcaaf759 284 {
DL3LD 1:1556bcaaf759 285 return QSPI_ERROR;
DL3LD 1:1556bcaaf759 286 }
DL3LD 1:1556bcaaf759 287
DL3LD 1:1556bcaaf759 288 /* Configure automatic polling mode to wait for end of program */
DL3LD 1:1556bcaaf759 289 if (QSPI_AutoPollingMemReady(&QSPIHandle, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != QSPI_OK)
DL3LD 1:1556bcaaf759 290 {
DL3LD 1:1556bcaaf759 291 return QSPI_ERROR;
DL3LD 1:1556bcaaf759 292 }
DL3LD 1:1556bcaaf759 293
DL3LD 1:1556bcaaf759 294 /* Update the address and size variables for next page programming */
DL3LD 1:1556bcaaf759 295 current_addr += current_size;
DL3LD 1:1556bcaaf759 296 pData += current_size;
DL3LD 1:1556bcaaf759 297 current_size = ((current_addr + N25Q128A_PAGE_SIZE) > end_addr) ? (end_addr - current_addr) : N25Q128A_PAGE_SIZE;
DL3LD 1:1556bcaaf759 298 } while (current_addr < end_addr);
DL3LD 1:1556bcaaf759 299
DL3LD 1:1556bcaaf759 300 return QSPI_OK;
DL3LD 1:1556bcaaf759 301 }
DL3LD 1:1556bcaaf759 302
DL3LD 1:1556bcaaf759 303 /**
DL3LD 1:1556bcaaf759 304 * @brief Erases the specified block of the QSPI memory.
DL3LD 1:1556bcaaf759 305 * @param BlockAddress: Block address to erase
DL3LD 1:1556bcaaf759 306 * @retval QSPI memory status
DL3LD 1:1556bcaaf759 307 */
DL3LD 1:1556bcaaf759 308 uint8_t BSP_QSPI_Erase_Block(uint32_t BlockAddress)
DL3LD 1:1556bcaaf759 309 {
DL3LD 1:1556bcaaf759 310 QSPI_CommandTypeDef s_command;
DL3LD 1:1556bcaaf759 311
DL3LD 1:1556bcaaf759 312 /* Initialize the erase command */
DL3LD 1:1556bcaaf759 313 s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE;
DL3LD 1:1556bcaaf759 314 s_command.Instruction = SUBSECTOR_ERASE_CMD;
DL3LD 1:1556bcaaf759 315 s_command.AddressMode = QSPI_ADDRESS_1_LINE;
DL3LD 1:1556bcaaf759 316 s_command.AddressSize = QSPI_ADDRESS_24_BITS;
DL3LD 1:1556bcaaf759 317 s_command.Address = BlockAddress;
DL3LD 1:1556bcaaf759 318 s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
DL3LD 1:1556bcaaf759 319 s_command.DataMode = QSPI_DATA_NONE;
DL3LD 1:1556bcaaf759 320 s_command.DummyCycles = 0;
DL3LD 1:1556bcaaf759 321 s_command.DdrMode = QSPI_DDR_MODE_DISABLE;
DL3LD 1:1556bcaaf759 322 s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
DL3LD 1:1556bcaaf759 323 s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
DL3LD 1:1556bcaaf759 324
DL3LD 1:1556bcaaf759 325 /* Enable write operations */
DL3LD 1:1556bcaaf759 326 if (QSPI_WriteEnable(&QSPIHandle) != QSPI_OK)
DL3LD 1:1556bcaaf759 327 {
DL3LD 1:1556bcaaf759 328 return QSPI_ERROR;
DL3LD 1:1556bcaaf759 329 }
DL3LD 1:1556bcaaf759 330
DL3LD 1:1556bcaaf759 331 /* Send the command */
DL3LD 1:1556bcaaf759 332 if (HAL_QSPI_Command(&QSPIHandle, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
DL3LD 1:1556bcaaf759 333 {
DL3LD 1:1556bcaaf759 334 return QSPI_ERROR;
DL3LD 1:1556bcaaf759 335 }
DL3LD 1:1556bcaaf759 336
DL3LD 1:1556bcaaf759 337 /* Configure automatic polling mode to wait for end of erase */
DL3LD 1:1556bcaaf759 338 if (QSPI_AutoPollingMemReady(&QSPIHandle, N25Q128A_SUBSECTOR_ERASE_MAX_TIME) != QSPI_OK)
DL3LD 1:1556bcaaf759 339 {
DL3LD 1:1556bcaaf759 340 return QSPI_ERROR;
DL3LD 1:1556bcaaf759 341 }
DL3LD 1:1556bcaaf759 342
DL3LD 1:1556bcaaf759 343 return QSPI_OK;
DL3LD 1:1556bcaaf759 344 }
DL3LD 1:1556bcaaf759 345
DL3LD 1:1556bcaaf759 346 /**
DL3LD 1:1556bcaaf759 347 * @brief Erases the entire QSPI memory.
DL3LD 1:1556bcaaf759 348 * @retval QSPI memory status
DL3LD 1:1556bcaaf759 349 */
DL3LD 1:1556bcaaf759 350 uint8_t BSP_QSPI_Erase_Chip(void)
DL3LD 1:1556bcaaf759 351 {
DL3LD 1:1556bcaaf759 352 QSPI_CommandTypeDef s_command;
DL3LD 1:1556bcaaf759 353
DL3LD 1:1556bcaaf759 354 /* Initialize the erase command */
DL3LD 1:1556bcaaf759 355 s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE;
DL3LD 1:1556bcaaf759 356 s_command.Instruction = BULK_ERASE_CMD;
DL3LD 1:1556bcaaf759 357 s_command.AddressMode = QSPI_ADDRESS_NONE;
DL3LD 1:1556bcaaf759 358 s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
DL3LD 1:1556bcaaf759 359 s_command.DataMode = QSPI_DATA_NONE;
DL3LD 1:1556bcaaf759 360 s_command.DummyCycles = 0;
DL3LD 1:1556bcaaf759 361 s_command.DdrMode = QSPI_DDR_MODE_DISABLE;
DL3LD 1:1556bcaaf759 362 s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
DL3LD 1:1556bcaaf759 363 s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
DL3LD 1:1556bcaaf759 364
DL3LD 1:1556bcaaf759 365 /* Enable write operations */
DL3LD 1:1556bcaaf759 366 if (QSPI_WriteEnable(&QSPIHandle) != QSPI_OK)
DL3LD 1:1556bcaaf759 367 {
DL3LD 1:1556bcaaf759 368 return QSPI_ERROR;
DL3LD 1:1556bcaaf759 369 }
DL3LD 1:1556bcaaf759 370
DL3LD 1:1556bcaaf759 371 /* Send the command */
DL3LD 1:1556bcaaf759 372 if (HAL_QSPI_Command(&QSPIHandle, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
DL3LD 1:1556bcaaf759 373 {
DL3LD 1:1556bcaaf759 374 return QSPI_ERROR;
DL3LD 1:1556bcaaf759 375 }
DL3LD 1:1556bcaaf759 376
DL3LD 1:1556bcaaf759 377 /* Configure automatic polling mode to wait for end of erase */
DL3LD 1:1556bcaaf759 378 if (QSPI_AutoPollingMemReady(&QSPIHandle, N25Q128A_BULK_ERASE_MAX_TIME) != QSPI_OK)
DL3LD 1:1556bcaaf759 379 {
DL3LD 1:1556bcaaf759 380 return QSPI_ERROR;
DL3LD 1:1556bcaaf759 381 }
DL3LD 1:1556bcaaf759 382
DL3LD 1:1556bcaaf759 383 return QSPI_OK;
DL3LD 1:1556bcaaf759 384 }
DL3LD 1:1556bcaaf759 385
DL3LD 1:1556bcaaf759 386 /**
DL3LD 1:1556bcaaf759 387 * @brief Reads current status of the QSPI memory.
DL3LD 1:1556bcaaf759 388 * @retval QSPI memory status
DL3LD 1:1556bcaaf759 389 */
DL3LD 1:1556bcaaf759 390 uint8_t BSP_QSPI_GetStatus(void)
DL3LD 1:1556bcaaf759 391 {
DL3LD 1:1556bcaaf759 392 QSPI_CommandTypeDef s_command;
DL3LD 1:1556bcaaf759 393 uint8_t reg;
DL3LD 1:1556bcaaf759 394
DL3LD 1:1556bcaaf759 395 /* Initialize the read flag status register command */
DL3LD 1:1556bcaaf759 396 s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE;
DL3LD 1:1556bcaaf759 397 s_command.Instruction = READ_FLAG_STATUS_REG_CMD;
DL3LD 1:1556bcaaf759 398 s_command.AddressMode = QSPI_ADDRESS_NONE;
DL3LD 1:1556bcaaf759 399 s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
DL3LD 1:1556bcaaf759 400 s_command.DataMode = QSPI_DATA_1_LINE;
DL3LD 1:1556bcaaf759 401 s_command.DummyCycles = 0;
DL3LD 1:1556bcaaf759 402 s_command.NbData = 1;
DL3LD 1:1556bcaaf759 403 s_command.DdrMode = QSPI_DDR_MODE_DISABLE;
DL3LD 1:1556bcaaf759 404 s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
DL3LD 1:1556bcaaf759 405 s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
DL3LD 1:1556bcaaf759 406
DL3LD 1:1556bcaaf759 407 /* Configure the command */
DL3LD 1:1556bcaaf759 408 if (HAL_QSPI_Command(&QSPIHandle, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
DL3LD 1:1556bcaaf759 409 {
DL3LD 1:1556bcaaf759 410 return QSPI_ERROR;
DL3LD 1:1556bcaaf759 411 }
DL3LD 1:1556bcaaf759 412
DL3LD 1:1556bcaaf759 413 /* Reception of the data */
DL3LD 1:1556bcaaf759 414 if (HAL_QSPI_Receive(&QSPIHandle, &reg, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
DL3LD 1:1556bcaaf759 415 {
DL3LD 1:1556bcaaf759 416 return QSPI_ERROR;
DL3LD 1:1556bcaaf759 417 }
DL3LD 1:1556bcaaf759 418
DL3LD 1:1556bcaaf759 419 /* Check the value of the register */
DL3LD 1:1556bcaaf759 420 if ((reg & (N25Q128A_FSR_PRERR | N25Q128A_FSR_VPPERR | N25Q128A_FSR_PGERR | N25Q128A_FSR_ERERR)) != 0)
DL3LD 1:1556bcaaf759 421 {
DL3LD 1:1556bcaaf759 422 return QSPI_ERROR;
DL3LD 1:1556bcaaf759 423 }
DL3LD 1:1556bcaaf759 424 else if ((reg & (N25Q128A_FSR_PGSUS | N25Q128A_FSR_ERSUS)) != 0)
DL3LD 1:1556bcaaf759 425 {
DL3LD 1:1556bcaaf759 426 return QSPI_SUSPENDED;
DL3LD 1:1556bcaaf759 427 }
DL3LD 1:1556bcaaf759 428 else if ((reg & N25Q128A_FSR_READY) != 0)
DL3LD 1:1556bcaaf759 429 {
DL3LD 1:1556bcaaf759 430 return QSPI_OK;
DL3LD 1:1556bcaaf759 431 }
DL3LD 1:1556bcaaf759 432 else
DL3LD 1:1556bcaaf759 433 {
DL3LD 1:1556bcaaf759 434 return QSPI_BUSY;
DL3LD 1:1556bcaaf759 435 }
DL3LD 1:1556bcaaf759 436 }
DL3LD 1:1556bcaaf759 437
DL3LD 1:1556bcaaf759 438 /**
DL3LD 1:1556bcaaf759 439 * @brief Return the configuration of the QSPI memory.
DL3LD 1:1556bcaaf759 440 * @param pInfo: pointer on the configuration structure
DL3LD 1:1556bcaaf759 441 * @retval QSPI memory status
DL3LD 1:1556bcaaf759 442 */
DL3LD 1:1556bcaaf759 443 uint8_t BSP_QSPI_GetInfo(QSPI_Info* pInfo)
DL3LD 1:1556bcaaf759 444 {
DL3LD 1:1556bcaaf759 445 /* Configure the structure with the memory configuration */
DL3LD 1:1556bcaaf759 446 pInfo->FlashSize = N25Q128A_FLASH_SIZE;
DL3LD 1:1556bcaaf759 447 pInfo->EraseSectorSize = N25Q128A_SUBSECTOR_SIZE;
DL3LD 1:1556bcaaf759 448 pInfo->EraseSectorsNumber = (N25Q128A_FLASH_SIZE/N25Q128A_SUBSECTOR_SIZE);
DL3LD 1:1556bcaaf759 449 pInfo->ProgPageSize = N25Q128A_PAGE_SIZE;
DL3LD 1:1556bcaaf759 450 pInfo->ProgPagesNumber = (N25Q128A_FLASH_SIZE/N25Q128A_PAGE_SIZE);
DL3LD 1:1556bcaaf759 451
DL3LD 1:1556bcaaf759 452 return QSPI_OK;
DL3LD 1:1556bcaaf759 453 }
DL3LD 1:1556bcaaf759 454
DL3LD 1:1556bcaaf759 455 /**
DL3LD 1:1556bcaaf759 456 * @brief Configure the QSPI in memory-mapped mode
DL3LD 1:1556bcaaf759 457 * @retval QSPI memory status
DL3LD 1:1556bcaaf759 458 */
DL3LD 1:1556bcaaf759 459 uint8_t BSP_QSPI_MemoryMappedMode(void)
DL3LD 1:1556bcaaf759 460 {
DL3LD 1:1556bcaaf759 461 QSPI_CommandTypeDef s_command;
DL3LD 1:1556bcaaf759 462 QSPI_MemoryMappedTypeDef s_mem_mapped_cfg;
DL3LD 1:1556bcaaf759 463
DL3LD 1:1556bcaaf759 464 /* Configure the command for the read instruction */
DL3LD 1:1556bcaaf759 465 s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE;
DL3LD 1:1556bcaaf759 466 s_command.Instruction = QUAD_INOUT_FAST_READ_CMD;
DL3LD 1:1556bcaaf759 467 s_command.AddressMode = QSPI_ADDRESS_4_LINES;
DL3LD 1:1556bcaaf759 468 s_command.AddressSize = QSPI_ADDRESS_24_BITS;
DL3LD 1:1556bcaaf759 469 s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
DL3LD 1:1556bcaaf759 470 s_command.DataMode = QSPI_DATA_4_LINES;
DL3LD 1:1556bcaaf759 471 s_command.DummyCycles = N25Q128A_DUMMY_CYCLES_READ_QUAD;
DL3LD 1:1556bcaaf759 472 s_command.DdrMode = QSPI_DDR_MODE_DISABLE;
DL3LD 1:1556bcaaf759 473 s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
DL3LD 1:1556bcaaf759 474 s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
DL3LD 1:1556bcaaf759 475
DL3LD 1:1556bcaaf759 476 /* Configure the memory mapped mode */
DL3LD 1:1556bcaaf759 477 s_mem_mapped_cfg.TimeOutActivation = QSPI_TIMEOUT_COUNTER_ENABLE;
DL3LD 1:1556bcaaf759 478 s_mem_mapped_cfg.TimeOutPeriod = 1;
DL3LD 1:1556bcaaf759 479
DL3LD 1:1556bcaaf759 480 if (HAL_QSPI_MemoryMapped(&QSPIHandle, &s_command, &s_mem_mapped_cfg) != HAL_OK)
DL3LD 1:1556bcaaf759 481 {
DL3LD 1:1556bcaaf759 482 return QSPI_ERROR;
DL3LD 1:1556bcaaf759 483 }
DL3LD 1:1556bcaaf759 484
DL3LD 1:1556bcaaf759 485 return QSPI_OK;
DL3LD 1:1556bcaaf759 486 }
DL3LD 1:1556bcaaf759 487
DL3LD 1:1556bcaaf759 488 /**
DL3LD 1:1556bcaaf759 489 * @}
DL3LD 1:1556bcaaf759 490 */
DL3LD 1:1556bcaaf759 491
DL3LD 1:1556bcaaf759 492 /** @addtogroup STM32746G_DISCOVERY_QSPI_Private_Functions
DL3LD 1:1556bcaaf759 493 * @{
DL3LD 1:1556bcaaf759 494 */
DL3LD 1:1556bcaaf759 495
DL3LD 1:1556bcaaf759 496 /**
DL3LD 1:1556bcaaf759 497 * @brief QSPI MSP Initialization
DL3LD 1:1556bcaaf759 498 * This function configures the hardware resources used in this example:
DL3LD 1:1556bcaaf759 499 * - Peripheral's clock enable
DL3LD 1:1556bcaaf759 500 * - Peripheral's GPIO Configuration
DL3LD 1:1556bcaaf759 501 * - NVIC configuration for QSPI interrupt
DL3LD 1:1556bcaaf759 502 * @retval None
DL3LD 1:1556bcaaf759 503 */
DL3LD 1:1556bcaaf759 504 __weak void BSP_QSPI_MspInit(QSPI_HandleTypeDef *hqspi, void *Params)
DL3LD 1:1556bcaaf759 505 {
DL3LD 1:1556bcaaf759 506 GPIO_InitTypeDef gpio_init_structure;
DL3LD 1:1556bcaaf759 507
DL3LD 1:1556bcaaf759 508 /*##-1- Enable peripherals and GPIO Clocks #################################*/
DL3LD 1:1556bcaaf759 509 /* Enable the QuadSPI memory interface clock */
DL3LD 1:1556bcaaf759 510 QSPI_CLK_ENABLE();
DL3LD 1:1556bcaaf759 511 /* Reset the QuadSPI memory interface */
DL3LD 1:1556bcaaf759 512 QSPI_FORCE_RESET();
DL3LD 1:1556bcaaf759 513 QSPI_RELEASE_RESET();
DL3LD 1:1556bcaaf759 514 /* Enable GPIO clocks */
DL3LD 1:1556bcaaf759 515 QSPI_CS_GPIO_CLK_ENABLE();
DL3LD 1:1556bcaaf759 516 QSPI_CLK_GPIO_CLK_ENABLE();
DL3LD 1:1556bcaaf759 517 QSPI_D0_GPIO_CLK_ENABLE();
DL3LD 1:1556bcaaf759 518 QSPI_D1_GPIO_CLK_ENABLE();
DL3LD 1:1556bcaaf759 519 QSPI_D2_GPIO_CLK_ENABLE();
DL3LD 1:1556bcaaf759 520 QSPI_D3_GPIO_CLK_ENABLE();
DL3LD 1:1556bcaaf759 521
DL3LD 1:1556bcaaf759 522 /*##-2- Configure peripheral GPIO ##########################################*/
DL3LD 1:1556bcaaf759 523 /* QSPI CS GPIO pin configuration */
DL3LD 1:1556bcaaf759 524 gpio_init_structure.Pin = QSPI_CS_PIN;
DL3LD 1:1556bcaaf759 525 gpio_init_structure.Mode = GPIO_MODE_AF_PP;
DL3LD 1:1556bcaaf759 526 gpio_init_structure.Pull = GPIO_PULLUP;
DL3LD 1:1556bcaaf759 527 gpio_init_structure.Speed = GPIO_SPEED_HIGH;
DL3LD 1:1556bcaaf759 528 gpio_init_structure.Alternate = GPIO_AF10_QUADSPI;
DL3LD 1:1556bcaaf759 529 HAL_GPIO_Init(QSPI_CS_GPIO_PORT, &gpio_init_structure);
DL3LD 1:1556bcaaf759 530
DL3LD 1:1556bcaaf759 531 /* QSPI CLK GPIO pin configuration */
DL3LD 1:1556bcaaf759 532 gpio_init_structure.Pin = QSPI_CLK_PIN;
DL3LD 1:1556bcaaf759 533 gpio_init_structure.Pull = GPIO_NOPULL;
DL3LD 1:1556bcaaf759 534 gpio_init_structure.Alternate = GPIO_AF9_QUADSPI;
DL3LD 1:1556bcaaf759 535 HAL_GPIO_Init(QSPI_CLK_GPIO_PORT, &gpio_init_structure);
DL3LD 1:1556bcaaf759 536
DL3LD 1:1556bcaaf759 537 /* QSPI D0 GPIO pin configuration */
DL3LD 1:1556bcaaf759 538 gpio_init_structure.Pin = QSPI_D0_PIN;
DL3LD 1:1556bcaaf759 539 gpio_init_structure.Alternate = GPIO_AF9_QUADSPI;
DL3LD 1:1556bcaaf759 540 HAL_GPIO_Init(QSPI_D0_GPIO_PORT, &gpio_init_structure);
DL3LD 1:1556bcaaf759 541
DL3LD 1:1556bcaaf759 542 /* QSPI D1 GPIO pin configuration */
DL3LD 1:1556bcaaf759 543 gpio_init_structure.Pin = QSPI_D1_PIN;
DL3LD 1:1556bcaaf759 544 gpio_init_structure.Alternate = GPIO_AF9_QUADSPI;
DL3LD 1:1556bcaaf759 545 HAL_GPIO_Init(QSPI_D1_GPIO_PORT, &gpio_init_structure);
DL3LD 1:1556bcaaf759 546
DL3LD 1:1556bcaaf759 547 /* QSPI D2 GPIO pin configuration */
DL3LD 1:1556bcaaf759 548 gpio_init_structure.Pin = QSPI_D2_PIN;
DL3LD 1:1556bcaaf759 549 gpio_init_structure.Alternate = GPIO_AF9_QUADSPI;
DL3LD 1:1556bcaaf759 550 HAL_GPIO_Init(QSPI_D2_GPIO_PORT, &gpio_init_structure);
DL3LD 1:1556bcaaf759 551
DL3LD 1:1556bcaaf759 552 /* QSPI D3 GPIO pin configuration */
DL3LD 1:1556bcaaf759 553 gpio_init_structure.Pin = QSPI_D3_PIN;
DL3LD 1:1556bcaaf759 554 gpio_init_structure.Alternate = GPIO_AF9_QUADSPI;
DL3LD 1:1556bcaaf759 555 HAL_GPIO_Init(QSPI_D3_GPIO_PORT, &gpio_init_structure);
DL3LD 1:1556bcaaf759 556
DL3LD 1:1556bcaaf759 557 /*##-3- Configure the NVIC for QSPI #########################################*/
DL3LD 1:1556bcaaf759 558 /* NVIC configuration for QSPI interrupt */
DL3LD 1:1556bcaaf759 559 HAL_NVIC_SetPriority(QUADSPI_IRQn, 0x0F, 0);
DL3LD 1:1556bcaaf759 560 HAL_NVIC_EnableIRQ(QUADSPI_IRQn);
DL3LD 1:1556bcaaf759 561 }
DL3LD 1:1556bcaaf759 562
DL3LD 1:1556bcaaf759 563 /**
DL3LD 1:1556bcaaf759 564 * @brief QSPI MSP De-Initialization
DL3LD 1:1556bcaaf759 565 * This function frees the hardware resources used in this example:
DL3LD 1:1556bcaaf759 566 * - Disable the Peripheral's clock
DL3LD 1:1556bcaaf759 567 * - Revert GPIO and NVIC configuration to their default state
DL3LD 1:1556bcaaf759 568 * @retval None
DL3LD 1:1556bcaaf759 569 */
DL3LD 1:1556bcaaf759 570 __weak void BSP_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi, void *Params)
DL3LD 1:1556bcaaf759 571 {
DL3LD 1:1556bcaaf759 572 /*##-1- Disable the NVIC for QSPI ###########################################*/
DL3LD 1:1556bcaaf759 573 HAL_NVIC_DisableIRQ(QUADSPI_IRQn);
DL3LD 1:1556bcaaf759 574
DL3LD 1:1556bcaaf759 575 /*##-2- Disable peripherals and GPIO Clocks ################################*/
DL3LD 1:1556bcaaf759 576 /* De-Configure QSPI pins */
DL3LD 1:1556bcaaf759 577 HAL_GPIO_DeInit(QSPI_CS_GPIO_PORT, QSPI_CS_PIN);
DL3LD 1:1556bcaaf759 578 HAL_GPIO_DeInit(QSPI_CLK_GPIO_PORT, QSPI_CLK_PIN);
DL3LD 1:1556bcaaf759 579 HAL_GPIO_DeInit(QSPI_D0_GPIO_PORT, QSPI_D0_PIN);
DL3LD 1:1556bcaaf759 580 HAL_GPIO_DeInit(QSPI_D1_GPIO_PORT, QSPI_D1_PIN);
DL3LD 1:1556bcaaf759 581 HAL_GPIO_DeInit(QSPI_D2_GPIO_PORT, QSPI_D2_PIN);
DL3LD 1:1556bcaaf759 582 HAL_GPIO_DeInit(QSPI_D3_GPIO_PORT, QSPI_D3_PIN);
DL3LD 1:1556bcaaf759 583
DL3LD 1:1556bcaaf759 584 /*##-3- Reset peripherals ##################################################*/
DL3LD 1:1556bcaaf759 585 /* Reset the QuadSPI memory interface */
DL3LD 1:1556bcaaf759 586 QSPI_FORCE_RESET();
DL3LD 1:1556bcaaf759 587 QSPI_RELEASE_RESET();
DL3LD 1:1556bcaaf759 588
DL3LD 1:1556bcaaf759 589 /* Disable the QuadSPI memory interface clock */
DL3LD 1:1556bcaaf759 590 QSPI_CLK_DISABLE();
DL3LD 1:1556bcaaf759 591 }
DL3LD 1:1556bcaaf759 592
DL3LD 1:1556bcaaf759 593 /**
DL3LD 1:1556bcaaf759 594 * @brief This function reset the QSPI memory.
DL3LD 1:1556bcaaf759 595 * @param hqspi: QSPI handle
DL3LD 1:1556bcaaf759 596 * @retval None
DL3LD 1:1556bcaaf759 597 */
DL3LD 1:1556bcaaf759 598 static uint8_t QSPI_ResetMemory(QSPI_HandleTypeDef *hqspi)
DL3LD 1:1556bcaaf759 599 {
DL3LD 1:1556bcaaf759 600 QSPI_CommandTypeDef s_command;
DL3LD 1:1556bcaaf759 601
DL3LD 1:1556bcaaf759 602 /* Initialize the reset enable command */
DL3LD 1:1556bcaaf759 603 s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE;
DL3LD 1:1556bcaaf759 604 s_command.Instruction = RESET_ENABLE_CMD;
DL3LD 1:1556bcaaf759 605 s_command.AddressMode = QSPI_ADDRESS_NONE;
DL3LD 1:1556bcaaf759 606 s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
DL3LD 1:1556bcaaf759 607 s_command.DataMode = QSPI_DATA_NONE;
DL3LD 1:1556bcaaf759 608 s_command.DummyCycles = 0;
DL3LD 1:1556bcaaf759 609 s_command.DdrMode = QSPI_DDR_MODE_DISABLE;
DL3LD 1:1556bcaaf759 610 s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
DL3LD 1:1556bcaaf759 611 s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
DL3LD 1:1556bcaaf759 612
DL3LD 1:1556bcaaf759 613 /* Send the command */
DL3LD 1:1556bcaaf759 614 if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
DL3LD 1:1556bcaaf759 615 {
DL3LD 1:1556bcaaf759 616 return QSPI_ERROR;
DL3LD 1:1556bcaaf759 617 }
DL3LD 1:1556bcaaf759 618
DL3LD 1:1556bcaaf759 619 /* Send the reset memory command */
DL3LD 1:1556bcaaf759 620 s_command.Instruction = RESET_MEMORY_CMD;
DL3LD 1:1556bcaaf759 621 if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
DL3LD 1:1556bcaaf759 622 {
DL3LD 1:1556bcaaf759 623 return QSPI_ERROR;
DL3LD 1:1556bcaaf759 624 }
DL3LD 1:1556bcaaf759 625
DL3LD 1:1556bcaaf759 626 /* Configure automatic polling mode to wait the memory is ready */
DL3LD 1:1556bcaaf759 627 if (QSPI_AutoPollingMemReady(hqspi, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != QSPI_OK)
DL3LD 1:1556bcaaf759 628 {
DL3LD 1:1556bcaaf759 629 return QSPI_ERROR;
DL3LD 1:1556bcaaf759 630 }
DL3LD 1:1556bcaaf759 631
DL3LD 1:1556bcaaf759 632 return QSPI_OK;
DL3LD 1:1556bcaaf759 633 }
DL3LD 1:1556bcaaf759 634
DL3LD 1:1556bcaaf759 635 /**
DL3LD 1:1556bcaaf759 636 * @brief This function configure the dummy cycles on memory side.
DL3LD 1:1556bcaaf759 637 * @param hqspi: QSPI handle
DL3LD 1:1556bcaaf759 638 * @retval None
DL3LD 1:1556bcaaf759 639 */
DL3LD 1:1556bcaaf759 640 static uint8_t QSPI_DummyCyclesCfg(QSPI_HandleTypeDef *hqspi)
DL3LD 1:1556bcaaf759 641 {
DL3LD 1:1556bcaaf759 642 QSPI_CommandTypeDef s_command;
DL3LD 1:1556bcaaf759 643 uint8_t reg;
DL3LD 1:1556bcaaf759 644
DL3LD 1:1556bcaaf759 645 /* Initialize the read volatile configuration register command */
DL3LD 1:1556bcaaf759 646 s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE;
DL3LD 1:1556bcaaf759 647 s_command.Instruction = READ_VOL_CFG_REG_CMD;
DL3LD 1:1556bcaaf759 648 s_command.AddressMode = QSPI_ADDRESS_NONE;
DL3LD 1:1556bcaaf759 649 s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
DL3LD 1:1556bcaaf759 650 s_command.DataMode = QSPI_DATA_1_LINE;
DL3LD 1:1556bcaaf759 651 s_command.DummyCycles = 0;
DL3LD 1:1556bcaaf759 652 s_command.NbData = 1;
DL3LD 1:1556bcaaf759 653 s_command.DdrMode = QSPI_DDR_MODE_DISABLE;
DL3LD 1:1556bcaaf759 654 s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
DL3LD 1:1556bcaaf759 655 s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
DL3LD 1:1556bcaaf759 656
DL3LD 1:1556bcaaf759 657 /* Configure the command */
DL3LD 1:1556bcaaf759 658 if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
DL3LD 1:1556bcaaf759 659 {
DL3LD 1:1556bcaaf759 660 return QSPI_ERROR;
DL3LD 1:1556bcaaf759 661 }
DL3LD 1:1556bcaaf759 662
DL3LD 1:1556bcaaf759 663 /* Reception of the data */
DL3LD 1:1556bcaaf759 664 if (HAL_QSPI_Receive(hqspi, &reg, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
DL3LD 1:1556bcaaf759 665 {
DL3LD 1:1556bcaaf759 666 return QSPI_ERROR;
DL3LD 1:1556bcaaf759 667 }
DL3LD 1:1556bcaaf759 668
DL3LD 1:1556bcaaf759 669 /* Enable write operations */
DL3LD 1:1556bcaaf759 670 if (QSPI_WriteEnable(hqspi) != QSPI_OK)
DL3LD 1:1556bcaaf759 671 {
DL3LD 1:1556bcaaf759 672 return QSPI_ERROR;
DL3LD 1:1556bcaaf759 673 }
DL3LD 1:1556bcaaf759 674
DL3LD 1:1556bcaaf759 675 /* Update volatile configuration register (with new dummy cycles) */
DL3LD 1:1556bcaaf759 676 s_command.Instruction = WRITE_VOL_CFG_REG_CMD;
DL3LD 1:1556bcaaf759 677 MODIFY_REG(reg, N25Q128A_VCR_NB_DUMMY, (N25Q128A_DUMMY_CYCLES_READ_QUAD << POSITION_VAL(N25Q128A_VCR_NB_DUMMY)));
DL3LD 1:1556bcaaf759 678
DL3LD 1:1556bcaaf759 679 /* Configure the write volatile configuration register command */
DL3LD 1:1556bcaaf759 680 if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
DL3LD 1:1556bcaaf759 681 {
DL3LD 1:1556bcaaf759 682 return QSPI_ERROR;
DL3LD 1:1556bcaaf759 683 }
DL3LD 1:1556bcaaf759 684
DL3LD 1:1556bcaaf759 685 /* Transmission of the data */
DL3LD 1:1556bcaaf759 686 if (HAL_QSPI_Transmit(hqspi, &reg, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
DL3LD 1:1556bcaaf759 687 {
DL3LD 1:1556bcaaf759 688 return QSPI_ERROR;
DL3LD 1:1556bcaaf759 689 }
DL3LD 1:1556bcaaf759 690
DL3LD 1:1556bcaaf759 691 return QSPI_OK;
DL3LD 1:1556bcaaf759 692 }
DL3LD 1:1556bcaaf759 693
DL3LD 1:1556bcaaf759 694 /**
DL3LD 1:1556bcaaf759 695 * @brief This function send a Write Enable and wait it is effective.
DL3LD 1:1556bcaaf759 696 * @param hqspi: QSPI handle
DL3LD 1:1556bcaaf759 697 * @retval None
DL3LD 1:1556bcaaf759 698 */
DL3LD 1:1556bcaaf759 699 static uint8_t QSPI_WriteEnable(QSPI_HandleTypeDef *hqspi)
DL3LD 1:1556bcaaf759 700 {
DL3LD 1:1556bcaaf759 701 QSPI_CommandTypeDef s_command;
DL3LD 1:1556bcaaf759 702 QSPI_AutoPollingTypeDef s_config;
DL3LD 1:1556bcaaf759 703
DL3LD 1:1556bcaaf759 704 /* Enable write operations */
DL3LD 1:1556bcaaf759 705 s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE;
DL3LD 1:1556bcaaf759 706 s_command.Instruction = WRITE_ENABLE_CMD;
DL3LD 1:1556bcaaf759 707 s_command.AddressMode = QSPI_ADDRESS_NONE;
DL3LD 1:1556bcaaf759 708 s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
DL3LD 1:1556bcaaf759 709 s_command.DataMode = QSPI_DATA_NONE;
DL3LD 1:1556bcaaf759 710 s_command.DummyCycles = 0;
DL3LD 1:1556bcaaf759 711 s_command.DdrMode = QSPI_DDR_MODE_DISABLE;
DL3LD 1:1556bcaaf759 712 s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
DL3LD 1:1556bcaaf759 713 s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
DL3LD 1:1556bcaaf759 714
DL3LD 1:1556bcaaf759 715 if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
DL3LD 1:1556bcaaf759 716 {
DL3LD 1:1556bcaaf759 717 return QSPI_ERROR;
DL3LD 1:1556bcaaf759 718 }
DL3LD 1:1556bcaaf759 719
DL3LD 1:1556bcaaf759 720 /* Configure automatic polling mode to wait for write enabling */
DL3LD 1:1556bcaaf759 721 s_config.Match = N25Q128A_SR_WREN;
DL3LD 1:1556bcaaf759 722 s_config.Mask = N25Q128A_SR_WREN;
DL3LD 1:1556bcaaf759 723 s_config.MatchMode = QSPI_MATCH_MODE_AND;
DL3LD 1:1556bcaaf759 724 s_config.StatusBytesSize = 1;
DL3LD 1:1556bcaaf759 725 s_config.Interval = 0x10;
DL3LD 1:1556bcaaf759 726 s_config.AutomaticStop = QSPI_AUTOMATIC_STOP_ENABLE;
DL3LD 1:1556bcaaf759 727
DL3LD 1:1556bcaaf759 728 s_command.Instruction = READ_STATUS_REG_CMD;
DL3LD 1:1556bcaaf759 729 s_command.DataMode = QSPI_DATA_1_LINE;
DL3LD 1:1556bcaaf759 730
DL3LD 1:1556bcaaf759 731 if (HAL_QSPI_AutoPolling(hqspi, &s_command, &s_config, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
DL3LD 1:1556bcaaf759 732 {
DL3LD 1:1556bcaaf759 733 return QSPI_ERROR;
DL3LD 1:1556bcaaf759 734 }
DL3LD 1:1556bcaaf759 735
DL3LD 1:1556bcaaf759 736 return QSPI_OK;
DL3LD 1:1556bcaaf759 737 }
DL3LD 1:1556bcaaf759 738
DL3LD 1:1556bcaaf759 739 /**
DL3LD 1:1556bcaaf759 740 * @brief This function read the SR of the memory and wait the EOP.
DL3LD 1:1556bcaaf759 741 * @param hqspi: QSPI handle
DL3LD 1:1556bcaaf759 742 * @param Timeout
DL3LD 1:1556bcaaf759 743 * @retval None
DL3LD 1:1556bcaaf759 744 */
DL3LD 1:1556bcaaf759 745 static uint8_t QSPI_AutoPollingMemReady(QSPI_HandleTypeDef *hqspi, uint32_t Timeout)
DL3LD 1:1556bcaaf759 746 {
DL3LD 1:1556bcaaf759 747 QSPI_CommandTypeDef s_command;
DL3LD 1:1556bcaaf759 748 QSPI_AutoPollingTypeDef s_config;
DL3LD 1:1556bcaaf759 749
DL3LD 1:1556bcaaf759 750 /* Configure automatic polling mode to wait for memory ready */
DL3LD 1:1556bcaaf759 751 s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE;
DL3LD 1:1556bcaaf759 752 s_command.Instruction = READ_STATUS_REG_CMD;
DL3LD 1:1556bcaaf759 753 s_command.AddressMode = QSPI_ADDRESS_NONE;
DL3LD 1:1556bcaaf759 754 s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
DL3LD 1:1556bcaaf759 755 s_command.DataMode = QSPI_DATA_1_LINE;
DL3LD 1:1556bcaaf759 756 s_command.DummyCycles = 0;
DL3LD 1:1556bcaaf759 757 s_command.DdrMode = QSPI_DDR_MODE_DISABLE;
DL3LD 1:1556bcaaf759 758 s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
DL3LD 1:1556bcaaf759 759 s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
DL3LD 1:1556bcaaf759 760
DL3LD 1:1556bcaaf759 761 s_config.Match = 0;
DL3LD 1:1556bcaaf759 762 s_config.Mask = N25Q128A_SR_WIP;
DL3LD 1:1556bcaaf759 763 s_config.MatchMode = QSPI_MATCH_MODE_AND;
DL3LD 1:1556bcaaf759 764 s_config.StatusBytesSize = 1;
DL3LD 1:1556bcaaf759 765 s_config.Interval = 0x10;
DL3LD 1:1556bcaaf759 766 s_config.AutomaticStop = QSPI_AUTOMATIC_STOP_ENABLE;
DL3LD 1:1556bcaaf759 767
DL3LD 1:1556bcaaf759 768 if (HAL_QSPI_AutoPolling(hqspi, &s_command, &s_config, Timeout) != HAL_OK)
DL3LD 1:1556bcaaf759 769 {
DL3LD 1:1556bcaaf759 770 return QSPI_ERROR;
DL3LD 1:1556bcaaf759 771 }
DL3LD 1:1556bcaaf759 772
DL3LD 1:1556bcaaf759 773 return QSPI_OK;
DL3LD 1:1556bcaaf759 774 }
DL3LD 1:1556bcaaf759 775 /**
DL3LD 1:1556bcaaf759 776 * @}
DL3LD 1:1556bcaaf759 777 */
DL3LD 1:1556bcaaf759 778
DL3LD 1:1556bcaaf759 779 /**
DL3LD 1:1556bcaaf759 780 * @}
DL3LD 1:1556bcaaf759 781 */
DL3LD 1:1556bcaaf759 782
DL3LD 1:1556bcaaf759 783 /**
DL3LD 1:1556bcaaf759 784 * @}
DL3LD 1:1556bcaaf759 785 */
DL3LD 1:1556bcaaf759 786
DL3LD 1:1556bcaaf759 787 /**
DL3LD 1:1556bcaaf759 788 * @}
DL3LD 1:1556bcaaf759 789 */
DL3LD 1:1556bcaaf759 790
DL3LD 1:1556bcaaf759 791 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
DL3LD 1:1556bcaaf759 792
DL3LD 1:1556bcaaf759 793