Viktor Zhezher / Mbed 2 deprecated SI570_VFO_F746NG

Library to control Silicon Labs SI570 10 MHZ TO 1.4 GHZ I2C PROGRAMMABLE XO/VCXO.

Dependencies:   mbed

Fork of SI570 by Gerrit Polder

BSP_F746NG/stm32746g_discovery_sdram.h@1:1556bcaaf759, 2016-03-27 (annotated)

Committer:
DL3LD
Date:
Sun Mar 27 06:55:59 2016 +0000
Revision:
1:1556bcaaf759
STM32F746NG SI570 VFO Test

Who changed what in which revision?

UserRevisionLine numberNew contents of line
DL3LD 1:1556bcaaf759 1 /**
DL3LD 1:1556bcaaf759 2 ******************************************************************************
DL3LD 1:1556bcaaf759 3 * @file stm32746g_discovery_sdram.h
DL3LD 1:1556bcaaf759 4 * @author MCD Application Team
DL3LD 1:1556bcaaf759 5 * @version V1.0.0
DL3LD 1:1556bcaaf759 6 * @date 25-June-2015
DL3LD 1:1556bcaaf759 7 * @brief This file contains the common defines and functions prototypes for
DL3LD 1:1556bcaaf759 8 * the stm32746g_discovery_sdram.c driver.
DL3LD 1:1556bcaaf759 9 ******************************************************************************
DL3LD 1:1556bcaaf759 10 * @attention
DL3LD 1:1556bcaaf759 11 *
DL3LD 1:1556bcaaf759 12 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
DL3LD 1:1556bcaaf759 13 *
DL3LD 1:1556bcaaf759 14 * Redistribution and use in source and binary forms, with or without modification,
DL3LD 1:1556bcaaf759 15 * are permitted provided that the following conditions are met:
DL3LD 1:1556bcaaf759 16 * 1. Redistributions of source code must retain the above copyright notice,
DL3LD 1:1556bcaaf759 17 * this list of conditions and the following disclaimer.
DL3LD 1:1556bcaaf759 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
DL3LD 1:1556bcaaf759 19 * this list of conditions and the following disclaimer in the documentation
DL3LD 1:1556bcaaf759 20 * and/or other materials provided with the distribution.
DL3LD 1:1556bcaaf759 21 * 3. Neither the name of STMicroelectronics nor the names of its contributors
DL3LD 1:1556bcaaf759 22 * may be used to endorse or promote products derived from this software
DL3LD 1:1556bcaaf759 23 * without specific prior written permission.
DL3LD 1:1556bcaaf759 24 *
DL3LD 1:1556bcaaf759 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
DL3LD 1:1556bcaaf759 26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
DL3LD 1:1556bcaaf759 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DL3LD 1:1556bcaaf759 28 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
DL3LD 1:1556bcaaf759 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DL3LD 1:1556bcaaf759 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
DL3LD 1:1556bcaaf759 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
DL3LD 1:1556bcaaf759 32 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
DL3LD 1:1556bcaaf759 33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
DL3LD 1:1556bcaaf759 34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
DL3LD 1:1556bcaaf759 35 *
DL3LD 1:1556bcaaf759 36 ******************************************************************************
DL3LD 1:1556bcaaf759 37 */
DL3LD 1:1556bcaaf759 38
DL3LD 1:1556bcaaf759 39 /* Define to prevent recursive inclusion -------------------------------------*/
DL3LD 1:1556bcaaf759 40 #ifndef __STM32746G_DISCOVERY_SDRAM_H
DL3LD 1:1556bcaaf759 41 #define __STM32746G_DISCOVERY_SDRAM_H
DL3LD 1:1556bcaaf759 42
DL3LD 1:1556bcaaf759 43 #ifdef __cplusplus
DL3LD 1:1556bcaaf759 44 extern "C" {
DL3LD 1:1556bcaaf759 45 #endif
DL3LD 1:1556bcaaf759 46
DL3LD 1:1556bcaaf759 47 /* Includes ------------------------------------------------------------------*/
DL3LD 1:1556bcaaf759 48 #include "stm32f7xx_hal.h"
DL3LD 1:1556bcaaf759 49
DL3LD 1:1556bcaaf759 50 /** @addtogroup BSP
DL3LD 1:1556bcaaf759 51 * @{
DL3LD 1:1556bcaaf759 52 */
DL3LD 1:1556bcaaf759 53
DL3LD 1:1556bcaaf759 54 /** @addtogroup STM32746G_DISCOVERY
DL3LD 1:1556bcaaf759 55 * @{
DL3LD 1:1556bcaaf759 56 */
DL3LD 1:1556bcaaf759 57
DL3LD 1:1556bcaaf759 58 /** @addtogroup STM32746G_DISCOVERY_SDRAM
DL3LD 1:1556bcaaf759 59 * @{
DL3LD 1:1556bcaaf759 60 */
DL3LD 1:1556bcaaf759 61
DL3LD 1:1556bcaaf759 62 /** @defgroup STM32746G_DISCOVERY_SDRAM_Exported_Types STM32746G_DISCOVERY_SDRAM Exported Types
DL3LD 1:1556bcaaf759 63 * @{
DL3LD 1:1556bcaaf759 64 */
DL3LD 1:1556bcaaf759 65
DL3LD 1:1556bcaaf759 66 /**
DL3LD 1:1556bcaaf759 67 * @brief SDRAM status structure definition
DL3LD 1:1556bcaaf759 68 */
DL3LD 1:1556bcaaf759 69 #define SDRAM_OK ((uint8_t)0x00)
DL3LD 1:1556bcaaf759 70 #define SDRAM_ERROR ((uint8_t)0x01)
DL3LD 1:1556bcaaf759 71
DL3LD 1:1556bcaaf759 72 /** @defgroup STM32746G_DISCOVERY_SDRAM_Exported_Constants STM32746G_DISCOVERY_SDRAM Exported Constants
DL3LD 1:1556bcaaf759 73 * @{
DL3LD 1:1556bcaaf759 74 */
DL3LD 1:1556bcaaf759 75 #define SDRAM_DEVICE_ADDR ((uint32_t)0xC0000000)
DL3LD 1:1556bcaaf759 76 #define SDRAM_DEVICE_SIZE ((uint32_t)0x800000) /* SDRAM device size in MBytes */
DL3LD 1:1556bcaaf759 77
DL3LD 1:1556bcaaf759 78 /* #define SDRAM_MEMORY_WIDTH FMC_SDRAM_MEM_BUS_WIDTH_8 */
DL3LD 1:1556bcaaf759 79 #define SDRAM_MEMORY_WIDTH FMC_SDRAM_MEM_BUS_WIDTH_16
DL3LD 1:1556bcaaf759 80
DL3LD 1:1556bcaaf759 81 #define SDCLOCK_PERIOD FMC_SDRAM_CLOCK_PERIOD_2
DL3LD 1:1556bcaaf759 82 /* #define SDCLOCK_PERIOD FMC_SDRAM_CLOCK_PERIOD_3 */
DL3LD 1:1556bcaaf759 83
DL3LD 1:1556bcaaf759 84 #define REFRESH_COUNT ((uint32_t)0x0603) /* SDRAM refresh counter (100Mhz SD clock) */
DL3LD 1:1556bcaaf759 85
DL3LD 1:1556bcaaf759 86 #define SDRAM_TIMEOUT ((uint32_t)0xFFFF)
DL3LD 1:1556bcaaf759 87
DL3LD 1:1556bcaaf759 88 /* DMA definitions for SDRAM DMA transfer */
DL3LD 1:1556bcaaf759 89 #define __DMAx_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
DL3LD 1:1556bcaaf759 90 #define __DMAx_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
DL3LD 1:1556bcaaf759 91 #define SDRAM_DMAx_CHANNEL DMA_CHANNEL_0
DL3LD 1:1556bcaaf759 92 #define SDRAM_DMAx_STREAM DMA2_Stream0
DL3LD 1:1556bcaaf759 93 #define SDRAM_DMAx_IRQn DMA2_Stream0_IRQn
DL3LD 1:1556bcaaf759 94 #define SDRAM_DMAx_IRQHandler DMA2_Stream0_IRQHandler
DL3LD 1:1556bcaaf759 95 /**
DL3LD 1:1556bcaaf759 96 * @}
DL3LD 1:1556bcaaf759 97 */
DL3LD 1:1556bcaaf759 98
DL3LD 1:1556bcaaf759 99 /**
DL3LD 1:1556bcaaf759 100 * @brief FMC SDRAM Mode definition register defines
DL3LD 1:1556bcaaf759 101 */
DL3LD 1:1556bcaaf759 102 #define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000)
DL3LD 1:1556bcaaf759 103 #define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001)
DL3LD 1:1556bcaaf759 104 #define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002)
DL3LD 1:1556bcaaf759 105 #define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0004)
DL3LD 1:1556bcaaf759 106 #define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000)
DL3LD 1:1556bcaaf759 107 #define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008)
DL3LD 1:1556bcaaf759 108 #define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020)
DL3LD 1:1556bcaaf759 109 #define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030)
DL3LD 1:1556bcaaf759 110 #define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000)
DL3LD 1:1556bcaaf759 111 #define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
DL3LD 1:1556bcaaf759 112 #define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200)
DL3LD 1:1556bcaaf759 113 /**
DL3LD 1:1556bcaaf759 114 * @}
DL3LD 1:1556bcaaf759 115 */
DL3LD 1:1556bcaaf759 116
DL3LD 1:1556bcaaf759 117 /** @defgroup STM32746G_DISCOVERY_SDRAM_Exported_Macro STM32746G_DISCOVERY_SDRAM Exported Macro
DL3LD 1:1556bcaaf759 118 * @{
DL3LD 1:1556bcaaf759 119 */
DL3LD 1:1556bcaaf759 120 /**
DL3LD 1:1556bcaaf759 121 * @}
DL3LD 1:1556bcaaf759 122 */
DL3LD 1:1556bcaaf759 123
DL3LD 1:1556bcaaf759 124 /** @addtogroup STM32746G_DISCOVERY_SDRAM_Exported_Functions
DL3LD 1:1556bcaaf759 125 * @{
DL3LD 1:1556bcaaf759 126 */
DL3LD 1:1556bcaaf759 127 uint8_t BSP_SDRAM_Init(void);
DL3LD 1:1556bcaaf759 128 uint8_t BSP_SDRAM_DeInit(void);
DL3LD 1:1556bcaaf759 129 void BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount);
DL3LD 1:1556bcaaf759 130 uint8_t BSP_SDRAM_ReadData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize);
DL3LD 1:1556bcaaf759 131 uint8_t BSP_SDRAM_ReadData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize);
DL3LD 1:1556bcaaf759 132 uint8_t BSP_SDRAM_WriteData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize);
DL3LD 1:1556bcaaf759 133 uint8_t BSP_SDRAM_WriteData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize);
DL3LD 1:1556bcaaf759 134 uint8_t BSP_SDRAM_Sendcmd(FMC_SDRAM_CommandTypeDef *SdramCmd);
DL3LD 1:1556bcaaf759 135 void BSP_SDRAM_DMA_IRQHandler(void);
DL3LD 1:1556bcaaf759 136
DL3LD 1:1556bcaaf759 137 /* These functions can be modified in case the current settings (e.g. DMA stream)
DL3LD 1:1556bcaaf759 138 need to be changed for specific application needs */
DL3LD 1:1556bcaaf759 139 void BSP_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram, void *Params);
DL3LD 1:1556bcaaf759 140 void BSP_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram, void *Params);
DL3LD 1:1556bcaaf759 141
DL3LD 1:1556bcaaf759 142
DL3LD 1:1556bcaaf759 143 /**
DL3LD 1:1556bcaaf759 144 * @}
DL3LD 1:1556bcaaf759 145 */
DL3LD 1:1556bcaaf759 146
DL3LD 1:1556bcaaf759 147 /**
DL3LD 1:1556bcaaf759 148 * @}
DL3LD 1:1556bcaaf759 149 */
DL3LD 1:1556bcaaf759 150
DL3LD 1:1556bcaaf759 151 /**
DL3LD 1:1556bcaaf759 152 * @}
DL3LD 1:1556bcaaf759 153 */
DL3LD 1:1556bcaaf759 154
DL3LD 1:1556bcaaf759 155 /**
DL3LD 1:1556bcaaf759 156 * @}
DL3LD 1:1556bcaaf759 157 */
DL3LD 1:1556bcaaf759 158
DL3LD 1:1556bcaaf759 159 #ifdef __cplusplus
DL3LD 1:1556bcaaf759 160 }
DL3LD 1:1556bcaaf759 161 #endif
DL3LD 1:1556bcaaf759 162
DL3LD 1:1556bcaaf759 163 #endif /* __STM32746G_DISCOVERY_SDRAM_H */
DL3LD 1:1556bcaaf759 164
DL3LD 1:1556bcaaf759 165 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
DL3LD 1:1556bcaaf759 166