Library to control Silicon Labs SI570 10 MHZ TO 1.4 GHZ I2C PROGRAMMABLE XO/VCXO.

Dependencies:   mbed

Fork of SI570 by Gerrit Polder

Committer:
DL3LD
Date:
Sun Mar 27 06:55:59 2016 +0000
Revision:
1:1556bcaaf759
STM32F746NG SI570 VFO Test

Who changed what in which revision?

UserRevisionLine numberNew contents of line
DL3LD 1:1556bcaaf759 1 /**
DL3LD 1:1556bcaaf759 2 ******************************************************************************
DL3LD 1:1556bcaaf759 3 * @file stm32746g_discovery_qspi.h
DL3LD 1:1556bcaaf759 4 * @author MCD Application Team
DL3LD 1:1556bcaaf759 5 * @version V1.0.0
DL3LD 1:1556bcaaf759 6 * @date 25-June-2015
DL3LD 1:1556bcaaf759 7 * @brief This file contains the common defines and functions prototypes for
DL3LD 1:1556bcaaf759 8 * the stm32746g_discovery_qspi.c driver.
DL3LD 1:1556bcaaf759 9 ******************************************************************************
DL3LD 1:1556bcaaf759 10 * @attention
DL3LD 1:1556bcaaf759 11 *
DL3LD 1:1556bcaaf759 12 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
DL3LD 1:1556bcaaf759 13 *
DL3LD 1:1556bcaaf759 14 * Redistribution and use in source and binary forms, with or without modification,
DL3LD 1:1556bcaaf759 15 * are permitted provided that the following conditions are met:
DL3LD 1:1556bcaaf759 16 * 1. Redistributions of source code must retain the above copyright notice,
DL3LD 1:1556bcaaf759 17 * this list of conditions and the following disclaimer.
DL3LD 1:1556bcaaf759 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
DL3LD 1:1556bcaaf759 19 * this list of conditions and the following disclaimer in the documentation
DL3LD 1:1556bcaaf759 20 * and/or other materials provided with the distribution.
DL3LD 1:1556bcaaf759 21 * 3. Neither the name of STMicroelectronics nor the names of its contributors
DL3LD 1:1556bcaaf759 22 * may be used to endorse or promote products derived from this software
DL3LD 1:1556bcaaf759 23 * without specific prior written permission.
DL3LD 1:1556bcaaf759 24 *
DL3LD 1:1556bcaaf759 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
DL3LD 1:1556bcaaf759 26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
DL3LD 1:1556bcaaf759 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DL3LD 1:1556bcaaf759 28 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
DL3LD 1:1556bcaaf759 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DL3LD 1:1556bcaaf759 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
DL3LD 1:1556bcaaf759 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
DL3LD 1:1556bcaaf759 32 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
DL3LD 1:1556bcaaf759 33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
DL3LD 1:1556bcaaf759 34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
DL3LD 1:1556bcaaf759 35 *
DL3LD 1:1556bcaaf759 36 ******************************************************************************
DL3LD 1:1556bcaaf759 37 */
DL3LD 1:1556bcaaf759 38
DL3LD 1:1556bcaaf759 39 /** @addtogroup BSP
DL3LD 1:1556bcaaf759 40 * @{
DL3LD 1:1556bcaaf759 41 */
DL3LD 1:1556bcaaf759 42
DL3LD 1:1556bcaaf759 43 /** @addtogroup STM32746G_DISCOVERY
DL3LD 1:1556bcaaf759 44 * @{
DL3LD 1:1556bcaaf759 45 */
DL3LD 1:1556bcaaf759 46
DL3LD 1:1556bcaaf759 47 /* Define to prevent recursive inclusion -------------------------------------*/
DL3LD 1:1556bcaaf759 48 #ifndef __STM32746G_DISCOVERY_QSPI_H
DL3LD 1:1556bcaaf759 49 #define __STM32746G_DISCOVERY_QSPI_H
DL3LD 1:1556bcaaf759 50
DL3LD 1:1556bcaaf759 51 #ifdef __cplusplus
DL3LD 1:1556bcaaf759 52 extern "C" {
DL3LD 1:1556bcaaf759 53 #endif
DL3LD 1:1556bcaaf759 54
DL3LD 1:1556bcaaf759 55 /* Includes ------------------------------------------------------------------*/
DL3LD 1:1556bcaaf759 56 #include "stm32f7xx_hal.h"
DL3LD 1:1556bcaaf759 57 #include "n25q128a.h"
DL3LD 1:1556bcaaf759 58
DL3LD 1:1556bcaaf759 59 /** @addtogroup STM32746G_DISCOVERY_QSPI
DL3LD 1:1556bcaaf759 60 * @{
DL3LD 1:1556bcaaf759 61 */
DL3LD 1:1556bcaaf759 62
DL3LD 1:1556bcaaf759 63
DL3LD 1:1556bcaaf759 64 /* Exported constants --------------------------------------------------------*/
DL3LD 1:1556bcaaf759 65 /** @defgroup STM32746G_DISCOVERY_QSPI_Exported_Constants STM32746G_DISCOVERY_QSPI Exported Constants
DL3LD 1:1556bcaaf759 66 * @{
DL3LD 1:1556bcaaf759 67 */
DL3LD 1:1556bcaaf759 68 /* QSPI Error codes */
DL3LD 1:1556bcaaf759 69 #define QSPI_OK ((uint8_t)0x00)
DL3LD 1:1556bcaaf759 70 #define QSPI_ERROR ((uint8_t)0x01)
DL3LD 1:1556bcaaf759 71 #define QSPI_BUSY ((uint8_t)0x02)
DL3LD 1:1556bcaaf759 72 #define QSPI_NOT_SUPPORTED ((uint8_t)0x04)
DL3LD 1:1556bcaaf759 73 #define QSPI_SUSPENDED ((uint8_t)0x08)
DL3LD 1:1556bcaaf759 74
DL3LD 1:1556bcaaf759 75
DL3LD 1:1556bcaaf759 76 /* Definition for QSPI clock resources */
DL3LD 1:1556bcaaf759 77 #define QSPI_CLK_ENABLE() __HAL_RCC_QSPI_CLK_ENABLE()
DL3LD 1:1556bcaaf759 78 #define QSPI_CLK_DISABLE() __HAL_RCC_QSPI_CLK_DISABLE()
DL3LD 1:1556bcaaf759 79 #define QSPI_CS_GPIO_CLK_ENABLE() __HAL_RCC_GPIOB_CLK_ENABLE()
DL3LD 1:1556bcaaf759 80 #define QSPI_CLK_GPIO_CLK_ENABLE() __HAL_RCC_GPIOB_CLK_ENABLE()
DL3LD 1:1556bcaaf759 81 #define QSPI_D0_GPIO_CLK_ENABLE() __HAL_RCC_GPIOD_CLK_ENABLE()
DL3LD 1:1556bcaaf759 82 #define QSPI_D1_GPIO_CLK_ENABLE() __HAL_RCC_GPIOD_CLK_ENABLE()
DL3LD 1:1556bcaaf759 83 #define QSPI_D2_GPIO_CLK_ENABLE() __HAL_RCC_GPIOE_CLK_ENABLE()
DL3LD 1:1556bcaaf759 84 #define QSPI_D3_GPIO_CLK_ENABLE() __HAL_RCC_GPIOD_CLK_ENABLE()
DL3LD 1:1556bcaaf759 85
DL3LD 1:1556bcaaf759 86 #define QSPI_FORCE_RESET() __HAL_RCC_QSPI_FORCE_RESET()
DL3LD 1:1556bcaaf759 87 #define QSPI_RELEASE_RESET() __HAL_RCC_QSPI_RELEASE_RESET()
DL3LD 1:1556bcaaf759 88
DL3LD 1:1556bcaaf759 89 /* Definition for QSPI Pins */
DL3LD 1:1556bcaaf759 90 #define QSPI_CS_PIN GPIO_PIN_6
DL3LD 1:1556bcaaf759 91 #define QSPI_CS_GPIO_PORT GPIOB
DL3LD 1:1556bcaaf759 92 #define QSPI_CLK_PIN GPIO_PIN_2
DL3LD 1:1556bcaaf759 93 #define QSPI_CLK_GPIO_PORT GPIOB
DL3LD 1:1556bcaaf759 94 #define QSPI_D0_PIN GPIO_PIN_11
DL3LD 1:1556bcaaf759 95 #define QSPI_D0_GPIO_PORT GPIOD
DL3LD 1:1556bcaaf759 96 #define QSPI_D1_PIN GPIO_PIN_12
DL3LD 1:1556bcaaf759 97 #define QSPI_D1_GPIO_PORT GPIOD
DL3LD 1:1556bcaaf759 98 #define QSPI_D2_PIN GPIO_PIN_2
DL3LD 1:1556bcaaf759 99 #define QSPI_D2_GPIO_PORT GPIOE
DL3LD 1:1556bcaaf759 100 #define QSPI_D3_PIN GPIO_PIN_13
DL3LD 1:1556bcaaf759 101 #define QSPI_D3_GPIO_PORT GPIOD
DL3LD 1:1556bcaaf759 102
DL3LD 1:1556bcaaf759 103 /* N25Q128A13EF840E Micron memory */
DL3LD 1:1556bcaaf759 104 /* Size of the flash */
DL3LD 1:1556bcaaf759 105 #define QSPI_FLASH_SIZE 23 /* Address bus width to access whole memory space */
DL3LD 1:1556bcaaf759 106 #define QSPI_PAGE_SIZE 256
DL3LD 1:1556bcaaf759 107
DL3LD 1:1556bcaaf759 108 /**
DL3LD 1:1556bcaaf759 109 * @}
DL3LD 1:1556bcaaf759 110 */
DL3LD 1:1556bcaaf759 111
DL3LD 1:1556bcaaf759 112 /* Exported types ------------------------------------------------------------*/
DL3LD 1:1556bcaaf759 113 /** @defgroup STM32746G_DISCOVERY_QSPI_Exported_Types STM32746G_DISCOVERY_QSPI Exported Types
DL3LD 1:1556bcaaf759 114 * @{
DL3LD 1:1556bcaaf759 115 */
DL3LD 1:1556bcaaf759 116 /* QSPI Info */
DL3LD 1:1556bcaaf759 117 typedef struct {
DL3LD 1:1556bcaaf759 118 uint32_t FlashSize; /*!< Size of the flash */
DL3LD 1:1556bcaaf759 119 uint32_t EraseSectorSize; /*!< Size of sectors for the erase operation */
DL3LD 1:1556bcaaf759 120 uint32_t EraseSectorsNumber; /*!< Number of sectors for the erase operation */
DL3LD 1:1556bcaaf759 121 uint32_t ProgPageSize; /*!< Size of pages for the program operation */
DL3LD 1:1556bcaaf759 122 uint32_t ProgPagesNumber; /*!< Number of pages for the program operation */
DL3LD 1:1556bcaaf759 123 } QSPI_Info;
DL3LD 1:1556bcaaf759 124
DL3LD 1:1556bcaaf759 125 /**
DL3LD 1:1556bcaaf759 126 * @}
DL3LD 1:1556bcaaf759 127 */
DL3LD 1:1556bcaaf759 128
DL3LD 1:1556bcaaf759 129
DL3LD 1:1556bcaaf759 130 /* Exported functions --------------------------------------------------------*/
DL3LD 1:1556bcaaf759 131 /** @addtogroup STM32746G_DISCOVERY_QSPI_Exported_Functions
DL3LD 1:1556bcaaf759 132 * @{
DL3LD 1:1556bcaaf759 133 */
DL3LD 1:1556bcaaf759 134 uint8_t BSP_QSPI_Init (void);
DL3LD 1:1556bcaaf759 135 uint8_t BSP_QSPI_DeInit (void);
DL3LD 1:1556bcaaf759 136 uint8_t BSP_QSPI_Read (uint8_t* pData, uint32_t ReadAddr, uint32_t Size);
DL3LD 1:1556bcaaf759 137 uint8_t BSP_QSPI_Write (uint8_t* pData, uint32_t WriteAddr, uint32_t Size);
DL3LD 1:1556bcaaf759 138 uint8_t BSP_QSPI_Erase_Block(uint32_t BlockAddress);
DL3LD 1:1556bcaaf759 139 uint8_t BSP_QSPI_Erase_Chip (void);
DL3LD 1:1556bcaaf759 140 uint8_t BSP_QSPI_GetStatus (void);
DL3LD 1:1556bcaaf759 141 uint8_t BSP_QSPI_GetInfo (QSPI_Info* pInfo);
DL3LD 1:1556bcaaf759 142 uint8_t BSP_QSPI_MemoryMappedMode(void);
DL3LD 1:1556bcaaf759 143
DL3LD 1:1556bcaaf759 144 /* These functions can be modified in case the current settings
DL3LD 1:1556bcaaf759 145 need to be changed for specific application needs */
DL3LD 1:1556bcaaf759 146 void BSP_QSPI_MspInit(QSPI_HandleTypeDef *hqspi, void *Params);
DL3LD 1:1556bcaaf759 147 void BSP_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi, void *Params);
DL3LD 1:1556bcaaf759 148
DL3LD 1:1556bcaaf759 149 /**
DL3LD 1:1556bcaaf759 150 * @}
DL3LD 1:1556bcaaf759 151 */
DL3LD 1:1556bcaaf759 152
DL3LD 1:1556bcaaf759 153 /**
DL3LD 1:1556bcaaf759 154 * @}
DL3LD 1:1556bcaaf759 155 */
DL3LD 1:1556bcaaf759 156
DL3LD 1:1556bcaaf759 157 #ifdef __cplusplus
DL3LD 1:1556bcaaf759 158 }
DL3LD 1:1556bcaaf759 159 #endif
DL3LD 1:1556bcaaf759 160
DL3LD 1:1556bcaaf759 161 #endif /* __STM32746G_DISCOVERY_QSPI_H */
DL3LD 1:1556bcaaf759 162 /**
DL3LD 1:1556bcaaf759 163 * @}
DL3LD 1:1556bcaaf759 164 */
DL3LD 1:1556bcaaf759 165
DL3LD 1:1556bcaaf759 166 /**
DL3LD 1:1556bcaaf759 167 * @}
DL3LD 1:1556bcaaf759 168 */
DL3LD 1:1556bcaaf759 169
DL3LD 1:1556bcaaf759 170 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
DL3LD 1:1556bcaaf759 171